drivers/scsi/cxlflash/common.h

   1 /*
   2  * CXL Flash Device Driver
   3  *
   4  * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
   5  *             Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
   6  *
   7  * Copyright (C) 2015 IBM Corporation
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14
  15 #ifndef _CXLFLASH_COMMON_H
  16 #define _CXLFLASH_COMMON_H
  17
  18 #include <linux/async.h>
  19 #include <linux/cdev.h>
  20 #include <linux/irq_poll.h>
  21 #include <linux/list.h>
  22 #include <linux/rwsem.h>
  23 #include <linux/types.h>
  24 #include <scsi/scsi.h>
  25 #include <scsi/scsi_cmnd.h>
  26 #include <scsi/scsi_device.h>
  27
  28 #include "backend.h"
  29
  30 extern const struct file_operations cxlflash_cxl_fops;
  31
  32 #define MAX_CONTEXT     CXLFLASH_MAX_CONTEXT    /* num contexts per afu */
  33 #define MAX_FC_PORTS    CXLFLASH_MAX_FC_PORTS   /* max ports per AFU */
  34 #define LEGACY_FC_PORTS 2                       /* legacy ports per AFU */
  35
  36 #define CHAN2PORTBANK(_x)       ((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK))
  37 #define CHAN2BANKPORT(_x)       ((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1))
  38
  39 #define CHAN2PORTMASK(_x)       (1 << (_x))     /* channel to port mask */
  40 #define PORTMASK2CHAN(_x)       (ilog2((_x)))   /* port mask to channel */
  41 #define PORTNUM2CHAN(_x)        ((_x) - 1)      /* port number to channel */
  42
  43 #define CXLFLASH_BLOCK_SIZE     4096            /* 4K blocks */
  44 #define CXLFLASH_MAX_XFER_SIZE  16777216        /* 16MB transfer */
  45 #define CXLFLASH_MAX_SECTORS    (CXLFLASH_MAX_XFER_SIZE/512)    /* SCSI wants
  46                                                                  * max_sectors
  47                                                                  * in units of
  48                                                                  * 512 byte
  49                                                                  * sectors
  50                                                                  */
  51
  52 #define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))
  53
  54 /* AFU command retry limit */
  55 #define MC_RETRY_CNT    5       /* Sufficient for SCSI and certain AFU errors */
  56
  57 /* Command management definitions */
  58 #define CXLFLASH_MAX_CMDS               256
  59 #define CXLFLASH_MAX_CMDS_PER_LUN       CXLFLASH_MAX_CMDS
  60
  61 /* RRQ for master issued cmds */
  62 #define NUM_RRQ_ENTRY                   CXLFLASH_MAX_CMDS
  63
  64 /* SQ for master issued cmds */
  65 #define NUM_SQ_ENTRY                    CXLFLASH_MAX_CMDS
  66
  67 /* Hardware queue definitions */
  68 #define CXLFLASH_DEF_HWQS               1
  69 #define CXLFLASH_MAX_HWQS               8
  70 #define PRIMARY_HWQ                     0
  71
  72
  73 static inline void check_sizes(void)
  74 {
  75         BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK);
  76         BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS);
  77 }
  78
  79 /* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
  80 #define CMD_BUFSIZE     SIZE_4K
  81
  82 enum cxlflash_lr_state {
  83         LINK_RESET_INVALID,
  84         LINK_RESET_REQUIRED,
  85         LINK_RESET_COMPLETE
  86 };
  87
  88 enum cxlflash_init_state {
  89         INIT_STATE_NONE,
  90         INIT_STATE_PCI,
  91         INIT_STATE_AFU,
  92         INIT_STATE_SCSI,
  93         INIT_STATE_CDEV
  94 };
  95
  96 enum cxlflash_state {
  97         STATE_PROBING,  /* Initial state during probe */
  98         STATE_PROBED,   /* Temporary state, probe completed but EEH occurred */
  99         STATE_NORMAL,   /* Normal running state, everything good */
 100         STATE_RESET,    /* Reset state, trying to reset/recover */
 101         STATE_FAILTERM  /* Failed/terminating state, error out users/threads */
 102 };
 103
 104 enum cxlflash_hwq_mode {
 105         HWQ_MODE_RR,    /* Roundrobin (default) */
 106         HWQ_MODE_TAG,   /* Distribute based on block MQ tag */
 107         HWQ_MODE_CPU,   /* CPU affinity */
 108         MAX_HWQ_MODE
 109 };
 110
 111 /*
 112  * Each context has its own set of resource handles that is visible
 113  * only from that context.
 114  */
 115
 116 struct cxlflash_cfg {
 117         struct afu *afu;
 118
 119         const struct cxlflash_backend_ops *ops;
 120         struct pci_dev *dev;
 121         struct pci_device_id *dev_id;
 122         struct Scsi_Host *host;
 123         int num_fc_ports;
 124         struct cdev cdev;
 125         struct device *chardev;
 126
 127         ulong cxlflash_regs_pci;
 128
 129         struct work_struct work_q;
 130         enum cxlflash_init_state init_state;
 131         enum cxlflash_lr_state lr_state;
 132         int lr_port;
 133         atomic_t scan_host_needed;
 134
 135         void *afu_cookie;
 136
 137         atomic_t recovery_threads;
 138         struct mutex ctx_recovery_mutex;
 139         struct mutex ctx_tbl_list_mutex;
 140         struct rw_semaphore ioctl_rwsem;
 141         struct ctx_info *ctx_tbl[MAX_CONTEXT];
 142         struct list_head ctx_err_recovery; /* contexts w/ recovery pending */
 143         struct file_operations cxl_fops;
 144
 145         /* Parameters that are LUN table related */
 146         int last_lun_index[MAX_FC_PORTS];
 147         int promote_lun_index;
 148         struct list_head lluns; /* list of llun_info structs */
 149
 150         wait_queue_head_t tmf_waitq;
 151         spinlock_t tmf_slock;
 152         bool tmf_active;
 153         bool ws_unmap;          /* Write-same unmap supported */
 154         wait_queue_head_t reset_waitq;
 155         enum cxlflash_state state;
 156         async_cookie_t async_reset_cookie;
 157 };
 158
 159 struct afu_cmd {
 160         struct sisl_ioarcb rcb; /* IOARCB (cache line aligned) */
 161         struct sisl_ioasa sa;   /* IOASA must follow IOARCB */
 162         struct afu *parent;
 163         struct scsi_cmnd *scp;
 164         struct completion cevent;
 165         struct list_head queue;
 166         u32 hwq_index;
 167
 168         u8 cmd_tmf:1,
 169            cmd_aborted:1;
 170
 171         struct list_head list;  /* Pending commands link */
 172
 173         /* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
 174          * However for performance reasons the IOARCB/IOASA should be
 175          * cache line aligned.
 176          */
 177 } __aligned(cache_line_size());
 178
 179 static inline struct afu_cmd *sc_to_afuc(struct scsi_cmnd *sc)
 180 {
 181         return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd));
 182 }
 183
 184 static inline struct afu_cmd *sc_to_afuci(struct scsi_cmnd *sc)
 185 {
 186         struct afu_cmd *afuc = sc_to_afuc(sc);
 187
 188         INIT_LIST_HEAD(&afuc->queue);
 189         return afuc;
 190 }
 191
 192 static inline struct afu_cmd *sc_to_afucz(struct scsi_cmnd *sc)
 193 {
 194         struct afu_cmd *afuc = sc_to_afuc(sc);
 195
 196         memset(afuc, 0, sizeof(*afuc));
 197         return sc_to_afuci(sc);
 198 }
 199
 200 struct hwq {
 201         /* Stuff requiring alignment go first. */
 202         struct sisl_ioarcb sq[NUM_SQ_ENTRY];            /* 16K SQ */
 203         u64 rrq_entry[NUM_RRQ_ENTRY];                   /* 2K RRQ */
 204
 205         /* Beware of alignment till here. Preferably introduce new
 206          * fields after this point
 207          */
 208         struct afu *afu;
 209         void *ctx_cookie;
 210         struct sisl_host_map __iomem *host_map;         /* MC host map */
 211         struct sisl_ctrl_map __iomem *ctrl_map;         /* MC control map */
 212         ctx_hndl_t ctx_hndl;    /* master's context handle */
 213         u32 index;              /* Index of this hwq */
 214         int num_irqs;           /* Numer of interrupts requested for context */
 215         struct list_head pending_cmds;  /* Commands pending completion */
 216
 217         atomic_t hsq_credits;
 218         spinlock_t hsq_slock;   /* Hardware send queue lock */
 219         struct sisl_ioarcb *hsq_start;
 220         struct sisl_ioarcb *hsq_end;
 221         struct sisl_ioarcb *hsq_curr;
 222         spinlock_t hrrq_slock;
 223         u64 *hrrq_start;
 224         u64 *hrrq_end;
 225         u64 *hrrq_curr;
 226         bool toggle;
 227
 228         s64 room;
 229
 230         struct irq_poll irqpoll;
 231 } __aligned(cache_line_size());
 232
 233 struct afu {
 234         struct hwq hwqs[CXLFLASH_MAX_HWQS];
 235         int (*send_cmd)(struct afu *afu, struct afu_cmd *cmd);
 236         int (*context_reset)(struct hwq *hwq);
 237
 238         /* AFU HW */
 239         struct cxlflash_afu_map __iomem *afu_map;       /* entire MMIO map */
 240
 241         atomic_t cmds_active;   /* Number of currently active AFU commands */
 242         u64 hb;
 243         u32 internal_lun;       /* User-desired LUN mode for this AFU */
 244
 245         u32 num_hwqs;           /* Number of hardware queues */
 246         u32 desired_hwqs;       /* Desired h/w queues, effective on AFU reset */
 247         enum cxlflash_hwq_mode hwq_mode; /* Steering mode for h/w queues */
 248         u32 hwq_rr_count;       /* Count to distribute traffic for roundrobin */
 249
 250         char version[16];
 251         u64 interface_version;
 252
 253         u32 irqpoll_weight;
 254         struct cxlflash_cfg *parent; /* Pointer back to parent cxlflash_cfg */
 255 };
 256
 257 static inline struct hwq *get_hwq(struct afu *afu, u32 index)
 258 {
 259         WARN_ON(index >= CXLFLASH_MAX_HWQS);
 260
 261         return &afu->hwqs[index];
 262 }
 263
 264 static inline bool afu_is_irqpoll_enabled(struct afu *afu)
 265 {
 266         return !!afu->irqpoll_weight;
 267 }
 268
 269 static inline bool afu_has_cap(struct afu *afu, u64 cap)
 270 {
 271         u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT;
 272
 273         return afu_cap & cap;
 274 }
 275
 276 static inline bool afu_is_afu_debug(struct afu *afu)
 277 {
 278         return afu_has_cap(afu, SISL_INTVER_CAP_AFU_DEBUG);
 279 }
 280
 281 static inline bool afu_is_lun_provision(struct afu *afu)
 282 {
 283         return afu_has_cap(afu, SISL_INTVER_CAP_LUN_PROVISION);
 284 }
 285
 286 static inline bool afu_is_sq_cmd_mode(struct afu *afu)
 287 {
 288         return afu_has_cap(afu, SISL_INTVER_CAP_SQ_CMD_MODE);
 289 }
 290
 291 static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu)
 292 {
 293         return afu_has_cap(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE);
 294 }
 295
 296 static inline u64 lun_to_lunid(u64 lun)
 297 {
 298         __be64 lun_id;
 299
 300         int_to_scsilun(lun, (struct scsi_lun *)&lun_id);
 301         return be64_to_cpu(lun_id);
 302 }
 303
 304 static inline struct fc_port_bank __iomem *get_fc_port_bank(
 305                                             struct cxlflash_cfg *cfg, int i)
 306 {
 307         struct afu *afu = cfg->afu;
 308
 309         return &afu->afu_map->global.bank[CHAN2PORTBANK(i)];
 310 }
 311
 312 static inline __be64 __iomem *get_fc_port_regs(struct cxlflash_cfg *cfg, int i)
 313 {
 314         struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
 315
 316         return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0];
 317 }
 318
 319 static inline __be64 __iomem *get_fc_port_luns(struct cxlflash_cfg *cfg, int i)
 320 {
 321         struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
 322
 323         return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0];
 324 }
 325
 326 int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode);
 327 void cxlflash_list_init(void);
 328 void cxlflash_term_global_luns(void);
 329 void cxlflash_free_errpage(void);
 330 int cxlflash_ioctl(struct scsi_device *sdev, int cmd, void __user *arg);
 331 void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg);
 332 int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg);
 333 void cxlflash_term_local_luns(struct cxlflash_cfg *cfg);
 334 void cxlflash_restore_luntable(struct cxlflash_cfg *cfg);
 335
 336 #endif /* ifndef _CXLFLASH_COMMON_H */