drivers/scsi/cxlflash/ocxl_hw.h

   1 /*
   2  * CXL Flash Device Driver
   3  *
   4  * Written by: Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
   5  *             Uma Krishnan <ukrishn@linux.vnet.ibm.com>, IBM Corporation
   6  *
   7  * Copyright (C) 2018 IBM Corporation
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14
  15 #define OCXL_MAX_IRQS   4       /* Max interrupts per process */
  16
  17 struct ocxlflash_irqs {
  18         int hwirq;
  19         u32 virq;
  20         u64 ptrig;
  21         void __iomem *vtrig;
  22 };
  23
  24 /* OCXL hardware AFU associated with the host */
  25 struct ocxl_hw_afu {
  26         struct ocxlflash_context *ocxl_ctx; /* Host context */
  27         struct pci_dev *pdev;           /* PCI device */
  28         struct device *dev;             /* Generic device */
  29         bool perst_same_image;          /* Same image loaded on perst */
  30
  31         struct ocxl_fn_config fcfg;     /* DVSEC config of the function */
  32         struct ocxl_afu_config acfg;    /* AFU configuration data */
  33
  34         int fn_actag_base;              /* Function acTag base */
  35         int fn_actag_enabled;           /* Function acTag number enabled */
  36         int afu_actag_base;             /* AFU acTag base */
  37         int afu_actag_enabled;          /* AFU acTag number enabled */
  38
  39         phys_addr_t ppmmio_phys;        /* Per process MMIO space */
  40         phys_addr_t gmmio_phys;         /* Global AFU MMIO space */
  41         void __iomem *gmmio_virt;       /* Global MMIO map */
  42
  43         void *link_token;               /* Link token for the SPA */
  44         struct idr idr;                 /* IDR to manage contexts */
  45         int max_pasid;                  /* Maximum number of contexts */
  46         bool is_present;                /* Function has AFUs defined */
  47 };
  48
  49 enum ocxlflash_ctx_state {
  50         CLOSED,
  51         OPENED,
  52         STARTED
  53 };
  54
  55 struct ocxlflash_context {
  56         struct ocxl_hw_afu *hw_afu;     /* HW AFU back pointer */
  57         struct address_space *mapping;  /* Mapping for pseudo filesystem */
  58         bool master;                    /* Whether this is a master context */
  59         int pe;                         /* Process element */
  60
  61         phys_addr_t psn_phys;           /* Process mapping */
  62         u64 psn_size;                   /* Process mapping size */
  63
  64         spinlock_t slock;               /* Protects irq/fault/event updates */
  65         wait_queue_head_t wq;           /* Wait queue for poll and interrupts */
  66         struct mutex state_mutex;       /* Mutex to update context state */
  67         enum ocxlflash_ctx_state state; /* Context state */
  68
  69         struct ocxlflash_irqs *irqs;    /* Pointer to array of structures */
  70         int num_irqs;                   /* Number of interrupts */
  71         bool pending_irq;               /* Pending interrupt on the context */
  72         ulong irq_bitmap;               /* Bits indicating pending irq num */
  73
  74         u64 fault_addr;                 /* Address that triggered the fault */
  75         u64 fault_dsisr;                /* Value of dsisr register at fault */
  76         bool pending_fault;             /* Pending translation fault */
  77 };