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[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v1_hw.c
1 /*
2 * Copyright (c) 2015 Linaro Ltd.
3 * Copyright (c) 2015 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12 #include "hisi_sas.h"
13 #define DRV_NAME "hisi_sas_v1_hw"
14
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define BROKEN_MSG_ADDR_LO 0x18
22 #define BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PHY_CONN_RATE 0x30
28 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
29 #define AXI_AHB_CLK_CFG 0x3c
30 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x84
31 #define HGC_GET_ITV_TIME 0x90
32 #define DEVICE_MSG_WORK_MODE 0x94
33 #define I_T_NEXUS_LOSS_TIME 0xa0
34 #define BUS_INACTIVE_LIMIT_TIME 0xa8
35 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
36 #define CFG_AGING_TIME 0xbc
37 #define CFG_AGING_TIME_ITCT_REL_OFF 0
38 #define CFG_AGING_TIME_ITCT_REL_MSK (0x1 << CFG_AGING_TIME_ITCT_REL_OFF)
39 #define HGC_DFX_CFG2 0xc0
40 #define FIS_LIST_BADDR_L 0xc4
41 #define CFG_1US_TIMER_TRSH 0xcc
42 #define CFG_SAS_CONFIG 0xd4
43 #define HGC_IOST_ECC_ADDR 0x140
44 #define HGC_IOST_ECC_ADDR_BAD_OFF 16
45 #define HGC_IOST_ECC_ADDR_BAD_MSK (0x3ff << HGC_IOST_ECC_ADDR_BAD_OFF)
46 #define HGC_DQ_ECC_ADDR 0x144
47 #define HGC_DQ_ECC_ADDR_BAD_OFF 16
48 #define HGC_DQ_ECC_ADDR_BAD_MSK (0xfff << HGC_DQ_ECC_ADDR_BAD_OFF)
49 #define HGC_INVLD_DQE_INFO 0x148
50 #define HGC_INVLD_DQE_INFO_DQ_OFF 0
51 #define HGC_INVLD_DQE_INFO_DQ_MSK (0xffff << HGC_INVLD_DQE_INFO_DQ_OFF)
52 #define HGC_INVLD_DQE_INFO_TYPE_OFF 16
53 #define HGC_INVLD_DQE_INFO_TYPE_MSK (0x1 << HGC_INVLD_DQE_INFO_TYPE_OFF)
54 #define HGC_INVLD_DQE_INFO_FORCE_OFF 17
55 #define HGC_INVLD_DQE_INFO_FORCE_MSK (0x1 << HGC_INVLD_DQE_INFO_FORCE_OFF)
56 #define HGC_INVLD_DQE_INFO_PHY_OFF 18
57 #define HGC_INVLD_DQE_INFO_PHY_MSK (0x1 << HGC_INVLD_DQE_INFO_PHY_OFF)
58 #define HGC_INVLD_DQE_INFO_ABORT_OFF 19
59 #define HGC_INVLD_DQE_INFO_ABORT_MSK (0x1 << HGC_INVLD_DQE_INFO_ABORT_OFF)
60 #define HGC_INVLD_DQE_INFO_IPTT_OF_OFF 20
61 #define HGC_INVLD_DQE_INFO_IPTT_OF_MSK (0x1 << HGC_INVLD_DQE_INFO_IPTT_OF_OFF)
62 #define HGC_INVLD_DQE_INFO_SSP_ERR_OFF 21
63 #define HGC_INVLD_DQE_INFO_SSP_ERR_MSK (0x1 << HGC_INVLD_DQE_INFO_SSP_ERR_OFF)
64 #define HGC_INVLD_DQE_INFO_OFL_OFF 22
65 #define HGC_INVLD_DQE_INFO_OFL_MSK (0x1 << HGC_INVLD_DQE_INFO_OFL_OFF)
66 #define HGC_ITCT_ECC_ADDR 0x150
67 #define HGC_ITCT_ECC_ADDR_BAD_OFF 16
68 #define HGC_ITCT_ECC_ADDR_BAD_MSK (0x3ff << HGC_ITCT_ECC_ADDR_BAD_OFF)
69 #define HGC_AXI_FIFO_ERR_INFO 0x154
70 #define INT_COAL_EN 0x1bc
71 #define OQ_INT_COAL_TIME 0x1c0
72 #define OQ_INT_COAL_CNT 0x1c4
73 #define ENT_INT_COAL_TIME 0x1c8
74 #define ENT_INT_COAL_CNT 0x1cc
75 #define OQ_INT_SRC 0x1d0
76 #define OQ_INT_SRC_MSK 0x1d4
77 #define ENT_INT_SRC1 0x1d8
78 #define ENT_INT_SRC2 0x1dc
79 #define ENT_INT_SRC2_DQ_CFG_ERR_OFF 25
80 #define ENT_INT_SRC2_DQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_DQ_CFG_ERR_OFF)
81 #define ENT_INT_SRC2_CQ_CFG_ERR_OFF 27
82 #define ENT_INT_SRC2_CQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_CQ_CFG_ERR_OFF)
83 #define ENT_INT_SRC2_AXI_WRONG_INT_OFF 28
84 #define ENT_INT_SRC2_AXI_WRONG_INT_MSK (0x1 << ENT_INT_SRC2_AXI_WRONG_INT_OFF)
85 #define ENT_INT_SRC2_AXI_OVERLF_INT_OFF 29
86 #define ENT_INT_SRC2_AXI_OVERLF_INT_MSK (0x1 << ENT_INT_SRC2_AXI_OVERLF_INT_OFF)
87 #define ENT_INT_SRC_MSK1 0x1e0
88 #define ENT_INT_SRC_MSK2 0x1e4
89 #define SAS_ECC_INTR 0x1e8
90 #define SAS_ECC_INTR_DQ_ECC1B_OFF 0
91 #define SAS_ECC_INTR_DQ_ECC1B_MSK (0x1 << SAS_ECC_INTR_DQ_ECC1B_OFF)
92 #define SAS_ECC_INTR_DQ_ECCBAD_OFF 1
93 #define SAS_ECC_INTR_DQ_ECCBAD_MSK (0x1 << SAS_ECC_INTR_DQ_ECCBAD_OFF)
94 #define SAS_ECC_INTR_IOST_ECC1B_OFF 2
95 #define SAS_ECC_INTR_IOST_ECC1B_MSK (0x1 << SAS_ECC_INTR_IOST_ECC1B_OFF)
96 #define SAS_ECC_INTR_IOST_ECCBAD_OFF 3
97 #define SAS_ECC_INTR_IOST_ECCBAD_MSK (0x1 << SAS_ECC_INTR_IOST_ECCBAD_OFF)
98 #define SAS_ECC_INTR_ITCT_ECC1B_OFF 4
99 #define SAS_ECC_INTR_ITCT_ECC1B_MSK (0x1 << SAS_ECC_INTR_ITCT_ECC1B_OFF)
100 #define SAS_ECC_INTR_ITCT_ECCBAD_OFF 5
101 #define SAS_ECC_INTR_ITCT_ECCBAD_MSK (0x1 << SAS_ECC_INTR_ITCT_ECCBAD_OFF)
102 #define SAS_ECC_INTR_MSK 0x1ec
103 #define HGC_ERR_STAT_EN 0x238
104 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
105 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
106 #define DLVRY_Q_0_DEPTH 0x268
107 #define DLVRY_Q_0_WR_PTR 0x26c
108 #define DLVRY_Q_0_RD_PTR 0x270
109 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
110 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
111 #define COMPL_Q_0_DEPTH 0x4e8
112 #define COMPL_Q_0_WR_PTR 0x4ec
113 #define COMPL_Q_0_RD_PTR 0x4f0
114 #define HGC_ECC_ERR 0x7d0
115
116 /* phy registers need init */
117 #define PORT_BASE (0x800)
118
119 #define PHY_CFG (PORT_BASE + 0x0)
120 #define PHY_CFG_ENA_OFF 0
121 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
122 #define PHY_CFG_DC_OPT_OFF 2
123 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
124 #define PROG_PHY_LINK_RATE (PORT_BASE + 0xc)
125 #define PROG_PHY_LINK_RATE_MAX_OFF 0
126 #define PROG_PHY_LINK_RATE_MAX_MSK (0xf << PROG_PHY_LINK_RATE_MAX_OFF)
127 #define PROG_PHY_LINK_RATE_MIN_OFF 4
128 #define PROG_PHY_LINK_RATE_MIN_MSK (0xf << PROG_PHY_LINK_RATE_MIN_OFF)
129 #define PROG_PHY_LINK_RATE_OOB_OFF 8
130 #define PROG_PHY_LINK_RATE_OOB_MSK (0xf << PROG_PHY_LINK_RATE_OOB_OFF)
131 #define PHY_CTRL (PORT_BASE + 0x14)
132 #define PHY_CTRL_RESET_OFF 0
133 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
134 #define PHY_RATE_NEGO (PORT_BASE + 0x30)
135 #define PHY_PCN (PORT_BASE + 0x44)
136 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
137 #define SL_CONTROL (PORT_BASE + 0x94)
138 #define SL_CONTROL_NOTIFY_EN_OFF 0
139 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
140 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
141 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
142 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
143 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
144 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
145 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
146 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
147 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
148 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
149 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
150 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
151 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
152 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
153 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
154 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
155 #define DONE_RECEIVED_TIME (PORT_BASE + 0x12c)
156 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
157 #define PHY_CONFIG2 (PORT_BASE + 0x1a8)
158 #define PHY_CONFIG2_FORCE_TXDEEMPH_OFF 3
159 #define PHY_CONFIG2_FORCE_TXDEEMPH_MSK (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF)
160 #define PHY_CONFIG2_TX_TRAIN_COMP_OFF 24
161 #define PHY_CONFIG2_TX_TRAIN_COMP_MSK (0x1 << PHY_CONFIG2_TX_TRAIN_COMP_OFF)
162 #define CHL_INT0 (PORT_BASE + 0x1b0)
163 #define CHL_INT0_PHYCTRL_NOTRDY_OFF 0
164 #define CHL_INT0_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_PHYCTRL_NOTRDY_OFF)
165 #define CHL_INT0_SN_FAIL_NGR_OFF 2
166 #define CHL_INT0_SN_FAIL_NGR_MSK (0x1 << CHL_INT0_SN_FAIL_NGR_OFF)
167 #define CHL_INT0_DWS_LOST_OFF 4
168 #define CHL_INT0_DWS_LOST_MSK (0x1 << CHL_INT0_DWS_LOST_OFF)
169 #define CHL_INT0_SL_IDAF_FAIL_OFF 10
170 #define CHL_INT0_SL_IDAF_FAIL_MSK (0x1 << CHL_INT0_SL_IDAF_FAIL_OFF)
171 #define CHL_INT0_ID_TIMEOUT_OFF 11
172 #define CHL_INT0_ID_TIMEOUT_MSK (0x1 << CHL_INT0_ID_TIMEOUT_OFF)
173 #define CHL_INT0_SL_OPAF_FAIL_OFF 12
174 #define CHL_INT0_SL_OPAF_FAIL_MSK (0x1 << CHL_INT0_SL_OPAF_FAIL_OFF)
175 #define CHL_INT0_SL_PS_FAIL_OFF 21
176 #define CHL_INT0_SL_PS_FAIL_MSK (0x1 << CHL_INT0_SL_PS_FAIL_OFF)
177 #define CHL_INT1 (PORT_BASE + 0x1b4)
178 #define CHL_INT2 (PORT_BASE + 0x1b8)
179 #define CHL_INT2_SL_RX_BC_ACK_OFF 2
180 #define CHL_INT2_SL_RX_BC_ACK_MSK (0x1 << CHL_INT2_SL_RX_BC_ACK_OFF)
181 #define CHL_INT2_SL_PHY_ENA_OFF 6
182 #define CHL_INT2_SL_PHY_ENA_MSK (0x1 << CHL_INT2_SL_PHY_ENA_OFF)
183 #define CHL_INT0_MSK (PORT_BASE + 0x1bc)
184 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF 0
185 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF)
186 #define CHL_INT1_MSK (PORT_BASE + 0x1c0)
187 #define CHL_INT2_MSK (PORT_BASE + 0x1c4)
188 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
189 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
190 #define DMA_TX_STATUS_BUSY_OFF 0
191 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
192 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
193 #define DMA_RX_STATUS_BUSY_OFF 0
194 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
195
196 #define AXI_CFG 0x5100
197 #define RESET_VALUE 0x7ffff
198
199 /* HW dma structures */
200 /* Delivery queue header */
201 /* dw0 */
202 #define CMD_HDR_RESP_REPORT_OFF 5
203 #define CMD_HDR_RESP_REPORT_MSK 0x20
204 #define CMD_HDR_TLR_CTRL_OFF 6
205 #define CMD_HDR_TLR_CTRL_MSK 0xc0
206 #define CMD_HDR_PORT_OFF 17
207 #define CMD_HDR_PORT_MSK 0xe0000
208 #define CMD_HDR_PRIORITY_OFF 27
209 #define CMD_HDR_PRIORITY_MSK 0x8000000
210 #define CMD_HDR_MODE_OFF 28
211 #define CMD_HDR_MODE_MSK 0x10000000
212 #define CMD_HDR_CMD_OFF 29
213 #define CMD_HDR_CMD_MSK 0xe0000000
214 /* dw1 */
215 #define CMD_HDR_VERIFY_DTL_OFF 10
216 #define CMD_HDR_VERIFY_DTL_MSK 0x400
217 #define CMD_HDR_SSP_FRAME_TYPE_OFF 13
218 #define CMD_HDR_SSP_FRAME_TYPE_MSK 0xe000
219 #define CMD_HDR_DEVICE_ID_OFF 16
220 #define CMD_HDR_DEVICE_ID_MSK 0xffff0000
221 /* dw2 */
222 #define CMD_HDR_CFL_OFF 0
223 #define CMD_HDR_CFL_MSK 0x1ff
224 #define CMD_HDR_MRFL_OFF 15
225 #define CMD_HDR_MRFL_MSK 0xff8000
226 #define CMD_HDR_FIRST_BURST_OFF 25
227 #define CMD_HDR_FIRST_BURST_MSK 0x2000000
228 /* dw3 */
229 #define CMD_HDR_IPTT_OFF 0
230 #define CMD_HDR_IPTT_MSK 0xffff
231 /* dw6 */
232 #define CMD_HDR_DATA_SGL_LEN_OFF 16
233 #define CMD_HDR_DATA_SGL_LEN_MSK 0xffff0000
234
235 /* Completion header */
236 #define CMPLT_HDR_IPTT_OFF 0
237 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
238 #define CMPLT_HDR_CMD_CMPLT_OFF 17
239 #define CMPLT_HDR_CMD_CMPLT_MSK (0x1 << CMPLT_HDR_CMD_CMPLT_OFF)
240 #define CMPLT_HDR_ERR_RCRD_XFRD_OFF 18
241 #define CMPLT_HDR_ERR_RCRD_XFRD_MSK (0x1 << CMPLT_HDR_ERR_RCRD_XFRD_OFF)
242 #define CMPLT_HDR_RSPNS_XFRD_OFF 19
243 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
244 #define CMPLT_HDR_IO_CFG_ERR_OFF 27
245 #define CMPLT_HDR_IO_CFG_ERR_MSK (0x1 << CMPLT_HDR_IO_CFG_ERR_OFF)
246
247 /* ITCT header */
248 /* qw0 */
249 #define ITCT_HDR_DEV_TYPE_OFF 0
250 #define ITCT_HDR_DEV_TYPE_MSK (0x3ULL << ITCT_HDR_DEV_TYPE_OFF)
251 #define ITCT_HDR_VALID_OFF 2
252 #define ITCT_HDR_VALID_MSK (0x1ULL << ITCT_HDR_VALID_OFF)
253 #define ITCT_HDR_AWT_CONTROL_OFF 4
254 #define ITCT_HDR_AWT_CONTROL_MSK (0x1ULL << ITCT_HDR_AWT_CONTROL_OFF)
255 #define ITCT_HDR_MAX_CONN_RATE_OFF 5
256 #define ITCT_HDR_MAX_CONN_RATE_MSK (0xfULL << ITCT_HDR_MAX_CONN_RATE_OFF)
257 #define ITCT_HDR_VALID_LINK_NUM_OFF 9
258 #define ITCT_HDR_VALID_LINK_NUM_MSK (0xfULL << ITCT_HDR_VALID_LINK_NUM_OFF)
259 #define ITCT_HDR_PORT_ID_OFF 13
260 #define ITCT_HDR_PORT_ID_MSK (0x7ULL << ITCT_HDR_PORT_ID_OFF)
261 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
262 #define ITCT_HDR_SMP_TIMEOUT_MSK (0xffffULL << ITCT_HDR_SMP_TIMEOUT_OFF)
263 /* qw1 */
264 #define ITCT_HDR_MAX_SAS_ADDR_OFF 0
265 #define ITCT_HDR_MAX_SAS_ADDR_MSK (0xffffffffffffffff << \
266 ITCT_HDR_MAX_SAS_ADDR_OFF)
267 /* qw2 */
268 #define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF 0
269 #define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK (0xffffULL << \
270 ITCT_HDR_IT_NEXUS_LOSS_TL_OFF)
271 #define ITCT_HDR_BUS_INACTIVE_TL_OFF 16
272 #define ITCT_HDR_BUS_INACTIVE_TL_MSK (0xffffULL << \
273 ITCT_HDR_BUS_INACTIVE_TL_OFF)
274 #define ITCT_HDR_MAX_CONN_TL_OFF 32
275 #define ITCT_HDR_MAX_CONN_TL_MSK (0xffffULL << \
276 ITCT_HDR_MAX_CONN_TL_OFF)
277 #define ITCT_HDR_REJ_OPEN_TL_OFF 48
278 #define ITCT_HDR_REJ_OPEN_TL_MSK (0xffffULL << \
279 ITCT_HDR_REJ_OPEN_TL_OFF)
280
281 /* Err record header */
282 #define ERR_HDR_DMA_TX_ERR_TYPE_OFF 0
283 #define ERR_HDR_DMA_TX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_TX_ERR_TYPE_OFF)
284 #define ERR_HDR_DMA_RX_ERR_TYPE_OFF 16
285 #define ERR_HDR_DMA_RX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_RX_ERR_TYPE_OFF)
286
287 struct hisi_sas_complete_v1_hdr {
288 __le32 data;
289 };
290
291 struct hisi_sas_err_record_v1 {
292 /* dw0 */
293 __le32 dma_err_type;
294
295 /* dw1 */
296 __le32 trans_tx_fail_type;
297
298 /* dw2 */
299 __le32 trans_rx_fail_type;
300
301 /* dw3 */
302 u32 rsvd;
303 };
304
305 enum {
306 HISI_SAS_PHY_BCAST_ACK = 0,
307 HISI_SAS_PHY_SL_PHY_ENABLED,
308 HISI_SAS_PHY_INT_ABNORMAL,
309 HISI_SAS_PHY_INT_NR
310 };
311
312 enum {
313 DMA_TX_ERR_BASE = 0x0,
314 DMA_RX_ERR_BASE = 0x100,
315 TRANS_TX_FAIL_BASE = 0x200,
316 TRANS_RX_FAIL_BASE = 0x300,
317
318 /* dma tx */
319 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x0 */
320 DMA_TX_DIF_APP_ERR, /* 0x1 */
321 DMA_TX_DIF_RPP_ERR, /* 0x2 */
322 DMA_TX_AXI_BUS_ERR, /* 0x3 */
323 DMA_TX_DATA_SGL_OVERFLOW_ERR, /* 0x4 */
324 DMA_TX_DIF_SGL_OVERFLOW_ERR, /* 0x5 */
325 DMA_TX_UNEXP_XFER_RDY_ERR, /* 0x6 */
326 DMA_TX_XFER_RDY_OFFSET_ERR, /* 0x7 */
327 DMA_TX_DATA_UNDERFLOW_ERR, /* 0x8 */
328 DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR, /* 0x9 */
329
330 /* dma rx */
331 DMA_RX_BUFFER_ECC_ERR = DMA_RX_ERR_BASE, /* 0x100 */
332 DMA_RX_DIF_CRC_ERR, /* 0x101 */
333 DMA_RX_DIF_APP_ERR, /* 0x102 */
334 DMA_RX_DIF_RPP_ERR, /* 0x103 */
335 DMA_RX_RESP_BUFFER_OVERFLOW_ERR, /* 0x104 */
336 DMA_RX_AXI_BUS_ERR, /* 0x105 */
337 DMA_RX_DATA_SGL_OVERFLOW_ERR, /* 0x106 */
338 DMA_RX_DIF_SGL_OVERFLOW_ERR, /* 0x107 */
339 DMA_RX_DATA_OFFSET_ERR, /* 0x108 */
340 DMA_RX_UNEXP_RX_DATA_ERR, /* 0x109 */
341 DMA_RX_DATA_OVERFLOW_ERR, /* 0x10a */
342 DMA_RX_DATA_UNDERFLOW_ERR, /* 0x10b */
343 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x10c */
344
345 /* trans tx */
346 TRANS_TX_RSVD0_ERR = TRANS_TX_FAIL_BASE, /* 0x200 */
347 TRANS_TX_PHY_NOT_ENABLE_ERR, /* 0x201 */
348 TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR, /* 0x202 */
349 TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR, /* 0x203 */
350 TRANS_TX_OPEN_REJCT_BY_OTHER_ERR, /* 0x204 */
351 TRANS_TX_RSVD1_ERR, /* 0x205 */
352 TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR, /* 0x206 */
353 TRANS_TX_OPEN_REJCT_STP_BUSY_ERR, /* 0x207 */
354 TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR, /* 0x208 */
355 TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR, /* 0x209 */
356 TRANS_TX_OPEN_REJCT_BAD_DEST_ERR, /* 0x20a */
357 TRANS_TX_OPEN_BREAK_RECEIVE_ERR, /* 0x20b */
358 TRANS_TX_LOW_PHY_POWER_ERR, /* 0x20c */
359 TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR, /* 0x20d */
360 TRANS_TX_OPEN_TIMEOUT_ERR, /* 0x20e */
361 TRANS_TX_OPEN_REJCT_NO_DEST_ERR, /* 0x20f */
362 TRANS_TX_OPEN_RETRY_ERR, /* 0x210 */
363 TRANS_TX_RSVD2_ERR, /* 0x211 */
364 TRANS_TX_BREAK_TIMEOUT_ERR, /* 0x212 */
365 TRANS_TX_BREAK_REQUEST_ERR, /* 0x213 */
366 TRANS_TX_BREAK_RECEIVE_ERR, /* 0x214 */
367 TRANS_TX_CLOSE_TIMEOUT_ERR, /* 0x215 */
368 TRANS_TX_CLOSE_NORMAL_ERR, /* 0x216 */
369 TRANS_TX_CLOSE_PHYRESET_ERR, /* 0x217 */
370 TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x218 */
371 TRANS_TX_WITH_CLOSE_COMINIT_ERR, /* 0x219 */
372 TRANS_TX_NAK_RECEIVE_ERR, /* 0x21a */
373 TRANS_TX_ACK_NAK_TIMEOUT_ERR, /* 0x21b */
374 TRANS_TX_CREDIT_TIMEOUT_ERR, /* 0x21c */
375 TRANS_TX_IPTT_CONFLICT_ERR, /* 0x21d */
376 TRANS_TX_TXFRM_TYPE_ERR, /* 0x21e */
377 TRANS_TX_TXSMP_LENGTH_ERR, /* 0x21f */
378
379 /* trans rx */
380 TRANS_RX_FRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x300 */
381 TRANS_RX_FRAME_DONE_ERR, /* 0x301 */
382 TRANS_RX_FRAME_ERRPRM_ERR, /* 0x302 */
383 TRANS_RX_FRAME_NO_CREDIT_ERR, /* 0x303 */
384 TRANS_RX_RSVD0_ERR, /* 0x304 */
385 TRANS_RX_FRAME_OVERRUN_ERR, /* 0x305 */
386 TRANS_RX_FRAME_NO_EOF_ERR, /* 0x306 */
387 TRANS_RX_LINK_BUF_OVERRUN_ERR, /* 0x307 */
388 TRANS_RX_BREAK_TIMEOUT_ERR, /* 0x308 */
389 TRANS_RX_BREAK_REQUEST_ERR, /* 0x309 */
390 TRANS_RX_BREAK_RECEIVE_ERR, /* 0x30a */
391 TRANS_RX_CLOSE_TIMEOUT_ERR, /* 0x30b */
392 TRANS_RX_CLOSE_NORMAL_ERR, /* 0x30c */
393 TRANS_RX_CLOSE_PHYRESET_ERR, /* 0x30d */
394 TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x30e */
395 TRANS_RX_WITH_CLOSE_COMINIT_ERR, /* 0x30f */
396 TRANS_RX_DATA_LENGTH0_ERR, /* 0x310 */
397 TRANS_RX_BAD_HASH_ERR, /* 0x311 */
398 TRANS_RX_XRDY_ZERO_ERR, /* 0x312 */
399 TRANS_RX_SSP_FRAME_LEN_ERR, /* 0x313 */
400 TRANS_RX_TRANS_RX_RSVD1_ERR, /* 0x314 */
401 TRANS_RX_NO_BALANCE_ERR, /* 0x315 */
402 TRANS_RX_TRANS_RX_RSVD2_ERR, /* 0x316 */
403 TRANS_RX_TRANS_RX_RSVD3_ERR, /* 0x317 */
404 TRANS_RX_BAD_FRAME_TYPE_ERR, /* 0x318 */
405 TRANS_RX_SMP_FRAME_LEN_ERR, /* 0x319 */
406 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x31a */
407 };
408
409 #define HISI_SAS_COMMAND_ENTRIES_V1_HW 8192
410
411 #define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS)
412 #define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES)
413 #define HISI_SAS_FATAL_INT_NR (2)
414
415 #define HISI_SAS_MAX_INT_NR \
416 (HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\
417 HISI_SAS_FATAL_INT_NR)
418
419 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
420 {
421 void __iomem *regs = hisi_hba->regs + off;
422
423 return readl(regs);
424 }
425
426 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
427 {
428 void __iomem *regs = hisi_hba->regs + off;
429
430 return readl_relaxed(regs);
431 }
432
433 static void hisi_sas_write32(struct hisi_hba *hisi_hba,
434 u32 off, u32 val)
435 {
436 void __iomem *regs = hisi_hba->regs + off;
437
438 writel(val, regs);
439 }
440
441 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba,
442 int phy_no, u32 off, u32 val)
443 {
444 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
445
446 writel(val, regs);
447 }
448
449 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
450 int phy_no, u32 off)
451 {
452 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
453
454 return readl(regs);
455 }
456
457 static void config_phy_opt_mode_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
458 {
459 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
460
461 cfg &= ~PHY_CFG_DC_OPT_MSK;
462 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
463 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
464 }
465
466 static void config_tx_tfe_autoneg_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
467 {
468 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CONFIG2);
469
470 cfg &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK;
471 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CONFIG2, cfg);
472 }
473
474 static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
475 {
476 struct sas_identify_frame identify_frame;
477 u32 *identify_buffer;
478
479 memset(&identify_frame, 0, sizeof(identify_frame));
480 identify_frame.dev_type = SAS_END_DEVICE;
481 identify_frame.frame_type = 0;
482 identify_frame._un1 = 1;
483 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
484 identify_frame.target_bits = SAS_PROTOCOL_NONE;
485 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
486 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
487 identify_frame.phy_id = phy_no;
488 identify_buffer = (u32 *)(&identify_frame);
489
490 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
491 __swab32(identify_buffer[0]));
492 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
493 __swab32(identify_buffer[1]));
494 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
495 __swab32(identify_buffer[2]));
496 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
497 __swab32(identify_buffer[3]));
498 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
499 __swab32(identify_buffer[4]));
500 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
501 __swab32(identify_buffer[5]));
502 }
503
504 static void setup_itct_v1_hw(struct hisi_hba *hisi_hba,
505 struct hisi_sas_device *sas_dev)
506 {
507 struct domain_device *device = sas_dev->sas_device;
508 struct device *dev = hisi_hba->dev;
509 u64 qw0, device_id = sas_dev->device_id;
510 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
511 struct asd_sas_port *sas_port = device->port;
512 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
513
514 memset(itct, 0, sizeof(*itct));
515
516 /* qw0 */
517 qw0 = 0;
518 switch (sas_dev->dev_type) {
519 case SAS_END_DEVICE:
520 case SAS_EDGE_EXPANDER_DEVICE:
521 case SAS_FANOUT_EXPANDER_DEVICE:
522 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
523 break;
524 default:
525 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
526 sas_dev->dev_type);
527 }
528
529 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
530 (1 << ITCT_HDR_AWT_CONTROL_OFF) |
531 (device->max_linkrate << ITCT_HDR_MAX_CONN_RATE_OFF) |
532 (1 << ITCT_HDR_VALID_LINK_NUM_OFF) |
533 (port->id << ITCT_HDR_PORT_ID_OFF));
534 itct->qw0 = cpu_to_le64(qw0);
535
536 /* qw1 */
537 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
538 itct->sas_addr = __swab64(itct->sas_addr);
539
540 /* qw2 */
541 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) |
542 (0xff00ULL << ITCT_HDR_BUS_INACTIVE_TL_OFF) |
543 (0xff00ULL << ITCT_HDR_MAX_CONN_TL_OFF) |
544 (0xff00ULL << ITCT_HDR_REJ_OPEN_TL_OFF));
545 }
546
547 static void clear_itct_v1_hw(struct hisi_hba *hisi_hba,
548 struct hisi_sas_device *sas_dev)
549 {
550 u64 dev_id = sas_dev->device_id;
551 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
552 u64 qw0;
553 u32 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);
554
555 reg_val |= CFG_AGING_TIME_ITCT_REL_MSK;
556 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
557
558 /* free itct */
559 udelay(1);
560 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);
561 reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK;
562 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
563
564 qw0 = cpu_to_le64(itct->qw0);
565 qw0 &= ~ITCT_HDR_VALID_MSK;
566 itct->qw0 = cpu_to_le64(qw0);
567 }
568
569 static int reset_hw_v1_hw(struct hisi_hba *hisi_hba)
570 {
571 int i;
572 unsigned long end_time;
573 u32 val;
574 struct device *dev = hisi_hba->dev;
575
576 for (i = 0; i < hisi_hba->n_phy; i++) {
577 u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL);
578
579 phy_ctrl |= PHY_CTRL_RESET_MSK;
580 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl);
581 }
582 msleep(1); /* It is safe to wait for 50us */
583
584 /* Ensure DMA tx & rx idle */
585 for (i = 0; i < hisi_hba->n_phy; i++) {
586 u32 dma_tx_status, dma_rx_status;
587
588 end_time = jiffies + msecs_to_jiffies(1000);
589
590 while (1) {
591 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
592 DMA_TX_STATUS);
593 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
594 DMA_RX_STATUS);
595
596 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
597 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
598 break;
599
600 msleep(20);
601 if (time_after(jiffies, end_time))
602 return -EIO;
603 }
604 }
605
606 /* Ensure axi bus idle */
607 end_time = jiffies + msecs_to_jiffies(1000);
608 while (1) {
609 u32 axi_status =
610 hisi_sas_read32(hisi_hba, AXI_CFG);
611
612 if (axi_status == 0)
613 break;
614
615 msleep(20);
616 if (time_after(jiffies, end_time))
617 return -EIO;
618 }
619
620 if (ACPI_HANDLE(dev)) {
621 acpi_status s;
622
623 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
624 if (ACPI_FAILURE(s)) {
625 dev_err(dev, "Reset failed\n");
626 return -EIO;
627 }
628 } else if (hisi_hba->ctrl) {
629 /* Apply reset and disable clock */
630 /* clk disable reg is offset by +4 bytes from clk enable reg */
631 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
632 RESET_VALUE);
633 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
634 RESET_VALUE);
635 msleep(1);
636 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
637 if (RESET_VALUE != (val & RESET_VALUE)) {
638 dev_err(dev, "Reset failed\n");
639 return -EIO;
640 }
641
642 /* De-reset and enable clock */
643 /* deassert rst reg is offset by +4 bytes from assert reg */
644 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
645 RESET_VALUE);
646 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
647 RESET_VALUE);
648 msleep(1);
649 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
650 if (val & RESET_VALUE) {
651 dev_err(dev, "De-reset failed\n");
652 return -EIO;
653 }
654 } else {
655 dev_warn(dev, "no reset method\n");
656 return -EINVAL;
657 }
658
659 return 0;
660 }
661
662 static void init_reg_v1_hw(struct hisi_hba *hisi_hba)
663 {
664 int i;
665
666 /* Global registers init*/
667 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
668 (u32)((1ULL << hisi_hba->queue_count) - 1));
669 hisi_sas_write32(hisi_hba, HGC_TRANS_TASK_CNT_LIMIT, 0x11);
670 hisi_sas_write32(hisi_hba, DEVICE_MSG_WORK_MODE, 0x1);
671 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff);
672 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x401);
673 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0x64);
674 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
675 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x64);
676 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x2710);
677 hisi_sas_write32(hisi_hba, REJECT_TO_OPEN_LIMIT_TIME, 0x1);
678 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x7a12);
679 hisi_sas_write32(hisi_hba, HGC_DFX_CFG2, 0x9c40);
680 hisi_sas_write32(hisi_hba, FIS_LIST_BADDR_L, 0x2);
681 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
682 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x186a0);
683 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 1);
684 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
685 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
686 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffffffff);
687 hisi_sas_write32(hisi_hba, OQ_INT_SRC_MSK, 0);
688 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
689 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0);
690 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
691 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0);
692 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0);
693 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 0x2);
694 hisi_sas_write32(hisi_hba, CFG_SAS_CONFIG, 0x22000000);
695
696 for (i = 0; i < hisi_hba->n_phy; i++) {
697 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x88a);
698 hisi_sas_phy_write32(hisi_hba, i, PHY_CONFIG2, 0x7c080);
699 hisi_sas_phy_write32(hisi_hba, i, PHY_RATE_NEGO, 0x415ee00);
700 hisi_sas_phy_write32(hisi_hba, i, PHY_PCN, 0x80a80000);
701 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
702 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x0);
703 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
704 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0);
705 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x13f0a);
706 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 3);
707 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 8);
708 }
709
710 for (i = 0; i < hisi_hba->queue_count; i++) {
711 /* Delivery queue */
712 hisi_sas_write32(hisi_hba,
713 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
714 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
715
716 hisi_sas_write32(hisi_hba,
717 DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
718 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
719
720 hisi_sas_write32(hisi_hba,
721 DLVRY_Q_0_DEPTH + (i * 0x14),
722 HISI_SAS_QUEUE_SLOTS);
723
724 /* Completion queue */
725 hisi_sas_write32(hisi_hba,
726 COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
727 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
728
729 hisi_sas_write32(hisi_hba,
730 COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
731 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
732
733 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
734 HISI_SAS_QUEUE_SLOTS);
735 }
736
737 /* itct */
738 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
739 lower_32_bits(hisi_hba->itct_dma));
740
741 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
742 upper_32_bits(hisi_hba->itct_dma));
743
744 /* iost */
745 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
746 lower_32_bits(hisi_hba->iost_dma));
747
748 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
749 upper_32_bits(hisi_hba->iost_dma));
750
751 /* breakpoint */
752 hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_LO,
753 lower_32_bits(hisi_hba->breakpoint_dma));
754
755 hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_HI,
756 upper_32_bits(hisi_hba->breakpoint_dma));
757 }
758
759 static int hw_init_v1_hw(struct hisi_hba *hisi_hba)
760 {
761 struct device *dev = hisi_hba->dev;
762 int rc;
763
764 rc = reset_hw_v1_hw(hisi_hba);
765 if (rc) {
766 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
767 return rc;
768 }
769
770 msleep(100);
771 init_reg_v1_hw(hisi_hba);
772
773 return 0;
774 }
775
776 static void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
777 {
778 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
779
780 cfg |= PHY_CFG_ENA_MSK;
781 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
782 }
783
784 static void disable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
785 {
786 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
787
788 cfg &= ~PHY_CFG_ENA_MSK;
789 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
790 }
791
792 static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
793 {
794 config_id_frame_v1_hw(hisi_hba, phy_no);
795 config_phy_opt_mode_v1_hw(hisi_hba, phy_no);
796 config_tx_tfe_autoneg_v1_hw(hisi_hba, phy_no);
797 enable_phy_v1_hw(hisi_hba, phy_no);
798 }
799
800 static void stop_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
801 {
802 disable_phy_v1_hw(hisi_hba, phy_no);
803 }
804
805 static void phy_hard_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
806 {
807 stop_phy_v1_hw(hisi_hba, phy_no);
808 msleep(100);
809 start_phy_v1_hw(hisi_hba, phy_no);
810 }
811
812 static void start_phys_v1_hw(struct timer_list *t)
813 {
814 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
815 int i;
816
817 for (i = 0; i < hisi_hba->n_phy; i++) {
818 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x12a);
819 start_phy_v1_hw(hisi_hba, i);
820 }
821 }
822
823 static void phys_init_v1_hw(struct hisi_hba *hisi_hba)
824 {
825 int i;
826 struct timer_list *timer = &hisi_hba->timer;
827
828 for (i = 0; i < hisi_hba->n_phy; i++) {
829 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
830 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
831 }
832
833 timer_setup(timer, start_phys_v1_hw, 0);
834 mod_timer(timer, jiffies + HZ);
835 }
836
837 static void sl_notify_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
838 {
839 u32 sl_control;
840
841 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
842 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
843 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
844 msleep(1);
845 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
846 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
847 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
848 }
849
850 static enum sas_linkrate phy_get_max_linkrate_v1_hw(void)
851 {
852 return SAS_LINK_RATE_6_0_GBPS;
853 }
854
855 static void phy_set_linkrate_v1_hw(struct hisi_hba *hisi_hba, int phy_no,
856 struct sas_phy_linkrates *r)
857 {
858 u32 prog_phy_link_rate =
859 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
860 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
861 struct asd_sas_phy *sas_phy = &phy->sas_phy;
862 int i;
863 enum sas_linkrate min, max;
864 u32 rate_mask = 0;
865
866 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
867 max = sas_phy->phy->maximum_linkrate;
868 min = r->minimum_linkrate;
869 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
870 max = r->maximum_linkrate;
871 min = sas_phy->phy->minimum_linkrate;
872 } else
873 return;
874
875 sas_phy->phy->maximum_linkrate = max;
876 sas_phy->phy->minimum_linkrate = min;
877
878 max -= SAS_LINK_RATE_1_5_GBPS;
879
880 for (i = 0; i <= max; i++)
881 rate_mask |= 1 << (i * 2);
882
883 prog_phy_link_rate &= ~0xff;
884 prog_phy_link_rate |= rate_mask;
885
886 disable_phy_v1_hw(hisi_hba, phy_no);
887 msleep(100);
888 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
889 prog_phy_link_rate);
890 start_phy_v1_hw(hisi_hba, phy_no);
891 }
892
893 static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id)
894 {
895 int i, bitmap = 0;
896 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
897
898 for (i = 0; i < hisi_hba->n_phy; i++)
899 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
900 bitmap |= 1 << i;
901
902 return bitmap;
903 }
904
905 /*
906 * The callpath to this function and upto writing the write
907 * queue pointer should be safe from interruption.
908 */
909 static int
910 get_free_slot_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
911 {
912 struct device *dev = hisi_hba->dev;
913 int queue = dq->id;
914 u32 r, w;
915
916 w = dq->wr_point;
917 r = hisi_sas_read32_relaxed(hisi_hba,
918 DLVRY_Q_0_RD_PTR + (queue * 0x14));
919 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
920 dev_warn(dev, "could not find free slot\n");
921 return -EAGAIN;
922 }
923
924 return 0;
925 }
926
927 static void start_delivery_v1_hw(struct hisi_sas_dq *dq)
928 {
929 struct hisi_hba *hisi_hba = dq->hisi_hba;
930 int dlvry_queue = dq->slot_prep->dlvry_queue;
931 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
932
933 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
934 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
935 dq->wr_point);
936 }
937
938 static void prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba,
939 struct hisi_sas_slot *slot,
940 struct hisi_sas_cmd_hdr *hdr,
941 struct scatterlist *scatter,
942 int n_elem)
943 {
944 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
945 struct scatterlist *sg;
946 int i;
947
948 for_each_sg(scatter, sg, n_elem, i) {
949 struct hisi_sas_sge *entry = &sge_page->sge[i];
950
951 entry->addr = cpu_to_le64(sg_dma_address(sg));
952 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
953 entry->data_len = cpu_to_le32(sg_dma_len(sg));
954 entry->data_off = 0;
955 }
956
957 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
958
959 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
960 }
961
962 static void prep_smp_v1_hw(struct hisi_hba *hisi_hba,
963 struct hisi_sas_slot *slot)
964 {
965 struct sas_task *task = slot->task;
966 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
967 struct domain_device *device = task->dev;
968 struct hisi_sas_port *port = slot->port;
969 struct scatterlist *sg_req;
970 struct hisi_sas_device *sas_dev = device->lldd_dev;
971 dma_addr_t req_dma_addr;
972 unsigned int req_len;
973
974 /* req */
975 sg_req = &task->smp_task.smp_req;
976 req_len = sg_dma_len(sg_req);
977 req_dma_addr = sg_dma_address(sg_req);
978
979 /* create header */
980 /* dw0 */
981 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
982 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
983 (1 << CMD_HDR_MODE_OFF) | /* ini mode */
984 (2 << CMD_HDR_CMD_OFF)); /* smp */
985
986 /* map itct entry */
987 hdr->dw1 = cpu_to_le32(sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF);
988
989 /* dw2 */
990 hdr->dw2 = cpu_to_le32((((req_len-4)/4) << CMD_HDR_CFL_OFF) |
991 (HISI_SAS_MAX_SMP_RESP_SZ/4 <<
992 CMD_HDR_MRFL_OFF));
993
994 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
995
996 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
997 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
998 }
999
1000 static void prep_ssp_v1_hw(struct hisi_hba *hisi_hba,
1001 struct hisi_sas_slot *slot, int is_tmf,
1002 struct hisi_sas_tmf_task *tmf)
1003 {
1004 struct sas_task *task = slot->task;
1005 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1006 struct domain_device *device = task->dev;
1007 struct hisi_sas_device *sas_dev = device->lldd_dev;
1008 struct hisi_sas_port *port = slot->port;
1009 struct sas_ssp_task *ssp_task = &task->ssp_task;
1010 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1011 int has_data = 0, priority = is_tmf;
1012 u8 *buf_cmd, fburst = 0;
1013 u32 dw1, dw2;
1014
1015 /* create header */
1016 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1017 (0x2 << CMD_HDR_TLR_CTRL_OFF) |
1018 (port->id << CMD_HDR_PORT_OFF) |
1019 (priority << CMD_HDR_PRIORITY_OFF) |
1020 (1 << CMD_HDR_MODE_OFF) | /* ini mode */
1021 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1022
1023 dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF;
1024
1025 if (is_tmf) {
1026 dw1 |= 3 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1027 } else {
1028 switch (scsi_cmnd->sc_data_direction) {
1029 case DMA_TO_DEVICE:
1030 dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1031 has_data = 1;
1032 break;
1033 case DMA_FROM_DEVICE:
1034 dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1035 has_data = 1;
1036 break;
1037 default:
1038 dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1039 }
1040 }
1041
1042 /* map itct entry */
1043 dw1 |= sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF;
1044 hdr->dw1 = cpu_to_le32(dw1);
1045
1046 if (is_tmf) {
1047 dw2 = ((sizeof(struct ssp_tmf_iu) +
1048 sizeof(struct ssp_frame_hdr)+3)/4) <<
1049 CMD_HDR_CFL_OFF;
1050 } else {
1051 dw2 = ((sizeof(struct ssp_command_iu) +
1052 sizeof(struct ssp_frame_hdr)+3)/4) <<
1053 CMD_HDR_CFL_OFF;
1054 }
1055
1056 dw2 |= (HISI_SAS_MAX_SSP_RESP_SZ/4) << CMD_HDR_MRFL_OFF;
1057
1058 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1059
1060 if (has_data)
1061 prep_prd_sge_v1_hw(hisi_hba, slot, hdr, task->scatter,
1062 slot->n_elem);
1063
1064 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1065 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1066 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1067
1068 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1069 sizeof(struct ssp_frame_hdr);
1070 if (task->ssp_task.enable_first_burst) {
1071 fburst = (1 << 7);
1072 dw2 |= 1 << CMD_HDR_FIRST_BURST_OFF;
1073 }
1074 hdr->dw2 = cpu_to_le32(dw2);
1075
1076 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1077 if (!is_tmf) {
1078 buf_cmd[9] = fburst | task->ssp_task.task_attr |
1079 (task->ssp_task.task_prio << 3);
1080 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1081 task->ssp_task.cmd->cmd_len);
1082 } else {
1083 buf_cmd[10] = tmf->tmf;
1084 switch (tmf->tmf) {
1085 case TMF_ABORT_TASK:
1086 case TMF_QUERY_TASK:
1087 buf_cmd[12] =
1088 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1089 buf_cmd[13] =
1090 tmf->tag_of_task_to_be_managed & 0xff;
1091 break;
1092 default:
1093 break;
1094 }
1095 }
1096 }
1097
1098 /* by default, task resp is complete */
1099 static void slot_err_v1_hw(struct hisi_hba *hisi_hba,
1100 struct sas_task *task,
1101 struct hisi_sas_slot *slot)
1102 {
1103 struct task_status_struct *ts = &task->task_status;
1104 struct hisi_sas_err_record_v1 *err_record =
1105 hisi_sas_status_buf_addr_mem(slot);
1106 struct device *dev = hisi_hba->dev;
1107
1108 switch (task->task_proto) {
1109 case SAS_PROTOCOL_SSP:
1110 {
1111 int error = -1;
1112 u32 dma_err_type = cpu_to_le32(err_record->dma_err_type);
1113 u32 dma_tx_err_type = ((dma_err_type &
1114 ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >>
1115 ERR_HDR_DMA_TX_ERR_TYPE_OFF;
1116 u32 dma_rx_err_type = ((dma_err_type &
1117 ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >>
1118 ERR_HDR_DMA_RX_ERR_TYPE_OFF;
1119 u32 trans_tx_fail_type =
1120 cpu_to_le32(err_record->trans_tx_fail_type);
1121 u32 trans_rx_fail_type =
1122 cpu_to_le32(err_record->trans_rx_fail_type);
1123
1124 if (dma_tx_err_type) {
1125 /* dma tx err */
1126 error = ffs(dma_tx_err_type)
1127 - 1 + DMA_TX_ERR_BASE;
1128 } else if (dma_rx_err_type) {
1129 /* dma rx err */
1130 error = ffs(dma_rx_err_type)
1131 - 1 + DMA_RX_ERR_BASE;
1132 } else if (trans_tx_fail_type) {
1133 /* trans tx err */
1134 error = ffs(trans_tx_fail_type)
1135 - 1 + TRANS_TX_FAIL_BASE;
1136 } else if (trans_rx_fail_type) {
1137 /* trans rx err */
1138 error = ffs(trans_rx_fail_type)
1139 - 1 + TRANS_RX_FAIL_BASE;
1140 }
1141
1142 switch (error) {
1143 case DMA_TX_DATA_UNDERFLOW_ERR:
1144 case DMA_RX_DATA_UNDERFLOW_ERR:
1145 {
1146 ts->residual = 0;
1147 ts->stat = SAS_DATA_UNDERRUN;
1148 break;
1149 }
1150 case DMA_TX_DATA_SGL_OVERFLOW_ERR:
1151 case DMA_TX_DIF_SGL_OVERFLOW_ERR:
1152 case DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR:
1153 case DMA_RX_DATA_OVERFLOW_ERR:
1154 case TRANS_RX_FRAME_OVERRUN_ERR:
1155 case TRANS_RX_LINK_BUF_OVERRUN_ERR:
1156 {
1157 ts->stat = SAS_DATA_OVERRUN;
1158 ts->residual = 0;
1159 break;
1160 }
1161 case TRANS_TX_PHY_NOT_ENABLE_ERR:
1162 {
1163 ts->stat = SAS_PHY_DOWN;
1164 break;
1165 }
1166 case TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR:
1167 case TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR:
1168 case TRANS_TX_OPEN_REJCT_BY_OTHER_ERR:
1169 case TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR:
1170 case TRANS_TX_OPEN_REJCT_STP_BUSY_ERR:
1171 case TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR:
1172 case TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR:
1173 case TRANS_TX_OPEN_REJCT_BAD_DEST_ERR:
1174 case TRANS_TX_OPEN_BREAK_RECEIVE_ERR:
1175 case TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR:
1176 case TRANS_TX_OPEN_REJCT_NO_DEST_ERR:
1177 case TRANS_TX_OPEN_RETRY_ERR:
1178 {
1179 ts->stat = SAS_OPEN_REJECT;
1180 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1181 break;
1182 }
1183 case TRANS_TX_OPEN_TIMEOUT_ERR:
1184 {
1185 ts->stat = SAS_OPEN_TO;
1186 break;
1187 }
1188 case TRANS_TX_NAK_RECEIVE_ERR:
1189 case TRANS_TX_ACK_NAK_TIMEOUT_ERR:
1190 {
1191 ts->stat = SAS_NAK_R_ERR;
1192 break;
1193 }
1194 case TRANS_TX_CREDIT_TIMEOUT_ERR:
1195 case TRANS_TX_CLOSE_NORMAL_ERR:
1196 {
1197 /* This will request a retry */
1198 ts->stat = SAS_QUEUE_FULL;
1199 slot->abort = 1;
1200 break;
1201 }
1202 default:
1203 {
1204 ts->stat = SAM_STAT_CHECK_CONDITION;
1205 break;
1206 }
1207 }
1208 }
1209 break;
1210 case SAS_PROTOCOL_SMP:
1211 ts->stat = SAM_STAT_CHECK_CONDITION;
1212 break;
1213
1214 case SAS_PROTOCOL_SATA:
1215 case SAS_PROTOCOL_STP:
1216 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1217 {
1218 dev_err(dev, "slot err: SATA/STP not supported");
1219 }
1220 break;
1221 default:
1222 break;
1223 }
1224
1225 }
1226
1227 static int slot_complete_v1_hw(struct hisi_hba *hisi_hba,
1228 struct hisi_sas_slot *slot)
1229 {
1230 struct sas_task *task = slot->task;
1231 struct hisi_sas_device *sas_dev;
1232 struct device *dev = hisi_hba->dev;
1233 struct task_status_struct *ts;
1234 struct domain_device *device;
1235 enum exec_status sts;
1236 struct hisi_sas_complete_v1_hdr *complete_queue =
1237 hisi_hba->complete_hdr[slot->cmplt_queue];
1238 struct hisi_sas_complete_v1_hdr *complete_hdr;
1239 unsigned long flags;
1240 u32 cmplt_hdr_data;
1241
1242 complete_hdr = &complete_queue[slot->cmplt_queue_slot];
1243 cmplt_hdr_data = le32_to_cpu(complete_hdr->data);
1244
1245 if (unlikely(!task || !task->lldd_task || !task->dev))
1246 return -EINVAL;
1247
1248 ts = &task->task_status;
1249 device = task->dev;
1250 sas_dev = device->lldd_dev;
1251
1252 spin_lock_irqsave(&task->task_state_lock, flags);
1253 task->task_state_flags &=
1254 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1255 task->task_state_flags |= SAS_TASK_STATE_DONE;
1256 spin_unlock_irqrestore(&task->task_state_lock, flags);
1257
1258 memset(ts, 0, sizeof(*ts));
1259 ts->resp = SAS_TASK_COMPLETE;
1260
1261 if (unlikely(!sas_dev)) {
1262 dev_dbg(dev, "slot complete: port has no device\n");
1263 ts->stat = SAS_PHY_DOWN;
1264 goto out;
1265 }
1266
1267 if (cmplt_hdr_data & CMPLT_HDR_IO_CFG_ERR_MSK) {
1268 u32 info_reg = hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO);
1269
1270 if (info_reg & HGC_INVLD_DQE_INFO_DQ_MSK)
1271 dev_err(dev, "slot complete: [%d:%d] has dq IPTT err",
1272 slot->cmplt_queue, slot->cmplt_queue_slot);
1273
1274 if (info_reg & HGC_INVLD_DQE_INFO_TYPE_MSK)
1275 dev_err(dev, "slot complete: [%d:%d] has dq type err",
1276 slot->cmplt_queue, slot->cmplt_queue_slot);
1277
1278 if (info_reg & HGC_INVLD_DQE_INFO_FORCE_MSK)
1279 dev_err(dev, "slot complete: [%d:%d] has dq force phy err",
1280 slot->cmplt_queue, slot->cmplt_queue_slot);
1281
1282 if (info_reg & HGC_INVLD_DQE_INFO_PHY_MSK)
1283 dev_err(dev, "slot complete: [%d:%d] has dq phy id err",
1284 slot->cmplt_queue, slot->cmplt_queue_slot);
1285
1286 if (info_reg & HGC_INVLD_DQE_INFO_ABORT_MSK)
1287 dev_err(dev, "slot complete: [%d:%d] has dq abort flag err",
1288 slot->cmplt_queue, slot->cmplt_queue_slot);
1289
1290 if (info_reg & HGC_INVLD_DQE_INFO_IPTT_OF_MSK)
1291 dev_err(dev, "slot complete: [%d:%d] has dq IPTT or ICT err",
1292 slot->cmplt_queue, slot->cmplt_queue_slot);
1293
1294 if (info_reg & HGC_INVLD_DQE_INFO_SSP_ERR_MSK)
1295 dev_err(dev, "slot complete: [%d:%d] has dq SSP frame type err",
1296 slot->cmplt_queue, slot->cmplt_queue_slot);
1297
1298 if (info_reg & HGC_INVLD_DQE_INFO_OFL_MSK)
1299 dev_err(dev, "slot complete: [%d:%d] has dq order frame len err",
1300 slot->cmplt_queue, slot->cmplt_queue_slot);
1301
1302 ts->stat = SAS_OPEN_REJECT;
1303 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1304 goto out;
1305 }
1306
1307 if (cmplt_hdr_data & CMPLT_HDR_ERR_RCRD_XFRD_MSK &&
1308 !(cmplt_hdr_data & CMPLT_HDR_RSPNS_XFRD_MSK)) {
1309
1310 slot_err_v1_hw(hisi_hba, task, slot);
1311 if (unlikely(slot->abort)) {
1312 queue_work(hisi_hba->wq, &slot->abort_slot);
1313 /* immediately return and do not complete */
1314 return ts->stat;
1315 }
1316 goto out;
1317 }
1318
1319 switch (task->task_proto) {
1320 case SAS_PROTOCOL_SSP:
1321 {
1322 struct hisi_sas_status_buffer *status_buffer =
1323 hisi_sas_status_buf_addr_mem(slot);
1324 struct ssp_response_iu *iu = (struct ssp_response_iu *)
1325 &status_buffer->iu[0];
1326
1327 sas_ssp_task_response(dev, task, iu);
1328 break;
1329 }
1330 case SAS_PROTOCOL_SMP:
1331 {
1332 void *to;
1333 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1334
1335 ts->stat = SAM_STAT_GOOD;
1336 to = kmap_atomic(sg_page(sg_resp));
1337
1338 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1339 DMA_FROM_DEVICE);
1340 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1341 DMA_TO_DEVICE);
1342 memcpy(to + sg_resp->offset,
1343 hisi_sas_status_buf_addr_mem(slot) +
1344 sizeof(struct hisi_sas_err_record),
1345 sg_dma_len(sg_resp));
1346 kunmap_atomic(to);
1347 break;
1348 }
1349 case SAS_PROTOCOL_SATA:
1350 case SAS_PROTOCOL_STP:
1351 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1352 dev_err(dev, "slot complete: SATA/STP not supported");
1353 break;
1354
1355 default:
1356 ts->stat = SAM_STAT_CHECK_CONDITION;
1357 break;
1358 }
1359
1360 if (!slot->port->port_attached) {
1361 dev_err(dev, "slot complete: port %d has removed\n",
1362 slot->port->sas_port.id);
1363 ts->stat = SAS_PHY_DOWN;
1364 }
1365
1366 out:
1367 hisi_sas_slot_task_free(hisi_hba, task, slot);
1368 sts = ts->stat;
1369
1370 if (task->task_done)
1371 task->task_done(task);
1372
1373 return sts;
1374 }
1375
1376 /* Interrupts */
1377 static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
1378 {
1379 struct hisi_sas_phy *phy = p;
1380 struct hisi_hba *hisi_hba = phy->hisi_hba;
1381 struct device *dev = hisi_hba->dev;
1382 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1383 int i, phy_no = sas_phy->id;
1384 u32 irq_value, context, port_id, link_rate;
1385 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1386 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
1387 irqreturn_t res = IRQ_HANDLED;
1388
1389 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1390 if (!(irq_value & CHL_INT2_SL_PHY_ENA_MSK)) {
1391 dev_dbg(dev, "phyup: irq_value = %x not set enable bit\n",
1392 irq_value);
1393 res = IRQ_NONE;
1394 goto end;
1395 }
1396
1397 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1398 if (context & 1 << phy_no) {
1399 dev_err(dev, "phyup: phy%d SATA attached equipment\n",
1400 phy_no);
1401 goto end;
1402 }
1403
1404 port_id = (hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA) >> (4 * phy_no))
1405 & 0xf;
1406 if (port_id == 0xf) {
1407 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1408 res = IRQ_NONE;
1409 goto end;
1410 }
1411
1412 for (i = 0; i < 6; i++) {
1413 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1414 RX_IDAF_DWORD0 + (i * 4));
1415 frame_rcvd[i] = __swab32(idaf);
1416 }
1417
1418 /* Get the linkrate */
1419 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1420 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1421 sas_phy->linkrate = link_rate;
1422 sas_phy->oob_mode = SAS_OOB_MODE;
1423 memcpy(sas_phy->attached_sas_addr,
1424 &id->sas_addr, SAS_ADDR_SIZE);
1425 dev_info(dev, "phyup: phy%d link_rate=%d\n",
1426 phy_no, link_rate);
1427 phy->port_id = port_id;
1428 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1429 phy->phy_type |= PORT_TYPE_SAS;
1430 phy->phy_attached = 1;
1431 phy->identify.device_type = id->dev_type;
1432 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1433 if (phy->identify.device_type == SAS_END_DEVICE)
1434 phy->identify.target_port_protocols =
1435 SAS_PROTOCOL_SSP;
1436 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1437 phy->identify.target_port_protocols =
1438 SAS_PROTOCOL_SMP;
1439 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1440
1441 end:
1442 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
1443 CHL_INT2_SL_PHY_ENA_MSK);
1444
1445 if (irq_value & CHL_INT2_SL_PHY_ENA_MSK) {
1446 u32 chl_int0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1447
1448 chl_int0 &= ~CHL_INT0_PHYCTRL_NOTRDY_MSK;
1449 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, chl_int0);
1450 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3ce3ee);
1451 }
1452
1453 return res;
1454 }
1455
1456 static irqreturn_t int_bcast_v1_hw(int irq, void *p)
1457 {
1458 struct hisi_sas_phy *phy = p;
1459 struct hisi_hba *hisi_hba = phy->hisi_hba;
1460 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1461 struct sas_ha_struct *sha = &hisi_hba->sha;
1462 struct device *dev = hisi_hba->dev;
1463 int phy_no = sas_phy->id;
1464 u32 irq_value;
1465 irqreturn_t res = IRQ_HANDLED;
1466
1467 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1468
1469 if (!(irq_value & CHL_INT2_SL_RX_BC_ACK_MSK)) {
1470 dev_err(dev, "bcast: irq_value = %x not set enable bit",
1471 irq_value);
1472 res = IRQ_NONE;
1473 goto end;
1474 }
1475
1476 sha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1477
1478 end:
1479 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
1480 CHL_INT2_SL_RX_BC_ACK_MSK);
1481
1482 return res;
1483 }
1484
1485 static irqreturn_t int_abnormal_v1_hw(int irq, void *p)
1486 {
1487 struct hisi_sas_phy *phy = p;
1488 struct hisi_hba *hisi_hba = phy->hisi_hba;
1489 struct device *dev = hisi_hba->dev;
1490 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1491 u32 irq_value, irq_mask_old;
1492 int phy_no = sas_phy->id;
1493
1494 /* mask_int0 */
1495 irq_mask_old = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0_MSK);
1496 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3fffff);
1497
1498 /* read int0 */
1499 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1500
1501 if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) {
1502 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1503
1504 hisi_sas_phy_down(hisi_hba, phy_no,
1505 (phy_state & 1 << phy_no) ? 1 : 0);
1506 }
1507
1508 if (irq_value & CHL_INT0_ID_TIMEOUT_MSK)
1509 dev_dbg(dev, "abnormal: ID_TIMEOUT phy%d identify timeout\n",
1510 phy_no);
1511
1512 if (irq_value & CHL_INT0_DWS_LOST_MSK)
1513 dev_dbg(dev, "abnormal: DWS_LOST phy%d dws lost\n", phy_no);
1514
1515 if (irq_value & CHL_INT0_SN_FAIL_NGR_MSK)
1516 dev_dbg(dev, "abnormal: SN_FAIL_NGR phy%d sn fail ngr\n",
1517 phy_no);
1518
1519 if (irq_value & CHL_INT0_SL_IDAF_FAIL_MSK ||
1520 irq_value & CHL_INT0_SL_OPAF_FAIL_MSK)
1521 dev_dbg(dev, "abnormal: SL_ID/OPAF_FAIL phy%d check adr frm err\n",
1522 phy_no);
1523
1524 if (irq_value & CHL_INT0_SL_PS_FAIL_OFF)
1525 dev_dbg(dev, "abnormal: SL_PS_FAIL phy%d fail\n", phy_no);
1526
1527 /* write to zero */
1528 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, irq_value);
1529
1530 if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK)
1531 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK,
1532 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK);
1533 else
1534 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK,
1535 irq_mask_old);
1536
1537 return IRQ_HANDLED;
1538 }
1539
1540 static irqreturn_t cq_interrupt_v1_hw(int irq, void *p)
1541 {
1542 struct hisi_sas_cq *cq = p;
1543 struct hisi_hba *hisi_hba = cq->hisi_hba;
1544 struct hisi_sas_slot *slot;
1545 int queue = cq->id;
1546 struct hisi_sas_complete_v1_hdr *complete_queue =
1547 (struct hisi_sas_complete_v1_hdr *)
1548 hisi_hba->complete_hdr[queue];
1549 u32 irq_value, rd_point = cq->rd_point, wr_point;
1550
1551 spin_lock(&hisi_hba->lock);
1552 irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
1553
1554 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1555 wr_point = hisi_sas_read32(hisi_hba,
1556 COMPL_Q_0_WR_PTR + (0x14 * queue));
1557
1558 while (rd_point != wr_point) {
1559 struct hisi_sas_complete_v1_hdr *complete_hdr;
1560 int idx;
1561 u32 cmplt_hdr_data;
1562
1563 complete_hdr = &complete_queue[rd_point];
1564 cmplt_hdr_data = cpu_to_le32(complete_hdr->data);
1565 idx = (cmplt_hdr_data & CMPLT_HDR_IPTT_MSK) >>
1566 CMPLT_HDR_IPTT_OFF;
1567 slot = &hisi_hba->slot_info[idx];
1568
1569 /* The completion queue and queue slot index are not
1570 * necessarily the same as the delivery queue and
1571 * queue slot index.
1572 */
1573 slot->cmplt_queue_slot = rd_point;
1574 slot->cmplt_queue = queue;
1575 slot_complete_v1_hw(hisi_hba, slot);
1576
1577 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1578 rd_point = 0;
1579 }
1580
1581 /* update rd_point */
1582 cq->rd_point = rd_point;
1583 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1584 spin_unlock(&hisi_hba->lock);
1585
1586 return IRQ_HANDLED;
1587 }
1588
1589 static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p)
1590 {
1591 struct hisi_hba *hisi_hba = p;
1592 struct device *dev = hisi_hba->dev;
1593 u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
1594
1595 if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) {
1596 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1597
1598 panic("%s: Fatal DQ 1b ECC interrupt (0x%x)\n",
1599 dev_name(dev), ecc_err);
1600 }
1601
1602 if (ecc_int & SAS_ECC_INTR_DQ_ECCBAD_MSK) {
1603 u32 addr = (hisi_sas_read32(hisi_hba, HGC_DQ_ECC_ADDR) &
1604 HGC_DQ_ECC_ADDR_BAD_MSK) >>
1605 HGC_DQ_ECC_ADDR_BAD_OFF;
1606
1607 panic("%s: Fatal DQ RAM ECC interrupt @ 0x%08x\n",
1608 dev_name(dev), addr);
1609 }
1610
1611 if (ecc_int & SAS_ECC_INTR_IOST_ECC1B_MSK) {
1612 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1613
1614 panic("%s: Fatal IOST 1b ECC interrupt (0x%x)\n",
1615 dev_name(dev), ecc_err);
1616 }
1617
1618 if (ecc_int & SAS_ECC_INTR_IOST_ECCBAD_MSK) {
1619 u32 addr = (hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR) &
1620 HGC_IOST_ECC_ADDR_BAD_MSK) >>
1621 HGC_IOST_ECC_ADDR_BAD_OFF;
1622
1623 panic("%s: Fatal IOST RAM ECC interrupt @ 0x%08x\n",
1624 dev_name(dev), addr);
1625 }
1626
1627 if (ecc_int & SAS_ECC_INTR_ITCT_ECCBAD_MSK) {
1628 u32 addr = (hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR) &
1629 HGC_ITCT_ECC_ADDR_BAD_MSK) >>
1630 HGC_ITCT_ECC_ADDR_BAD_OFF;
1631
1632 panic("%s: Fatal TCT RAM ECC interrupt @ 0x%08x\n",
1633 dev_name(dev), addr);
1634 }
1635
1636 if (ecc_int & SAS_ECC_INTR_ITCT_ECC1B_MSK) {
1637 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1638
1639 panic("%s: Fatal ITCT 1b ECC interrupt (0x%x)\n",
1640 dev_name(dev), ecc_err);
1641 }
1642
1643 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, ecc_int | 0x3f);
1644
1645 return IRQ_HANDLED;
1646 }
1647
1648 static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p)
1649 {
1650 struct hisi_hba *hisi_hba = p;
1651 struct device *dev = hisi_hba->dev;
1652 u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2);
1653 u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO);
1654
1655 if (axi_int & ENT_INT_SRC2_DQ_CFG_ERR_MSK)
1656 panic("%s: Fatal DQ_CFG_ERR interrupt (0x%x)\n",
1657 dev_name(dev), axi_info);
1658
1659 if (axi_int & ENT_INT_SRC2_CQ_CFG_ERR_MSK)
1660 panic("%s: Fatal CQ_CFG_ERR interrupt (0x%x)\n",
1661 dev_name(dev), axi_info);
1662
1663 if (axi_int & ENT_INT_SRC2_AXI_WRONG_INT_MSK)
1664 panic("%s: Fatal AXI_WRONG_INT interrupt (0x%x)\n",
1665 dev_name(dev), axi_info);
1666
1667 if (axi_int & ENT_INT_SRC2_AXI_OVERLF_INT_MSK)
1668 panic("%s: Fatal AXI_OVERLF_INT incorrect interrupt (0x%x)\n",
1669 dev_name(dev), axi_info);
1670
1671 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, axi_int | 0x30000000);
1672
1673 return IRQ_HANDLED;
1674 }
1675
1676 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
1677 int_bcast_v1_hw,
1678 int_phyup_v1_hw,
1679 int_abnormal_v1_hw
1680 };
1681
1682 static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = {
1683 fatal_ecc_int_v1_hw,
1684 fatal_axi_int_v1_hw
1685 };
1686
1687 static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
1688 {
1689 struct platform_device *pdev = hisi_hba->platform_dev;
1690 struct device *dev = &pdev->dev;
1691 int i, j, irq, rc, idx;
1692
1693 for (i = 0; i < hisi_hba->n_phy; i++) {
1694 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1695
1696 idx = i * HISI_SAS_PHY_INT_NR;
1697 for (j = 0; j < HISI_SAS_PHY_INT_NR; j++, idx++) {
1698 irq = platform_get_irq(pdev, idx);
1699 if (!irq) {
1700 dev_err(dev,
1701 "irq init: fail map phy interrupt %d\n",
1702 idx);
1703 return -ENOENT;
1704 }
1705
1706 rc = devm_request_irq(dev, irq, phy_interrupts[j], 0,
1707 DRV_NAME " phy", phy);
1708 if (rc) {
1709 dev_err(dev, "irq init: could not request "
1710 "phy interrupt %d, rc=%d\n",
1711 irq, rc);
1712 return -ENOENT;
1713 }
1714 }
1715 }
1716
1717 idx = hisi_hba->n_phy * HISI_SAS_PHY_INT_NR;
1718 for (i = 0; i < hisi_hba->queue_count; i++, idx++) {
1719 irq = platform_get_irq(pdev, idx);
1720 if (!irq) {
1721 dev_err(dev, "irq init: could not map cq interrupt %d\n",
1722 idx);
1723 return -ENOENT;
1724 }
1725
1726 rc = devm_request_irq(dev, irq, cq_interrupt_v1_hw, 0,
1727 DRV_NAME " cq", &hisi_hba->cq[i]);
1728 if (rc) {
1729 dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n",
1730 irq, rc);
1731 return -ENOENT;
1732 }
1733 }
1734
1735 idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + hisi_hba->queue_count;
1736 for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++, idx++) {
1737 irq = platform_get_irq(pdev, idx);
1738 if (!irq) {
1739 dev_err(dev, "irq init: could not map fatal interrupt %d\n",
1740 idx);
1741 return -ENOENT;
1742 }
1743
1744 rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0,
1745 DRV_NAME " fatal", hisi_hba);
1746 if (rc) {
1747 dev_err(dev,
1748 "irq init: could not request fatal interrupt %d, rc=%d\n",
1749 irq, rc);
1750 return -ENOENT;
1751 }
1752 }
1753
1754 return 0;
1755 }
1756
1757 static int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba)
1758 {
1759 int i;
1760 u32 val;
1761
1762 for (i = 0; i < hisi_hba->n_phy; i++) {
1763 /* Clear interrupt status */
1764 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT0);
1765 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, val);
1766 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT1);
1767 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, val);
1768 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT2);
1769 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, val);
1770
1771 /* Unmask interrupt */
1772 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 0x3ce3ee);
1773 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0x17fff);
1774 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8000012a);
1775
1776 /* bypass chip bug mask abnormal intr */
1777 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK,
1778 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK);
1779 }
1780
1781 return 0;
1782 }
1783
1784 static int hisi_sas_v1_init(struct hisi_hba *hisi_hba)
1785 {
1786 int rc;
1787
1788 rc = hw_init_v1_hw(hisi_hba);
1789 if (rc)
1790 return rc;
1791
1792 rc = interrupt_init_v1_hw(hisi_hba);
1793 if (rc)
1794 return rc;
1795
1796 rc = interrupt_openall_v1_hw(hisi_hba);
1797 if (rc)
1798 return rc;
1799
1800 return 0;
1801 }
1802
1803 static const struct hisi_sas_hw hisi_sas_v1_hw = {
1804 .hw_init = hisi_sas_v1_init,
1805 .setup_itct = setup_itct_v1_hw,
1806 .sl_notify = sl_notify_v1_hw,
1807 .clear_itct = clear_itct_v1_hw,
1808 .prep_smp = prep_smp_v1_hw,
1809 .prep_ssp = prep_ssp_v1_hw,
1810 .get_free_slot = get_free_slot_v1_hw,
1811 .start_delivery = start_delivery_v1_hw,
1812 .slot_complete = slot_complete_v1_hw,
1813 .phys_init = phys_init_v1_hw,
1814 .phy_start = start_phy_v1_hw,
1815 .phy_disable = disable_phy_v1_hw,
1816 .phy_hard_reset = phy_hard_reset_v1_hw,
1817 .phy_set_linkrate = phy_set_linkrate_v1_hw,
1818 .phy_get_max_linkrate = phy_get_max_linkrate_v1_hw,
1819 .get_wideport_bitmap = get_wideport_bitmap_v1_hw,
1820 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V1_HW,
1821 .complete_hdr_size = sizeof(struct hisi_sas_complete_v1_hdr),
1822 };
1823
1824 static int hisi_sas_v1_probe(struct platform_device *pdev)
1825 {
1826 return hisi_sas_probe(pdev, &hisi_sas_v1_hw);
1827 }
1828
1829 static int hisi_sas_v1_remove(struct platform_device *pdev)
1830 {
1831 return hisi_sas_remove(pdev);
1832 }
1833
1834 static const struct of_device_id sas_v1_of_match[] = {
1835 { .compatible = "hisilicon,hip05-sas-v1",},
1836 {},
1837 };
1838 MODULE_DEVICE_TABLE(of, sas_v1_of_match);
1839
1840 static const struct acpi_device_id sas_v1_acpi_match[] = {
1841 { "HISI0161", 0 },
1842 { }
1843 };
1844
1845 MODULE_DEVICE_TABLE(acpi, sas_v1_acpi_match);
1846
1847 static struct platform_driver hisi_sas_v1_driver = {
1848 .probe = hisi_sas_v1_probe,
1849 .remove = hisi_sas_v1_remove,
1850 .driver = {
1851 .name = DRV_NAME,
1852 .of_match_table = sas_v1_of_match,
1853 .acpi_match_table = ACPI_PTR(sas_v1_acpi_match),
1854 },
1855 };
1856
1857 module_platform_driver(hisi_sas_v1_driver);
1858
1859 MODULE_LICENSE("GPL");
1860 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
1861 MODULE_DESCRIPTION("HISILICON SAS controller v1 hw driver");
1862 MODULE_ALIAS("platform:" DRV_NAME);
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