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[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
1 /*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12 #include "hisi_sas.h"
13 #define DRV_NAME "hisi_sas_v2_hw"
14
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
34 #define ITCT_CLR 0x44
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
148 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
149 #define DLVRY_Q_0_DEPTH 0x268
150 #define DLVRY_Q_0_WR_PTR 0x26c
151 #define DLVRY_Q_0_RD_PTR 0x270
152 #define HYPER_STREAM_ID_EN_CFG 0xc80
153 #define OQ0_INT_SRC_MSK 0xc90
154 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
155 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
156 #define COMPL_Q_0_DEPTH 0x4e8
157 #define COMPL_Q_0_WR_PTR 0x4ec
158 #define COMPL_Q_0_RD_PTR 0x4f0
159 #define HGC_RXM_DFX_STATUS14 0xae8
160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
162 HGC_RXM_DFX_STATUS14_MEM0_OFF)
163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM1_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM2_OFF)
169 #define HGC_RXM_DFX_STATUS15 0xaec
170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
172 HGC_RXM_DFX_STATUS15_MEM3_OFF)
173 /* phy registers need init */
174 #define PORT_BASE (0x2000)
175
176 #define PHY_CFG (PORT_BASE + 0x0)
177 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PHY_CFG_ENA_OFF 0
179 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
180 #define PHY_CFG_DC_OPT_OFF 2
181 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
182 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
183 #define PROG_PHY_LINK_RATE_MAX_OFF 0
184 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
185 #define PHY_CTRL (PORT_BASE + 0x14)
186 #define PHY_CTRL_RESET_OFF 0
187 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
188 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
189 #define SL_CFG (PORT_BASE + 0x84)
190 #define PHY_PCN (PORT_BASE + 0x44)
191 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
192 #define SL_CONTROL (PORT_BASE + 0x94)
193 #define SL_CONTROL_NOTIFY_EN_OFF 0
194 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
195 #define SL_CONTROL_CTA_OFF 17
196 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
197 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
198 #define RX_BCAST_CHG_OFF 1
199 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
200 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
201 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
202 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
203 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
204 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
205 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
206 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
207 #define TXID_AUTO (PORT_BASE + 0xb8)
208 #define TXID_AUTO_CT3_OFF 1
209 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
210 #define TXID_AUTO_CTB_OFF 11
211 #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
212 #define TX_HARDRST_OFF 2
213 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
214 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
215 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
216 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
217 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
218 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
219 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
220 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
221 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
222 #define CON_CONTROL (PORT_BASE + 0x118)
223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
225 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
226 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
227 #define CHL_INT0 (PORT_BASE + 0x1b4)
228 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
229 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
230 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
231 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
232 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
233 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
234 #define CHL_INT0_NOT_RDY_OFF 4
235 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
236 #define CHL_INT0_PHY_RDY_OFF 5
237 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
238 #define CHL_INT1 (PORT_BASE + 0x1b8)
239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
243 #define CHL_INT2 (PORT_BASE + 0x1bc)
244 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
245 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
246 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
247 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
248 #define DMA_TX_DFX0 (PORT_BASE + 0x200)
249 #define DMA_TX_DFX1 (PORT_BASE + 0x204)
250 #define DMA_TX_DFX1_IPTT_OFF 0
251 #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
252 #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
253 #define PORT_DFX0 (PORT_BASE + 0x258)
254 #define LINK_DFX2 (PORT_BASE + 0X264)
255 #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
256 #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
257 #define LINK_DFX2_SEND_HOLD_STS_OFF 10
258 #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
259 #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
260 #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
261 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
262 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
263 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
264 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
265 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
266 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
267 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
268 #define DMA_TX_STATUS_BUSY_OFF 0
269 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
270 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
271 #define DMA_RX_STATUS_BUSY_OFF 0
272 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
273
274 #define AXI_CFG (0x5100)
275 #define AM_CFG_MAX_TRANS (0x5010)
276 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
277
278 #define AXI_MASTER_CFG_BASE (0x5000)
279 #define AM_CTRL_GLOBAL (0x0)
280 #define AM_CURR_TRANS_RETURN (0x150)
281
282 /* HW dma structures */
283 /* Delivery queue header */
284 /* dw0 */
285 #define CMD_HDR_ABORT_FLAG_OFF 0
286 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
287 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
288 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
289 #define CMD_HDR_RESP_REPORT_OFF 5
290 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
291 #define CMD_HDR_TLR_CTRL_OFF 6
292 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
293 #define CMD_HDR_PORT_OFF 18
294 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
295 #define CMD_HDR_PRIORITY_OFF 27
296 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
297 #define CMD_HDR_CMD_OFF 29
298 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
299 /* dw1 */
300 #define CMD_HDR_DIR_OFF 5
301 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
302 #define CMD_HDR_RESET_OFF 7
303 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
304 #define CMD_HDR_VDTL_OFF 10
305 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
306 #define CMD_HDR_FRAME_TYPE_OFF 11
307 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
308 #define CMD_HDR_DEV_ID_OFF 16
309 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
310 /* dw2 */
311 #define CMD_HDR_CFL_OFF 0
312 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
313 #define CMD_HDR_NCQ_TAG_OFF 10
314 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
315 #define CMD_HDR_MRFL_OFF 15
316 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
317 #define CMD_HDR_SG_MOD_OFF 24
318 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
319 #define CMD_HDR_FIRST_BURST_OFF 26
320 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
321 /* dw3 */
322 #define CMD_HDR_IPTT_OFF 0
323 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
324 /* dw6 */
325 #define CMD_HDR_DIF_SGL_LEN_OFF 0
326 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
327 #define CMD_HDR_DATA_SGL_LEN_OFF 16
328 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
329 #define CMD_HDR_ABORT_IPTT_OFF 16
330 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
331
332 /* Completion header */
333 /* dw0 */
334 #define CMPLT_HDR_ERR_PHASE_OFF 2
335 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
336 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
337 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
338 #define CMPLT_HDR_ERX_OFF 12
339 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
340 #define CMPLT_HDR_ABORT_STAT_OFF 13
341 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
342 /* abort_stat */
343 #define STAT_IO_NOT_VALID 0x1
344 #define STAT_IO_NO_DEVICE 0x2
345 #define STAT_IO_COMPLETE 0x3
346 #define STAT_IO_ABORTED 0x4
347 /* dw1 */
348 #define CMPLT_HDR_IPTT_OFF 0
349 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
350 #define CMPLT_HDR_DEV_ID_OFF 16
351 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
352
353 /* ITCT header */
354 /* qw0 */
355 #define ITCT_HDR_DEV_TYPE_OFF 0
356 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
357 #define ITCT_HDR_VALID_OFF 2
358 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
359 #define ITCT_HDR_MCR_OFF 5
360 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
361 #define ITCT_HDR_VLN_OFF 9
362 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
363 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
364 #define ITCT_HDR_SMP_TIMEOUT_8US 1
365 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
366 250) /* 2ms */
367 #define ITCT_HDR_AWT_CONTINUE_OFF 25
368 #define ITCT_HDR_PORT_ID_OFF 28
369 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
370 /* qw2 */
371 #define ITCT_HDR_INLT_OFF 0
372 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
373 #define ITCT_HDR_BITLT_OFF 16
374 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
375 #define ITCT_HDR_MCTLT_OFF 32
376 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
377 #define ITCT_HDR_RTOLT_OFF 48
378 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
379
380 #define HISI_SAS_FATAL_INT_NR 2
381
382 struct hisi_sas_complete_v2_hdr {
383 __le32 dw0;
384 __le32 dw1;
385 __le32 act;
386 __le32 dw3;
387 };
388
389 struct hisi_sas_err_record_v2 {
390 /* dw0 */
391 __le32 trans_tx_fail_type;
392
393 /* dw1 */
394 __le32 trans_rx_fail_type;
395
396 /* dw2 */
397 __le16 dma_tx_err_type;
398 __le16 sipc_rx_err_type;
399
400 /* dw3 */
401 __le32 dma_rx_err_type;
402 };
403
404 enum {
405 HISI_SAS_PHY_PHY_UPDOWN,
406 HISI_SAS_PHY_CHNL_INT,
407 HISI_SAS_PHY_INT_NR
408 };
409
410 enum {
411 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
412 TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
413 DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
414 SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
415 DMA_RX_ERR_BASE = 0x60, /* dw3 */
416
417 /* trans tx*/
418 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
419 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
420 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
421 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
422 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
423 RESERVED0, /* 0x5 */
424 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
425 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
426 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
427 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
428 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
429 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
430 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
431 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
432 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
433 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
434 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
435 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
436 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
437 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
438 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
439 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
440 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
441 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
442 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
443 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
444 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
445 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
446 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
447 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
448 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
449 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
450 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
451 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
452 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
453
454 /* trans rx */
455 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
456 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
457 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
458 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
459 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
460 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
461 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
462 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
463 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
464 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
465 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
466 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
467 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
468 RESERVED1, /* 0x2b */
469 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
470 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
471 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
472 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
473 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
474 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
475 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
476 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
477 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
478 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
479 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
480 RESERVED2, /* 0x34 */
481 RESERVED3, /* 0x35 */
482 RESERVED4, /* 0x36 */
483 RESERVED5, /* 0x37 */
484 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
485 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
486 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
487 RESERVED6, /* 0x3b */
488 RESERVED7, /* 0x3c */
489 RESERVED8, /* 0x3d */
490 RESERVED9, /* 0x3e */
491 TRANS_RX_R_ERR, /* 0x3f */
492
493 /* dma tx */
494 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
495 DMA_TX_DIF_APP_ERR, /* 0x41 */
496 DMA_TX_DIF_RPP_ERR, /* 0x42 */
497 DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
498 DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
499 DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
500 DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
501 DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
502 DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
503 DMA_TX_RAM_ECC_ERR, /* 0x49 */
504 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
505 DMA_TX_MAX_ERR_CODE,
506
507 /* sipc rx */
508 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
509 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
510 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
511 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
512 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
513 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
514 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
515 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
516 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
517 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
518 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
519 SIPC_RX_MAX_ERR_CODE,
520
521 /* dma rx */
522 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
523 DMA_RX_DIF_APP_ERR, /* 0x61 */
524 DMA_RX_DIF_RPP_ERR, /* 0x62 */
525 DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
526 DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
527 DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
528 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
529 DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
530 RESERVED10, /* 0x68 */
531 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
532 DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
533 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
534 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
535 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
536 DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
537 DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
538 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
539 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
540 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
541 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
542 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
543 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
544 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
545 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
546 DMA_RX_RAM_ECC_ERR, /* 0x78 */
547 DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
548 DMA_RX_MAX_ERR_CODE,
549 };
550
551 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
552 #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
553
554 #define DIR_NO_DATA 0
555 #define DIR_TO_INI 1
556 #define DIR_TO_DEVICE 2
557 #define DIR_RESERVED 3
558
559 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
560 err_phase == 0x4 || err_phase == 0x8 ||\
561 err_phase == 0x6 || err_phase == 0xa)
562 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
563 err_phase == 0x20 || err_phase == 0x40)
564
565 static void link_timeout_disable_link(unsigned long data);
566
567 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
568 {
569 void __iomem *regs = hisi_hba->regs + off;
570
571 return readl(regs);
572 }
573
574 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
575 {
576 void __iomem *regs = hisi_hba->regs + off;
577
578 return readl_relaxed(regs);
579 }
580
581 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
582 {
583 void __iomem *regs = hisi_hba->regs + off;
584
585 writel(val, regs);
586 }
587
588 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
589 u32 off, u32 val)
590 {
591 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
592
593 writel(val, regs);
594 }
595
596 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
597 int phy_no, u32 off)
598 {
599 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
600
601 return readl(regs);
602 }
603
604 /* This function needs to be protected from pre-emption. */
605 static int
606 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
607 struct domain_device *device)
608 {
609 int sata_dev = dev_is_sata(device);
610 void *bitmap = hisi_hba->slot_index_tags;
611 struct hisi_sas_device *sas_dev = device->lldd_dev;
612 int sata_idx = sas_dev->sata_idx;
613 int start, end;
614
615 if (!sata_dev) {
616 /*
617 * STP link SoC bug workaround: index starts from 1.
618 * additionally, we can only allocate odd IPTT(1~4095)
619 * for SAS/SMP device.
620 */
621 start = 1;
622 end = hisi_hba->slot_index_count;
623 } else {
624 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
625 return -EINVAL;
626
627 /*
628 * For SATA device: allocate even IPTT in this interval
629 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
630 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
631 * SoC bug workaround. So we ignore the first 32 even IPTTs.
632 */
633 start = 64 * (sata_idx + 1);
634 end = 64 * (sata_idx + 2);
635 }
636
637 while (1) {
638 start = find_next_zero_bit(bitmap,
639 hisi_hba->slot_index_count, start);
640 if (start >= end)
641 return -SAS_QUEUE_FULL;
642 /*
643 * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
644 */
645 if (sata_dev ^ (start & 1))
646 break;
647 start++;
648 }
649
650 set_bit(start, bitmap);
651 *slot_idx = start;
652 return 0;
653 }
654
655 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
656 {
657 unsigned int index;
658 struct device *dev = hisi_hba->dev;
659 void *bitmap = hisi_hba->sata_dev_bitmap;
660
661 index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
662 if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
663 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
664 return false;
665 }
666
667 set_bit(index, bitmap);
668 *idx = index;
669 return true;
670 }
671
672
673 static struct
674 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
675 {
676 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
677 struct hisi_sas_device *sas_dev = NULL;
678 int i, sata_dev = dev_is_sata(device);
679 int sata_idx = -1;
680
681 spin_lock(&hisi_hba->lock);
682
683 if (sata_dev)
684 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
685 goto out;
686
687 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
688 /*
689 * SATA device id bit0 should be 0
690 */
691 if (sata_dev && (i & 1))
692 continue;
693 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
694 int queue = i % hisi_hba->queue_count;
695 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
696
697 hisi_hba->devices[i].device_id = i;
698 sas_dev = &hisi_hba->devices[i];
699 sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
700 sas_dev->dev_type = device->dev_type;
701 sas_dev->hisi_hba = hisi_hba;
702 sas_dev->sas_device = device;
703 sas_dev->sata_idx = sata_idx;
704 sas_dev->dq = dq;
705 INIT_LIST_HEAD(&hisi_hba->devices[i].list);
706 break;
707 }
708 }
709
710 out:
711 spin_unlock(&hisi_hba->lock);
712
713 return sas_dev;
714 }
715
716 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
717 {
718 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
719
720 cfg &= ~PHY_CFG_DC_OPT_MSK;
721 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
722 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
723 }
724
725 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
726 {
727 struct sas_identify_frame identify_frame;
728 u32 *identify_buffer;
729
730 memset(&identify_frame, 0, sizeof(identify_frame));
731 identify_frame.dev_type = SAS_END_DEVICE;
732 identify_frame.frame_type = 0;
733 identify_frame._un1 = 1;
734 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
735 identify_frame.target_bits = SAS_PROTOCOL_NONE;
736 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
737 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
738 identify_frame.phy_id = phy_no;
739 identify_buffer = (u32 *)(&identify_frame);
740
741 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
742 __swab32(identify_buffer[0]));
743 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
744 __swab32(identify_buffer[1]));
745 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
746 __swab32(identify_buffer[2]));
747 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
748 __swab32(identify_buffer[3]));
749 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
750 __swab32(identify_buffer[4]));
751 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
752 __swab32(identify_buffer[5]));
753 }
754
755 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
756 struct hisi_sas_device *sas_dev)
757 {
758 struct domain_device *device = sas_dev->sas_device;
759 struct device *dev = hisi_hba->dev;
760 u64 qw0, device_id = sas_dev->device_id;
761 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
762 struct domain_device *parent_dev = device->parent;
763 struct asd_sas_port *sas_port = device->port;
764 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
765
766 memset(itct, 0, sizeof(*itct));
767
768 /* qw0 */
769 qw0 = 0;
770 switch (sas_dev->dev_type) {
771 case SAS_END_DEVICE:
772 case SAS_EDGE_EXPANDER_DEVICE:
773 case SAS_FANOUT_EXPANDER_DEVICE:
774 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
775 break;
776 case SAS_SATA_DEV:
777 case SAS_SATA_PENDING:
778 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
779 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
780 else
781 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
782 break;
783 default:
784 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
785 sas_dev->dev_type);
786 }
787
788 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
789 (device->linkrate << ITCT_HDR_MCR_OFF) |
790 (1 << ITCT_HDR_VLN_OFF) |
791 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
792 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
793 (port->id << ITCT_HDR_PORT_ID_OFF));
794 itct->qw0 = cpu_to_le64(qw0);
795
796 /* qw1 */
797 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
798 itct->sas_addr = __swab64(itct->sas_addr);
799
800 /* qw2 */
801 if (!dev_is_sata(device))
802 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
803 (0x1ULL << ITCT_HDR_BITLT_OFF) |
804 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
805 (0x1ULL << ITCT_HDR_RTOLT_OFF));
806 }
807
808 static void free_device_v2_hw(struct hisi_hba *hisi_hba,
809 struct hisi_sas_device *sas_dev)
810 {
811 DECLARE_COMPLETION_ONSTACK(completion);
812 u64 dev_id = sas_dev->device_id;
813 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
814 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
815 int i;
816
817 sas_dev->completion = &completion;
818
819 /* SoC bug workaround */
820 if (dev_is_sata(sas_dev->sas_device))
821 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
822
823 /* clear the itct interrupt state */
824 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
825 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
826 ENT_INT_SRC3_ITC_INT_MSK);
827
828 for (i = 0; i < 2; i++) {
829 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
830 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
831 wait_for_completion(sas_dev->completion);
832
833 memset(itct, 0, sizeof(struct hisi_sas_itct));
834 }
835 }
836
837 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
838 {
839 int i, reset_val;
840 u32 val;
841 unsigned long end_time;
842 struct device *dev = hisi_hba->dev;
843
844 /* The mask needs to be set depending on the number of phys */
845 if (hisi_hba->n_phy == 9)
846 reset_val = 0x1fffff;
847 else
848 reset_val = 0x7ffff;
849
850 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
851
852 /* Disable all of the PHYs */
853 for (i = 0; i < hisi_hba->n_phy; i++) {
854 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
855
856 phy_cfg &= ~PHY_CTRL_RESET_MSK;
857 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
858 }
859 udelay(50);
860
861 /* Ensure DMA tx & rx idle */
862 for (i = 0; i < hisi_hba->n_phy; i++) {
863 u32 dma_tx_status, dma_rx_status;
864
865 end_time = jiffies + msecs_to_jiffies(1000);
866
867 while (1) {
868 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
869 DMA_TX_STATUS);
870 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
871 DMA_RX_STATUS);
872
873 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
874 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
875 break;
876
877 msleep(20);
878 if (time_after(jiffies, end_time))
879 return -EIO;
880 }
881 }
882
883 /* Ensure axi bus idle */
884 end_time = jiffies + msecs_to_jiffies(1000);
885 while (1) {
886 u32 axi_status =
887 hisi_sas_read32(hisi_hba, AXI_CFG);
888
889 if (axi_status == 0)
890 break;
891
892 msleep(20);
893 if (time_after(jiffies, end_time))
894 return -EIO;
895 }
896
897 if (ACPI_HANDLE(dev)) {
898 acpi_status s;
899
900 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
901 if (ACPI_FAILURE(s)) {
902 dev_err(dev, "Reset failed\n");
903 return -EIO;
904 }
905 } else if (hisi_hba->ctrl) {
906 /* reset and disable clock*/
907 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
908 reset_val);
909 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
910 reset_val);
911 msleep(1);
912 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
913 if (reset_val != (val & reset_val)) {
914 dev_err(dev, "SAS reset fail.\n");
915 return -EIO;
916 }
917
918 /* De-reset and enable clock*/
919 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
920 reset_val);
921 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
922 reset_val);
923 msleep(1);
924 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
925 &val);
926 if (val & reset_val) {
927 dev_err(dev, "SAS de-reset fail.\n");
928 return -EIO;
929 }
930 } else
931 dev_warn(dev, "no reset method\n");
932
933 return 0;
934 }
935
936 /* This function needs to be called after resetting SAS controller. */
937 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
938 {
939 u32 cfg;
940 int phy_no;
941
942 hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
943 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
944 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
945 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
946 continue;
947
948 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
949 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
950 }
951 }
952
953 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
954 {
955 int phy_no;
956 u32 dma_tx_dfx1;
957
958 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
959 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
960 continue;
961
962 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
963 DMA_TX_DFX1);
964 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
965 u32 cfg = hisi_sas_phy_read32(hisi_hba,
966 phy_no, CON_CONTROL);
967
968 cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
969 hisi_sas_phy_write32(hisi_hba, phy_no,
970 CON_CONTROL, cfg);
971 clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
972 }
973 }
974 }
975
976 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
977 {
978 struct device *dev = hisi_hba->dev;
979 int i;
980
981 /* Global registers init */
982
983 /* Deal with am-max-transmissions quirk */
984 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
985 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
986 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
987 0x2020);
988 } /* Else, use defaults -> do nothing */
989
990 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
991 (u32)((1ULL << hisi_hba->queue_count) - 1));
992 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
993 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
994 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
995 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
996 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
997 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
998 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
999 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1000 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1001 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1002 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1003 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1004 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1005 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1006 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1007 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1008 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1009 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1010 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1011 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1012 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1013 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1014 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1015 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1016 for (i = 0; i < hisi_hba->queue_count; i++)
1017 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1018
1019 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1020 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1021
1022 for (i = 0; i < hisi_hba->n_phy; i++) {
1023 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
1024 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
1025 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1026 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1027 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1028 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1029 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1030 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1031 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1032 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1033 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1034 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
1035 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1036 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1037 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1038 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1039 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1040 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1041 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1042 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1043 if (hisi_hba->refclk_frequency_mhz == 66)
1044 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1045 /* else, do nothing -> leave it how you found it */
1046 }
1047
1048 for (i = 0; i < hisi_hba->queue_count; i++) {
1049 /* Delivery queue */
1050 hisi_sas_write32(hisi_hba,
1051 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1052 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1053
1054 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1055 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1056
1057 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1058 HISI_SAS_QUEUE_SLOTS);
1059
1060 /* Completion queue */
1061 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1062 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1063
1064 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1065 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1066
1067 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1068 HISI_SAS_QUEUE_SLOTS);
1069 }
1070
1071 /* itct */
1072 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1073 lower_32_bits(hisi_hba->itct_dma));
1074
1075 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1076 upper_32_bits(hisi_hba->itct_dma));
1077
1078 /* iost */
1079 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1080 lower_32_bits(hisi_hba->iost_dma));
1081
1082 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1083 upper_32_bits(hisi_hba->iost_dma));
1084
1085 /* breakpoint */
1086 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1087 lower_32_bits(hisi_hba->breakpoint_dma));
1088
1089 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1090 upper_32_bits(hisi_hba->breakpoint_dma));
1091
1092 /* SATA broken msg */
1093 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1094 lower_32_bits(hisi_hba->sata_breakpoint_dma));
1095
1096 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1097 upper_32_bits(hisi_hba->sata_breakpoint_dma));
1098
1099 /* SATA initial fis */
1100 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1101 lower_32_bits(hisi_hba->initial_fis_dma));
1102
1103 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1104 upper_32_bits(hisi_hba->initial_fis_dma));
1105 }
1106
1107 static void link_timeout_enable_link(unsigned long data)
1108 {
1109 struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
1110 int i, reg_val;
1111
1112 for (i = 0; i < hisi_hba->n_phy; i++) {
1113 if (hisi_hba->reject_stp_links_msk & BIT(i))
1114 continue;
1115
1116 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1117 if (!(reg_val & BIT(0))) {
1118 hisi_sas_phy_write32(hisi_hba, i,
1119 CON_CONTROL, 0x7);
1120 break;
1121 }
1122 }
1123
1124 hisi_hba->timer.function = link_timeout_disable_link;
1125 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1126 }
1127
1128 static void link_timeout_disable_link(unsigned long data)
1129 {
1130 struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
1131 int i, reg_val;
1132
1133 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1134 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1135 if (hisi_hba->reject_stp_links_msk & BIT(i))
1136 continue;
1137
1138 if (reg_val & BIT(i)) {
1139 hisi_sas_phy_write32(hisi_hba, i,
1140 CON_CONTROL, 0x6);
1141 break;
1142 }
1143 }
1144
1145 hisi_hba->timer.function = link_timeout_enable_link;
1146 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1147 }
1148
1149 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1150 {
1151 hisi_hba->timer.data = (unsigned long)hisi_hba;
1152 hisi_hba->timer.function = link_timeout_disable_link;
1153 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1154 add_timer(&hisi_hba->timer);
1155 }
1156
1157 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1158 {
1159 struct device *dev = hisi_hba->dev;
1160 int rc;
1161
1162 rc = reset_hw_v2_hw(hisi_hba);
1163 if (rc) {
1164 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1165 return rc;
1166 }
1167
1168 msleep(100);
1169 init_reg_v2_hw(hisi_hba);
1170
1171 return 0;
1172 }
1173
1174 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1175 {
1176 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1177
1178 cfg |= PHY_CFG_ENA_MSK;
1179 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1180 }
1181
1182 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1183 {
1184 u32 context;
1185
1186 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1187 if (context & (1 << phy_no))
1188 return true;
1189
1190 return false;
1191 }
1192
1193 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1194 {
1195 u32 dfx_val;
1196
1197 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1198
1199 if (dfx_val & BIT(16))
1200 return false;
1201
1202 return true;
1203 }
1204
1205 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1206 {
1207 int i, max_loop = 1000;
1208 struct device *dev = hisi_hba->dev;
1209 u32 status, axi_status, dfx_val, dfx_tx_val;
1210
1211 for (i = 0; i < max_loop; i++) {
1212 status = hisi_sas_read32_relaxed(hisi_hba,
1213 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1214
1215 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1216 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1217 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1218 phy_no, DMA_TX_FIFO_DFX0);
1219
1220 if ((status == 0x3) && (axi_status == 0x0) &&
1221 (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1222 return true;
1223 udelay(10);
1224 }
1225 dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1226 phy_no, status, axi_status,
1227 dfx_val, dfx_tx_val);
1228 return false;
1229 }
1230
1231 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1232 {
1233 int i, max_loop = 1000;
1234 struct device *dev = hisi_hba->dev;
1235 u32 status, tx_dfx0;
1236
1237 for (i = 0; i < max_loop; i++) {
1238 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1239 status = (status & 0x3fc0) >> 6;
1240
1241 if (status != 0x1)
1242 return true;
1243
1244 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1245 if ((tx_dfx0 & 0x1ff) == 0x2)
1246 return true;
1247 udelay(10);
1248 }
1249 dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1250 phy_no, status, tx_dfx0);
1251 return false;
1252 }
1253
1254 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1255 {
1256 if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1257 return true;
1258
1259 if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1260 return false;
1261
1262 if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1263 return false;
1264
1265 return true;
1266 }
1267
1268
1269 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1270 {
1271 u32 cfg, axi_val, dfx0_val, txid_auto;
1272 struct device *dev = hisi_hba->dev;
1273
1274 /* Close axi bus. */
1275 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1276 AM_CTRL_GLOBAL);
1277 axi_val |= 0x1;
1278 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1279 AM_CTRL_GLOBAL, axi_val);
1280
1281 if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1282 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1283 goto do_disable;
1284
1285 /* Reset host controller. */
1286 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1287 return;
1288 }
1289
1290 dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1291 dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1292 if (dfx0_val != 0x4)
1293 goto do_disable;
1294
1295 if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1296 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1297 phy_no);
1298 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1299 TXID_AUTO);
1300 txid_auto |= TXID_AUTO_CTB_MSK;
1301 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1302 txid_auto);
1303 }
1304
1305 do_disable:
1306 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1307 cfg &= ~PHY_CFG_ENA_MSK;
1308 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1309
1310 /* Open axi bus. */
1311 axi_val &= ~0x1;
1312 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1313 AM_CTRL_GLOBAL, axi_val);
1314 }
1315
1316 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1317 {
1318 config_id_frame_v2_hw(hisi_hba, phy_no);
1319 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1320 enable_phy_v2_hw(hisi_hba, phy_no);
1321 }
1322
1323 static void stop_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1324 {
1325 disable_phy_v2_hw(hisi_hba, phy_no);
1326 }
1327
1328 static void stop_phys_v2_hw(struct hisi_hba *hisi_hba)
1329 {
1330 int i;
1331
1332 for (i = 0; i < hisi_hba->n_phy; i++)
1333 stop_phy_v2_hw(hisi_hba, i);
1334 }
1335
1336 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1337 {
1338 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1339 u32 txid_auto;
1340
1341 stop_phy_v2_hw(hisi_hba, phy_no);
1342 if (phy->identify.device_type == SAS_END_DEVICE) {
1343 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1344 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1345 txid_auto | TX_HARDRST_MSK);
1346 }
1347 msleep(100);
1348 start_phy_v2_hw(hisi_hba, phy_no);
1349 }
1350
1351 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1352 {
1353 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1354 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1355 struct sas_phy *sphy = sas_phy->phy;
1356 u32 err4_reg_val, err6_reg_val;
1357
1358 /* loss dword syn, phy reset problem */
1359 err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1360
1361 /* disparity err, invalid dword */
1362 err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1363
1364 sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1365 sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1366 sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1367 sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1368 }
1369
1370 static void start_phys_v2_hw(struct hisi_hba *hisi_hba)
1371 {
1372 int i;
1373
1374 for (i = 0; i < hisi_hba->n_phy; i++) {
1375 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1376 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1377
1378 if (!sas_phy->phy->enabled)
1379 continue;
1380
1381 start_phy_v2_hw(hisi_hba, i);
1382 }
1383 }
1384
1385 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1386 {
1387 start_phys_v2_hw(hisi_hba);
1388 }
1389
1390 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1391 {
1392 u32 sl_control;
1393
1394 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1395 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1396 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1397 msleep(1);
1398 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1399 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1400 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1401 }
1402
1403 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1404 {
1405 return SAS_LINK_RATE_12_0_GBPS;
1406 }
1407
1408 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1409 struct sas_phy_linkrates *r)
1410 {
1411 u32 prog_phy_link_rate =
1412 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1413 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1414 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1415 int i;
1416 enum sas_linkrate min, max;
1417 u32 rate_mask = 0;
1418
1419 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1420 max = sas_phy->phy->maximum_linkrate;
1421 min = r->minimum_linkrate;
1422 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1423 max = r->maximum_linkrate;
1424 min = sas_phy->phy->minimum_linkrate;
1425 } else
1426 return;
1427
1428 sas_phy->phy->maximum_linkrate = max;
1429 sas_phy->phy->minimum_linkrate = min;
1430
1431 min -= SAS_LINK_RATE_1_5_GBPS;
1432 max -= SAS_LINK_RATE_1_5_GBPS;
1433
1434 for (i = 0; i <= max; i++)
1435 rate_mask |= 1 << (i * 2);
1436
1437 prog_phy_link_rate &= ~0xff;
1438 prog_phy_link_rate |= rate_mask;
1439
1440 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1441 prog_phy_link_rate);
1442
1443 phy_hard_reset_v2_hw(hisi_hba, phy_no);
1444 }
1445
1446 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1447 {
1448 int i, bitmap = 0;
1449 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1450 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1451
1452 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1453 if (phy_state & 1 << i)
1454 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1455 bitmap |= 1 << i;
1456
1457 if (hisi_hba->n_phy == 9) {
1458 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1459
1460 if (phy_state & 1 << 8)
1461 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1462 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1463 bitmap |= 1 << 9;
1464 }
1465
1466 return bitmap;
1467 }
1468
1469 /*
1470 * The callpath to this function and upto writing the write
1471 * queue pointer should be safe from interruption.
1472 */
1473 static int
1474 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1475 {
1476 struct device *dev = hisi_hba->dev;
1477 int queue = dq->id;
1478 u32 r, w;
1479
1480 w = dq->wr_point;
1481 r = hisi_sas_read32_relaxed(hisi_hba,
1482 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1483 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1484 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
1485 queue, r, w);
1486 return -EAGAIN;
1487 }
1488
1489 return 0;
1490 }
1491
1492 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1493 {
1494 struct hisi_hba *hisi_hba = dq->hisi_hba;
1495 int dlvry_queue = dq->slot_prep->dlvry_queue;
1496 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
1497
1498 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1499 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1500 dq->wr_point);
1501 }
1502
1503 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1504 struct hisi_sas_slot *slot,
1505 struct hisi_sas_cmd_hdr *hdr,
1506 struct scatterlist *scatter,
1507 int n_elem)
1508 {
1509 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1510 struct device *dev = hisi_hba->dev;
1511 struct scatterlist *sg;
1512 int i;
1513
1514 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1515 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1516 n_elem);
1517 return -EINVAL;
1518 }
1519
1520 for_each_sg(scatter, sg, n_elem, i) {
1521 struct hisi_sas_sge *entry = &sge_page->sge[i];
1522
1523 entry->addr = cpu_to_le64(sg_dma_address(sg));
1524 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1525 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1526 entry->data_off = 0;
1527 }
1528
1529 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1530
1531 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1532
1533 return 0;
1534 }
1535
1536 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1537 struct hisi_sas_slot *slot)
1538 {
1539 struct sas_task *task = slot->task;
1540 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1541 struct domain_device *device = task->dev;
1542 struct device *dev = hisi_hba->dev;
1543 struct hisi_sas_port *port = slot->port;
1544 struct scatterlist *sg_req, *sg_resp;
1545 struct hisi_sas_device *sas_dev = device->lldd_dev;
1546 dma_addr_t req_dma_addr;
1547 unsigned int req_len, resp_len;
1548 int elem, rc;
1549
1550 /*
1551 * DMA-map SMP request, response buffers
1552 */
1553 /* req */
1554 sg_req = &task->smp_task.smp_req;
1555 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1556 if (!elem)
1557 return -ENOMEM;
1558 req_len = sg_dma_len(sg_req);
1559 req_dma_addr = sg_dma_address(sg_req);
1560
1561 /* resp */
1562 sg_resp = &task->smp_task.smp_resp;
1563 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1564 if (!elem) {
1565 rc = -ENOMEM;
1566 goto err_out_req;
1567 }
1568 resp_len = sg_dma_len(sg_resp);
1569 if ((req_len & 0x3) || (resp_len & 0x3)) {
1570 rc = -EINVAL;
1571 goto err_out_resp;
1572 }
1573
1574 /* create header */
1575 /* dw0 */
1576 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1577 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1578 (2 << CMD_HDR_CMD_OFF)); /* smp */
1579
1580 /* map itct entry */
1581 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1582 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1583 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1584
1585 /* dw2 */
1586 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1587 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1588 CMD_HDR_MRFL_OFF));
1589
1590 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1591
1592 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1593 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1594
1595 return 0;
1596
1597 err_out_resp:
1598 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1599 DMA_FROM_DEVICE);
1600 err_out_req:
1601 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1602 DMA_TO_DEVICE);
1603 return rc;
1604 }
1605
1606 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1607 struct hisi_sas_slot *slot, int is_tmf,
1608 struct hisi_sas_tmf_task *tmf)
1609 {
1610 struct sas_task *task = slot->task;
1611 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1612 struct domain_device *device = task->dev;
1613 struct hisi_sas_device *sas_dev = device->lldd_dev;
1614 struct hisi_sas_port *port = slot->port;
1615 struct sas_ssp_task *ssp_task = &task->ssp_task;
1616 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1617 int has_data = 0, rc, priority = is_tmf;
1618 u8 *buf_cmd;
1619 u32 dw1 = 0, dw2 = 0;
1620
1621 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1622 (2 << CMD_HDR_TLR_CTRL_OFF) |
1623 (port->id << CMD_HDR_PORT_OFF) |
1624 (priority << CMD_HDR_PRIORITY_OFF) |
1625 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1626
1627 dw1 = 1 << CMD_HDR_VDTL_OFF;
1628 if (is_tmf) {
1629 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1630 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1631 } else {
1632 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1633 switch (scsi_cmnd->sc_data_direction) {
1634 case DMA_TO_DEVICE:
1635 has_data = 1;
1636 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1637 break;
1638 case DMA_FROM_DEVICE:
1639 has_data = 1;
1640 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1641 break;
1642 default:
1643 dw1 &= ~CMD_HDR_DIR_MSK;
1644 }
1645 }
1646
1647 /* map itct entry */
1648 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1649 hdr->dw1 = cpu_to_le32(dw1);
1650
1651 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1652 + 3) / 4) << CMD_HDR_CFL_OFF) |
1653 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1654 (2 << CMD_HDR_SG_MOD_OFF);
1655 hdr->dw2 = cpu_to_le32(dw2);
1656
1657 hdr->transfer_tags = cpu_to_le32(slot->idx);
1658
1659 if (has_data) {
1660 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1661 slot->n_elem);
1662 if (rc)
1663 return rc;
1664 }
1665
1666 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1667 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1668 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1669
1670 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1671 sizeof(struct ssp_frame_hdr);
1672
1673 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1674 if (!is_tmf) {
1675 buf_cmd[9] = task->ssp_task.task_attr |
1676 (task->ssp_task.task_prio << 3);
1677 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1678 task->ssp_task.cmd->cmd_len);
1679 } else {
1680 buf_cmd[10] = tmf->tmf;
1681 switch (tmf->tmf) {
1682 case TMF_ABORT_TASK:
1683 case TMF_QUERY_TASK:
1684 buf_cmd[12] =
1685 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1686 buf_cmd[13] =
1687 tmf->tag_of_task_to_be_managed & 0xff;
1688 break;
1689 default:
1690 break;
1691 }
1692 }
1693
1694 return 0;
1695 }
1696
1697 #define TRANS_TX_ERR 0
1698 #define TRANS_RX_ERR 1
1699 #define DMA_TX_ERR 2
1700 #define SIPC_RX_ERR 3
1701 #define DMA_RX_ERR 4
1702
1703 #define DMA_TX_ERR_OFF 0
1704 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1705 #define SIPC_RX_ERR_OFF 16
1706 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1707
1708 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1709 {
1710 static const u8 trans_tx_err_code_prio[] = {
1711 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1712 TRANS_TX_ERR_PHY_NOT_ENABLE,
1713 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1714 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1715 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1716 RESERVED0,
1717 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1718 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1719 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1720 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1721 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1722 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1723 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1724 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1725 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1726 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1727 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1728 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1729 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1730 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1731 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1732 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1733 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1734 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1735 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1736 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1737 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1738 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1739 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1740 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1741 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1742 };
1743 int index, i;
1744
1745 for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1746 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1747 if (err_msk & (1 << index))
1748 return trans_tx_err_code_prio[i];
1749 }
1750 return -1;
1751 }
1752
1753 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1754 {
1755 static const u8 trans_rx_err_code_prio[] = {
1756 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1757 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1758 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1759 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1760 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1761 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1762 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1763 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1764 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1765 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1766 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1767 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1768 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1769 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1770 RESERVED1,
1771 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1772 TRANS_RX_ERR_WITH_DATA_LEN0,
1773 TRANS_RX_ERR_WITH_BAD_HASH,
1774 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1775 TRANS_RX_SSP_FRM_LEN_ERR,
1776 RESERVED2,
1777 RESERVED3,
1778 RESERVED4,
1779 RESERVED5,
1780 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1781 TRANS_RX_SMP_FRM_LEN_ERR,
1782 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1783 RESERVED6,
1784 RESERVED7,
1785 RESERVED8,
1786 RESERVED9,
1787 TRANS_RX_R_ERR,
1788 };
1789 int index, i;
1790
1791 for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1792 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1793 if (err_msk & (1 << index))
1794 return trans_rx_err_code_prio[i];
1795 }
1796 return -1;
1797 }
1798
1799 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1800 {
1801 static const u8 dma_tx_err_code_prio[] = {
1802 DMA_TX_UNEXP_XFER_ERR,
1803 DMA_TX_UNEXP_RETRANS_ERR,
1804 DMA_TX_XFER_LEN_OVERFLOW,
1805 DMA_TX_XFER_OFFSET_ERR,
1806 DMA_TX_RAM_ECC_ERR,
1807 DMA_TX_DIF_LEN_ALIGN_ERR,
1808 DMA_TX_DIF_CRC_ERR,
1809 DMA_TX_DIF_APP_ERR,
1810 DMA_TX_DIF_RPP_ERR,
1811 DMA_TX_DATA_SGL_OVERFLOW,
1812 DMA_TX_DIF_SGL_OVERFLOW,
1813 };
1814 int index, i;
1815
1816 for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1817 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1818 err_msk = err_msk & DMA_TX_ERR_MSK;
1819 if (err_msk & (1 << index))
1820 return dma_tx_err_code_prio[i];
1821 }
1822 return -1;
1823 }
1824
1825 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1826 {
1827 static const u8 sipc_rx_err_code_prio[] = {
1828 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1829 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1830 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1831 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1832 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1833 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1834 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1835 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1836 SIPC_RX_SATA_UNEXP_FIS_ERR,
1837 SIPC_RX_WRSETUP_ESTATUS_ERR,
1838 SIPC_RX_DATA_UNDERFLOW_ERR,
1839 };
1840 int index, i;
1841
1842 for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1843 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1844 err_msk = err_msk & SIPC_RX_ERR_MSK;
1845 if (err_msk & (1 << (index + 0x10)))
1846 return sipc_rx_err_code_prio[i];
1847 }
1848 return -1;
1849 }
1850
1851 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
1852 {
1853 static const u8 dma_rx_err_code_prio[] = {
1854 DMA_RX_UNKNOWN_FRM_ERR,
1855 DMA_RX_DATA_LEN_OVERFLOW,
1856 DMA_RX_DATA_LEN_UNDERFLOW,
1857 DMA_RX_DATA_OFFSET_ERR,
1858 RESERVED10,
1859 DMA_RX_SATA_FRAME_TYPE_ERR,
1860 DMA_RX_RESP_BUF_OVERFLOW,
1861 DMA_RX_UNEXP_RETRANS_RESP_ERR,
1862 DMA_RX_UNEXP_NORM_RESP_ERR,
1863 DMA_RX_UNEXP_RDFRAME_ERR,
1864 DMA_RX_PIO_DATA_LEN_ERR,
1865 DMA_RX_RDSETUP_STATUS_ERR,
1866 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
1867 DMA_RX_RDSETUP_STATUS_BSY_ERR,
1868 DMA_RX_RDSETUP_LEN_ODD_ERR,
1869 DMA_RX_RDSETUP_LEN_ZERO_ERR,
1870 DMA_RX_RDSETUP_LEN_OVER_ERR,
1871 DMA_RX_RDSETUP_OFFSET_ERR,
1872 DMA_RX_RDSETUP_ACTIVE_ERR,
1873 DMA_RX_RDSETUP_ESTATUS_ERR,
1874 DMA_RX_RAM_ECC_ERR,
1875 DMA_RX_DIF_CRC_ERR,
1876 DMA_RX_DIF_APP_ERR,
1877 DMA_RX_DIF_RPP_ERR,
1878 DMA_RX_DATA_SGL_OVERFLOW,
1879 DMA_RX_DIF_SGL_OVERFLOW,
1880 };
1881 int index, i;
1882
1883 for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
1884 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
1885 if (err_msk & (1 << index))
1886 return dma_rx_err_code_prio[i];
1887 }
1888 return -1;
1889 }
1890
1891 /* by default, task resp is complete */
1892 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
1893 struct sas_task *task,
1894 struct hisi_sas_slot *slot,
1895 int err_phase)
1896 {
1897 struct task_status_struct *ts = &task->task_status;
1898 struct hisi_sas_err_record_v2 *err_record =
1899 hisi_sas_status_buf_addr_mem(slot);
1900 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
1901 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
1902 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
1903 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
1904 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
1905 int error = -1;
1906
1907 if (err_phase == 1) {
1908 /* error in TX phase, the priority of error is: DW2 > DW0 */
1909 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
1910 if (error == -1)
1911 error = parse_trans_tx_err_code_v2_hw(
1912 trans_tx_fail_type);
1913 } else if (err_phase == 2) {
1914 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
1915 error = parse_trans_rx_err_code_v2_hw(
1916 trans_rx_fail_type);
1917 if (error == -1) {
1918 error = parse_dma_rx_err_code_v2_hw(
1919 dma_rx_err_type);
1920 if (error == -1)
1921 error = parse_sipc_rx_err_code_v2_hw(
1922 sipc_rx_err_type);
1923 }
1924 }
1925
1926 switch (task->task_proto) {
1927 case SAS_PROTOCOL_SSP:
1928 {
1929 switch (error) {
1930 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
1931 {
1932 ts->stat = SAS_OPEN_REJECT;
1933 ts->open_rej_reason = SAS_OREJ_NO_DEST;
1934 break;
1935 }
1936 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
1937 {
1938 ts->stat = SAS_OPEN_REJECT;
1939 ts->open_rej_reason = SAS_OREJ_EPROTO;
1940 break;
1941 }
1942 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
1943 {
1944 ts->stat = SAS_OPEN_REJECT;
1945 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1946 break;
1947 }
1948 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
1949 {
1950 ts->stat = SAS_OPEN_REJECT;
1951 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1952 break;
1953 }
1954 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
1955 {
1956 ts->stat = SAS_OPEN_REJECT;
1957 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1958 break;
1959 }
1960 case DMA_RX_UNEXP_NORM_RESP_ERR:
1961 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
1962 case DMA_RX_RESP_BUF_OVERFLOW:
1963 {
1964 ts->stat = SAS_OPEN_REJECT;
1965 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1966 break;
1967 }
1968 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
1969 {
1970 /* not sure */
1971 ts->stat = SAS_DEV_NO_RESPONSE;
1972 break;
1973 }
1974 case DMA_RX_DATA_LEN_OVERFLOW:
1975 {
1976 ts->stat = SAS_DATA_OVERRUN;
1977 ts->residual = 0;
1978 break;
1979 }
1980 case DMA_RX_DATA_LEN_UNDERFLOW:
1981 {
1982 ts->residual = trans_tx_fail_type;
1983 ts->stat = SAS_DATA_UNDERRUN;
1984 break;
1985 }
1986 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
1987 case TRANS_TX_ERR_PHY_NOT_ENABLE:
1988 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
1989 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
1990 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
1991 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
1992 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
1993 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
1994 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
1995 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
1996 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
1997 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
1998 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
1999 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2000 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2001 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2002 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2003 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2004 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2005 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2006 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2007 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2008 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2009 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2010 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2011 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2012 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2013 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2014 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2015 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2016 case TRANS_TX_ERR_FRAME_TXED:
2017 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2018 case TRANS_RX_ERR_WITH_DATA_LEN0:
2019 case TRANS_RX_ERR_WITH_BAD_HASH:
2020 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2021 case TRANS_RX_SSP_FRM_LEN_ERR:
2022 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2023 case DMA_TX_DATA_SGL_OVERFLOW:
2024 case DMA_TX_UNEXP_XFER_ERR:
2025 case DMA_TX_UNEXP_RETRANS_ERR:
2026 case DMA_TX_XFER_LEN_OVERFLOW:
2027 case DMA_TX_XFER_OFFSET_ERR:
2028 case SIPC_RX_DATA_UNDERFLOW_ERR:
2029 case DMA_RX_DATA_SGL_OVERFLOW:
2030 case DMA_RX_DATA_OFFSET_ERR:
2031 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2032 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2033 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2034 case DMA_RX_SATA_FRAME_TYPE_ERR:
2035 case DMA_RX_UNKNOWN_FRM_ERR:
2036 {
2037 /* This will request a retry */
2038 ts->stat = SAS_QUEUE_FULL;
2039 slot->abort = 1;
2040 break;
2041 }
2042 default:
2043 break;
2044 }
2045 }
2046 break;
2047 case SAS_PROTOCOL_SMP:
2048 ts->stat = SAM_STAT_CHECK_CONDITION;
2049 break;
2050
2051 case SAS_PROTOCOL_SATA:
2052 case SAS_PROTOCOL_STP:
2053 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2054 {
2055 switch (error) {
2056 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2057 {
2058 ts->stat = SAS_OPEN_REJECT;
2059 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2060 break;
2061 }
2062 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2063 {
2064 ts->resp = SAS_TASK_UNDELIVERED;
2065 ts->stat = SAS_DEV_NO_RESPONSE;
2066 break;
2067 }
2068 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2069 {
2070 ts->stat = SAS_OPEN_REJECT;
2071 ts->open_rej_reason = SAS_OREJ_EPROTO;
2072 break;
2073 }
2074 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2075 {
2076 ts->stat = SAS_OPEN_REJECT;
2077 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2078 break;
2079 }
2080 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2081 {
2082 ts->stat = SAS_OPEN_REJECT;
2083 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2084 break;
2085 }
2086 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2087 {
2088 ts->stat = SAS_OPEN_REJECT;
2089 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2090 break;
2091 }
2092 case DMA_RX_RESP_BUF_OVERFLOW:
2093 case DMA_RX_UNEXP_NORM_RESP_ERR:
2094 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2095 {
2096 ts->stat = SAS_OPEN_REJECT;
2097 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2098 break;
2099 }
2100 case DMA_RX_DATA_LEN_OVERFLOW:
2101 {
2102 ts->stat = SAS_DATA_OVERRUN;
2103 ts->residual = 0;
2104 break;
2105 }
2106 case DMA_RX_DATA_LEN_UNDERFLOW:
2107 {
2108 ts->residual = trans_tx_fail_type;
2109 ts->stat = SAS_DATA_UNDERRUN;
2110 break;
2111 }
2112 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2113 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2114 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2115 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2116 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2117 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2118 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2119 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2120 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2121 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2122 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2123 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2124 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2125 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2126 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2127 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2128 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2129 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2130 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2131 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2132 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2133 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2134 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2135 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2136 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2137 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2138 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2139 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2140 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2141 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2142 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2143 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2144 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2145 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2146 case TRANS_RX_ERR_WITH_DATA_LEN0:
2147 case TRANS_RX_ERR_WITH_BAD_HASH:
2148 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2149 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2150 case DMA_TX_DATA_SGL_OVERFLOW:
2151 case DMA_TX_UNEXP_XFER_ERR:
2152 case DMA_TX_UNEXP_RETRANS_ERR:
2153 case DMA_TX_XFER_LEN_OVERFLOW:
2154 case DMA_TX_XFER_OFFSET_ERR:
2155 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2156 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2157 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2158 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2159 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2160 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2161 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2162 case DMA_RX_DATA_SGL_OVERFLOW:
2163 case DMA_RX_DATA_OFFSET_ERR:
2164 case DMA_RX_SATA_FRAME_TYPE_ERR:
2165 case DMA_RX_UNEXP_RDFRAME_ERR:
2166 case DMA_RX_PIO_DATA_LEN_ERR:
2167 case DMA_RX_RDSETUP_STATUS_ERR:
2168 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2169 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2170 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2171 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2172 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2173 case DMA_RX_RDSETUP_OFFSET_ERR:
2174 case DMA_RX_RDSETUP_ACTIVE_ERR:
2175 case DMA_RX_RDSETUP_ESTATUS_ERR:
2176 case DMA_RX_UNKNOWN_FRM_ERR:
2177 case TRANS_RX_SSP_FRM_LEN_ERR:
2178 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2179 {
2180 slot->abort = 1;
2181 ts->stat = SAS_PHY_DOWN;
2182 break;
2183 }
2184 default:
2185 {
2186 ts->stat = SAS_PROTO_RESPONSE;
2187 break;
2188 }
2189 }
2190 hisi_sas_sata_done(task, slot);
2191 }
2192 break;
2193 default:
2194 break;
2195 }
2196 }
2197
2198 static int
2199 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2200 {
2201 struct sas_task *task = slot->task;
2202 struct hisi_sas_device *sas_dev;
2203 struct device *dev = hisi_hba->dev;
2204 struct task_status_struct *ts;
2205 struct domain_device *device;
2206 enum exec_status sts;
2207 struct hisi_sas_complete_v2_hdr *complete_queue =
2208 hisi_hba->complete_hdr[slot->cmplt_queue];
2209 struct hisi_sas_complete_v2_hdr *complete_hdr =
2210 &complete_queue[slot->cmplt_queue_slot];
2211 unsigned long flags;
2212 int aborted;
2213
2214 if (unlikely(!task || !task->lldd_task || !task->dev))
2215 return -EINVAL;
2216
2217 ts = &task->task_status;
2218 device = task->dev;
2219 sas_dev = device->lldd_dev;
2220
2221 spin_lock_irqsave(&task->task_state_lock, flags);
2222 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
2223 task->task_state_flags &=
2224 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2225 spin_unlock_irqrestore(&task->task_state_lock, flags);
2226
2227 memset(ts, 0, sizeof(*ts));
2228 ts->resp = SAS_TASK_COMPLETE;
2229
2230 if (unlikely(aborted)) {
2231 ts->stat = SAS_ABORTED_TASK;
2232 hisi_sas_slot_task_free(hisi_hba, task, slot);
2233 return -1;
2234 }
2235
2236 if (unlikely(!sas_dev)) {
2237 dev_dbg(dev, "slot complete: port has no device\n");
2238 ts->stat = SAS_PHY_DOWN;
2239 goto out;
2240 }
2241
2242 /* Use SAS+TMF status codes */
2243 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2244 >> CMPLT_HDR_ABORT_STAT_OFF) {
2245 case STAT_IO_ABORTED:
2246 /* this io has been aborted by abort command */
2247 ts->stat = SAS_ABORTED_TASK;
2248 goto out;
2249 case STAT_IO_COMPLETE:
2250 /* internal abort command complete */
2251 ts->stat = TMF_RESP_FUNC_SUCC;
2252 del_timer(&slot->internal_abort_timer);
2253 goto out;
2254 case STAT_IO_NO_DEVICE:
2255 ts->stat = TMF_RESP_FUNC_COMPLETE;
2256 del_timer(&slot->internal_abort_timer);
2257 goto out;
2258 case STAT_IO_NOT_VALID:
2259 /* abort single io, controller don't find
2260 * the io need to abort
2261 */
2262 ts->stat = TMF_RESP_FUNC_FAILED;
2263 del_timer(&slot->internal_abort_timer);
2264 goto out;
2265 default:
2266 break;
2267 }
2268
2269 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2270 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2271 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2272 >> CMPLT_HDR_ERR_PHASE_OFF;
2273
2274 /* Analyse error happens on which phase TX or RX */
2275 if (ERR_ON_TX_PHASE(err_phase))
2276 slot_err_v2_hw(hisi_hba, task, slot, 1);
2277 else if (ERR_ON_RX_PHASE(err_phase))
2278 slot_err_v2_hw(hisi_hba, task, slot, 2);
2279
2280 if (unlikely(slot->abort))
2281 return ts->stat;
2282 goto out;
2283 }
2284
2285 switch (task->task_proto) {
2286 case SAS_PROTOCOL_SSP:
2287 {
2288 struct hisi_sas_status_buffer *status_buffer =
2289 hisi_sas_status_buf_addr_mem(slot);
2290 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2291 &status_buffer->iu[0];
2292
2293 sas_ssp_task_response(dev, task, iu);
2294 break;
2295 }
2296 case SAS_PROTOCOL_SMP:
2297 {
2298 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2299 void *to;
2300
2301 ts->stat = SAM_STAT_GOOD;
2302 to = kmap_atomic(sg_page(sg_resp));
2303
2304 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2305 DMA_FROM_DEVICE);
2306 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2307 DMA_TO_DEVICE);
2308 memcpy(to + sg_resp->offset,
2309 hisi_sas_status_buf_addr_mem(slot) +
2310 sizeof(struct hisi_sas_err_record),
2311 sg_dma_len(sg_resp));
2312 kunmap_atomic(to);
2313 break;
2314 }
2315 case SAS_PROTOCOL_SATA:
2316 case SAS_PROTOCOL_STP:
2317 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2318 {
2319 ts->stat = SAM_STAT_GOOD;
2320 hisi_sas_sata_done(task, slot);
2321 break;
2322 }
2323 default:
2324 ts->stat = SAM_STAT_CHECK_CONDITION;
2325 break;
2326 }
2327
2328 if (!slot->port->port_attached) {
2329 dev_err(dev, "slot complete: port %d has removed\n",
2330 slot->port->sas_port.id);
2331 ts->stat = SAS_PHY_DOWN;
2332 }
2333
2334 out:
2335 spin_lock_irqsave(&task->task_state_lock, flags);
2336 task->task_state_flags |= SAS_TASK_STATE_DONE;
2337 spin_unlock_irqrestore(&task->task_state_lock, flags);
2338 spin_lock_irqsave(&hisi_hba->lock, flags);
2339 hisi_sas_slot_task_free(hisi_hba, task, slot);
2340 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2341 sts = ts->stat;
2342
2343 if (task->task_done)
2344 task->task_done(task);
2345
2346 return sts;
2347 }
2348
2349 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2350 struct hisi_sas_slot *slot)
2351 {
2352 struct sas_task *task = slot->task;
2353 struct domain_device *device = task->dev;
2354 struct domain_device *parent_dev = device->parent;
2355 struct hisi_sas_device *sas_dev = device->lldd_dev;
2356 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2357 struct asd_sas_port *sas_port = device->port;
2358 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2359 u8 *buf_cmd;
2360 int has_data = 0, rc = 0, hdr_tag = 0;
2361 u32 dw1 = 0, dw2 = 0;
2362
2363 /* create header */
2364 /* dw0 */
2365 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2366 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2367 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2368 else
2369 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2370
2371 /* dw1 */
2372 switch (task->data_dir) {
2373 case DMA_TO_DEVICE:
2374 has_data = 1;
2375 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2376 break;
2377 case DMA_FROM_DEVICE:
2378 has_data = 1;
2379 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2380 break;
2381 default:
2382 dw1 &= ~CMD_HDR_DIR_MSK;
2383 }
2384
2385 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2386 (task->ata_task.fis.control & ATA_SRST))
2387 dw1 |= 1 << CMD_HDR_RESET_OFF;
2388
2389 dw1 |= (hisi_sas_get_ata_protocol(
2390 task->ata_task.fis.command, task->data_dir))
2391 << CMD_HDR_FRAME_TYPE_OFF;
2392 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2393 hdr->dw1 = cpu_to_le32(dw1);
2394
2395 /* dw2 */
2396 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2397 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2398 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2399 }
2400
2401 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2402 2 << CMD_HDR_SG_MOD_OFF;
2403 hdr->dw2 = cpu_to_le32(dw2);
2404
2405 /* dw3 */
2406 hdr->transfer_tags = cpu_to_le32(slot->idx);
2407
2408 if (has_data) {
2409 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2410 slot->n_elem);
2411 if (rc)
2412 return rc;
2413 }
2414
2415 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2416 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2417 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2418
2419 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2420
2421 if (likely(!task->ata_task.device_control_reg_update))
2422 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2423 /* fill in command FIS */
2424 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2425
2426 return 0;
2427 }
2428
2429 static void hisi_sas_internal_abort_quirk_timeout(unsigned long data)
2430 {
2431 struct hisi_sas_slot *slot = (struct hisi_sas_slot *)data;
2432 struct hisi_sas_port *port = slot->port;
2433 struct asd_sas_port *asd_sas_port;
2434 struct asd_sas_phy *sas_phy;
2435
2436 if (!port)
2437 return;
2438
2439 asd_sas_port = &port->sas_port;
2440
2441 /* Kick the hardware - send break command */
2442 list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2443 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2444 struct hisi_hba *hisi_hba = phy->hisi_hba;
2445 int phy_no = sas_phy->id;
2446 u32 link_dfx2;
2447
2448 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2449 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2450 (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2451 u32 txid_auto;
2452
2453 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2454 TXID_AUTO);
2455 txid_auto |= TXID_AUTO_CTB_MSK;
2456 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2457 txid_auto);
2458 return;
2459 }
2460 }
2461 }
2462
2463 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2464 struct hisi_sas_slot *slot,
2465 int device_id, int abort_flag, int tag_to_abort)
2466 {
2467 struct sas_task *task = slot->task;
2468 struct domain_device *dev = task->dev;
2469 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2470 struct hisi_sas_port *port = slot->port;
2471 struct timer_list *timer = &slot->internal_abort_timer;
2472
2473 /* setup the quirk timer */
2474 setup_timer(timer, hisi_sas_internal_abort_quirk_timeout,
2475 (unsigned long)slot);
2476 /* Set the timeout to 10ms less than internal abort timeout */
2477 mod_timer(timer, jiffies + msecs_to_jiffies(100));
2478
2479 /* dw0 */
2480 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2481 (port->id << CMD_HDR_PORT_OFF) |
2482 ((dev_is_sata(dev) ? 1:0) <<
2483 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2484 (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2485
2486 /* dw1 */
2487 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2488
2489 /* dw7 */
2490 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2491 hdr->transfer_tags = cpu_to_le32(slot->idx);
2492
2493 return 0;
2494 }
2495
2496 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2497 {
2498 int i, res = IRQ_HANDLED;
2499 u32 port_id, link_rate, hard_phy_linkrate;
2500 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2501 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2502 struct device *dev = hisi_hba->dev;
2503 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2504 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2505
2506 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2507
2508 if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2509 goto end;
2510
2511 if (phy_no == 8) {
2512 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2513
2514 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2515 PORT_STATE_PHY8_PORT_NUM_OFF;
2516 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2517 PORT_STATE_PHY8_CONN_RATE_OFF;
2518 } else {
2519 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2520 port_id = (port_id >> (4 * phy_no)) & 0xf;
2521 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2522 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2523 }
2524
2525 if (port_id == 0xf) {
2526 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2527 res = IRQ_NONE;
2528 goto end;
2529 }
2530
2531 for (i = 0; i < 6; i++) {
2532 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2533 RX_IDAF_DWORD0 + (i * 4));
2534 frame_rcvd[i] = __swab32(idaf);
2535 }
2536
2537 sas_phy->linkrate = link_rate;
2538 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2539 HARD_PHY_LINKRATE);
2540 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2541 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2542
2543 sas_phy->oob_mode = SAS_OOB_MODE;
2544 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2545 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2546 phy->port_id = port_id;
2547 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2548 phy->phy_type |= PORT_TYPE_SAS;
2549 phy->phy_attached = 1;
2550 phy->identify.device_type = id->dev_type;
2551 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
2552 if (phy->identify.device_type == SAS_END_DEVICE)
2553 phy->identify.target_port_protocols =
2554 SAS_PROTOCOL_SSP;
2555 else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2556 phy->identify.target_port_protocols =
2557 SAS_PROTOCOL_SMP;
2558 if (!timer_pending(&hisi_hba->timer))
2559 set_link_timer_quirk(hisi_hba);
2560 }
2561 queue_work(hisi_hba->wq, &phy->phyup_ws);
2562
2563 end:
2564 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2565 CHL_INT0_SL_PHY_ENABLE_MSK);
2566 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2567
2568 return res;
2569 }
2570
2571 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2572 {
2573 u32 port_state;
2574
2575 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2576 if (port_state & 0x1ff)
2577 return true;
2578
2579 return false;
2580 }
2581
2582 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2583 {
2584 u32 phy_state, sl_ctrl, txid_auto;
2585 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2586 struct hisi_sas_port *port = phy->port;
2587
2588 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2589
2590 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2591 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2592
2593 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2594 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2595 sl_ctrl & ~SL_CONTROL_CTA_MSK);
2596 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2597 if (!check_any_wideports_v2_hw(hisi_hba) &&
2598 timer_pending(&hisi_hba->timer))
2599 del_timer(&hisi_hba->timer);
2600
2601 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2602 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2603 txid_auto | TXID_AUTO_CT3_MSK);
2604
2605 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2606 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2607
2608 return IRQ_HANDLED;
2609 }
2610
2611 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2612 {
2613 struct hisi_hba *hisi_hba = p;
2614 u32 irq_msk;
2615 int phy_no = 0;
2616 irqreturn_t res = IRQ_NONE;
2617
2618 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2619 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2620 while (irq_msk) {
2621 if (irq_msk & 1) {
2622 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2623 CHL_INT0);
2624
2625 switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2626 CHL_INT0_SL_PHY_ENABLE_MSK)) {
2627
2628 case CHL_INT0_SL_PHY_ENABLE_MSK:
2629 /* phy up */
2630 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2631 IRQ_HANDLED)
2632 res = IRQ_HANDLED;
2633 break;
2634
2635 case CHL_INT0_NOT_RDY_MSK:
2636 /* phy down */
2637 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2638 IRQ_HANDLED)
2639 res = IRQ_HANDLED;
2640 break;
2641
2642 case (CHL_INT0_NOT_RDY_MSK |
2643 CHL_INT0_SL_PHY_ENABLE_MSK):
2644 reg_value = hisi_sas_read32(hisi_hba,
2645 PHY_STATE);
2646 if (reg_value & BIT(phy_no)) {
2647 /* phy up */
2648 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2649 IRQ_HANDLED)
2650 res = IRQ_HANDLED;
2651 } else {
2652 /* phy down */
2653 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2654 IRQ_HANDLED)
2655 res = IRQ_HANDLED;
2656 }
2657 break;
2658
2659 default:
2660 break;
2661 }
2662
2663 }
2664 irq_msk >>= 1;
2665 phy_no++;
2666 }
2667
2668 return res;
2669 }
2670
2671 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2672 {
2673 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2674 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2675 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2676 u32 bcast_status;
2677
2678 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2679 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2680 if (bcast_status & RX_BCAST_CHG_MSK)
2681 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2682 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2683 CHL_INT0_SL_RX_BCST_ACK_MSK);
2684 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2685 }
2686
2687 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2688 {
2689 struct hisi_hba *hisi_hba = p;
2690 struct device *dev = hisi_hba->dev;
2691 u32 ent_msk, ent_tmp, irq_msk;
2692 int phy_no = 0;
2693
2694 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2695 ent_tmp = ent_msk;
2696 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2697 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2698
2699 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2700 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2701
2702 while (irq_msk) {
2703 if (irq_msk & (1 << phy_no)) {
2704 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2705 CHL_INT0);
2706 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2707 CHL_INT1);
2708 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2709 CHL_INT2);
2710
2711 if (irq_value1) {
2712 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
2713 CHL_INT1_DMAC_TX_ECC_ERR_MSK))
2714 panic("%s: DMAC RX/TX ecc bad error!\
2715 (0x%x)",
2716 dev_name(dev), irq_value1);
2717
2718 hisi_sas_phy_write32(hisi_hba, phy_no,
2719 CHL_INT1, irq_value1);
2720 }
2721
2722 if (irq_value2)
2723 hisi_sas_phy_write32(hisi_hba, phy_no,
2724 CHL_INT2, irq_value2);
2725
2726
2727 if (irq_value0) {
2728 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2729 phy_bcast_v2_hw(phy_no, hisi_hba);
2730
2731 hisi_sas_phy_write32(hisi_hba, phy_no,
2732 CHL_INT0, irq_value0
2733 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2734 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2735 & (~CHL_INT0_NOT_RDY_MSK));
2736 }
2737 }
2738 irq_msk &= ~(1 << phy_no);
2739 phy_no++;
2740 }
2741
2742 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2743
2744 return IRQ_HANDLED;
2745 }
2746
2747 static void
2748 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2749 {
2750 struct device *dev = hisi_hba->dev;
2751 u32 reg_val;
2752
2753 if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF)) {
2754 reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR);
2755 dev_warn(dev, "hgc_dqe_acc1b_intr found: \
2756 Ram address is 0x%08X\n",
2757 (reg_val & HGC_DQE_ECC_1B_ADDR_MSK) >>
2758 HGC_DQE_ECC_1B_ADDR_OFF);
2759 }
2760
2761 if (irq_value & BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF)) {
2762 reg_val = hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR);
2763 dev_warn(dev, "hgc_iost_acc1b_intr found: \
2764 Ram address is 0x%08X\n",
2765 (reg_val & HGC_IOST_ECC_1B_ADDR_MSK) >>
2766 HGC_IOST_ECC_1B_ADDR_OFF);
2767 }
2768
2769 if (irq_value & BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF)) {
2770 reg_val = hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR);
2771 dev_warn(dev, "hgc_itct_acc1b_intr found: \
2772 Ram address is 0x%08X\n",
2773 (reg_val & HGC_ITCT_ECC_1B_ADDR_MSK) >>
2774 HGC_ITCT_ECC_1B_ADDR_OFF);
2775 }
2776
2777 if (irq_value & BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF)) {
2778 reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
2779 dev_warn(dev, "hgc_iostl_acc1b_intr found: \
2780 memory address is 0x%08X\n",
2781 (reg_val & HGC_LM_DFX_STATUS2_IOSTLIST_MSK) >>
2782 HGC_LM_DFX_STATUS2_IOSTLIST_OFF);
2783 }
2784
2785 if (irq_value & BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF)) {
2786 reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
2787 dev_warn(dev, "hgc_itctl_acc1b_intr found: \
2788 memory address is 0x%08X\n",
2789 (reg_val & HGC_LM_DFX_STATUS2_ITCTLIST_MSK) >>
2790 HGC_LM_DFX_STATUS2_ITCTLIST_OFF);
2791 }
2792
2793 if (irq_value & BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF)) {
2794 reg_val = hisi_sas_read32(hisi_hba, HGC_CQE_ECC_ADDR);
2795 dev_warn(dev, "hgc_cqe_acc1b_intr found: \
2796 Ram address is 0x%08X\n",
2797 (reg_val & HGC_CQE_ECC_1B_ADDR_MSK) >>
2798 HGC_CQE_ECC_1B_ADDR_OFF);
2799 }
2800
2801 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF)) {
2802 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
2803 dev_warn(dev, "rxm_mem0_acc1b_intr found: \
2804 memory address is 0x%08X\n",
2805 (reg_val & HGC_RXM_DFX_STATUS14_MEM0_MSK) >>
2806 HGC_RXM_DFX_STATUS14_MEM0_OFF);
2807 }
2808
2809 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF)) {
2810 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
2811 dev_warn(dev, "rxm_mem1_acc1b_intr found: \
2812 memory address is 0x%08X\n",
2813 (reg_val & HGC_RXM_DFX_STATUS14_MEM1_MSK) >>
2814 HGC_RXM_DFX_STATUS14_MEM1_OFF);
2815 }
2816
2817 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF)) {
2818 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
2819 dev_warn(dev, "rxm_mem2_acc1b_intr found: \
2820 memory address is 0x%08X\n",
2821 (reg_val & HGC_RXM_DFX_STATUS14_MEM2_MSK) >>
2822 HGC_RXM_DFX_STATUS14_MEM2_OFF);
2823 }
2824
2825 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF)) {
2826 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS15);
2827 dev_warn(dev, "rxm_mem3_acc1b_intr found: \
2828 memory address is 0x%08X\n",
2829 (reg_val & HGC_RXM_DFX_STATUS15_MEM3_MSK) >>
2830 HGC_RXM_DFX_STATUS15_MEM3_OFF);
2831 }
2832
2833 }
2834
2835 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2836 u32 irq_value)
2837 {
2838 u32 reg_val;
2839 struct device *dev = hisi_hba->dev;
2840
2841 if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF)) {
2842 reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR);
2843 dev_warn(dev, "hgc_dqe_accbad_intr (0x%x) found: \
2844 Ram address is 0x%08X\n",
2845 irq_value,
2846 (reg_val & HGC_DQE_ECC_MB_ADDR_MSK) >>
2847 HGC_DQE_ECC_MB_ADDR_OFF);
2848 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2849 }
2850
2851 if (irq_value & BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF)) {
2852 reg_val = hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR);
2853 dev_warn(dev, "hgc_iost_accbad_intr (0x%x) found: \
2854 Ram address is 0x%08X\n",
2855 irq_value,
2856 (reg_val & HGC_IOST_ECC_MB_ADDR_MSK) >>
2857 HGC_IOST_ECC_MB_ADDR_OFF);
2858 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2859 }
2860
2861 if (irq_value & BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF)) {
2862 reg_val = hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR);
2863 dev_warn(dev,"hgc_itct_accbad_intr (0x%x) found: \
2864 Ram address is 0x%08X\n",
2865 irq_value,
2866 (reg_val & HGC_ITCT_ECC_MB_ADDR_MSK) >>
2867 HGC_ITCT_ECC_MB_ADDR_OFF);
2868 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2869 }
2870
2871 if (irq_value & BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF)) {
2872 reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
2873 dev_warn(dev, "hgc_iostl_accbad_intr (0x%x) found: \
2874 memory address is 0x%08X\n",
2875 irq_value,
2876 (reg_val & HGC_LM_DFX_STATUS2_IOSTLIST_MSK) >>
2877 HGC_LM_DFX_STATUS2_IOSTLIST_OFF);
2878 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2879 }
2880
2881 if (irq_value & BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF)) {
2882 reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
2883 dev_warn(dev, "hgc_itctl_accbad_intr (0x%x) found: \
2884 memory address is 0x%08X\n",
2885 irq_value,
2886 (reg_val & HGC_LM_DFX_STATUS2_ITCTLIST_MSK) >>
2887 HGC_LM_DFX_STATUS2_ITCTLIST_OFF);
2888 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2889 }
2890
2891 if (irq_value & BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF)) {
2892 reg_val = hisi_sas_read32(hisi_hba, HGC_CQE_ECC_ADDR);
2893 dev_warn(dev, "hgc_cqe_accbad_intr (0x%x) found: \
2894 Ram address is 0x%08X\n",
2895 irq_value,
2896 (reg_val & HGC_CQE_ECC_MB_ADDR_MSK) >>
2897 HGC_CQE_ECC_MB_ADDR_OFF);
2898 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2899 }
2900
2901 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF)) {
2902 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
2903 dev_warn(dev, "rxm_mem0_accbad_intr (0x%x) found: \
2904 memory address is 0x%08X\n",
2905 irq_value,
2906 (reg_val & HGC_RXM_DFX_STATUS14_MEM0_MSK) >>
2907 HGC_RXM_DFX_STATUS14_MEM0_OFF);
2908 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2909 }
2910
2911 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF)) {
2912 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
2913 dev_warn(dev, "rxm_mem1_accbad_intr (0x%x) found: \
2914 memory address is 0x%08X\n",
2915 irq_value,
2916 (reg_val & HGC_RXM_DFX_STATUS14_MEM1_MSK) >>
2917 HGC_RXM_DFX_STATUS14_MEM1_OFF);
2918 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2919 }
2920
2921 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF)) {
2922 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
2923 dev_warn(dev, "rxm_mem2_accbad_intr (0x%x) found: \
2924 memory address is 0x%08X\n",
2925 irq_value,
2926 (reg_val & HGC_RXM_DFX_STATUS14_MEM2_MSK) >>
2927 HGC_RXM_DFX_STATUS14_MEM2_OFF);
2928 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2929 }
2930
2931 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF)) {
2932 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS15);
2933 dev_warn(dev, "rxm_mem3_accbad_intr (0x%x) found: \
2934 memory address is 0x%08X\n",
2935 irq_value,
2936 (reg_val & HGC_RXM_DFX_STATUS15_MEM3_MSK) >>
2937 HGC_RXM_DFX_STATUS15_MEM3_OFF);
2938 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2939 }
2940
2941 return;
2942 }
2943
2944 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
2945 {
2946 struct hisi_hba *hisi_hba = p;
2947 u32 irq_value, irq_msk;
2948
2949 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2950 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
2951
2952 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2953 if (irq_value) {
2954 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2955 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2956 }
2957
2958 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2959 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2960
2961 return IRQ_HANDLED;
2962 }
2963
2964 #define AXI_ERR_NR 8
2965 static const char axi_err_info[AXI_ERR_NR][32] = {
2966 "IOST_AXI_W_ERR",
2967 "IOST_AXI_R_ERR",
2968 "ITCT_AXI_W_ERR",
2969 "ITCT_AXI_R_ERR",
2970 "SATA_AXI_W_ERR",
2971 "SATA_AXI_R_ERR",
2972 "DQE_AXI_R_ERR",
2973 "CQE_AXI_W_ERR"
2974 };
2975
2976 #define FIFO_ERR_NR 5
2977 static const char fifo_err_info[FIFO_ERR_NR][32] = {
2978 "CQE_WINFO_FIFO",
2979 "CQE_MSG_FIFIO",
2980 "GETDQE_FIFO",
2981 "CMDP_FIFO",
2982 "AWTCTRL_FIFO"
2983 };
2984
2985 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
2986 {
2987 struct hisi_hba *hisi_hba = p;
2988 u32 irq_value, irq_msk, err_value;
2989 struct device *dev = hisi_hba->dev;
2990
2991 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2992 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
2993
2994 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
2995 if (irq_value) {
2996 if (irq_value & BIT(ENT_INT_SRC3_WP_DEPTH_OFF)) {
2997 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
2998 1 << ENT_INT_SRC3_WP_DEPTH_OFF);
2999 dev_warn(dev, "write pointer and depth error (0x%x) \
3000 found!\n",
3001 irq_value);
3002 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3003 }
3004
3005 if (irq_value & BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF)) {
3006 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3007 1 <<
3008 ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF);
3009 dev_warn(dev, "iptt no match slot error (0x%x) found!\n",
3010 irq_value);
3011 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3012 }
3013
3014 if (irq_value & BIT(ENT_INT_SRC3_RP_DEPTH_OFF)) {
3015 dev_warn(dev, "read pointer and depth error (0x%x) \
3016 found!\n",
3017 irq_value);
3018 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3019 }
3020
3021 if (irq_value & BIT(ENT_INT_SRC3_AXI_OFF)) {
3022 int i;
3023
3024 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3025 1 << ENT_INT_SRC3_AXI_OFF);
3026 err_value = hisi_sas_read32(hisi_hba,
3027 HGC_AXI_FIFO_ERR_INFO);
3028
3029 for (i = 0; i < AXI_ERR_NR; i++) {
3030 if (err_value & BIT(i)) {
3031 dev_warn(dev, "%s (0x%x) found!\n",
3032 axi_err_info[i], irq_value);
3033 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3034 }
3035 }
3036 }
3037
3038 if (irq_value & BIT(ENT_INT_SRC3_FIFO_OFF)) {
3039 int i;
3040
3041 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3042 1 << ENT_INT_SRC3_FIFO_OFF);
3043 err_value = hisi_sas_read32(hisi_hba,
3044 HGC_AXI_FIFO_ERR_INFO);
3045
3046 for (i = 0; i < FIFO_ERR_NR; i++) {
3047 if (err_value & BIT(AXI_ERR_NR + i)) {
3048 dev_warn(dev, "%s (0x%x) found!\n",
3049 fifo_err_info[i], irq_value);
3050 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3051 }
3052 }
3053
3054 }
3055
3056 if (irq_value & BIT(ENT_INT_SRC3_LM_OFF)) {
3057 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3058 1 << ENT_INT_SRC3_LM_OFF);
3059 dev_warn(dev, "LM add/fetch list error (0x%x) found!\n",
3060 irq_value);
3061 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3062 }
3063
3064 if (irq_value & BIT(ENT_INT_SRC3_ABT_OFF)) {
3065 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3066 1 << ENT_INT_SRC3_ABT_OFF);
3067 dev_warn(dev, "SAS_HGC_ABT fetch LM list error (0x%x) found!\n",
3068 irq_value);
3069 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3070 }
3071
3072 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3073 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3074 u32 dev_id = reg_val & ITCT_DEV_MSK;
3075 struct hisi_sas_device *sas_dev =
3076 &hisi_hba->devices[dev_id];
3077
3078 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3079 dev_dbg(dev, "clear ITCT ok\n");
3080 complete(sas_dev->completion);
3081 }
3082 }
3083
3084 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3085 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3086
3087 return IRQ_HANDLED;
3088 }
3089
3090 static void cq_tasklet_v2_hw(unsigned long val)
3091 {
3092 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3093 struct hisi_hba *hisi_hba = cq->hisi_hba;
3094 struct hisi_sas_slot *slot;
3095 struct hisi_sas_itct *itct;
3096 struct hisi_sas_complete_v2_hdr *complete_queue;
3097 u32 rd_point = cq->rd_point, wr_point, dev_id;
3098 int queue = cq->id;
3099 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
3100
3101 if (unlikely(hisi_hba->reject_stp_links_msk))
3102 phys_try_accept_stp_links_v2_hw(hisi_hba);
3103
3104 complete_queue = hisi_hba->complete_hdr[queue];
3105
3106 spin_lock(&dq->lock);
3107 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3108 (0x14 * queue));
3109
3110 while (rd_point != wr_point) {
3111 struct hisi_sas_complete_v2_hdr *complete_hdr;
3112 int iptt;
3113
3114 complete_hdr = &complete_queue[rd_point];
3115
3116 /* Check for NCQ completion */
3117 if (complete_hdr->act) {
3118 u32 act_tmp = complete_hdr->act;
3119 int ncq_tag_count = ffs(act_tmp);
3120
3121 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3122 CMPLT_HDR_DEV_ID_OFF;
3123 itct = &hisi_hba->itct[dev_id];
3124
3125 /* The NCQ tags are held in the itct header */
3126 while (ncq_tag_count) {
3127 __le64 *ncq_tag = &itct->qw4_15[0];
3128
3129 ncq_tag_count -= 1;
3130 iptt = (ncq_tag[ncq_tag_count / 5]
3131 >> (ncq_tag_count % 5) * 12) & 0xfff;
3132
3133 slot = &hisi_hba->slot_info[iptt];
3134 slot->cmplt_queue_slot = rd_point;
3135 slot->cmplt_queue = queue;
3136 slot_complete_v2_hw(hisi_hba, slot);
3137
3138 act_tmp &= ~(1 << ncq_tag_count);
3139 ncq_tag_count = ffs(act_tmp);
3140 }
3141 } else {
3142 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3143 slot = &hisi_hba->slot_info[iptt];
3144 slot->cmplt_queue_slot = rd_point;
3145 slot->cmplt_queue = queue;
3146 slot_complete_v2_hw(hisi_hba, slot);
3147 }
3148
3149 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3150 rd_point = 0;
3151 }
3152
3153 /* update rd_point */
3154 cq->rd_point = rd_point;
3155 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3156 spin_unlock(&dq->lock);
3157 }
3158
3159 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3160 {
3161 struct hisi_sas_cq *cq = p;
3162 struct hisi_hba *hisi_hba = cq->hisi_hba;
3163 int queue = cq->id;
3164
3165 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3166
3167 tasklet_schedule(&cq->tasklet);
3168
3169 return IRQ_HANDLED;
3170 }
3171
3172 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3173 {
3174 struct hisi_sas_phy *phy = p;
3175 struct hisi_hba *hisi_hba = phy->hisi_hba;
3176 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3177 struct device *dev = hisi_hba->dev;
3178 struct hisi_sas_initial_fis *initial_fis;
3179 struct dev_to_host_fis *fis;
3180 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3181 irqreturn_t res = IRQ_HANDLED;
3182 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3183 int phy_no, offset;
3184
3185 phy_no = sas_phy->id;
3186 initial_fis = &hisi_hba->initial_fis[phy_no];
3187 fis = &initial_fis->fis;
3188
3189 offset = 4 * (phy_no / 4);
3190 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3191 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3192 ent_msk | 1 << ((phy_no % 4) * 8));
3193
3194 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3195 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3196 (phy_no % 4)));
3197 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3198 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3199 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3200 res = IRQ_NONE;
3201 goto end;
3202 }
3203
3204 /* check ERR bit of Status Register */
3205 if (fis->status & ATA_ERR) {
3206 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3207 fis->status);
3208 disable_phy_v2_hw(hisi_hba, phy_no);
3209 enable_phy_v2_hw(hisi_hba, phy_no);
3210 res = IRQ_NONE;
3211 goto end;
3212 }
3213
3214 if (unlikely(phy_no == 8)) {
3215 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3216
3217 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3218 PORT_STATE_PHY8_PORT_NUM_OFF;
3219 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3220 PORT_STATE_PHY8_CONN_RATE_OFF;
3221 } else {
3222 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3223 port_id = (port_id >> (4 * phy_no)) & 0xf;
3224 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3225 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3226 }
3227
3228 if (port_id == 0xf) {
3229 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3230 res = IRQ_NONE;
3231 goto end;
3232 }
3233
3234 sas_phy->linkrate = link_rate;
3235 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3236 HARD_PHY_LINKRATE);
3237 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3238 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3239
3240 sas_phy->oob_mode = SATA_OOB_MODE;
3241 /* Make up some unique SAS address */
3242 attached_sas_addr[0] = 0x50;
3243 attached_sas_addr[7] = phy_no;
3244 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3245 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3246 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3247 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3248 phy->port_id = port_id;
3249 phy->phy_type |= PORT_TYPE_SATA;
3250 phy->phy_attached = 1;
3251 phy->identify.device_type = SAS_SATA_DEV;
3252 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3253 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3254 queue_work(hisi_hba->wq, &phy->phyup_ws);
3255
3256 end:
3257 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3258 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3259
3260 return res;
3261 }
3262
3263 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3264 int_phy_updown_v2_hw,
3265 int_chnl_int_v2_hw,
3266 };
3267
3268 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3269 fatal_ecc_int_v2_hw,
3270 fatal_axi_int_v2_hw
3271 };
3272
3273 /**
3274 * There is a limitation in the hip06 chipset that we need
3275 * to map in all mbigen interrupts, even if they are not used.
3276 */
3277 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3278 {
3279 struct platform_device *pdev = hisi_hba->platform_dev;
3280 struct device *dev = &pdev->dev;
3281 int irq, rc, irq_map[128];
3282 int i, phy_no, fatal_no, queue_no, k;
3283
3284 for (i = 0; i < 128; i++)
3285 irq_map[i] = platform_get_irq(pdev, i);
3286
3287 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3288 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3289 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3290 DRV_NAME " phy", hisi_hba);
3291 if (rc) {
3292 dev_err(dev, "irq init: could not request "
3293 "phy interrupt %d, rc=%d\n",
3294 irq, rc);
3295 rc = -ENOENT;
3296 goto free_phy_int_irqs;
3297 }
3298 }
3299
3300 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3301 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3302
3303 irq = irq_map[phy_no + 72];
3304 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3305 DRV_NAME " sata", phy);
3306 if (rc) {
3307 dev_err(dev, "irq init: could not request "
3308 "sata interrupt %d, rc=%d\n",
3309 irq, rc);
3310 rc = -ENOENT;
3311 goto free_sata_int_irqs;
3312 }
3313 }
3314
3315 for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3316 irq = irq_map[fatal_no + 81];
3317 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3318 DRV_NAME " fatal", hisi_hba);
3319 if (rc) {
3320 dev_err(dev,
3321 "irq init: could not request fatal interrupt %d, rc=%d\n",
3322 irq, rc);
3323 rc = -ENOENT;
3324 goto free_fatal_int_irqs;
3325 }
3326 }
3327
3328 for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3329 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3330 struct tasklet_struct *t = &cq->tasklet;
3331
3332 irq = irq_map[queue_no + 96];
3333 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3334 DRV_NAME " cq", cq);
3335 if (rc) {
3336 dev_err(dev,
3337 "irq init: could not request cq interrupt %d, rc=%d\n",
3338 irq, rc);
3339 rc = -ENOENT;
3340 goto free_cq_int_irqs;
3341 }
3342 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3343 }
3344
3345 return 0;
3346
3347 free_cq_int_irqs:
3348 for (k = 0; k < queue_no; k++) {
3349 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3350
3351 free_irq(irq_map[k + 96], cq);
3352 tasklet_kill(&cq->tasklet);
3353 }
3354 free_fatal_int_irqs:
3355 for (k = 0; k < fatal_no; k++)
3356 free_irq(irq_map[k + 81], hisi_hba);
3357 free_sata_int_irqs:
3358 for (k = 0; k < phy_no; k++) {
3359 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3360
3361 free_irq(irq_map[k + 72], phy);
3362 }
3363 free_phy_int_irqs:
3364 for (k = 0; k < i; k++)
3365 free_irq(irq_map[k + 1], hisi_hba);
3366 return rc;
3367 }
3368
3369 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3370 {
3371 int rc;
3372
3373 memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3374
3375 rc = hw_init_v2_hw(hisi_hba);
3376 if (rc)
3377 return rc;
3378
3379 rc = interrupt_init_v2_hw(hisi_hba);
3380 if (rc)
3381 return rc;
3382
3383 return 0;
3384 }
3385
3386 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3387 {
3388 struct platform_device *pdev = hisi_hba->platform_dev;
3389 int i;
3390
3391 for (i = 0; i < hisi_hba->queue_count; i++)
3392 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3393
3394 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3395 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3396 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3397 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3398
3399 for (i = 0; i < hisi_hba->n_phy; i++) {
3400 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3401 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3402 }
3403
3404 for (i = 0; i < 128; i++)
3405 synchronize_irq(platform_get_irq(pdev, i));
3406 }
3407
3408
3409 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3410 {
3411 return hisi_sas_read32(hisi_hba, PHY_STATE);
3412 }
3413
3414 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3415 {
3416 struct device *dev = hisi_hba->dev;
3417 int rc, cnt;
3418
3419 interrupt_disable_v2_hw(hisi_hba);
3420 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3421 hisi_sas_kill_tasklets(hisi_hba);
3422
3423 stop_phys_v2_hw(hisi_hba);
3424
3425 mdelay(10);
3426
3427 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3428
3429 /* wait until bus idle */
3430 cnt = 0;
3431 while (1) {
3432 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3433 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3434
3435 if (status == 0x3)
3436 break;
3437
3438 udelay(10);
3439 if (cnt++ > 10) {
3440 dev_info(dev, "wait axi bus state to idle timeout!\n");
3441 return -1;
3442 }
3443 }
3444
3445 hisi_sas_init_mem(hisi_hba);
3446
3447 rc = hw_init_v2_hw(hisi_hba);
3448 if (rc)
3449 return rc;
3450
3451 phys_reject_stp_links_v2_hw(hisi_hba);
3452
3453 return 0;
3454 }
3455
3456 static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
3457 u8 reg_index, u8 reg_count, u8 *write_data)
3458 {
3459 struct device *dev = hisi_hba->dev;
3460 int phy_no, count;
3461
3462 if (!hisi_hba->sgpio_regs)
3463 return -EOPNOTSUPP;
3464
3465 switch (reg_type) {
3466 case SAS_GPIO_REG_TX:
3467 count = reg_count * 4;
3468 count = min(count, hisi_hba->n_phy);
3469
3470 for (phy_no = 0; phy_no < count; phy_no++) {
3471 /*
3472 * GPIO_TX[n] register has the highest numbered drive
3473 * of the four in the first byte and the lowest
3474 * numbered drive in the fourth byte.
3475 * See SFF-8485 Rev. 0.7 Table 24.
3476 */
3477 void __iomem *reg_addr = hisi_hba->sgpio_regs +
3478 reg_index * 4 + phy_no;
3479 int data_idx = phy_no + 3 - (phy_no % 4) * 2;
3480
3481 writeb(write_data[data_idx], reg_addr);
3482 }
3483
3484 break;
3485 default:
3486 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3487 reg_type);
3488 return -EINVAL;
3489 }
3490
3491 return 0;
3492 }
3493
3494 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3495 .hw_init = hisi_sas_v2_init,
3496 .setup_itct = setup_itct_v2_hw,
3497 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3498 .alloc_dev = alloc_dev_quirk_v2_hw,
3499 .sl_notify = sl_notify_v2_hw,
3500 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3501 .free_device = free_device_v2_hw,
3502 .prep_smp = prep_smp_v2_hw,
3503 .prep_ssp = prep_ssp_v2_hw,
3504 .prep_stp = prep_ata_v2_hw,
3505 .prep_abort = prep_abort_v2_hw,
3506 .get_free_slot = get_free_slot_v2_hw,
3507 .start_delivery = start_delivery_v2_hw,
3508 .slot_complete = slot_complete_v2_hw,
3509 .phys_init = phys_init_v2_hw,
3510 .phy_start = start_phy_v2_hw,
3511 .phy_disable = disable_phy_v2_hw,
3512 .phy_hard_reset = phy_hard_reset_v2_hw,
3513 .get_events = phy_get_events_v2_hw,
3514 .phy_set_linkrate = phy_set_linkrate_v2_hw,
3515 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3516 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3517 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3518 .soft_reset = soft_reset_v2_hw,
3519 .get_phys_state = get_phys_state_v2_hw,
3520 .write_gpio = write_gpio_v2_hw,
3521 };
3522
3523 static int hisi_sas_v2_probe(struct platform_device *pdev)
3524 {
3525 /*
3526 * Check if we should defer the probe before we probe the
3527 * upper layer, as it's hard to defer later on.
3528 */
3529 int ret = platform_get_irq(pdev, 0);
3530
3531 if (ret < 0) {
3532 if (ret != -EPROBE_DEFER)
3533 dev_err(&pdev->dev, "cannot obtain irq\n");
3534 return ret;
3535 }
3536
3537 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3538 }
3539
3540 static int hisi_sas_v2_remove(struct platform_device *pdev)
3541 {
3542 struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3543 struct hisi_hba *hisi_hba = sha->lldd_ha;
3544
3545 if (timer_pending(&hisi_hba->timer))
3546 del_timer(&hisi_hba->timer);
3547
3548 hisi_sas_kill_tasklets(hisi_hba);
3549
3550 return hisi_sas_remove(pdev);
3551 }
3552
3553 static const struct of_device_id sas_v2_of_match[] = {
3554 { .compatible = "hisilicon,hip06-sas-v2",},
3555 { .compatible = "hisilicon,hip07-sas-v2",},
3556 {},
3557 };
3558 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3559
3560 static const struct acpi_device_id sas_v2_acpi_match[] = {
3561 { "HISI0162", 0 },
3562 { }
3563 };
3564
3565 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3566
3567 static struct platform_driver hisi_sas_v2_driver = {
3568 .probe = hisi_sas_v2_probe,
3569 .remove = hisi_sas_v2_remove,
3570 .driver = {
3571 .name = DRV_NAME,
3572 .of_match_table = sas_v2_of_match,
3573 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3574 },
3575 };
3576
3577 module_platform_driver(hisi_sas_v2_driver);
3578
3579 MODULE_LICENSE("GPL");
3580 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3581 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3582 MODULE_ALIAS("platform:" DRV_NAME);
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