2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
13 #define DRV_NAME "hisi_sas_v2_hw"
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
148 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
149 #define DLVRY_Q_0_DEPTH 0x268
150 #define DLVRY_Q_0_WR_PTR 0x26c
151 #define DLVRY_Q_0_RD_PTR 0x270
152 #define HYPER_STREAM_ID_EN_CFG 0xc80
153 #define OQ0_INT_SRC_MSK 0xc90
154 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
155 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
156 #define COMPL_Q_0_DEPTH 0x4e8
157 #define COMPL_Q_0_WR_PTR 0x4ec
158 #define COMPL_Q_0_RD_PTR 0x4f0
159 #define HGC_RXM_DFX_STATUS14 0xae8
160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
162 HGC_RXM_DFX_STATUS14_MEM0_OFF)
163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM1_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM2_OFF)
169 #define HGC_RXM_DFX_STATUS15 0xaec
170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
172 HGC_RXM_DFX_STATUS15_MEM3_OFF)
173 /* phy registers need init */
174 #define PORT_BASE (0x2000)
176 #define PHY_CFG (PORT_BASE + 0x0)
177 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PHY_CFG_ENA_OFF 0
179 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
180 #define PHY_CFG_DC_OPT_OFF 2
181 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
182 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
183 #define PROG_PHY_LINK_RATE_MAX_OFF 0
184 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
185 #define PHY_CTRL (PORT_BASE + 0x14)
186 #define PHY_CTRL_RESET_OFF 0
187 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
188 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
189 #define SL_CFG (PORT_BASE + 0x84)
190 #define PHY_PCN (PORT_BASE + 0x44)
191 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
192 #define SL_CONTROL (PORT_BASE + 0x94)
193 #define SL_CONTROL_NOTIFY_EN_OFF 0
194 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
195 #define SL_CONTROL_CTA_OFF 17
196 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
197 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
198 #define RX_BCAST_CHG_OFF 1
199 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
200 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
201 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
202 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
203 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
204 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
205 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
206 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
207 #define TXID_AUTO (PORT_BASE + 0xb8)
208 #define TXID_AUTO_CT3_OFF 1
209 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
210 #define TXID_AUTO_CTB_OFF 11
211 #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
212 #define TX_HARDRST_OFF 2
213 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
214 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
215 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
216 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
217 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
218 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
219 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
220 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
221 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
222 #define CON_CONTROL (PORT_BASE + 0x118)
223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
225 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
226 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
227 #define CHL_INT0 (PORT_BASE + 0x1b4)
228 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
229 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
230 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
231 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
232 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
233 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
234 #define CHL_INT0_NOT_RDY_OFF 4
235 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
236 #define CHL_INT0_PHY_RDY_OFF 5
237 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
238 #define CHL_INT1 (PORT_BASE + 0x1b8)
239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
243 #define CHL_INT2 (PORT_BASE + 0x1bc)
244 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
245 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
246 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
247 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
248 #define DMA_TX_DFX0 (PORT_BASE + 0x200)
249 #define DMA_TX_DFX1 (PORT_BASE + 0x204)
250 #define DMA_TX_DFX1_IPTT_OFF 0
251 #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
252 #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
253 #define PORT_DFX0 (PORT_BASE + 0x258)
254 #define LINK_DFX2 (PORT_BASE + 0X264)
255 #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
256 #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
257 #define LINK_DFX2_SEND_HOLD_STS_OFF 10
258 #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
259 #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
260 #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
261 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
262 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
263 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
264 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
265 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
266 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
267 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
268 #define DMA_TX_STATUS_BUSY_OFF 0
269 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
270 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
271 #define DMA_RX_STATUS_BUSY_OFF 0
272 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
274 #define AXI_CFG (0x5100)
275 #define AM_CFG_MAX_TRANS (0x5010)
276 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
278 #define AXI_MASTER_CFG_BASE (0x5000)
279 #define AM_CTRL_GLOBAL (0x0)
280 #define AM_CURR_TRANS_RETURN (0x150)
282 /* HW dma structures */
283 /* Delivery queue header */
285 #define CMD_HDR_ABORT_FLAG_OFF 0
286 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
287 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
288 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
289 #define CMD_HDR_RESP_REPORT_OFF 5
290 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
291 #define CMD_HDR_TLR_CTRL_OFF 6
292 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
293 #define CMD_HDR_PORT_OFF 18
294 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
295 #define CMD_HDR_PRIORITY_OFF 27
296 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
297 #define CMD_HDR_CMD_OFF 29
298 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
300 #define CMD_HDR_DIR_OFF 5
301 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
302 #define CMD_HDR_RESET_OFF 7
303 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
304 #define CMD_HDR_VDTL_OFF 10
305 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
306 #define CMD_HDR_FRAME_TYPE_OFF 11
307 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
308 #define CMD_HDR_DEV_ID_OFF 16
309 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
311 #define CMD_HDR_CFL_OFF 0
312 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
313 #define CMD_HDR_NCQ_TAG_OFF 10
314 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
315 #define CMD_HDR_MRFL_OFF 15
316 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
317 #define CMD_HDR_SG_MOD_OFF 24
318 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
319 #define CMD_HDR_FIRST_BURST_OFF 26
320 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
322 #define CMD_HDR_IPTT_OFF 0
323 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
325 #define CMD_HDR_DIF_SGL_LEN_OFF 0
326 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
327 #define CMD_HDR_DATA_SGL_LEN_OFF 16
328 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
329 #define CMD_HDR_ABORT_IPTT_OFF 16
330 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
332 /* Completion header */
334 #define CMPLT_HDR_ERR_PHASE_OFF 2
335 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
336 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
337 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
338 #define CMPLT_HDR_ERX_OFF 12
339 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
340 #define CMPLT_HDR_ABORT_STAT_OFF 13
341 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
343 #define STAT_IO_NOT_VALID 0x1
344 #define STAT_IO_NO_DEVICE 0x2
345 #define STAT_IO_COMPLETE 0x3
346 #define STAT_IO_ABORTED 0x4
348 #define CMPLT_HDR_IPTT_OFF 0
349 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
350 #define CMPLT_HDR_DEV_ID_OFF 16
351 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
355 #define ITCT_HDR_DEV_TYPE_OFF 0
356 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
357 #define ITCT_HDR_VALID_OFF 2
358 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
359 #define ITCT_HDR_MCR_OFF 5
360 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
361 #define ITCT_HDR_VLN_OFF 9
362 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
363 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
364 #define ITCT_HDR_SMP_TIMEOUT_8US 1
365 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
367 #define ITCT_HDR_AWT_CONTINUE_OFF 25
368 #define ITCT_HDR_PORT_ID_OFF 28
369 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
371 #define ITCT_HDR_INLT_OFF 0
372 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
373 #define ITCT_HDR_BITLT_OFF 16
374 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
375 #define ITCT_HDR_MCTLT_OFF 32
376 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
377 #define ITCT_HDR_RTOLT_OFF 48
378 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
380 #define HISI_SAS_FATAL_INT_NR 2
382 struct hisi_sas_complete_v2_hdr
{
389 struct hisi_sas_err_record_v2
{
391 __le32 trans_tx_fail_type
;
394 __le32 trans_rx_fail_type
;
397 __le16 dma_tx_err_type
;
398 __le16 sipc_rx_err_type
;
401 __le32 dma_rx_err_type
;
404 static const struct hisi_sas_hw_error one_bit_ecc_errors
[] = {
406 .irq_msk
= BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF
),
407 .msk
= HGC_DQE_ECC_1B_ADDR_MSK
,
408 .shift
= HGC_DQE_ECC_1B_ADDR_OFF
,
409 .msg
= "hgc_dqe_acc1b_intr found: \
410 Ram address is 0x%08X\n",
411 .reg
= HGC_DQE_ECC_ADDR
,
414 .irq_msk
= BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF
),
415 .msk
= HGC_IOST_ECC_1B_ADDR_MSK
,
416 .shift
= HGC_IOST_ECC_1B_ADDR_OFF
,
417 .msg
= "hgc_iost_acc1b_intr found: \
418 Ram address is 0x%08X\n",
419 .reg
= HGC_IOST_ECC_ADDR
,
422 .irq_msk
= BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF
),
423 .msk
= HGC_ITCT_ECC_1B_ADDR_MSK
,
424 .shift
= HGC_ITCT_ECC_1B_ADDR_OFF
,
425 .msg
= "hgc_itct_acc1b_intr found: \
426 Ram address is 0x%08X\n",
427 .reg
= HGC_ITCT_ECC_ADDR
,
430 .irq_msk
= BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF
),
431 .msk
= HGC_LM_DFX_STATUS2_IOSTLIST_MSK
,
432 .shift
= HGC_LM_DFX_STATUS2_IOSTLIST_OFF
,
433 .msg
= "hgc_iostl_acc1b_intr found: \
434 memory address is 0x%08X\n",
435 .reg
= HGC_LM_DFX_STATUS2
,
438 .irq_msk
= BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF
),
439 .msk
= HGC_LM_DFX_STATUS2_ITCTLIST_MSK
,
440 .shift
= HGC_LM_DFX_STATUS2_ITCTLIST_OFF
,
441 .msg
= "hgc_itctl_acc1b_intr found: \
442 memory address is 0x%08X\n",
443 .reg
= HGC_LM_DFX_STATUS2
,
446 .irq_msk
= BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF
),
447 .msk
= HGC_CQE_ECC_1B_ADDR_MSK
,
448 .shift
= HGC_CQE_ECC_1B_ADDR_OFF
,
449 .msg
= "hgc_cqe_acc1b_intr found: \
450 Ram address is 0x%08X\n",
451 .reg
= HGC_CQE_ECC_ADDR
,
454 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF
),
455 .msk
= HGC_RXM_DFX_STATUS14_MEM0_MSK
,
456 .shift
= HGC_RXM_DFX_STATUS14_MEM0_OFF
,
457 .msg
= "rxm_mem0_acc1b_intr found: \
458 memory address is 0x%08X\n",
459 .reg
= HGC_RXM_DFX_STATUS14
,
462 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF
),
463 .msk
= HGC_RXM_DFX_STATUS14_MEM1_MSK
,
464 .shift
= HGC_RXM_DFX_STATUS14_MEM1_OFF
,
465 .msg
= "rxm_mem1_acc1b_intr found: \
466 memory address is 0x%08X\n",
467 .reg
= HGC_RXM_DFX_STATUS14
,
470 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF
),
471 .msk
= HGC_RXM_DFX_STATUS14_MEM2_MSK
,
472 .shift
= HGC_RXM_DFX_STATUS14_MEM2_OFF
,
473 .msg
= "rxm_mem2_acc1b_intr found: \
474 memory address is 0x%08X\n",
475 .reg
= HGC_RXM_DFX_STATUS14
,
478 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF
),
479 .msk
= HGC_RXM_DFX_STATUS15_MEM3_MSK
,
480 .shift
= HGC_RXM_DFX_STATUS15_MEM3_OFF
,
481 .msg
= "rxm_mem3_acc1b_intr found: \
482 memory address is 0x%08X\n",
483 .reg
= HGC_RXM_DFX_STATUS15
,
487 static const struct hisi_sas_hw_error multi_bit_ecc_errors
[] = {
489 .irq_msk
= BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF
),
490 .msk
= HGC_DQE_ECC_MB_ADDR_MSK
,
491 .shift
= HGC_DQE_ECC_MB_ADDR_OFF
,
492 .msg
= "hgc_dqe_accbad_intr (0x%x) found: \
493 Ram address is 0x%08X\n",
494 .reg
= HGC_DQE_ECC_ADDR
,
497 .irq_msk
= BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF
),
498 .msk
= HGC_IOST_ECC_MB_ADDR_MSK
,
499 .shift
= HGC_IOST_ECC_MB_ADDR_OFF
,
500 .msg
= "hgc_iost_accbad_intr (0x%x) found: \
501 Ram address is 0x%08X\n",
502 .reg
= HGC_IOST_ECC_ADDR
,
505 .irq_msk
= BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF
),
506 .msk
= HGC_ITCT_ECC_MB_ADDR_MSK
,
507 .shift
= HGC_ITCT_ECC_MB_ADDR_OFF
,
508 .msg
= "hgc_itct_accbad_intr (0x%x) found: \
509 Ram address is 0x%08X\n",
510 .reg
= HGC_ITCT_ECC_ADDR
,
513 .irq_msk
= BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF
),
514 .msk
= HGC_LM_DFX_STATUS2_IOSTLIST_MSK
,
515 .shift
= HGC_LM_DFX_STATUS2_IOSTLIST_OFF
,
516 .msg
= "hgc_iostl_accbad_intr (0x%x) found: \
517 memory address is 0x%08X\n",
518 .reg
= HGC_LM_DFX_STATUS2
,
521 .irq_msk
= BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF
),
522 .msk
= HGC_LM_DFX_STATUS2_ITCTLIST_MSK
,
523 .shift
= HGC_LM_DFX_STATUS2_ITCTLIST_OFF
,
524 .msg
= "hgc_itctl_accbad_intr (0x%x) found: \
525 memory address is 0x%08X\n",
526 .reg
= HGC_LM_DFX_STATUS2
,
529 .irq_msk
= BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF
),
530 .msk
= HGC_CQE_ECC_MB_ADDR_MSK
,
531 .shift
= HGC_CQE_ECC_MB_ADDR_OFF
,
532 .msg
= "hgc_cqe_accbad_intr (0x%x) found: \
533 Ram address is 0x%08X\n",
534 .reg
= HGC_CQE_ECC_ADDR
,
537 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF
),
538 .msk
= HGC_RXM_DFX_STATUS14_MEM0_MSK
,
539 .shift
= HGC_RXM_DFX_STATUS14_MEM0_OFF
,
540 .msg
= "rxm_mem0_accbad_intr (0x%x) found: \
541 memory address is 0x%08X\n",
542 .reg
= HGC_RXM_DFX_STATUS14
,
545 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF
),
546 .msk
= HGC_RXM_DFX_STATUS14_MEM1_MSK
,
547 .shift
= HGC_RXM_DFX_STATUS14_MEM1_OFF
,
548 .msg
= "rxm_mem1_accbad_intr (0x%x) found: \
549 memory address is 0x%08X\n",
550 .reg
= HGC_RXM_DFX_STATUS14
,
553 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF
),
554 .msk
= HGC_RXM_DFX_STATUS14_MEM2_MSK
,
555 .shift
= HGC_RXM_DFX_STATUS14_MEM2_OFF
,
556 .msg
= "rxm_mem2_accbad_intr (0x%x) found: \
557 memory address is 0x%08X\n",
558 .reg
= HGC_RXM_DFX_STATUS14
,
561 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF
),
562 .msk
= HGC_RXM_DFX_STATUS15_MEM3_MSK
,
563 .shift
= HGC_RXM_DFX_STATUS15_MEM3_OFF
,
564 .msg
= "rxm_mem3_accbad_intr (0x%x) found: \
565 memory address is 0x%08X\n",
566 .reg
= HGC_RXM_DFX_STATUS15
,
571 HISI_SAS_PHY_PHY_UPDOWN
,
572 HISI_SAS_PHY_CHNL_INT
,
577 TRANS_TX_FAIL_BASE
= 0x0, /* dw0 */
578 TRANS_RX_FAIL_BASE
= 0x20, /* dw1 */
579 DMA_TX_ERR_BASE
= 0x40, /* dw2 bit 15-0 */
580 SIPC_RX_ERR_BASE
= 0x50, /* dw2 bit 31-16*/
581 DMA_RX_ERR_BASE
= 0x60, /* dw3 */
584 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
= TRANS_TX_FAIL_BASE
, /* 0x0 */
585 TRANS_TX_ERR_PHY_NOT_ENABLE
, /* 0x1 */
586 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
, /* 0x2 */
587 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
, /* 0x3 */
588 TRANS_TX_OPEN_CNX_ERR_BY_OTHER
, /* 0x4 */
590 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
, /* 0x6 */
591 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
, /* 0x7 */
592 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
, /* 0x8 */
593 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
, /* 0x9 */
594 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
, /* 0xa */
595 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
, /* 0xb */
596 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
, /* 0xc */
597 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
, /* 0xd */
598 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
, /* 0xe */
599 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
, /* 0xf */
600 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
, /* 0x10 */
601 TRANS_TX_ERR_FRAME_TXED
, /* 0x11 */
602 TRANS_TX_ERR_WITH_BREAK_TIMEOUT
, /* 0x12 */
603 TRANS_TX_ERR_WITH_BREAK_REQUEST
, /* 0x13 */
604 TRANS_TX_ERR_WITH_BREAK_RECEVIED
, /* 0x14 */
605 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
, /* 0x15 */
606 TRANS_TX_ERR_WITH_CLOSE_NORMAL
, /* 0x16 for ssp*/
607 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
, /* 0x17 */
608 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
, /* 0x18 */
609 TRANS_TX_ERR_WITH_CLOSE_COMINIT
, /* 0x19 */
610 TRANS_TX_ERR_WITH_NAK_RECEVIED
, /* 0x1a for ssp*/
611 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
, /* 0x1b for ssp*/
612 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
613 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
, /* 0x1c for ssp */
614 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
615 TRANS_TX_ERR_WITH_IPTT_CONFLICT
, /* 0x1d for ssp/smp */
616 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS
, /* 0x1e */
617 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
618 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
, /* 0x1f for sata/stp */
621 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
= TRANS_RX_FAIL_BASE
, /* 0x20 */
622 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
, /* 0x21 for sata/stp */
623 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
, /* 0x22 for ssp/smp */
624 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
625 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
, /* 0x23 for sata/stp */
626 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
, /* 0x24 for sata/stp */
627 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
, /* 0x25 for smp */
628 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
629 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
, /* 0x26 for sata/stp*/
630 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
, /* 0x27 */
631 TRANS_RX_ERR_WITH_BREAK_TIMEOUT
, /* 0x28 */
632 TRANS_RX_ERR_WITH_BREAK_REQUEST
, /* 0x29 */
633 TRANS_RX_ERR_WITH_BREAK_RECEVIED
, /* 0x2a */
634 RESERVED1
, /* 0x2b */
635 TRANS_RX_ERR_WITH_CLOSE_NORMAL
, /* 0x2c */
636 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
, /* 0x2d */
637 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
, /* 0x2e */
638 TRANS_RX_ERR_WITH_CLOSE_COMINIT
, /* 0x2f */
639 TRANS_RX_ERR_WITH_DATA_LEN0
, /* 0x30 for ssp/smp */
640 TRANS_RX_ERR_WITH_BAD_HASH
, /* 0x31 for ssp */
641 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
642 TRANS_RX_XRDY_WLEN_ZERO_ERR
, /* 0x32 for ssp*/
643 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
644 TRANS_RX_SSP_FRM_LEN_ERR
, /* 0x33 for ssp */
645 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
646 RESERVED2
, /* 0x34 */
647 RESERVED3
, /* 0x35 */
648 RESERVED4
, /* 0x36 */
649 RESERVED5
, /* 0x37 */
650 TRANS_RX_ERR_WITH_BAD_FRM_TYPE
, /* 0x38 */
651 TRANS_RX_SMP_FRM_LEN_ERR
, /* 0x39 */
652 TRANS_RX_SMP_RESP_TIMEOUT_ERR
, /* 0x3a */
653 RESERVED6
, /* 0x3b */
654 RESERVED7
, /* 0x3c */
655 RESERVED8
, /* 0x3d */
656 RESERVED9
, /* 0x3e */
657 TRANS_RX_R_ERR
, /* 0x3f */
660 DMA_TX_DIF_CRC_ERR
= DMA_TX_ERR_BASE
, /* 0x40 */
661 DMA_TX_DIF_APP_ERR
, /* 0x41 */
662 DMA_TX_DIF_RPP_ERR
, /* 0x42 */
663 DMA_TX_DATA_SGL_OVERFLOW
, /* 0x43 */
664 DMA_TX_DIF_SGL_OVERFLOW
, /* 0x44 */
665 DMA_TX_UNEXP_XFER_ERR
, /* 0x45 */
666 DMA_TX_UNEXP_RETRANS_ERR
, /* 0x46 */
667 DMA_TX_XFER_LEN_OVERFLOW
, /* 0x47 */
668 DMA_TX_XFER_OFFSET_ERR
, /* 0x48 */
669 DMA_TX_RAM_ECC_ERR
, /* 0x49 */
670 DMA_TX_DIF_LEN_ALIGN_ERR
, /* 0x4a */
674 SIPC_RX_FIS_STATUS_ERR_BIT_VLD
= SIPC_RX_ERR_BASE
, /* 0x50 */
675 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR
, /* 0x51 */
676 SIPC_RX_FIS_STATUS_BSY_BIT_ERR
, /* 0x52 */
677 SIPC_RX_WRSETUP_LEN_ODD_ERR
, /* 0x53 */
678 SIPC_RX_WRSETUP_LEN_ZERO_ERR
, /* 0x54 */
679 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR
, /* 0x55 */
680 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR
, /* 0x56 */
681 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR
, /* 0x57 */
682 SIPC_RX_SATA_UNEXP_FIS_ERR
, /* 0x58 */
683 SIPC_RX_WRSETUP_ESTATUS_ERR
, /* 0x59 */
684 SIPC_RX_DATA_UNDERFLOW_ERR
, /* 0x5a */
685 SIPC_RX_MAX_ERR_CODE
,
688 DMA_RX_DIF_CRC_ERR
= DMA_RX_ERR_BASE
, /* 0x60 */
689 DMA_RX_DIF_APP_ERR
, /* 0x61 */
690 DMA_RX_DIF_RPP_ERR
, /* 0x62 */
691 DMA_RX_DATA_SGL_OVERFLOW
, /* 0x63 */
692 DMA_RX_DIF_SGL_OVERFLOW
, /* 0x64 */
693 DMA_RX_DATA_LEN_OVERFLOW
, /* 0x65 */
694 DMA_RX_DATA_LEN_UNDERFLOW
, /* 0x66 */
695 DMA_RX_DATA_OFFSET_ERR
, /* 0x67 */
696 RESERVED10
, /* 0x68 */
697 DMA_RX_SATA_FRAME_TYPE_ERR
, /* 0x69 */
698 DMA_RX_RESP_BUF_OVERFLOW
, /* 0x6a */
699 DMA_RX_UNEXP_RETRANS_RESP_ERR
, /* 0x6b */
700 DMA_RX_UNEXP_NORM_RESP_ERR
, /* 0x6c */
701 DMA_RX_UNEXP_RDFRAME_ERR
, /* 0x6d */
702 DMA_RX_PIO_DATA_LEN_ERR
, /* 0x6e */
703 DMA_RX_RDSETUP_STATUS_ERR
, /* 0x6f */
704 DMA_RX_RDSETUP_STATUS_DRQ_ERR
, /* 0x70 */
705 DMA_RX_RDSETUP_STATUS_BSY_ERR
, /* 0x71 */
706 DMA_RX_RDSETUP_LEN_ODD_ERR
, /* 0x72 */
707 DMA_RX_RDSETUP_LEN_ZERO_ERR
, /* 0x73 */
708 DMA_RX_RDSETUP_LEN_OVER_ERR
, /* 0x74 */
709 DMA_RX_RDSETUP_OFFSET_ERR
, /* 0x75 */
710 DMA_RX_RDSETUP_ACTIVE_ERR
, /* 0x76 */
711 DMA_RX_RDSETUP_ESTATUS_ERR
, /* 0x77 */
712 DMA_RX_RAM_ECC_ERR
, /* 0x78 */
713 DMA_RX_UNKNOWN_FRM_ERR
, /* 0x79 */
717 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
718 #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
720 #define DIR_NO_DATA 0
722 #define DIR_TO_DEVICE 2
723 #define DIR_RESERVED 3
725 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
726 err_phase == 0x4 || err_phase == 0x8 ||\
727 err_phase == 0x6 || err_phase == 0xa)
728 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
729 err_phase == 0x20 || err_phase == 0x40)
731 static void link_timeout_disable_link(unsigned long data
);
733 static u32
hisi_sas_read32(struct hisi_hba
*hisi_hba
, u32 off
)
735 void __iomem
*regs
= hisi_hba
->regs
+ off
;
740 static u32
hisi_sas_read32_relaxed(struct hisi_hba
*hisi_hba
, u32 off
)
742 void __iomem
*regs
= hisi_hba
->regs
+ off
;
744 return readl_relaxed(regs
);
747 static void hisi_sas_write32(struct hisi_hba
*hisi_hba
, u32 off
, u32 val
)
749 void __iomem
*regs
= hisi_hba
->regs
+ off
;
754 static void hisi_sas_phy_write32(struct hisi_hba
*hisi_hba
, int phy_no
,
757 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
762 static u32
hisi_sas_phy_read32(struct hisi_hba
*hisi_hba
,
765 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
770 /* This function needs to be protected from pre-emption. */
772 slot_index_alloc_quirk_v2_hw(struct hisi_hba
*hisi_hba
, int *slot_idx
,
773 struct domain_device
*device
)
775 int sata_dev
= dev_is_sata(device
);
776 void *bitmap
= hisi_hba
->slot_index_tags
;
777 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
778 int sata_idx
= sas_dev
->sata_idx
;
783 * STP link SoC bug workaround: index starts from 1.
784 * additionally, we can only allocate odd IPTT(1~4095)
785 * for SAS/SMP device.
788 end
= hisi_hba
->slot_index_count
;
790 if (sata_idx
>= HISI_MAX_SATA_SUPPORT_V2_HW
)
794 * For SATA device: allocate even IPTT in this interval
795 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
796 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
797 * SoC bug workaround. So we ignore the first 32 even IPTTs.
799 start
= 64 * (sata_idx
+ 1);
800 end
= 64 * (sata_idx
+ 2);
804 start
= find_next_zero_bit(bitmap
,
805 hisi_hba
->slot_index_count
, start
);
807 return -SAS_QUEUE_FULL
;
809 * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
811 if (sata_dev
^ (start
& 1))
816 set_bit(start
, bitmap
);
821 static bool sata_index_alloc_v2_hw(struct hisi_hba
*hisi_hba
, int *idx
)
824 struct device
*dev
= hisi_hba
->dev
;
825 void *bitmap
= hisi_hba
->sata_dev_bitmap
;
827 index
= find_first_zero_bit(bitmap
, HISI_MAX_SATA_SUPPORT_V2_HW
);
828 if (index
>= HISI_MAX_SATA_SUPPORT_V2_HW
) {
829 dev_warn(dev
, "alloc sata index failed, index=%d\n", index
);
833 set_bit(index
, bitmap
);
840 hisi_sas_device
*alloc_dev_quirk_v2_hw(struct domain_device
*device
)
842 struct hisi_hba
*hisi_hba
= device
->port
->ha
->lldd_ha
;
843 struct hisi_sas_device
*sas_dev
= NULL
;
844 int i
, sata_dev
= dev_is_sata(device
);
847 spin_lock(&hisi_hba
->lock
);
850 if (!sata_index_alloc_v2_hw(hisi_hba
, &sata_idx
))
853 for (i
= 0; i
< HISI_SAS_MAX_DEVICES
; i
++) {
855 * SATA device id bit0 should be 0
857 if (sata_dev
&& (i
& 1))
859 if (hisi_hba
->devices
[i
].dev_type
== SAS_PHY_UNUSED
) {
860 int queue
= i
% hisi_hba
->queue_count
;
861 struct hisi_sas_dq
*dq
= &hisi_hba
->dq
[queue
];
863 hisi_hba
->devices
[i
].device_id
= i
;
864 sas_dev
= &hisi_hba
->devices
[i
];
865 sas_dev
->dev_status
= HISI_SAS_DEV_NORMAL
;
866 sas_dev
->dev_type
= device
->dev_type
;
867 sas_dev
->hisi_hba
= hisi_hba
;
868 sas_dev
->sas_device
= device
;
869 sas_dev
->sata_idx
= sata_idx
;
871 INIT_LIST_HEAD(&hisi_hba
->devices
[i
].list
);
877 spin_unlock(&hisi_hba
->lock
);
882 static void config_phy_opt_mode_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
884 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
886 cfg
&= ~PHY_CFG_DC_OPT_MSK
;
887 cfg
|= 1 << PHY_CFG_DC_OPT_OFF
;
888 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
891 static void config_id_frame_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
893 struct sas_identify_frame identify_frame
;
894 u32
*identify_buffer
;
896 memset(&identify_frame
, 0, sizeof(identify_frame
));
897 identify_frame
.dev_type
= SAS_END_DEVICE
;
898 identify_frame
.frame_type
= 0;
899 identify_frame
._un1
= 1;
900 identify_frame
.initiator_bits
= SAS_PROTOCOL_ALL
;
901 identify_frame
.target_bits
= SAS_PROTOCOL_NONE
;
902 memcpy(&identify_frame
._un4_11
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
903 memcpy(&identify_frame
.sas_addr
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
904 identify_frame
.phy_id
= phy_no
;
905 identify_buffer
= (u32
*)(&identify_frame
);
907 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD0
,
908 __swab32(identify_buffer
[0]));
909 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD1
,
910 __swab32(identify_buffer
[1]));
911 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD2
,
912 __swab32(identify_buffer
[2]));
913 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD3
,
914 __swab32(identify_buffer
[3]));
915 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD4
,
916 __swab32(identify_buffer
[4]));
917 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD5
,
918 __swab32(identify_buffer
[5]));
921 static void setup_itct_v2_hw(struct hisi_hba
*hisi_hba
,
922 struct hisi_sas_device
*sas_dev
)
924 struct domain_device
*device
= sas_dev
->sas_device
;
925 struct device
*dev
= hisi_hba
->dev
;
926 u64 qw0
, device_id
= sas_dev
->device_id
;
927 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[device_id
];
928 struct domain_device
*parent_dev
= device
->parent
;
929 struct asd_sas_port
*sas_port
= device
->port
;
930 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
932 memset(itct
, 0, sizeof(*itct
));
936 switch (sas_dev
->dev_type
) {
938 case SAS_EDGE_EXPANDER_DEVICE
:
939 case SAS_FANOUT_EXPANDER_DEVICE
:
940 qw0
= HISI_SAS_DEV_TYPE_SSP
<< ITCT_HDR_DEV_TYPE_OFF
;
943 case SAS_SATA_PENDING
:
944 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
945 qw0
= HISI_SAS_DEV_TYPE_STP
<< ITCT_HDR_DEV_TYPE_OFF
;
947 qw0
= HISI_SAS_DEV_TYPE_SATA
<< ITCT_HDR_DEV_TYPE_OFF
;
950 dev_warn(dev
, "setup itct: unsupported dev type (%d)\n",
954 qw0
|= ((1 << ITCT_HDR_VALID_OFF
) |
955 (device
->linkrate
<< ITCT_HDR_MCR_OFF
) |
956 (1 << ITCT_HDR_VLN_OFF
) |
957 (ITCT_HDR_SMP_TIMEOUT
<< ITCT_HDR_SMP_TIMEOUT_OFF
) |
958 (1 << ITCT_HDR_AWT_CONTINUE_OFF
) |
959 (port
->id
<< ITCT_HDR_PORT_ID_OFF
));
960 itct
->qw0
= cpu_to_le64(qw0
);
963 memcpy(&itct
->sas_addr
, device
->sas_addr
, SAS_ADDR_SIZE
);
964 itct
->sas_addr
= __swab64(itct
->sas_addr
);
967 if (!dev_is_sata(device
))
968 itct
->qw2
= cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF
) |
969 (0x1ULL
<< ITCT_HDR_BITLT_OFF
) |
970 (0x32ULL
<< ITCT_HDR_MCTLT_OFF
) |
971 (0x1ULL
<< ITCT_HDR_RTOLT_OFF
));
974 static void free_device_v2_hw(struct hisi_hba
*hisi_hba
,
975 struct hisi_sas_device
*sas_dev
)
977 DECLARE_COMPLETION_ONSTACK(completion
);
978 u64 dev_id
= sas_dev
->device_id
;
979 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[dev_id
];
980 u32 reg_val
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
983 sas_dev
->completion
= &completion
;
985 /* SoC bug workaround */
986 if (dev_is_sata(sas_dev
->sas_device
))
987 clear_bit(sas_dev
->sata_idx
, hisi_hba
->sata_dev_bitmap
);
989 /* clear the itct interrupt state */
990 if (ENT_INT_SRC3_ITC_INT_MSK
& reg_val
)
991 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
992 ENT_INT_SRC3_ITC_INT_MSK
);
994 for (i
= 0; i
< 2; i
++) {
995 reg_val
= ITCT_CLR_EN_MSK
| (dev_id
& ITCT_DEV_MSK
);
996 hisi_sas_write32(hisi_hba
, ITCT_CLR
, reg_val
);
997 wait_for_completion(sas_dev
->completion
);
999 memset(itct
, 0, sizeof(struct hisi_sas_itct
));
1003 static int reset_hw_v2_hw(struct hisi_hba
*hisi_hba
)
1007 unsigned long end_time
;
1008 struct device
*dev
= hisi_hba
->dev
;
1010 /* The mask needs to be set depending on the number of phys */
1011 if (hisi_hba
->n_phy
== 9)
1012 reset_val
= 0x1fffff;
1014 reset_val
= 0x7ffff;
1016 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0);
1018 /* Disable all of the PHYs */
1019 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1020 u32 phy_cfg
= hisi_sas_phy_read32(hisi_hba
, i
, PHY_CFG
);
1022 phy_cfg
&= ~PHY_CTRL_RESET_MSK
;
1023 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CFG
, phy_cfg
);
1027 /* Ensure DMA tx & rx idle */
1028 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1029 u32 dma_tx_status
, dma_rx_status
;
1031 end_time
= jiffies
+ msecs_to_jiffies(1000);
1034 dma_tx_status
= hisi_sas_phy_read32(hisi_hba
, i
,
1036 dma_rx_status
= hisi_sas_phy_read32(hisi_hba
, i
,
1039 if (!(dma_tx_status
& DMA_TX_STATUS_BUSY_MSK
) &&
1040 !(dma_rx_status
& DMA_RX_STATUS_BUSY_MSK
))
1044 if (time_after(jiffies
, end_time
))
1049 /* Ensure axi bus idle */
1050 end_time
= jiffies
+ msecs_to_jiffies(1000);
1053 hisi_sas_read32(hisi_hba
, AXI_CFG
);
1055 if (axi_status
== 0)
1059 if (time_after(jiffies
, end_time
))
1063 if (ACPI_HANDLE(dev
)) {
1066 s
= acpi_evaluate_object(ACPI_HANDLE(dev
), "_RST", NULL
, NULL
);
1067 if (ACPI_FAILURE(s
)) {
1068 dev_err(dev
, "Reset failed\n");
1071 } else if (hisi_hba
->ctrl
) {
1072 /* reset and disable clock*/
1073 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_reg
,
1075 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_clock_ena_reg
+ 4,
1078 regmap_read(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_sts_reg
, &val
);
1079 if (reset_val
!= (val
& reset_val
)) {
1080 dev_err(dev
, "SAS reset fail.\n");
1084 /* De-reset and enable clock*/
1085 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_reg
+ 4,
1087 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_clock_ena_reg
,
1090 regmap_read(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_sts_reg
,
1092 if (val
& reset_val
) {
1093 dev_err(dev
, "SAS de-reset fail.\n");
1097 dev_warn(dev
, "no reset method\n");
1102 /* This function needs to be called after resetting SAS controller. */
1103 static void phys_reject_stp_links_v2_hw(struct hisi_hba
*hisi_hba
)
1108 hisi_hba
->reject_stp_links_msk
= (1 << hisi_hba
->n_phy
) - 1;
1109 for (phy_no
= 0; phy_no
< hisi_hba
->n_phy
; phy_no
++) {
1110 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, CON_CONTROL
);
1111 if (!(cfg
& CON_CONTROL_CFG_OPEN_ACC_STP_MSK
))
1114 cfg
&= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK
;
1115 hisi_sas_phy_write32(hisi_hba
, phy_no
, CON_CONTROL
, cfg
);
1119 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba
*hisi_hba
)
1124 for (phy_no
= 0; phy_no
< hisi_hba
->n_phy
; phy_no
++) {
1125 if (!(hisi_hba
->reject_stp_links_msk
& BIT(phy_no
)))
1128 dma_tx_dfx1
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1130 if (dma_tx_dfx1
& DMA_TX_DFX1_IPTT_MSK
) {
1131 u32 cfg
= hisi_sas_phy_read32(hisi_hba
,
1132 phy_no
, CON_CONTROL
);
1134 cfg
|= CON_CONTROL_CFG_OPEN_ACC_STP_MSK
;
1135 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1137 clear_bit(phy_no
, &hisi_hba
->reject_stp_links_msk
);
1142 static void init_reg_v2_hw(struct hisi_hba
*hisi_hba
)
1144 struct device
*dev
= hisi_hba
->dev
;
1147 /* Global registers init */
1149 /* Deal with am-max-transmissions quirk */
1150 if (device_property_present(dev
, "hip06-sas-v2-quirk-amt")) {
1151 hisi_sas_write32(hisi_hba
, AM_CFG_MAX_TRANS
, 0x2020);
1152 hisi_sas_write32(hisi_hba
, AM_CFG_SINGLE_PORT_MAX_TRANS
,
1154 } /* Else, use defaults -> do nothing */
1156 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
,
1157 (u32
)((1ULL << hisi_hba
->queue_count
) - 1));
1158 hisi_sas_write32(hisi_hba
, AXI_USER1
, 0xc0000000);
1159 hisi_sas_write32(hisi_hba
, AXI_USER2
, 0x10000);
1160 hisi_sas_write32(hisi_hba
, HGC_SAS_TXFAIL_RETRY_CTRL
, 0x0);
1161 hisi_sas_write32(hisi_hba
, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL
, 0x7FF);
1162 hisi_sas_write32(hisi_hba
, OPENA_WT_CONTI_TIME
, 0x1);
1163 hisi_sas_write32(hisi_hba
, I_T_NEXUS_LOSS_TIME
, 0x1F4);
1164 hisi_sas_write32(hisi_hba
, MAX_CON_TIME_LIMIT_TIME
, 0x32);
1165 hisi_sas_write32(hisi_hba
, BUS_INACTIVE_LIMIT_TIME
, 0x1);
1166 hisi_sas_write32(hisi_hba
, CFG_AGING_TIME
, 0x1);
1167 hisi_sas_write32(hisi_hba
, HGC_ERR_STAT_EN
, 0x1);
1168 hisi_sas_write32(hisi_hba
, HGC_GET_ITV_TIME
, 0x1);
1169 hisi_sas_write32(hisi_hba
, INT_COAL_EN
, 0xc);
1170 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_TIME
, 0x60);
1171 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_CNT
, 0x3);
1172 hisi_sas_write32(hisi_hba
, ENT_INT_COAL_TIME
, 0x1);
1173 hisi_sas_write32(hisi_hba
, ENT_INT_COAL_CNT
, 0x1);
1174 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 0x0);
1175 hisi_sas_write32(hisi_hba
, ENT_INT_SRC1
, 0xffffffff);
1176 hisi_sas_write32(hisi_hba
, ENT_INT_SRC2
, 0xffffffff);
1177 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
, 0xffffffff);
1178 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0x7efefefe);
1179 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0x7efefefe);
1180 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0x7ffe20fe);
1181 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0xfff00c30);
1182 for (i
= 0; i
< hisi_hba
->queue_count
; i
++)
1183 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+0x4*i
, 0);
1185 hisi_sas_write32(hisi_hba
, AXI_AHB_CLK_CFG
, 1);
1186 hisi_sas_write32(hisi_hba
, HYPER_STREAM_ID_EN_CFG
, 1);
1188 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1189 hisi_sas_phy_write32(hisi_hba
, i
, PROG_PHY_LINK_RATE
, 0x855);
1190 hisi_sas_phy_write32(hisi_hba
, i
, SAS_PHY_CTRL
, 0x30b9908);
1191 hisi_sas_phy_write32(hisi_hba
, i
, SL_TOUT_CFG
, 0x7d7d7d7d);
1192 hisi_sas_phy_write32(hisi_hba
, i
, SL_CONTROL
, 0x0);
1193 hisi_sas_phy_write32(hisi_hba
, i
, TXID_AUTO
, 0x2);
1194 hisi_sas_phy_write32(hisi_hba
, i
, DONE_RECEIVED_TIME
, 0x8);
1195 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT0
, 0xffffffff);
1196 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1
, 0xffffffff);
1197 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2
, 0xfff87fff);
1198 hisi_sas_phy_write32(hisi_hba
, i
, RXOP_CHECK_CFG_H
, 0x1000);
1199 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xffffffff);
1200 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0x8ffffbff);
1201 hisi_sas_phy_write32(hisi_hba
, i
, SL_CFG
, 0x13f801fc);
1202 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL_RDY_MSK
, 0x0);
1203 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_NOT_RDY_MSK
, 0x0);
1204 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_DWS_RESET_MSK
, 0x0);
1205 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_PHY_ENA_MSK
, 0x0);
1206 hisi_sas_phy_write32(hisi_hba
, i
, SL_RX_BCAST_CHK_MSK
, 0x0);
1207 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT_COAL_EN
, 0x0);
1208 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_OOB_RESTART_MSK
, 0x0);
1209 if (hisi_hba
->refclk_frequency_mhz
== 66)
1210 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL
, 0x199B694);
1211 /* else, do nothing -> leave it how you found it */
1214 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
1215 /* Delivery queue */
1216 hisi_sas_write32(hisi_hba
,
1217 DLVRY_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
1218 upper_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
1220 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
1221 lower_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
1223 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_DEPTH
+ (i
* 0x14),
1224 HISI_SAS_QUEUE_SLOTS
);
1226 /* Completion queue */
1227 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
1228 upper_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
1230 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
1231 lower_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
1233 hisi_sas_write32(hisi_hba
, COMPL_Q_0_DEPTH
+ (i
* 0x14),
1234 HISI_SAS_QUEUE_SLOTS
);
1238 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_LO
,
1239 lower_32_bits(hisi_hba
->itct_dma
));
1241 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_HI
,
1242 upper_32_bits(hisi_hba
->itct_dma
));
1245 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_LO
,
1246 lower_32_bits(hisi_hba
->iost_dma
));
1248 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_HI
,
1249 upper_32_bits(hisi_hba
->iost_dma
));
1252 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_LO
,
1253 lower_32_bits(hisi_hba
->breakpoint_dma
));
1255 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_HI
,
1256 upper_32_bits(hisi_hba
->breakpoint_dma
));
1258 /* SATA broken msg */
1259 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_LO
,
1260 lower_32_bits(hisi_hba
->sata_breakpoint_dma
));
1262 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_HI
,
1263 upper_32_bits(hisi_hba
->sata_breakpoint_dma
));
1265 /* SATA initial fis */
1266 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_LO
,
1267 lower_32_bits(hisi_hba
->initial_fis_dma
));
1269 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_HI
,
1270 upper_32_bits(hisi_hba
->initial_fis_dma
));
1273 static void link_timeout_enable_link(unsigned long data
)
1275 struct hisi_hba
*hisi_hba
= (struct hisi_hba
*)data
;
1278 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1279 if (hisi_hba
->reject_stp_links_msk
& BIT(i
))
1282 reg_val
= hisi_sas_phy_read32(hisi_hba
, i
, CON_CONTROL
);
1283 if (!(reg_val
& BIT(0))) {
1284 hisi_sas_phy_write32(hisi_hba
, i
,
1290 hisi_hba
->timer
.function
= link_timeout_disable_link
;
1291 mod_timer(&hisi_hba
->timer
, jiffies
+ msecs_to_jiffies(900));
1294 static void link_timeout_disable_link(unsigned long data
)
1296 struct hisi_hba
*hisi_hba
= (struct hisi_hba
*)data
;
1299 reg_val
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1300 for (i
= 0; i
< hisi_hba
->n_phy
&& reg_val
; i
++) {
1301 if (hisi_hba
->reject_stp_links_msk
& BIT(i
))
1304 if (reg_val
& BIT(i
)) {
1305 hisi_sas_phy_write32(hisi_hba
, i
,
1311 hisi_hba
->timer
.function
= link_timeout_enable_link
;
1312 mod_timer(&hisi_hba
->timer
, jiffies
+ msecs_to_jiffies(100));
1315 static void set_link_timer_quirk(struct hisi_hba
*hisi_hba
)
1317 hisi_hba
->timer
.data
= (unsigned long)hisi_hba
;
1318 hisi_hba
->timer
.function
= link_timeout_disable_link
;
1319 hisi_hba
->timer
.expires
= jiffies
+ msecs_to_jiffies(1000);
1320 add_timer(&hisi_hba
->timer
);
1323 static int hw_init_v2_hw(struct hisi_hba
*hisi_hba
)
1325 struct device
*dev
= hisi_hba
->dev
;
1328 rc
= reset_hw_v2_hw(hisi_hba
);
1330 dev_err(dev
, "hisi_sas_reset_hw failed, rc=%d", rc
);
1335 init_reg_v2_hw(hisi_hba
);
1340 static void enable_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1342 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
1344 cfg
|= PHY_CFG_ENA_MSK
;
1345 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
1348 static bool is_sata_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1352 context
= hisi_sas_read32(hisi_hba
, PHY_CONTEXT
);
1353 if (context
& (1 << phy_no
))
1359 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1363 dfx_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, DMA_TX_DFX1
);
1365 if (dfx_val
& BIT(16))
1371 static bool axi_bus_is_idle_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1373 int i
, max_loop
= 1000;
1374 struct device
*dev
= hisi_hba
->dev
;
1375 u32 status
, axi_status
, dfx_val
, dfx_tx_val
;
1377 for (i
= 0; i
< max_loop
; i
++) {
1378 status
= hisi_sas_read32_relaxed(hisi_hba
,
1379 AXI_MASTER_CFG_BASE
+ AM_CURR_TRANS_RETURN
);
1381 axi_status
= hisi_sas_read32(hisi_hba
, AXI_CFG
);
1382 dfx_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, DMA_TX_DFX1
);
1383 dfx_tx_val
= hisi_sas_phy_read32(hisi_hba
,
1384 phy_no
, DMA_TX_FIFO_DFX0
);
1386 if ((status
== 0x3) && (axi_status
== 0x0) &&
1387 (dfx_val
& BIT(20)) && (dfx_tx_val
& BIT(10)))
1391 dev_err(dev
, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1392 phy_no
, status
, axi_status
,
1393 dfx_val
, dfx_tx_val
);
1397 static bool wait_io_done_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1399 int i
, max_loop
= 1000;
1400 struct device
*dev
= hisi_hba
->dev
;
1401 u32 status
, tx_dfx0
;
1403 for (i
= 0; i
< max_loop
; i
++) {
1404 status
= hisi_sas_phy_read32(hisi_hba
, phy_no
, LINK_DFX2
);
1405 status
= (status
& 0x3fc0) >> 6;
1410 tx_dfx0
= hisi_sas_phy_read32(hisi_hba
, phy_no
, DMA_TX_DFX0
);
1411 if ((tx_dfx0
& 0x1ff) == 0x2)
1415 dev_err(dev
, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1416 phy_no
, status
, tx_dfx0
);
1420 static bool allowed_disable_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1422 if (tx_fifo_is_empty_v2_hw(hisi_hba
, phy_no
))
1425 if (!axi_bus_is_idle_v2_hw(hisi_hba
, phy_no
))
1428 if (!wait_io_done_v2_hw(hisi_hba
, phy_no
))
1435 static void disable_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1437 u32 cfg
, axi_val
, dfx0_val
, txid_auto
;
1438 struct device
*dev
= hisi_hba
->dev
;
1440 /* Close axi bus. */
1441 axi_val
= hisi_sas_read32(hisi_hba
, AXI_MASTER_CFG_BASE
+
1444 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
+
1445 AM_CTRL_GLOBAL
, axi_val
);
1447 if (is_sata_phy_v2_hw(hisi_hba
, phy_no
)) {
1448 if (allowed_disable_phy_v2_hw(hisi_hba
, phy_no
))
1451 /* Reset host controller. */
1452 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
1456 dfx0_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PORT_DFX0
);
1457 dfx0_val
= (dfx0_val
& 0x1fc0) >> 6;
1458 if (dfx0_val
!= 0x4)
1461 if (!tx_fifo_is_empty_v2_hw(hisi_hba
, phy_no
)) {
1462 dev_warn(dev
, "phy%d, wait tx fifo need send break\n",
1464 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1466 txid_auto
|= TXID_AUTO_CTB_MSK
;
1467 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
1472 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
1473 cfg
&= ~PHY_CFG_ENA_MSK
;
1474 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
1478 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
+
1479 AM_CTRL_GLOBAL
, axi_val
);
1482 static void start_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1484 config_id_frame_v2_hw(hisi_hba
, phy_no
);
1485 config_phy_opt_mode_v2_hw(hisi_hba
, phy_no
);
1486 enable_phy_v2_hw(hisi_hba
, phy_no
);
1489 static void stop_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1491 disable_phy_v2_hw(hisi_hba
, phy_no
);
1494 static void stop_phys_v2_hw(struct hisi_hba
*hisi_hba
)
1498 for (i
= 0; i
< hisi_hba
->n_phy
; i
++)
1499 stop_phy_v2_hw(hisi_hba
, i
);
1502 static void phy_hard_reset_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1504 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1507 stop_phy_v2_hw(hisi_hba
, phy_no
);
1508 if (phy
->identify
.device_type
== SAS_END_DEVICE
) {
1509 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
1510 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
1511 txid_auto
| TX_HARDRST_MSK
);
1514 start_phy_v2_hw(hisi_hba
, phy_no
);
1517 static void phy_get_events_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1519 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1520 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1521 struct sas_phy
*sphy
= sas_phy
->phy
;
1522 u32 err4_reg_val
, err6_reg_val
;
1524 /* loss dword syn, phy reset problem */
1525 err4_reg_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SAS_ERR_CNT4_REG
);
1527 /* disparity err, invalid dword */
1528 err6_reg_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SAS_ERR_CNT6_REG
);
1530 sphy
->loss_of_dword_sync_count
+= (err4_reg_val
>> 16) & 0xFFFF;
1531 sphy
->phy_reset_problem_count
+= err4_reg_val
& 0xFFFF;
1532 sphy
->invalid_dword_count
+= (err6_reg_val
& 0xFF0000) >> 16;
1533 sphy
->running_disparity_error_count
+= err6_reg_val
& 0xFF;
1536 static void start_phys_v2_hw(struct hisi_hba
*hisi_hba
)
1540 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1541 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[i
];
1542 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1544 if (!sas_phy
->phy
->enabled
)
1547 start_phy_v2_hw(hisi_hba
, i
);
1551 static void phys_init_v2_hw(struct hisi_hba
*hisi_hba
)
1553 start_phys_v2_hw(hisi_hba
);
1556 static void sl_notify_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1560 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
1561 sl_control
|= SL_CONTROL_NOTIFY_EN_MSK
;
1562 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
1564 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
1565 sl_control
&= ~SL_CONTROL_NOTIFY_EN_MSK
;
1566 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
1569 static enum sas_linkrate
phy_get_max_linkrate_v2_hw(void)
1571 return SAS_LINK_RATE_12_0_GBPS
;
1574 static void phy_set_linkrate_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
,
1575 struct sas_phy_linkrates
*r
)
1577 u32 prog_phy_link_rate
=
1578 hisi_sas_phy_read32(hisi_hba
, phy_no
, PROG_PHY_LINK_RATE
);
1579 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1580 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1582 enum sas_linkrate min
, max
;
1585 if (r
->maximum_linkrate
== SAS_LINK_RATE_UNKNOWN
) {
1586 max
= sas_phy
->phy
->maximum_linkrate
;
1587 min
= r
->minimum_linkrate
;
1588 } else if (r
->minimum_linkrate
== SAS_LINK_RATE_UNKNOWN
) {
1589 max
= r
->maximum_linkrate
;
1590 min
= sas_phy
->phy
->minimum_linkrate
;
1594 sas_phy
->phy
->maximum_linkrate
= max
;
1595 sas_phy
->phy
->minimum_linkrate
= min
;
1597 min
-= SAS_LINK_RATE_1_5_GBPS
;
1598 max
-= SAS_LINK_RATE_1_5_GBPS
;
1600 for (i
= 0; i
<= max
; i
++)
1601 rate_mask
|= 1 << (i
* 2);
1603 prog_phy_link_rate
&= ~0xff;
1604 prog_phy_link_rate
|= rate_mask
;
1606 hisi_sas_phy_write32(hisi_hba
, phy_no
, PROG_PHY_LINK_RATE
,
1607 prog_phy_link_rate
);
1609 phy_hard_reset_v2_hw(hisi_hba
, phy_no
);
1612 static int get_wideport_bitmap_v2_hw(struct hisi_hba
*hisi_hba
, int port_id
)
1615 u32 phy_port_num_ma
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
1616 u32 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1618 for (i
= 0; i
< (hisi_hba
->n_phy
< 9 ? hisi_hba
->n_phy
: 8); i
++)
1619 if (phy_state
& 1 << i
)
1620 if (((phy_port_num_ma
>> (i
* 4)) & 0xf) == port_id
)
1623 if (hisi_hba
->n_phy
== 9) {
1624 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
1626 if (phy_state
& 1 << 8)
1627 if (((port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
1628 PORT_STATE_PHY8_PORT_NUM_OFF
) == port_id
)
1636 * The callpath to this function and upto writing the write
1637 * queue pointer should be safe from interruption.
1640 get_free_slot_v2_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_dq
*dq
)
1642 struct device
*dev
= hisi_hba
->dev
;
1647 r
= hisi_sas_read32_relaxed(hisi_hba
,
1648 DLVRY_Q_0_RD_PTR
+ (queue
* 0x14));
1649 if (r
== (w
+1) % HISI_SAS_QUEUE_SLOTS
) {
1650 dev_warn(dev
, "full queue=%d r=%d w=%d\n\n",
1658 static void start_delivery_v2_hw(struct hisi_sas_dq
*dq
)
1660 struct hisi_hba
*hisi_hba
= dq
->hisi_hba
;
1661 int dlvry_queue
= dq
->slot_prep
->dlvry_queue
;
1662 int dlvry_queue_slot
= dq
->slot_prep
->dlvry_queue_slot
;
1664 dq
->wr_point
= ++dlvry_queue_slot
% HISI_SAS_QUEUE_SLOTS
;
1665 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_WR_PTR
+ (dlvry_queue
* 0x14),
1669 static int prep_prd_sge_v2_hw(struct hisi_hba
*hisi_hba
,
1670 struct hisi_sas_slot
*slot
,
1671 struct hisi_sas_cmd_hdr
*hdr
,
1672 struct scatterlist
*scatter
,
1675 struct hisi_sas_sge_page
*sge_page
= hisi_sas_sge_addr_mem(slot
);
1676 struct device
*dev
= hisi_hba
->dev
;
1677 struct scatterlist
*sg
;
1680 if (n_elem
> HISI_SAS_SGE_PAGE_CNT
) {
1681 dev_err(dev
, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1686 for_each_sg(scatter
, sg
, n_elem
, i
) {
1687 struct hisi_sas_sge
*entry
= &sge_page
->sge
[i
];
1689 entry
->addr
= cpu_to_le64(sg_dma_address(sg
));
1690 entry
->page_ctrl_0
= entry
->page_ctrl_1
= 0;
1691 entry
->data_len
= cpu_to_le32(sg_dma_len(sg
));
1692 entry
->data_off
= 0;
1695 hdr
->prd_table_addr
= cpu_to_le64(hisi_sas_sge_addr_dma(slot
));
1697 hdr
->sg_len
= cpu_to_le32(n_elem
<< CMD_HDR_DATA_SGL_LEN_OFF
);
1702 static int prep_smp_v2_hw(struct hisi_hba
*hisi_hba
,
1703 struct hisi_sas_slot
*slot
)
1705 struct sas_task
*task
= slot
->task
;
1706 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1707 struct domain_device
*device
= task
->dev
;
1708 struct device
*dev
= hisi_hba
->dev
;
1709 struct hisi_sas_port
*port
= slot
->port
;
1710 struct scatterlist
*sg_req
, *sg_resp
;
1711 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
1712 dma_addr_t req_dma_addr
;
1713 unsigned int req_len
, resp_len
;
1717 * DMA-map SMP request, response buffers
1720 sg_req
= &task
->smp_task
.smp_req
;
1721 elem
= dma_map_sg(dev
, sg_req
, 1, DMA_TO_DEVICE
);
1724 req_len
= sg_dma_len(sg_req
);
1725 req_dma_addr
= sg_dma_address(sg_req
);
1728 sg_resp
= &task
->smp_task
.smp_resp
;
1729 elem
= dma_map_sg(dev
, sg_resp
, 1, DMA_FROM_DEVICE
);
1734 resp_len
= sg_dma_len(sg_resp
);
1735 if ((req_len
& 0x3) || (resp_len
& 0x3)) {
1742 hdr
->dw0
= cpu_to_le32((port
->id
<< CMD_HDR_PORT_OFF
) |
1743 (1 << CMD_HDR_PRIORITY_OFF
) | /* high pri */
1744 (2 << CMD_HDR_CMD_OFF
)); /* smp */
1746 /* map itct entry */
1747 hdr
->dw1
= cpu_to_le32((sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
) |
1748 (1 << CMD_HDR_FRAME_TYPE_OFF
) |
1749 (DIR_NO_DATA
<< CMD_HDR_DIR_OFF
));
1752 hdr
->dw2
= cpu_to_le32((((req_len
- 4) / 4) << CMD_HDR_CFL_OFF
) |
1753 (HISI_SAS_MAX_SMP_RESP_SZ
/ 4 <<
1756 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
<< CMD_HDR_IPTT_OFF
);
1758 hdr
->cmd_table_addr
= cpu_to_le64(req_dma_addr
);
1759 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
1764 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_resp
, 1,
1767 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_req
, 1,
1772 static int prep_ssp_v2_hw(struct hisi_hba
*hisi_hba
,
1773 struct hisi_sas_slot
*slot
, int is_tmf
,
1774 struct hisi_sas_tmf_task
*tmf
)
1776 struct sas_task
*task
= slot
->task
;
1777 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1778 struct domain_device
*device
= task
->dev
;
1779 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
1780 struct hisi_sas_port
*port
= slot
->port
;
1781 struct sas_ssp_task
*ssp_task
= &task
->ssp_task
;
1782 struct scsi_cmnd
*scsi_cmnd
= ssp_task
->cmd
;
1783 int has_data
= 0, rc
, priority
= is_tmf
;
1785 u32 dw1
= 0, dw2
= 0;
1787 hdr
->dw0
= cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF
) |
1788 (2 << CMD_HDR_TLR_CTRL_OFF
) |
1789 (port
->id
<< CMD_HDR_PORT_OFF
) |
1790 (priority
<< CMD_HDR_PRIORITY_OFF
) |
1791 (1 << CMD_HDR_CMD_OFF
)); /* ssp */
1793 dw1
= 1 << CMD_HDR_VDTL_OFF
;
1795 dw1
|= 2 << CMD_HDR_FRAME_TYPE_OFF
;
1796 dw1
|= DIR_NO_DATA
<< CMD_HDR_DIR_OFF
;
1798 dw1
|= 1 << CMD_HDR_FRAME_TYPE_OFF
;
1799 switch (scsi_cmnd
->sc_data_direction
) {
1802 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
1804 case DMA_FROM_DEVICE
:
1806 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
1809 dw1
&= ~CMD_HDR_DIR_MSK
;
1813 /* map itct entry */
1814 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
1815 hdr
->dw1
= cpu_to_le32(dw1
);
1817 dw2
= (((sizeof(struct ssp_command_iu
) + sizeof(struct ssp_frame_hdr
)
1818 + 3) / 4) << CMD_HDR_CFL_OFF
) |
1819 ((HISI_SAS_MAX_SSP_RESP_SZ
/ 4) << CMD_HDR_MRFL_OFF
) |
1820 (2 << CMD_HDR_SG_MOD_OFF
);
1821 hdr
->dw2
= cpu_to_le32(dw2
);
1823 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
1826 rc
= prep_prd_sge_v2_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
1832 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
1833 hdr
->cmd_table_addr
= cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot
));
1834 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
1836 buf_cmd
= hisi_sas_cmd_hdr_addr_mem(slot
) +
1837 sizeof(struct ssp_frame_hdr
);
1839 memcpy(buf_cmd
, &task
->ssp_task
.LUN
, 8);
1841 buf_cmd
[9] = task
->ssp_task
.task_attr
|
1842 (task
->ssp_task
.task_prio
<< 3);
1843 memcpy(buf_cmd
+ 12, task
->ssp_task
.cmd
->cmnd
,
1844 task
->ssp_task
.cmd
->cmd_len
);
1846 buf_cmd
[10] = tmf
->tmf
;
1848 case TMF_ABORT_TASK
:
1849 case TMF_QUERY_TASK
:
1851 (tmf
->tag_of_task_to_be_managed
>> 8) & 0xff;
1853 tmf
->tag_of_task_to_be_managed
& 0xff;
1863 #define TRANS_TX_ERR 0
1864 #define TRANS_RX_ERR 1
1865 #define DMA_TX_ERR 2
1866 #define SIPC_RX_ERR 3
1867 #define DMA_RX_ERR 4
1869 #define DMA_TX_ERR_OFF 0
1870 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1871 #define SIPC_RX_ERR_OFF 16
1872 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1874 static int parse_trans_tx_err_code_v2_hw(u32 err_msk
)
1876 static const u8 trans_tx_err_code_prio
[] = {
1877 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
,
1878 TRANS_TX_ERR_PHY_NOT_ENABLE
,
1879 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
,
1880 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
,
1881 TRANS_TX_OPEN_CNX_ERR_BY_OTHER
,
1883 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
,
1884 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
,
1885 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
,
1886 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
,
1887 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
,
1888 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
,
1889 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
,
1890 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
,
1891 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
,
1892 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
,
1893 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
,
1894 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
,
1895 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
,
1896 TRANS_TX_ERR_WITH_CLOSE_COMINIT
,
1897 TRANS_TX_ERR_WITH_BREAK_TIMEOUT
,
1898 TRANS_TX_ERR_WITH_BREAK_REQUEST
,
1899 TRANS_TX_ERR_WITH_BREAK_RECEVIED
,
1900 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
,
1901 TRANS_TX_ERR_WITH_CLOSE_NORMAL
,
1902 TRANS_TX_ERR_WITH_NAK_RECEVIED
,
1903 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
,
1904 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
,
1905 TRANS_TX_ERR_WITH_IPTT_CONFLICT
,
1906 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS
,
1907 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
,
1911 for (i
= 0; i
< ARRAY_SIZE(trans_tx_err_code_prio
); i
++) {
1912 index
= trans_tx_err_code_prio
[i
] - TRANS_TX_FAIL_BASE
;
1913 if (err_msk
& (1 << index
))
1914 return trans_tx_err_code_prio
[i
];
1919 static int parse_trans_rx_err_code_v2_hw(u32 err_msk
)
1921 static const u8 trans_rx_err_code_prio
[] = {
1922 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
,
1923 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
,
1924 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
,
1925 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
,
1926 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
,
1927 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
,
1928 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
,
1929 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
,
1930 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
,
1931 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
,
1932 TRANS_RX_ERR_WITH_CLOSE_COMINIT
,
1933 TRANS_RX_ERR_WITH_BREAK_TIMEOUT
,
1934 TRANS_RX_ERR_WITH_BREAK_REQUEST
,
1935 TRANS_RX_ERR_WITH_BREAK_RECEVIED
,
1937 TRANS_RX_ERR_WITH_CLOSE_NORMAL
,
1938 TRANS_RX_ERR_WITH_DATA_LEN0
,
1939 TRANS_RX_ERR_WITH_BAD_HASH
,
1940 TRANS_RX_XRDY_WLEN_ZERO_ERR
,
1941 TRANS_RX_SSP_FRM_LEN_ERR
,
1946 TRANS_RX_ERR_WITH_BAD_FRM_TYPE
,
1947 TRANS_RX_SMP_FRM_LEN_ERR
,
1948 TRANS_RX_SMP_RESP_TIMEOUT_ERR
,
1957 for (i
= 0; i
< ARRAY_SIZE(trans_rx_err_code_prio
); i
++) {
1958 index
= trans_rx_err_code_prio
[i
] - TRANS_RX_FAIL_BASE
;
1959 if (err_msk
& (1 << index
))
1960 return trans_rx_err_code_prio
[i
];
1965 static int parse_dma_tx_err_code_v2_hw(u32 err_msk
)
1967 static const u8 dma_tx_err_code_prio
[] = {
1968 DMA_TX_UNEXP_XFER_ERR
,
1969 DMA_TX_UNEXP_RETRANS_ERR
,
1970 DMA_TX_XFER_LEN_OVERFLOW
,
1971 DMA_TX_XFER_OFFSET_ERR
,
1973 DMA_TX_DIF_LEN_ALIGN_ERR
,
1977 DMA_TX_DATA_SGL_OVERFLOW
,
1978 DMA_TX_DIF_SGL_OVERFLOW
,
1982 for (i
= 0; i
< ARRAY_SIZE(dma_tx_err_code_prio
); i
++) {
1983 index
= dma_tx_err_code_prio
[i
] - DMA_TX_ERR_BASE
;
1984 err_msk
= err_msk
& DMA_TX_ERR_MSK
;
1985 if (err_msk
& (1 << index
))
1986 return dma_tx_err_code_prio
[i
];
1991 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk
)
1993 static const u8 sipc_rx_err_code_prio
[] = {
1994 SIPC_RX_FIS_STATUS_ERR_BIT_VLD
,
1995 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR
,
1996 SIPC_RX_FIS_STATUS_BSY_BIT_ERR
,
1997 SIPC_RX_WRSETUP_LEN_ODD_ERR
,
1998 SIPC_RX_WRSETUP_LEN_ZERO_ERR
,
1999 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR
,
2000 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR
,
2001 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR
,
2002 SIPC_RX_SATA_UNEXP_FIS_ERR
,
2003 SIPC_RX_WRSETUP_ESTATUS_ERR
,
2004 SIPC_RX_DATA_UNDERFLOW_ERR
,
2008 for (i
= 0; i
< ARRAY_SIZE(sipc_rx_err_code_prio
); i
++) {
2009 index
= sipc_rx_err_code_prio
[i
] - SIPC_RX_ERR_BASE
;
2010 err_msk
= err_msk
& SIPC_RX_ERR_MSK
;
2011 if (err_msk
& (1 << (index
+ 0x10)))
2012 return sipc_rx_err_code_prio
[i
];
2017 static int parse_dma_rx_err_code_v2_hw(u32 err_msk
)
2019 static const u8 dma_rx_err_code_prio
[] = {
2020 DMA_RX_UNKNOWN_FRM_ERR
,
2021 DMA_RX_DATA_LEN_OVERFLOW
,
2022 DMA_RX_DATA_LEN_UNDERFLOW
,
2023 DMA_RX_DATA_OFFSET_ERR
,
2025 DMA_RX_SATA_FRAME_TYPE_ERR
,
2026 DMA_RX_RESP_BUF_OVERFLOW
,
2027 DMA_RX_UNEXP_RETRANS_RESP_ERR
,
2028 DMA_RX_UNEXP_NORM_RESP_ERR
,
2029 DMA_RX_UNEXP_RDFRAME_ERR
,
2030 DMA_RX_PIO_DATA_LEN_ERR
,
2031 DMA_RX_RDSETUP_STATUS_ERR
,
2032 DMA_RX_RDSETUP_STATUS_DRQ_ERR
,
2033 DMA_RX_RDSETUP_STATUS_BSY_ERR
,
2034 DMA_RX_RDSETUP_LEN_ODD_ERR
,
2035 DMA_RX_RDSETUP_LEN_ZERO_ERR
,
2036 DMA_RX_RDSETUP_LEN_OVER_ERR
,
2037 DMA_RX_RDSETUP_OFFSET_ERR
,
2038 DMA_RX_RDSETUP_ACTIVE_ERR
,
2039 DMA_RX_RDSETUP_ESTATUS_ERR
,
2044 DMA_RX_DATA_SGL_OVERFLOW
,
2045 DMA_RX_DIF_SGL_OVERFLOW
,
2049 for (i
= 0; i
< ARRAY_SIZE(dma_rx_err_code_prio
); i
++) {
2050 index
= dma_rx_err_code_prio
[i
] - DMA_RX_ERR_BASE
;
2051 if (err_msk
& (1 << index
))
2052 return dma_rx_err_code_prio
[i
];
2057 /* by default, task resp is complete */
2058 static void slot_err_v2_hw(struct hisi_hba
*hisi_hba
,
2059 struct sas_task
*task
,
2060 struct hisi_sas_slot
*slot
,
2063 struct task_status_struct
*ts
= &task
->task_status
;
2064 struct hisi_sas_err_record_v2
*err_record
=
2065 hisi_sas_status_buf_addr_mem(slot
);
2066 u32 trans_tx_fail_type
= cpu_to_le32(err_record
->trans_tx_fail_type
);
2067 u32 trans_rx_fail_type
= cpu_to_le32(err_record
->trans_rx_fail_type
);
2068 u16 dma_tx_err_type
= cpu_to_le16(err_record
->dma_tx_err_type
);
2069 u16 sipc_rx_err_type
= cpu_to_le16(err_record
->sipc_rx_err_type
);
2070 u32 dma_rx_err_type
= cpu_to_le32(err_record
->dma_rx_err_type
);
2073 if (err_phase
== 1) {
2074 /* error in TX phase, the priority of error is: DW2 > DW0 */
2075 error
= parse_dma_tx_err_code_v2_hw(dma_tx_err_type
);
2077 error
= parse_trans_tx_err_code_v2_hw(
2078 trans_tx_fail_type
);
2079 } else if (err_phase
== 2) {
2080 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2081 error
= parse_trans_rx_err_code_v2_hw(
2082 trans_rx_fail_type
);
2084 error
= parse_dma_rx_err_code_v2_hw(
2087 error
= parse_sipc_rx_err_code_v2_hw(
2092 switch (task
->task_proto
) {
2093 case SAS_PROTOCOL_SSP
:
2096 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
:
2098 ts
->stat
= SAS_OPEN_REJECT
;
2099 ts
->open_rej_reason
= SAS_OREJ_NO_DEST
;
2102 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
:
2104 ts
->stat
= SAS_OPEN_REJECT
;
2105 ts
->open_rej_reason
= SAS_OREJ_EPROTO
;
2108 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
:
2110 ts
->stat
= SAS_OPEN_REJECT
;
2111 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
2114 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
:
2116 ts
->stat
= SAS_OPEN_REJECT
;
2117 ts
->open_rej_reason
= SAS_OREJ_BAD_DEST
;
2120 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
:
2122 ts
->stat
= SAS_OPEN_REJECT
;
2123 ts
->open_rej_reason
= SAS_OREJ_WRONG_DEST
;
2126 case DMA_RX_UNEXP_NORM_RESP_ERR
:
2127 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
:
2128 case DMA_RX_RESP_BUF_OVERFLOW
:
2130 ts
->stat
= SAS_OPEN_REJECT
;
2131 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
2134 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
:
2137 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2140 case DMA_RX_DATA_LEN_OVERFLOW
:
2142 ts
->stat
= SAS_DATA_OVERRUN
;
2146 case DMA_RX_DATA_LEN_UNDERFLOW
:
2148 ts
->residual
= trans_tx_fail_type
;
2149 ts
->stat
= SAS_DATA_UNDERRUN
;
2152 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
:
2153 case TRANS_TX_ERR_PHY_NOT_ENABLE
:
2154 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER
:
2155 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
:
2156 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
:
2157 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
:
2158 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
:
2159 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
:
2160 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT
:
2161 case TRANS_TX_ERR_WITH_BREAK_REQUEST
:
2162 case TRANS_TX_ERR_WITH_BREAK_RECEVIED
:
2163 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
:
2164 case TRANS_TX_ERR_WITH_CLOSE_NORMAL
:
2165 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
:
2166 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
2167 case TRANS_TX_ERR_WITH_CLOSE_COMINIT
:
2168 case TRANS_TX_ERR_WITH_NAK_RECEVIED
:
2169 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
:
2170 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
:
2171 case TRANS_TX_ERR_WITH_IPTT_CONFLICT
:
2172 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
:
2173 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
:
2174 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
:
2175 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
:
2176 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT
:
2177 case TRANS_RX_ERR_WITH_BREAK_REQUEST
:
2178 case TRANS_RX_ERR_WITH_BREAK_RECEVIED
:
2179 case TRANS_RX_ERR_WITH_CLOSE_NORMAL
:
2180 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
2181 case TRANS_RX_ERR_WITH_CLOSE_COMINIT
:
2182 case TRANS_TX_ERR_FRAME_TXED
:
2183 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
:
2184 case TRANS_RX_ERR_WITH_DATA_LEN0
:
2185 case TRANS_RX_ERR_WITH_BAD_HASH
:
2186 case TRANS_RX_XRDY_WLEN_ZERO_ERR
:
2187 case TRANS_RX_SSP_FRM_LEN_ERR
:
2188 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE
:
2189 case DMA_TX_DATA_SGL_OVERFLOW
:
2190 case DMA_TX_UNEXP_XFER_ERR
:
2191 case DMA_TX_UNEXP_RETRANS_ERR
:
2192 case DMA_TX_XFER_LEN_OVERFLOW
:
2193 case DMA_TX_XFER_OFFSET_ERR
:
2194 case SIPC_RX_DATA_UNDERFLOW_ERR
:
2195 case DMA_RX_DATA_SGL_OVERFLOW
:
2196 case DMA_RX_DATA_OFFSET_ERR
:
2197 case DMA_RX_RDSETUP_LEN_ODD_ERR
:
2198 case DMA_RX_RDSETUP_LEN_ZERO_ERR
:
2199 case DMA_RX_RDSETUP_LEN_OVER_ERR
:
2200 case DMA_RX_SATA_FRAME_TYPE_ERR
:
2201 case DMA_RX_UNKNOWN_FRM_ERR
:
2203 /* This will request a retry */
2204 ts
->stat
= SAS_QUEUE_FULL
;
2213 case SAS_PROTOCOL_SMP
:
2214 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
2217 case SAS_PROTOCOL_SATA
:
2218 case SAS_PROTOCOL_STP
:
2219 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
2222 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
:
2224 ts
->stat
= SAS_OPEN_REJECT
;
2225 ts
->open_rej_reason
= SAS_OREJ_NO_DEST
;
2228 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
:
2230 ts
->resp
= SAS_TASK_UNDELIVERED
;
2231 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2234 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
:
2236 ts
->stat
= SAS_OPEN_REJECT
;
2237 ts
->open_rej_reason
= SAS_OREJ_EPROTO
;
2240 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
:
2242 ts
->stat
= SAS_OPEN_REJECT
;
2243 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
2246 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
:
2248 ts
->stat
= SAS_OPEN_REJECT
;
2249 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
2252 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
:
2254 ts
->stat
= SAS_OPEN_REJECT
;
2255 ts
->open_rej_reason
= SAS_OREJ_WRONG_DEST
;
2258 case DMA_RX_RESP_BUF_OVERFLOW
:
2259 case DMA_RX_UNEXP_NORM_RESP_ERR
:
2260 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
:
2262 ts
->stat
= SAS_OPEN_REJECT
;
2263 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
2266 case DMA_RX_DATA_LEN_OVERFLOW
:
2268 ts
->stat
= SAS_DATA_OVERRUN
;
2272 case DMA_RX_DATA_LEN_UNDERFLOW
:
2274 ts
->residual
= trans_tx_fail_type
;
2275 ts
->stat
= SAS_DATA_UNDERRUN
;
2278 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
:
2279 case TRANS_TX_ERR_PHY_NOT_ENABLE
:
2280 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER
:
2281 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
:
2282 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
:
2283 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
:
2284 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
:
2285 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
:
2286 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT
:
2287 case TRANS_TX_ERR_WITH_BREAK_REQUEST
:
2288 case TRANS_TX_ERR_WITH_BREAK_RECEVIED
:
2289 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
:
2290 case TRANS_TX_ERR_WITH_CLOSE_NORMAL
:
2291 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
:
2292 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
2293 case TRANS_TX_ERR_WITH_CLOSE_COMINIT
:
2294 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
:
2295 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
:
2296 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS
:
2297 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
:
2298 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
:
2299 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
:
2300 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
:
2301 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
:
2302 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
:
2303 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
:
2304 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
:
2305 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT
:
2306 case TRANS_RX_ERR_WITH_BREAK_REQUEST
:
2307 case TRANS_RX_ERR_WITH_BREAK_RECEVIED
:
2308 case TRANS_RX_ERR_WITH_CLOSE_NORMAL
:
2309 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
:
2310 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
2311 case TRANS_RX_ERR_WITH_CLOSE_COMINIT
:
2312 case TRANS_RX_ERR_WITH_DATA_LEN0
:
2313 case TRANS_RX_ERR_WITH_BAD_HASH
:
2314 case TRANS_RX_XRDY_WLEN_ZERO_ERR
:
2315 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE
:
2316 case DMA_TX_DATA_SGL_OVERFLOW
:
2317 case DMA_TX_UNEXP_XFER_ERR
:
2318 case DMA_TX_UNEXP_RETRANS_ERR
:
2319 case DMA_TX_XFER_LEN_OVERFLOW
:
2320 case DMA_TX_XFER_OFFSET_ERR
:
2321 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD
:
2322 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR
:
2323 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR
:
2324 case SIPC_RX_WRSETUP_LEN_ODD_ERR
:
2325 case SIPC_RX_WRSETUP_LEN_ZERO_ERR
:
2326 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR
:
2327 case SIPC_RX_SATA_UNEXP_FIS_ERR
:
2328 case DMA_RX_DATA_SGL_OVERFLOW
:
2329 case DMA_RX_DATA_OFFSET_ERR
:
2330 case DMA_RX_SATA_FRAME_TYPE_ERR
:
2331 case DMA_RX_UNEXP_RDFRAME_ERR
:
2332 case DMA_RX_PIO_DATA_LEN_ERR
:
2333 case DMA_RX_RDSETUP_STATUS_ERR
:
2334 case DMA_RX_RDSETUP_STATUS_DRQ_ERR
:
2335 case DMA_RX_RDSETUP_STATUS_BSY_ERR
:
2336 case DMA_RX_RDSETUP_LEN_ODD_ERR
:
2337 case DMA_RX_RDSETUP_LEN_ZERO_ERR
:
2338 case DMA_RX_RDSETUP_LEN_OVER_ERR
:
2339 case DMA_RX_RDSETUP_OFFSET_ERR
:
2340 case DMA_RX_RDSETUP_ACTIVE_ERR
:
2341 case DMA_RX_RDSETUP_ESTATUS_ERR
:
2342 case DMA_RX_UNKNOWN_FRM_ERR
:
2343 case TRANS_RX_SSP_FRM_LEN_ERR
:
2344 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
:
2347 ts
->stat
= SAS_PHY_DOWN
;
2352 ts
->stat
= SAS_PROTO_RESPONSE
;
2356 hisi_sas_sata_done(task
, slot
);
2365 slot_complete_v2_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_slot
*slot
)
2367 struct sas_task
*task
= slot
->task
;
2368 struct hisi_sas_device
*sas_dev
;
2369 struct device
*dev
= hisi_hba
->dev
;
2370 struct task_status_struct
*ts
;
2371 struct domain_device
*device
;
2372 enum exec_status sts
;
2373 struct hisi_sas_complete_v2_hdr
*complete_queue
=
2374 hisi_hba
->complete_hdr
[slot
->cmplt_queue
];
2375 struct hisi_sas_complete_v2_hdr
*complete_hdr
=
2376 &complete_queue
[slot
->cmplt_queue_slot
];
2377 unsigned long flags
;
2380 if (unlikely(!task
|| !task
->lldd_task
|| !task
->dev
))
2383 ts
= &task
->task_status
;
2385 sas_dev
= device
->lldd_dev
;
2387 spin_lock_irqsave(&task
->task_state_lock
, flags
);
2388 aborted
= task
->task_state_flags
& SAS_TASK_STATE_ABORTED
;
2389 task
->task_state_flags
&=
2390 ~(SAS_TASK_STATE_PENDING
| SAS_TASK_AT_INITIATOR
);
2391 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
2393 memset(ts
, 0, sizeof(*ts
));
2394 ts
->resp
= SAS_TASK_COMPLETE
;
2396 if (unlikely(aborted
)) {
2397 ts
->stat
= SAS_ABORTED_TASK
;
2398 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
2402 if (unlikely(!sas_dev
)) {
2403 dev_dbg(dev
, "slot complete: port has no device\n");
2404 ts
->stat
= SAS_PHY_DOWN
;
2408 /* Use SAS+TMF status codes */
2409 switch ((complete_hdr
->dw0
& CMPLT_HDR_ABORT_STAT_MSK
)
2410 >> CMPLT_HDR_ABORT_STAT_OFF
) {
2411 case STAT_IO_ABORTED
:
2412 /* this io has been aborted by abort command */
2413 ts
->stat
= SAS_ABORTED_TASK
;
2415 case STAT_IO_COMPLETE
:
2416 /* internal abort command complete */
2417 ts
->stat
= TMF_RESP_FUNC_SUCC
;
2418 del_timer(&slot
->internal_abort_timer
);
2420 case STAT_IO_NO_DEVICE
:
2421 ts
->stat
= TMF_RESP_FUNC_COMPLETE
;
2422 del_timer(&slot
->internal_abort_timer
);
2424 case STAT_IO_NOT_VALID
:
2425 /* abort single io, controller don't find
2426 * the io need to abort
2428 ts
->stat
= TMF_RESP_FUNC_FAILED
;
2429 del_timer(&slot
->internal_abort_timer
);
2435 if ((complete_hdr
->dw0
& CMPLT_HDR_ERX_MSK
) &&
2436 (!(complete_hdr
->dw0
& CMPLT_HDR_RSPNS_XFRD_MSK
))) {
2437 u32 err_phase
= (complete_hdr
->dw0
& CMPLT_HDR_ERR_PHASE_MSK
)
2438 >> CMPLT_HDR_ERR_PHASE_OFF
;
2440 /* Analyse error happens on which phase TX or RX */
2441 if (ERR_ON_TX_PHASE(err_phase
))
2442 slot_err_v2_hw(hisi_hba
, task
, slot
, 1);
2443 else if (ERR_ON_RX_PHASE(err_phase
))
2444 slot_err_v2_hw(hisi_hba
, task
, slot
, 2);
2446 if (unlikely(slot
->abort
))
2451 switch (task
->task_proto
) {
2452 case SAS_PROTOCOL_SSP
:
2454 struct hisi_sas_status_buffer
*status_buffer
=
2455 hisi_sas_status_buf_addr_mem(slot
);
2456 struct ssp_response_iu
*iu
= (struct ssp_response_iu
*)
2457 &status_buffer
->iu
[0];
2459 sas_ssp_task_response(dev
, task
, iu
);
2462 case SAS_PROTOCOL_SMP
:
2464 struct scatterlist
*sg_resp
= &task
->smp_task
.smp_resp
;
2467 ts
->stat
= SAM_STAT_GOOD
;
2468 to
= kmap_atomic(sg_page(sg_resp
));
2470 dma_unmap_sg(dev
, &task
->smp_task
.smp_resp
, 1,
2472 dma_unmap_sg(dev
, &task
->smp_task
.smp_req
, 1,
2474 memcpy(to
+ sg_resp
->offset
,
2475 hisi_sas_status_buf_addr_mem(slot
) +
2476 sizeof(struct hisi_sas_err_record
),
2477 sg_dma_len(sg_resp
));
2481 case SAS_PROTOCOL_SATA
:
2482 case SAS_PROTOCOL_STP
:
2483 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
2485 ts
->stat
= SAM_STAT_GOOD
;
2486 hisi_sas_sata_done(task
, slot
);
2490 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
2494 if (!slot
->port
->port_attached
) {
2495 dev_err(dev
, "slot complete: port %d has removed\n",
2496 slot
->port
->sas_port
.id
);
2497 ts
->stat
= SAS_PHY_DOWN
;
2501 spin_lock_irqsave(&task
->task_state_lock
, flags
);
2502 task
->task_state_flags
|= SAS_TASK_STATE_DONE
;
2503 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
2504 spin_lock_irqsave(&hisi_hba
->lock
, flags
);
2505 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
2506 spin_unlock_irqrestore(&hisi_hba
->lock
, flags
);
2509 if (task
->task_done
)
2510 task
->task_done(task
);
2515 static int prep_ata_v2_hw(struct hisi_hba
*hisi_hba
,
2516 struct hisi_sas_slot
*slot
)
2518 struct sas_task
*task
= slot
->task
;
2519 struct domain_device
*device
= task
->dev
;
2520 struct domain_device
*parent_dev
= device
->parent
;
2521 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
2522 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
2523 struct asd_sas_port
*sas_port
= device
->port
;
2524 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
2526 int has_data
= 0, rc
= 0, hdr_tag
= 0;
2527 u32 dw1
= 0, dw2
= 0;
2531 hdr
->dw0
= cpu_to_le32(port
->id
<< CMD_HDR_PORT_OFF
);
2532 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
2533 hdr
->dw0
|= cpu_to_le32(3 << CMD_HDR_CMD_OFF
);
2535 hdr
->dw0
|= cpu_to_le32(4 << CMD_HDR_CMD_OFF
);
2538 switch (task
->data_dir
) {
2541 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
2543 case DMA_FROM_DEVICE
:
2545 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
2548 dw1
&= ~CMD_HDR_DIR_MSK
;
2551 if ((task
->ata_task
.fis
.command
== ATA_CMD_DEV_RESET
) &&
2552 (task
->ata_task
.fis
.control
& ATA_SRST
))
2553 dw1
|= 1 << CMD_HDR_RESET_OFF
;
2555 dw1
|= (hisi_sas_get_ata_protocol(
2556 task
->ata_task
.fis
.command
, task
->data_dir
))
2557 << CMD_HDR_FRAME_TYPE_OFF
;
2558 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
2559 hdr
->dw1
= cpu_to_le32(dw1
);
2562 if (task
->ata_task
.use_ncq
&& hisi_sas_get_ncq_tag(task
, &hdr_tag
)) {
2563 task
->ata_task
.fis
.sector_count
|= (u8
) (hdr_tag
<< 3);
2564 dw2
|= hdr_tag
<< CMD_HDR_NCQ_TAG_OFF
;
2567 dw2
|= (HISI_SAS_MAX_STP_RESP_SZ
/ 4) << CMD_HDR_CFL_OFF
|
2568 2 << CMD_HDR_SG_MOD_OFF
;
2569 hdr
->dw2
= cpu_to_le32(dw2
);
2572 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
2575 rc
= prep_prd_sge_v2_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
2581 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
2582 hdr
->cmd_table_addr
= cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot
));
2583 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
2585 buf_cmd
= hisi_sas_cmd_hdr_addr_mem(slot
);
2587 if (likely(!task
->ata_task
.device_control_reg_update
))
2588 task
->ata_task
.fis
.flags
|= 0x80; /* C=1: update ATA cmd reg */
2589 /* fill in command FIS */
2590 memcpy(buf_cmd
, &task
->ata_task
.fis
, sizeof(struct host_to_dev_fis
));
2595 static void hisi_sas_internal_abort_quirk_timeout(unsigned long data
)
2597 struct hisi_sas_slot
*slot
= (struct hisi_sas_slot
*)data
;
2598 struct hisi_sas_port
*port
= slot
->port
;
2599 struct asd_sas_port
*asd_sas_port
;
2600 struct asd_sas_phy
*sas_phy
;
2605 asd_sas_port
= &port
->sas_port
;
2607 /* Kick the hardware - send break command */
2608 list_for_each_entry(sas_phy
, &asd_sas_port
->phy_list
, port_phy_el
) {
2609 struct hisi_sas_phy
*phy
= sas_phy
->lldd_phy
;
2610 struct hisi_hba
*hisi_hba
= phy
->hisi_hba
;
2611 int phy_no
= sas_phy
->id
;
2614 link_dfx2
= hisi_sas_phy_read32(hisi_hba
, phy_no
, LINK_DFX2
);
2615 if ((link_dfx2
== LINK_DFX2_RCVR_HOLD_STS_MSK
) ||
2616 (link_dfx2
& LINK_DFX2_SEND_HOLD_STS_MSK
)) {
2619 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2621 txid_auto
|= TXID_AUTO_CTB_MSK
;
2622 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
2629 static int prep_abort_v2_hw(struct hisi_hba
*hisi_hba
,
2630 struct hisi_sas_slot
*slot
,
2631 int device_id
, int abort_flag
, int tag_to_abort
)
2633 struct sas_task
*task
= slot
->task
;
2634 struct domain_device
*dev
= task
->dev
;
2635 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
2636 struct hisi_sas_port
*port
= slot
->port
;
2637 struct timer_list
*timer
= &slot
->internal_abort_timer
;
2639 /* setup the quirk timer */
2640 setup_timer(timer
, hisi_sas_internal_abort_quirk_timeout
,
2641 (unsigned long)slot
);
2642 /* Set the timeout to 10ms less than internal abort timeout */
2643 mod_timer(timer
, jiffies
+ msecs_to_jiffies(100));
2646 hdr
->dw0
= cpu_to_le32((5 << CMD_HDR_CMD_OFF
) | /*abort*/
2647 (port
->id
<< CMD_HDR_PORT_OFF
) |
2648 ((dev_is_sata(dev
) ? 1:0) <<
2649 CMD_HDR_ABORT_DEVICE_TYPE_OFF
) |
2650 (abort_flag
<< CMD_HDR_ABORT_FLAG_OFF
));
2653 hdr
->dw1
= cpu_to_le32(device_id
<< CMD_HDR_DEV_ID_OFF
);
2656 hdr
->dw7
= cpu_to_le32(tag_to_abort
<< CMD_HDR_ABORT_IPTT_OFF
);
2657 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
2662 static int phy_up_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2664 int i
, res
= IRQ_HANDLED
;
2665 u32 port_id
, link_rate
, hard_phy_linkrate
;
2666 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2667 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
2668 struct device
*dev
= hisi_hba
->dev
;
2669 u32
*frame_rcvd
= (u32
*)sas_phy
->frame_rcvd
;
2670 struct sas_identify_frame
*id
= (struct sas_identify_frame
*)frame_rcvd
;
2672 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 1);
2674 if (is_sata_phy_v2_hw(hisi_hba
, phy_no
))
2678 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
2680 port_id
= (port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
2681 PORT_STATE_PHY8_PORT_NUM_OFF
;
2682 link_rate
= (port_state
& PORT_STATE_PHY8_CONN_RATE_MSK
) >>
2683 PORT_STATE_PHY8_CONN_RATE_OFF
;
2685 port_id
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
2686 port_id
= (port_id
>> (4 * phy_no
)) & 0xf;
2687 link_rate
= hisi_sas_read32(hisi_hba
, PHY_CONN_RATE
);
2688 link_rate
= (link_rate
>> (phy_no
* 4)) & 0xf;
2691 if (port_id
== 0xf) {
2692 dev_err(dev
, "phyup: phy%d invalid portid\n", phy_no
);
2697 for (i
= 0; i
< 6; i
++) {
2698 u32 idaf
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2699 RX_IDAF_DWORD0
+ (i
* 4));
2700 frame_rcvd
[i
] = __swab32(idaf
);
2703 sas_phy
->linkrate
= link_rate
;
2704 hard_phy_linkrate
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2706 phy
->maximum_linkrate
= hard_phy_linkrate
& 0xf;
2707 phy
->minimum_linkrate
= (hard_phy_linkrate
>> 4) & 0xf;
2709 sas_phy
->oob_mode
= SAS_OOB_MODE
;
2710 memcpy(sas_phy
->attached_sas_addr
, &id
->sas_addr
, SAS_ADDR_SIZE
);
2711 dev_info(dev
, "phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
2712 phy
->port_id
= port_id
;
2713 phy
->phy_type
&= ~(PORT_TYPE_SAS
| PORT_TYPE_SATA
);
2714 phy
->phy_type
|= PORT_TYPE_SAS
;
2715 phy
->phy_attached
= 1;
2716 phy
->identify
.device_type
= id
->dev_type
;
2717 phy
->frame_rcvd_size
= sizeof(struct sas_identify_frame
);
2718 if (phy
->identify
.device_type
== SAS_END_DEVICE
)
2719 phy
->identify
.target_port_protocols
=
2721 else if (phy
->identify
.device_type
!= SAS_PHY_UNUSED
) {
2722 phy
->identify
.target_port_protocols
=
2724 if (!timer_pending(&hisi_hba
->timer
))
2725 set_link_timer_quirk(hisi_hba
);
2727 queue_work(hisi_hba
->wq
, &phy
->phyup_ws
);
2730 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
2731 CHL_INT0_SL_PHY_ENABLE_MSK
);
2732 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 0);
2737 static bool check_any_wideports_v2_hw(struct hisi_hba
*hisi_hba
)
2741 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
2742 if (port_state
& 0x1ff)
2748 static int phy_down_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2750 u32 phy_state
, sl_ctrl
, txid_auto
;
2751 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2752 struct hisi_sas_port
*port
= phy
->port
;
2754 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 1);
2756 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
2757 hisi_sas_phy_down(hisi_hba
, phy_no
, (phy_state
& 1 << phy_no
) ? 1 : 0);
2759 sl_ctrl
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
2760 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
,
2761 sl_ctrl
& ~SL_CONTROL_CTA_MSK
);
2762 if (port
&& !get_wideport_bitmap_v2_hw(hisi_hba
, port
->id
))
2763 if (!check_any_wideports_v2_hw(hisi_hba
) &&
2764 timer_pending(&hisi_hba
->timer
))
2765 del_timer(&hisi_hba
->timer
);
2767 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
2768 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
2769 txid_auto
| TXID_AUTO_CT3_MSK
);
2771 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
, CHL_INT0_NOT_RDY_MSK
);
2772 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 0);
2777 static irqreturn_t
int_phy_updown_v2_hw(int irq_no
, void *p
)
2779 struct hisi_hba
*hisi_hba
= p
;
2782 irqreturn_t res
= IRQ_NONE
;
2784 irq_msk
= (hisi_sas_read32(hisi_hba
, HGC_INVLD_DQE_INFO
)
2785 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF
) & 0x1ff;
2788 u32 reg_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2791 switch (reg_value
& (CHL_INT0_NOT_RDY_MSK
|
2792 CHL_INT0_SL_PHY_ENABLE_MSK
)) {
2794 case CHL_INT0_SL_PHY_ENABLE_MSK
:
2796 if (phy_up_v2_hw(phy_no
, hisi_hba
) ==
2801 case CHL_INT0_NOT_RDY_MSK
:
2803 if (phy_down_v2_hw(phy_no
, hisi_hba
) ==
2808 case (CHL_INT0_NOT_RDY_MSK
|
2809 CHL_INT0_SL_PHY_ENABLE_MSK
):
2810 reg_value
= hisi_sas_read32(hisi_hba
,
2812 if (reg_value
& BIT(phy_no
)) {
2814 if (phy_up_v2_hw(phy_no
, hisi_hba
) ==
2819 if (phy_down_v2_hw(phy_no
, hisi_hba
) ==
2837 static void phy_bcast_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2839 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2840 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
2841 struct sas_ha_struct
*sas_ha
= &hisi_hba
->sha
;
2844 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 1);
2845 bcast_status
= hisi_sas_phy_read32(hisi_hba
, phy_no
, RX_PRIMS_STATUS
);
2846 if (bcast_status
& RX_BCAST_CHG_MSK
)
2847 sas_ha
->notify_port_event(sas_phy
, PORTE_BROADCAST_RCVD
);
2848 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
2849 CHL_INT0_SL_RX_BCST_ACK_MSK
);
2850 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 0);
2853 static irqreturn_t
int_chnl_int_v2_hw(int irq_no
, void *p
)
2855 struct hisi_hba
*hisi_hba
= p
;
2856 struct device
*dev
= hisi_hba
->dev
;
2857 u32 ent_msk
, ent_tmp
, irq_msk
;
2860 ent_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
2862 ent_msk
|= ENT_INT_SRC_MSK3_ENT95_MSK_MSK
;
2863 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_msk
);
2865 irq_msk
= (hisi_sas_read32(hisi_hba
, HGC_INVLD_DQE_INFO
) >>
2866 HGC_INVLD_DQE_INFO_FB_CH3_OFF
) & 0x1ff;
2869 if (irq_msk
& (1 << phy_no
)) {
2870 u32 irq_value0
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2872 u32 irq_value1
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2874 u32 irq_value2
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2878 if (irq_value1
& (CHL_INT1_DMAC_RX_ECC_ERR_MSK
|
2879 CHL_INT1_DMAC_TX_ECC_ERR_MSK
))
2880 panic("%s: DMAC RX/TX ecc bad error!\
2882 dev_name(dev
), irq_value1
);
2884 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2885 CHL_INT1
, irq_value1
);
2889 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2890 CHL_INT2
, irq_value2
);
2894 if (irq_value0
& CHL_INT0_SL_RX_BCST_ACK_MSK
)
2895 phy_bcast_v2_hw(phy_no
, hisi_hba
);
2897 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2898 CHL_INT0
, irq_value0
2899 & (~CHL_INT0_HOTPLUG_TOUT_MSK
)
2900 & (~CHL_INT0_SL_PHY_ENABLE_MSK
)
2901 & (~CHL_INT0_NOT_RDY_MSK
));
2904 irq_msk
&= ~(1 << phy_no
);
2908 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_tmp
);
2914 one_bit_ecc_error_process_v2_hw(struct hisi_hba
*hisi_hba
, u32 irq_value
)
2916 struct device
*dev
= hisi_hba
->dev
;
2917 const struct hisi_sas_hw_error
*ecc_error
;
2921 for (i
= 0; i
< ARRAY_SIZE(one_bit_ecc_errors
); i
++) {
2922 ecc_error
= &one_bit_ecc_errors
[i
];
2923 if (irq_value
& ecc_error
->irq_msk
) {
2924 val
= hisi_sas_read32(hisi_hba
, ecc_error
->reg
);
2925 val
&= ecc_error
->msk
;
2926 val
>>= ecc_error
->shift
;
2927 dev_warn(dev
, ecc_error
->msg
, val
);
2932 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba
*hisi_hba
,
2935 struct device
*dev
= hisi_hba
->dev
;
2936 const struct hisi_sas_hw_error
*ecc_error
;
2940 for (i
= 0; i
< ARRAY_SIZE(multi_bit_ecc_errors
); i
++) {
2941 ecc_error
= &multi_bit_ecc_errors
[i
];
2942 if (irq_value
& ecc_error
->irq_msk
) {
2943 val
= hisi_sas_read32(hisi_hba
, ecc_error
->reg
);
2944 val
&= ecc_error
->msk
;
2945 val
>>= ecc_error
->shift
;
2946 dev_warn(dev
, ecc_error
->msg
, irq_value
, val
);
2947 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
2954 static irqreturn_t
fatal_ecc_int_v2_hw(int irq_no
, void *p
)
2956 struct hisi_hba
*hisi_hba
= p
;
2957 u32 irq_value
, irq_msk
;
2959 irq_msk
= hisi_sas_read32(hisi_hba
, SAS_ECC_INTR_MSK
);
2960 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, irq_msk
| 0xffffffff);
2962 irq_value
= hisi_sas_read32(hisi_hba
, SAS_ECC_INTR
);
2964 one_bit_ecc_error_process_v2_hw(hisi_hba
, irq_value
);
2965 multi_bit_ecc_error_process_v2_hw(hisi_hba
, irq_value
);
2968 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR
, irq_value
);
2969 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, irq_msk
);
2974 #define AXI_ERR_NR 8
2975 static const char axi_err_info
[AXI_ERR_NR
][32] = {
2986 #define FIFO_ERR_NR 5
2987 static const char fifo_err_info
[FIFO_ERR_NR
][32] = {
2995 static irqreturn_t
fatal_axi_int_v2_hw(int irq_no
, void *p
)
2997 struct hisi_hba
*hisi_hba
= p
;
2998 u32 irq_value
, irq_msk
, err_value
;
2999 struct device
*dev
= hisi_hba
->dev
;
3001 irq_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
3002 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, irq_msk
| 0xfffffffe);
3004 irq_value
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
3006 if (irq_value
& BIT(ENT_INT_SRC3_WP_DEPTH_OFF
)) {
3007 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
3008 1 << ENT_INT_SRC3_WP_DEPTH_OFF
);
3009 dev_warn(dev
, "write pointer and depth error (0x%x) \
3012 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
3015 if (irq_value
& BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF
)) {
3016 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
3018 ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF
);
3019 dev_warn(dev
, "iptt no match slot error (0x%x) found!\n",
3021 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
3024 if (irq_value
& BIT(ENT_INT_SRC3_RP_DEPTH_OFF
)) {
3025 dev_warn(dev
, "read pointer and depth error (0x%x) \
3028 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
3031 if (irq_value
& BIT(ENT_INT_SRC3_AXI_OFF
)) {
3034 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
3035 1 << ENT_INT_SRC3_AXI_OFF
);
3036 err_value
= hisi_sas_read32(hisi_hba
,
3037 HGC_AXI_FIFO_ERR_INFO
);
3039 for (i
= 0; i
< AXI_ERR_NR
; i
++) {
3040 if (err_value
& BIT(i
)) {
3041 dev_warn(dev
, "%s (0x%x) found!\n",
3042 axi_err_info
[i
], irq_value
);
3043 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
3048 if (irq_value
& BIT(ENT_INT_SRC3_FIFO_OFF
)) {
3051 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
3052 1 << ENT_INT_SRC3_FIFO_OFF
);
3053 err_value
= hisi_sas_read32(hisi_hba
,
3054 HGC_AXI_FIFO_ERR_INFO
);
3056 for (i
= 0; i
< FIFO_ERR_NR
; i
++) {
3057 if (err_value
& BIT(AXI_ERR_NR
+ i
)) {
3058 dev_warn(dev
, "%s (0x%x) found!\n",
3059 fifo_err_info
[i
], irq_value
);
3060 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
3066 if (irq_value
& BIT(ENT_INT_SRC3_LM_OFF
)) {
3067 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
3068 1 << ENT_INT_SRC3_LM_OFF
);
3069 dev_warn(dev
, "LM add/fetch list error (0x%x) found!\n",
3071 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
3074 if (irq_value
& BIT(ENT_INT_SRC3_ABT_OFF
)) {
3075 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
3076 1 << ENT_INT_SRC3_ABT_OFF
);
3077 dev_warn(dev
, "SAS_HGC_ABT fetch LM list error (0x%x) found!\n",
3079 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
3082 if (irq_value
& BIT(ENT_INT_SRC3_ITC_INT_OFF
)) {
3083 u32 reg_val
= hisi_sas_read32(hisi_hba
, ITCT_CLR
);
3084 u32 dev_id
= reg_val
& ITCT_DEV_MSK
;
3085 struct hisi_sas_device
*sas_dev
=
3086 &hisi_hba
->devices
[dev_id
];
3088 hisi_sas_write32(hisi_hba
, ITCT_CLR
, 0);
3089 dev_dbg(dev
, "clear ITCT ok\n");
3090 complete(sas_dev
->completion
);
3094 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
, irq_value
);
3095 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, irq_msk
);
3100 static void cq_tasklet_v2_hw(unsigned long val
)
3102 struct hisi_sas_cq
*cq
= (struct hisi_sas_cq
*)val
;
3103 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
3104 struct hisi_sas_slot
*slot
;
3105 struct hisi_sas_itct
*itct
;
3106 struct hisi_sas_complete_v2_hdr
*complete_queue
;
3107 u32 rd_point
= cq
->rd_point
, wr_point
, dev_id
;
3109 struct hisi_sas_dq
*dq
= &hisi_hba
->dq
[queue
];
3111 if (unlikely(hisi_hba
->reject_stp_links_msk
))
3112 phys_try_accept_stp_links_v2_hw(hisi_hba
);
3114 complete_queue
= hisi_hba
->complete_hdr
[queue
];
3116 spin_lock(&dq
->lock
);
3117 wr_point
= hisi_sas_read32(hisi_hba
, COMPL_Q_0_WR_PTR
+
3120 while (rd_point
!= wr_point
) {
3121 struct hisi_sas_complete_v2_hdr
*complete_hdr
;
3124 complete_hdr
= &complete_queue
[rd_point
];
3126 /* Check for NCQ completion */
3127 if (complete_hdr
->act
) {
3128 u32 act_tmp
= complete_hdr
->act
;
3129 int ncq_tag_count
= ffs(act_tmp
);
3131 dev_id
= (complete_hdr
->dw1
& CMPLT_HDR_DEV_ID_MSK
) >>
3132 CMPLT_HDR_DEV_ID_OFF
;
3133 itct
= &hisi_hba
->itct
[dev_id
];
3135 /* The NCQ tags are held in the itct header */
3136 while (ncq_tag_count
) {
3137 __le64
*ncq_tag
= &itct
->qw4_15
[0];
3140 iptt
= (ncq_tag
[ncq_tag_count
/ 5]
3141 >> (ncq_tag_count
% 5) * 12) & 0xfff;
3143 slot
= &hisi_hba
->slot_info
[iptt
];
3144 slot
->cmplt_queue_slot
= rd_point
;
3145 slot
->cmplt_queue
= queue
;
3146 slot_complete_v2_hw(hisi_hba
, slot
);
3148 act_tmp
&= ~(1 << ncq_tag_count
);
3149 ncq_tag_count
= ffs(act_tmp
);
3152 iptt
= (complete_hdr
->dw1
) & CMPLT_HDR_IPTT_MSK
;
3153 slot
= &hisi_hba
->slot_info
[iptt
];
3154 slot
->cmplt_queue_slot
= rd_point
;
3155 slot
->cmplt_queue
= queue
;
3156 slot_complete_v2_hw(hisi_hba
, slot
);
3159 if (++rd_point
>= HISI_SAS_QUEUE_SLOTS
)
3163 /* update rd_point */
3164 cq
->rd_point
= rd_point
;
3165 hisi_sas_write32(hisi_hba
, COMPL_Q_0_RD_PTR
+ (0x14 * queue
), rd_point
);
3166 spin_unlock(&dq
->lock
);
3169 static irqreturn_t
cq_interrupt_v2_hw(int irq_no
, void *p
)
3171 struct hisi_sas_cq
*cq
= p
;
3172 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
3175 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 1 << queue
);
3177 tasklet_schedule(&cq
->tasklet
);
3182 static irqreturn_t
sata_int_v2_hw(int irq_no
, void *p
)
3184 struct hisi_sas_phy
*phy
= p
;
3185 struct hisi_hba
*hisi_hba
= phy
->hisi_hba
;
3186 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
3187 struct device
*dev
= hisi_hba
->dev
;
3188 struct hisi_sas_initial_fis
*initial_fis
;
3189 struct dev_to_host_fis
*fis
;
3190 u32 ent_tmp
, ent_msk
, ent_int
, port_id
, link_rate
, hard_phy_linkrate
;
3191 irqreturn_t res
= IRQ_HANDLED
;
3192 u8 attached_sas_addr
[SAS_ADDR_SIZE
] = {0};
3195 phy_no
= sas_phy
->id
;
3196 initial_fis
= &hisi_hba
->initial_fis
[phy_no
];
3197 fis
= &initial_fis
->fis
;
3199 offset
= 4 * (phy_no
/ 4);
3200 ent_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
);
3201 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
,
3202 ent_msk
| 1 << ((phy_no
% 4) * 8));
3204 ent_int
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC1
+ offset
);
3205 ent_tmp
= ent_int
& (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF
*
3207 ent_int
>>= ENT_INT_SRC1_D2H_FIS_CH1_OFF
* (phy_no
% 4);
3208 if ((ent_int
& ENT_INT_SRC1_D2H_FIS_CH0_MSK
) == 0) {
3209 dev_warn(dev
, "sata int: phy%d did not receive FIS\n", phy_no
);
3214 /* check ERR bit of Status Register */
3215 if (fis
->status
& ATA_ERR
) {
3216 dev_warn(dev
, "sata int: phy%d FIS status: 0x%x\n", phy_no
,
3218 disable_phy_v2_hw(hisi_hba
, phy_no
);
3219 enable_phy_v2_hw(hisi_hba
, phy_no
);
3224 if (unlikely(phy_no
== 8)) {
3225 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
3227 port_id
= (port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
3228 PORT_STATE_PHY8_PORT_NUM_OFF
;
3229 link_rate
= (port_state
& PORT_STATE_PHY8_CONN_RATE_MSK
) >>
3230 PORT_STATE_PHY8_CONN_RATE_OFF
;
3232 port_id
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
3233 port_id
= (port_id
>> (4 * phy_no
)) & 0xf;
3234 link_rate
= hisi_sas_read32(hisi_hba
, PHY_CONN_RATE
);
3235 link_rate
= (link_rate
>> (phy_no
* 4)) & 0xf;
3238 if (port_id
== 0xf) {
3239 dev_err(dev
, "sata int: phy%d invalid portid\n", phy_no
);
3244 sas_phy
->linkrate
= link_rate
;
3245 hard_phy_linkrate
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
3247 phy
->maximum_linkrate
= hard_phy_linkrate
& 0xf;
3248 phy
->minimum_linkrate
= (hard_phy_linkrate
>> 4) & 0xf;
3250 sas_phy
->oob_mode
= SATA_OOB_MODE
;
3251 /* Make up some unique SAS address */
3252 attached_sas_addr
[0] = 0x50;
3253 attached_sas_addr
[7] = phy_no
;
3254 memcpy(sas_phy
->attached_sas_addr
, attached_sas_addr
, SAS_ADDR_SIZE
);
3255 memcpy(sas_phy
->frame_rcvd
, fis
, sizeof(struct dev_to_host_fis
));
3256 dev_info(dev
, "sata int phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
3257 phy
->phy_type
&= ~(PORT_TYPE_SAS
| PORT_TYPE_SATA
);
3258 phy
->port_id
= port_id
;
3259 phy
->phy_type
|= PORT_TYPE_SATA
;
3260 phy
->phy_attached
= 1;
3261 phy
->identify
.device_type
= SAS_SATA_DEV
;
3262 phy
->frame_rcvd_size
= sizeof(struct dev_to_host_fis
);
3263 phy
->identify
.target_port_protocols
= SAS_PROTOCOL_SATA
;
3264 queue_work(hisi_hba
->wq
, &phy
->phyup_ws
);
3267 hisi_sas_write32(hisi_hba
, ENT_INT_SRC1
+ offset
, ent_tmp
);
3268 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
, ent_msk
);
3273 static irq_handler_t phy_interrupts
[HISI_SAS_PHY_INT_NR
] = {
3274 int_phy_updown_v2_hw
,
3278 static irq_handler_t fatal_interrupts
[HISI_SAS_FATAL_INT_NR
] = {
3279 fatal_ecc_int_v2_hw
,
3284 * There is a limitation in the hip06 chipset that we need
3285 * to map in all mbigen interrupts, even if they are not used.
3287 static int interrupt_init_v2_hw(struct hisi_hba
*hisi_hba
)
3289 struct platform_device
*pdev
= hisi_hba
->platform_dev
;
3290 struct device
*dev
= &pdev
->dev
;
3291 int irq
, rc
, irq_map
[128];
3292 int i
, phy_no
, fatal_no
, queue_no
, k
;
3294 for (i
= 0; i
< 128; i
++)
3295 irq_map
[i
] = platform_get_irq(pdev
, i
);
3297 for (i
= 0; i
< HISI_SAS_PHY_INT_NR
; i
++) {
3298 irq
= irq_map
[i
+ 1]; /* Phy up/down is irq1 */
3299 rc
= devm_request_irq(dev
, irq
, phy_interrupts
[i
], 0,
3300 DRV_NAME
" phy", hisi_hba
);
3302 dev_err(dev
, "irq init: could not request "
3303 "phy interrupt %d, rc=%d\n",
3306 goto free_phy_int_irqs
;
3310 for (phy_no
= 0; phy_no
< hisi_hba
->n_phy
; phy_no
++) {
3311 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
3313 irq
= irq_map
[phy_no
+ 72];
3314 rc
= devm_request_irq(dev
, irq
, sata_int_v2_hw
, 0,
3315 DRV_NAME
" sata", phy
);
3317 dev_err(dev
, "irq init: could not request "
3318 "sata interrupt %d, rc=%d\n",
3321 goto free_sata_int_irqs
;
3325 for (fatal_no
= 0; fatal_no
< HISI_SAS_FATAL_INT_NR
; fatal_no
++) {
3326 irq
= irq_map
[fatal_no
+ 81];
3327 rc
= devm_request_irq(dev
, irq
, fatal_interrupts
[fatal_no
], 0,
3328 DRV_NAME
" fatal", hisi_hba
);
3331 "irq init: could not request fatal interrupt %d, rc=%d\n",
3334 goto free_fatal_int_irqs
;
3338 for (queue_no
= 0; queue_no
< hisi_hba
->queue_count
; queue_no
++) {
3339 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[queue_no
];
3340 struct tasklet_struct
*t
= &cq
->tasklet
;
3342 irq
= irq_map
[queue_no
+ 96];
3343 rc
= devm_request_irq(dev
, irq
, cq_interrupt_v2_hw
, 0,
3344 DRV_NAME
" cq", cq
);
3347 "irq init: could not request cq interrupt %d, rc=%d\n",
3350 goto free_cq_int_irqs
;
3352 tasklet_init(t
, cq_tasklet_v2_hw
, (unsigned long)cq
);
3358 for (k
= 0; k
< queue_no
; k
++) {
3359 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[k
];
3361 free_irq(irq_map
[k
+ 96], cq
);
3362 tasklet_kill(&cq
->tasklet
);
3364 free_fatal_int_irqs
:
3365 for (k
= 0; k
< fatal_no
; k
++)
3366 free_irq(irq_map
[k
+ 81], hisi_hba
);
3368 for (k
= 0; k
< phy_no
; k
++) {
3369 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[k
];
3371 free_irq(irq_map
[k
+ 72], phy
);
3374 for (k
= 0; k
< i
; k
++)
3375 free_irq(irq_map
[k
+ 1], hisi_hba
);
3379 static int hisi_sas_v2_init(struct hisi_hba
*hisi_hba
)
3383 memset(hisi_hba
->sata_dev_bitmap
, 0, sizeof(hisi_hba
->sata_dev_bitmap
));
3385 rc
= hw_init_v2_hw(hisi_hba
);
3389 rc
= interrupt_init_v2_hw(hisi_hba
);
3396 static void interrupt_disable_v2_hw(struct hisi_hba
*hisi_hba
)
3398 struct platform_device
*pdev
= hisi_hba
->platform_dev
;
3401 for (i
= 0; i
< hisi_hba
->queue_count
; i
++)
3402 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+ 0x4 * i
, 0x1);
3404 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0xffffffff);
3405 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0xffffffff);
3406 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0xffffffff);
3407 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0xffffffff);
3409 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
3410 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xffffffff);
3411 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0xffffffff);
3414 for (i
= 0; i
< 128; i
++)
3415 synchronize_irq(platform_get_irq(pdev
, i
));
3419 static u32
get_phys_state_v2_hw(struct hisi_hba
*hisi_hba
)
3421 return hisi_sas_read32(hisi_hba
, PHY_STATE
);
3424 static int soft_reset_v2_hw(struct hisi_hba
*hisi_hba
)
3426 struct device
*dev
= hisi_hba
->dev
;
3429 interrupt_disable_v2_hw(hisi_hba
);
3430 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0x0);
3432 stop_phys_v2_hw(hisi_hba
);
3436 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
+ AM_CTRL_GLOBAL
, 0x1);
3438 /* wait until bus idle */
3441 u32 status
= hisi_sas_read32_relaxed(hisi_hba
,
3442 AXI_MASTER_CFG_BASE
+ AM_CURR_TRANS_RETURN
);
3449 dev_info(dev
, "wait axi bus state to idle timeout!\n");
3454 hisi_sas_init_mem(hisi_hba
);
3456 rc
= hw_init_v2_hw(hisi_hba
);
3460 phys_reject_stp_links_v2_hw(hisi_hba
);
3465 static const struct hisi_sas_hw hisi_sas_v2_hw
= {
3466 .hw_init
= hisi_sas_v2_init
,
3467 .setup_itct
= setup_itct_v2_hw
,
3468 .slot_index_alloc
= slot_index_alloc_quirk_v2_hw
,
3469 .alloc_dev
= alloc_dev_quirk_v2_hw
,
3470 .sl_notify
= sl_notify_v2_hw
,
3471 .get_wideport_bitmap
= get_wideport_bitmap_v2_hw
,
3472 .free_device
= free_device_v2_hw
,
3473 .prep_smp
= prep_smp_v2_hw
,
3474 .prep_ssp
= prep_ssp_v2_hw
,
3475 .prep_stp
= prep_ata_v2_hw
,
3476 .prep_abort
= prep_abort_v2_hw
,
3477 .get_free_slot
= get_free_slot_v2_hw
,
3478 .start_delivery
= start_delivery_v2_hw
,
3479 .slot_complete
= slot_complete_v2_hw
,
3480 .phys_init
= phys_init_v2_hw
,
3481 .phy_enable
= enable_phy_v2_hw
,
3482 .phy_disable
= disable_phy_v2_hw
,
3483 .phy_hard_reset
= phy_hard_reset_v2_hw
,
3484 .get_events
= phy_get_events_v2_hw
,
3485 .phy_set_linkrate
= phy_set_linkrate_v2_hw
,
3486 .phy_get_max_linkrate
= phy_get_max_linkrate_v2_hw
,
3487 .max_command_entries
= HISI_SAS_COMMAND_ENTRIES_V2_HW
,
3488 .complete_hdr_size
= sizeof(struct hisi_sas_complete_v2_hdr
),
3489 .soft_reset
= soft_reset_v2_hw
,
3490 .get_phys_state
= get_phys_state_v2_hw
,
3493 static int hisi_sas_v2_probe(struct platform_device
*pdev
)
3496 * Check if we should defer the probe before we probe the
3497 * upper layer, as it's hard to defer later on.
3499 int ret
= platform_get_irq(pdev
, 0);
3502 if (ret
!= -EPROBE_DEFER
)
3503 dev_err(&pdev
->dev
, "cannot obtain irq\n");
3507 return hisi_sas_probe(pdev
, &hisi_sas_v2_hw
);
3510 static int hisi_sas_v2_remove(struct platform_device
*pdev
)
3512 struct sas_ha_struct
*sha
= platform_get_drvdata(pdev
);
3513 struct hisi_hba
*hisi_hba
= sha
->lldd_ha
;
3516 if (timer_pending(&hisi_hba
->timer
))
3517 del_timer(&hisi_hba
->timer
);
3519 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
3520 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[i
];
3522 tasklet_kill(&cq
->tasklet
);
3525 return hisi_sas_remove(pdev
);
3528 static const struct of_device_id sas_v2_of_match
[] = {
3529 { .compatible
= "hisilicon,hip06-sas-v2",},
3530 { .compatible
= "hisilicon,hip07-sas-v2",},
3533 MODULE_DEVICE_TABLE(of
, sas_v2_of_match
);
3535 static const struct acpi_device_id sas_v2_acpi_match
[] = {
3540 MODULE_DEVICE_TABLE(acpi
, sas_v2_acpi_match
);
3542 static struct platform_driver hisi_sas_v2_driver
= {
3543 .probe
= hisi_sas_v2_probe
,
3544 .remove
= hisi_sas_v2_remove
,
3547 .of_match_table
= sas_v2_of_match
,
3548 .acpi_match_table
= ACPI_PTR(sas_v2_acpi_match
),
3552 module_platform_driver(hisi_sas_v2_driver
);
3554 MODULE_LICENSE("GPL");
3555 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3556 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3557 MODULE_ALIAS("platform:" DRV_NAME
);