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[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
1 /*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12 #include "hisi_sas.h"
13 #define DRV_NAME "hisi_sas_v2_hw"
14
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
34 #define ITCT_CLR 0x44
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
148 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
149 #define DLVRY_Q_0_DEPTH 0x268
150 #define DLVRY_Q_0_WR_PTR 0x26c
151 #define DLVRY_Q_0_RD_PTR 0x270
152 #define HYPER_STREAM_ID_EN_CFG 0xc80
153 #define OQ0_INT_SRC_MSK 0xc90
154 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
155 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
156 #define COMPL_Q_0_DEPTH 0x4e8
157 #define COMPL_Q_0_WR_PTR 0x4ec
158 #define COMPL_Q_0_RD_PTR 0x4f0
159 #define HGC_RXM_DFX_STATUS14 0xae8
160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
162 HGC_RXM_DFX_STATUS14_MEM0_OFF)
163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM1_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM2_OFF)
169 #define HGC_RXM_DFX_STATUS15 0xaec
170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
172 HGC_RXM_DFX_STATUS15_MEM3_OFF)
173 /* phy registers need init */
174 #define PORT_BASE (0x2000)
175
176 #define PHY_CFG (PORT_BASE + 0x0)
177 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PHY_CFG_ENA_OFF 0
179 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
180 #define PHY_CFG_DC_OPT_OFF 2
181 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
182 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
183 #define PROG_PHY_LINK_RATE_MAX_OFF 0
184 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
185 #define PHY_CTRL (PORT_BASE + 0x14)
186 #define PHY_CTRL_RESET_OFF 0
187 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
188 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
189 #define SL_CFG (PORT_BASE + 0x84)
190 #define PHY_PCN (PORT_BASE + 0x44)
191 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
192 #define SL_CONTROL (PORT_BASE + 0x94)
193 #define SL_CONTROL_NOTIFY_EN_OFF 0
194 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
195 #define SL_CONTROL_CTA_OFF 17
196 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
197 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
198 #define RX_BCAST_CHG_OFF 1
199 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
200 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
201 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
202 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
203 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
204 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
205 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
206 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
207 #define TXID_AUTO (PORT_BASE + 0xb8)
208 #define TXID_AUTO_CT3_OFF 1
209 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
210 #define TX_HARDRST_OFF 2
211 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
212 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
213 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
214 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
215 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
216 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
217 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
218 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
219 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
220 #define CON_CONTROL (PORT_BASE + 0x118)
221 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
222 #define CHL_INT0 (PORT_BASE + 0x1b4)
223 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
224 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
225 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
226 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
227 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
228 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
229 #define CHL_INT0_NOT_RDY_OFF 4
230 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
231 #define CHL_INT0_PHY_RDY_OFF 5
232 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
233 #define CHL_INT1 (PORT_BASE + 0x1b8)
234 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
235 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
236 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
237 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
238 #define CHL_INT2 (PORT_BASE + 0x1bc)
239 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
240 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
241 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
242 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
243 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
244 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
245 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
246 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
247 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
248 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
249 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
250 #define DMA_TX_STATUS_BUSY_OFF 0
251 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
252 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
253 #define DMA_RX_STATUS_BUSY_OFF 0
254 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
255
256 #define AXI_CFG (0x5100)
257 #define AM_CFG_MAX_TRANS (0x5010)
258 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
259
260 #define AXI_MASTER_CFG_BASE (0x5000)
261 #define AM_CTRL_GLOBAL (0x0)
262 #define AM_CURR_TRANS_RETURN (0x150)
263
264 /* HW dma structures */
265 /* Delivery queue header */
266 /* dw0 */
267 #define CMD_HDR_ABORT_FLAG_OFF 0
268 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
269 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
270 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
271 #define CMD_HDR_RESP_REPORT_OFF 5
272 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
273 #define CMD_HDR_TLR_CTRL_OFF 6
274 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
275 #define CMD_HDR_PORT_OFF 18
276 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
277 #define CMD_HDR_PRIORITY_OFF 27
278 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
279 #define CMD_HDR_CMD_OFF 29
280 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
281 /* dw1 */
282 #define CMD_HDR_DIR_OFF 5
283 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
284 #define CMD_HDR_RESET_OFF 7
285 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
286 #define CMD_HDR_VDTL_OFF 10
287 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
288 #define CMD_HDR_FRAME_TYPE_OFF 11
289 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
290 #define CMD_HDR_DEV_ID_OFF 16
291 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
292 /* dw2 */
293 #define CMD_HDR_CFL_OFF 0
294 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
295 #define CMD_HDR_NCQ_TAG_OFF 10
296 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
297 #define CMD_HDR_MRFL_OFF 15
298 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
299 #define CMD_HDR_SG_MOD_OFF 24
300 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
301 #define CMD_HDR_FIRST_BURST_OFF 26
302 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
303 /* dw3 */
304 #define CMD_HDR_IPTT_OFF 0
305 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
306 /* dw6 */
307 #define CMD_HDR_DIF_SGL_LEN_OFF 0
308 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
309 #define CMD_HDR_DATA_SGL_LEN_OFF 16
310 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
311 #define CMD_HDR_ABORT_IPTT_OFF 16
312 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
313
314 /* Completion header */
315 /* dw0 */
316 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
317 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
318 #define CMPLT_HDR_ERX_OFF 12
319 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
320 #define CMPLT_HDR_ABORT_STAT_OFF 13
321 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
322 /* abort_stat */
323 #define STAT_IO_NOT_VALID 0x1
324 #define STAT_IO_NO_DEVICE 0x2
325 #define STAT_IO_COMPLETE 0x3
326 #define STAT_IO_ABORTED 0x4
327 /* dw1 */
328 #define CMPLT_HDR_IPTT_OFF 0
329 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
330 #define CMPLT_HDR_DEV_ID_OFF 16
331 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
332
333 /* ITCT header */
334 /* qw0 */
335 #define ITCT_HDR_DEV_TYPE_OFF 0
336 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
337 #define ITCT_HDR_VALID_OFF 2
338 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
339 #define ITCT_HDR_MCR_OFF 5
340 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
341 #define ITCT_HDR_VLN_OFF 9
342 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
343 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
344 #define ITCT_HDR_SMP_TIMEOUT_8US 1
345 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
346 250) /* 2ms */
347 #define ITCT_HDR_AWT_CONTINUE_OFF 25
348 #define ITCT_HDR_PORT_ID_OFF 28
349 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
350 /* qw2 */
351 #define ITCT_HDR_INLT_OFF 0
352 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
353 #define ITCT_HDR_BITLT_OFF 16
354 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
355 #define ITCT_HDR_MCTLT_OFF 32
356 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
357 #define ITCT_HDR_RTOLT_OFF 48
358 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
359
360 #define HISI_SAS_FATAL_INT_NR 2
361
362 struct hisi_sas_complete_v2_hdr {
363 __le32 dw0;
364 __le32 dw1;
365 __le32 act;
366 __le32 dw3;
367 };
368
369 struct hisi_sas_err_record_v2 {
370 /* dw0 */
371 __le32 trans_tx_fail_type;
372
373 /* dw1 */
374 __le32 trans_rx_fail_type;
375
376 /* dw2 */
377 __le16 dma_tx_err_type;
378 __le16 sipc_rx_err_type;
379
380 /* dw3 */
381 __le32 dma_rx_err_type;
382 };
383
384 enum {
385 HISI_SAS_PHY_PHY_UPDOWN,
386 HISI_SAS_PHY_CHNL_INT,
387 HISI_SAS_PHY_INT_NR
388 };
389
390 enum {
391 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
392 TRANS_RX_FAIL_BASE = 0x100, /* dw1 */
393 DMA_TX_ERR_BASE = 0x200, /* dw2 bit 15-0 */
394 SIPC_RX_ERR_BASE = 0x300, /* dw2 bit 31-16*/
395 DMA_RX_ERR_BASE = 0x400, /* dw3 */
396
397 /* trans tx*/
398 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
399 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
400 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
401 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
402 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
403 RESERVED0, /* 0x5 */
404 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
405 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
406 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
407 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
408 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
409 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
410 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
411 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
412 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
413 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
414 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
415 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
416 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
417 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
418 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
419 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
420 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
421 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
422 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
423 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
424 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
425 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
426 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
427 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
428 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
429 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
430 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
431 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
432 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
433
434 /* trans rx */
435 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x100 */
436 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x101 for sata/stp */
437 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x102 for ssp/smp */
438 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x102 <] for sata/stp */
439 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x103 for sata/stp */
440 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x104 for sata/stp */
441 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x105 for smp */
442 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x105 <] for sata/stp */
443 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x106 for sata/stp*/
444 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x107 */
445 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x108 */
446 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x109 */
447 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x10a */
448 RESERVED1, /* 0x10b */
449 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x10c */
450 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x10d */
451 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x10e */
452 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x10f */
453 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x110 for ssp/smp */
454 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x111 for ssp */
455 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x111 <] for sata/stp */
456 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x112 for ssp*/
457 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x112 <] for sata/stp */
458 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x113 for ssp */
459 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x113 <] for sata */
460 RESERVED2, /* 0x114 */
461 RESERVED3, /* 0x115 */
462 RESERVED4, /* 0x116 */
463 RESERVED5, /* 0x117 */
464 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x118 */
465 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x119 */
466 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x11a */
467 RESERVED6, /* 0x11b */
468 RESERVED7, /* 0x11c */
469 RESERVED8, /* 0x11d */
470 RESERVED9, /* 0x11e */
471 TRANS_RX_R_ERR, /* 0x11f */
472
473 /* dma tx */
474 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x200 */
475 DMA_TX_DIF_APP_ERR, /* 0x201 */
476 DMA_TX_DIF_RPP_ERR, /* 0x202 */
477 DMA_TX_DATA_SGL_OVERFLOW, /* 0x203 */
478 DMA_TX_DIF_SGL_OVERFLOW, /* 0x204 */
479 DMA_TX_UNEXP_XFER_ERR, /* 0x205 */
480 DMA_TX_UNEXP_RETRANS_ERR, /* 0x206 */
481 DMA_TX_XFER_LEN_OVERFLOW, /* 0x207 */
482 DMA_TX_XFER_OFFSET_ERR, /* 0x208 */
483 DMA_TX_RAM_ECC_ERR, /* 0x209 */
484 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x20a */
485
486 /* sipc rx */
487 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x300 */
488 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x301 */
489 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x302 */
490 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x303 */
491 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x304 */
492 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x305 */
493 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x306 */
494 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x307 */
495 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x308 */
496 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x309 */
497 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x30a */
498
499 /* dma rx */
500 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x400 */
501 DMA_RX_DIF_APP_ERR, /* 0x401 */
502 DMA_RX_DIF_RPP_ERR, /* 0x402 */
503 DMA_RX_DATA_SGL_OVERFLOW, /* 0x403 */
504 DMA_RX_DIF_SGL_OVERFLOW, /* 0x404 */
505 DMA_RX_DATA_LEN_OVERFLOW, /* 0x405 */
506 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x406 */
507 DMA_RX_DATA_OFFSET_ERR, /* 0x407 */
508 RESERVED10, /* 0x408 */
509 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x409 */
510 DMA_RX_RESP_BUF_OVERFLOW, /* 0x40a */
511 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x40b */
512 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x40c */
513 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x40d */
514 DMA_RX_PIO_DATA_LEN_ERR, /* 0x40e */
515 DMA_RX_RDSETUP_STATUS_ERR, /* 0x40f */
516 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x410 */
517 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x411 */
518 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x412 */
519 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x413 */
520 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x414 */
521 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x415 */
522 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x416 */
523 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x417 */
524 DMA_RX_RAM_ECC_ERR, /* 0x418 */
525 DMA_RX_UNKNOWN_FRM_ERR, /* 0x419 */
526 };
527
528 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
529
530 #define DIR_NO_DATA 0
531 #define DIR_TO_INI 1
532 #define DIR_TO_DEVICE 2
533 #define DIR_RESERVED 3
534
535 #define SATA_PROTOCOL_NONDATA 0x1
536 #define SATA_PROTOCOL_PIO 0x2
537 #define SATA_PROTOCOL_DMA 0x4
538 #define SATA_PROTOCOL_FPDMA 0x8
539 #define SATA_PROTOCOL_ATAPI 0x10
540
541 static void hisi_sas_link_timeout_disable_link(unsigned long data);
542
543 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
544 {
545 void __iomem *regs = hisi_hba->regs + off;
546
547 return readl(regs);
548 }
549
550 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
551 {
552 void __iomem *regs = hisi_hba->regs + off;
553
554 return readl_relaxed(regs);
555 }
556
557 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
558 {
559 void __iomem *regs = hisi_hba->regs + off;
560
561 writel(val, regs);
562 }
563
564 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
565 u32 off, u32 val)
566 {
567 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
568
569 writel(val, regs);
570 }
571
572 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
573 int phy_no, u32 off)
574 {
575 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
576
577 return readl(regs);
578 }
579
580 /* This function needs to be protected from pre-emption. */
581 static int
582 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
583 struct domain_device *device)
584 {
585 unsigned int index = 0;
586 void *bitmap = hisi_hba->slot_index_tags;
587 int sata_dev = dev_is_sata(device);
588
589 while (1) {
590 index = find_next_zero_bit(bitmap, hisi_hba->slot_index_count,
591 index);
592 if (index >= hisi_hba->slot_index_count)
593 return -SAS_QUEUE_FULL;
594 /*
595 * SAS IPTT bit0 should be 1
596 */
597 if (sata_dev || (index & 1))
598 break;
599 index++;
600 }
601
602 set_bit(index, bitmap);
603 *slot_idx = index;
604 return 0;
605 }
606
607 static struct
608 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
609 {
610 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
611 struct hisi_sas_device *sas_dev = NULL;
612 int i, sata_dev = dev_is_sata(device);
613
614 spin_lock(&hisi_hba->lock);
615 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
616 /*
617 * SATA device id bit0 should be 0
618 */
619 if (sata_dev && (i & 1))
620 continue;
621 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
622 hisi_hba->devices[i].device_id = i;
623 sas_dev = &hisi_hba->devices[i];
624 sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
625 sas_dev->dev_type = device->dev_type;
626 sas_dev->hisi_hba = hisi_hba;
627 sas_dev->sas_device = device;
628 break;
629 }
630 }
631 spin_unlock(&hisi_hba->lock);
632
633 return sas_dev;
634 }
635
636 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
637 {
638 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
639
640 cfg &= ~PHY_CFG_DC_OPT_MSK;
641 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
642 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
643 }
644
645 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
646 {
647 struct sas_identify_frame identify_frame;
648 u32 *identify_buffer;
649
650 memset(&identify_frame, 0, sizeof(identify_frame));
651 identify_frame.dev_type = SAS_END_DEVICE;
652 identify_frame.frame_type = 0;
653 identify_frame._un1 = 1;
654 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
655 identify_frame.target_bits = SAS_PROTOCOL_NONE;
656 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
657 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
658 identify_frame.phy_id = phy_no;
659 identify_buffer = (u32 *)(&identify_frame);
660
661 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
662 __swab32(identify_buffer[0]));
663 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
664 __swab32(identify_buffer[1]));
665 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
666 __swab32(identify_buffer[2]));
667 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
668 __swab32(identify_buffer[3]));
669 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
670 __swab32(identify_buffer[4]));
671 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
672 __swab32(identify_buffer[5]));
673 }
674
675 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
676 struct hisi_sas_device *sas_dev)
677 {
678 struct domain_device *device = sas_dev->sas_device;
679 struct device *dev = &hisi_hba->pdev->dev;
680 u64 qw0, device_id = sas_dev->device_id;
681 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
682 struct domain_device *parent_dev = device->parent;
683 struct asd_sas_port *sas_port = device->port;
684 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
685
686 memset(itct, 0, sizeof(*itct));
687
688 /* qw0 */
689 qw0 = 0;
690 switch (sas_dev->dev_type) {
691 case SAS_END_DEVICE:
692 case SAS_EDGE_EXPANDER_DEVICE:
693 case SAS_FANOUT_EXPANDER_DEVICE:
694 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
695 break;
696 case SAS_SATA_DEV:
697 case SAS_SATA_PENDING:
698 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
699 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
700 else
701 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
702 break;
703 default:
704 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
705 sas_dev->dev_type);
706 }
707
708 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
709 (device->linkrate << ITCT_HDR_MCR_OFF) |
710 (1 << ITCT_HDR_VLN_OFF) |
711 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
712 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
713 (port->id << ITCT_HDR_PORT_ID_OFF));
714 itct->qw0 = cpu_to_le64(qw0);
715
716 /* qw1 */
717 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
718 itct->sas_addr = __swab64(itct->sas_addr);
719
720 /* qw2 */
721 if (!dev_is_sata(device))
722 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
723 (0x1ULL << ITCT_HDR_BITLT_OFF) |
724 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
725 (0x1ULL << ITCT_HDR_RTOLT_OFF));
726 }
727
728 static void free_device_v2_hw(struct hisi_hba *hisi_hba,
729 struct hisi_sas_device *sas_dev)
730 {
731 u64 dev_id = sas_dev->device_id;
732 struct device *dev = &hisi_hba->pdev->dev;
733 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
734 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
735 int i;
736
737 /* clear the itct interrupt state */
738 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
739 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
740 ENT_INT_SRC3_ITC_INT_MSK);
741
742 /* clear the itct int*/
743 for (i = 0; i < 2; i++) {
744 /* clear the itct table*/
745 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
746 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
747 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
748
749 udelay(10);
750 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
751 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
752 dev_dbg(dev, "got clear ITCT done interrupt\n");
753
754 /* invalid the itct state*/
755 memset(itct, 0, sizeof(struct hisi_sas_itct));
756 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
757 ENT_INT_SRC3_ITC_INT_MSK);
758
759 /* clear the itct */
760 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
761 dev_dbg(dev, "clear ITCT ok\n");
762 break;
763 }
764 }
765 }
766
767 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
768 {
769 int i, reset_val;
770 u32 val;
771 unsigned long end_time;
772 struct device *dev = &hisi_hba->pdev->dev;
773
774 /* The mask needs to be set depending on the number of phys */
775 if (hisi_hba->n_phy == 9)
776 reset_val = 0x1fffff;
777 else
778 reset_val = 0x7ffff;
779
780 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
781
782 /* Disable all of the PHYs */
783 for (i = 0; i < hisi_hba->n_phy; i++) {
784 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
785
786 phy_cfg &= ~PHY_CTRL_RESET_MSK;
787 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
788 }
789 udelay(50);
790
791 /* Ensure DMA tx & rx idle */
792 for (i = 0; i < hisi_hba->n_phy; i++) {
793 u32 dma_tx_status, dma_rx_status;
794
795 end_time = jiffies + msecs_to_jiffies(1000);
796
797 while (1) {
798 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
799 DMA_TX_STATUS);
800 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
801 DMA_RX_STATUS);
802
803 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
804 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
805 break;
806
807 msleep(20);
808 if (time_after(jiffies, end_time))
809 return -EIO;
810 }
811 }
812
813 /* Ensure axi bus idle */
814 end_time = jiffies + msecs_to_jiffies(1000);
815 while (1) {
816 u32 axi_status =
817 hisi_sas_read32(hisi_hba, AXI_CFG);
818
819 if (axi_status == 0)
820 break;
821
822 msleep(20);
823 if (time_after(jiffies, end_time))
824 return -EIO;
825 }
826
827 if (ACPI_HANDLE(dev)) {
828 acpi_status s;
829
830 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
831 if (ACPI_FAILURE(s)) {
832 dev_err(dev, "Reset failed\n");
833 return -EIO;
834 }
835 } else if (hisi_hba->ctrl) {
836 /* reset and disable clock*/
837 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
838 reset_val);
839 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
840 reset_val);
841 msleep(1);
842 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
843 if (reset_val != (val & reset_val)) {
844 dev_err(dev, "SAS reset fail.\n");
845 return -EIO;
846 }
847
848 /* De-reset and enable clock*/
849 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
850 reset_val);
851 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
852 reset_val);
853 msleep(1);
854 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
855 &val);
856 if (val & reset_val) {
857 dev_err(dev, "SAS de-reset fail.\n");
858 return -EIO;
859 }
860 } else
861 dev_warn(dev, "no reset method\n");
862
863 return 0;
864 }
865
866 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
867 {
868 struct device *dev = &hisi_hba->pdev->dev;
869 int i;
870
871 /* Global registers init */
872
873 /* Deal with am-max-transmissions quirk */
874 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
875 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
876 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
877 0x2020);
878 } /* Else, use defaults -> do nothing */
879
880 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
881 (u32)((1ULL << hisi_hba->queue_count) - 1));
882 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
883 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
884 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
885 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
886 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
887 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
888 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
889 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
890 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
891 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
892 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
893 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
894 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
895 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
896 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
897 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
898 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
899 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
900 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
901 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
902 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
903 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
904 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
905 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
906 for (i = 0; i < hisi_hba->queue_count; i++)
907 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
908
909 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
910 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
911
912 for (i = 0; i < hisi_hba->n_phy; i++) {
913 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
914 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
915 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
916 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
917 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
918 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10);
919 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
920 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
921 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
922 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
923 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
924 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
925 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc);
926 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
927 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
928 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
929 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
930 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
931 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
932 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
933 if (hisi_hba->refclk_frequency_mhz == 66)
934 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
935 /* else, do nothing -> leave it how you found it */
936 }
937
938 for (i = 0; i < hisi_hba->queue_count; i++) {
939 /* Delivery queue */
940 hisi_sas_write32(hisi_hba,
941 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
942 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
943
944 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
945 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
946
947 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
948 HISI_SAS_QUEUE_SLOTS);
949
950 /* Completion queue */
951 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
952 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
953
954 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
955 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
956
957 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
958 HISI_SAS_QUEUE_SLOTS);
959 }
960
961 /* itct */
962 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
963 lower_32_bits(hisi_hba->itct_dma));
964
965 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
966 upper_32_bits(hisi_hba->itct_dma));
967
968 /* iost */
969 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
970 lower_32_bits(hisi_hba->iost_dma));
971
972 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
973 upper_32_bits(hisi_hba->iost_dma));
974
975 /* breakpoint */
976 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
977 lower_32_bits(hisi_hba->breakpoint_dma));
978
979 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
980 upper_32_bits(hisi_hba->breakpoint_dma));
981
982 /* SATA broken msg */
983 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
984 lower_32_bits(hisi_hba->sata_breakpoint_dma));
985
986 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
987 upper_32_bits(hisi_hba->sata_breakpoint_dma));
988
989 /* SATA initial fis */
990 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
991 lower_32_bits(hisi_hba->initial_fis_dma));
992
993 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
994 upper_32_bits(hisi_hba->initial_fis_dma));
995 }
996
997 static void hisi_sas_link_timeout_enable_link(unsigned long data)
998 {
999 struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
1000 int i, reg_val;
1001
1002 for (i = 0; i < hisi_hba->n_phy; i++) {
1003 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1004 if (!(reg_val & BIT(0))) {
1005 hisi_sas_phy_write32(hisi_hba, i,
1006 CON_CONTROL, 0x7);
1007 break;
1008 }
1009 }
1010
1011 hisi_hba->timer.function = hisi_sas_link_timeout_disable_link;
1012 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1013 }
1014
1015 static void hisi_sas_link_timeout_disable_link(unsigned long data)
1016 {
1017 struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
1018 int i, reg_val;
1019
1020 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1021 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1022 if (reg_val & BIT(i)) {
1023 hisi_sas_phy_write32(hisi_hba, i,
1024 CON_CONTROL, 0x6);
1025 break;
1026 }
1027 }
1028
1029 hisi_hba->timer.function = hisi_sas_link_timeout_enable_link;
1030 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1031 }
1032
1033 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1034 {
1035 hisi_hba->timer.data = (unsigned long)hisi_hba;
1036 hisi_hba->timer.function = hisi_sas_link_timeout_disable_link;
1037 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1038 add_timer(&hisi_hba->timer);
1039 }
1040
1041 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1042 {
1043 struct device *dev = &hisi_hba->pdev->dev;
1044 int rc;
1045
1046 rc = reset_hw_v2_hw(hisi_hba);
1047 if (rc) {
1048 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1049 return rc;
1050 }
1051
1052 msleep(100);
1053 init_reg_v2_hw(hisi_hba);
1054
1055 return 0;
1056 }
1057
1058 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1059 {
1060 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1061
1062 cfg |= PHY_CFG_ENA_MSK;
1063 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1064 }
1065
1066 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1067 {
1068 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1069
1070 cfg &= ~PHY_CFG_ENA_MSK;
1071 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1072 }
1073
1074 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1075 {
1076 config_id_frame_v2_hw(hisi_hba, phy_no);
1077 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1078 enable_phy_v2_hw(hisi_hba, phy_no);
1079 }
1080
1081 static void stop_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1082 {
1083 disable_phy_v2_hw(hisi_hba, phy_no);
1084 }
1085
1086 static void stop_phys_v2_hw(struct hisi_hba *hisi_hba)
1087 {
1088 int i;
1089
1090 for (i = 0; i < hisi_hba->n_phy; i++)
1091 stop_phy_v2_hw(hisi_hba, i);
1092 }
1093
1094 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1095 {
1096 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1097 u32 txid_auto;
1098
1099 stop_phy_v2_hw(hisi_hba, phy_no);
1100 if (phy->identify.device_type == SAS_END_DEVICE) {
1101 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1102 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1103 txid_auto | TX_HARDRST_MSK);
1104 }
1105 msleep(100);
1106 start_phy_v2_hw(hisi_hba, phy_no);
1107 }
1108
1109 static void start_phys_v2_hw(struct hisi_hba *hisi_hba)
1110 {
1111 int i;
1112
1113 for (i = 0; i < hisi_hba->n_phy; i++)
1114 start_phy_v2_hw(hisi_hba, i);
1115 }
1116
1117 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1118 {
1119 start_phys_v2_hw(hisi_hba);
1120 }
1121
1122 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1123 {
1124 u32 sl_control;
1125
1126 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1127 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1128 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1129 msleep(1);
1130 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1131 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1132 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1133 }
1134
1135 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1136 {
1137 return SAS_LINK_RATE_12_0_GBPS;
1138 }
1139
1140 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1141 struct sas_phy_linkrates *r)
1142 {
1143 u32 prog_phy_link_rate =
1144 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1145 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1146 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1147 int i;
1148 enum sas_linkrate min, max;
1149 u32 rate_mask = 0;
1150
1151 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1152 max = sas_phy->phy->maximum_linkrate;
1153 min = r->minimum_linkrate;
1154 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1155 max = r->maximum_linkrate;
1156 min = sas_phy->phy->minimum_linkrate;
1157 } else
1158 return;
1159
1160 sas_phy->phy->maximum_linkrate = max;
1161 sas_phy->phy->minimum_linkrate = min;
1162
1163 min -= SAS_LINK_RATE_1_5_GBPS;
1164 max -= SAS_LINK_RATE_1_5_GBPS;
1165
1166 for (i = 0; i <= max; i++)
1167 rate_mask |= 1 << (i * 2);
1168
1169 prog_phy_link_rate &= ~0xff;
1170 prog_phy_link_rate |= rate_mask;
1171
1172 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1173 prog_phy_link_rate);
1174
1175 phy_hard_reset_v2_hw(hisi_hba, phy_no);
1176 }
1177
1178 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1179 {
1180 int i, bitmap = 0;
1181 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1182 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1183
1184 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1185 if (phy_state & 1 << i)
1186 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1187 bitmap |= 1 << i;
1188
1189 if (hisi_hba->n_phy == 9) {
1190 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1191
1192 if (phy_state & 1 << 8)
1193 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1194 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1195 bitmap |= 1 << 9;
1196 }
1197
1198 return bitmap;
1199 }
1200
1201 /**
1202 * This function allocates across all queues to load balance.
1203 * Slots are allocated from queues in a round-robin fashion.
1204 *
1205 * The callpath to this function and upto writing the write
1206 * queue pointer should be safe from interruption.
1207 */
1208 static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, u32 dev_id,
1209 int *q, int *s)
1210 {
1211 struct device *dev = &hisi_hba->pdev->dev;
1212 struct hisi_sas_dq *dq;
1213 u32 r, w;
1214 int queue = dev_id % hisi_hba->queue_count;
1215
1216 dq = &hisi_hba->dq[queue];
1217 w = dq->wr_point;
1218 r = hisi_sas_read32_relaxed(hisi_hba,
1219 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1220 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1221 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
1222 queue, r, w);
1223 return -EAGAIN;
1224 }
1225
1226 *q = queue;
1227 *s = w;
1228 return 0;
1229 }
1230
1231 static void start_delivery_v2_hw(struct hisi_hba *hisi_hba)
1232 {
1233 int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
1234 int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
1235 struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue];
1236
1237 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1238 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1239 dq->wr_point);
1240 }
1241
1242 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1243 struct hisi_sas_slot *slot,
1244 struct hisi_sas_cmd_hdr *hdr,
1245 struct scatterlist *scatter,
1246 int n_elem)
1247 {
1248 struct device *dev = &hisi_hba->pdev->dev;
1249 struct scatterlist *sg;
1250 int i;
1251
1252 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1253 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1254 n_elem);
1255 return -EINVAL;
1256 }
1257
1258 slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
1259 &slot->sge_page_dma);
1260 if (!slot->sge_page)
1261 return -ENOMEM;
1262
1263 for_each_sg(scatter, sg, n_elem, i) {
1264 struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
1265
1266 entry->addr = cpu_to_le64(sg_dma_address(sg));
1267 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1268 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1269 entry->data_off = 0;
1270 }
1271
1272 hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
1273
1274 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1275
1276 return 0;
1277 }
1278
1279 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1280 struct hisi_sas_slot *slot)
1281 {
1282 struct sas_task *task = slot->task;
1283 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1284 struct domain_device *device = task->dev;
1285 struct device *dev = &hisi_hba->pdev->dev;
1286 struct hisi_sas_port *port = slot->port;
1287 struct scatterlist *sg_req, *sg_resp;
1288 struct hisi_sas_device *sas_dev = device->lldd_dev;
1289 dma_addr_t req_dma_addr;
1290 unsigned int req_len, resp_len;
1291 int elem, rc;
1292
1293 /*
1294 * DMA-map SMP request, response buffers
1295 */
1296 /* req */
1297 sg_req = &task->smp_task.smp_req;
1298 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1299 if (!elem)
1300 return -ENOMEM;
1301 req_len = sg_dma_len(sg_req);
1302 req_dma_addr = sg_dma_address(sg_req);
1303
1304 /* resp */
1305 sg_resp = &task->smp_task.smp_resp;
1306 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1307 if (!elem) {
1308 rc = -ENOMEM;
1309 goto err_out_req;
1310 }
1311 resp_len = sg_dma_len(sg_resp);
1312 if ((req_len & 0x3) || (resp_len & 0x3)) {
1313 rc = -EINVAL;
1314 goto err_out_resp;
1315 }
1316
1317 /* create header */
1318 /* dw0 */
1319 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1320 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1321 (2 << CMD_HDR_CMD_OFF)); /* smp */
1322
1323 /* map itct entry */
1324 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1325 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1326 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1327
1328 /* dw2 */
1329 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1330 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1331 CMD_HDR_MRFL_OFF));
1332
1333 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1334
1335 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1336 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1337
1338 return 0;
1339
1340 err_out_resp:
1341 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1342 DMA_FROM_DEVICE);
1343 err_out_req:
1344 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1345 DMA_TO_DEVICE);
1346 return rc;
1347 }
1348
1349 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1350 struct hisi_sas_slot *slot, int is_tmf,
1351 struct hisi_sas_tmf_task *tmf)
1352 {
1353 struct sas_task *task = slot->task;
1354 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1355 struct domain_device *device = task->dev;
1356 struct hisi_sas_device *sas_dev = device->lldd_dev;
1357 struct hisi_sas_port *port = slot->port;
1358 struct sas_ssp_task *ssp_task = &task->ssp_task;
1359 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1360 int has_data = 0, rc, priority = is_tmf;
1361 u8 *buf_cmd;
1362 u32 dw1 = 0, dw2 = 0;
1363
1364 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1365 (2 << CMD_HDR_TLR_CTRL_OFF) |
1366 (port->id << CMD_HDR_PORT_OFF) |
1367 (priority << CMD_HDR_PRIORITY_OFF) |
1368 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1369
1370 dw1 = 1 << CMD_HDR_VDTL_OFF;
1371 if (is_tmf) {
1372 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1373 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1374 } else {
1375 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1376 switch (scsi_cmnd->sc_data_direction) {
1377 case DMA_TO_DEVICE:
1378 has_data = 1;
1379 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1380 break;
1381 case DMA_FROM_DEVICE:
1382 has_data = 1;
1383 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1384 break;
1385 default:
1386 dw1 &= ~CMD_HDR_DIR_MSK;
1387 }
1388 }
1389
1390 /* map itct entry */
1391 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1392 hdr->dw1 = cpu_to_le32(dw1);
1393
1394 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1395 + 3) / 4) << CMD_HDR_CFL_OFF) |
1396 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1397 (2 << CMD_HDR_SG_MOD_OFF);
1398 hdr->dw2 = cpu_to_le32(dw2);
1399
1400 hdr->transfer_tags = cpu_to_le32(slot->idx);
1401
1402 if (has_data) {
1403 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1404 slot->n_elem);
1405 if (rc)
1406 return rc;
1407 }
1408
1409 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1410 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1411 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1412
1413 buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
1414
1415 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1416 if (!is_tmf) {
1417 buf_cmd[9] = task->ssp_task.task_attr |
1418 (task->ssp_task.task_prio << 3);
1419 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1420 task->ssp_task.cmd->cmd_len);
1421 } else {
1422 buf_cmd[10] = tmf->tmf;
1423 switch (tmf->tmf) {
1424 case TMF_ABORT_TASK:
1425 case TMF_QUERY_TASK:
1426 buf_cmd[12] =
1427 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1428 buf_cmd[13] =
1429 tmf->tag_of_task_to_be_managed & 0xff;
1430 break;
1431 default:
1432 break;
1433 }
1434 }
1435
1436 return 0;
1437 }
1438
1439 static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1440 struct hisi_sas_slot *slot)
1441 {
1442 struct task_status_struct *ts = &task->task_status;
1443 struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf;
1444 struct dev_to_host_fis *d2h = slot->status_buffer +
1445 sizeof(struct hisi_sas_err_record);
1446
1447 resp->frame_len = sizeof(struct dev_to_host_fis);
1448 memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis));
1449
1450 ts->buf_valid_size = sizeof(*resp);
1451 }
1452
1453 /* by default, task resp is complete */
1454 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
1455 struct sas_task *task,
1456 struct hisi_sas_slot *slot)
1457 {
1458 struct task_status_struct *ts = &task->task_status;
1459 struct hisi_sas_err_record_v2 *err_record = slot->status_buffer;
1460 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
1461 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
1462 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
1463 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
1464 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
1465 int error = -1;
1466
1467 if (dma_rx_err_type) {
1468 error = ffs(dma_rx_err_type)
1469 - 1 + DMA_RX_ERR_BASE;
1470 } else if (sipc_rx_err_type) {
1471 error = ffs(sipc_rx_err_type)
1472 - 1 + SIPC_RX_ERR_BASE;
1473 } else if (dma_tx_err_type) {
1474 error = ffs(dma_tx_err_type)
1475 - 1 + DMA_TX_ERR_BASE;
1476 } else if (trans_rx_fail_type) {
1477 error = ffs(trans_rx_fail_type)
1478 - 1 + TRANS_RX_FAIL_BASE;
1479 } else if (trans_tx_fail_type) {
1480 error = ffs(trans_tx_fail_type)
1481 - 1 + TRANS_TX_FAIL_BASE;
1482 }
1483
1484 switch (task->task_proto) {
1485 case SAS_PROTOCOL_SSP:
1486 {
1487 switch (error) {
1488 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
1489 {
1490 ts->stat = SAS_OPEN_REJECT;
1491 ts->open_rej_reason = SAS_OREJ_NO_DEST;
1492 break;
1493 }
1494 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
1495 {
1496 ts->stat = SAS_OPEN_REJECT;
1497 ts->open_rej_reason = SAS_OREJ_PATH_BLOCKED;
1498 break;
1499 }
1500 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
1501 {
1502 ts->stat = SAS_OPEN_REJECT;
1503 ts->open_rej_reason = SAS_OREJ_EPROTO;
1504 break;
1505 }
1506 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
1507 {
1508 ts->stat = SAS_OPEN_REJECT;
1509 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1510 break;
1511 }
1512 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
1513 {
1514 ts->stat = SAS_OPEN_REJECT;
1515 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1516 break;
1517 }
1518 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
1519 {
1520 ts->stat = SAS_OPEN_REJECT;
1521 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1522 break;
1523 }
1524 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
1525 {
1526 ts->stat = SAS_OPEN_REJECT;
1527 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1528 break;
1529 }
1530 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
1531 {
1532 ts->stat = SAS_OPEN_REJECT;
1533 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1534 break;
1535 }
1536 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
1537 {
1538 /* not sure */
1539 ts->stat = SAS_DEV_NO_RESPONSE;
1540 break;
1541 }
1542 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
1543 {
1544 ts->stat = SAS_PHY_DOWN;
1545 break;
1546 }
1547 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
1548 {
1549 ts->stat = SAS_OPEN_TO;
1550 break;
1551 }
1552 case DMA_RX_DATA_LEN_OVERFLOW:
1553 {
1554 ts->stat = SAS_DATA_OVERRUN;
1555 ts->residual = 0;
1556 break;
1557 }
1558 case DMA_RX_DATA_LEN_UNDERFLOW:
1559 case SIPC_RX_DATA_UNDERFLOW_ERR:
1560 {
1561 ts->residual = trans_tx_fail_type;
1562 ts->stat = SAS_DATA_UNDERRUN;
1563 break;
1564 }
1565 case TRANS_TX_ERR_FRAME_TXED:
1566 {
1567 /* This will request a retry */
1568 ts->stat = SAS_QUEUE_FULL;
1569 slot->abort = 1;
1570 break;
1571 }
1572 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
1573 case TRANS_TX_ERR_PHY_NOT_ENABLE:
1574 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
1575 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
1576 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
1577 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
1578 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
1579 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
1580 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
1581 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
1582 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1583 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
1584 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
1585 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
1586 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
1587 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
1588 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
1589 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
1590 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
1591 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
1592 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
1593 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
1594 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
1595 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1596 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
1597 case TRANS_RX_ERR_WITH_DATA_LEN0:
1598 case TRANS_RX_ERR_WITH_BAD_HASH:
1599 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
1600 case TRANS_RX_SSP_FRM_LEN_ERR:
1601 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
1602 case DMA_TX_UNEXP_XFER_ERR:
1603 case DMA_TX_UNEXP_RETRANS_ERR:
1604 case DMA_TX_XFER_LEN_OVERFLOW:
1605 case DMA_TX_XFER_OFFSET_ERR:
1606 case DMA_RX_DATA_OFFSET_ERR:
1607 case DMA_RX_UNEXP_NORM_RESP_ERR:
1608 case DMA_RX_UNEXP_RDFRAME_ERR:
1609 case DMA_RX_UNKNOWN_FRM_ERR:
1610 {
1611 ts->stat = SAS_OPEN_REJECT;
1612 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1613 break;
1614 }
1615 default:
1616 break;
1617 }
1618 }
1619 break;
1620 case SAS_PROTOCOL_SMP:
1621 ts->stat = SAM_STAT_CHECK_CONDITION;
1622 break;
1623
1624 case SAS_PROTOCOL_SATA:
1625 case SAS_PROTOCOL_STP:
1626 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1627 {
1628 switch (error) {
1629 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
1630 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
1631 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
1632 {
1633 ts->resp = SAS_TASK_UNDELIVERED;
1634 ts->stat = SAS_DEV_NO_RESPONSE;
1635 break;
1636 }
1637 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
1638 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
1639 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
1640 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
1641 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
1642 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
1643 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
1644 {
1645 ts->stat = SAS_OPEN_REJECT;
1646 break;
1647 }
1648 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
1649 {
1650 ts->stat = SAS_OPEN_TO;
1651 break;
1652 }
1653 case DMA_RX_DATA_LEN_OVERFLOW:
1654 {
1655 ts->stat = SAS_DATA_OVERRUN;
1656 break;
1657 }
1658 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
1659 case TRANS_TX_ERR_PHY_NOT_ENABLE:
1660 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
1661 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
1662 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
1663 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
1664 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
1665 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
1666 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
1667 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
1668 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1669 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
1670 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
1671 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
1672 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
1673 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
1674 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
1675 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
1676 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
1677 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
1678 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
1679 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
1680 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
1681 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
1682 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1683 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
1684 case TRANS_RX_ERR_WITH_DATA_LEN0:
1685 case TRANS_RX_ERR_WITH_BAD_HASH:
1686 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
1687 case TRANS_RX_SSP_FRM_LEN_ERR:
1688 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
1689 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
1690 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
1691 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
1692 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
1693 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
1694 case SIPC_RX_SATA_UNEXP_FIS_ERR:
1695 case DMA_RX_SATA_FRAME_TYPE_ERR:
1696 case DMA_RX_UNEXP_RDFRAME_ERR:
1697 case DMA_RX_PIO_DATA_LEN_ERR:
1698 case DMA_RX_RDSETUP_STATUS_ERR:
1699 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
1700 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
1701 case DMA_RX_RDSETUP_LEN_ODD_ERR:
1702 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
1703 case DMA_RX_RDSETUP_LEN_OVER_ERR:
1704 case DMA_RX_RDSETUP_OFFSET_ERR:
1705 case DMA_RX_RDSETUP_ACTIVE_ERR:
1706 case DMA_RX_RDSETUP_ESTATUS_ERR:
1707 case DMA_RX_UNKNOWN_FRM_ERR:
1708 {
1709 ts->stat = SAS_OPEN_REJECT;
1710 break;
1711 }
1712 default:
1713 {
1714 ts->stat = SAS_PROTO_RESPONSE;
1715 break;
1716 }
1717 }
1718 sata_done_v2_hw(hisi_hba, task, slot);
1719 }
1720 break;
1721 default:
1722 break;
1723 }
1724 }
1725
1726 static int
1727 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot,
1728 int abort)
1729 {
1730 struct sas_task *task = slot->task;
1731 struct hisi_sas_device *sas_dev;
1732 struct device *dev = &hisi_hba->pdev->dev;
1733 struct task_status_struct *ts;
1734 struct domain_device *device;
1735 enum exec_status sts;
1736 struct hisi_sas_complete_v2_hdr *complete_queue =
1737 hisi_hba->complete_hdr[slot->cmplt_queue];
1738 struct hisi_sas_complete_v2_hdr *complete_hdr =
1739 &complete_queue[slot->cmplt_queue_slot];
1740
1741 if (unlikely(!task || !task->lldd_task || !task->dev))
1742 return -EINVAL;
1743
1744 ts = &task->task_status;
1745 device = task->dev;
1746 sas_dev = device->lldd_dev;
1747
1748 task->task_state_flags &=
1749 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1750 task->task_state_flags |= SAS_TASK_STATE_DONE;
1751
1752 memset(ts, 0, sizeof(*ts));
1753 ts->resp = SAS_TASK_COMPLETE;
1754
1755 if (unlikely(!sas_dev || abort)) {
1756 if (!sas_dev)
1757 dev_dbg(dev, "slot complete: port has not device\n");
1758 ts->stat = SAS_PHY_DOWN;
1759 goto out;
1760 }
1761
1762 /* Use SAS+TMF status codes */
1763 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1764 >> CMPLT_HDR_ABORT_STAT_OFF) {
1765 case STAT_IO_ABORTED:
1766 /* this io has been aborted by abort command */
1767 ts->stat = SAS_ABORTED_TASK;
1768 goto out;
1769 case STAT_IO_COMPLETE:
1770 /* internal abort command complete */
1771 ts->stat = TMF_RESP_FUNC_COMPLETE;
1772 goto out;
1773 case STAT_IO_NO_DEVICE:
1774 ts->stat = TMF_RESP_FUNC_COMPLETE;
1775 goto out;
1776 case STAT_IO_NOT_VALID:
1777 /* abort single io, controller don't find
1778 * the io need to abort
1779 */
1780 ts->stat = TMF_RESP_FUNC_FAILED;
1781 goto out;
1782 default:
1783 break;
1784 }
1785
1786 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
1787 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
1788
1789 slot_err_v2_hw(hisi_hba, task, slot);
1790 if (unlikely(slot->abort)) {
1791 queue_work(hisi_hba->wq, &slot->abort_slot);
1792 /* immediately return and do not complete */
1793 return ts->stat;
1794 }
1795 goto out;
1796 }
1797
1798 switch (task->task_proto) {
1799 case SAS_PROTOCOL_SSP:
1800 {
1801 struct ssp_response_iu *iu = slot->status_buffer +
1802 sizeof(struct hisi_sas_err_record);
1803
1804 sas_ssp_task_response(dev, task, iu);
1805 break;
1806 }
1807 case SAS_PROTOCOL_SMP:
1808 {
1809 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1810 void *to;
1811
1812 ts->stat = SAM_STAT_GOOD;
1813 to = kmap_atomic(sg_page(sg_resp));
1814
1815 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1816 DMA_FROM_DEVICE);
1817 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1818 DMA_TO_DEVICE);
1819 memcpy(to + sg_resp->offset,
1820 slot->status_buffer +
1821 sizeof(struct hisi_sas_err_record),
1822 sg_dma_len(sg_resp));
1823 kunmap_atomic(to);
1824 break;
1825 }
1826 case SAS_PROTOCOL_SATA:
1827 case SAS_PROTOCOL_STP:
1828 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1829 {
1830 ts->stat = SAM_STAT_GOOD;
1831 sata_done_v2_hw(hisi_hba, task, slot);
1832 break;
1833 }
1834 default:
1835 ts->stat = SAM_STAT_CHECK_CONDITION;
1836 break;
1837 }
1838
1839 if (!slot->port->port_attached) {
1840 dev_err(dev, "slot complete: port %d has removed\n",
1841 slot->port->sas_port.id);
1842 ts->stat = SAS_PHY_DOWN;
1843 }
1844
1845 out:
1846
1847 hisi_sas_slot_task_free(hisi_hba, task, slot);
1848 sts = ts->stat;
1849
1850 if (task->task_done)
1851 task->task_done(task);
1852
1853 return sts;
1854 }
1855
1856 static u8 get_ata_protocol(u8 cmd, int direction)
1857 {
1858 switch (cmd) {
1859 case ATA_CMD_FPDMA_WRITE:
1860 case ATA_CMD_FPDMA_READ:
1861 case ATA_CMD_FPDMA_RECV:
1862 case ATA_CMD_FPDMA_SEND:
1863 case ATA_CMD_NCQ_NON_DATA:
1864 return SATA_PROTOCOL_FPDMA;
1865
1866 case ATA_CMD_DOWNLOAD_MICRO:
1867 case ATA_CMD_ID_ATA:
1868 case ATA_CMD_PMP_READ:
1869 case ATA_CMD_READ_LOG_EXT:
1870 case ATA_CMD_PIO_READ:
1871 case ATA_CMD_PIO_READ_EXT:
1872 case ATA_CMD_PMP_WRITE:
1873 case ATA_CMD_WRITE_LOG_EXT:
1874 case ATA_CMD_PIO_WRITE:
1875 case ATA_CMD_PIO_WRITE_EXT:
1876 return SATA_PROTOCOL_PIO;
1877
1878 case ATA_CMD_DSM:
1879 case ATA_CMD_DOWNLOAD_MICRO_DMA:
1880 case ATA_CMD_PMP_READ_DMA:
1881 case ATA_CMD_PMP_WRITE_DMA:
1882 case ATA_CMD_READ:
1883 case ATA_CMD_READ_EXT:
1884 case ATA_CMD_READ_LOG_DMA_EXT:
1885 case ATA_CMD_READ_STREAM_DMA_EXT:
1886 case ATA_CMD_TRUSTED_RCV_DMA:
1887 case ATA_CMD_TRUSTED_SND_DMA:
1888 case ATA_CMD_WRITE:
1889 case ATA_CMD_WRITE_EXT:
1890 case ATA_CMD_WRITE_FUA_EXT:
1891 case ATA_CMD_WRITE_QUEUED:
1892 case ATA_CMD_WRITE_LOG_DMA_EXT:
1893 case ATA_CMD_WRITE_STREAM_DMA_EXT:
1894 return SATA_PROTOCOL_DMA;
1895
1896 case ATA_CMD_CHK_POWER:
1897 case ATA_CMD_DEV_RESET:
1898 case ATA_CMD_EDD:
1899 case ATA_CMD_FLUSH:
1900 case ATA_CMD_FLUSH_EXT:
1901 case ATA_CMD_VERIFY:
1902 case ATA_CMD_VERIFY_EXT:
1903 case ATA_CMD_SET_FEATURES:
1904 case ATA_CMD_STANDBY:
1905 case ATA_CMD_STANDBYNOW1:
1906 return SATA_PROTOCOL_NONDATA;
1907 default:
1908 if (direction == DMA_NONE)
1909 return SATA_PROTOCOL_NONDATA;
1910 return SATA_PROTOCOL_PIO;
1911 }
1912 }
1913
1914 static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag)
1915 {
1916 struct ata_queued_cmd *qc = task->uldd_task;
1917
1918 if (qc) {
1919 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
1920 qc->tf.command == ATA_CMD_FPDMA_READ) {
1921 *tag = qc->tag;
1922 return 1;
1923 }
1924 }
1925 return 0;
1926 }
1927
1928 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
1929 struct hisi_sas_slot *slot)
1930 {
1931 struct sas_task *task = slot->task;
1932 struct domain_device *device = task->dev;
1933 struct domain_device *parent_dev = device->parent;
1934 struct hisi_sas_device *sas_dev = device->lldd_dev;
1935 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1936 struct asd_sas_port *sas_port = device->port;
1937 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1938 u8 *buf_cmd;
1939 int has_data = 0, rc = 0, hdr_tag = 0;
1940 u32 dw1 = 0, dw2 = 0;
1941
1942 /* create header */
1943 /* dw0 */
1944 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1945 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1946 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1947 else
1948 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1949
1950 /* dw1 */
1951 switch (task->data_dir) {
1952 case DMA_TO_DEVICE:
1953 has_data = 1;
1954 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1955 break;
1956 case DMA_FROM_DEVICE:
1957 has_data = 1;
1958 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1959 break;
1960 default:
1961 dw1 &= ~CMD_HDR_DIR_MSK;
1962 }
1963
1964 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1965 (task->ata_task.fis.control & ATA_SRST))
1966 dw1 |= 1 << CMD_HDR_RESET_OFF;
1967
1968 dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir))
1969 << CMD_HDR_FRAME_TYPE_OFF;
1970 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1971 hdr->dw1 = cpu_to_le32(dw1);
1972
1973 /* dw2 */
1974 if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) {
1975 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1976 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1977 }
1978
1979 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1980 2 << CMD_HDR_SG_MOD_OFF;
1981 hdr->dw2 = cpu_to_le32(dw2);
1982
1983 /* dw3 */
1984 hdr->transfer_tags = cpu_to_le32(slot->idx);
1985
1986 if (has_data) {
1987 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1988 slot->n_elem);
1989 if (rc)
1990 return rc;
1991 }
1992
1993
1994 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1995 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1996 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1997
1998 buf_cmd = slot->command_table;
1999
2000 if (likely(!task->ata_task.device_control_reg_update))
2001 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2002 /* fill in command FIS */
2003 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2004
2005 return 0;
2006 }
2007
2008 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2009 struct hisi_sas_slot *slot,
2010 int device_id, int abort_flag, int tag_to_abort)
2011 {
2012 struct sas_task *task = slot->task;
2013 struct domain_device *dev = task->dev;
2014 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2015 struct hisi_sas_port *port = slot->port;
2016
2017 /* dw0 */
2018 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2019 (port->id << CMD_HDR_PORT_OFF) |
2020 ((dev_is_sata(dev) ? 1:0) <<
2021 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2022 (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2023
2024 /* dw1 */
2025 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2026
2027 /* dw7 */
2028 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2029 hdr->transfer_tags = cpu_to_le32(slot->idx);
2030
2031 return 0;
2032 }
2033
2034 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2035 {
2036 int i, res = 0;
2037 u32 context, port_id, link_rate, hard_phy_linkrate;
2038 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2039 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2040 struct device *dev = &hisi_hba->pdev->dev;
2041 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2042 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2043
2044 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2045
2046 /* Check for SATA dev */
2047 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
2048 if (context & (1 << phy_no))
2049 goto end;
2050
2051 if (phy_no == 8) {
2052 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2053
2054 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2055 PORT_STATE_PHY8_PORT_NUM_OFF;
2056 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2057 PORT_STATE_PHY8_CONN_RATE_OFF;
2058 } else {
2059 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2060 port_id = (port_id >> (4 * phy_no)) & 0xf;
2061 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2062 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2063 }
2064
2065 if (port_id == 0xf) {
2066 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2067 res = IRQ_NONE;
2068 goto end;
2069 }
2070
2071 for (i = 0; i < 6; i++) {
2072 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2073 RX_IDAF_DWORD0 + (i * 4));
2074 frame_rcvd[i] = __swab32(idaf);
2075 }
2076
2077 sas_phy->linkrate = link_rate;
2078 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2079 HARD_PHY_LINKRATE);
2080 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2081 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2082
2083 sas_phy->oob_mode = SAS_OOB_MODE;
2084 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2085 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2086 phy->port_id = port_id;
2087 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2088 phy->phy_type |= PORT_TYPE_SAS;
2089 phy->phy_attached = 1;
2090 phy->identify.device_type = id->dev_type;
2091 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
2092 if (phy->identify.device_type == SAS_END_DEVICE)
2093 phy->identify.target_port_protocols =
2094 SAS_PROTOCOL_SSP;
2095 else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2096 phy->identify.target_port_protocols =
2097 SAS_PROTOCOL_SMP;
2098 if (!timer_pending(&hisi_hba->timer))
2099 set_link_timer_quirk(hisi_hba);
2100 }
2101 queue_work(hisi_hba->wq, &phy->phyup_ws);
2102
2103 end:
2104 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2105 CHL_INT0_SL_PHY_ENABLE_MSK);
2106 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2107
2108 return res;
2109 }
2110
2111 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2112 {
2113 u32 port_state;
2114
2115 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2116 if (port_state & 0x1ff)
2117 return true;
2118
2119 return false;
2120 }
2121
2122 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2123 {
2124 int res = 0;
2125 u32 phy_state, sl_ctrl, txid_auto;
2126 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2127 struct hisi_sas_port *port = phy->port;
2128
2129 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2130
2131 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2132 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2133
2134 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2135 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2136 sl_ctrl & ~SL_CONTROL_CTA_MSK);
2137 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2138 if (!check_any_wideports_v2_hw(hisi_hba) &&
2139 timer_pending(&hisi_hba->timer))
2140 del_timer(&hisi_hba->timer);
2141
2142 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2143 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2144 txid_auto | TXID_AUTO_CT3_MSK);
2145
2146 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2147 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2148
2149 return res;
2150 }
2151
2152 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2153 {
2154 struct hisi_hba *hisi_hba = p;
2155 u32 irq_msk;
2156 int phy_no = 0;
2157 irqreturn_t res = IRQ_HANDLED;
2158
2159 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2160 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2161 while (irq_msk) {
2162 if (irq_msk & 1) {
2163 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2164 CHL_INT0);
2165
2166 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
2167 /* phy up */
2168 if (phy_up_v2_hw(phy_no, hisi_hba)) {
2169 res = IRQ_NONE;
2170 goto end;
2171 }
2172
2173 if (irq_value & CHL_INT0_NOT_RDY_MSK)
2174 /* phy down */
2175 if (phy_down_v2_hw(phy_no, hisi_hba)) {
2176 res = IRQ_NONE;
2177 goto end;
2178 }
2179 }
2180 irq_msk >>= 1;
2181 phy_no++;
2182 }
2183
2184 end:
2185 return res;
2186 }
2187
2188 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2189 {
2190 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2191 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2192 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2193 u32 bcast_status;
2194
2195 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2196 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2197 if (bcast_status & RX_BCAST_CHG_MSK)
2198 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2199 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2200 CHL_INT0_SL_RX_BCST_ACK_MSK);
2201 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2202 }
2203
2204 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2205 {
2206 struct hisi_hba *hisi_hba = p;
2207 struct device *dev = &hisi_hba->pdev->dev;
2208 u32 ent_msk, ent_tmp, irq_msk;
2209 int phy_no = 0;
2210
2211 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2212 ent_tmp = ent_msk;
2213 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2214 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2215
2216 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2217 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2218
2219 while (irq_msk) {
2220 if (irq_msk & (1 << phy_no)) {
2221 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2222 CHL_INT0);
2223 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2224 CHL_INT1);
2225 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2226 CHL_INT2);
2227
2228 if (irq_value1) {
2229 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
2230 CHL_INT1_DMAC_TX_ECC_ERR_MSK))
2231 panic("%s: DMAC RX/TX ecc bad error!\
2232 (0x%x)",
2233 dev_name(dev), irq_value1);
2234
2235 hisi_sas_phy_write32(hisi_hba, phy_no,
2236 CHL_INT1, irq_value1);
2237 }
2238
2239 if (irq_value2)
2240 hisi_sas_phy_write32(hisi_hba, phy_no,
2241 CHL_INT2, irq_value2);
2242
2243
2244 if (irq_value0) {
2245 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2246 phy_bcast_v2_hw(phy_no, hisi_hba);
2247
2248 hisi_sas_phy_write32(hisi_hba, phy_no,
2249 CHL_INT0, irq_value0
2250 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2251 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2252 & (~CHL_INT0_NOT_RDY_MSK));
2253 }
2254 }
2255 irq_msk &= ~(1 << phy_no);
2256 phy_no++;
2257 }
2258
2259 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2260
2261 return IRQ_HANDLED;
2262 }
2263
2264 static void
2265 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2266 {
2267 struct device *dev = &hisi_hba->pdev->dev;
2268 u32 reg_val;
2269
2270 if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF)) {
2271 reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR);
2272 dev_warn(dev, "hgc_dqe_acc1b_intr found: \
2273 Ram address is 0x%08X\n",
2274 (reg_val & HGC_DQE_ECC_1B_ADDR_MSK) >>
2275 HGC_DQE_ECC_1B_ADDR_OFF);
2276 }
2277
2278 if (irq_value & BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF)) {
2279 reg_val = hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR);
2280 dev_warn(dev, "hgc_iost_acc1b_intr found: \
2281 Ram address is 0x%08X\n",
2282 (reg_val & HGC_IOST_ECC_1B_ADDR_MSK) >>
2283 HGC_IOST_ECC_1B_ADDR_OFF);
2284 }
2285
2286 if (irq_value & BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF)) {
2287 reg_val = hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR);
2288 dev_warn(dev, "hgc_itct_acc1b_intr found: \
2289 Ram address is 0x%08X\n",
2290 (reg_val & HGC_ITCT_ECC_1B_ADDR_MSK) >>
2291 HGC_ITCT_ECC_1B_ADDR_OFF);
2292 }
2293
2294 if (irq_value & BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF)) {
2295 reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
2296 dev_warn(dev, "hgc_iostl_acc1b_intr found: \
2297 memory address is 0x%08X\n",
2298 (reg_val & HGC_LM_DFX_STATUS2_IOSTLIST_MSK) >>
2299 HGC_LM_DFX_STATUS2_IOSTLIST_OFF);
2300 }
2301
2302 if (irq_value & BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF)) {
2303 reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
2304 dev_warn(dev, "hgc_itctl_acc1b_intr found: \
2305 memory address is 0x%08X\n",
2306 (reg_val & HGC_LM_DFX_STATUS2_ITCTLIST_MSK) >>
2307 HGC_LM_DFX_STATUS2_ITCTLIST_OFF);
2308 }
2309
2310 if (irq_value & BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF)) {
2311 reg_val = hisi_sas_read32(hisi_hba, HGC_CQE_ECC_ADDR);
2312 dev_warn(dev, "hgc_cqe_acc1b_intr found: \
2313 Ram address is 0x%08X\n",
2314 (reg_val & HGC_CQE_ECC_1B_ADDR_MSK) >>
2315 HGC_CQE_ECC_1B_ADDR_OFF);
2316 }
2317
2318 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF)) {
2319 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
2320 dev_warn(dev, "rxm_mem0_acc1b_intr found: \
2321 memory address is 0x%08X\n",
2322 (reg_val & HGC_RXM_DFX_STATUS14_MEM0_MSK) >>
2323 HGC_RXM_DFX_STATUS14_MEM0_OFF);
2324 }
2325
2326 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF)) {
2327 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
2328 dev_warn(dev, "rxm_mem1_acc1b_intr found: \
2329 memory address is 0x%08X\n",
2330 (reg_val & HGC_RXM_DFX_STATUS14_MEM1_MSK) >>
2331 HGC_RXM_DFX_STATUS14_MEM1_OFF);
2332 }
2333
2334 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF)) {
2335 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
2336 dev_warn(dev, "rxm_mem2_acc1b_intr found: \
2337 memory address is 0x%08X\n",
2338 (reg_val & HGC_RXM_DFX_STATUS14_MEM2_MSK) >>
2339 HGC_RXM_DFX_STATUS14_MEM2_OFF);
2340 }
2341
2342 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF)) {
2343 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS15);
2344 dev_warn(dev, "rxm_mem3_acc1b_intr found: \
2345 memory address is 0x%08X\n",
2346 (reg_val & HGC_RXM_DFX_STATUS15_MEM3_MSK) >>
2347 HGC_RXM_DFX_STATUS15_MEM3_OFF);
2348 }
2349
2350 }
2351
2352 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2353 u32 irq_value)
2354 {
2355 u32 reg_val;
2356 struct device *dev = &hisi_hba->pdev->dev;
2357
2358 if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF)) {
2359 reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR);
2360 panic("%s: hgc_dqe_accbad_intr (0x%x) found: \
2361 Ram address is 0x%08X\n",
2362 dev_name(dev), irq_value,
2363 (reg_val & HGC_DQE_ECC_MB_ADDR_MSK) >>
2364 HGC_DQE_ECC_MB_ADDR_OFF);
2365 }
2366
2367 if (irq_value & BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF)) {
2368 reg_val = hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR);
2369 panic("%s: hgc_iost_accbad_intr (0x%x) found: \
2370 Ram address is 0x%08X\n",
2371 dev_name(dev), irq_value,
2372 (reg_val & HGC_IOST_ECC_MB_ADDR_MSK) >>
2373 HGC_IOST_ECC_MB_ADDR_OFF);
2374 }
2375
2376 if (irq_value & BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF)) {
2377 reg_val = hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR);
2378 panic("%s: hgc_itct_accbad_intr (0x%x) found: \
2379 Ram address is 0x%08X\n",
2380 dev_name(dev), irq_value,
2381 (reg_val & HGC_ITCT_ECC_MB_ADDR_MSK) >>
2382 HGC_ITCT_ECC_MB_ADDR_OFF);
2383 }
2384
2385 if (irq_value & BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF)) {
2386 reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
2387 panic("%s: hgc_iostl_accbad_intr (0x%x) found: \
2388 memory address is 0x%08X\n",
2389 dev_name(dev), irq_value,
2390 (reg_val & HGC_LM_DFX_STATUS2_IOSTLIST_MSK) >>
2391 HGC_LM_DFX_STATUS2_IOSTLIST_OFF);
2392 }
2393
2394 if (irq_value & BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF)) {
2395 reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
2396 panic("%s: hgc_itctl_accbad_intr (0x%x) found: \
2397 memory address is 0x%08X\n",
2398 dev_name(dev), irq_value,
2399 (reg_val & HGC_LM_DFX_STATUS2_ITCTLIST_MSK) >>
2400 HGC_LM_DFX_STATUS2_ITCTLIST_OFF);
2401 }
2402
2403 if (irq_value & BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF)) {
2404 reg_val = hisi_sas_read32(hisi_hba, HGC_CQE_ECC_ADDR);
2405 panic("%s: hgc_cqe_accbad_intr (0x%x) found: \
2406 Ram address is 0x%08X\n",
2407 dev_name(dev), irq_value,
2408 (reg_val & HGC_CQE_ECC_MB_ADDR_MSK) >>
2409 HGC_CQE_ECC_MB_ADDR_OFF);
2410 }
2411
2412 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF)) {
2413 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
2414 panic("%s: rxm_mem0_accbad_intr (0x%x) found: \
2415 memory address is 0x%08X\n",
2416 dev_name(dev), irq_value,
2417 (reg_val & HGC_RXM_DFX_STATUS14_MEM0_MSK) >>
2418 HGC_RXM_DFX_STATUS14_MEM0_OFF);
2419 }
2420
2421 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF)) {
2422 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
2423 panic("%s: rxm_mem1_accbad_intr (0x%x) found: \
2424 memory address is 0x%08X\n",
2425 dev_name(dev), irq_value,
2426 (reg_val & HGC_RXM_DFX_STATUS14_MEM1_MSK) >>
2427 HGC_RXM_DFX_STATUS14_MEM1_OFF);
2428 }
2429
2430 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF)) {
2431 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
2432 panic("%s: rxm_mem2_accbad_intr (0x%x) found: \
2433 memory address is 0x%08X\n",
2434 dev_name(dev), irq_value,
2435 (reg_val & HGC_RXM_DFX_STATUS14_MEM2_MSK) >>
2436 HGC_RXM_DFX_STATUS14_MEM2_OFF);
2437 }
2438
2439 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF)) {
2440 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS15);
2441 panic("%s: rxm_mem3_accbad_intr (0x%x) found: \
2442 memory address is 0x%08X\n",
2443 dev_name(dev), irq_value,
2444 (reg_val & HGC_RXM_DFX_STATUS15_MEM3_MSK) >>
2445 HGC_RXM_DFX_STATUS15_MEM3_OFF);
2446 }
2447
2448 }
2449
2450 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
2451 {
2452 struct hisi_hba *hisi_hba = p;
2453 u32 irq_value, irq_msk;
2454
2455 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2456 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
2457
2458 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2459 if (irq_value) {
2460 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2461 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2462 }
2463
2464 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2465 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2466
2467 return IRQ_HANDLED;
2468 }
2469
2470 #define AXI_ERR_NR 8
2471 static const char axi_err_info[AXI_ERR_NR][32] = {
2472 "IOST_AXI_W_ERR",
2473 "IOST_AXI_R_ERR",
2474 "ITCT_AXI_W_ERR",
2475 "ITCT_AXI_R_ERR",
2476 "SATA_AXI_W_ERR",
2477 "SATA_AXI_R_ERR",
2478 "DQE_AXI_R_ERR",
2479 "CQE_AXI_W_ERR"
2480 };
2481
2482 #define FIFO_ERR_NR 5
2483 static const char fifo_err_info[FIFO_ERR_NR][32] = {
2484 "CQE_WINFO_FIFO",
2485 "CQE_MSG_FIFIO",
2486 "GETDQE_FIFO",
2487 "CMDP_FIFO",
2488 "AWTCTRL_FIFO"
2489 };
2490
2491 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
2492 {
2493 struct hisi_hba *hisi_hba = p;
2494 u32 irq_value, irq_msk, err_value;
2495 struct device *dev = &hisi_hba->pdev->dev;
2496
2497 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2498 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
2499
2500 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
2501 if (irq_value) {
2502 if (irq_value & BIT(ENT_INT_SRC3_WP_DEPTH_OFF)) {
2503 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
2504 1 << ENT_INT_SRC3_WP_DEPTH_OFF);
2505 panic("%s: write pointer and depth error (0x%x) \
2506 found!\n",
2507 dev_name(dev), irq_value);
2508 }
2509
2510 if (irq_value & BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF)) {
2511 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
2512 1 <<
2513 ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF);
2514 panic("%s: iptt no match slot error (0x%x) found!\n",
2515 dev_name(dev), irq_value);
2516 }
2517
2518 if (irq_value & BIT(ENT_INT_SRC3_RP_DEPTH_OFF))
2519 panic("%s: read pointer and depth error (0x%x) \
2520 found!\n",
2521 dev_name(dev), irq_value);
2522
2523 if (irq_value & BIT(ENT_INT_SRC3_AXI_OFF)) {
2524 int i;
2525
2526 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
2527 1 << ENT_INT_SRC3_AXI_OFF);
2528 err_value = hisi_sas_read32(hisi_hba,
2529 HGC_AXI_FIFO_ERR_INFO);
2530
2531 for (i = 0; i < AXI_ERR_NR; i++) {
2532 if (err_value & BIT(i))
2533 panic("%s: %s (0x%x) found!\n",
2534 dev_name(dev),
2535 axi_err_info[i], irq_value);
2536 }
2537 }
2538
2539 if (irq_value & BIT(ENT_INT_SRC3_FIFO_OFF)) {
2540 int i;
2541
2542 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
2543 1 << ENT_INT_SRC3_FIFO_OFF);
2544 err_value = hisi_sas_read32(hisi_hba,
2545 HGC_AXI_FIFO_ERR_INFO);
2546
2547 for (i = 0; i < FIFO_ERR_NR; i++) {
2548 if (err_value & BIT(AXI_ERR_NR + i))
2549 panic("%s: %s (0x%x) found!\n",
2550 dev_name(dev),
2551 fifo_err_info[i], irq_value);
2552 }
2553
2554 }
2555
2556 if (irq_value & BIT(ENT_INT_SRC3_LM_OFF)) {
2557 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
2558 1 << ENT_INT_SRC3_LM_OFF);
2559 panic("%s: LM add/fetch list error (0x%x) found!\n",
2560 dev_name(dev), irq_value);
2561 }
2562
2563 if (irq_value & BIT(ENT_INT_SRC3_ABT_OFF)) {
2564 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
2565 1 << ENT_INT_SRC3_ABT_OFF);
2566 panic("%s: SAS_HGC_ABT fetch LM list error (0x%x) found!\n",
2567 dev_name(dev), irq_value);
2568 }
2569 }
2570
2571 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
2572
2573 return IRQ_HANDLED;
2574 }
2575
2576 static void cq_tasklet_v2_hw(unsigned long val)
2577 {
2578 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
2579 struct hisi_hba *hisi_hba = cq->hisi_hba;
2580 struct hisi_sas_slot *slot;
2581 struct hisi_sas_itct *itct;
2582 struct hisi_sas_complete_v2_hdr *complete_queue;
2583 u32 rd_point = cq->rd_point, wr_point, dev_id;
2584 int queue = cq->id;
2585
2586 complete_queue = hisi_hba->complete_hdr[queue];
2587
2588 spin_lock(&hisi_hba->lock);
2589 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2590 (0x14 * queue));
2591
2592 while (rd_point != wr_point) {
2593 struct hisi_sas_complete_v2_hdr *complete_hdr;
2594 int iptt;
2595
2596 complete_hdr = &complete_queue[rd_point];
2597
2598 /* Check for NCQ completion */
2599 if (complete_hdr->act) {
2600 u32 act_tmp = complete_hdr->act;
2601 int ncq_tag_count = ffs(act_tmp);
2602
2603 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
2604 CMPLT_HDR_DEV_ID_OFF;
2605 itct = &hisi_hba->itct[dev_id];
2606
2607 /* The NCQ tags are held in the itct header */
2608 while (ncq_tag_count) {
2609 __le64 *ncq_tag = &itct->qw4_15[0];
2610
2611 ncq_tag_count -= 1;
2612 iptt = (ncq_tag[ncq_tag_count / 5]
2613 >> (ncq_tag_count % 5) * 12) & 0xfff;
2614
2615 slot = &hisi_hba->slot_info[iptt];
2616 slot->cmplt_queue_slot = rd_point;
2617 slot->cmplt_queue = queue;
2618 slot_complete_v2_hw(hisi_hba, slot, 0);
2619
2620 act_tmp &= ~(1 << ncq_tag_count);
2621 ncq_tag_count = ffs(act_tmp);
2622 }
2623 } else {
2624 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
2625 slot = &hisi_hba->slot_info[iptt];
2626 slot->cmplt_queue_slot = rd_point;
2627 slot->cmplt_queue = queue;
2628 slot_complete_v2_hw(hisi_hba, slot, 0);
2629 }
2630
2631 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2632 rd_point = 0;
2633 }
2634
2635 /* update rd_point */
2636 cq->rd_point = rd_point;
2637 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2638 spin_unlock(&hisi_hba->lock);
2639 }
2640
2641 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
2642 {
2643 struct hisi_sas_cq *cq = p;
2644 struct hisi_hba *hisi_hba = cq->hisi_hba;
2645 int queue = cq->id;
2646
2647 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
2648
2649 tasklet_schedule(&cq->tasklet);
2650
2651 return IRQ_HANDLED;
2652 }
2653
2654 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
2655 {
2656 struct hisi_sas_phy *phy = p;
2657 struct hisi_hba *hisi_hba = phy->hisi_hba;
2658 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2659 struct device *dev = &hisi_hba->pdev->dev;
2660 struct hisi_sas_initial_fis *initial_fis;
2661 struct dev_to_host_fis *fis;
2662 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
2663 irqreturn_t res = IRQ_HANDLED;
2664 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
2665 int phy_no, offset;
2666
2667 phy_no = sas_phy->id;
2668 initial_fis = &hisi_hba->initial_fis[phy_no];
2669 fis = &initial_fis->fis;
2670
2671 offset = 4 * (phy_no / 4);
2672 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
2673 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
2674 ent_msk | 1 << ((phy_no % 4) * 8));
2675
2676 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
2677 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
2678 (phy_no % 4)));
2679 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
2680 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
2681 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
2682 res = IRQ_NONE;
2683 goto end;
2684 }
2685
2686 /* check ERR bit of Status Register */
2687 if (fis->status & ATA_ERR) {
2688 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
2689 fis->status);
2690 disable_phy_v2_hw(hisi_hba, phy_no);
2691 enable_phy_v2_hw(hisi_hba, phy_no);
2692 res = IRQ_NONE;
2693 goto end;
2694 }
2695
2696 if (unlikely(phy_no == 8)) {
2697 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2698
2699 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2700 PORT_STATE_PHY8_PORT_NUM_OFF;
2701 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2702 PORT_STATE_PHY8_CONN_RATE_OFF;
2703 } else {
2704 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2705 port_id = (port_id >> (4 * phy_no)) & 0xf;
2706 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2707 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2708 }
2709
2710 if (port_id == 0xf) {
2711 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
2712 res = IRQ_NONE;
2713 goto end;
2714 }
2715
2716 sas_phy->linkrate = link_rate;
2717 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2718 HARD_PHY_LINKRATE);
2719 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2720 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2721
2722 sas_phy->oob_mode = SATA_OOB_MODE;
2723 /* Make up some unique SAS address */
2724 attached_sas_addr[0] = 0x50;
2725 attached_sas_addr[7] = phy_no;
2726 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
2727 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
2728 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2729 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2730 phy->port_id = port_id;
2731 phy->phy_type |= PORT_TYPE_SATA;
2732 phy->phy_attached = 1;
2733 phy->identify.device_type = SAS_SATA_DEV;
2734 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2735 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2736 queue_work(hisi_hba->wq, &phy->phyup_ws);
2737
2738 end:
2739 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
2740 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
2741
2742 return res;
2743 }
2744
2745 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
2746 int_phy_updown_v2_hw,
2747 int_chnl_int_v2_hw,
2748 };
2749
2750 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
2751 fatal_ecc_int_v2_hw,
2752 fatal_axi_int_v2_hw
2753 };
2754
2755 /**
2756 * There is a limitation in the hip06 chipset that we need
2757 * to map in all mbigen interrupts, even if they are not used.
2758 */
2759 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
2760 {
2761 struct platform_device *pdev = hisi_hba->pdev;
2762 struct device *dev = &pdev->dev;
2763 int i, irq, rc, irq_map[128];
2764
2765
2766 for (i = 0; i < 128; i++)
2767 irq_map[i] = platform_get_irq(pdev, i);
2768
2769 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
2770 int idx = i;
2771
2772 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */
2773 if (!irq) {
2774 dev_err(dev, "irq init: fail map phy interrupt %d\n",
2775 idx);
2776 return -ENOENT;
2777 }
2778
2779 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
2780 DRV_NAME " phy", hisi_hba);
2781 if (rc) {
2782 dev_err(dev, "irq init: could not request "
2783 "phy interrupt %d, rc=%d\n",
2784 irq, rc);
2785 return -ENOENT;
2786 }
2787 }
2788
2789 for (i = 0; i < hisi_hba->n_phy; i++) {
2790 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
2791 int idx = i + 72; /* First SATA interrupt is irq72 */
2792
2793 irq = irq_map[idx];
2794 if (!irq) {
2795 dev_err(dev, "irq init: fail map phy interrupt %d\n",
2796 idx);
2797 return -ENOENT;
2798 }
2799
2800 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
2801 DRV_NAME " sata", phy);
2802 if (rc) {
2803 dev_err(dev, "irq init: could not request "
2804 "sata interrupt %d, rc=%d\n",
2805 irq, rc);
2806 return -ENOENT;
2807 }
2808 }
2809
2810 for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++) {
2811 int idx = i;
2812
2813 irq = irq_map[idx + 81];
2814 if (!irq) {
2815 dev_err(dev, "irq init: fail map fatal interrupt %d\n",
2816 idx);
2817 return -ENOENT;
2818 }
2819
2820 rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0,
2821 DRV_NAME " fatal", hisi_hba);
2822 if (rc) {
2823 dev_err(dev,
2824 "irq init: could not request fatal interrupt %d, rc=%d\n",
2825 irq, rc);
2826 return -ENOENT;
2827 }
2828 }
2829
2830 for (i = 0; i < hisi_hba->queue_count; i++) {
2831 int idx = i + 96; /* First cq interrupt is irq96 */
2832 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2833 struct tasklet_struct *t = &cq->tasklet;
2834
2835 irq = irq_map[idx];
2836 if (!irq) {
2837 dev_err(dev,
2838 "irq init: could not map cq interrupt %d\n",
2839 idx);
2840 return -ENOENT;
2841 }
2842 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
2843 DRV_NAME " cq", &hisi_hba->cq[i]);
2844 if (rc) {
2845 dev_err(dev,
2846 "irq init: could not request cq interrupt %d, rc=%d\n",
2847 irq, rc);
2848 return -ENOENT;
2849 }
2850 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
2851 }
2852
2853 return 0;
2854 }
2855
2856 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
2857 {
2858 int rc;
2859
2860 rc = hw_init_v2_hw(hisi_hba);
2861 if (rc)
2862 return rc;
2863
2864 rc = interrupt_init_v2_hw(hisi_hba);
2865 if (rc)
2866 return rc;
2867
2868 return 0;
2869 }
2870
2871 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
2872 {
2873 struct platform_device *pdev = hisi_hba->pdev;
2874 int i;
2875
2876 for (i = 0; i < hisi_hba->queue_count; i++)
2877 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
2878
2879 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
2880 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
2881 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
2882 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2883
2884 for (i = 0; i < hisi_hba->n_phy; i++) {
2885 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
2886 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
2887 }
2888
2889 for (i = 0; i < 128; i++)
2890 synchronize_irq(platform_get_irq(pdev, i));
2891 }
2892
2893 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
2894 {
2895 struct device *dev = &hisi_hba->pdev->dev;
2896 u32 old_state, state;
2897 int rc, cnt;
2898 int phy_no;
2899
2900 old_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2901
2902 interrupt_disable_v2_hw(hisi_hba);
2903 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2904
2905 stop_phys_v2_hw(hisi_hba);
2906
2907 mdelay(10);
2908
2909 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
2910
2911 /* wait until bus idle */
2912 cnt = 0;
2913 while (1) {
2914 u32 status = hisi_sas_read32_relaxed(hisi_hba,
2915 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
2916
2917 if (status == 0x3)
2918 break;
2919
2920 udelay(10);
2921 if (cnt++ > 10) {
2922 dev_info(dev, "wait axi bus state to idle timeout!\n");
2923 return -1;
2924 }
2925 }
2926
2927 hisi_sas_init_mem(hisi_hba);
2928
2929 rc = hw_init_v2_hw(hisi_hba);
2930 if (rc)
2931 return rc;
2932
2933 /* Re-enable the PHYs */
2934 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
2935 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2936 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2937
2938 if (sas_phy->enabled)
2939 start_phy_v2_hw(hisi_hba, phy_no);
2940 }
2941
2942 /* Wait for the PHYs to come up and read the PHY state */
2943 msleep(1000);
2944
2945 state = hisi_sas_read32(hisi_hba, PHY_STATE);
2946
2947 hisi_sas_rescan_topology(hisi_hba, old_state, state);
2948
2949 return 0;
2950 }
2951
2952 static const struct hisi_sas_hw hisi_sas_v2_hw = {
2953 .hw_init = hisi_sas_v2_init,
2954 .setup_itct = setup_itct_v2_hw,
2955 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
2956 .alloc_dev = alloc_dev_quirk_v2_hw,
2957 .sl_notify = sl_notify_v2_hw,
2958 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
2959 .free_device = free_device_v2_hw,
2960 .prep_smp = prep_smp_v2_hw,
2961 .prep_ssp = prep_ssp_v2_hw,
2962 .prep_stp = prep_ata_v2_hw,
2963 .prep_abort = prep_abort_v2_hw,
2964 .get_free_slot = get_free_slot_v2_hw,
2965 .start_delivery = start_delivery_v2_hw,
2966 .slot_complete = slot_complete_v2_hw,
2967 .phys_init = phys_init_v2_hw,
2968 .phy_enable = enable_phy_v2_hw,
2969 .phy_disable = disable_phy_v2_hw,
2970 .phy_hard_reset = phy_hard_reset_v2_hw,
2971 .phy_set_linkrate = phy_set_linkrate_v2_hw,
2972 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
2973 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
2974 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
2975 .soft_reset = soft_reset_v2_hw,
2976 };
2977
2978 static int hisi_sas_v2_probe(struct platform_device *pdev)
2979 {
2980 /*
2981 * Check if we should defer the probe before we probe the
2982 * upper layer, as it's hard to defer later on.
2983 */
2984 int ret = platform_get_irq(pdev, 0);
2985
2986 if (ret < 0) {
2987 if (ret != -EPROBE_DEFER)
2988 dev_err(&pdev->dev, "cannot obtain irq\n");
2989 return ret;
2990 }
2991
2992 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
2993 }
2994
2995 static int hisi_sas_v2_remove(struct platform_device *pdev)
2996 {
2997 struct sas_ha_struct *sha = platform_get_drvdata(pdev);
2998 struct hisi_hba *hisi_hba = sha->lldd_ha;
2999
3000 if (timer_pending(&hisi_hba->timer))
3001 del_timer(&hisi_hba->timer);
3002
3003 return hisi_sas_remove(pdev);
3004 }
3005
3006 static const struct of_device_id sas_v2_of_match[] = {
3007 { .compatible = "hisilicon,hip06-sas-v2",},
3008 { .compatible = "hisilicon,hip07-sas-v2",},
3009 {},
3010 };
3011 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3012
3013 static const struct acpi_device_id sas_v2_acpi_match[] = {
3014 { "HISI0162", 0 },
3015 { }
3016 };
3017
3018 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3019
3020 static struct platform_driver hisi_sas_v2_driver = {
3021 .probe = hisi_sas_v2_probe,
3022 .remove = hisi_sas_v2_remove,
3023 .driver = {
3024 .name = DRV_NAME,
3025 .of_match_table = sas_v2_of_match,
3026 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3027 },
3028 };
3029
3030 module_platform_driver(hisi_sas_v2_driver);
3031
3032 MODULE_LICENSE("GPL");
3033 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3034 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3035 MODULE_ALIAS("platform:" DRV_NAME);
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