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[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
1 /*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12 #include "hisi_sas.h"
13 #define DRV_NAME "hisi_sas_v2_hw"
14
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
34 #define ITCT_CLR 0x44
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
148 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
149 #define DLVRY_Q_0_DEPTH 0x268
150 #define DLVRY_Q_0_WR_PTR 0x26c
151 #define DLVRY_Q_0_RD_PTR 0x270
152 #define HYPER_STREAM_ID_EN_CFG 0xc80
153 #define OQ0_INT_SRC_MSK 0xc90
154 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
155 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
156 #define COMPL_Q_0_DEPTH 0x4e8
157 #define COMPL_Q_0_WR_PTR 0x4ec
158 #define COMPL_Q_0_RD_PTR 0x4f0
159 #define HGC_RXM_DFX_STATUS14 0xae8
160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
162 HGC_RXM_DFX_STATUS14_MEM0_OFF)
163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM1_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM2_OFF)
169 #define HGC_RXM_DFX_STATUS15 0xaec
170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
172 HGC_RXM_DFX_STATUS15_MEM3_OFF)
173 /* phy registers need init */
174 #define PORT_BASE (0x2000)
175
176 #define PHY_CFG (PORT_BASE + 0x0)
177 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PHY_CFG_ENA_OFF 0
179 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
180 #define PHY_CFG_DC_OPT_OFF 2
181 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
182 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
183 #define PROG_PHY_LINK_RATE_MAX_OFF 0
184 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
185 #define PHY_CTRL (PORT_BASE + 0x14)
186 #define PHY_CTRL_RESET_OFF 0
187 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
188 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
189 #define SL_CFG (PORT_BASE + 0x84)
190 #define PHY_PCN (PORT_BASE + 0x44)
191 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
192 #define SL_CONTROL (PORT_BASE + 0x94)
193 #define SL_CONTROL_NOTIFY_EN_OFF 0
194 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
195 #define SL_CONTROL_CTA_OFF 17
196 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
197 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
198 #define RX_BCAST_CHG_OFF 1
199 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
200 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
201 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
202 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
203 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
204 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
205 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
206 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
207 #define TXID_AUTO (PORT_BASE + 0xb8)
208 #define TXID_AUTO_CT3_OFF 1
209 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
210 #define TXID_AUTO_CTB_OFF 11
211 #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
212 #define TX_HARDRST_OFF 2
213 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
214 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
215 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
216 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
217 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
218 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
219 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
220 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
221 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
222 #define CON_CONTROL (PORT_BASE + 0x118)
223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
225 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
226 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
227 #define CHL_INT0 (PORT_BASE + 0x1b4)
228 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
229 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
230 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
231 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
232 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
233 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
234 #define CHL_INT0_NOT_RDY_OFF 4
235 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
236 #define CHL_INT0_PHY_RDY_OFF 5
237 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
238 #define CHL_INT1 (PORT_BASE + 0x1b8)
239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
243 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
244 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
245 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
246 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
247 #define CHL_INT2 (PORT_BASE + 0x1bc)
248 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
249 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
250 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
251 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
252 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
253 #define DMA_TX_DFX0 (PORT_BASE + 0x200)
254 #define DMA_TX_DFX1 (PORT_BASE + 0x204)
255 #define DMA_TX_DFX1_IPTT_OFF 0
256 #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
257 #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
258 #define PORT_DFX0 (PORT_BASE + 0x258)
259 #define LINK_DFX2 (PORT_BASE + 0X264)
260 #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
261 #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
262 #define LINK_DFX2_SEND_HOLD_STS_OFF 10
263 #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
264 #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
265 #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
266 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
267 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
268 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
269 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
270 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
271 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
272 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
273 #define DMA_TX_STATUS_BUSY_OFF 0
274 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
275 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
276 #define DMA_RX_STATUS_BUSY_OFF 0
277 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
278
279 #define AXI_CFG (0x5100)
280 #define AM_CFG_MAX_TRANS (0x5010)
281 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
282
283 #define AXI_MASTER_CFG_BASE (0x5000)
284 #define AM_CTRL_GLOBAL (0x0)
285 #define AM_CURR_TRANS_RETURN (0x150)
286
287 /* HW dma structures */
288 /* Delivery queue header */
289 /* dw0 */
290 #define CMD_HDR_ABORT_FLAG_OFF 0
291 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
292 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
293 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
294 #define CMD_HDR_RESP_REPORT_OFF 5
295 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
296 #define CMD_HDR_TLR_CTRL_OFF 6
297 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
298 #define CMD_HDR_PORT_OFF 18
299 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
300 #define CMD_HDR_PRIORITY_OFF 27
301 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
302 #define CMD_HDR_CMD_OFF 29
303 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
304 /* dw1 */
305 #define CMD_HDR_DIR_OFF 5
306 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
307 #define CMD_HDR_RESET_OFF 7
308 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
309 #define CMD_HDR_VDTL_OFF 10
310 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
311 #define CMD_HDR_FRAME_TYPE_OFF 11
312 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
313 #define CMD_HDR_DEV_ID_OFF 16
314 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
315 /* dw2 */
316 #define CMD_HDR_CFL_OFF 0
317 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
318 #define CMD_HDR_NCQ_TAG_OFF 10
319 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
320 #define CMD_HDR_MRFL_OFF 15
321 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
322 #define CMD_HDR_SG_MOD_OFF 24
323 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
324 #define CMD_HDR_FIRST_BURST_OFF 26
325 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
326 /* dw3 */
327 #define CMD_HDR_IPTT_OFF 0
328 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
329 /* dw6 */
330 #define CMD_HDR_DIF_SGL_LEN_OFF 0
331 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
332 #define CMD_HDR_DATA_SGL_LEN_OFF 16
333 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
334 #define CMD_HDR_ABORT_IPTT_OFF 16
335 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
336
337 /* Completion header */
338 /* dw0 */
339 #define CMPLT_HDR_ERR_PHASE_OFF 2
340 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
341 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
342 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
343 #define CMPLT_HDR_ERX_OFF 12
344 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
345 #define CMPLT_HDR_ABORT_STAT_OFF 13
346 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
347 /* abort_stat */
348 #define STAT_IO_NOT_VALID 0x1
349 #define STAT_IO_NO_DEVICE 0x2
350 #define STAT_IO_COMPLETE 0x3
351 #define STAT_IO_ABORTED 0x4
352 /* dw1 */
353 #define CMPLT_HDR_IPTT_OFF 0
354 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
355 #define CMPLT_HDR_DEV_ID_OFF 16
356 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
357
358 /* ITCT header */
359 /* qw0 */
360 #define ITCT_HDR_DEV_TYPE_OFF 0
361 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
362 #define ITCT_HDR_VALID_OFF 2
363 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
364 #define ITCT_HDR_MCR_OFF 5
365 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
366 #define ITCT_HDR_VLN_OFF 9
367 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
368 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
369 #define ITCT_HDR_SMP_TIMEOUT_8US 1
370 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
371 250) /* 2ms */
372 #define ITCT_HDR_AWT_CONTINUE_OFF 25
373 #define ITCT_HDR_PORT_ID_OFF 28
374 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
375 /* qw2 */
376 #define ITCT_HDR_INLT_OFF 0
377 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
378 #define ITCT_HDR_BITLT_OFF 16
379 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
380 #define ITCT_HDR_MCTLT_OFF 32
381 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
382 #define ITCT_HDR_RTOLT_OFF 48
383 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
384
385 #define HISI_SAS_FATAL_INT_NR 2
386
387 struct hisi_sas_complete_v2_hdr {
388 __le32 dw0;
389 __le32 dw1;
390 __le32 act;
391 __le32 dw3;
392 };
393
394 struct hisi_sas_err_record_v2 {
395 /* dw0 */
396 __le32 trans_tx_fail_type;
397
398 /* dw1 */
399 __le32 trans_rx_fail_type;
400
401 /* dw2 */
402 __le16 dma_tx_err_type;
403 __le16 sipc_rx_err_type;
404
405 /* dw3 */
406 __le32 dma_rx_err_type;
407 };
408
409 struct signal_attenuation_s {
410 u32 de_emphasis;
411 u32 preshoot;
412 u32 boost;
413 };
414
415 struct sig_atten_lu_s {
416 const struct signal_attenuation_s *att;
417 u32 sas_phy_ctrl;
418 };
419
420 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
421 {
422 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
423 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
424 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
425 .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
426 .reg = HGC_DQE_ECC_ADDR,
427 },
428 {
429 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
430 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
431 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
432 .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
433 .reg = HGC_IOST_ECC_ADDR,
434 },
435 {
436 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
437 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
438 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
439 .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
440 .reg = HGC_ITCT_ECC_ADDR,
441 },
442 {
443 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
444 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
445 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
446 .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
447 .reg = HGC_LM_DFX_STATUS2,
448 },
449 {
450 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
451 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
452 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
453 .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
454 .reg = HGC_LM_DFX_STATUS2,
455 },
456 {
457 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
458 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
459 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
460 .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
461 .reg = HGC_CQE_ECC_ADDR,
462 },
463 {
464 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
465 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
466 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
467 .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
468 .reg = HGC_RXM_DFX_STATUS14,
469 },
470 {
471 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
472 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
473 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
474 .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
475 .reg = HGC_RXM_DFX_STATUS14,
476 },
477 {
478 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
479 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
480 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
481 .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
482 .reg = HGC_RXM_DFX_STATUS14,
483 },
484 {
485 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
486 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
487 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
488 .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
489 .reg = HGC_RXM_DFX_STATUS15,
490 },
491 };
492
493 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
494 {
495 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
496 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
497 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
498 .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
499 .reg = HGC_DQE_ECC_ADDR,
500 },
501 {
502 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
503 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
504 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
505 .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
506 .reg = HGC_IOST_ECC_ADDR,
507 },
508 {
509 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
510 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
511 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
512 .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
513 .reg = HGC_ITCT_ECC_ADDR,
514 },
515 {
516 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
517 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
518 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
519 .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
520 .reg = HGC_LM_DFX_STATUS2,
521 },
522 {
523 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
524 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
525 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
526 .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
527 .reg = HGC_LM_DFX_STATUS2,
528 },
529 {
530 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
531 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
532 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
533 .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
534 .reg = HGC_CQE_ECC_ADDR,
535 },
536 {
537 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
538 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
539 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
540 .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
541 .reg = HGC_RXM_DFX_STATUS14,
542 },
543 {
544 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
545 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
546 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
547 .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
548 .reg = HGC_RXM_DFX_STATUS14,
549 },
550 {
551 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
552 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
553 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
554 .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
555 .reg = HGC_RXM_DFX_STATUS14,
556 },
557 {
558 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
559 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
560 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
561 .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
562 .reg = HGC_RXM_DFX_STATUS15,
563 },
564 };
565
566 enum {
567 HISI_SAS_PHY_PHY_UPDOWN,
568 HISI_SAS_PHY_CHNL_INT,
569 HISI_SAS_PHY_INT_NR
570 };
571
572 enum {
573 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
574 TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
575 DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
576 SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
577 DMA_RX_ERR_BASE = 0x60, /* dw3 */
578
579 /* trans tx*/
580 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
581 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
582 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
583 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
584 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
585 RESERVED0, /* 0x5 */
586 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
587 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
588 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
589 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
590 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
591 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
592 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
593 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
594 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
595 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
596 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
597 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
598 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
599 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
600 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
601 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
602 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
603 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
604 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
605 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
606 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
607 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
608 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
609 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
610 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
611 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
612 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
613 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
614 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
615
616 /* trans rx */
617 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
618 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
619 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
620 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
621 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
622 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
623 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
624 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
625 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
626 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
627 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
628 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
629 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
630 RESERVED1, /* 0x2b */
631 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
632 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
633 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
634 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
635 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
636 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
637 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
638 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
639 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
640 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
641 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
642 RESERVED2, /* 0x34 */
643 RESERVED3, /* 0x35 */
644 RESERVED4, /* 0x36 */
645 RESERVED5, /* 0x37 */
646 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
647 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
648 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
649 RESERVED6, /* 0x3b */
650 RESERVED7, /* 0x3c */
651 RESERVED8, /* 0x3d */
652 RESERVED9, /* 0x3e */
653 TRANS_RX_R_ERR, /* 0x3f */
654
655 /* dma tx */
656 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
657 DMA_TX_DIF_APP_ERR, /* 0x41 */
658 DMA_TX_DIF_RPP_ERR, /* 0x42 */
659 DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
660 DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
661 DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
662 DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
663 DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
664 DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
665 DMA_TX_RAM_ECC_ERR, /* 0x49 */
666 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
667 DMA_TX_MAX_ERR_CODE,
668
669 /* sipc rx */
670 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
671 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
672 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
673 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
674 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
675 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
676 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
677 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
678 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
679 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
680 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
681 SIPC_RX_MAX_ERR_CODE,
682
683 /* dma rx */
684 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
685 DMA_RX_DIF_APP_ERR, /* 0x61 */
686 DMA_RX_DIF_RPP_ERR, /* 0x62 */
687 DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
688 DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
689 DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
690 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
691 DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
692 RESERVED10, /* 0x68 */
693 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
694 DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
695 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
696 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
697 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
698 DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
699 DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
700 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
701 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
702 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
703 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
704 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
705 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
706 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
707 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
708 DMA_RX_RAM_ECC_ERR, /* 0x78 */
709 DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
710 DMA_RX_MAX_ERR_CODE,
711 };
712
713 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
714 #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
715
716 #define DIR_NO_DATA 0
717 #define DIR_TO_INI 1
718 #define DIR_TO_DEVICE 2
719 #define DIR_RESERVED 3
720
721 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
722 err_phase == 0x4 || err_phase == 0x8 ||\
723 err_phase == 0x6 || err_phase == 0xa)
724 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
725 err_phase == 0x20 || err_phase == 0x40)
726
727 static void link_timeout_disable_link(struct timer_list *t);
728
729 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
730 {
731 void __iomem *regs = hisi_hba->regs + off;
732
733 return readl(regs);
734 }
735
736 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
737 {
738 void __iomem *regs = hisi_hba->regs + off;
739
740 return readl_relaxed(regs);
741 }
742
743 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
744 {
745 void __iomem *regs = hisi_hba->regs + off;
746
747 writel(val, regs);
748 }
749
750 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
751 u32 off, u32 val)
752 {
753 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
754
755 writel(val, regs);
756 }
757
758 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
759 int phy_no, u32 off)
760 {
761 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
762
763 return readl(regs);
764 }
765
766 /* This function needs to be protected from pre-emption. */
767 static int
768 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
769 struct domain_device *device)
770 {
771 int sata_dev = dev_is_sata(device);
772 void *bitmap = hisi_hba->slot_index_tags;
773 struct hisi_sas_device *sas_dev = device->lldd_dev;
774 int sata_idx = sas_dev->sata_idx;
775 int start, end;
776
777 if (!sata_dev) {
778 /*
779 * STP link SoC bug workaround: index starts from 1.
780 * additionally, we can only allocate odd IPTT(1~4095)
781 * for SAS/SMP device.
782 */
783 start = 1;
784 end = hisi_hba->slot_index_count;
785 } else {
786 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
787 return -EINVAL;
788
789 /*
790 * For SATA device: allocate even IPTT in this interval
791 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
792 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
793 * SoC bug workaround. So we ignore the first 32 even IPTTs.
794 */
795 start = 64 * (sata_idx + 1);
796 end = 64 * (sata_idx + 2);
797 }
798
799 while (1) {
800 start = find_next_zero_bit(bitmap,
801 hisi_hba->slot_index_count, start);
802 if (start >= end)
803 return -SAS_QUEUE_FULL;
804 /*
805 * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
806 */
807 if (sata_dev ^ (start & 1))
808 break;
809 start++;
810 }
811
812 set_bit(start, bitmap);
813 *slot_idx = start;
814 return 0;
815 }
816
817 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
818 {
819 unsigned int index;
820 struct device *dev = hisi_hba->dev;
821 void *bitmap = hisi_hba->sata_dev_bitmap;
822
823 index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
824 if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
825 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
826 return false;
827 }
828
829 set_bit(index, bitmap);
830 *idx = index;
831 return true;
832 }
833
834
835 static struct
836 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
837 {
838 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
839 struct hisi_sas_device *sas_dev = NULL;
840 int i, sata_dev = dev_is_sata(device);
841 int sata_idx = -1;
842 unsigned long flags;
843
844 spin_lock_irqsave(&hisi_hba->lock, flags);
845
846 if (sata_dev)
847 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
848 goto out;
849
850 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
851 /*
852 * SATA device id bit0 should be 0
853 */
854 if (sata_dev && (i & 1))
855 continue;
856 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
857 int queue = i % hisi_hba->queue_count;
858 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
859
860 hisi_hba->devices[i].device_id = i;
861 sas_dev = &hisi_hba->devices[i];
862 sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
863 sas_dev->dev_type = device->dev_type;
864 sas_dev->hisi_hba = hisi_hba;
865 sas_dev->sas_device = device;
866 sas_dev->sata_idx = sata_idx;
867 sas_dev->dq = dq;
868 INIT_LIST_HEAD(&hisi_hba->devices[i].list);
869 break;
870 }
871 }
872
873 out:
874 spin_unlock_irqrestore(&hisi_hba->lock, flags);
875
876 return sas_dev;
877 }
878
879 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
880 {
881 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
882
883 cfg &= ~PHY_CFG_DC_OPT_MSK;
884 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
885 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
886 }
887
888 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
889 {
890 struct sas_identify_frame identify_frame;
891 u32 *identify_buffer;
892
893 memset(&identify_frame, 0, sizeof(identify_frame));
894 identify_frame.dev_type = SAS_END_DEVICE;
895 identify_frame.frame_type = 0;
896 identify_frame._un1 = 1;
897 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
898 identify_frame.target_bits = SAS_PROTOCOL_NONE;
899 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
900 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
901 identify_frame.phy_id = phy_no;
902 identify_buffer = (u32 *)(&identify_frame);
903
904 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
905 __swab32(identify_buffer[0]));
906 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
907 __swab32(identify_buffer[1]));
908 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
909 __swab32(identify_buffer[2]));
910 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
911 __swab32(identify_buffer[3]));
912 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
913 __swab32(identify_buffer[4]));
914 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
915 __swab32(identify_buffer[5]));
916 }
917
918 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
919 struct hisi_sas_device *sas_dev)
920 {
921 struct domain_device *device = sas_dev->sas_device;
922 struct device *dev = hisi_hba->dev;
923 u64 qw0, device_id = sas_dev->device_id;
924 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
925 struct domain_device *parent_dev = device->parent;
926 struct asd_sas_port *sas_port = device->port;
927 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
928
929 memset(itct, 0, sizeof(*itct));
930
931 /* qw0 */
932 qw0 = 0;
933 switch (sas_dev->dev_type) {
934 case SAS_END_DEVICE:
935 case SAS_EDGE_EXPANDER_DEVICE:
936 case SAS_FANOUT_EXPANDER_DEVICE:
937 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
938 break;
939 case SAS_SATA_DEV:
940 case SAS_SATA_PENDING:
941 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
942 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
943 else
944 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
945 break;
946 default:
947 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
948 sas_dev->dev_type);
949 }
950
951 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
952 (device->linkrate << ITCT_HDR_MCR_OFF) |
953 (1 << ITCT_HDR_VLN_OFF) |
954 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
955 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
956 (port->id << ITCT_HDR_PORT_ID_OFF));
957 itct->qw0 = cpu_to_le64(qw0);
958
959 /* qw1 */
960 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
961 itct->sas_addr = __swab64(itct->sas_addr);
962
963 /* qw2 */
964 if (!dev_is_sata(device))
965 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
966 (0x1ULL << ITCT_HDR_BITLT_OFF) |
967 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
968 (0x1ULL << ITCT_HDR_RTOLT_OFF));
969 }
970
971 static void clear_itct_v2_hw(struct hisi_hba *hisi_hba,
972 struct hisi_sas_device *sas_dev)
973 {
974 DECLARE_COMPLETION_ONSTACK(completion);
975 u64 dev_id = sas_dev->device_id;
976 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
977 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
978 int i;
979
980 sas_dev->completion = &completion;
981
982 /* clear the itct interrupt state */
983 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
984 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
985 ENT_INT_SRC3_ITC_INT_MSK);
986
987 for (i = 0; i < 2; i++) {
988 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
989 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
990 wait_for_completion(sas_dev->completion);
991
992 memset(itct, 0, sizeof(struct hisi_sas_itct));
993 }
994 }
995
996 static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
997 {
998 struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
999
1000 /* SoC bug workaround */
1001 if (dev_is_sata(sas_dev->sas_device))
1002 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
1003 }
1004
1005 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
1006 {
1007 int i, reset_val;
1008 u32 val;
1009 unsigned long end_time;
1010 struct device *dev = hisi_hba->dev;
1011
1012 /* The mask needs to be set depending on the number of phys */
1013 if (hisi_hba->n_phy == 9)
1014 reset_val = 0x1fffff;
1015 else
1016 reset_val = 0x7ffff;
1017
1018 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1019
1020 /* Disable all of the PHYs */
1021 for (i = 0; i < hisi_hba->n_phy; i++) {
1022 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1023
1024 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1025 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1026 }
1027 udelay(50);
1028
1029 /* Ensure DMA tx & rx idle */
1030 for (i = 0; i < hisi_hba->n_phy; i++) {
1031 u32 dma_tx_status, dma_rx_status;
1032
1033 end_time = jiffies + msecs_to_jiffies(1000);
1034
1035 while (1) {
1036 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1037 DMA_TX_STATUS);
1038 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1039 DMA_RX_STATUS);
1040
1041 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1042 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1043 break;
1044
1045 msleep(20);
1046 if (time_after(jiffies, end_time))
1047 return -EIO;
1048 }
1049 }
1050
1051 /* Ensure axi bus idle */
1052 end_time = jiffies + msecs_to_jiffies(1000);
1053 while (1) {
1054 u32 axi_status =
1055 hisi_sas_read32(hisi_hba, AXI_CFG);
1056
1057 if (axi_status == 0)
1058 break;
1059
1060 msleep(20);
1061 if (time_after(jiffies, end_time))
1062 return -EIO;
1063 }
1064
1065 if (ACPI_HANDLE(dev)) {
1066 acpi_status s;
1067
1068 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1069 if (ACPI_FAILURE(s)) {
1070 dev_err(dev, "Reset failed\n");
1071 return -EIO;
1072 }
1073 } else if (hisi_hba->ctrl) {
1074 /* reset and disable clock*/
1075 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1076 reset_val);
1077 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1078 reset_val);
1079 msleep(1);
1080 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1081 if (reset_val != (val & reset_val)) {
1082 dev_err(dev, "SAS reset fail.\n");
1083 return -EIO;
1084 }
1085
1086 /* De-reset and enable clock*/
1087 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1088 reset_val);
1089 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1090 reset_val);
1091 msleep(1);
1092 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1093 &val);
1094 if (val & reset_val) {
1095 dev_err(dev, "SAS de-reset fail.\n");
1096 return -EIO;
1097 }
1098 } else
1099 dev_warn(dev, "no reset method\n");
1100
1101 return 0;
1102 }
1103
1104 /* This function needs to be called after resetting SAS controller. */
1105 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1106 {
1107 u32 cfg;
1108 int phy_no;
1109
1110 hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1111 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1112 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1113 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1114 continue;
1115
1116 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1117 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1118 }
1119 }
1120
1121 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1122 {
1123 int phy_no;
1124 u32 dma_tx_dfx1;
1125
1126 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1127 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1128 continue;
1129
1130 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1131 DMA_TX_DFX1);
1132 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1133 u32 cfg = hisi_sas_phy_read32(hisi_hba,
1134 phy_no, CON_CONTROL);
1135
1136 cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1137 hisi_sas_phy_write32(hisi_hba, phy_no,
1138 CON_CONTROL, cfg);
1139 clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1140 }
1141 }
1142 }
1143
1144 static const struct signal_attenuation_s x6000 = {9200, 0, 10476};
1145 static const struct sig_atten_lu_s sig_atten_lu[] = {
1146 { &x6000, 0x3016a68 },
1147 };
1148
1149 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1150 {
1151 struct device *dev = hisi_hba->dev;
1152 u32 sas_phy_ctrl = 0x30b9908;
1153 u32 signal[3];
1154 int i;
1155
1156 /* Global registers init */
1157
1158 /* Deal with am-max-transmissions quirk */
1159 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1160 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1161 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1162 0x2020);
1163 } /* Else, use defaults -> do nothing */
1164
1165 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1166 (u32)((1ULL << hisi_hba->queue_count) - 1));
1167 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1168 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1169 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1170 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1171 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1172 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1173 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1174 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1175 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1176 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1177 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1178 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1179 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1180 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1181 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1182 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1183 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1184 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1185 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1186 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1187 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1188 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1189 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1190 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1191 for (i = 0; i < hisi_hba->queue_count; i++)
1192 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1193
1194 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1195 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1196
1197 /* Get sas_phy_ctrl value to deal with TX FFE issue. */
1198 if (!device_property_read_u32_array(dev, "hisilicon,signal-attenuation",
1199 signal, ARRAY_SIZE(signal))) {
1200 for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) {
1201 const struct sig_atten_lu_s *lookup = &sig_atten_lu[i];
1202 const struct signal_attenuation_s *att = lookup->att;
1203
1204 if ((signal[0] == att->de_emphasis) &&
1205 (signal[1] == att->preshoot) &&
1206 (signal[2] == att->boost)) {
1207 sas_phy_ctrl = lookup->sas_phy_ctrl;
1208 break;
1209 }
1210 }
1211
1212 if (i == ARRAY_SIZE(sig_atten_lu))
1213 dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n");
1214 }
1215
1216 for (i = 0; i < hisi_hba->n_phy; i++) {
1217 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
1218 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl);
1219 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1220 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1221 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1222 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1223 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1224 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1225 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1226 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1227 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff);
1228 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbfe);
1229 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1230 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1231 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1232 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1233 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1234 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1235 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1236 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1237 if (hisi_hba->refclk_frequency_mhz == 66)
1238 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1239 /* else, do nothing -> leave it how you found it */
1240 }
1241
1242 for (i = 0; i < hisi_hba->queue_count; i++) {
1243 /* Delivery queue */
1244 hisi_sas_write32(hisi_hba,
1245 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1246 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1247
1248 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1249 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1250
1251 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1252 HISI_SAS_QUEUE_SLOTS);
1253
1254 /* Completion queue */
1255 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1256 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1257
1258 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1259 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1260
1261 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1262 HISI_SAS_QUEUE_SLOTS);
1263 }
1264
1265 /* itct */
1266 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1267 lower_32_bits(hisi_hba->itct_dma));
1268
1269 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1270 upper_32_bits(hisi_hba->itct_dma));
1271
1272 /* iost */
1273 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1274 lower_32_bits(hisi_hba->iost_dma));
1275
1276 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1277 upper_32_bits(hisi_hba->iost_dma));
1278
1279 /* breakpoint */
1280 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1281 lower_32_bits(hisi_hba->breakpoint_dma));
1282
1283 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1284 upper_32_bits(hisi_hba->breakpoint_dma));
1285
1286 /* SATA broken msg */
1287 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1288 lower_32_bits(hisi_hba->sata_breakpoint_dma));
1289
1290 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1291 upper_32_bits(hisi_hba->sata_breakpoint_dma));
1292
1293 /* SATA initial fis */
1294 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1295 lower_32_bits(hisi_hba->initial_fis_dma));
1296
1297 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1298 upper_32_bits(hisi_hba->initial_fis_dma));
1299 }
1300
1301 static void link_timeout_enable_link(struct timer_list *t)
1302 {
1303 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1304 int i, reg_val;
1305
1306 for (i = 0; i < hisi_hba->n_phy; i++) {
1307 if (hisi_hba->reject_stp_links_msk & BIT(i))
1308 continue;
1309
1310 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1311 if (!(reg_val & BIT(0))) {
1312 hisi_sas_phy_write32(hisi_hba, i,
1313 CON_CONTROL, 0x7);
1314 break;
1315 }
1316 }
1317
1318 hisi_hba->timer.function = link_timeout_disable_link;
1319 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1320 }
1321
1322 static void link_timeout_disable_link(struct timer_list *t)
1323 {
1324 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1325 int i, reg_val;
1326
1327 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1328 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1329 if (hisi_hba->reject_stp_links_msk & BIT(i))
1330 continue;
1331
1332 if (reg_val & BIT(i)) {
1333 hisi_sas_phy_write32(hisi_hba, i,
1334 CON_CONTROL, 0x6);
1335 break;
1336 }
1337 }
1338
1339 hisi_hba->timer.function = link_timeout_enable_link;
1340 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1341 }
1342
1343 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1344 {
1345 hisi_hba->timer.function = link_timeout_disable_link;
1346 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1347 add_timer(&hisi_hba->timer);
1348 }
1349
1350 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1351 {
1352 struct device *dev = hisi_hba->dev;
1353 int rc;
1354
1355 rc = reset_hw_v2_hw(hisi_hba);
1356 if (rc) {
1357 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1358 return rc;
1359 }
1360
1361 msleep(100);
1362 init_reg_v2_hw(hisi_hba);
1363
1364 return 0;
1365 }
1366
1367 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1368 {
1369 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1370
1371 cfg |= PHY_CFG_ENA_MSK;
1372 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1373 }
1374
1375 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1376 {
1377 u32 context;
1378
1379 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1380 if (context & (1 << phy_no))
1381 return true;
1382
1383 return false;
1384 }
1385
1386 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1387 {
1388 u32 dfx_val;
1389
1390 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1391
1392 if (dfx_val & BIT(16))
1393 return false;
1394
1395 return true;
1396 }
1397
1398 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1399 {
1400 int i, max_loop = 1000;
1401 struct device *dev = hisi_hba->dev;
1402 u32 status, axi_status, dfx_val, dfx_tx_val;
1403
1404 for (i = 0; i < max_loop; i++) {
1405 status = hisi_sas_read32_relaxed(hisi_hba,
1406 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1407
1408 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1409 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1410 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1411 phy_no, DMA_TX_FIFO_DFX0);
1412
1413 if ((status == 0x3) && (axi_status == 0x0) &&
1414 (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1415 return true;
1416 udelay(10);
1417 }
1418 dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1419 phy_no, status, axi_status,
1420 dfx_val, dfx_tx_val);
1421 return false;
1422 }
1423
1424 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1425 {
1426 int i, max_loop = 1000;
1427 struct device *dev = hisi_hba->dev;
1428 u32 status, tx_dfx0;
1429
1430 for (i = 0; i < max_loop; i++) {
1431 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1432 status = (status & 0x3fc0) >> 6;
1433
1434 if (status != 0x1)
1435 return true;
1436
1437 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1438 if ((tx_dfx0 & 0x1ff) == 0x2)
1439 return true;
1440 udelay(10);
1441 }
1442 dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1443 phy_no, status, tx_dfx0);
1444 return false;
1445 }
1446
1447 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1448 {
1449 if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1450 return true;
1451
1452 if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1453 return false;
1454
1455 if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1456 return false;
1457
1458 return true;
1459 }
1460
1461
1462 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1463 {
1464 u32 cfg, axi_val, dfx0_val, txid_auto;
1465 struct device *dev = hisi_hba->dev;
1466
1467 /* Close axi bus. */
1468 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1469 AM_CTRL_GLOBAL);
1470 axi_val |= 0x1;
1471 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1472 AM_CTRL_GLOBAL, axi_val);
1473
1474 if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1475 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1476 goto do_disable;
1477
1478 /* Reset host controller. */
1479 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1480 return;
1481 }
1482
1483 dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1484 dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1485 if (dfx0_val != 0x4)
1486 goto do_disable;
1487
1488 if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1489 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1490 phy_no);
1491 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1492 TXID_AUTO);
1493 txid_auto |= TXID_AUTO_CTB_MSK;
1494 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1495 txid_auto);
1496 }
1497
1498 do_disable:
1499 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1500 cfg &= ~PHY_CFG_ENA_MSK;
1501 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1502
1503 /* Open axi bus. */
1504 axi_val &= ~0x1;
1505 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1506 AM_CTRL_GLOBAL, axi_val);
1507 }
1508
1509 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1510 {
1511 config_id_frame_v2_hw(hisi_hba, phy_no);
1512 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1513 enable_phy_v2_hw(hisi_hba, phy_no);
1514 }
1515
1516 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1517 {
1518 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1519 u32 txid_auto;
1520
1521 disable_phy_v2_hw(hisi_hba, phy_no);
1522 if (phy->identify.device_type == SAS_END_DEVICE) {
1523 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1524 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1525 txid_auto | TX_HARDRST_MSK);
1526 }
1527 msleep(100);
1528 start_phy_v2_hw(hisi_hba, phy_no);
1529 }
1530
1531 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1532 {
1533 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1534 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1535 struct sas_phy *sphy = sas_phy->phy;
1536 u32 err4_reg_val, err6_reg_val;
1537
1538 /* loss dword syn, phy reset problem */
1539 err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1540
1541 /* disparity err, invalid dword */
1542 err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1543
1544 sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1545 sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1546 sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1547 sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1548 }
1549
1550 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1551 {
1552 int i;
1553
1554 for (i = 0; i < hisi_hba->n_phy; i++) {
1555 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1556 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1557
1558 if (!sas_phy->phy->enabled)
1559 continue;
1560
1561 start_phy_v2_hw(hisi_hba, i);
1562 }
1563 }
1564
1565 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1566 {
1567 u32 sl_control;
1568
1569 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1570 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1571 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1572 msleep(1);
1573 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1574 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1575 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1576 }
1577
1578 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1579 {
1580 return SAS_LINK_RATE_12_0_GBPS;
1581 }
1582
1583 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1584 struct sas_phy_linkrates *r)
1585 {
1586 u32 prog_phy_link_rate =
1587 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1588 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1589 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1590 int i;
1591 enum sas_linkrate min, max;
1592 u32 rate_mask = 0;
1593
1594 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1595 max = sas_phy->phy->maximum_linkrate;
1596 min = r->minimum_linkrate;
1597 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1598 max = r->maximum_linkrate;
1599 min = sas_phy->phy->minimum_linkrate;
1600 } else
1601 return;
1602
1603 sas_phy->phy->maximum_linkrate = max;
1604 sas_phy->phy->minimum_linkrate = min;
1605
1606 max -= SAS_LINK_RATE_1_5_GBPS;
1607
1608 for (i = 0; i <= max; i++)
1609 rate_mask |= 1 << (i * 2);
1610
1611 prog_phy_link_rate &= ~0xff;
1612 prog_phy_link_rate |= rate_mask;
1613
1614 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1615 prog_phy_link_rate);
1616
1617 phy_hard_reset_v2_hw(hisi_hba, phy_no);
1618 }
1619
1620 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1621 {
1622 int i, bitmap = 0;
1623 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1624 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1625
1626 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1627 if (phy_state & 1 << i)
1628 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1629 bitmap |= 1 << i;
1630
1631 if (hisi_hba->n_phy == 9) {
1632 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1633
1634 if (phy_state & 1 << 8)
1635 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1636 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1637 bitmap |= 1 << 9;
1638 }
1639
1640 return bitmap;
1641 }
1642
1643 /*
1644 * The callpath to this function and upto writing the write
1645 * queue pointer should be safe from interruption.
1646 */
1647 static int
1648 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1649 {
1650 struct device *dev = hisi_hba->dev;
1651 int queue = dq->id;
1652 u32 r, w;
1653
1654 w = dq->wr_point;
1655 r = hisi_sas_read32_relaxed(hisi_hba,
1656 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1657 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1658 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
1659 queue, r, w);
1660 return -EAGAIN;
1661 }
1662
1663 return 0;
1664 }
1665
1666 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1667 {
1668 struct hisi_hba *hisi_hba = dq->hisi_hba;
1669 int dlvry_queue = dq->slot_prep->dlvry_queue;
1670 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
1671
1672 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1673 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1674 dq->wr_point);
1675 }
1676
1677 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1678 struct hisi_sas_slot *slot,
1679 struct hisi_sas_cmd_hdr *hdr,
1680 struct scatterlist *scatter,
1681 int n_elem)
1682 {
1683 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1684 struct device *dev = hisi_hba->dev;
1685 struct scatterlist *sg;
1686 int i;
1687
1688 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1689 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1690 n_elem);
1691 return -EINVAL;
1692 }
1693
1694 for_each_sg(scatter, sg, n_elem, i) {
1695 struct hisi_sas_sge *entry = &sge_page->sge[i];
1696
1697 entry->addr = cpu_to_le64(sg_dma_address(sg));
1698 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1699 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1700 entry->data_off = 0;
1701 }
1702
1703 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1704
1705 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1706
1707 return 0;
1708 }
1709
1710 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1711 struct hisi_sas_slot *slot)
1712 {
1713 struct sas_task *task = slot->task;
1714 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1715 struct domain_device *device = task->dev;
1716 struct device *dev = hisi_hba->dev;
1717 struct hisi_sas_port *port = slot->port;
1718 struct scatterlist *sg_req, *sg_resp;
1719 struct hisi_sas_device *sas_dev = device->lldd_dev;
1720 dma_addr_t req_dma_addr;
1721 unsigned int req_len, resp_len;
1722 int elem, rc;
1723
1724 /*
1725 * DMA-map SMP request, response buffers
1726 */
1727 /* req */
1728 sg_req = &task->smp_task.smp_req;
1729 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1730 if (!elem)
1731 return -ENOMEM;
1732 req_len = sg_dma_len(sg_req);
1733 req_dma_addr = sg_dma_address(sg_req);
1734
1735 /* resp */
1736 sg_resp = &task->smp_task.smp_resp;
1737 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1738 if (!elem) {
1739 rc = -ENOMEM;
1740 goto err_out_req;
1741 }
1742 resp_len = sg_dma_len(sg_resp);
1743 if ((req_len & 0x3) || (resp_len & 0x3)) {
1744 rc = -EINVAL;
1745 goto err_out_resp;
1746 }
1747
1748 /* create header */
1749 /* dw0 */
1750 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1751 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1752 (2 << CMD_HDR_CMD_OFF)); /* smp */
1753
1754 /* map itct entry */
1755 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1756 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1757 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1758
1759 /* dw2 */
1760 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1761 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1762 CMD_HDR_MRFL_OFF));
1763
1764 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1765
1766 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1767 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1768
1769 return 0;
1770
1771 err_out_resp:
1772 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1773 DMA_FROM_DEVICE);
1774 err_out_req:
1775 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1776 DMA_TO_DEVICE);
1777 return rc;
1778 }
1779
1780 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1781 struct hisi_sas_slot *slot, int is_tmf,
1782 struct hisi_sas_tmf_task *tmf)
1783 {
1784 struct sas_task *task = slot->task;
1785 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1786 struct domain_device *device = task->dev;
1787 struct hisi_sas_device *sas_dev = device->lldd_dev;
1788 struct hisi_sas_port *port = slot->port;
1789 struct sas_ssp_task *ssp_task = &task->ssp_task;
1790 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1791 int has_data = 0, rc, priority = is_tmf;
1792 u8 *buf_cmd;
1793 u32 dw1 = 0, dw2 = 0;
1794
1795 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1796 (2 << CMD_HDR_TLR_CTRL_OFF) |
1797 (port->id << CMD_HDR_PORT_OFF) |
1798 (priority << CMD_HDR_PRIORITY_OFF) |
1799 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1800
1801 dw1 = 1 << CMD_HDR_VDTL_OFF;
1802 if (is_tmf) {
1803 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1804 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1805 } else {
1806 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1807 switch (scsi_cmnd->sc_data_direction) {
1808 case DMA_TO_DEVICE:
1809 has_data = 1;
1810 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1811 break;
1812 case DMA_FROM_DEVICE:
1813 has_data = 1;
1814 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1815 break;
1816 default:
1817 dw1 &= ~CMD_HDR_DIR_MSK;
1818 }
1819 }
1820
1821 /* map itct entry */
1822 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1823 hdr->dw1 = cpu_to_le32(dw1);
1824
1825 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1826 + 3) / 4) << CMD_HDR_CFL_OFF) |
1827 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1828 (2 << CMD_HDR_SG_MOD_OFF);
1829 hdr->dw2 = cpu_to_le32(dw2);
1830
1831 hdr->transfer_tags = cpu_to_le32(slot->idx);
1832
1833 if (has_data) {
1834 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1835 slot->n_elem);
1836 if (rc)
1837 return rc;
1838 }
1839
1840 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1841 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1842 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1843
1844 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1845 sizeof(struct ssp_frame_hdr);
1846
1847 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1848 if (!is_tmf) {
1849 buf_cmd[9] = task->ssp_task.task_attr |
1850 (task->ssp_task.task_prio << 3);
1851 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1852 task->ssp_task.cmd->cmd_len);
1853 } else {
1854 buf_cmd[10] = tmf->tmf;
1855 switch (tmf->tmf) {
1856 case TMF_ABORT_TASK:
1857 case TMF_QUERY_TASK:
1858 buf_cmd[12] =
1859 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1860 buf_cmd[13] =
1861 tmf->tag_of_task_to_be_managed & 0xff;
1862 break;
1863 default:
1864 break;
1865 }
1866 }
1867
1868 return 0;
1869 }
1870
1871 #define TRANS_TX_ERR 0
1872 #define TRANS_RX_ERR 1
1873 #define DMA_TX_ERR 2
1874 #define SIPC_RX_ERR 3
1875 #define DMA_RX_ERR 4
1876
1877 #define DMA_TX_ERR_OFF 0
1878 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1879 #define SIPC_RX_ERR_OFF 16
1880 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1881
1882 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1883 {
1884 static const u8 trans_tx_err_code_prio[] = {
1885 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1886 TRANS_TX_ERR_PHY_NOT_ENABLE,
1887 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1888 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1889 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1890 RESERVED0,
1891 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1892 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1893 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1894 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1895 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1896 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1897 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1898 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1899 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1900 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1901 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1902 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1903 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1904 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1905 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1906 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1907 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1908 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1909 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1910 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1911 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1912 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1913 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1914 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1915 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1916 };
1917 int index, i;
1918
1919 for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1920 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1921 if (err_msk & (1 << index))
1922 return trans_tx_err_code_prio[i];
1923 }
1924 return -1;
1925 }
1926
1927 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1928 {
1929 static const u8 trans_rx_err_code_prio[] = {
1930 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1931 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1932 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1933 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1934 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1935 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1936 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1937 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1938 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1939 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1940 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1941 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1942 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1943 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1944 RESERVED1,
1945 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1946 TRANS_RX_ERR_WITH_DATA_LEN0,
1947 TRANS_RX_ERR_WITH_BAD_HASH,
1948 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1949 TRANS_RX_SSP_FRM_LEN_ERR,
1950 RESERVED2,
1951 RESERVED3,
1952 RESERVED4,
1953 RESERVED5,
1954 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1955 TRANS_RX_SMP_FRM_LEN_ERR,
1956 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1957 RESERVED6,
1958 RESERVED7,
1959 RESERVED8,
1960 RESERVED9,
1961 TRANS_RX_R_ERR,
1962 };
1963 int index, i;
1964
1965 for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1966 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1967 if (err_msk & (1 << index))
1968 return trans_rx_err_code_prio[i];
1969 }
1970 return -1;
1971 }
1972
1973 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1974 {
1975 static const u8 dma_tx_err_code_prio[] = {
1976 DMA_TX_UNEXP_XFER_ERR,
1977 DMA_TX_UNEXP_RETRANS_ERR,
1978 DMA_TX_XFER_LEN_OVERFLOW,
1979 DMA_TX_XFER_OFFSET_ERR,
1980 DMA_TX_RAM_ECC_ERR,
1981 DMA_TX_DIF_LEN_ALIGN_ERR,
1982 DMA_TX_DIF_CRC_ERR,
1983 DMA_TX_DIF_APP_ERR,
1984 DMA_TX_DIF_RPP_ERR,
1985 DMA_TX_DATA_SGL_OVERFLOW,
1986 DMA_TX_DIF_SGL_OVERFLOW,
1987 };
1988 int index, i;
1989
1990 for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1991 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1992 err_msk = err_msk & DMA_TX_ERR_MSK;
1993 if (err_msk & (1 << index))
1994 return dma_tx_err_code_prio[i];
1995 }
1996 return -1;
1997 }
1998
1999 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
2000 {
2001 static const u8 sipc_rx_err_code_prio[] = {
2002 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
2003 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
2004 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
2005 SIPC_RX_WRSETUP_LEN_ODD_ERR,
2006 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
2007 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
2008 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
2009 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
2010 SIPC_RX_SATA_UNEXP_FIS_ERR,
2011 SIPC_RX_WRSETUP_ESTATUS_ERR,
2012 SIPC_RX_DATA_UNDERFLOW_ERR,
2013 };
2014 int index, i;
2015
2016 for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
2017 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
2018 err_msk = err_msk & SIPC_RX_ERR_MSK;
2019 if (err_msk & (1 << (index + 0x10)))
2020 return sipc_rx_err_code_prio[i];
2021 }
2022 return -1;
2023 }
2024
2025 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
2026 {
2027 static const u8 dma_rx_err_code_prio[] = {
2028 DMA_RX_UNKNOWN_FRM_ERR,
2029 DMA_RX_DATA_LEN_OVERFLOW,
2030 DMA_RX_DATA_LEN_UNDERFLOW,
2031 DMA_RX_DATA_OFFSET_ERR,
2032 RESERVED10,
2033 DMA_RX_SATA_FRAME_TYPE_ERR,
2034 DMA_RX_RESP_BUF_OVERFLOW,
2035 DMA_RX_UNEXP_RETRANS_RESP_ERR,
2036 DMA_RX_UNEXP_NORM_RESP_ERR,
2037 DMA_RX_UNEXP_RDFRAME_ERR,
2038 DMA_RX_PIO_DATA_LEN_ERR,
2039 DMA_RX_RDSETUP_STATUS_ERR,
2040 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2041 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2042 DMA_RX_RDSETUP_LEN_ODD_ERR,
2043 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2044 DMA_RX_RDSETUP_LEN_OVER_ERR,
2045 DMA_RX_RDSETUP_OFFSET_ERR,
2046 DMA_RX_RDSETUP_ACTIVE_ERR,
2047 DMA_RX_RDSETUP_ESTATUS_ERR,
2048 DMA_RX_RAM_ECC_ERR,
2049 DMA_RX_DIF_CRC_ERR,
2050 DMA_RX_DIF_APP_ERR,
2051 DMA_RX_DIF_RPP_ERR,
2052 DMA_RX_DATA_SGL_OVERFLOW,
2053 DMA_RX_DIF_SGL_OVERFLOW,
2054 };
2055 int index, i;
2056
2057 for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2058 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2059 if (err_msk & (1 << index))
2060 return dma_rx_err_code_prio[i];
2061 }
2062 return -1;
2063 }
2064
2065 /* by default, task resp is complete */
2066 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2067 struct sas_task *task,
2068 struct hisi_sas_slot *slot,
2069 int err_phase)
2070 {
2071 struct task_status_struct *ts = &task->task_status;
2072 struct hisi_sas_err_record_v2 *err_record =
2073 hisi_sas_status_buf_addr_mem(slot);
2074 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2075 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2076 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2077 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2078 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2079 int error = -1;
2080
2081 if (err_phase == 1) {
2082 /* error in TX phase, the priority of error is: DW2 > DW0 */
2083 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2084 if (error == -1)
2085 error = parse_trans_tx_err_code_v2_hw(
2086 trans_tx_fail_type);
2087 } else if (err_phase == 2) {
2088 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2089 error = parse_trans_rx_err_code_v2_hw(
2090 trans_rx_fail_type);
2091 if (error == -1) {
2092 error = parse_dma_rx_err_code_v2_hw(
2093 dma_rx_err_type);
2094 if (error == -1)
2095 error = parse_sipc_rx_err_code_v2_hw(
2096 sipc_rx_err_type);
2097 }
2098 }
2099
2100 switch (task->task_proto) {
2101 case SAS_PROTOCOL_SSP:
2102 {
2103 switch (error) {
2104 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2105 {
2106 ts->stat = SAS_OPEN_REJECT;
2107 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2108 break;
2109 }
2110 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2111 {
2112 ts->stat = SAS_OPEN_REJECT;
2113 ts->open_rej_reason = SAS_OREJ_EPROTO;
2114 break;
2115 }
2116 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2117 {
2118 ts->stat = SAS_OPEN_REJECT;
2119 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2120 break;
2121 }
2122 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2123 {
2124 ts->stat = SAS_OPEN_REJECT;
2125 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2126 break;
2127 }
2128 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2129 {
2130 ts->stat = SAS_OPEN_REJECT;
2131 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2132 break;
2133 }
2134 case DMA_RX_UNEXP_NORM_RESP_ERR:
2135 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2136 case DMA_RX_RESP_BUF_OVERFLOW:
2137 {
2138 ts->stat = SAS_OPEN_REJECT;
2139 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2140 break;
2141 }
2142 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2143 {
2144 /* not sure */
2145 ts->stat = SAS_DEV_NO_RESPONSE;
2146 break;
2147 }
2148 case DMA_RX_DATA_LEN_OVERFLOW:
2149 {
2150 ts->stat = SAS_DATA_OVERRUN;
2151 ts->residual = 0;
2152 break;
2153 }
2154 case DMA_RX_DATA_LEN_UNDERFLOW:
2155 {
2156 ts->residual = trans_tx_fail_type;
2157 ts->stat = SAS_DATA_UNDERRUN;
2158 break;
2159 }
2160 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2161 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2162 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2163 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2164 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2165 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2166 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2167 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2168 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2169 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2170 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2171 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2172 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2173 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2174 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2175 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2176 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2177 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2178 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2179 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2180 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2181 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2182 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2183 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2184 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2185 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2186 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2187 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2188 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2189 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2190 case TRANS_TX_ERR_FRAME_TXED:
2191 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2192 case TRANS_RX_ERR_WITH_DATA_LEN0:
2193 case TRANS_RX_ERR_WITH_BAD_HASH:
2194 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2195 case TRANS_RX_SSP_FRM_LEN_ERR:
2196 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2197 case DMA_TX_DATA_SGL_OVERFLOW:
2198 case DMA_TX_UNEXP_XFER_ERR:
2199 case DMA_TX_UNEXP_RETRANS_ERR:
2200 case DMA_TX_XFER_LEN_OVERFLOW:
2201 case DMA_TX_XFER_OFFSET_ERR:
2202 case SIPC_RX_DATA_UNDERFLOW_ERR:
2203 case DMA_RX_DATA_SGL_OVERFLOW:
2204 case DMA_RX_DATA_OFFSET_ERR:
2205 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2206 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2207 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2208 case DMA_RX_SATA_FRAME_TYPE_ERR:
2209 case DMA_RX_UNKNOWN_FRM_ERR:
2210 {
2211 /* This will request a retry */
2212 ts->stat = SAS_QUEUE_FULL;
2213 slot->abort = 1;
2214 break;
2215 }
2216 default:
2217 break;
2218 }
2219 }
2220 break;
2221 case SAS_PROTOCOL_SMP:
2222 ts->stat = SAM_STAT_CHECK_CONDITION;
2223 break;
2224
2225 case SAS_PROTOCOL_SATA:
2226 case SAS_PROTOCOL_STP:
2227 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2228 {
2229 switch (error) {
2230 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2231 {
2232 ts->stat = SAS_OPEN_REJECT;
2233 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2234 break;
2235 }
2236 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2237 {
2238 ts->resp = SAS_TASK_UNDELIVERED;
2239 ts->stat = SAS_DEV_NO_RESPONSE;
2240 break;
2241 }
2242 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2243 {
2244 ts->stat = SAS_OPEN_REJECT;
2245 ts->open_rej_reason = SAS_OREJ_EPROTO;
2246 break;
2247 }
2248 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2249 {
2250 ts->stat = SAS_OPEN_REJECT;
2251 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2252 break;
2253 }
2254 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2255 {
2256 ts->stat = SAS_OPEN_REJECT;
2257 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2258 break;
2259 }
2260 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2261 {
2262 ts->stat = SAS_OPEN_REJECT;
2263 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2264 break;
2265 }
2266 case DMA_RX_RESP_BUF_OVERFLOW:
2267 case DMA_RX_UNEXP_NORM_RESP_ERR:
2268 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2269 {
2270 ts->stat = SAS_OPEN_REJECT;
2271 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2272 break;
2273 }
2274 case DMA_RX_DATA_LEN_OVERFLOW:
2275 {
2276 ts->stat = SAS_DATA_OVERRUN;
2277 ts->residual = 0;
2278 break;
2279 }
2280 case DMA_RX_DATA_LEN_UNDERFLOW:
2281 {
2282 ts->residual = trans_tx_fail_type;
2283 ts->stat = SAS_DATA_UNDERRUN;
2284 break;
2285 }
2286 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2287 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2288 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2289 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2290 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2291 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2292 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2293 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2294 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2295 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2296 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2297 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2298 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2299 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2300 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2301 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2302 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2303 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2304 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2305 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2306 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2307 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2308 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2309 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2310 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2311 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2312 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2313 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2314 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2315 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2316 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2317 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2318 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2319 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2320 case TRANS_RX_ERR_WITH_DATA_LEN0:
2321 case TRANS_RX_ERR_WITH_BAD_HASH:
2322 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2323 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2324 case DMA_TX_DATA_SGL_OVERFLOW:
2325 case DMA_TX_UNEXP_XFER_ERR:
2326 case DMA_TX_UNEXP_RETRANS_ERR:
2327 case DMA_TX_XFER_LEN_OVERFLOW:
2328 case DMA_TX_XFER_OFFSET_ERR:
2329 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2330 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2331 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2332 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2333 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2334 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2335 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2336 case DMA_RX_DATA_SGL_OVERFLOW:
2337 case DMA_RX_DATA_OFFSET_ERR:
2338 case DMA_RX_SATA_FRAME_TYPE_ERR:
2339 case DMA_RX_UNEXP_RDFRAME_ERR:
2340 case DMA_RX_PIO_DATA_LEN_ERR:
2341 case DMA_RX_RDSETUP_STATUS_ERR:
2342 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2343 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2344 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2345 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2346 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2347 case DMA_RX_RDSETUP_OFFSET_ERR:
2348 case DMA_RX_RDSETUP_ACTIVE_ERR:
2349 case DMA_RX_RDSETUP_ESTATUS_ERR:
2350 case DMA_RX_UNKNOWN_FRM_ERR:
2351 case TRANS_RX_SSP_FRM_LEN_ERR:
2352 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2353 {
2354 slot->abort = 1;
2355 ts->stat = SAS_PHY_DOWN;
2356 break;
2357 }
2358 default:
2359 {
2360 ts->stat = SAS_PROTO_RESPONSE;
2361 break;
2362 }
2363 }
2364 hisi_sas_sata_done(task, slot);
2365 }
2366 break;
2367 default:
2368 break;
2369 }
2370 }
2371
2372 static int
2373 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2374 {
2375 struct sas_task *task = slot->task;
2376 struct hisi_sas_device *sas_dev;
2377 struct device *dev = hisi_hba->dev;
2378 struct task_status_struct *ts;
2379 struct domain_device *device;
2380 enum exec_status sts;
2381 struct hisi_sas_complete_v2_hdr *complete_queue =
2382 hisi_hba->complete_hdr[slot->cmplt_queue];
2383 struct hisi_sas_complete_v2_hdr *complete_hdr =
2384 &complete_queue[slot->cmplt_queue_slot];
2385 unsigned long flags;
2386 int aborted;
2387
2388 if (unlikely(!task || !task->lldd_task || !task->dev))
2389 return -EINVAL;
2390
2391 ts = &task->task_status;
2392 device = task->dev;
2393 sas_dev = device->lldd_dev;
2394
2395 spin_lock_irqsave(&task->task_state_lock, flags);
2396 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
2397 task->task_state_flags &=
2398 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2399 spin_unlock_irqrestore(&task->task_state_lock, flags);
2400
2401 memset(ts, 0, sizeof(*ts));
2402 ts->resp = SAS_TASK_COMPLETE;
2403
2404 if (unlikely(aborted)) {
2405 dev_dbg(dev, "slot_complete: task(%p) aborted\n", task);
2406 ts->stat = SAS_ABORTED_TASK;
2407 spin_lock_irqsave(&hisi_hba->lock, flags);
2408 hisi_sas_slot_task_free(hisi_hba, task, slot);
2409 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2410 return -1;
2411 }
2412
2413 if (unlikely(!sas_dev)) {
2414 dev_dbg(dev, "slot complete: port has no device\n");
2415 ts->stat = SAS_PHY_DOWN;
2416 goto out;
2417 }
2418
2419 /* Use SAS+TMF status codes */
2420 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2421 >> CMPLT_HDR_ABORT_STAT_OFF) {
2422 case STAT_IO_ABORTED:
2423 /* this io has been aborted by abort command */
2424 ts->stat = SAS_ABORTED_TASK;
2425 goto out;
2426 case STAT_IO_COMPLETE:
2427 /* internal abort command complete */
2428 ts->stat = TMF_RESP_FUNC_SUCC;
2429 del_timer(&slot->internal_abort_timer);
2430 goto out;
2431 case STAT_IO_NO_DEVICE:
2432 ts->stat = TMF_RESP_FUNC_COMPLETE;
2433 del_timer(&slot->internal_abort_timer);
2434 goto out;
2435 case STAT_IO_NOT_VALID:
2436 /* abort single io, controller don't find
2437 * the io need to abort
2438 */
2439 ts->stat = TMF_RESP_FUNC_FAILED;
2440 del_timer(&slot->internal_abort_timer);
2441 goto out;
2442 default:
2443 break;
2444 }
2445
2446 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2447 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2448 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2449 >> CMPLT_HDR_ERR_PHASE_OFF;
2450 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2451
2452 /* Analyse error happens on which phase TX or RX */
2453 if (ERR_ON_TX_PHASE(err_phase))
2454 slot_err_v2_hw(hisi_hba, task, slot, 1);
2455 else if (ERR_ON_RX_PHASE(err_phase))
2456 slot_err_v2_hw(hisi_hba, task, slot, 2);
2457
2458 if (ts->stat != SAS_DATA_UNDERRUN)
2459 dev_info(dev, "erroneous completion iptt=%d task=%p "
2460 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
2461 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
2462 slot->idx, task,
2463 complete_hdr->dw0, complete_hdr->dw1,
2464 complete_hdr->act, complete_hdr->dw3,
2465 error_info[0], error_info[1],
2466 error_info[2], error_info[3]);
2467
2468 if (unlikely(slot->abort))
2469 return ts->stat;
2470 goto out;
2471 }
2472
2473 switch (task->task_proto) {
2474 case SAS_PROTOCOL_SSP:
2475 {
2476 struct hisi_sas_status_buffer *status_buffer =
2477 hisi_sas_status_buf_addr_mem(slot);
2478 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2479 &status_buffer->iu[0];
2480
2481 sas_ssp_task_response(dev, task, iu);
2482 break;
2483 }
2484 case SAS_PROTOCOL_SMP:
2485 {
2486 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2487 void *to;
2488
2489 ts->stat = SAM_STAT_GOOD;
2490 to = kmap_atomic(sg_page(sg_resp));
2491
2492 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2493 DMA_FROM_DEVICE);
2494 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2495 DMA_TO_DEVICE);
2496 memcpy(to + sg_resp->offset,
2497 hisi_sas_status_buf_addr_mem(slot) +
2498 sizeof(struct hisi_sas_err_record),
2499 sg_dma_len(sg_resp));
2500 kunmap_atomic(to);
2501 break;
2502 }
2503 case SAS_PROTOCOL_SATA:
2504 case SAS_PROTOCOL_STP:
2505 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2506 {
2507 ts->stat = SAM_STAT_GOOD;
2508 hisi_sas_sata_done(task, slot);
2509 break;
2510 }
2511 default:
2512 ts->stat = SAM_STAT_CHECK_CONDITION;
2513 break;
2514 }
2515
2516 if (!slot->port->port_attached) {
2517 dev_warn(dev, "slot complete: port %d has removed\n",
2518 slot->port->sas_port.id);
2519 ts->stat = SAS_PHY_DOWN;
2520 }
2521
2522 out:
2523 spin_lock_irqsave(&task->task_state_lock, flags);
2524 task->task_state_flags |= SAS_TASK_STATE_DONE;
2525 spin_unlock_irqrestore(&task->task_state_lock, flags);
2526 spin_lock_irqsave(&hisi_hba->lock, flags);
2527 hisi_sas_slot_task_free(hisi_hba, task, slot);
2528 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2529 sts = ts->stat;
2530
2531 if (task->task_done)
2532 task->task_done(task);
2533
2534 return sts;
2535 }
2536
2537 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2538 struct hisi_sas_slot *slot)
2539 {
2540 struct sas_task *task = slot->task;
2541 struct domain_device *device = task->dev;
2542 struct domain_device *parent_dev = device->parent;
2543 struct hisi_sas_device *sas_dev = device->lldd_dev;
2544 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2545 struct asd_sas_port *sas_port = device->port;
2546 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2547 u8 *buf_cmd;
2548 int has_data = 0, rc = 0, hdr_tag = 0;
2549 u32 dw1 = 0, dw2 = 0;
2550
2551 /* create header */
2552 /* dw0 */
2553 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2554 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2555 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2556 else
2557 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2558
2559 /* dw1 */
2560 switch (task->data_dir) {
2561 case DMA_TO_DEVICE:
2562 has_data = 1;
2563 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2564 break;
2565 case DMA_FROM_DEVICE:
2566 has_data = 1;
2567 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2568 break;
2569 default:
2570 dw1 &= ~CMD_HDR_DIR_MSK;
2571 }
2572
2573 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2574 (task->ata_task.fis.control & ATA_SRST))
2575 dw1 |= 1 << CMD_HDR_RESET_OFF;
2576
2577 dw1 |= (hisi_sas_get_ata_protocol(
2578 &task->ata_task.fis, task->data_dir))
2579 << CMD_HDR_FRAME_TYPE_OFF;
2580 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2581 hdr->dw1 = cpu_to_le32(dw1);
2582
2583 /* dw2 */
2584 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2585 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2586 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2587 }
2588
2589 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2590 2 << CMD_HDR_SG_MOD_OFF;
2591 hdr->dw2 = cpu_to_le32(dw2);
2592
2593 /* dw3 */
2594 hdr->transfer_tags = cpu_to_le32(slot->idx);
2595
2596 if (has_data) {
2597 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2598 slot->n_elem);
2599 if (rc)
2600 return rc;
2601 }
2602
2603 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2604 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2605 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2606
2607 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2608
2609 if (likely(!task->ata_task.device_control_reg_update))
2610 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2611 /* fill in command FIS */
2612 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2613
2614 return 0;
2615 }
2616
2617 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
2618 {
2619 struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
2620 struct hisi_sas_port *port = slot->port;
2621 struct asd_sas_port *asd_sas_port;
2622 struct asd_sas_phy *sas_phy;
2623
2624 if (!port)
2625 return;
2626
2627 asd_sas_port = &port->sas_port;
2628
2629 /* Kick the hardware - send break command */
2630 list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2631 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2632 struct hisi_hba *hisi_hba = phy->hisi_hba;
2633 int phy_no = sas_phy->id;
2634 u32 link_dfx2;
2635
2636 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2637 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2638 (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2639 u32 txid_auto;
2640
2641 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2642 TXID_AUTO);
2643 txid_auto |= TXID_AUTO_CTB_MSK;
2644 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2645 txid_auto);
2646 return;
2647 }
2648 }
2649 }
2650
2651 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2652 struct hisi_sas_slot *slot,
2653 int device_id, int abort_flag, int tag_to_abort)
2654 {
2655 struct sas_task *task = slot->task;
2656 struct domain_device *dev = task->dev;
2657 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2658 struct hisi_sas_port *port = slot->port;
2659 struct timer_list *timer = &slot->internal_abort_timer;
2660
2661 /* setup the quirk timer */
2662 timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
2663 /* Set the timeout to 10ms less than internal abort timeout */
2664 mod_timer(timer, jiffies + msecs_to_jiffies(100));
2665
2666 /* dw0 */
2667 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2668 (port->id << CMD_HDR_PORT_OFF) |
2669 ((dev_is_sata(dev) ? 1:0) <<
2670 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2671 (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2672
2673 /* dw1 */
2674 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2675
2676 /* dw7 */
2677 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2678 hdr->transfer_tags = cpu_to_le32(slot->idx);
2679
2680 return 0;
2681 }
2682
2683 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2684 {
2685 int i, res = IRQ_HANDLED;
2686 u32 port_id, link_rate;
2687 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2688 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2689 struct device *dev = hisi_hba->dev;
2690 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2691 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2692
2693 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2694
2695 if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2696 goto end;
2697
2698 if (phy_no == 8) {
2699 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2700
2701 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2702 PORT_STATE_PHY8_PORT_NUM_OFF;
2703 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2704 PORT_STATE_PHY8_CONN_RATE_OFF;
2705 } else {
2706 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2707 port_id = (port_id >> (4 * phy_no)) & 0xf;
2708 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2709 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2710 }
2711
2712 if (port_id == 0xf) {
2713 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2714 res = IRQ_NONE;
2715 goto end;
2716 }
2717
2718 for (i = 0; i < 6; i++) {
2719 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2720 RX_IDAF_DWORD0 + (i * 4));
2721 frame_rcvd[i] = __swab32(idaf);
2722 }
2723
2724 sas_phy->linkrate = link_rate;
2725 sas_phy->oob_mode = SAS_OOB_MODE;
2726 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2727 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2728 phy->port_id = port_id;
2729 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2730 phy->phy_type |= PORT_TYPE_SAS;
2731 phy->phy_attached = 1;
2732 phy->identify.device_type = id->dev_type;
2733 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
2734 if (phy->identify.device_type == SAS_END_DEVICE)
2735 phy->identify.target_port_protocols =
2736 SAS_PROTOCOL_SSP;
2737 else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2738 phy->identify.target_port_protocols =
2739 SAS_PROTOCOL_SMP;
2740 if (!timer_pending(&hisi_hba->timer))
2741 set_link_timer_quirk(hisi_hba);
2742 }
2743 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
2744
2745 end:
2746 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2747 CHL_INT0_SL_PHY_ENABLE_MSK);
2748 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2749
2750 return res;
2751 }
2752
2753 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2754 {
2755 u32 port_state;
2756
2757 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2758 if (port_state & 0x1ff)
2759 return true;
2760
2761 return false;
2762 }
2763
2764 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2765 {
2766 u32 phy_state, sl_ctrl, txid_auto;
2767 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2768 struct hisi_sas_port *port = phy->port;
2769 struct device *dev = hisi_hba->dev;
2770
2771 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2772
2773 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2774 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
2775 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2776
2777 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2778 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2779 sl_ctrl & ~SL_CONTROL_CTA_MSK);
2780 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2781 if (!check_any_wideports_v2_hw(hisi_hba) &&
2782 timer_pending(&hisi_hba->timer))
2783 del_timer(&hisi_hba->timer);
2784
2785 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2786 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2787 txid_auto | TXID_AUTO_CT3_MSK);
2788
2789 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2790 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2791
2792 return IRQ_HANDLED;
2793 }
2794
2795 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2796 {
2797 struct hisi_hba *hisi_hba = p;
2798 u32 irq_msk;
2799 int phy_no = 0;
2800 irqreturn_t res = IRQ_NONE;
2801
2802 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2803 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2804 while (irq_msk) {
2805 if (irq_msk & 1) {
2806 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2807 CHL_INT0);
2808
2809 switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2810 CHL_INT0_SL_PHY_ENABLE_MSK)) {
2811
2812 case CHL_INT0_SL_PHY_ENABLE_MSK:
2813 /* phy up */
2814 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2815 IRQ_HANDLED)
2816 res = IRQ_HANDLED;
2817 break;
2818
2819 case CHL_INT0_NOT_RDY_MSK:
2820 /* phy down */
2821 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2822 IRQ_HANDLED)
2823 res = IRQ_HANDLED;
2824 break;
2825
2826 case (CHL_INT0_NOT_RDY_MSK |
2827 CHL_INT0_SL_PHY_ENABLE_MSK):
2828 reg_value = hisi_sas_read32(hisi_hba,
2829 PHY_STATE);
2830 if (reg_value & BIT(phy_no)) {
2831 /* phy up */
2832 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2833 IRQ_HANDLED)
2834 res = IRQ_HANDLED;
2835 } else {
2836 /* phy down */
2837 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2838 IRQ_HANDLED)
2839 res = IRQ_HANDLED;
2840 }
2841 break;
2842
2843 default:
2844 break;
2845 }
2846
2847 }
2848 irq_msk >>= 1;
2849 phy_no++;
2850 }
2851
2852 return res;
2853 }
2854
2855 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2856 {
2857 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2858 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2859 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2860 u32 bcast_status;
2861
2862 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2863 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2864 if (bcast_status & RX_BCAST_CHG_MSK)
2865 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2866 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2867 CHL_INT0_SL_RX_BCST_ACK_MSK);
2868 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2869 }
2870
2871 static const struct hisi_sas_hw_error port_ecc_axi_error[] = {
2872 {
2873 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF),
2874 .msg = "dmac_tx_ecc_bad_err",
2875 },
2876 {
2877 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF),
2878 .msg = "dmac_rx_ecc_bad_err",
2879 },
2880 {
2881 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
2882 .msg = "dma_tx_axi_wr_err",
2883 },
2884 {
2885 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
2886 .msg = "dma_tx_axi_rd_err",
2887 },
2888 {
2889 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
2890 .msg = "dma_rx_axi_wr_err",
2891 },
2892 {
2893 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
2894 .msg = "dma_rx_axi_rd_err",
2895 },
2896 };
2897
2898 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2899 {
2900 struct hisi_hba *hisi_hba = p;
2901 struct device *dev = hisi_hba->dev;
2902 u32 ent_msk, ent_tmp, irq_msk;
2903 int phy_no = 0;
2904
2905 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2906 ent_tmp = ent_msk;
2907 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2908 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2909
2910 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2911 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2912
2913 while (irq_msk) {
2914 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2915 CHL_INT0);
2916 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2917 CHL_INT1);
2918 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2919 CHL_INT2);
2920
2921 if ((irq_msk & (1 << phy_no)) && irq_value1) {
2922 int i;
2923
2924 for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) {
2925 const struct hisi_sas_hw_error *error =
2926 &port_ecc_axi_error[i];
2927
2928 if (!(irq_value1 & error->irq_msk))
2929 continue;
2930
2931 dev_warn(dev, "%s error (phy%d 0x%x) found!\n",
2932 error->msg, phy_no, irq_value1);
2933 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2934 }
2935
2936 hisi_sas_phy_write32(hisi_hba, phy_no,
2937 CHL_INT1, irq_value1);
2938 }
2939
2940 if ((irq_msk & (1 << phy_no)) && irq_value2) {
2941 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2942
2943 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
2944 dev_warn(dev, "phy%d identify timeout\n",
2945 phy_no);
2946 hisi_sas_notify_phy_event(phy,
2947 HISI_PHYE_LINK_RESET);
2948 }
2949
2950 hisi_sas_phy_write32(hisi_hba, phy_no,
2951 CHL_INT2, irq_value2);
2952 }
2953
2954 if ((irq_msk & (1 << phy_no)) && irq_value0) {
2955 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2956 phy_bcast_v2_hw(phy_no, hisi_hba);
2957
2958 hisi_sas_phy_write32(hisi_hba, phy_no,
2959 CHL_INT0, irq_value0
2960 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2961 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2962 & (~CHL_INT0_NOT_RDY_MSK));
2963 }
2964 irq_msk &= ~(1 << phy_no);
2965 phy_no++;
2966 }
2967
2968 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2969
2970 return IRQ_HANDLED;
2971 }
2972
2973 static void
2974 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2975 {
2976 struct device *dev = hisi_hba->dev;
2977 const struct hisi_sas_hw_error *ecc_error;
2978 u32 val;
2979 int i;
2980
2981 for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2982 ecc_error = &one_bit_ecc_errors[i];
2983 if (irq_value & ecc_error->irq_msk) {
2984 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2985 val &= ecc_error->msk;
2986 val >>= ecc_error->shift;
2987 dev_warn(dev, ecc_error->msg, val);
2988 }
2989 }
2990 }
2991
2992 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2993 u32 irq_value)
2994 {
2995 struct device *dev = hisi_hba->dev;
2996 const struct hisi_sas_hw_error *ecc_error;
2997 u32 val;
2998 int i;
2999
3000 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
3001 ecc_error = &multi_bit_ecc_errors[i];
3002 if (irq_value & ecc_error->irq_msk) {
3003 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
3004 val &= ecc_error->msk;
3005 val >>= ecc_error->shift;
3006 dev_err(dev, ecc_error->msg, irq_value, val);
3007 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3008 }
3009 }
3010
3011 return;
3012 }
3013
3014 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
3015 {
3016 struct hisi_hba *hisi_hba = p;
3017 u32 irq_value, irq_msk;
3018
3019 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
3020 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
3021
3022 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
3023 if (irq_value) {
3024 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3025 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3026 }
3027
3028 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
3029 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
3030
3031 return IRQ_HANDLED;
3032 }
3033
3034 static const struct hisi_sas_hw_error axi_error[] = {
3035 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
3036 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
3037 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
3038 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
3039 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
3040 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
3041 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
3042 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
3043 {},
3044 };
3045
3046 static const struct hisi_sas_hw_error fifo_error[] = {
3047 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
3048 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
3049 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
3050 { .msk = BIT(11), .msg = "CMDP_FIFO" },
3051 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
3052 {},
3053 };
3054
3055 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
3056 {
3057 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
3058 .msg = "write pointer and depth",
3059 },
3060 {
3061 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
3062 .msg = "iptt no match slot",
3063 },
3064 {
3065 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
3066 .msg = "read pointer and depth",
3067 },
3068 {
3069 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
3070 .reg = HGC_AXI_FIFO_ERR_INFO,
3071 .sub = axi_error,
3072 },
3073 {
3074 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
3075 .reg = HGC_AXI_FIFO_ERR_INFO,
3076 .sub = fifo_error,
3077 },
3078 {
3079 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
3080 .msg = "LM add/fetch list",
3081 },
3082 {
3083 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
3084 .msg = "SAS_HGC_ABT fetch LM list",
3085 },
3086 };
3087
3088 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
3089 {
3090 struct hisi_hba *hisi_hba = p;
3091 u32 irq_value, irq_msk, err_value;
3092 struct device *dev = hisi_hba->dev;
3093 const struct hisi_sas_hw_error *axi_error;
3094 int i;
3095
3096 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3097 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3098
3099 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3100
3101 for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3102 axi_error = &fatal_axi_errors[i];
3103 if (!(irq_value & axi_error->irq_msk))
3104 continue;
3105
3106 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3107 1 << axi_error->shift);
3108 if (axi_error->sub) {
3109 const struct hisi_sas_hw_error *sub = axi_error->sub;
3110
3111 err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3112 for (; sub->msk || sub->msg; sub++) {
3113 if (!(err_value & sub->msk))
3114 continue;
3115 dev_err(dev, "%s (0x%x) found!\n",
3116 sub->msg, irq_value);
3117 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3118 }
3119 } else {
3120 dev_err(dev, "%s (0x%x) found!\n",
3121 axi_error->msg, irq_value);
3122 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3123 }
3124 }
3125
3126 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3127 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3128 u32 dev_id = reg_val & ITCT_DEV_MSK;
3129 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3130
3131 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3132 dev_dbg(dev, "clear ITCT ok\n");
3133 complete(sas_dev->completion);
3134 }
3135
3136 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3137 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3138
3139 return IRQ_HANDLED;
3140 }
3141
3142 static void cq_tasklet_v2_hw(unsigned long val)
3143 {
3144 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3145 struct hisi_hba *hisi_hba = cq->hisi_hba;
3146 struct hisi_sas_slot *slot;
3147 struct hisi_sas_itct *itct;
3148 struct hisi_sas_complete_v2_hdr *complete_queue;
3149 u32 rd_point = cq->rd_point, wr_point, dev_id;
3150 int queue = cq->id;
3151 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
3152
3153 if (unlikely(hisi_hba->reject_stp_links_msk))
3154 phys_try_accept_stp_links_v2_hw(hisi_hba);
3155
3156 complete_queue = hisi_hba->complete_hdr[queue];
3157
3158 spin_lock(&dq->lock);
3159 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3160 (0x14 * queue));
3161
3162 while (rd_point != wr_point) {
3163 struct hisi_sas_complete_v2_hdr *complete_hdr;
3164 int iptt;
3165
3166 complete_hdr = &complete_queue[rd_point];
3167
3168 /* Check for NCQ completion */
3169 if (complete_hdr->act) {
3170 u32 act_tmp = complete_hdr->act;
3171 int ncq_tag_count = ffs(act_tmp);
3172
3173 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3174 CMPLT_HDR_DEV_ID_OFF;
3175 itct = &hisi_hba->itct[dev_id];
3176
3177 /* The NCQ tags are held in the itct header */
3178 while (ncq_tag_count) {
3179 __le64 *ncq_tag = &itct->qw4_15[0];
3180
3181 ncq_tag_count -= 1;
3182 iptt = (ncq_tag[ncq_tag_count / 5]
3183 >> (ncq_tag_count % 5) * 12) & 0xfff;
3184
3185 slot = &hisi_hba->slot_info[iptt];
3186 slot->cmplt_queue_slot = rd_point;
3187 slot->cmplt_queue = queue;
3188 slot_complete_v2_hw(hisi_hba, slot);
3189
3190 act_tmp &= ~(1 << ncq_tag_count);
3191 ncq_tag_count = ffs(act_tmp);
3192 }
3193 } else {
3194 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3195 slot = &hisi_hba->slot_info[iptt];
3196 slot->cmplt_queue_slot = rd_point;
3197 slot->cmplt_queue = queue;
3198 slot_complete_v2_hw(hisi_hba, slot);
3199 }
3200
3201 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3202 rd_point = 0;
3203 }
3204
3205 /* update rd_point */
3206 cq->rd_point = rd_point;
3207 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3208 spin_unlock(&dq->lock);
3209 }
3210
3211 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3212 {
3213 struct hisi_sas_cq *cq = p;
3214 struct hisi_hba *hisi_hba = cq->hisi_hba;
3215 int queue = cq->id;
3216
3217 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3218
3219 tasklet_schedule(&cq->tasklet);
3220
3221 return IRQ_HANDLED;
3222 }
3223
3224 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3225 {
3226 struct hisi_sas_phy *phy = p;
3227 struct hisi_hba *hisi_hba = phy->hisi_hba;
3228 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3229 struct device *dev = hisi_hba->dev;
3230 struct hisi_sas_initial_fis *initial_fis;
3231 struct dev_to_host_fis *fis;
3232 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3233 irqreturn_t res = IRQ_HANDLED;
3234 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3235 int phy_no, offset;
3236
3237 phy_no = sas_phy->id;
3238 initial_fis = &hisi_hba->initial_fis[phy_no];
3239 fis = &initial_fis->fis;
3240
3241 offset = 4 * (phy_no / 4);
3242 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3243 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3244 ent_msk | 1 << ((phy_no % 4) * 8));
3245
3246 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3247 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3248 (phy_no % 4)));
3249 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3250 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3251 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3252 res = IRQ_NONE;
3253 goto end;
3254 }
3255
3256 /* check ERR bit of Status Register */
3257 if (fis->status & ATA_ERR) {
3258 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3259 fis->status);
3260 disable_phy_v2_hw(hisi_hba, phy_no);
3261 enable_phy_v2_hw(hisi_hba, phy_no);
3262 res = IRQ_NONE;
3263 goto end;
3264 }
3265
3266 if (unlikely(phy_no == 8)) {
3267 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3268
3269 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3270 PORT_STATE_PHY8_PORT_NUM_OFF;
3271 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3272 PORT_STATE_PHY8_CONN_RATE_OFF;
3273 } else {
3274 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3275 port_id = (port_id >> (4 * phy_no)) & 0xf;
3276 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3277 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3278 }
3279
3280 if (port_id == 0xf) {
3281 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3282 res = IRQ_NONE;
3283 goto end;
3284 }
3285
3286 sas_phy->linkrate = link_rate;
3287 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3288 HARD_PHY_LINKRATE);
3289 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3290 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3291
3292 sas_phy->oob_mode = SATA_OOB_MODE;
3293 /* Make up some unique SAS address */
3294 attached_sas_addr[0] = 0x50;
3295 attached_sas_addr[7] = phy_no;
3296 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3297 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3298 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3299 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3300 phy->port_id = port_id;
3301 phy->phy_type |= PORT_TYPE_SATA;
3302 phy->phy_attached = 1;
3303 phy->identify.device_type = SAS_SATA_DEV;
3304 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3305 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3306 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
3307
3308 end:
3309 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3310 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3311
3312 return res;
3313 }
3314
3315 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3316 int_phy_updown_v2_hw,
3317 int_chnl_int_v2_hw,
3318 };
3319
3320 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3321 fatal_ecc_int_v2_hw,
3322 fatal_axi_int_v2_hw
3323 };
3324
3325 /**
3326 * There is a limitation in the hip06 chipset that we need
3327 * to map in all mbigen interrupts, even if they are not used.
3328 */
3329 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3330 {
3331 struct platform_device *pdev = hisi_hba->platform_dev;
3332 struct device *dev = &pdev->dev;
3333 int irq, rc, irq_map[128];
3334 int i, phy_no, fatal_no, queue_no, k;
3335
3336 for (i = 0; i < 128; i++)
3337 irq_map[i] = platform_get_irq(pdev, i);
3338
3339 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3340 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3341 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3342 DRV_NAME " phy", hisi_hba);
3343 if (rc) {
3344 dev_err(dev, "irq init: could not request "
3345 "phy interrupt %d, rc=%d\n",
3346 irq, rc);
3347 rc = -ENOENT;
3348 goto free_phy_int_irqs;
3349 }
3350 }
3351
3352 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3353 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3354
3355 irq = irq_map[phy_no + 72];
3356 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3357 DRV_NAME " sata", phy);
3358 if (rc) {
3359 dev_err(dev, "irq init: could not request "
3360 "sata interrupt %d, rc=%d\n",
3361 irq, rc);
3362 rc = -ENOENT;
3363 goto free_sata_int_irqs;
3364 }
3365 }
3366
3367 for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3368 irq = irq_map[fatal_no + 81];
3369 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3370 DRV_NAME " fatal", hisi_hba);
3371 if (rc) {
3372 dev_err(dev,
3373 "irq init: could not request fatal interrupt %d, rc=%d\n",
3374 irq, rc);
3375 rc = -ENOENT;
3376 goto free_fatal_int_irqs;
3377 }
3378 }
3379
3380 for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3381 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3382 struct tasklet_struct *t = &cq->tasklet;
3383
3384 irq = irq_map[queue_no + 96];
3385 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3386 DRV_NAME " cq", cq);
3387 if (rc) {
3388 dev_err(dev,
3389 "irq init: could not request cq interrupt %d, rc=%d\n",
3390 irq, rc);
3391 rc = -ENOENT;
3392 goto free_cq_int_irqs;
3393 }
3394 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3395 }
3396
3397 return 0;
3398
3399 free_cq_int_irqs:
3400 for (k = 0; k < queue_no; k++) {
3401 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3402
3403 free_irq(irq_map[k + 96], cq);
3404 tasklet_kill(&cq->tasklet);
3405 }
3406 free_fatal_int_irqs:
3407 for (k = 0; k < fatal_no; k++)
3408 free_irq(irq_map[k + 81], hisi_hba);
3409 free_sata_int_irqs:
3410 for (k = 0; k < phy_no; k++) {
3411 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3412
3413 free_irq(irq_map[k + 72], phy);
3414 }
3415 free_phy_int_irqs:
3416 for (k = 0; k < i; k++)
3417 free_irq(irq_map[k + 1], hisi_hba);
3418 return rc;
3419 }
3420
3421 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3422 {
3423 int rc;
3424
3425 memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3426
3427 rc = hw_init_v2_hw(hisi_hba);
3428 if (rc)
3429 return rc;
3430
3431 rc = interrupt_init_v2_hw(hisi_hba);
3432 if (rc)
3433 return rc;
3434
3435 return 0;
3436 }
3437
3438 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3439 {
3440 struct platform_device *pdev = hisi_hba->platform_dev;
3441 int i;
3442
3443 for (i = 0; i < hisi_hba->queue_count; i++)
3444 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3445
3446 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3447 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3448 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3449 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3450
3451 for (i = 0; i < hisi_hba->n_phy; i++) {
3452 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3453 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3454 }
3455
3456 for (i = 0; i < 128; i++)
3457 synchronize_irq(platform_get_irq(pdev, i));
3458 }
3459
3460
3461 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3462 {
3463 return hisi_sas_read32(hisi_hba, PHY_STATE);
3464 }
3465
3466 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3467 {
3468 struct device *dev = hisi_hba->dev;
3469 int rc, cnt;
3470
3471 interrupt_disable_v2_hw(hisi_hba);
3472 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3473 hisi_sas_kill_tasklets(hisi_hba);
3474
3475 hisi_sas_stop_phys(hisi_hba);
3476
3477 mdelay(10);
3478
3479 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3480
3481 /* wait until bus idle */
3482 cnt = 0;
3483 while (1) {
3484 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3485 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3486
3487 if (status == 0x3)
3488 break;
3489
3490 udelay(10);
3491 if (cnt++ > 10) {
3492 dev_err(dev, "wait axi bus state to idle timeout!\n");
3493 return -1;
3494 }
3495 }
3496
3497 hisi_sas_init_mem(hisi_hba);
3498
3499 rc = hw_init_v2_hw(hisi_hba);
3500 if (rc)
3501 return rc;
3502
3503 phys_reject_stp_links_v2_hw(hisi_hba);
3504
3505 return 0;
3506 }
3507
3508 static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
3509 u8 reg_index, u8 reg_count, u8 *write_data)
3510 {
3511 struct device *dev = hisi_hba->dev;
3512 int phy_no, count;
3513
3514 if (!hisi_hba->sgpio_regs)
3515 return -EOPNOTSUPP;
3516
3517 switch (reg_type) {
3518 case SAS_GPIO_REG_TX:
3519 count = reg_count * 4;
3520 count = min(count, hisi_hba->n_phy);
3521
3522 for (phy_no = 0; phy_no < count; phy_no++) {
3523 /*
3524 * GPIO_TX[n] register has the highest numbered drive
3525 * of the four in the first byte and the lowest
3526 * numbered drive in the fourth byte.
3527 * See SFF-8485 Rev. 0.7 Table 24.
3528 */
3529 void __iomem *reg_addr = hisi_hba->sgpio_regs +
3530 reg_index * 4 + phy_no;
3531 int data_idx = phy_no + 3 - (phy_no % 4) * 2;
3532
3533 writeb(write_data[data_idx], reg_addr);
3534 }
3535
3536 break;
3537 default:
3538 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3539 reg_type);
3540 return -EINVAL;
3541 }
3542
3543 return 0;
3544 }
3545
3546 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3547 .hw_init = hisi_sas_v2_init,
3548 .setup_itct = setup_itct_v2_hw,
3549 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3550 .alloc_dev = alloc_dev_quirk_v2_hw,
3551 .sl_notify = sl_notify_v2_hw,
3552 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3553 .clear_itct = clear_itct_v2_hw,
3554 .free_device = free_device_v2_hw,
3555 .prep_smp = prep_smp_v2_hw,
3556 .prep_ssp = prep_ssp_v2_hw,
3557 .prep_stp = prep_ata_v2_hw,
3558 .prep_abort = prep_abort_v2_hw,
3559 .get_free_slot = get_free_slot_v2_hw,
3560 .start_delivery = start_delivery_v2_hw,
3561 .slot_complete = slot_complete_v2_hw,
3562 .phys_init = phys_init_v2_hw,
3563 .phy_start = start_phy_v2_hw,
3564 .phy_disable = disable_phy_v2_hw,
3565 .phy_hard_reset = phy_hard_reset_v2_hw,
3566 .get_events = phy_get_events_v2_hw,
3567 .phy_set_linkrate = phy_set_linkrate_v2_hw,
3568 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3569 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3570 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3571 .soft_reset = soft_reset_v2_hw,
3572 .get_phys_state = get_phys_state_v2_hw,
3573 .write_gpio = write_gpio_v2_hw,
3574 };
3575
3576 static int hisi_sas_v2_probe(struct platform_device *pdev)
3577 {
3578 /*
3579 * Check if we should defer the probe before we probe the
3580 * upper layer, as it's hard to defer later on.
3581 */
3582 int ret = platform_get_irq(pdev, 0);
3583
3584 if (ret < 0) {
3585 if (ret != -EPROBE_DEFER)
3586 dev_err(&pdev->dev, "cannot obtain irq\n");
3587 return ret;
3588 }
3589
3590 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3591 }
3592
3593 static int hisi_sas_v2_remove(struct platform_device *pdev)
3594 {
3595 struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3596 struct hisi_hba *hisi_hba = sha->lldd_ha;
3597
3598 if (timer_pending(&hisi_hba->timer))
3599 del_timer(&hisi_hba->timer);
3600
3601 hisi_sas_kill_tasklets(hisi_hba);
3602
3603 return hisi_sas_remove(pdev);
3604 }
3605
3606 static const struct of_device_id sas_v2_of_match[] = {
3607 { .compatible = "hisilicon,hip06-sas-v2",},
3608 { .compatible = "hisilicon,hip07-sas-v2",},
3609 {},
3610 };
3611 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3612
3613 static const struct acpi_device_id sas_v2_acpi_match[] = {
3614 { "HISI0162", 0 },
3615 { }
3616 };
3617
3618 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3619
3620 static struct platform_driver hisi_sas_v2_driver = {
3621 .probe = hisi_sas_v2_probe,
3622 .remove = hisi_sas_v2_remove,
3623 .driver = {
3624 .name = DRV_NAME,
3625 .of_match_table = sas_v2_of_match,
3626 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3627 },
3628 };
3629
3630 module_platform_driver(hisi_sas_v2_driver);
3631
3632 MODULE_LICENSE("GPL");
3633 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3634 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3635 MODULE_ALIAS("platform:" DRV_NAME);
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