2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
13 #define DRV_NAME "hisi_sas_v2_hw"
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define CQE_SEND_CNT 0x248
148 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
149 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
150 #define DLVRY_Q_0_DEPTH 0x268
151 #define DLVRY_Q_0_WR_PTR 0x26c
152 #define DLVRY_Q_0_RD_PTR 0x270
153 #define HYPER_STREAM_ID_EN_CFG 0xc80
154 #define OQ0_INT_SRC_MSK 0xc90
155 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
156 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
157 #define COMPL_Q_0_DEPTH 0x4e8
158 #define COMPL_Q_0_WR_PTR 0x4ec
159 #define COMPL_Q_0_RD_PTR 0x4f0
160 #define HGC_RXM_DFX_STATUS14 0xae8
161 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
162 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
163 HGC_RXM_DFX_STATUS14_MEM0_OFF)
164 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
165 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
166 HGC_RXM_DFX_STATUS14_MEM1_OFF)
167 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
168 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
169 HGC_RXM_DFX_STATUS14_MEM2_OFF)
170 #define HGC_RXM_DFX_STATUS15 0xaec
171 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
172 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
173 HGC_RXM_DFX_STATUS15_MEM3_OFF)
174 /* phy registers need init */
175 #define PORT_BASE (0x2000)
177 #define PHY_CFG (PORT_BASE + 0x0)
178 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
179 #define PHY_CFG_ENA_OFF 0
180 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
181 #define PHY_CFG_DC_OPT_OFF 2
182 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
183 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
184 #define PROG_PHY_LINK_RATE_MAX_OFF 0
185 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
186 #define PHY_CTRL (PORT_BASE + 0x14)
187 #define PHY_CTRL_RESET_OFF 0
188 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
189 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
190 #define SL_CFG (PORT_BASE + 0x84)
191 #define PHY_PCN (PORT_BASE + 0x44)
192 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
193 #define SL_CONTROL (PORT_BASE + 0x94)
194 #define SL_CONTROL_NOTIFY_EN_OFF 0
195 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
196 #define SL_CONTROL_CTA_OFF 17
197 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
198 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
199 #define RX_BCAST_CHG_OFF 1
200 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
201 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
202 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
203 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
204 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
205 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
206 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
207 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
208 #define TXID_AUTO (PORT_BASE + 0xb8)
209 #define TXID_AUTO_CT3_OFF 1
210 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
211 #define TXID_AUTO_CTB_OFF 11
212 #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
213 #define TX_HARDRST_OFF 2
214 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
215 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
216 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
217 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
218 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
219 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
220 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
221 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
222 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
223 #define CON_CONTROL (PORT_BASE + 0x118)
224 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
225 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
226 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
227 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
228 #define CHL_INT0 (PORT_BASE + 0x1b4)
229 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
230 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
231 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
232 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
233 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
234 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
235 #define CHL_INT0_NOT_RDY_OFF 4
236 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
237 #define CHL_INT0_PHY_RDY_OFF 5
238 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
239 #define CHL_INT1 (PORT_BASE + 0x1b8)
240 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
241 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
242 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
243 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
244 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
245 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
246 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
247 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
248 #define CHL_INT2 (PORT_BASE + 0x1bc)
249 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
250 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
251 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
252 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
253 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
254 #define DMA_TX_DFX0 (PORT_BASE + 0x200)
255 #define DMA_TX_DFX1 (PORT_BASE + 0x204)
256 #define DMA_TX_DFX1_IPTT_OFF 0
257 #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
258 #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
259 #define PORT_DFX0 (PORT_BASE + 0x258)
260 #define LINK_DFX2 (PORT_BASE + 0X264)
261 #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
262 #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
263 #define LINK_DFX2_SEND_HOLD_STS_OFF 10
264 #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
265 #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
266 #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
267 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
268 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
269 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
270 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
271 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
272 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
273 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
274 #define DMA_TX_STATUS_BUSY_OFF 0
275 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
276 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
277 #define DMA_RX_STATUS_BUSY_OFF 0
278 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
280 #define AXI_CFG (0x5100)
281 #define AM_CFG_MAX_TRANS (0x5010)
282 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
284 #define AXI_MASTER_CFG_BASE (0x5000)
285 #define AM_CTRL_GLOBAL (0x0)
286 #define AM_CURR_TRANS_RETURN (0x150)
288 /* HW dma structures */
289 /* Delivery queue header */
291 #define CMD_HDR_ABORT_FLAG_OFF 0
292 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
293 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
294 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
295 #define CMD_HDR_RESP_REPORT_OFF 5
296 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
297 #define CMD_HDR_TLR_CTRL_OFF 6
298 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
299 #define CMD_HDR_PHY_ID_OFF 8
300 #define CMD_HDR_PHY_ID_MSK (0x1ff << CMD_HDR_PHY_ID_OFF)
301 #define CMD_HDR_FORCE_PHY_OFF 17
302 #define CMD_HDR_FORCE_PHY_MSK (0x1 << CMD_HDR_FORCE_PHY_OFF)
303 #define CMD_HDR_PORT_OFF 18
304 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
305 #define CMD_HDR_PRIORITY_OFF 27
306 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
307 #define CMD_HDR_CMD_OFF 29
308 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
310 #define CMD_HDR_DIR_OFF 5
311 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
312 #define CMD_HDR_RESET_OFF 7
313 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
314 #define CMD_HDR_VDTL_OFF 10
315 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
316 #define CMD_HDR_FRAME_TYPE_OFF 11
317 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
318 #define CMD_HDR_DEV_ID_OFF 16
319 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
321 #define CMD_HDR_CFL_OFF 0
322 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
323 #define CMD_HDR_NCQ_TAG_OFF 10
324 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
325 #define CMD_HDR_MRFL_OFF 15
326 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
327 #define CMD_HDR_SG_MOD_OFF 24
328 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
329 #define CMD_HDR_FIRST_BURST_OFF 26
330 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
332 #define CMD_HDR_IPTT_OFF 0
333 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
335 #define CMD_HDR_DIF_SGL_LEN_OFF 0
336 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
337 #define CMD_HDR_DATA_SGL_LEN_OFF 16
338 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
339 #define CMD_HDR_ABORT_IPTT_OFF 16
340 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
342 /* Completion header */
344 #define CMPLT_HDR_ERR_PHASE_OFF 2
345 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
346 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
347 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
348 #define CMPLT_HDR_ERX_OFF 12
349 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
350 #define CMPLT_HDR_ABORT_STAT_OFF 13
351 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
353 #define STAT_IO_NOT_VALID 0x1
354 #define STAT_IO_NO_DEVICE 0x2
355 #define STAT_IO_COMPLETE 0x3
356 #define STAT_IO_ABORTED 0x4
358 #define CMPLT_HDR_IPTT_OFF 0
359 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
360 #define CMPLT_HDR_DEV_ID_OFF 16
361 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
365 #define ITCT_HDR_DEV_TYPE_OFF 0
366 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
367 #define ITCT_HDR_VALID_OFF 2
368 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
369 #define ITCT_HDR_MCR_OFF 5
370 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
371 #define ITCT_HDR_VLN_OFF 9
372 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
373 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
374 #define ITCT_HDR_SMP_TIMEOUT_8US 1
375 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
377 #define ITCT_HDR_AWT_CONTINUE_OFF 25
378 #define ITCT_HDR_PORT_ID_OFF 28
379 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
381 #define ITCT_HDR_INLT_OFF 0
382 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
383 #define ITCT_HDR_BITLT_OFF 16
384 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
385 #define ITCT_HDR_MCTLT_OFF 32
386 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
387 #define ITCT_HDR_RTOLT_OFF 48
388 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
390 #define HISI_SAS_FATAL_INT_NR 2
392 struct hisi_sas_complete_v2_hdr
{
399 struct hisi_sas_err_record_v2
{
401 __le32 trans_tx_fail_type
;
404 __le32 trans_rx_fail_type
;
407 __le16 dma_tx_err_type
;
408 __le16 sipc_rx_err_type
;
411 __le32 dma_rx_err_type
;
414 struct signal_attenuation_s
{
420 struct sig_atten_lu_s
{
421 const struct signal_attenuation_s
*att
;
425 static const struct hisi_sas_hw_error one_bit_ecc_errors
[] = {
427 .irq_msk
= BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF
),
428 .msk
= HGC_DQE_ECC_1B_ADDR_MSK
,
429 .shift
= HGC_DQE_ECC_1B_ADDR_OFF
,
430 .msg
= "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
431 .reg
= HGC_DQE_ECC_ADDR
,
434 .irq_msk
= BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF
),
435 .msk
= HGC_IOST_ECC_1B_ADDR_MSK
,
436 .shift
= HGC_IOST_ECC_1B_ADDR_OFF
,
437 .msg
= "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
438 .reg
= HGC_IOST_ECC_ADDR
,
441 .irq_msk
= BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF
),
442 .msk
= HGC_ITCT_ECC_1B_ADDR_MSK
,
443 .shift
= HGC_ITCT_ECC_1B_ADDR_OFF
,
444 .msg
= "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
445 .reg
= HGC_ITCT_ECC_ADDR
,
448 .irq_msk
= BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF
),
449 .msk
= HGC_LM_DFX_STATUS2_IOSTLIST_MSK
,
450 .shift
= HGC_LM_DFX_STATUS2_IOSTLIST_OFF
,
451 .msg
= "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
452 .reg
= HGC_LM_DFX_STATUS2
,
455 .irq_msk
= BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF
),
456 .msk
= HGC_LM_DFX_STATUS2_ITCTLIST_MSK
,
457 .shift
= HGC_LM_DFX_STATUS2_ITCTLIST_OFF
,
458 .msg
= "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
459 .reg
= HGC_LM_DFX_STATUS2
,
462 .irq_msk
= BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF
),
463 .msk
= HGC_CQE_ECC_1B_ADDR_MSK
,
464 .shift
= HGC_CQE_ECC_1B_ADDR_OFF
,
465 .msg
= "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
466 .reg
= HGC_CQE_ECC_ADDR
,
469 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF
),
470 .msk
= HGC_RXM_DFX_STATUS14_MEM0_MSK
,
471 .shift
= HGC_RXM_DFX_STATUS14_MEM0_OFF
,
472 .msg
= "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
473 .reg
= HGC_RXM_DFX_STATUS14
,
476 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF
),
477 .msk
= HGC_RXM_DFX_STATUS14_MEM1_MSK
,
478 .shift
= HGC_RXM_DFX_STATUS14_MEM1_OFF
,
479 .msg
= "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
480 .reg
= HGC_RXM_DFX_STATUS14
,
483 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF
),
484 .msk
= HGC_RXM_DFX_STATUS14_MEM2_MSK
,
485 .shift
= HGC_RXM_DFX_STATUS14_MEM2_OFF
,
486 .msg
= "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
487 .reg
= HGC_RXM_DFX_STATUS14
,
490 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF
),
491 .msk
= HGC_RXM_DFX_STATUS15_MEM3_MSK
,
492 .shift
= HGC_RXM_DFX_STATUS15_MEM3_OFF
,
493 .msg
= "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
494 .reg
= HGC_RXM_DFX_STATUS15
,
498 static const struct hisi_sas_hw_error multi_bit_ecc_errors
[] = {
500 .irq_msk
= BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF
),
501 .msk
= HGC_DQE_ECC_MB_ADDR_MSK
,
502 .shift
= HGC_DQE_ECC_MB_ADDR_OFF
,
503 .msg
= "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
504 .reg
= HGC_DQE_ECC_ADDR
,
507 .irq_msk
= BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF
),
508 .msk
= HGC_IOST_ECC_MB_ADDR_MSK
,
509 .shift
= HGC_IOST_ECC_MB_ADDR_OFF
,
510 .msg
= "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
511 .reg
= HGC_IOST_ECC_ADDR
,
514 .irq_msk
= BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF
),
515 .msk
= HGC_ITCT_ECC_MB_ADDR_MSK
,
516 .shift
= HGC_ITCT_ECC_MB_ADDR_OFF
,
517 .msg
= "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
518 .reg
= HGC_ITCT_ECC_ADDR
,
521 .irq_msk
= BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF
),
522 .msk
= HGC_LM_DFX_STATUS2_IOSTLIST_MSK
,
523 .shift
= HGC_LM_DFX_STATUS2_IOSTLIST_OFF
,
524 .msg
= "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
525 .reg
= HGC_LM_DFX_STATUS2
,
528 .irq_msk
= BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF
),
529 .msk
= HGC_LM_DFX_STATUS2_ITCTLIST_MSK
,
530 .shift
= HGC_LM_DFX_STATUS2_ITCTLIST_OFF
,
531 .msg
= "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
532 .reg
= HGC_LM_DFX_STATUS2
,
535 .irq_msk
= BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF
),
536 .msk
= HGC_CQE_ECC_MB_ADDR_MSK
,
537 .shift
= HGC_CQE_ECC_MB_ADDR_OFF
,
538 .msg
= "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
539 .reg
= HGC_CQE_ECC_ADDR
,
542 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF
),
543 .msk
= HGC_RXM_DFX_STATUS14_MEM0_MSK
,
544 .shift
= HGC_RXM_DFX_STATUS14_MEM0_OFF
,
545 .msg
= "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
546 .reg
= HGC_RXM_DFX_STATUS14
,
549 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF
),
550 .msk
= HGC_RXM_DFX_STATUS14_MEM1_MSK
,
551 .shift
= HGC_RXM_DFX_STATUS14_MEM1_OFF
,
552 .msg
= "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
553 .reg
= HGC_RXM_DFX_STATUS14
,
556 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF
),
557 .msk
= HGC_RXM_DFX_STATUS14_MEM2_MSK
,
558 .shift
= HGC_RXM_DFX_STATUS14_MEM2_OFF
,
559 .msg
= "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
560 .reg
= HGC_RXM_DFX_STATUS14
,
563 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF
),
564 .msk
= HGC_RXM_DFX_STATUS15_MEM3_MSK
,
565 .shift
= HGC_RXM_DFX_STATUS15_MEM3_OFF
,
566 .msg
= "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
567 .reg
= HGC_RXM_DFX_STATUS15
,
572 HISI_SAS_PHY_PHY_UPDOWN
,
573 HISI_SAS_PHY_CHNL_INT
,
578 TRANS_TX_FAIL_BASE
= 0x0, /* dw0 */
579 TRANS_RX_FAIL_BASE
= 0x20, /* dw1 */
580 DMA_TX_ERR_BASE
= 0x40, /* dw2 bit 15-0 */
581 SIPC_RX_ERR_BASE
= 0x50, /* dw2 bit 31-16*/
582 DMA_RX_ERR_BASE
= 0x60, /* dw3 */
585 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
= TRANS_TX_FAIL_BASE
, /* 0x0 */
586 TRANS_TX_ERR_PHY_NOT_ENABLE
, /* 0x1 */
587 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
, /* 0x2 */
588 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
, /* 0x3 */
589 TRANS_TX_OPEN_CNX_ERR_BY_OTHER
, /* 0x4 */
591 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
, /* 0x6 */
592 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
, /* 0x7 */
593 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
, /* 0x8 */
594 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
, /* 0x9 */
595 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
, /* 0xa */
596 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
, /* 0xb */
597 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
, /* 0xc */
598 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
, /* 0xd */
599 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
, /* 0xe */
600 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
, /* 0xf */
601 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
, /* 0x10 */
602 TRANS_TX_ERR_FRAME_TXED
, /* 0x11 */
603 TRANS_TX_ERR_WITH_BREAK_TIMEOUT
, /* 0x12 */
604 TRANS_TX_ERR_WITH_BREAK_REQUEST
, /* 0x13 */
605 TRANS_TX_ERR_WITH_BREAK_RECEVIED
, /* 0x14 */
606 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
, /* 0x15 */
607 TRANS_TX_ERR_WITH_CLOSE_NORMAL
, /* 0x16 for ssp*/
608 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
, /* 0x17 */
609 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
, /* 0x18 */
610 TRANS_TX_ERR_WITH_CLOSE_COMINIT
, /* 0x19 */
611 TRANS_TX_ERR_WITH_NAK_RECEVIED
, /* 0x1a for ssp*/
612 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
, /* 0x1b for ssp*/
613 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
614 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
, /* 0x1c for ssp */
615 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
616 TRANS_TX_ERR_WITH_IPTT_CONFLICT
, /* 0x1d for ssp/smp */
617 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS
, /* 0x1e */
618 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
619 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
, /* 0x1f for sata/stp */
622 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
= TRANS_RX_FAIL_BASE
, /* 0x20 */
623 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
, /* 0x21 for sata/stp */
624 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
, /* 0x22 for ssp/smp */
625 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
626 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
, /* 0x23 for sata/stp */
627 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
, /* 0x24 for sata/stp */
628 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
, /* 0x25 for smp */
629 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
630 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
, /* 0x26 for sata/stp*/
631 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
, /* 0x27 */
632 TRANS_RX_ERR_WITH_BREAK_TIMEOUT
, /* 0x28 */
633 TRANS_RX_ERR_WITH_BREAK_REQUEST
, /* 0x29 */
634 TRANS_RX_ERR_WITH_BREAK_RECEVIED
, /* 0x2a */
635 RESERVED1
, /* 0x2b */
636 TRANS_RX_ERR_WITH_CLOSE_NORMAL
, /* 0x2c */
637 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
, /* 0x2d */
638 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
, /* 0x2e */
639 TRANS_RX_ERR_WITH_CLOSE_COMINIT
, /* 0x2f */
640 TRANS_RX_ERR_WITH_DATA_LEN0
, /* 0x30 for ssp/smp */
641 TRANS_RX_ERR_WITH_BAD_HASH
, /* 0x31 for ssp */
642 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
643 TRANS_RX_XRDY_WLEN_ZERO_ERR
, /* 0x32 for ssp*/
644 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
645 TRANS_RX_SSP_FRM_LEN_ERR
, /* 0x33 for ssp */
646 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
647 RESERVED2
, /* 0x34 */
648 RESERVED3
, /* 0x35 */
649 RESERVED4
, /* 0x36 */
650 RESERVED5
, /* 0x37 */
651 TRANS_RX_ERR_WITH_BAD_FRM_TYPE
, /* 0x38 */
652 TRANS_RX_SMP_FRM_LEN_ERR
, /* 0x39 */
653 TRANS_RX_SMP_RESP_TIMEOUT_ERR
, /* 0x3a */
654 RESERVED6
, /* 0x3b */
655 RESERVED7
, /* 0x3c */
656 RESERVED8
, /* 0x3d */
657 RESERVED9
, /* 0x3e */
658 TRANS_RX_R_ERR
, /* 0x3f */
661 DMA_TX_DIF_CRC_ERR
= DMA_TX_ERR_BASE
, /* 0x40 */
662 DMA_TX_DIF_APP_ERR
, /* 0x41 */
663 DMA_TX_DIF_RPP_ERR
, /* 0x42 */
664 DMA_TX_DATA_SGL_OVERFLOW
, /* 0x43 */
665 DMA_TX_DIF_SGL_OVERFLOW
, /* 0x44 */
666 DMA_TX_UNEXP_XFER_ERR
, /* 0x45 */
667 DMA_TX_UNEXP_RETRANS_ERR
, /* 0x46 */
668 DMA_TX_XFER_LEN_OVERFLOW
, /* 0x47 */
669 DMA_TX_XFER_OFFSET_ERR
, /* 0x48 */
670 DMA_TX_RAM_ECC_ERR
, /* 0x49 */
671 DMA_TX_DIF_LEN_ALIGN_ERR
, /* 0x4a */
675 SIPC_RX_FIS_STATUS_ERR_BIT_VLD
= SIPC_RX_ERR_BASE
, /* 0x50 */
676 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR
, /* 0x51 */
677 SIPC_RX_FIS_STATUS_BSY_BIT_ERR
, /* 0x52 */
678 SIPC_RX_WRSETUP_LEN_ODD_ERR
, /* 0x53 */
679 SIPC_RX_WRSETUP_LEN_ZERO_ERR
, /* 0x54 */
680 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR
, /* 0x55 */
681 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR
, /* 0x56 */
682 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR
, /* 0x57 */
683 SIPC_RX_SATA_UNEXP_FIS_ERR
, /* 0x58 */
684 SIPC_RX_WRSETUP_ESTATUS_ERR
, /* 0x59 */
685 SIPC_RX_DATA_UNDERFLOW_ERR
, /* 0x5a */
686 SIPC_RX_MAX_ERR_CODE
,
689 DMA_RX_DIF_CRC_ERR
= DMA_RX_ERR_BASE
, /* 0x60 */
690 DMA_RX_DIF_APP_ERR
, /* 0x61 */
691 DMA_RX_DIF_RPP_ERR
, /* 0x62 */
692 DMA_RX_DATA_SGL_OVERFLOW
, /* 0x63 */
693 DMA_RX_DIF_SGL_OVERFLOW
, /* 0x64 */
694 DMA_RX_DATA_LEN_OVERFLOW
, /* 0x65 */
695 DMA_RX_DATA_LEN_UNDERFLOW
, /* 0x66 */
696 DMA_RX_DATA_OFFSET_ERR
, /* 0x67 */
697 RESERVED10
, /* 0x68 */
698 DMA_RX_SATA_FRAME_TYPE_ERR
, /* 0x69 */
699 DMA_RX_RESP_BUF_OVERFLOW
, /* 0x6a */
700 DMA_RX_UNEXP_RETRANS_RESP_ERR
, /* 0x6b */
701 DMA_RX_UNEXP_NORM_RESP_ERR
, /* 0x6c */
702 DMA_RX_UNEXP_RDFRAME_ERR
, /* 0x6d */
703 DMA_RX_PIO_DATA_LEN_ERR
, /* 0x6e */
704 DMA_RX_RDSETUP_STATUS_ERR
, /* 0x6f */
705 DMA_RX_RDSETUP_STATUS_DRQ_ERR
, /* 0x70 */
706 DMA_RX_RDSETUP_STATUS_BSY_ERR
, /* 0x71 */
707 DMA_RX_RDSETUP_LEN_ODD_ERR
, /* 0x72 */
708 DMA_RX_RDSETUP_LEN_ZERO_ERR
, /* 0x73 */
709 DMA_RX_RDSETUP_LEN_OVER_ERR
, /* 0x74 */
710 DMA_RX_RDSETUP_OFFSET_ERR
, /* 0x75 */
711 DMA_RX_RDSETUP_ACTIVE_ERR
, /* 0x76 */
712 DMA_RX_RDSETUP_ESTATUS_ERR
, /* 0x77 */
713 DMA_RX_RAM_ECC_ERR
, /* 0x78 */
714 DMA_RX_UNKNOWN_FRM_ERR
, /* 0x79 */
718 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
719 #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
721 #define DIR_NO_DATA 0
723 #define DIR_TO_DEVICE 2
724 #define DIR_RESERVED 3
726 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
727 err_phase == 0x4 || err_phase == 0x8 ||\
728 err_phase == 0x6 || err_phase == 0xa)
729 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
730 err_phase == 0x20 || err_phase == 0x40)
732 static void link_timeout_disable_link(struct timer_list
*t
);
734 static u32
hisi_sas_read32(struct hisi_hba
*hisi_hba
, u32 off
)
736 void __iomem
*regs
= hisi_hba
->regs
+ off
;
741 static u32
hisi_sas_read32_relaxed(struct hisi_hba
*hisi_hba
, u32 off
)
743 void __iomem
*regs
= hisi_hba
->regs
+ off
;
745 return readl_relaxed(regs
);
748 static void hisi_sas_write32(struct hisi_hba
*hisi_hba
, u32 off
, u32 val
)
750 void __iomem
*regs
= hisi_hba
->regs
+ off
;
755 static void hisi_sas_phy_write32(struct hisi_hba
*hisi_hba
, int phy_no
,
758 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
763 static u32
hisi_sas_phy_read32(struct hisi_hba
*hisi_hba
,
766 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
771 /* This function needs to be protected from pre-emption. */
773 slot_index_alloc_quirk_v2_hw(struct hisi_hba
*hisi_hba
,
774 struct domain_device
*device
)
776 int sata_dev
= dev_is_sata(device
);
777 void *bitmap
= hisi_hba
->slot_index_tags
;
778 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
779 int sata_idx
= sas_dev
->sata_idx
;
785 * STP link SoC bug workaround: index starts from 1.
786 * additionally, we can only allocate odd IPTT(1~4095)
787 * for SAS/SMP device.
790 end
= hisi_hba
->slot_index_count
;
792 if (sata_idx
>= HISI_MAX_SATA_SUPPORT_V2_HW
)
796 * For SATA device: allocate even IPTT in this interval
797 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
798 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
799 * SoC bug workaround. So we ignore the first 32 even IPTTs.
801 start
= 64 * (sata_idx
+ 1);
802 end
= 64 * (sata_idx
+ 2);
805 spin_lock_irqsave(&hisi_hba
->lock
, flags
);
807 start
= find_next_zero_bit(bitmap
,
808 hisi_hba
->slot_index_count
, start
);
810 spin_unlock_irqrestore(&hisi_hba
->lock
, flags
);
811 return -SAS_QUEUE_FULL
;
814 * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
816 if (sata_dev
^ (start
& 1))
821 set_bit(start
, bitmap
);
822 spin_unlock_irqrestore(&hisi_hba
->lock
, flags
);
826 static bool sata_index_alloc_v2_hw(struct hisi_hba
*hisi_hba
, int *idx
)
829 struct device
*dev
= hisi_hba
->dev
;
830 void *bitmap
= hisi_hba
->sata_dev_bitmap
;
832 index
= find_first_zero_bit(bitmap
, HISI_MAX_SATA_SUPPORT_V2_HW
);
833 if (index
>= HISI_MAX_SATA_SUPPORT_V2_HW
) {
834 dev_warn(dev
, "alloc sata index failed, index=%d\n", index
);
838 set_bit(index
, bitmap
);
845 hisi_sas_device
*alloc_dev_quirk_v2_hw(struct domain_device
*device
)
847 struct hisi_hba
*hisi_hba
= device
->port
->ha
->lldd_ha
;
848 struct hisi_sas_device
*sas_dev
= NULL
;
849 int i
, sata_dev
= dev_is_sata(device
);
853 spin_lock_irqsave(&hisi_hba
->lock
, flags
);
856 if (!sata_index_alloc_v2_hw(hisi_hba
, &sata_idx
))
859 for (i
= 0; i
< HISI_SAS_MAX_DEVICES
; i
++) {
861 * SATA device id bit0 should be 0
863 if (sata_dev
&& (i
& 1))
865 if (hisi_hba
->devices
[i
].dev_type
== SAS_PHY_UNUSED
) {
866 int queue
= i
% hisi_hba
->queue_count
;
867 struct hisi_sas_dq
*dq
= &hisi_hba
->dq
[queue
];
869 hisi_hba
->devices
[i
].device_id
= i
;
870 sas_dev
= &hisi_hba
->devices
[i
];
871 sas_dev
->dev_status
= HISI_SAS_DEV_NORMAL
;
872 sas_dev
->dev_type
= device
->dev_type
;
873 sas_dev
->hisi_hba
= hisi_hba
;
874 sas_dev
->sas_device
= device
;
875 sas_dev
->sata_idx
= sata_idx
;
877 INIT_LIST_HEAD(&hisi_hba
->devices
[i
].list
);
883 spin_unlock_irqrestore(&hisi_hba
->lock
, flags
);
888 static void config_phy_opt_mode_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
890 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
892 cfg
&= ~PHY_CFG_DC_OPT_MSK
;
893 cfg
|= 1 << PHY_CFG_DC_OPT_OFF
;
894 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
897 static void config_id_frame_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
899 struct sas_identify_frame identify_frame
;
900 u32
*identify_buffer
;
902 memset(&identify_frame
, 0, sizeof(identify_frame
));
903 identify_frame
.dev_type
= SAS_END_DEVICE
;
904 identify_frame
.frame_type
= 0;
905 identify_frame
._un1
= 1;
906 identify_frame
.initiator_bits
= SAS_PROTOCOL_ALL
;
907 identify_frame
.target_bits
= SAS_PROTOCOL_NONE
;
908 memcpy(&identify_frame
._un4_11
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
909 memcpy(&identify_frame
.sas_addr
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
910 identify_frame
.phy_id
= phy_no
;
911 identify_buffer
= (u32
*)(&identify_frame
);
913 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD0
,
914 __swab32(identify_buffer
[0]));
915 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD1
,
916 __swab32(identify_buffer
[1]));
917 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD2
,
918 __swab32(identify_buffer
[2]));
919 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD3
,
920 __swab32(identify_buffer
[3]));
921 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD4
,
922 __swab32(identify_buffer
[4]));
923 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD5
,
924 __swab32(identify_buffer
[5]));
927 static void setup_itct_v2_hw(struct hisi_hba
*hisi_hba
,
928 struct hisi_sas_device
*sas_dev
)
930 struct domain_device
*device
= sas_dev
->sas_device
;
931 struct device
*dev
= hisi_hba
->dev
;
932 u64 qw0
, device_id
= sas_dev
->device_id
;
933 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[device_id
];
934 struct domain_device
*parent_dev
= device
->parent
;
935 struct asd_sas_port
*sas_port
= device
->port
;
936 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
938 memset(itct
, 0, sizeof(*itct
));
942 switch (sas_dev
->dev_type
) {
944 case SAS_EDGE_EXPANDER_DEVICE
:
945 case SAS_FANOUT_EXPANDER_DEVICE
:
946 qw0
= HISI_SAS_DEV_TYPE_SSP
<< ITCT_HDR_DEV_TYPE_OFF
;
949 case SAS_SATA_PENDING
:
950 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
951 qw0
= HISI_SAS_DEV_TYPE_STP
<< ITCT_HDR_DEV_TYPE_OFF
;
953 qw0
= HISI_SAS_DEV_TYPE_SATA
<< ITCT_HDR_DEV_TYPE_OFF
;
956 dev_warn(dev
, "setup itct: unsupported dev type (%d)\n",
960 qw0
|= ((1 << ITCT_HDR_VALID_OFF
) |
961 (device
->linkrate
<< ITCT_HDR_MCR_OFF
) |
962 (1 << ITCT_HDR_VLN_OFF
) |
963 (ITCT_HDR_SMP_TIMEOUT
<< ITCT_HDR_SMP_TIMEOUT_OFF
) |
964 (1 << ITCT_HDR_AWT_CONTINUE_OFF
) |
965 (port
->id
<< ITCT_HDR_PORT_ID_OFF
));
966 itct
->qw0
= cpu_to_le64(qw0
);
969 memcpy(&itct
->sas_addr
, device
->sas_addr
, SAS_ADDR_SIZE
);
970 itct
->sas_addr
= __swab64(itct
->sas_addr
);
973 if (!dev_is_sata(device
))
974 itct
->qw2
= cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF
) |
975 (0x1ULL
<< ITCT_HDR_BITLT_OFF
) |
976 (0x32ULL
<< ITCT_HDR_MCTLT_OFF
) |
977 (0x1ULL
<< ITCT_HDR_RTOLT_OFF
));
980 static void clear_itct_v2_hw(struct hisi_hba
*hisi_hba
,
981 struct hisi_sas_device
*sas_dev
)
983 DECLARE_COMPLETION_ONSTACK(completion
);
984 u64 dev_id
= sas_dev
->device_id
;
985 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[dev_id
];
986 u32 reg_val
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
989 sas_dev
->completion
= &completion
;
991 /* clear the itct interrupt state */
992 if (ENT_INT_SRC3_ITC_INT_MSK
& reg_val
)
993 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
994 ENT_INT_SRC3_ITC_INT_MSK
);
996 for (i
= 0; i
< 2; i
++) {
997 reg_val
= ITCT_CLR_EN_MSK
| (dev_id
& ITCT_DEV_MSK
);
998 hisi_sas_write32(hisi_hba
, ITCT_CLR
, reg_val
);
999 wait_for_completion(sas_dev
->completion
);
1001 memset(itct
, 0, sizeof(struct hisi_sas_itct
));
1005 static void free_device_v2_hw(struct hisi_sas_device
*sas_dev
)
1007 struct hisi_hba
*hisi_hba
= sas_dev
->hisi_hba
;
1009 /* SoC bug workaround */
1010 if (dev_is_sata(sas_dev
->sas_device
))
1011 clear_bit(sas_dev
->sata_idx
, hisi_hba
->sata_dev_bitmap
);
1014 static int reset_hw_v2_hw(struct hisi_hba
*hisi_hba
)
1018 unsigned long end_time
;
1019 struct device
*dev
= hisi_hba
->dev
;
1021 /* The mask needs to be set depending on the number of phys */
1022 if (hisi_hba
->n_phy
== 9)
1023 reset_val
= 0x1fffff;
1025 reset_val
= 0x7ffff;
1027 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0);
1029 /* Disable all of the PHYs */
1030 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1031 u32 phy_cfg
= hisi_sas_phy_read32(hisi_hba
, i
, PHY_CFG
);
1033 phy_cfg
&= ~PHY_CTRL_RESET_MSK
;
1034 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CFG
, phy_cfg
);
1038 /* Ensure DMA tx & rx idle */
1039 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1040 u32 dma_tx_status
, dma_rx_status
;
1042 end_time
= jiffies
+ msecs_to_jiffies(1000);
1045 dma_tx_status
= hisi_sas_phy_read32(hisi_hba
, i
,
1047 dma_rx_status
= hisi_sas_phy_read32(hisi_hba
, i
,
1050 if (!(dma_tx_status
& DMA_TX_STATUS_BUSY_MSK
) &&
1051 !(dma_rx_status
& DMA_RX_STATUS_BUSY_MSK
))
1055 if (time_after(jiffies
, end_time
))
1060 /* Ensure axi bus idle */
1061 end_time
= jiffies
+ msecs_to_jiffies(1000);
1064 hisi_sas_read32(hisi_hba
, AXI_CFG
);
1066 if (axi_status
== 0)
1070 if (time_after(jiffies
, end_time
))
1074 if (ACPI_HANDLE(dev
)) {
1077 s
= acpi_evaluate_object(ACPI_HANDLE(dev
), "_RST", NULL
, NULL
);
1078 if (ACPI_FAILURE(s
)) {
1079 dev_err(dev
, "Reset failed\n");
1082 } else if (hisi_hba
->ctrl
) {
1083 /* reset and disable clock*/
1084 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_reg
,
1086 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_clock_ena_reg
+ 4,
1089 regmap_read(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_sts_reg
, &val
);
1090 if (reset_val
!= (val
& reset_val
)) {
1091 dev_err(dev
, "SAS reset fail.\n");
1095 /* De-reset and enable clock*/
1096 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_reg
+ 4,
1098 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_clock_ena_reg
,
1101 regmap_read(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_sts_reg
,
1103 if (val
& reset_val
) {
1104 dev_err(dev
, "SAS de-reset fail.\n");
1108 dev_err(dev
, "no reset method\n");
1115 /* This function needs to be called after resetting SAS controller. */
1116 static void phys_reject_stp_links_v2_hw(struct hisi_hba
*hisi_hba
)
1121 hisi_hba
->reject_stp_links_msk
= (1 << hisi_hba
->n_phy
) - 1;
1122 for (phy_no
= 0; phy_no
< hisi_hba
->n_phy
; phy_no
++) {
1123 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, CON_CONTROL
);
1124 if (!(cfg
& CON_CONTROL_CFG_OPEN_ACC_STP_MSK
))
1127 cfg
&= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK
;
1128 hisi_sas_phy_write32(hisi_hba
, phy_no
, CON_CONTROL
, cfg
);
1132 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba
*hisi_hba
)
1137 for (phy_no
= 0; phy_no
< hisi_hba
->n_phy
; phy_no
++) {
1138 if (!(hisi_hba
->reject_stp_links_msk
& BIT(phy_no
)))
1141 dma_tx_dfx1
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1143 if (dma_tx_dfx1
& DMA_TX_DFX1_IPTT_MSK
) {
1144 u32 cfg
= hisi_sas_phy_read32(hisi_hba
,
1145 phy_no
, CON_CONTROL
);
1147 cfg
|= CON_CONTROL_CFG_OPEN_ACC_STP_MSK
;
1148 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1150 clear_bit(phy_no
, &hisi_hba
->reject_stp_links_msk
);
1155 static const struct signal_attenuation_s x6000
= {9200, 0, 10476};
1156 static const struct sig_atten_lu_s sig_atten_lu
[] = {
1157 { &x6000
, 0x3016a68 },
1160 static void init_reg_v2_hw(struct hisi_hba
*hisi_hba
)
1162 struct device
*dev
= hisi_hba
->dev
;
1163 u32 sas_phy_ctrl
= 0x30b9908;
1167 /* Global registers init */
1169 /* Deal with am-max-transmissions quirk */
1170 if (device_property_present(dev
, "hip06-sas-v2-quirk-amt")) {
1171 hisi_sas_write32(hisi_hba
, AM_CFG_MAX_TRANS
, 0x2020);
1172 hisi_sas_write32(hisi_hba
, AM_CFG_SINGLE_PORT_MAX_TRANS
,
1174 } /* Else, use defaults -> do nothing */
1176 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
,
1177 (u32
)((1ULL << hisi_hba
->queue_count
) - 1));
1178 hisi_sas_write32(hisi_hba
, AXI_USER1
, 0xc0000000);
1179 hisi_sas_write32(hisi_hba
, AXI_USER2
, 0x10000);
1180 hisi_sas_write32(hisi_hba
, HGC_SAS_TXFAIL_RETRY_CTRL
, 0x0);
1181 hisi_sas_write32(hisi_hba
, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL
, 0x7FF);
1182 hisi_sas_write32(hisi_hba
, OPENA_WT_CONTI_TIME
, 0x1);
1183 hisi_sas_write32(hisi_hba
, I_T_NEXUS_LOSS_TIME
, 0x1F4);
1184 hisi_sas_write32(hisi_hba
, MAX_CON_TIME_LIMIT_TIME
, 0x32);
1185 hisi_sas_write32(hisi_hba
, BUS_INACTIVE_LIMIT_TIME
, 0x1);
1186 hisi_sas_write32(hisi_hba
, CFG_AGING_TIME
, 0x1);
1187 hisi_sas_write32(hisi_hba
, HGC_ERR_STAT_EN
, 0x1);
1188 hisi_sas_write32(hisi_hba
, HGC_GET_ITV_TIME
, 0x1);
1189 hisi_sas_write32(hisi_hba
, INT_COAL_EN
, 0xc);
1190 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_TIME
, 0x60);
1191 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_CNT
, 0x3);
1192 hisi_sas_write32(hisi_hba
, ENT_INT_COAL_TIME
, 0x1);
1193 hisi_sas_write32(hisi_hba
, ENT_INT_COAL_CNT
, 0x1);
1194 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 0x0);
1195 hisi_sas_write32(hisi_hba
, ENT_INT_SRC1
, 0xffffffff);
1196 hisi_sas_write32(hisi_hba
, ENT_INT_SRC2
, 0xffffffff);
1197 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
, 0xffffffff);
1198 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0x7efefefe);
1199 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0x7efefefe);
1200 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0x7ffe20fe);
1201 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0xfff00c30);
1202 for (i
= 0; i
< hisi_hba
->queue_count
; i
++)
1203 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+0x4*i
, 0);
1205 hisi_sas_write32(hisi_hba
, AXI_AHB_CLK_CFG
, 1);
1206 hisi_sas_write32(hisi_hba
, HYPER_STREAM_ID_EN_CFG
, 1);
1208 /* Get sas_phy_ctrl value to deal with TX FFE issue. */
1209 if (!device_property_read_u32_array(dev
, "hisilicon,signal-attenuation",
1210 signal
, ARRAY_SIZE(signal
))) {
1211 for (i
= 0; i
< ARRAY_SIZE(sig_atten_lu
); i
++) {
1212 const struct sig_atten_lu_s
*lookup
= &sig_atten_lu
[i
];
1213 const struct signal_attenuation_s
*att
= lookup
->att
;
1215 if ((signal
[0] == att
->de_emphasis
) &&
1216 (signal
[1] == att
->preshoot
) &&
1217 (signal
[2] == att
->boost
)) {
1218 sas_phy_ctrl
= lookup
->sas_phy_ctrl
;
1223 if (i
== ARRAY_SIZE(sig_atten_lu
))
1224 dev_warn(dev
, "unknown signal attenuation values, using default PHY ctrl config\n");
1227 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1228 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[i
];
1229 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1230 u32 prog_phy_link_rate
= 0x800;
1232 if (!sas_phy
->phy
|| (sas_phy
->phy
->maximum_linkrate
<
1233 SAS_LINK_RATE_1_5_GBPS
)) {
1234 prog_phy_link_rate
= 0x855;
1236 enum sas_linkrate max
= sas_phy
->phy
->maximum_linkrate
;
1238 prog_phy_link_rate
=
1239 hisi_sas_get_prog_phy_linkrate_mask(max
) |
1242 hisi_sas_phy_write32(hisi_hba
, i
, PROG_PHY_LINK_RATE
,
1243 prog_phy_link_rate
);
1244 hisi_sas_phy_write32(hisi_hba
, i
, SAS_PHY_CTRL
, sas_phy_ctrl
);
1245 hisi_sas_phy_write32(hisi_hba
, i
, SL_TOUT_CFG
, 0x7d7d7d7d);
1246 hisi_sas_phy_write32(hisi_hba
, i
, SL_CONTROL
, 0x0);
1247 hisi_sas_phy_write32(hisi_hba
, i
, TXID_AUTO
, 0x2);
1248 hisi_sas_phy_write32(hisi_hba
, i
, DONE_RECEIVED_TIME
, 0x8);
1249 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT0
, 0xffffffff);
1250 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1
, 0xffffffff);
1251 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2
, 0xfff87fff);
1252 hisi_sas_phy_write32(hisi_hba
, i
, RXOP_CHECK_CFG_H
, 0x1000);
1253 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xff857fff);
1254 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0x8ffffbfe);
1255 hisi_sas_phy_write32(hisi_hba
, i
, SL_CFG
, 0x13f801fc);
1256 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL_RDY_MSK
, 0x0);
1257 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_NOT_RDY_MSK
, 0x0);
1258 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_DWS_RESET_MSK
, 0x0);
1259 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_PHY_ENA_MSK
, 0x0);
1260 hisi_sas_phy_write32(hisi_hba
, i
, SL_RX_BCAST_CHK_MSK
, 0x0);
1261 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT_COAL_EN
, 0x0);
1262 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_OOB_RESTART_MSK
, 0x0);
1263 if (hisi_hba
->refclk_frequency_mhz
== 66)
1264 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL
, 0x199B694);
1265 /* else, do nothing -> leave it how you found it */
1268 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
1269 /* Delivery queue */
1270 hisi_sas_write32(hisi_hba
,
1271 DLVRY_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
1272 upper_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
1274 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
1275 lower_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
1277 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_DEPTH
+ (i
* 0x14),
1278 HISI_SAS_QUEUE_SLOTS
);
1280 /* Completion queue */
1281 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
1282 upper_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
1284 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
1285 lower_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
1287 hisi_sas_write32(hisi_hba
, COMPL_Q_0_DEPTH
+ (i
* 0x14),
1288 HISI_SAS_QUEUE_SLOTS
);
1292 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_LO
,
1293 lower_32_bits(hisi_hba
->itct_dma
));
1295 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_HI
,
1296 upper_32_bits(hisi_hba
->itct_dma
));
1299 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_LO
,
1300 lower_32_bits(hisi_hba
->iost_dma
));
1302 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_HI
,
1303 upper_32_bits(hisi_hba
->iost_dma
));
1306 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_LO
,
1307 lower_32_bits(hisi_hba
->breakpoint_dma
));
1309 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_HI
,
1310 upper_32_bits(hisi_hba
->breakpoint_dma
));
1312 /* SATA broken msg */
1313 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_LO
,
1314 lower_32_bits(hisi_hba
->sata_breakpoint_dma
));
1316 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_HI
,
1317 upper_32_bits(hisi_hba
->sata_breakpoint_dma
));
1319 /* SATA initial fis */
1320 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_LO
,
1321 lower_32_bits(hisi_hba
->initial_fis_dma
));
1323 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_HI
,
1324 upper_32_bits(hisi_hba
->initial_fis_dma
));
1327 static void link_timeout_enable_link(struct timer_list
*t
)
1329 struct hisi_hba
*hisi_hba
= from_timer(hisi_hba
, t
, timer
);
1332 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1333 if (hisi_hba
->reject_stp_links_msk
& BIT(i
))
1336 reg_val
= hisi_sas_phy_read32(hisi_hba
, i
, CON_CONTROL
);
1337 if (!(reg_val
& BIT(0))) {
1338 hisi_sas_phy_write32(hisi_hba
, i
,
1344 hisi_hba
->timer
.function
= link_timeout_disable_link
;
1345 mod_timer(&hisi_hba
->timer
, jiffies
+ msecs_to_jiffies(900));
1348 static void link_timeout_disable_link(struct timer_list
*t
)
1350 struct hisi_hba
*hisi_hba
= from_timer(hisi_hba
, t
, timer
);
1353 reg_val
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1354 for (i
= 0; i
< hisi_hba
->n_phy
&& reg_val
; i
++) {
1355 if (hisi_hba
->reject_stp_links_msk
& BIT(i
))
1358 if (reg_val
& BIT(i
)) {
1359 hisi_sas_phy_write32(hisi_hba
, i
,
1365 hisi_hba
->timer
.function
= link_timeout_enable_link
;
1366 mod_timer(&hisi_hba
->timer
, jiffies
+ msecs_to_jiffies(100));
1369 static void set_link_timer_quirk(struct hisi_hba
*hisi_hba
)
1371 hisi_hba
->timer
.function
= link_timeout_disable_link
;
1372 hisi_hba
->timer
.expires
= jiffies
+ msecs_to_jiffies(1000);
1373 add_timer(&hisi_hba
->timer
);
1376 static int hw_init_v2_hw(struct hisi_hba
*hisi_hba
)
1378 struct device
*dev
= hisi_hba
->dev
;
1381 rc
= reset_hw_v2_hw(hisi_hba
);
1383 dev_err(dev
, "hisi_sas_reset_hw failed, rc=%d", rc
);
1388 init_reg_v2_hw(hisi_hba
);
1393 static void enable_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1395 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
1397 cfg
|= PHY_CFG_ENA_MSK
;
1398 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
1401 static bool is_sata_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1405 context
= hisi_sas_read32(hisi_hba
, PHY_CONTEXT
);
1406 if (context
& (1 << phy_no
))
1412 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1416 dfx_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, DMA_TX_DFX1
);
1418 if (dfx_val
& BIT(16))
1424 static bool axi_bus_is_idle_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1426 int i
, max_loop
= 1000;
1427 struct device
*dev
= hisi_hba
->dev
;
1428 u32 status
, axi_status
, dfx_val
, dfx_tx_val
;
1430 for (i
= 0; i
< max_loop
; i
++) {
1431 status
= hisi_sas_read32_relaxed(hisi_hba
,
1432 AXI_MASTER_CFG_BASE
+ AM_CURR_TRANS_RETURN
);
1434 axi_status
= hisi_sas_read32(hisi_hba
, AXI_CFG
);
1435 dfx_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, DMA_TX_DFX1
);
1436 dfx_tx_val
= hisi_sas_phy_read32(hisi_hba
,
1437 phy_no
, DMA_TX_FIFO_DFX0
);
1439 if ((status
== 0x3) && (axi_status
== 0x0) &&
1440 (dfx_val
& BIT(20)) && (dfx_tx_val
& BIT(10)))
1444 dev_err(dev
, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1445 phy_no
, status
, axi_status
,
1446 dfx_val
, dfx_tx_val
);
1450 static bool wait_io_done_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1452 int i
, max_loop
= 1000;
1453 struct device
*dev
= hisi_hba
->dev
;
1454 u32 status
, tx_dfx0
;
1456 for (i
= 0; i
< max_loop
; i
++) {
1457 status
= hisi_sas_phy_read32(hisi_hba
, phy_no
, LINK_DFX2
);
1458 status
= (status
& 0x3fc0) >> 6;
1463 tx_dfx0
= hisi_sas_phy_read32(hisi_hba
, phy_no
, DMA_TX_DFX0
);
1464 if ((tx_dfx0
& 0x1ff) == 0x2)
1468 dev_err(dev
, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1469 phy_no
, status
, tx_dfx0
);
1473 static bool allowed_disable_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1475 if (tx_fifo_is_empty_v2_hw(hisi_hba
, phy_no
))
1478 if (!axi_bus_is_idle_v2_hw(hisi_hba
, phy_no
))
1481 if (!wait_io_done_v2_hw(hisi_hba
, phy_no
))
1488 static void disable_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1490 u32 cfg
, axi_val
, dfx0_val
, txid_auto
;
1491 struct device
*dev
= hisi_hba
->dev
;
1493 /* Close axi bus. */
1494 axi_val
= hisi_sas_read32(hisi_hba
, AXI_MASTER_CFG_BASE
+
1497 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
+
1498 AM_CTRL_GLOBAL
, axi_val
);
1500 if (is_sata_phy_v2_hw(hisi_hba
, phy_no
)) {
1501 if (allowed_disable_phy_v2_hw(hisi_hba
, phy_no
))
1504 /* Reset host controller. */
1505 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
1509 dfx0_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PORT_DFX0
);
1510 dfx0_val
= (dfx0_val
& 0x1fc0) >> 6;
1511 if (dfx0_val
!= 0x4)
1514 if (!tx_fifo_is_empty_v2_hw(hisi_hba
, phy_no
)) {
1515 dev_warn(dev
, "phy%d, wait tx fifo need send break\n",
1517 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1519 txid_auto
|= TXID_AUTO_CTB_MSK
;
1520 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
1525 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
1526 cfg
&= ~PHY_CFG_ENA_MSK
;
1527 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
1531 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
+
1532 AM_CTRL_GLOBAL
, axi_val
);
1535 static void start_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1537 config_id_frame_v2_hw(hisi_hba
, phy_no
);
1538 config_phy_opt_mode_v2_hw(hisi_hba
, phy_no
);
1539 enable_phy_v2_hw(hisi_hba
, phy_no
);
1542 static void phy_hard_reset_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1544 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1547 disable_phy_v2_hw(hisi_hba
, phy_no
);
1548 if (phy
->identify
.device_type
== SAS_END_DEVICE
) {
1549 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
1550 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
1551 txid_auto
| TX_HARDRST_MSK
);
1554 start_phy_v2_hw(hisi_hba
, phy_no
);
1557 static void phy_get_events_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1559 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1560 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1561 struct sas_phy
*sphy
= sas_phy
->phy
;
1562 u32 err4_reg_val
, err6_reg_val
;
1564 /* loss dword syn, phy reset problem */
1565 err4_reg_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SAS_ERR_CNT4_REG
);
1567 /* disparity err, invalid dword */
1568 err6_reg_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SAS_ERR_CNT6_REG
);
1570 sphy
->loss_of_dword_sync_count
+= (err4_reg_val
>> 16) & 0xFFFF;
1571 sphy
->phy_reset_problem_count
+= err4_reg_val
& 0xFFFF;
1572 sphy
->invalid_dword_count
+= (err6_reg_val
& 0xFF0000) >> 16;
1573 sphy
->running_disparity_error_count
+= err6_reg_val
& 0xFF;
1576 static void phys_init_v2_hw(struct hisi_hba
*hisi_hba
)
1580 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1581 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[i
];
1582 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1584 if (!sas_phy
->phy
->enabled
)
1587 start_phy_v2_hw(hisi_hba
, i
);
1591 static void sl_notify_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1595 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
1596 sl_control
|= SL_CONTROL_NOTIFY_EN_MSK
;
1597 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
1599 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
1600 sl_control
&= ~SL_CONTROL_NOTIFY_EN_MSK
;
1601 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
1604 static enum sas_linkrate
phy_get_max_linkrate_v2_hw(void)
1606 return SAS_LINK_RATE_12_0_GBPS
;
1609 static void phy_set_linkrate_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
,
1610 struct sas_phy_linkrates
*r
)
1612 enum sas_linkrate max
= r
->maximum_linkrate
;
1613 u32 prog_phy_link_rate
= 0x800;
1615 prog_phy_link_rate
|= hisi_sas_get_prog_phy_linkrate_mask(max
);
1616 hisi_sas_phy_write32(hisi_hba
, phy_no
, PROG_PHY_LINK_RATE
,
1617 prog_phy_link_rate
);
1620 static int get_wideport_bitmap_v2_hw(struct hisi_hba
*hisi_hba
, int port_id
)
1623 u32 phy_port_num_ma
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
1624 u32 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1626 for (i
= 0; i
< (hisi_hba
->n_phy
< 9 ? hisi_hba
->n_phy
: 8); i
++)
1627 if (phy_state
& 1 << i
)
1628 if (((phy_port_num_ma
>> (i
* 4)) & 0xf) == port_id
)
1631 if (hisi_hba
->n_phy
== 9) {
1632 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
1634 if (phy_state
& 1 << 8)
1635 if (((port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
1636 PORT_STATE_PHY8_PORT_NUM_OFF
) == port_id
)
1644 * The callpath to this function and upto writing the write
1645 * queue pointer should be safe from interruption.
1648 get_free_slot_v2_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_dq
*dq
)
1650 struct device
*dev
= hisi_hba
->dev
;
1655 r
= hisi_sas_read32_relaxed(hisi_hba
,
1656 DLVRY_Q_0_RD_PTR
+ (queue
* 0x14));
1657 if (r
== (w
+1) % HISI_SAS_QUEUE_SLOTS
) {
1658 dev_warn(dev
, "full queue=%d r=%d w=%d\n",
1663 dq
->wr_point
= (dq
->wr_point
+ 1) % HISI_SAS_QUEUE_SLOTS
;
1668 /* DQ lock must be taken here */
1669 static void start_delivery_v2_hw(struct hisi_sas_dq
*dq
)
1671 struct hisi_hba
*hisi_hba
= dq
->hisi_hba
;
1672 struct hisi_sas_slot
*s
, *s1
, *s2
= NULL
;
1673 int dlvry_queue
= dq
->id
;
1676 list_for_each_entry_safe(s
, s1
, &dq
->list
, delivery
) {
1680 list_del(&s
->delivery
);
1687 * Ensure that memories for slots built on other CPUs is observed.
1690 wp
= (s2
->dlvry_queue_slot
+ 1) % HISI_SAS_QUEUE_SLOTS
;
1692 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_WR_PTR
+ (dlvry_queue
* 0x14), wp
);
1695 static void prep_prd_sge_v2_hw(struct hisi_hba
*hisi_hba
,
1696 struct hisi_sas_slot
*slot
,
1697 struct hisi_sas_cmd_hdr
*hdr
,
1698 struct scatterlist
*scatter
,
1701 struct hisi_sas_sge_page
*sge_page
= hisi_sas_sge_addr_mem(slot
);
1702 struct scatterlist
*sg
;
1705 for_each_sg(scatter
, sg
, n_elem
, i
) {
1706 struct hisi_sas_sge
*entry
= &sge_page
->sge
[i
];
1708 entry
->addr
= cpu_to_le64(sg_dma_address(sg
));
1709 entry
->page_ctrl_0
= entry
->page_ctrl_1
= 0;
1710 entry
->data_len
= cpu_to_le32(sg_dma_len(sg
));
1711 entry
->data_off
= 0;
1714 hdr
->prd_table_addr
= cpu_to_le64(hisi_sas_sge_addr_dma(slot
));
1716 hdr
->sg_len
= cpu_to_le32(n_elem
<< CMD_HDR_DATA_SGL_LEN_OFF
);
1719 static void prep_smp_v2_hw(struct hisi_hba
*hisi_hba
,
1720 struct hisi_sas_slot
*slot
)
1722 struct sas_task
*task
= slot
->task
;
1723 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1724 struct domain_device
*device
= task
->dev
;
1725 struct hisi_sas_port
*port
= slot
->port
;
1726 struct scatterlist
*sg_req
;
1727 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
1728 dma_addr_t req_dma_addr
;
1729 unsigned int req_len
;
1732 sg_req
= &task
->smp_task
.smp_req
;
1733 req_dma_addr
= sg_dma_address(sg_req
);
1734 req_len
= sg_dma_len(&task
->smp_task
.smp_req
);
1738 hdr
->dw0
= cpu_to_le32((port
->id
<< CMD_HDR_PORT_OFF
) |
1739 (1 << CMD_HDR_PRIORITY_OFF
) | /* high pri */
1740 (2 << CMD_HDR_CMD_OFF
)); /* smp */
1742 /* map itct entry */
1743 hdr
->dw1
= cpu_to_le32((sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
) |
1744 (1 << CMD_HDR_FRAME_TYPE_OFF
) |
1745 (DIR_NO_DATA
<< CMD_HDR_DIR_OFF
));
1748 hdr
->dw2
= cpu_to_le32((((req_len
- 4) / 4) << CMD_HDR_CFL_OFF
) |
1749 (HISI_SAS_MAX_SMP_RESP_SZ
/ 4 <<
1752 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
<< CMD_HDR_IPTT_OFF
);
1754 hdr
->cmd_table_addr
= cpu_to_le64(req_dma_addr
);
1755 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
1758 static void prep_ssp_v2_hw(struct hisi_hba
*hisi_hba
,
1759 struct hisi_sas_slot
*slot
)
1761 struct sas_task
*task
= slot
->task
;
1762 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1763 struct domain_device
*device
= task
->dev
;
1764 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
1765 struct hisi_sas_port
*port
= slot
->port
;
1766 struct sas_ssp_task
*ssp_task
= &task
->ssp_task
;
1767 struct scsi_cmnd
*scsi_cmnd
= ssp_task
->cmd
;
1768 struct hisi_sas_tmf_task
*tmf
= slot
->tmf
;
1769 int has_data
= 0, priority
= !!tmf
;
1771 u32 dw1
= 0, dw2
= 0;
1773 hdr
->dw0
= cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF
) |
1774 (2 << CMD_HDR_TLR_CTRL_OFF
) |
1775 (port
->id
<< CMD_HDR_PORT_OFF
) |
1776 (priority
<< CMD_HDR_PRIORITY_OFF
) |
1777 (1 << CMD_HDR_CMD_OFF
)); /* ssp */
1779 dw1
= 1 << CMD_HDR_VDTL_OFF
;
1781 dw1
|= 2 << CMD_HDR_FRAME_TYPE_OFF
;
1782 dw1
|= DIR_NO_DATA
<< CMD_HDR_DIR_OFF
;
1784 dw1
|= 1 << CMD_HDR_FRAME_TYPE_OFF
;
1785 switch (scsi_cmnd
->sc_data_direction
) {
1788 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
1790 case DMA_FROM_DEVICE
:
1792 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
1795 dw1
&= ~CMD_HDR_DIR_MSK
;
1799 /* map itct entry */
1800 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
1801 hdr
->dw1
= cpu_to_le32(dw1
);
1803 dw2
= (((sizeof(struct ssp_command_iu
) + sizeof(struct ssp_frame_hdr
)
1804 + 3) / 4) << CMD_HDR_CFL_OFF
) |
1805 ((HISI_SAS_MAX_SSP_RESP_SZ
/ 4) << CMD_HDR_MRFL_OFF
) |
1806 (2 << CMD_HDR_SG_MOD_OFF
);
1807 hdr
->dw2
= cpu_to_le32(dw2
);
1809 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
1812 prep_prd_sge_v2_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
1815 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
1816 hdr
->cmd_table_addr
= cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot
));
1817 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
1819 buf_cmd
= hisi_sas_cmd_hdr_addr_mem(slot
) +
1820 sizeof(struct ssp_frame_hdr
);
1822 memcpy(buf_cmd
, &task
->ssp_task
.LUN
, 8);
1824 buf_cmd
[9] = task
->ssp_task
.task_attr
|
1825 (task
->ssp_task
.task_prio
<< 3);
1826 memcpy(buf_cmd
+ 12, task
->ssp_task
.cmd
->cmnd
,
1827 task
->ssp_task
.cmd
->cmd_len
);
1829 buf_cmd
[10] = tmf
->tmf
;
1831 case TMF_ABORT_TASK
:
1832 case TMF_QUERY_TASK
:
1834 (tmf
->tag_of_task_to_be_managed
>> 8) & 0xff;
1836 tmf
->tag_of_task_to_be_managed
& 0xff;
1844 #define TRANS_TX_ERR 0
1845 #define TRANS_RX_ERR 1
1846 #define DMA_TX_ERR 2
1847 #define SIPC_RX_ERR 3
1848 #define DMA_RX_ERR 4
1850 #define DMA_TX_ERR_OFF 0
1851 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1852 #define SIPC_RX_ERR_OFF 16
1853 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1855 static int parse_trans_tx_err_code_v2_hw(u32 err_msk
)
1857 static const u8 trans_tx_err_code_prio
[] = {
1858 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
,
1859 TRANS_TX_ERR_PHY_NOT_ENABLE
,
1860 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
,
1861 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
,
1862 TRANS_TX_OPEN_CNX_ERR_BY_OTHER
,
1864 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
,
1865 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
,
1866 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
,
1867 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
,
1868 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
,
1869 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
,
1870 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
,
1871 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
,
1872 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
,
1873 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
,
1874 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
,
1875 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
,
1876 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
,
1877 TRANS_TX_ERR_WITH_CLOSE_COMINIT
,
1878 TRANS_TX_ERR_WITH_BREAK_TIMEOUT
,
1879 TRANS_TX_ERR_WITH_BREAK_REQUEST
,
1880 TRANS_TX_ERR_WITH_BREAK_RECEVIED
,
1881 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
,
1882 TRANS_TX_ERR_WITH_CLOSE_NORMAL
,
1883 TRANS_TX_ERR_WITH_NAK_RECEVIED
,
1884 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
,
1885 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
,
1886 TRANS_TX_ERR_WITH_IPTT_CONFLICT
,
1887 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS
,
1888 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
,
1892 for (i
= 0; i
< ARRAY_SIZE(trans_tx_err_code_prio
); i
++) {
1893 index
= trans_tx_err_code_prio
[i
] - TRANS_TX_FAIL_BASE
;
1894 if (err_msk
& (1 << index
))
1895 return trans_tx_err_code_prio
[i
];
1900 static int parse_trans_rx_err_code_v2_hw(u32 err_msk
)
1902 static const u8 trans_rx_err_code_prio
[] = {
1903 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
,
1904 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
,
1905 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
,
1906 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
,
1907 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
,
1908 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
,
1909 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
,
1910 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
,
1911 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
,
1912 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
,
1913 TRANS_RX_ERR_WITH_CLOSE_COMINIT
,
1914 TRANS_RX_ERR_WITH_BREAK_TIMEOUT
,
1915 TRANS_RX_ERR_WITH_BREAK_REQUEST
,
1916 TRANS_RX_ERR_WITH_BREAK_RECEVIED
,
1918 TRANS_RX_ERR_WITH_CLOSE_NORMAL
,
1919 TRANS_RX_ERR_WITH_DATA_LEN0
,
1920 TRANS_RX_ERR_WITH_BAD_HASH
,
1921 TRANS_RX_XRDY_WLEN_ZERO_ERR
,
1922 TRANS_RX_SSP_FRM_LEN_ERR
,
1927 TRANS_RX_ERR_WITH_BAD_FRM_TYPE
,
1928 TRANS_RX_SMP_FRM_LEN_ERR
,
1929 TRANS_RX_SMP_RESP_TIMEOUT_ERR
,
1938 for (i
= 0; i
< ARRAY_SIZE(trans_rx_err_code_prio
); i
++) {
1939 index
= trans_rx_err_code_prio
[i
] - TRANS_RX_FAIL_BASE
;
1940 if (err_msk
& (1 << index
))
1941 return trans_rx_err_code_prio
[i
];
1946 static int parse_dma_tx_err_code_v2_hw(u32 err_msk
)
1948 static const u8 dma_tx_err_code_prio
[] = {
1949 DMA_TX_UNEXP_XFER_ERR
,
1950 DMA_TX_UNEXP_RETRANS_ERR
,
1951 DMA_TX_XFER_LEN_OVERFLOW
,
1952 DMA_TX_XFER_OFFSET_ERR
,
1954 DMA_TX_DIF_LEN_ALIGN_ERR
,
1958 DMA_TX_DATA_SGL_OVERFLOW
,
1959 DMA_TX_DIF_SGL_OVERFLOW
,
1963 for (i
= 0; i
< ARRAY_SIZE(dma_tx_err_code_prio
); i
++) {
1964 index
= dma_tx_err_code_prio
[i
] - DMA_TX_ERR_BASE
;
1965 err_msk
= err_msk
& DMA_TX_ERR_MSK
;
1966 if (err_msk
& (1 << index
))
1967 return dma_tx_err_code_prio
[i
];
1972 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk
)
1974 static const u8 sipc_rx_err_code_prio
[] = {
1975 SIPC_RX_FIS_STATUS_ERR_BIT_VLD
,
1976 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR
,
1977 SIPC_RX_FIS_STATUS_BSY_BIT_ERR
,
1978 SIPC_RX_WRSETUP_LEN_ODD_ERR
,
1979 SIPC_RX_WRSETUP_LEN_ZERO_ERR
,
1980 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR
,
1981 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR
,
1982 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR
,
1983 SIPC_RX_SATA_UNEXP_FIS_ERR
,
1984 SIPC_RX_WRSETUP_ESTATUS_ERR
,
1985 SIPC_RX_DATA_UNDERFLOW_ERR
,
1989 for (i
= 0; i
< ARRAY_SIZE(sipc_rx_err_code_prio
); i
++) {
1990 index
= sipc_rx_err_code_prio
[i
] - SIPC_RX_ERR_BASE
;
1991 err_msk
= err_msk
& SIPC_RX_ERR_MSK
;
1992 if (err_msk
& (1 << (index
+ 0x10)))
1993 return sipc_rx_err_code_prio
[i
];
1998 static int parse_dma_rx_err_code_v2_hw(u32 err_msk
)
2000 static const u8 dma_rx_err_code_prio
[] = {
2001 DMA_RX_UNKNOWN_FRM_ERR
,
2002 DMA_RX_DATA_LEN_OVERFLOW
,
2003 DMA_RX_DATA_LEN_UNDERFLOW
,
2004 DMA_RX_DATA_OFFSET_ERR
,
2006 DMA_RX_SATA_FRAME_TYPE_ERR
,
2007 DMA_RX_RESP_BUF_OVERFLOW
,
2008 DMA_RX_UNEXP_RETRANS_RESP_ERR
,
2009 DMA_RX_UNEXP_NORM_RESP_ERR
,
2010 DMA_RX_UNEXP_RDFRAME_ERR
,
2011 DMA_RX_PIO_DATA_LEN_ERR
,
2012 DMA_RX_RDSETUP_STATUS_ERR
,
2013 DMA_RX_RDSETUP_STATUS_DRQ_ERR
,
2014 DMA_RX_RDSETUP_STATUS_BSY_ERR
,
2015 DMA_RX_RDSETUP_LEN_ODD_ERR
,
2016 DMA_RX_RDSETUP_LEN_ZERO_ERR
,
2017 DMA_RX_RDSETUP_LEN_OVER_ERR
,
2018 DMA_RX_RDSETUP_OFFSET_ERR
,
2019 DMA_RX_RDSETUP_ACTIVE_ERR
,
2020 DMA_RX_RDSETUP_ESTATUS_ERR
,
2025 DMA_RX_DATA_SGL_OVERFLOW
,
2026 DMA_RX_DIF_SGL_OVERFLOW
,
2030 for (i
= 0; i
< ARRAY_SIZE(dma_rx_err_code_prio
); i
++) {
2031 index
= dma_rx_err_code_prio
[i
] - DMA_RX_ERR_BASE
;
2032 if (err_msk
& (1 << index
))
2033 return dma_rx_err_code_prio
[i
];
2038 /* by default, task resp is complete */
2039 static void slot_err_v2_hw(struct hisi_hba
*hisi_hba
,
2040 struct sas_task
*task
,
2041 struct hisi_sas_slot
*slot
,
2044 struct task_status_struct
*ts
= &task
->task_status
;
2045 struct hisi_sas_err_record_v2
*err_record
=
2046 hisi_sas_status_buf_addr_mem(slot
);
2047 u32 trans_tx_fail_type
= cpu_to_le32(err_record
->trans_tx_fail_type
);
2048 u32 trans_rx_fail_type
= cpu_to_le32(err_record
->trans_rx_fail_type
);
2049 u16 dma_tx_err_type
= cpu_to_le16(err_record
->dma_tx_err_type
);
2050 u16 sipc_rx_err_type
= cpu_to_le16(err_record
->sipc_rx_err_type
);
2051 u32 dma_rx_err_type
= cpu_to_le32(err_record
->dma_rx_err_type
);
2054 if (err_phase
== 1) {
2055 /* error in TX phase, the priority of error is: DW2 > DW0 */
2056 error
= parse_dma_tx_err_code_v2_hw(dma_tx_err_type
);
2058 error
= parse_trans_tx_err_code_v2_hw(
2059 trans_tx_fail_type
);
2060 } else if (err_phase
== 2) {
2061 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2062 error
= parse_trans_rx_err_code_v2_hw(
2063 trans_rx_fail_type
);
2065 error
= parse_dma_rx_err_code_v2_hw(
2068 error
= parse_sipc_rx_err_code_v2_hw(
2073 switch (task
->task_proto
) {
2074 case SAS_PROTOCOL_SSP
:
2077 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
:
2079 ts
->stat
= SAS_OPEN_REJECT
;
2080 ts
->open_rej_reason
= SAS_OREJ_NO_DEST
;
2083 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
:
2085 ts
->stat
= SAS_OPEN_REJECT
;
2086 ts
->open_rej_reason
= SAS_OREJ_EPROTO
;
2089 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
:
2091 ts
->stat
= SAS_OPEN_REJECT
;
2092 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
2095 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
:
2097 ts
->stat
= SAS_OPEN_REJECT
;
2098 ts
->open_rej_reason
= SAS_OREJ_BAD_DEST
;
2101 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
:
2103 ts
->stat
= SAS_OPEN_REJECT
;
2104 ts
->open_rej_reason
= SAS_OREJ_WRONG_DEST
;
2107 case DMA_RX_UNEXP_NORM_RESP_ERR
:
2108 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
:
2109 case DMA_RX_RESP_BUF_OVERFLOW
:
2111 ts
->stat
= SAS_OPEN_REJECT
;
2112 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
2115 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
:
2118 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2121 case DMA_RX_DATA_LEN_OVERFLOW
:
2123 ts
->stat
= SAS_DATA_OVERRUN
;
2127 case DMA_RX_DATA_LEN_UNDERFLOW
:
2129 ts
->residual
= trans_tx_fail_type
;
2130 ts
->stat
= SAS_DATA_UNDERRUN
;
2133 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
:
2134 case TRANS_TX_ERR_PHY_NOT_ENABLE
:
2135 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER
:
2136 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
:
2137 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
:
2138 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
:
2139 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
:
2140 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
:
2141 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT
:
2142 case TRANS_TX_ERR_WITH_BREAK_REQUEST
:
2143 case TRANS_TX_ERR_WITH_BREAK_RECEVIED
:
2144 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
:
2145 case TRANS_TX_ERR_WITH_CLOSE_NORMAL
:
2146 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
:
2147 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
2148 case TRANS_TX_ERR_WITH_CLOSE_COMINIT
:
2149 case TRANS_TX_ERR_WITH_NAK_RECEVIED
:
2150 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
:
2151 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
:
2152 case TRANS_TX_ERR_WITH_IPTT_CONFLICT
:
2153 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
:
2154 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
:
2155 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
:
2156 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
:
2157 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT
:
2158 case TRANS_RX_ERR_WITH_BREAK_REQUEST
:
2159 case TRANS_RX_ERR_WITH_BREAK_RECEVIED
:
2160 case TRANS_RX_ERR_WITH_CLOSE_NORMAL
:
2161 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
2162 case TRANS_RX_ERR_WITH_CLOSE_COMINIT
:
2163 case TRANS_TX_ERR_FRAME_TXED
:
2164 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
:
2165 case TRANS_RX_ERR_WITH_DATA_LEN0
:
2166 case TRANS_RX_ERR_WITH_BAD_HASH
:
2167 case TRANS_RX_XRDY_WLEN_ZERO_ERR
:
2168 case TRANS_RX_SSP_FRM_LEN_ERR
:
2169 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE
:
2170 case DMA_TX_DATA_SGL_OVERFLOW
:
2171 case DMA_TX_UNEXP_XFER_ERR
:
2172 case DMA_TX_UNEXP_RETRANS_ERR
:
2173 case DMA_TX_XFER_LEN_OVERFLOW
:
2174 case DMA_TX_XFER_OFFSET_ERR
:
2175 case SIPC_RX_DATA_UNDERFLOW_ERR
:
2176 case DMA_RX_DATA_SGL_OVERFLOW
:
2177 case DMA_RX_DATA_OFFSET_ERR
:
2178 case DMA_RX_RDSETUP_LEN_ODD_ERR
:
2179 case DMA_RX_RDSETUP_LEN_ZERO_ERR
:
2180 case DMA_RX_RDSETUP_LEN_OVER_ERR
:
2181 case DMA_RX_SATA_FRAME_TYPE_ERR
:
2182 case DMA_RX_UNKNOWN_FRM_ERR
:
2184 /* This will request a retry */
2185 ts
->stat
= SAS_QUEUE_FULL
;
2194 case SAS_PROTOCOL_SMP
:
2195 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
2198 case SAS_PROTOCOL_SATA
:
2199 case SAS_PROTOCOL_STP
:
2200 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
2203 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
:
2205 ts
->stat
= SAS_OPEN_REJECT
;
2206 ts
->open_rej_reason
= SAS_OREJ_NO_DEST
;
2209 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
:
2211 ts
->resp
= SAS_TASK_UNDELIVERED
;
2212 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2215 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
:
2217 ts
->stat
= SAS_OPEN_REJECT
;
2218 ts
->open_rej_reason
= SAS_OREJ_EPROTO
;
2221 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
:
2223 ts
->stat
= SAS_OPEN_REJECT
;
2224 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
2227 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
:
2229 ts
->stat
= SAS_OPEN_REJECT
;
2230 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
2233 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
:
2235 ts
->stat
= SAS_OPEN_REJECT
;
2236 ts
->open_rej_reason
= SAS_OREJ_WRONG_DEST
;
2239 case DMA_RX_RESP_BUF_OVERFLOW
:
2240 case DMA_RX_UNEXP_NORM_RESP_ERR
:
2241 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
:
2243 ts
->stat
= SAS_OPEN_REJECT
;
2244 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
2247 case DMA_RX_DATA_LEN_OVERFLOW
:
2249 ts
->stat
= SAS_DATA_OVERRUN
;
2253 case DMA_RX_DATA_LEN_UNDERFLOW
:
2255 ts
->residual
= trans_tx_fail_type
;
2256 ts
->stat
= SAS_DATA_UNDERRUN
;
2259 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
:
2260 case TRANS_TX_ERR_PHY_NOT_ENABLE
:
2261 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER
:
2262 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
:
2263 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
:
2264 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
:
2265 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
:
2266 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
:
2267 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT
:
2268 case TRANS_TX_ERR_WITH_BREAK_REQUEST
:
2269 case TRANS_TX_ERR_WITH_BREAK_RECEVIED
:
2270 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
:
2271 case TRANS_TX_ERR_WITH_CLOSE_NORMAL
:
2272 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
:
2273 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
2274 case TRANS_TX_ERR_WITH_CLOSE_COMINIT
:
2275 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
:
2276 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
:
2277 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS
:
2278 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
:
2279 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
:
2280 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
:
2281 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
:
2282 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
:
2283 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
:
2284 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
:
2285 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
:
2286 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT
:
2287 case TRANS_RX_ERR_WITH_BREAK_REQUEST
:
2288 case TRANS_RX_ERR_WITH_BREAK_RECEVIED
:
2289 case TRANS_RX_ERR_WITH_CLOSE_NORMAL
:
2290 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
:
2291 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
2292 case TRANS_RX_ERR_WITH_CLOSE_COMINIT
:
2293 case TRANS_RX_ERR_WITH_DATA_LEN0
:
2294 case TRANS_RX_ERR_WITH_BAD_HASH
:
2295 case TRANS_RX_XRDY_WLEN_ZERO_ERR
:
2296 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE
:
2297 case DMA_TX_DATA_SGL_OVERFLOW
:
2298 case DMA_TX_UNEXP_XFER_ERR
:
2299 case DMA_TX_UNEXP_RETRANS_ERR
:
2300 case DMA_TX_XFER_LEN_OVERFLOW
:
2301 case DMA_TX_XFER_OFFSET_ERR
:
2302 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD
:
2303 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR
:
2304 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR
:
2305 case SIPC_RX_WRSETUP_LEN_ODD_ERR
:
2306 case SIPC_RX_WRSETUP_LEN_ZERO_ERR
:
2307 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR
:
2308 case SIPC_RX_SATA_UNEXP_FIS_ERR
:
2309 case DMA_RX_DATA_SGL_OVERFLOW
:
2310 case DMA_RX_DATA_OFFSET_ERR
:
2311 case DMA_RX_SATA_FRAME_TYPE_ERR
:
2312 case DMA_RX_UNEXP_RDFRAME_ERR
:
2313 case DMA_RX_PIO_DATA_LEN_ERR
:
2314 case DMA_RX_RDSETUP_STATUS_ERR
:
2315 case DMA_RX_RDSETUP_STATUS_DRQ_ERR
:
2316 case DMA_RX_RDSETUP_STATUS_BSY_ERR
:
2317 case DMA_RX_RDSETUP_LEN_ODD_ERR
:
2318 case DMA_RX_RDSETUP_LEN_ZERO_ERR
:
2319 case DMA_RX_RDSETUP_LEN_OVER_ERR
:
2320 case DMA_RX_RDSETUP_OFFSET_ERR
:
2321 case DMA_RX_RDSETUP_ACTIVE_ERR
:
2322 case DMA_RX_RDSETUP_ESTATUS_ERR
:
2323 case DMA_RX_UNKNOWN_FRM_ERR
:
2324 case TRANS_RX_SSP_FRM_LEN_ERR
:
2325 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
:
2328 ts
->stat
= SAS_PHY_DOWN
;
2333 ts
->stat
= SAS_PROTO_RESPONSE
;
2337 hisi_sas_sata_done(task
, slot
);
2346 slot_complete_v2_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_slot
*slot
)
2348 struct sas_task
*task
= slot
->task
;
2349 struct hisi_sas_device
*sas_dev
;
2350 struct device
*dev
= hisi_hba
->dev
;
2351 struct task_status_struct
*ts
;
2352 struct domain_device
*device
;
2353 struct sas_ha_struct
*ha
;
2354 enum exec_status sts
;
2355 struct hisi_sas_complete_v2_hdr
*complete_queue
=
2356 hisi_hba
->complete_hdr
[slot
->cmplt_queue
];
2357 struct hisi_sas_complete_v2_hdr
*complete_hdr
=
2358 &complete_queue
[slot
->cmplt_queue_slot
];
2359 unsigned long flags
;
2360 bool is_internal
= slot
->is_internal
;
2362 if (unlikely(!task
|| !task
->lldd_task
|| !task
->dev
))
2365 ts
= &task
->task_status
;
2367 ha
= device
->port
->ha
;
2368 sas_dev
= device
->lldd_dev
;
2370 spin_lock_irqsave(&task
->task_state_lock
, flags
);
2371 task
->task_state_flags
&=
2372 ~(SAS_TASK_STATE_PENDING
| SAS_TASK_AT_INITIATOR
);
2373 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
2375 memset(ts
, 0, sizeof(*ts
));
2376 ts
->resp
= SAS_TASK_COMPLETE
;
2378 if (unlikely(!sas_dev
)) {
2379 dev_dbg(dev
, "slot complete: port has no device\n");
2380 ts
->stat
= SAS_PHY_DOWN
;
2384 /* Use SAS+TMF status codes */
2385 switch ((complete_hdr
->dw0
& CMPLT_HDR_ABORT_STAT_MSK
)
2386 >> CMPLT_HDR_ABORT_STAT_OFF
) {
2387 case STAT_IO_ABORTED
:
2388 /* this io has been aborted by abort command */
2389 ts
->stat
= SAS_ABORTED_TASK
;
2391 case STAT_IO_COMPLETE
:
2392 /* internal abort command complete */
2393 ts
->stat
= TMF_RESP_FUNC_SUCC
;
2394 del_timer(&slot
->internal_abort_timer
);
2396 case STAT_IO_NO_DEVICE
:
2397 ts
->stat
= TMF_RESP_FUNC_COMPLETE
;
2398 del_timer(&slot
->internal_abort_timer
);
2400 case STAT_IO_NOT_VALID
:
2401 /* abort single io, controller don't find
2402 * the io need to abort
2404 ts
->stat
= TMF_RESP_FUNC_FAILED
;
2405 del_timer(&slot
->internal_abort_timer
);
2411 if ((complete_hdr
->dw0
& CMPLT_HDR_ERX_MSK
) &&
2412 (!(complete_hdr
->dw0
& CMPLT_HDR_RSPNS_XFRD_MSK
))) {
2413 u32 err_phase
= (complete_hdr
->dw0
& CMPLT_HDR_ERR_PHASE_MSK
)
2414 >> CMPLT_HDR_ERR_PHASE_OFF
;
2415 u32
*error_info
= hisi_sas_status_buf_addr_mem(slot
);
2417 /* Analyse error happens on which phase TX or RX */
2418 if (ERR_ON_TX_PHASE(err_phase
))
2419 slot_err_v2_hw(hisi_hba
, task
, slot
, 1);
2420 else if (ERR_ON_RX_PHASE(err_phase
))
2421 slot_err_v2_hw(hisi_hba
, task
, slot
, 2);
2423 if (ts
->stat
!= SAS_DATA_UNDERRUN
)
2424 dev_info(dev
, "erroneous completion iptt=%d task=%p dev id=%d "
2425 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
2426 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
2427 slot
->idx
, task
, sas_dev
->device_id
,
2428 complete_hdr
->dw0
, complete_hdr
->dw1
,
2429 complete_hdr
->act
, complete_hdr
->dw3
,
2430 error_info
[0], error_info
[1],
2431 error_info
[2], error_info
[3]);
2433 if (unlikely(slot
->abort
))
2438 switch (task
->task_proto
) {
2439 case SAS_PROTOCOL_SSP
:
2441 struct hisi_sas_status_buffer
*status_buffer
=
2442 hisi_sas_status_buf_addr_mem(slot
);
2443 struct ssp_response_iu
*iu
= (struct ssp_response_iu
*)
2444 &status_buffer
->iu
[0];
2446 sas_ssp_task_response(dev
, task
, iu
);
2449 case SAS_PROTOCOL_SMP
:
2451 struct scatterlist
*sg_resp
= &task
->smp_task
.smp_resp
;
2454 ts
->stat
= SAM_STAT_GOOD
;
2455 to
= kmap_atomic(sg_page(sg_resp
));
2457 dma_unmap_sg(dev
, &task
->smp_task
.smp_resp
, 1,
2459 dma_unmap_sg(dev
, &task
->smp_task
.smp_req
, 1,
2461 memcpy(to
+ sg_resp
->offset
,
2462 hisi_sas_status_buf_addr_mem(slot
) +
2463 sizeof(struct hisi_sas_err_record
),
2464 sg_dma_len(sg_resp
));
2468 case SAS_PROTOCOL_SATA
:
2469 case SAS_PROTOCOL_STP
:
2470 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
2472 ts
->stat
= SAM_STAT_GOOD
;
2473 hisi_sas_sata_done(task
, slot
);
2477 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
2481 if (!slot
->port
->port_attached
) {
2482 dev_warn(dev
, "slot complete: port %d has removed\n",
2483 slot
->port
->sas_port
.id
);
2484 ts
->stat
= SAS_PHY_DOWN
;
2489 spin_lock_irqsave(&task
->task_state_lock
, flags
);
2490 if (task
->task_state_flags
& SAS_TASK_STATE_ABORTED
) {
2491 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
2492 dev_info(dev
, "slot complete: task(%p) aborted\n", task
);
2493 return SAS_ABORTED_TASK
;
2495 task
->task_state_flags
|= SAS_TASK_STATE_DONE
;
2496 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
2497 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
2499 if (!is_internal
&& (task
->task_proto
!= SAS_PROTOCOL_SMP
)) {
2500 spin_lock_irqsave(&device
->done_lock
, flags
);
2501 if (test_bit(SAS_HA_FROZEN
, &ha
->state
)) {
2502 spin_unlock_irqrestore(&device
->done_lock
, flags
);
2503 dev_info(dev
, "slot complete: task(%p) ignored\n ",
2507 spin_unlock_irqrestore(&device
->done_lock
, flags
);
2510 if (task
->task_done
)
2511 task
->task_done(task
);
2516 static void prep_ata_v2_hw(struct hisi_hba
*hisi_hba
,
2517 struct hisi_sas_slot
*slot
)
2519 struct sas_task
*task
= slot
->task
;
2520 struct domain_device
*device
= task
->dev
;
2521 struct domain_device
*parent_dev
= device
->parent
;
2522 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
2523 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
2524 struct asd_sas_port
*sas_port
= device
->port
;
2525 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
2526 struct hisi_sas_tmf_task
*tmf
= slot
->tmf
;
2528 int has_data
= 0, hdr_tag
= 0;
2529 u32 dw1
= 0, dw2
= 0;
2533 hdr
->dw0
= cpu_to_le32(port
->id
<< CMD_HDR_PORT_OFF
);
2534 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
2535 hdr
->dw0
|= cpu_to_le32(3 << CMD_HDR_CMD_OFF
);
2537 hdr
->dw0
|= cpu_to_le32(4 << CMD_HDR_CMD_OFF
);
2539 if (tmf
&& tmf
->force_phy
) {
2540 hdr
->dw0
|= CMD_HDR_FORCE_PHY_MSK
;
2541 hdr
->dw0
|= cpu_to_le32((1 << tmf
->phy_id
)
2542 << CMD_HDR_PHY_ID_OFF
);
2546 switch (task
->data_dir
) {
2549 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
2551 case DMA_FROM_DEVICE
:
2553 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
2556 dw1
&= ~CMD_HDR_DIR_MSK
;
2559 if ((task
->ata_task
.fis
.command
== ATA_CMD_DEV_RESET
) &&
2560 (task
->ata_task
.fis
.control
& ATA_SRST
))
2561 dw1
|= 1 << CMD_HDR_RESET_OFF
;
2563 dw1
|= (hisi_sas_get_ata_protocol(
2564 &task
->ata_task
.fis
, task
->data_dir
))
2565 << CMD_HDR_FRAME_TYPE_OFF
;
2566 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
2567 hdr
->dw1
= cpu_to_le32(dw1
);
2570 if (task
->ata_task
.use_ncq
&& hisi_sas_get_ncq_tag(task
, &hdr_tag
)) {
2571 task
->ata_task
.fis
.sector_count
|= (u8
) (hdr_tag
<< 3);
2572 dw2
|= hdr_tag
<< CMD_HDR_NCQ_TAG_OFF
;
2575 dw2
|= (HISI_SAS_MAX_STP_RESP_SZ
/ 4) << CMD_HDR_CFL_OFF
|
2576 2 << CMD_HDR_SG_MOD_OFF
;
2577 hdr
->dw2
= cpu_to_le32(dw2
);
2580 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
2583 prep_prd_sge_v2_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
2586 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
2587 hdr
->cmd_table_addr
= cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot
));
2588 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
2590 buf_cmd
= hisi_sas_cmd_hdr_addr_mem(slot
);
2592 if (likely(!task
->ata_task
.device_control_reg_update
))
2593 task
->ata_task
.fis
.flags
|= 0x80; /* C=1: update ATA cmd reg */
2594 /* fill in command FIS */
2595 memcpy(buf_cmd
, &task
->ata_task
.fis
, sizeof(struct host_to_dev_fis
));
2598 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list
*t
)
2600 struct hisi_sas_slot
*slot
= from_timer(slot
, t
, internal_abort_timer
);
2601 struct hisi_sas_port
*port
= slot
->port
;
2602 struct asd_sas_port
*asd_sas_port
;
2603 struct asd_sas_phy
*sas_phy
;
2608 asd_sas_port
= &port
->sas_port
;
2610 /* Kick the hardware - send break command */
2611 list_for_each_entry(sas_phy
, &asd_sas_port
->phy_list
, port_phy_el
) {
2612 struct hisi_sas_phy
*phy
= sas_phy
->lldd_phy
;
2613 struct hisi_hba
*hisi_hba
= phy
->hisi_hba
;
2614 int phy_no
= sas_phy
->id
;
2617 link_dfx2
= hisi_sas_phy_read32(hisi_hba
, phy_no
, LINK_DFX2
);
2618 if ((link_dfx2
== LINK_DFX2_RCVR_HOLD_STS_MSK
) ||
2619 (link_dfx2
& LINK_DFX2_SEND_HOLD_STS_MSK
)) {
2622 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2624 txid_auto
|= TXID_AUTO_CTB_MSK
;
2625 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
2632 static void prep_abort_v2_hw(struct hisi_hba
*hisi_hba
,
2633 struct hisi_sas_slot
*slot
,
2634 int device_id
, int abort_flag
, int tag_to_abort
)
2636 struct sas_task
*task
= slot
->task
;
2637 struct domain_device
*dev
= task
->dev
;
2638 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
2639 struct hisi_sas_port
*port
= slot
->port
;
2640 struct timer_list
*timer
= &slot
->internal_abort_timer
;
2642 /* setup the quirk timer */
2643 timer_setup(timer
, hisi_sas_internal_abort_quirk_timeout
, 0);
2644 /* Set the timeout to 10ms less than internal abort timeout */
2645 mod_timer(timer
, jiffies
+ msecs_to_jiffies(100));
2648 hdr
->dw0
= cpu_to_le32((5 << CMD_HDR_CMD_OFF
) | /*abort*/
2649 (port
->id
<< CMD_HDR_PORT_OFF
) |
2650 (dev_is_sata(dev
) <<
2651 CMD_HDR_ABORT_DEVICE_TYPE_OFF
) |
2652 (abort_flag
<< CMD_HDR_ABORT_FLAG_OFF
));
2655 hdr
->dw1
= cpu_to_le32(device_id
<< CMD_HDR_DEV_ID_OFF
);
2658 hdr
->dw7
= cpu_to_le32(tag_to_abort
<< CMD_HDR_ABORT_IPTT_OFF
);
2659 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
2662 static int phy_up_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2664 int i
, res
= IRQ_HANDLED
;
2665 u32 port_id
, link_rate
;
2666 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2667 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
2668 struct device
*dev
= hisi_hba
->dev
;
2669 u32
*frame_rcvd
= (u32
*)sas_phy
->frame_rcvd
;
2670 struct sas_identify_frame
*id
= (struct sas_identify_frame
*)frame_rcvd
;
2671 unsigned long flags
;
2673 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 1);
2675 if (is_sata_phy_v2_hw(hisi_hba
, phy_no
))
2679 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
2681 port_id
= (port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
2682 PORT_STATE_PHY8_PORT_NUM_OFF
;
2683 link_rate
= (port_state
& PORT_STATE_PHY8_CONN_RATE_MSK
) >>
2684 PORT_STATE_PHY8_CONN_RATE_OFF
;
2686 port_id
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
2687 port_id
= (port_id
>> (4 * phy_no
)) & 0xf;
2688 link_rate
= hisi_sas_read32(hisi_hba
, PHY_CONN_RATE
);
2689 link_rate
= (link_rate
>> (phy_no
* 4)) & 0xf;
2692 if (port_id
== 0xf) {
2693 dev_err(dev
, "phyup: phy%d invalid portid\n", phy_no
);
2698 for (i
= 0; i
< 6; i
++) {
2699 u32 idaf
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2700 RX_IDAF_DWORD0
+ (i
* 4));
2701 frame_rcvd
[i
] = __swab32(idaf
);
2704 sas_phy
->linkrate
= link_rate
;
2705 sas_phy
->oob_mode
= SAS_OOB_MODE
;
2706 memcpy(sas_phy
->attached_sas_addr
, &id
->sas_addr
, SAS_ADDR_SIZE
);
2707 dev_info(dev
, "phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
2708 phy
->port_id
= port_id
;
2709 phy
->phy_type
&= ~(PORT_TYPE_SAS
| PORT_TYPE_SATA
);
2710 phy
->phy_type
|= PORT_TYPE_SAS
;
2711 phy
->phy_attached
= 1;
2712 phy
->identify
.device_type
= id
->dev_type
;
2713 phy
->frame_rcvd_size
= sizeof(struct sas_identify_frame
);
2714 if (phy
->identify
.device_type
== SAS_END_DEVICE
)
2715 phy
->identify
.target_port_protocols
=
2717 else if (phy
->identify
.device_type
!= SAS_PHY_UNUSED
) {
2718 phy
->identify
.target_port_protocols
=
2720 if (!timer_pending(&hisi_hba
->timer
))
2721 set_link_timer_quirk(hisi_hba
);
2723 hisi_sas_notify_phy_event(phy
, HISI_PHYE_PHY_UP
);
2724 spin_lock_irqsave(&phy
->lock
, flags
);
2725 if (phy
->reset_completion
) {
2727 complete(phy
->reset_completion
);
2729 spin_unlock_irqrestore(&phy
->lock
, flags
);
2732 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
2733 CHL_INT0_SL_PHY_ENABLE_MSK
);
2734 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 0);
2739 static bool check_any_wideports_v2_hw(struct hisi_hba
*hisi_hba
)
2743 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
2744 if (port_state
& 0x1ff)
2750 static int phy_down_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2752 u32 phy_state
, sl_ctrl
, txid_auto
;
2753 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2754 struct hisi_sas_port
*port
= phy
->port
;
2755 struct device
*dev
= hisi_hba
->dev
;
2757 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 1);
2759 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
2760 dev_info(dev
, "phydown: phy%d phy_state=0x%x\n", phy_no
, phy_state
);
2761 hisi_sas_phy_down(hisi_hba
, phy_no
, (phy_state
& 1 << phy_no
) ? 1 : 0);
2763 sl_ctrl
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
2764 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
,
2765 sl_ctrl
& ~SL_CONTROL_CTA_MSK
);
2766 if (port
&& !get_wideport_bitmap_v2_hw(hisi_hba
, port
->id
))
2767 if (!check_any_wideports_v2_hw(hisi_hba
) &&
2768 timer_pending(&hisi_hba
->timer
))
2769 del_timer(&hisi_hba
->timer
);
2771 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
2772 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
2773 txid_auto
| TXID_AUTO_CT3_MSK
);
2775 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
, CHL_INT0_NOT_RDY_MSK
);
2776 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 0);
2781 static irqreturn_t
int_phy_updown_v2_hw(int irq_no
, void *p
)
2783 struct hisi_hba
*hisi_hba
= p
;
2786 irqreturn_t res
= IRQ_NONE
;
2788 irq_msk
= (hisi_sas_read32(hisi_hba
, HGC_INVLD_DQE_INFO
)
2789 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF
) & 0x1ff;
2792 u32 reg_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2795 switch (reg_value
& (CHL_INT0_NOT_RDY_MSK
|
2796 CHL_INT0_SL_PHY_ENABLE_MSK
)) {
2798 case CHL_INT0_SL_PHY_ENABLE_MSK
:
2800 if (phy_up_v2_hw(phy_no
, hisi_hba
) ==
2805 case CHL_INT0_NOT_RDY_MSK
:
2807 if (phy_down_v2_hw(phy_no
, hisi_hba
) ==
2812 case (CHL_INT0_NOT_RDY_MSK
|
2813 CHL_INT0_SL_PHY_ENABLE_MSK
):
2814 reg_value
= hisi_sas_read32(hisi_hba
,
2816 if (reg_value
& BIT(phy_no
)) {
2818 if (phy_up_v2_hw(phy_no
, hisi_hba
) ==
2823 if (phy_down_v2_hw(phy_no
, hisi_hba
) ==
2841 static void phy_bcast_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2843 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2844 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
2845 struct sas_ha_struct
*sas_ha
= &hisi_hba
->sha
;
2848 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 1);
2849 bcast_status
= hisi_sas_phy_read32(hisi_hba
, phy_no
, RX_PRIMS_STATUS
);
2850 if ((bcast_status
& RX_BCAST_CHG_MSK
) &&
2851 !test_bit(HISI_SAS_RESET_BIT
, &hisi_hba
->flags
))
2852 sas_ha
->notify_port_event(sas_phy
, PORTE_BROADCAST_RCVD
);
2853 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
2854 CHL_INT0_SL_RX_BCST_ACK_MSK
);
2855 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 0);
2858 static const struct hisi_sas_hw_error port_ecc_axi_error
[] = {
2860 .irq_msk
= BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF
),
2861 .msg
= "dmac_tx_ecc_bad_err",
2864 .irq_msk
= BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF
),
2865 .msg
= "dmac_rx_ecc_bad_err",
2868 .irq_msk
= BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF
),
2869 .msg
= "dma_tx_axi_wr_err",
2872 .irq_msk
= BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF
),
2873 .msg
= "dma_tx_axi_rd_err",
2876 .irq_msk
= BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF
),
2877 .msg
= "dma_rx_axi_wr_err",
2880 .irq_msk
= BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF
),
2881 .msg
= "dma_rx_axi_rd_err",
2885 static irqreturn_t
int_chnl_int_v2_hw(int irq_no
, void *p
)
2887 struct hisi_hba
*hisi_hba
= p
;
2888 struct device
*dev
= hisi_hba
->dev
;
2889 u32 ent_msk
, ent_tmp
, irq_msk
;
2892 ent_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
2894 ent_msk
|= ENT_INT_SRC_MSK3_ENT95_MSK_MSK
;
2895 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_msk
);
2897 irq_msk
= (hisi_sas_read32(hisi_hba
, HGC_INVLD_DQE_INFO
) >>
2898 HGC_INVLD_DQE_INFO_FB_CH3_OFF
) & 0x1ff;
2901 u32 irq_value0
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2903 u32 irq_value1
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2905 u32 irq_value2
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2908 if ((irq_msk
& (1 << phy_no
)) && irq_value1
) {
2911 for (i
= 0; i
< ARRAY_SIZE(port_ecc_axi_error
); i
++) {
2912 const struct hisi_sas_hw_error
*error
=
2913 &port_ecc_axi_error
[i
];
2915 if (!(irq_value1
& error
->irq_msk
))
2918 dev_warn(dev
, "%s error (phy%d 0x%x) found!\n",
2919 error
->msg
, phy_no
, irq_value1
);
2920 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
2923 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2924 CHL_INT1
, irq_value1
);
2927 if ((irq_msk
& (1 << phy_no
)) && irq_value2
) {
2928 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2930 if (irq_value2
& BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF
)) {
2931 dev_warn(dev
, "phy%d identify timeout\n",
2933 hisi_sas_notify_phy_event(phy
,
2934 HISI_PHYE_LINK_RESET
);
2937 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2938 CHL_INT2
, irq_value2
);
2941 if ((irq_msk
& (1 << phy_no
)) && irq_value0
) {
2942 if (irq_value0
& CHL_INT0_SL_RX_BCST_ACK_MSK
)
2943 phy_bcast_v2_hw(phy_no
, hisi_hba
);
2945 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2946 CHL_INT0
, irq_value0
2947 & (~CHL_INT0_HOTPLUG_TOUT_MSK
)
2948 & (~CHL_INT0_SL_PHY_ENABLE_MSK
)
2949 & (~CHL_INT0_NOT_RDY_MSK
));
2951 irq_msk
&= ~(1 << phy_no
);
2955 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_tmp
);
2961 one_bit_ecc_error_process_v2_hw(struct hisi_hba
*hisi_hba
, u32 irq_value
)
2963 struct device
*dev
= hisi_hba
->dev
;
2964 const struct hisi_sas_hw_error
*ecc_error
;
2968 for (i
= 0; i
< ARRAY_SIZE(one_bit_ecc_errors
); i
++) {
2969 ecc_error
= &one_bit_ecc_errors
[i
];
2970 if (irq_value
& ecc_error
->irq_msk
) {
2971 val
= hisi_sas_read32(hisi_hba
, ecc_error
->reg
);
2972 val
&= ecc_error
->msk
;
2973 val
>>= ecc_error
->shift
;
2974 dev_warn(dev
, ecc_error
->msg
, val
);
2979 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba
*hisi_hba
,
2982 struct device
*dev
= hisi_hba
->dev
;
2983 const struct hisi_sas_hw_error
*ecc_error
;
2987 for (i
= 0; i
< ARRAY_SIZE(multi_bit_ecc_errors
); i
++) {
2988 ecc_error
= &multi_bit_ecc_errors
[i
];
2989 if (irq_value
& ecc_error
->irq_msk
) {
2990 val
= hisi_sas_read32(hisi_hba
, ecc_error
->reg
);
2991 val
&= ecc_error
->msk
;
2992 val
>>= ecc_error
->shift
;
2993 dev_err(dev
, ecc_error
->msg
, irq_value
, val
);
2994 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
3001 static irqreturn_t
fatal_ecc_int_v2_hw(int irq_no
, void *p
)
3003 struct hisi_hba
*hisi_hba
= p
;
3004 u32 irq_value
, irq_msk
;
3006 irq_msk
= hisi_sas_read32(hisi_hba
, SAS_ECC_INTR_MSK
);
3007 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, irq_msk
| 0xffffffff);
3009 irq_value
= hisi_sas_read32(hisi_hba
, SAS_ECC_INTR
);
3011 one_bit_ecc_error_process_v2_hw(hisi_hba
, irq_value
);
3012 multi_bit_ecc_error_process_v2_hw(hisi_hba
, irq_value
);
3015 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR
, irq_value
);
3016 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, irq_msk
);
3021 static const struct hisi_sas_hw_error axi_error
[] = {
3022 { .msk
= BIT(0), .msg
= "IOST_AXI_W_ERR" },
3023 { .msk
= BIT(1), .msg
= "IOST_AXI_R_ERR" },
3024 { .msk
= BIT(2), .msg
= "ITCT_AXI_W_ERR" },
3025 { .msk
= BIT(3), .msg
= "ITCT_AXI_R_ERR" },
3026 { .msk
= BIT(4), .msg
= "SATA_AXI_W_ERR" },
3027 { .msk
= BIT(5), .msg
= "SATA_AXI_R_ERR" },
3028 { .msk
= BIT(6), .msg
= "DQE_AXI_R_ERR" },
3029 { .msk
= BIT(7), .msg
= "CQE_AXI_W_ERR" },
3033 static const struct hisi_sas_hw_error fifo_error
[] = {
3034 { .msk
= BIT(8), .msg
= "CQE_WINFO_FIFO" },
3035 { .msk
= BIT(9), .msg
= "CQE_MSG_FIFIO" },
3036 { .msk
= BIT(10), .msg
= "GETDQE_FIFO" },
3037 { .msk
= BIT(11), .msg
= "CMDP_FIFO" },
3038 { .msk
= BIT(12), .msg
= "AWTCTRL_FIFO" },
3042 static const struct hisi_sas_hw_error fatal_axi_errors
[] = {
3044 .irq_msk
= BIT(ENT_INT_SRC3_WP_DEPTH_OFF
),
3045 .msg
= "write pointer and depth",
3048 .irq_msk
= BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF
),
3049 .msg
= "iptt no match slot",
3052 .irq_msk
= BIT(ENT_INT_SRC3_RP_DEPTH_OFF
),
3053 .msg
= "read pointer and depth",
3056 .irq_msk
= BIT(ENT_INT_SRC3_AXI_OFF
),
3057 .reg
= HGC_AXI_FIFO_ERR_INFO
,
3061 .irq_msk
= BIT(ENT_INT_SRC3_FIFO_OFF
),
3062 .reg
= HGC_AXI_FIFO_ERR_INFO
,
3066 .irq_msk
= BIT(ENT_INT_SRC3_LM_OFF
),
3067 .msg
= "LM add/fetch list",
3070 .irq_msk
= BIT(ENT_INT_SRC3_ABT_OFF
),
3071 .msg
= "SAS_HGC_ABT fetch LM list",
3075 static irqreturn_t
fatal_axi_int_v2_hw(int irq_no
, void *p
)
3077 struct hisi_hba
*hisi_hba
= p
;
3078 u32 irq_value
, irq_msk
, err_value
;
3079 struct device
*dev
= hisi_hba
->dev
;
3080 const struct hisi_sas_hw_error
*axi_error
;
3083 irq_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
3084 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, irq_msk
| 0xfffffffe);
3086 irq_value
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
3088 for (i
= 0; i
< ARRAY_SIZE(fatal_axi_errors
); i
++) {
3089 axi_error
= &fatal_axi_errors
[i
];
3090 if (!(irq_value
& axi_error
->irq_msk
))
3093 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
3094 1 << axi_error
->shift
);
3095 if (axi_error
->sub
) {
3096 const struct hisi_sas_hw_error
*sub
= axi_error
->sub
;
3098 err_value
= hisi_sas_read32(hisi_hba
, axi_error
->reg
);
3099 for (; sub
->msk
|| sub
->msg
; sub
++) {
3100 if (!(err_value
& sub
->msk
))
3102 dev_err(dev
, "%s (0x%x) found!\n",
3103 sub
->msg
, irq_value
);
3104 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
3107 dev_err(dev
, "%s (0x%x) found!\n",
3108 axi_error
->msg
, irq_value
);
3109 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
3113 if (irq_value
& BIT(ENT_INT_SRC3_ITC_INT_OFF
)) {
3114 u32 reg_val
= hisi_sas_read32(hisi_hba
, ITCT_CLR
);
3115 u32 dev_id
= reg_val
& ITCT_DEV_MSK
;
3116 struct hisi_sas_device
*sas_dev
= &hisi_hba
->devices
[dev_id
];
3118 hisi_sas_write32(hisi_hba
, ITCT_CLR
, 0);
3119 dev_dbg(dev
, "clear ITCT ok\n");
3120 complete(sas_dev
->completion
);
3123 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
, irq_value
);
3124 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, irq_msk
);
3129 static void cq_tasklet_v2_hw(unsigned long val
)
3131 struct hisi_sas_cq
*cq
= (struct hisi_sas_cq
*)val
;
3132 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
3133 struct hisi_sas_slot
*slot
;
3134 struct hisi_sas_itct
*itct
;
3135 struct hisi_sas_complete_v2_hdr
*complete_queue
;
3136 u32 rd_point
= cq
->rd_point
, wr_point
, dev_id
;
3139 if (unlikely(hisi_hba
->reject_stp_links_msk
))
3140 phys_try_accept_stp_links_v2_hw(hisi_hba
);
3142 complete_queue
= hisi_hba
->complete_hdr
[queue
];
3144 wr_point
= hisi_sas_read32(hisi_hba
, COMPL_Q_0_WR_PTR
+
3147 while (rd_point
!= wr_point
) {
3148 struct hisi_sas_complete_v2_hdr
*complete_hdr
;
3151 complete_hdr
= &complete_queue
[rd_point
];
3153 /* Check for NCQ completion */
3154 if (complete_hdr
->act
) {
3155 u32 act_tmp
= complete_hdr
->act
;
3156 int ncq_tag_count
= ffs(act_tmp
);
3158 dev_id
= (complete_hdr
->dw1
& CMPLT_HDR_DEV_ID_MSK
) >>
3159 CMPLT_HDR_DEV_ID_OFF
;
3160 itct
= &hisi_hba
->itct
[dev_id
];
3162 /* The NCQ tags are held in the itct header */
3163 while (ncq_tag_count
) {
3164 __le64
*ncq_tag
= &itct
->qw4_15
[0];
3167 iptt
= (ncq_tag
[ncq_tag_count
/ 5]
3168 >> (ncq_tag_count
% 5) * 12) & 0xfff;
3170 slot
= &hisi_hba
->slot_info
[iptt
];
3171 slot
->cmplt_queue_slot
= rd_point
;
3172 slot
->cmplt_queue
= queue
;
3173 slot_complete_v2_hw(hisi_hba
, slot
);
3175 act_tmp
&= ~(1 << ncq_tag_count
);
3176 ncq_tag_count
= ffs(act_tmp
);
3179 iptt
= (complete_hdr
->dw1
) & CMPLT_HDR_IPTT_MSK
;
3180 slot
= &hisi_hba
->slot_info
[iptt
];
3181 slot
->cmplt_queue_slot
= rd_point
;
3182 slot
->cmplt_queue
= queue
;
3183 slot_complete_v2_hw(hisi_hba
, slot
);
3186 if (++rd_point
>= HISI_SAS_QUEUE_SLOTS
)
3190 /* update rd_point */
3191 cq
->rd_point
= rd_point
;
3192 hisi_sas_write32(hisi_hba
, COMPL_Q_0_RD_PTR
+ (0x14 * queue
), rd_point
);
3195 static irqreturn_t
cq_interrupt_v2_hw(int irq_no
, void *p
)
3197 struct hisi_sas_cq
*cq
= p
;
3198 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
3201 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 1 << queue
);
3203 tasklet_schedule(&cq
->tasklet
);
3208 static irqreturn_t
sata_int_v2_hw(int irq_no
, void *p
)
3210 struct hisi_sas_phy
*phy
= p
;
3211 struct hisi_hba
*hisi_hba
= phy
->hisi_hba
;
3212 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
3213 struct device
*dev
= hisi_hba
->dev
;
3214 struct hisi_sas_initial_fis
*initial_fis
;
3215 struct dev_to_host_fis
*fis
;
3216 u32 ent_tmp
, ent_msk
, ent_int
, port_id
, link_rate
, hard_phy_linkrate
;
3217 irqreturn_t res
= IRQ_HANDLED
;
3218 u8 attached_sas_addr
[SAS_ADDR_SIZE
] = {0};
3219 unsigned long flags
;
3222 phy_no
= sas_phy
->id
;
3223 initial_fis
= &hisi_hba
->initial_fis
[phy_no
];
3224 fis
= &initial_fis
->fis
;
3226 offset
= 4 * (phy_no
/ 4);
3227 ent_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
);
3228 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
,
3229 ent_msk
| 1 << ((phy_no
% 4) * 8));
3231 ent_int
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC1
+ offset
);
3232 ent_tmp
= ent_int
& (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF
*
3234 ent_int
>>= ENT_INT_SRC1_D2H_FIS_CH1_OFF
* (phy_no
% 4);
3235 if ((ent_int
& ENT_INT_SRC1_D2H_FIS_CH0_MSK
) == 0) {
3236 dev_warn(dev
, "sata int: phy%d did not receive FIS\n", phy_no
);
3241 /* check ERR bit of Status Register */
3242 if (fis
->status
& ATA_ERR
) {
3243 dev_warn(dev
, "sata int: phy%d FIS status: 0x%x\n", phy_no
,
3245 hisi_sas_notify_phy_event(phy
, HISI_PHYE_LINK_RESET
);
3250 if (unlikely(phy_no
== 8)) {
3251 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
3253 port_id
= (port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
3254 PORT_STATE_PHY8_PORT_NUM_OFF
;
3255 link_rate
= (port_state
& PORT_STATE_PHY8_CONN_RATE_MSK
) >>
3256 PORT_STATE_PHY8_CONN_RATE_OFF
;
3258 port_id
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
3259 port_id
= (port_id
>> (4 * phy_no
)) & 0xf;
3260 link_rate
= hisi_sas_read32(hisi_hba
, PHY_CONN_RATE
);
3261 link_rate
= (link_rate
>> (phy_no
* 4)) & 0xf;
3264 if (port_id
== 0xf) {
3265 dev_err(dev
, "sata int: phy%d invalid portid\n", phy_no
);
3270 sas_phy
->linkrate
= link_rate
;
3271 hard_phy_linkrate
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
3273 phy
->maximum_linkrate
= hard_phy_linkrate
& 0xf;
3274 phy
->minimum_linkrate
= (hard_phy_linkrate
>> 4) & 0xf;
3276 sas_phy
->oob_mode
= SATA_OOB_MODE
;
3277 /* Make up some unique SAS address */
3278 attached_sas_addr
[0] = 0x50;
3279 attached_sas_addr
[6] = hisi_hba
->shost
->host_no
;
3280 attached_sas_addr
[7] = phy_no
;
3281 memcpy(sas_phy
->attached_sas_addr
, attached_sas_addr
, SAS_ADDR_SIZE
);
3282 memcpy(sas_phy
->frame_rcvd
, fis
, sizeof(struct dev_to_host_fis
));
3283 dev_info(dev
, "sata int phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
3284 phy
->phy_type
&= ~(PORT_TYPE_SAS
| PORT_TYPE_SATA
);
3285 phy
->port_id
= port_id
;
3286 phy
->phy_type
|= PORT_TYPE_SATA
;
3287 phy
->phy_attached
= 1;
3288 phy
->identify
.device_type
= SAS_SATA_DEV
;
3289 phy
->frame_rcvd_size
= sizeof(struct dev_to_host_fis
);
3290 phy
->identify
.target_port_protocols
= SAS_PROTOCOL_SATA
;
3291 hisi_sas_notify_phy_event(phy
, HISI_PHYE_PHY_UP
);
3293 spin_lock_irqsave(&phy
->lock
, flags
);
3294 if (phy
->reset_completion
) {
3296 complete(phy
->reset_completion
);
3298 spin_unlock_irqrestore(&phy
->lock
, flags
);
3300 hisi_sas_write32(hisi_hba
, ENT_INT_SRC1
+ offset
, ent_tmp
);
3301 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
, ent_msk
);
3306 static irq_handler_t phy_interrupts
[HISI_SAS_PHY_INT_NR
] = {
3307 int_phy_updown_v2_hw
,
3311 static irq_handler_t fatal_interrupts
[HISI_SAS_FATAL_INT_NR
] = {
3312 fatal_ecc_int_v2_hw
,
3317 * There is a limitation in the hip06 chipset that we need
3318 * to map in all mbigen interrupts, even if they are not used.
3320 static int interrupt_init_v2_hw(struct hisi_hba
*hisi_hba
)
3322 struct platform_device
*pdev
= hisi_hba
->platform_dev
;
3323 struct device
*dev
= &pdev
->dev
;
3324 int irq
, rc
, irq_map
[128];
3325 int i
, phy_no
, fatal_no
, queue_no
, k
;
3327 for (i
= 0; i
< 128; i
++)
3328 irq_map
[i
] = platform_get_irq(pdev
, i
);
3330 for (i
= 0; i
< HISI_SAS_PHY_INT_NR
; i
++) {
3331 irq
= irq_map
[i
+ 1]; /* Phy up/down is irq1 */
3332 rc
= devm_request_irq(dev
, irq
, phy_interrupts
[i
], 0,
3333 DRV_NAME
" phy", hisi_hba
);
3335 dev_err(dev
, "irq init: could not request "
3336 "phy interrupt %d, rc=%d\n",
3339 goto free_phy_int_irqs
;
3343 for (phy_no
= 0; phy_no
< hisi_hba
->n_phy
; phy_no
++) {
3344 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
3346 irq
= irq_map
[phy_no
+ 72];
3347 rc
= devm_request_irq(dev
, irq
, sata_int_v2_hw
, 0,
3348 DRV_NAME
" sata", phy
);
3350 dev_err(dev
, "irq init: could not request "
3351 "sata interrupt %d, rc=%d\n",
3354 goto free_sata_int_irqs
;
3358 for (fatal_no
= 0; fatal_no
< HISI_SAS_FATAL_INT_NR
; fatal_no
++) {
3359 irq
= irq_map
[fatal_no
+ 81];
3360 rc
= devm_request_irq(dev
, irq
, fatal_interrupts
[fatal_no
], 0,
3361 DRV_NAME
" fatal", hisi_hba
);
3364 "irq init: could not request fatal interrupt %d, rc=%d\n",
3367 goto free_fatal_int_irqs
;
3371 for (queue_no
= 0; queue_no
< hisi_hba
->queue_count
; queue_no
++) {
3372 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[queue_no
];
3373 struct tasklet_struct
*t
= &cq
->tasklet
;
3375 irq
= irq_map
[queue_no
+ 96];
3376 rc
= devm_request_irq(dev
, irq
, cq_interrupt_v2_hw
, 0,
3377 DRV_NAME
" cq", cq
);
3380 "irq init: could not request cq interrupt %d, rc=%d\n",
3383 goto free_cq_int_irqs
;
3385 tasklet_init(t
, cq_tasklet_v2_hw
, (unsigned long)cq
);
3391 for (k
= 0; k
< queue_no
; k
++) {
3392 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[k
];
3394 free_irq(irq_map
[k
+ 96], cq
);
3395 tasklet_kill(&cq
->tasklet
);
3397 free_fatal_int_irqs
:
3398 for (k
= 0; k
< fatal_no
; k
++)
3399 free_irq(irq_map
[k
+ 81], hisi_hba
);
3401 for (k
= 0; k
< phy_no
; k
++) {
3402 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[k
];
3404 free_irq(irq_map
[k
+ 72], phy
);
3407 for (k
= 0; k
< i
; k
++)
3408 free_irq(irq_map
[k
+ 1], hisi_hba
);
3412 static int hisi_sas_v2_init(struct hisi_hba
*hisi_hba
)
3416 memset(hisi_hba
->sata_dev_bitmap
, 0, sizeof(hisi_hba
->sata_dev_bitmap
));
3418 rc
= hw_init_v2_hw(hisi_hba
);
3422 rc
= interrupt_init_v2_hw(hisi_hba
);
3429 static void interrupt_disable_v2_hw(struct hisi_hba
*hisi_hba
)
3431 struct platform_device
*pdev
= hisi_hba
->platform_dev
;
3434 for (i
= 0; i
< hisi_hba
->queue_count
; i
++)
3435 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+ 0x4 * i
, 0x1);
3437 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0xffffffff);
3438 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0xffffffff);
3439 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0xffffffff);
3440 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0xffffffff);
3442 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
3443 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xffffffff);
3444 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0xffffffff);
3447 for (i
= 0; i
< 128; i
++)
3448 synchronize_irq(platform_get_irq(pdev
, i
));
3452 static u32
get_phys_state_v2_hw(struct hisi_hba
*hisi_hba
)
3454 return hisi_sas_read32(hisi_hba
, PHY_STATE
);
3457 static int soft_reset_v2_hw(struct hisi_hba
*hisi_hba
)
3459 struct device
*dev
= hisi_hba
->dev
;
3462 interrupt_disable_v2_hw(hisi_hba
);
3463 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0x0);
3464 hisi_sas_kill_tasklets(hisi_hba
);
3466 hisi_sas_stop_phys(hisi_hba
);
3470 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
+ AM_CTRL_GLOBAL
, 0x1);
3472 /* wait until bus idle */
3475 u32 status
= hisi_sas_read32_relaxed(hisi_hba
,
3476 AXI_MASTER_CFG_BASE
+ AM_CURR_TRANS_RETURN
);
3483 dev_err(dev
, "wait axi bus state to idle timeout!\n");
3488 hisi_sas_init_mem(hisi_hba
);
3490 rc
= hw_init_v2_hw(hisi_hba
);
3494 phys_reject_stp_links_v2_hw(hisi_hba
);
3499 static int write_gpio_v2_hw(struct hisi_hba
*hisi_hba
, u8 reg_type
,
3500 u8 reg_index
, u8 reg_count
, u8
*write_data
)
3502 struct device
*dev
= hisi_hba
->dev
;
3505 if (!hisi_hba
->sgpio_regs
)
3509 case SAS_GPIO_REG_TX
:
3510 count
= reg_count
* 4;
3511 count
= min(count
, hisi_hba
->n_phy
);
3513 for (phy_no
= 0; phy_no
< count
; phy_no
++) {
3515 * GPIO_TX[n] register has the highest numbered drive
3516 * of the four in the first byte and the lowest
3517 * numbered drive in the fourth byte.
3518 * See SFF-8485 Rev. 0.7 Table 24.
3520 void __iomem
*reg_addr
= hisi_hba
->sgpio_regs
+
3521 reg_index
* 4 + phy_no
;
3522 int data_idx
= phy_no
+ 3 - (phy_no
% 4) * 2;
3524 writeb(write_data
[data_idx
], reg_addr
);
3529 dev_err(dev
, "write gpio: unsupported or bad reg type %d\n",
3537 static void wait_cmds_complete_timeout_v2_hw(struct hisi_hba
*hisi_hba
,
3538 int delay_ms
, int timeout_ms
)
3540 struct device
*dev
= hisi_hba
->dev
;
3541 int entries
, entries_old
= 0, time
;
3543 for (time
= 0; time
< timeout_ms
; time
+= delay_ms
) {
3544 entries
= hisi_sas_read32(hisi_hba
, CQE_SEND_CNT
);
3545 if (entries
== entries_old
)
3548 entries_old
= entries
;
3552 dev_dbg(dev
, "wait commands complete %dms\n", time
);
3555 static struct scsi_host_template sht_v2_hw
= {
3557 .module
= THIS_MODULE
,
3558 .queuecommand
= sas_queuecommand
,
3559 .target_alloc
= sas_target_alloc
,
3560 .slave_configure
= hisi_sas_slave_configure
,
3561 .scan_finished
= hisi_sas_scan_finished
,
3562 .scan_start
= hisi_sas_scan_start
,
3563 .change_queue_depth
= sas_change_queue_depth
,
3564 .bios_param
= sas_bios_param
,
3566 .sg_tablesize
= SG_ALL
,
3567 .max_sectors
= SCSI_DEFAULT_MAX_SECTORS
,
3568 .use_clustering
= ENABLE_CLUSTERING
,
3569 .eh_device_reset_handler
= sas_eh_device_reset_handler
,
3570 .eh_target_reset_handler
= sas_eh_target_reset_handler
,
3571 .target_destroy
= sas_target_destroy
,
3573 .shost_attrs
= host_attrs
,
3576 static const struct hisi_sas_hw hisi_sas_v2_hw
= {
3577 .hw_init
= hisi_sas_v2_init
,
3578 .setup_itct
= setup_itct_v2_hw
,
3579 .slot_index_alloc
= slot_index_alloc_quirk_v2_hw
,
3580 .alloc_dev
= alloc_dev_quirk_v2_hw
,
3581 .sl_notify
= sl_notify_v2_hw
,
3582 .get_wideport_bitmap
= get_wideport_bitmap_v2_hw
,
3583 .clear_itct
= clear_itct_v2_hw
,
3584 .free_device
= free_device_v2_hw
,
3585 .prep_smp
= prep_smp_v2_hw
,
3586 .prep_ssp
= prep_ssp_v2_hw
,
3587 .prep_stp
= prep_ata_v2_hw
,
3588 .prep_abort
= prep_abort_v2_hw
,
3589 .get_free_slot
= get_free_slot_v2_hw
,
3590 .start_delivery
= start_delivery_v2_hw
,
3591 .slot_complete
= slot_complete_v2_hw
,
3592 .phys_init
= phys_init_v2_hw
,
3593 .phy_start
= start_phy_v2_hw
,
3594 .phy_disable
= disable_phy_v2_hw
,
3595 .phy_hard_reset
= phy_hard_reset_v2_hw
,
3596 .get_events
= phy_get_events_v2_hw
,
3597 .phy_set_linkrate
= phy_set_linkrate_v2_hw
,
3598 .phy_get_max_linkrate
= phy_get_max_linkrate_v2_hw
,
3599 .max_command_entries
= HISI_SAS_COMMAND_ENTRIES_V2_HW
,
3600 .complete_hdr_size
= sizeof(struct hisi_sas_complete_v2_hdr
),
3601 .soft_reset
= soft_reset_v2_hw
,
3602 .get_phys_state
= get_phys_state_v2_hw
,
3603 .write_gpio
= write_gpio_v2_hw
,
3604 .wait_cmds_complete_timeout
= wait_cmds_complete_timeout_v2_hw
,
3608 static int hisi_sas_v2_probe(struct platform_device
*pdev
)
3611 * Check if we should defer the probe before we probe the
3612 * upper layer, as it's hard to defer later on.
3614 int ret
= platform_get_irq(pdev
, 0);
3617 if (ret
!= -EPROBE_DEFER
)
3618 dev_err(&pdev
->dev
, "cannot obtain irq\n");
3622 return hisi_sas_probe(pdev
, &hisi_sas_v2_hw
);
3625 static int hisi_sas_v2_remove(struct platform_device
*pdev
)
3627 struct sas_ha_struct
*sha
= platform_get_drvdata(pdev
);
3628 struct hisi_hba
*hisi_hba
= sha
->lldd_ha
;
3630 hisi_sas_kill_tasklets(hisi_hba
);
3632 return hisi_sas_remove(pdev
);
3635 static const struct of_device_id sas_v2_of_match
[] = {
3636 { .compatible
= "hisilicon,hip06-sas-v2",},
3637 { .compatible
= "hisilicon,hip07-sas-v2",},
3640 MODULE_DEVICE_TABLE(of
, sas_v2_of_match
);
3642 static const struct acpi_device_id sas_v2_acpi_match
[] = {
3647 MODULE_DEVICE_TABLE(acpi
, sas_v2_acpi_match
);
3649 static struct platform_driver hisi_sas_v2_driver
= {
3650 .probe
= hisi_sas_v2_probe
,
3651 .remove
= hisi_sas_v2_remove
,
3654 .of_match_table
= sas_v2_of_match
,
3655 .acpi_match_table
= ACPI_PTR(sas_v2_acpi_match
),
3659 module_platform_driver(hisi_sas_v2_driver
);
3661 MODULE_LICENSE("GPL");
3662 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3663 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3664 MODULE_ALIAS("platform:" DRV_NAME
);