2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
13 #define DRV_NAME "hisi_sas_v2_hw"
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
148 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
149 #define DLVRY_Q_0_DEPTH 0x268
150 #define DLVRY_Q_0_WR_PTR 0x26c
151 #define DLVRY_Q_0_RD_PTR 0x270
152 #define HYPER_STREAM_ID_EN_CFG 0xc80
153 #define OQ0_INT_SRC_MSK 0xc90
154 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
155 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
156 #define COMPL_Q_0_DEPTH 0x4e8
157 #define COMPL_Q_0_WR_PTR 0x4ec
158 #define COMPL_Q_0_RD_PTR 0x4f0
159 #define HGC_RXM_DFX_STATUS14 0xae8
160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
162 HGC_RXM_DFX_STATUS14_MEM0_OFF)
163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM1_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM2_OFF)
169 #define HGC_RXM_DFX_STATUS15 0xaec
170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
172 HGC_RXM_DFX_STATUS15_MEM3_OFF)
173 /* phy registers need init */
174 #define PORT_BASE (0x2000)
176 #define PHY_CFG (PORT_BASE + 0x0)
177 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PHY_CFG_ENA_OFF 0
179 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
180 #define PHY_CFG_DC_OPT_OFF 2
181 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
182 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
183 #define PROG_PHY_LINK_RATE_MAX_OFF 0
184 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
185 #define PHY_CTRL (PORT_BASE + 0x14)
186 #define PHY_CTRL_RESET_OFF 0
187 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
188 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
189 #define SL_CFG (PORT_BASE + 0x84)
190 #define PHY_PCN (PORT_BASE + 0x44)
191 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
192 #define SL_CONTROL (PORT_BASE + 0x94)
193 #define SL_CONTROL_NOTIFY_EN_OFF 0
194 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
195 #define SL_CONTROL_CTA_OFF 17
196 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
197 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
198 #define RX_BCAST_CHG_OFF 1
199 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
200 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
201 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
202 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
203 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
204 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
205 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
206 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
207 #define TXID_AUTO (PORT_BASE + 0xb8)
208 #define TXID_AUTO_CT3_OFF 1
209 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
210 #define TX_HARDRST_OFF 2
211 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
212 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
213 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
214 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
215 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
216 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
217 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
218 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
219 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
220 #define CON_CONTROL (PORT_BASE + 0x118)
221 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
222 #define CHL_INT0 (PORT_BASE + 0x1b4)
223 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
224 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
225 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
226 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
227 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
228 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
229 #define CHL_INT0_NOT_RDY_OFF 4
230 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
231 #define CHL_INT0_PHY_RDY_OFF 5
232 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
233 #define CHL_INT1 (PORT_BASE + 0x1b8)
234 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
235 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
236 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
237 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
238 #define CHL_INT2 (PORT_BASE + 0x1bc)
239 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
240 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
241 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
242 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
243 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
244 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
245 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
246 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
247 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
248 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
249 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
250 #define DMA_TX_STATUS_BUSY_OFF 0
251 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
252 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
253 #define DMA_RX_STATUS_BUSY_OFF 0
254 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
256 #define AXI_CFG (0x5100)
257 #define AM_CFG_MAX_TRANS (0x5010)
258 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
260 #define AXI_MASTER_CFG_BASE (0x5000)
261 #define AM_CTRL_GLOBAL (0x0)
262 #define AM_CURR_TRANS_RETURN (0x150)
264 /* HW dma structures */
265 /* Delivery queue header */
267 #define CMD_HDR_ABORT_FLAG_OFF 0
268 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
269 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
270 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
271 #define CMD_HDR_RESP_REPORT_OFF 5
272 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
273 #define CMD_HDR_TLR_CTRL_OFF 6
274 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
275 #define CMD_HDR_PORT_OFF 18
276 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
277 #define CMD_HDR_PRIORITY_OFF 27
278 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
279 #define CMD_HDR_CMD_OFF 29
280 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
282 #define CMD_HDR_DIR_OFF 5
283 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
284 #define CMD_HDR_RESET_OFF 7
285 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
286 #define CMD_HDR_VDTL_OFF 10
287 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
288 #define CMD_HDR_FRAME_TYPE_OFF 11
289 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
290 #define CMD_HDR_DEV_ID_OFF 16
291 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
293 #define CMD_HDR_CFL_OFF 0
294 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
295 #define CMD_HDR_NCQ_TAG_OFF 10
296 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
297 #define CMD_HDR_MRFL_OFF 15
298 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
299 #define CMD_HDR_SG_MOD_OFF 24
300 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
301 #define CMD_HDR_FIRST_BURST_OFF 26
302 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
304 #define CMD_HDR_IPTT_OFF 0
305 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
307 #define CMD_HDR_DIF_SGL_LEN_OFF 0
308 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
309 #define CMD_HDR_DATA_SGL_LEN_OFF 16
310 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
311 #define CMD_HDR_ABORT_IPTT_OFF 16
312 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
314 /* Completion header */
316 #define CMPLT_HDR_ERR_PHASE_OFF 2
317 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
318 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
319 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
320 #define CMPLT_HDR_ERX_OFF 12
321 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
322 #define CMPLT_HDR_ABORT_STAT_OFF 13
323 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
325 #define STAT_IO_NOT_VALID 0x1
326 #define STAT_IO_NO_DEVICE 0x2
327 #define STAT_IO_COMPLETE 0x3
328 #define STAT_IO_ABORTED 0x4
330 #define CMPLT_HDR_IPTT_OFF 0
331 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
332 #define CMPLT_HDR_DEV_ID_OFF 16
333 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
337 #define ITCT_HDR_DEV_TYPE_OFF 0
338 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
339 #define ITCT_HDR_VALID_OFF 2
340 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
341 #define ITCT_HDR_MCR_OFF 5
342 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
343 #define ITCT_HDR_VLN_OFF 9
344 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
345 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
346 #define ITCT_HDR_SMP_TIMEOUT_8US 1
347 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
349 #define ITCT_HDR_AWT_CONTINUE_OFF 25
350 #define ITCT_HDR_PORT_ID_OFF 28
351 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
353 #define ITCT_HDR_INLT_OFF 0
354 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
355 #define ITCT_HDR_BITLT_OFF 16
356 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
357 #define ITCT_HDR_MCTLT_OFF 32
358 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
359 #define ITCT_HDR_RTOLT_OFF 48
360 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
362 #define HISI_SAS_FATAL_INT_NR 2
364 struct hisi_sas_complete_v2_hdr
{
371 struct hisi_sas_err_record_v2
{
373 __le32 trans_tx_fail_type
;
376 __le32 trans_rx_fail_type
;
379 __le16 dma_tx_err_type
;
380 __le16 sipc_rx_err_type
;
383 __le32 dma_rx_err_type
;
387 HISI_SAS_PHY_PHY_UPDOWN
,
388 HISI_SAS_PHY_CHNL_INT
,
393 TRANS_TX_FAIL_BASE
= 0x0, /* dw0 */
394 TRANS_RX_FAIL_BASE
= 0x20, /* dw1 */
395 DMA_TX_ERR_BASE
= 0x40, /* dw2 bit 15-0 */
396 SIPC_RX_ERR_BASE
= 0x50, /* dw2 bit 31-16*/
397 DMA_RX_ERR_BASE
= 0x60, /* dw3 */
400 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
= TRANS_TX_FAIL_BASE
, /* 0x0 */
401 TRANS_TX_ERR_PHY_NOT_ENABLE
, /* 0x1 */
402 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
, /* 0x2 */
403 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
, /* 0x3 */
404 TRANS_TX_OPEN_CNX_ERR_BY_OTHER
, /* 0x4 */
406 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
, /* 0x6 */
407 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
, /* 0x7 */
408 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
, /* 0x8 */
409 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
, /* 0x9 */
410 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
, /* 0xa */
411 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
, /* 0xb */
412 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
, /* 0xc */
413 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
, /* 0xd */
414 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
, /* 0xe */
415 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
, /* 0xf */
416 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
, /* 0x10 */
417 TRANS_TX_ERR_FRAME_TXED
, /* 0x11 */
418 TRANS_TX_ERR_WITH_BREAK_TIMEOUT
, /* 0x12 */
419 TRANS_TX_ERR_WITH_BREAK_REQUEST
, /* 0x13 */
420 TRANS_TX_ERR_WITH_BREAK_RECEVIED
, /* 0x14 */
421 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
, /* 0x15 */
422 TRANS_TX_ERR_WITH_CLOSE_NORMAL
, /* 0x16 for ssp*/
423 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
, /* 0x17 */
424 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
, /* 0x18 */
425 TRANS_TX_ERR_WITH_CLOSE_COMINIT
, /* 0x19 */
426 TRANS_TX_ERR_WITH_NAK_RECEVIED
, /* 0x1a for ssp*/
427 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
, /* 0x1b for ssp*/
428 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
429 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
, /* 0x1c for ssp */
430 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
431 TRANS_TX_ERR_WITH_IPTT_CONFLICT
, /* 0x1d for ssp/smp */
432 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS
, /* 0x1e */
433 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
434 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
, /* 0x1f for sata/stp */
437 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
= TRANS_RX_FAIL_BASE
, /* 0x20 */
438 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
, /* 0x21 for sata/stp */
439 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
, /* 0x22 for ssp/smp */
440 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
441 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
, /* 0x23 for sata/stp */
442 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
, /* 0x24 for sata/stp */
443 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
, /* 0x25 for smp */
444 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
445 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
, /* 0x26 for sata/stp*/
446 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
, /* 0x27 */
447 TRANS_RX_ERR_WITH_BREAK_TIMEOUT
, /* 0x28 */
448 TRANS_RX_ERR_WITH_BREAK_REQUEST
, /* 0x29 */
449 TRANS_RX_ERR_WITH_BREAK_RECEVIED
, /* 0x2a */
450 RESERVED1
, /* 0x2b */
451 TRANS_RX_ERR_WITH_CLOSE_NORMAL
, /* 0x2c */
452 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
, /* 0x2d */
453 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
, /* 0x2e */
454 TRANS_RX_ERR_WITH_CLOSE_COMINIT
, /* 0x2f */
455 TRANS_RX_ERR_WITH_DATA_LEN0
, /* 0x30 for ssp/smp */
456 TRANS_RX_ERR_WITH_BAD_HASH
, /* 0x31 for ssp */
457 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
458 TRANS_RX_XRDY_WLEN_ZERO_ERR
, /* 0x32 for ssp*/
459 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
460 TRANS_RX_SSP_FRM_LEN_ERR
, /* 0x33 for ssp */
461 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
462 RESERVED2
, /* 0x34 */
463 RESERVED3
, /* 0x35 */
464 RESERVED4
, /* 0x36 */
465 RESERVED5
, /* 0x37 */
466 TRANS_RX_ERR_WITH_BAD_FRM_TYPE
, /* 0x38 */
467 TRANS_RX_SMP_FRM_LEN_ERR
, /* 0x39 */
468 TRANS_RX_SMP_RESP_TIMEOUT_ERR
, /* 0x3a */
469 RESERVED6
, /* 0x3b */
470 RESERVED7
, /* 0x3c */
471 RESERVED8
, /* 0x3d */
472 RESERVED9
, /* 0x3e */
473 TRANS_RX_R_ERR
, /* 0x3f */
476 DMA_TX_DIF_CRC_ERR
= DMA_TX_ERR_BASE
, /* 0x40 */
477 DMA_TX_DIF_APP_ERR
, /* 0x41 */
478 DMA_TX_DIF_RPP_ERR
, /* 0x42 */
479 DMA_TX_DATA_SGL_OVERFLOW
, /* 0x43 */
480 DMA_TX_DIF_SGL_OVERFLOW
, /* 0x44 */
481 DMA_TX_UNEXP_XFER_ERR
, /* 0x45 */
482 DMA_TX_UNEXP_RETRANS_ERR
, /* 0x46 */
483 DMA_TX_XFER_LEN_OVERFLOW
, /* 0x47 */
484 DMA_TX_XFER_OFFSET_ERR
, /* 0x48 */
485 DMA_TX_RAM_ECC_ERR
, /* 0x49 */
486 DMA_TX_DIF_LEN_ALIGN_ERR
, /* 0x4a */
490 SIPC_RX_FIS_STATUS_ERR_BIT_VLD
= SIPC_RX_ERR_BASE
, /* 0x50 */
491 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR
, /* 0x51 */
492 SIPC_RX_FIS_STATUS_BSY_BIT_ERR
, /* 0x52 */
493 SIPC_RX_WRSETUP_LEN_ODD_ERR
, /* 0x53 */
494 SIPC_RX_WRSETUP_LEN_ZERO_ERR
, /* 0x54 */
495 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR
, /* 0x55 */
496 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR
, /* 0x56 */
497 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR
, /* 0x57 */
498 SIPC_RX_SATA_UNEXP_FIS_ERR
, /* 0x58 */
499 SIPC_RX_WRSETUP_ESTATUS_ERR
, /* 0x59 */
500 SIPC_RX_DATA_UNDERFLOW_ERR
, /* 0x5a */
501 SIPC_RX_MAX_ERR_CODE
,
504 DMA_RX_DIF_CRC_ERR
= DMA_RX_ERR_BASE
, /* 0x60 */
505 DMA_RX_DIF_APP_ERR
, /* 0x61 */
506 DMA_RX_DIF_RPP_ERR
, /* 0x62 */
507 DMA_RX_DATA_SGL_OVERFLOW
, /* 0x63 */
508 DMA_RX_DIF_SGL_OVERFLOW
, /* 0x64 */
509 DMA_RX_DATA_LEN_OVERFLOW
, /* 0x65 */
510 DMA_RX_DATA_LEN_UNDERFLOW
, /* 0x66 */
511 DMA_RX_DATA_OFFSET_ERR
, /* 0x67 */
512 RESERVED10
, /* 0x68 */
513 DMA_RX_SATA_FRAME_TYPE_ERR
, /* 0x69 */
514 DMA_RX_RESP_BUF_OVERFLOW
, /* 0x6a */
515 DMA_RX_UNEXP_RETRANS_RESP_ERR
, /* 0x6b */
516 DMA_RX_UNEXP_NORM_RESP_ERR
, /* 0x6c */
517 DMA_RX_UNEXP_RDFRAME_ERR
, /* 0x6d */
518 DMA_RX_PIO_DATA_LEN_ERR
, /* 0x6e */
519 DMA_RX_RDSETUP_STATUS_ERR
, /* 0x6f */
520 DMA_RX_RDSETUP_STATUS_DRQ_ERR
, /* 0x70 */
521 DMA_RX_RDSETUP_STATUS_BSY_ERR
, /* 0x71 */
522 DMA_RX_RDSETUP_LEN_ODD_ERR
, /* 0x72 */
523 DMA_RX_RDSETUP_LEN_ZERO_ERR
, /* 0x73 */
524 DMA_RX_RDSETUP_LEN_OVER_ERR
, /* 0x74 */
525 DMA_RX_RDSETUP_OFFSET_ERR
, /* 0x75 */
526 DMA_RX_RDSETUP_ACTIVE_ERR
, /* 0x76 */
527 DMA_RX_RDSETUP_ESTATUS_ERR
, /* 0x77 */
528 DMA_RX_RAM_ECC_ERR
, /* 0x78 */
529 DMA_RX_UNKNOWN_FRM_ERR
, /* 0x79 */
533 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
535 #define DIR_NO_DATA 0
537 #define DIR_TO_DEVICE 2
538 #define DIR_RESERVED 3
540 #define SATA_PROTOCOL_NONDATA 0x1
541 #define SATA_PROTOCOL_PIO 0x2
542 #define SATA_PROTOCOL_DMA 0x4
543 #define SATA_PROTOCOL_FPDMA 0x8
544 #define SATA_PROTOCOL_ATAPI 0x10
546 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
547 err_phase == 0x4 || err_phase == 0x8 ||\
548 err_phase == 0x6 || err_phase == 0xa)
549 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
550 err_phase == 0x20 || err_phase == 0x40)
552 static void hisi_sas_link_timeout_disable_link(unsigned long data
);
554 static u32
hisi_sas_read32(struct hisi_hba
*hisi_hba
, u32 off
)
556 void __iomem
*regs
= hisi_hba
->regs
+ off
;
561 static u32
hisi_sas_read32_relaxed(struct hisi_hba
*hisi_hba
, u32 off
)
563 void __iomem
*regs
= hisi_hba
->regs
+ off
;
565 return readl_relaxed(regs
);
568 static void hisi_sas_write32(struct hisi_hba
*hisi_hba
, u32 off
, u32 val
)
570 void __iomem
*regs
= hisi_hba
->regs
+ off
;
575 static void hisi_sas_phy_write32(struct hisi_hba
*hisi_hba
, int phy_no
,
578 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
583 static u32
hisi_sas_phy_read32(struct hisi_hba
*hisi_hba
,
586 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
591 /* This function needs to be protected from pre-emption. */
593 slot_index_alloc_quirk_v2_hw(struct hisi_hba
*hisi_hba
, int *slot_idx
,
594 struct domain_device
*device
)
596 unsigned int index
= 0;
597 void *bitmap
= hisi_hba
->slot_index_tags
;
598 int sata_dev
= dev_is_sata(device
);
601 index
= find_next_zero_bit(bitmap
, hisi_hba
->slot_index_count
,
603 if (index
>= hisi_hba
->slot_index_count
)
604 return -SAS_QUEUE_FULL
;
606 * SAS IPTT bit0 should be 1
608 if (sata_dev
|| (index
& 1))
613 set_bit(index
, bitmap
);
619 hisi_sas_device
*alloc_dev_quirk_v2_hw(struct domain_device
*device
)
621 struct hisi_hba
*hisi_hba
= device
->port
->ha
->lldd_ha
;
622 struct hisi_sas_device
*sas_dev
= NULL
;
623 int i
, sata_dev
= dev_is_sata(device
);
625 spin_lock(&hisi_hba
->lock
);
626 for (i
= 0; i
< HISI_SAS_MAX_DEVICES
; i
++) {
628 * SATA device id bit0 should be 0
630 if (sata_dev
&& (i
& 1))
632 if (hisi_hba
->devices
[i
].dev_type
== SAS_PHY_UNUSED
) {
633 hisi_hba
->devices
[i
].device_id
= i
;
634 sas_dev
= &hisi_hba
->devices
[i
];
635 sas_dev
->dev_status
= HISI_SAS_DEV_NORMAL
;
636 sas_dev
->dev_type
= device
->dev_type
;
637 sas_dev
->hisi_hba
= hisi_hba
;
638 sas_dev
->sas_device
= device
;
639 INIT_LIST_HEAD(&hisi_hba
->devices
[i
].list
);
643 spin_unlock(&hisi_hba
->lock
);
648 static void config_phy_opt_mode_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
650 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
652 cfg
&= ~PHY_CFG_DC_OPT_MSK
;
653 cfg
|= 1 << PHY_CFG_DC_OPT_OFF
;
654 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
657 static void config_id_frame_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
659 struct sas_identify_frame identify_frame
;
660 u32
*identify_buffer
;
662 memset(&identify_frame
, 0, sizeof(identify_frame
));
663 identify_frame
.dev_type
= SAS_END_DEVICE
;
664 identify_frame
.frame_type
= 0;
665 identify_frame
._un1
= 1;
666 identify_frame
.initiator_bits
= SAS_PROTOCOL_ALL
;
667 identify_frame
.target_bits
= SAS_PROTOCOL_NONE
;
668 memcpy(&identify_frame
._un4_11
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
669 memcpy(&identify_frame
.sas_addr
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
670 identify_frame
.phy_id
= phy_no
;
671 identify_buffer
= (u32
*)(&identify_frame
);
673 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD0
,
674 __swab32(identify_buffer
[0]));
675 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD1
,
676 __swab32(identify_buffer
[1]));
677 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD2
,
678 __swab32(identify_buffer
[2]));
679 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD3
,
680 __swab32(identify_buffer
[3]));
681 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD4
,
682 __swab32(identify_buffer
[4]));
683 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD5
,
684 __swab32(identify_buffer
[5]));
687 static void setup_itct_v2_hw(struct hisi_hba
*hisi_hba
,
688 struct hisi_sas_device
*sas_dev
)
690 struct domain_device
*device
= sas_dev
->sas_device
;
691 struct device
*dev
= &hisi_hba
->pdev
->dev
;
692 u64 qw0
, device_id
= sas_dev
->device_id
;
693 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[device_id
];
694 struct domain_device
*parent_dev
= device
->parent
;
695 struct asd_sas_port
*sas_port
= device
->port
;
696 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
698 memset(itct
, 0, sizeof(*itct
));
702 switch (sas_dev
->dev_type
) {
704 case SAS_EDGE_EXPANDER_DEVICE
:
705 case SAS_FANOUT_EXPANDER_DEVICE
:
706 qw0
= HISI_SAS_DEV_TYPE_SSP
<< ITCT_HDR_DEV_TYPE_OFF
;
709 case SAS_SATA_PENDING
:
710 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
711 qw0
= HISI_SAS_DEV_TYPE_STP
<< ITCT_HDR_DEV_TYPE_OFF
;
713 qw0
= HISI_SAS_DEV_TYPE_SATA
<< ITCT_HDR_DEV_TYPE_OFF
;
716 dev_warn(dev
, "setup itct: unsupported dev type (%d)\n",
720 qw0
|= ((1 << ITCT_HDR_VALID_OFF
) |
721 (device
->linkrate
<< ITCT_HDR_MCR_OFF
) |
722 (1 << ITCT_HDR_VLN_OFF
) |
723 (ITCT_HDR_SMP_TIMEOUT
<< ITCT_HDR_SMP_TIMEOUT_OFF
) |
724 (1 << ITCT_HDR_AWT_CONTINUE_OFF
) |
725 (port
->id
<< ITCT_HDR_PORT_ID_OFF
));
726 itct
->qw0
= cpu_to_le64(qw0
);
729 memcpy(&itct
->sas_addr
, device
->sas_addr
, SAS_ADDR_SIZE
);
730 itct
->sas_addr
= __swab64(itct
->sas_addr
);
733 if (!dev_is_sata(device
))
734 itct
->qw2
= cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF
) |
735 (0x1ULL
<< ITCT_HDR_BITLT_OFF
) |
736 (0x32ULL
<< ITCT_HDR_MCTLT_OFF
) |
737 (0x1ULL
<< ITCT_HDR_RTOLT_OFF
));
740 static void free_device_v2_hw(struct hisi_hba
*hisi_hba
,
741 struct hisi_sas_device
*sas_dev
)
743 u64 dev_id
= sas_dev
->device_id
;
744 struct device
*dev
= &hisi_hba
->pdev
->dev
;
745 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[dev_id
];
746 u32 reg_val
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
749 /* clear the itct interrupt state */
750 if (ENT_INT_SRC3_ITC_INT_MSK
& reg_val
)
751 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
752 ENT_INT_SRC3_ITC_INT_MSK
);
754 /* clear the itct int*/
755 for (i
= 0; i
< 2; i
++) {
756 /* clear the itct table*/
757 reg_val
= hisi_sas_read32(hisi_hba
, ITCT_CLR
);
758 reg_val
|= ITCT_CLR_EN_MSK
| (dev_id
& ITCT_DEV_MSK
);
759 hisi_sas_write32(hisi_hba
, ITCT_CLR
, reg_val
);
762 reg_val
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
763 if (ENT_INT_SRC3_ITC_INT_MSK
& reg_val
) {
764 dev_dbg(dev
, "got clear ITCT done interrupt\n");
766 /* invalid the itct state*/
767 memset(itct
, 0, sizeof(struct hisi_sas_itct
));
768 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
769 ENT_INT_SRC3_ITC_INT_MSK
);
772 hisi_sas_write32(hisi_hba
, ITCT_CLR
, 0);
773 dev_dbg(dev
, "clear ITCT ok\n");
779 static int reset_hw_v2_hw(struct hisi_hba
*hisi_hba
)
783 unsigned long end_time
;
784 struct device
*dev
= &hisi_hba
->pdev
->dev
;
786 /* The mask needs to be set depending on the number of phys */
787 if (hisi_hba
->n_phy
== 9)
788 reset_val
= 0x1fffff;
792 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0);
794 /* Disable all of the PHYs */
795 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
796 u32 phy_cfg
= hisi_sas_phy_read32(hisi_hba
, i
, PHY_CFG
);
798 phy_cfg
&= ~PHY_CTRL_RESET_MSK
;
799 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CFG
, phy_cfg
);
803 /* Ensure DMA tx & rx idle */
804 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
805 u32 dma_tx_status
, dma_rx_status
;
807 end_time
= jiffies
+ msecs_to_jiffies(1000);
810 dma_tx_status
= hisi_sas_phy_read32(hisi_hba
, i
,
812 dma_rx_status
= hisi_sas_phy_read32(hisi_hba
, i
,
815 if (!(dma_tx_status
& DMA_TX_STATUS_BUSY_MSK
) &&
816 !(dma_rx_status
& DMA_RX_STATUS_BUSY_MSK
))
820 if (time_after(jiffies
, end_time
))
825 /* Ensure axi bus idle */
826 end_time
= jiffies
+ msecs_to_jiffies(1000);
829 hisi_sas_read32(hisi_hba
, AXI_CFG
);
835 if (time_after(jiffies
, end_time
))
839 if (ACPI_HANDLE(dev
)) {
842 s
= acpi_evaluate_object(ACPI_HANDLE(dev
), "_RST", NULL
, NULL
);
843 if (ACPI_FAILURE(s
)) {
844 dev_err(dev
, "Reset failed\n");
847 } else if (hisi_hba
->ctrl
) {
848 /* reset and disable clock*/
849 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_reg
,
851 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_clock_ena_reg
+ 4,
854 regmap_read(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_sts_reg
, &val
);
855 if (reset_val
!= (val
& reset_val
)) {
856 dev_err(dev
, "SAS reset fail.\n");
860 /* De-reset and enable clock*/
861 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_reg
+ 4,
863 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_clock_ena_reg
,
866 regmap_read(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_sts_reg
,
868 if (val
& reset_val
) {
869 dev_err(dev
, "SAS de-reset fail.\n");
873 dev_warn(dev
, "no reset method\n");
878 static void init_reg_v2_hw(struct hisi_hba
*hisi_hba
)
880 struct device
*dev
= &hisi_hba
->pdev
->dev
;
883 /* Global registers init */
885 /* Deal with am-max-transmissions quirk */
886 if (device_property_present(dev
, "hip06-sas-v2-quirk-amt")) {
887 hisi_sas_write32(hisi_hba
, AM_CFG_MAX_TRANS
, 0x2020);
888 hisi_sas_write32(hisi_hba
, AM_CFG_SINGLE_PORT_MAX_TRANS
,
890 } /* Else, use defaults -> do nothing */
892 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
,
893 (u32
)((1ULL << hisi_hba
->queue_count
) - 1));
894 hisi_sas_write32(hisi_hba
, AXI_USER1
, 0xc0000000);
895 hisi_sas_write32(hisi_hba
, AXI_USER2
, 0x10000);
896 hisi_sas_write32(hisi_hba
, HGC_SAS_TXFAIL_RETRY_CTRL
, 0x0);
897 hisi_sas_write32(hisi_hba
, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL
, 0x7FF);
898 hisi_sas_write32(hisi_hba
, OPENA_WT_CONTI_TIME
, 0x1);
899 hisi_sas_write32(hisi_hba
, I_T_NEXUS_LOSS_TIME
, 0x1F4);
900 hisi_sas_write32(hisi_hba
, MAX_CON_TIME_LIMIT_TIME
, 0x32);
901 hisi_sas_write32(hisi_hba
, BUS_INACTIVE_LIMIT_TIME
, 0x1);
902 hisi_sas_write32(hisi_hba
, CFG_AGING_TIME
, 0x1);
903 hisi_sas_write32(hisi_hba
, HGC_ERR_STAT_EN
, 0x1);
904 hisi_sas_write32(hisi_hba
, HGC_GET_ITV_TIME
, 0x1);
905 hisi_sas_write32(hisi_hba
, INT_COAL_EN
, 0xc);
906 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_TIME
, 0x60);
907 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_CNT
, 0x3);
908 hisi_sas_write32(hisi_hba
, ENT_INT_COAL_TIME
, 0x1);
909 hisi_sas_write32(hisi_hba
, ENT_INT_COAL_CNT
, 0x1);
910 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 0x0);
911 hisi_sas_write32(hisi_hba
, ENT_INT_SRC1
, 0xffffffff);
912 hisi_sas_write32(hisi_hba
, ENT_INT_SRC2
, 0xffffffff);
913 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
, 0xffffffff);
914 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0x7efefefe);
915 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0x7efefefe);
916 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0x7ffffffe);
917 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0xfff00c30);
918 for (i
= 0; i
< hisi_hba
->queue_count
; i
++)
919 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+0x4*i
, 0);
921 hisi_sas_write32(hisi_hba
, AXI_AHB_CLK_CFG
, 1);
922 hisi_sas_write32(hisi_hba
, HYPER_STREAM_ID_EN_CFG
, 1);
924 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
925 hisi_sas_phy_write32(hisi_hba
, i
, PROG_PHY_LINK_RATE
, 0x855);
926 hisi_sas_phy_write32(hisi_hba
, i
, SAS_PHY_CTRL
, 0x30b9908);
927 hisi_sas_phy_write32(hisi_hba
, i
, SL_TOUT_CFG
, 0x7d7d7d7d);
928 hisi_sas_phy_write32(hisi_hba
, i
, SL_CONTROL
, 0x0);
929 hisi_sas_phy_write32(hisi_hba
, i
, TXID_AUTO
, 0x2);
930 hisi_sas_phy_write32(hisi_hba
, i
, DONE_RECEIVED_TIME
, 0x8);
931 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT0
, 0xffffffff);
932 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1
, 0xffffffff);
933 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2
, 0xfff87fff);
934 hisi_sas_phy_write32(hisi_hba
, i
, RXOP_CHECK_CFG_H
, 0x1000);
935 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xffffffff);
936 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0x8ffffbff);
937 hisi_sas_phy_write32(hisi_hba
, i
, SL_CFG
, 0x13f801fc);
938 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL_RDY_MSK
, 0x0);
939 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_NOT_RDY_MSK
, 0x0);
940 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_DWS_RESET_MSK
, 0x0);
941 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_PHY_ENA_MSK
, 0x0);
942 hisi_sas_phy_write32(hisi_hba
, i
, SL_RX_BCAST_CHK_MSK
, 0x0);
943 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT_COAL_EN
, 0x0);
944 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_OOB_RESTART_MSK
, 0x0);
945 if (hisi_hba
->refclk_frequency_mhz
== 66)
946 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL
, 0x199B694);
947 /* else, do nothing -> leave it how you found it */
950 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
952 hisi_sas_write32(hisi_hba
,
953 DLVRY_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
954 upper_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
956 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
957 lower_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
959 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_DEPTH
+ (i
* 0x14),
960 HISI_SAS_QUEUE_SLOTS
);
962 /* Completion queue */
963 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
964 upper_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
966 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
967 lower_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
969 hisi_sas_write32(hisi_hba
, COMPL_Q_0_DEPTH
+ (i
* 0x14),
970 HISI_SAS_QUEUE_SLOTS
);
974 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_LO
,
975 lower_32_bits(hisi_hba
->itct_dma
));
977 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_HI
,
978 upper_32_bits(hisi_hba
->itct_dma
));
981 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_LO
,
982 lower_32_bits(hisi_hba
->iost_dma
));
984 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_HI
,
985 upper_32_bits(hisi_hba
->iost_dma
));
988 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_LO
,
989 lower_32_bits(hisi_hba
->breakpoint_dma
));
991 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_HI
,
992 upper_32_bits(hisi_hba
->breakpoint_dma
));
994 /* SATA broken msg */
995 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_LO
,
996 lower_32_bits(hisi_hba
->sata_breakpoint_dma
));
998 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_HI
,
999 upper_32_bits(hisi_hba
->sata_breakpoint_dma
));
1001 /* SATA initial fis */
1002 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_LO
,
1003 lower_32_bits(hisi_hba
->initial_fis_dma
));
1005 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_HI
,
1006 upper_32_bits(hisi_hba
->initial_fis_dma
));
1009 static void hisi_sas_link_timeout_enable_link(unsigned long data
)
1011 struct hisi_hba
*hisi_hba
= (struct hisi_hba
*)data
;
1014 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1015 reg_val
= hisi_sas_phy_read32(hisi_hba
, i
, CON_CONTROL
);
1016 if (!(reg_val
& BIT(0))) {
1017 hisi_sas_phy_write32(hisi_hba
, i
,
1023 hisi_hba
->timer
.function
= hisi_sas_link_timeout_disable_link
;
1024 mod_timer(&hisi_hba
->timer
, jiffies
+ msecs_to_jiffies(900));
1027 static void hisi_sas_link_timeout_disable_link(unsigned long data
)
1029 struct hisi_hba
*hisi_hba
= (struct hisi_hba
*)data
;
1032 reg_val
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1033 for (i
= 0; i
< hisi_hba
->n_phy
&& reg_val
; i
++) {
1034 if (reg_val
& BIT(i
)) {
1035 hisi_sas_phy_write32(hisi_hba
, i
,
1041 hisi_hba
->timer
.function
= hisi_sas_link_timeout_enable_link
;
1042 mod_timer(&hisi_hba
->timer
, jiffies
+ msecs_to_jiffies(100));
1045 static void set_link_timer_quirk(struct hisi_hba
*hisi_hba
)
1047 hisi_hba
->timer
.data
= (unsigned long)hisi_hba
;
1048 hisi_hba
->timer
.function
= hisi_sas_link_timeout_disable_link
;
1049 hisi_hba
->timer
.expires
= jiffies
+ msecs_to_jiffies(1000);
1050 add_timer(&hisi_hba
->timer
);
1053 static int hw_init_v2_hw(struct hisi_hba
*hisi_hba
)
1055 struct device
*dev
= &hisi_hba
->pdev
->dev
;
1058 rc
= reset_hw_v2_hw(hisi_hba
);
1060 dev_err(dev
, "hisi_sas_reset_hw failed, rc=%d", rc
);
1065 init_reg_v2_hw(hisi_hba
);
1070 static void enable_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1072 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
1074 cfg
|= PHY_CFG_ENA_MSK
;
1075 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
1078 static void disable_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1080 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
1082 cfg
&= ~PHY_CFG_ENA_MSK
;
1083 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
1086 static void start_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1088 config_id_frame_v2_hw(hisi_hba
, phy_no
);
1089 config_phy_opt_mode_v2_hw(hisi_hba
, phy_no
);
1090 enable_phy_v2_hw(hisi_hba
, phy_no
);
1093 static void stop_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1095 disable_phy_v2_hw(hisi_hba
, phy_no
);
1098 static void stop_phys_v2_hw(struct hisi_hba
*hisi_hba
)
1102 for (i
= 0; i
< hisi_hba
->n_phy
; i
++)
1103 stop_phy_v2_hw(hisi_hba
, i
);
1106 static void phy_hard_reset_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1108 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1111 stop_phy_v2_hw(hisi_hba
, phy_no
);
1112 if (phy
->identify
.device_type
== SAS_END_DEVICE
) {
1113 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
1114 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
1115 txid_auto
| TX_HARDRST_MSK
);
1118 start_phy_v2_hw(hisi_hba
, phy_no
);
1121 static void start_phys_v2_hw(struct hisi_hba
*hisi_hba
)
1125 for (i
= 0; i
< hisi_hba
->n_phy
; i
++)
1126 start_phy_v2_hw(hisi_hba
, i
);
1129 static void phys_init_v2_hw(struct hisi_hba
*hisi_hba
)
1131 start_phys_v2_hw(hisi_hba
);
1134 static void sl_notify_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1138 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
1139 sl_control
|= SL_CONTROL_NOTIFY_EN_MSK
;
1140 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
1142 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
1143 sl_control
&= ~SL_CONTROL_NOTIFY_EN_MSK
;
1144 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
1147 static enum sas_linkrate
phy_get_max_linkrate_v2_hw(void)
1149 return SAS_LINK_RATE_12_0_GBPS
;
1152 static void phy_set_linkrate_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
,
1153 struct sas_phy_linkrates
*r
)
1155 u32 prog_phy_link_rate
=
1156 hisi_sas_phy_read32(hisi_hba
, phy_no
, PROG_PHY_LINK_RATE
);
1157 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1158 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1160 enum sas_linkrate min
, max
;
1163 if (r
->maximum_linkrate
== SAS_LINK_RATE_UNKNOWN
) {
1164 max
= sas_phy
->phy
->maximum_linkrate
;
1165 min
= r
->minimum_linkrate
;
1166 } else if (r
->minimum_linkrate
== SAS_LINK_RATE_UNKNOWN
) {
1167 max
= r
->maximum_linkrate
;
1168 min
= sas_phy
->phy
->minimum_linkrate
;
1172 sas_phy
->phy
->maximum_linkrate
= max
;
1173 sas_phy
->phy
->minimum_linkrate
= min
;
1175 min
-= SAS_LINK_RATE_1_5_GBPS
;
1176 max
-= SAS_LINK_RATE_1_5_GBPS
;
1178 for (i
= 0; i
<= max
; i
++)
1179 rate_mask
|= 1 << (i
* 2);
1181 prog_phy_link_rate
&= ~0xff;
1182 prog_phy_link_rate
|= rate_mask
;
1184 hisi_sas_phy_write32(hisi_hba
, phy_no
, PROG_PHY_LINK_RATE
,
1185 prog_phy_link_rate
);
1187 phy_hard_reset_v2_hw(hisi_hba
, phy_no
);
1190 static int get_wideport_bitmap_v2_hw(struct hisi_hba
*hisi_hba
, int port_id
)
1193 u32 phy_port_num_ma
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
1194 u32 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1196 for (i
= 0; i
< (hisi_hba
->n_phy
< 9 ? hisi_hba
->n_phy
: 8); i
++)
1197 if (phy_state
& 1 << i
)
1198 if (((phy_port_num_ma
>> (i
* 4)) & 0xf) == port_id
)
1201 if (hisi_hba
->n_phy
== 9) {
1202 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
1204 if (phy_state
& 1 << 8)
1205 if (((port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
1206 PORT_STATE_PHY8_PORT_NUM_OFF
) == port_id
)
1214 * This function allocates across all queues to load balance.
1215 * Slots are allocated from queues in a round-robin fashion.
1217 * The callpath to this function and upto writing the write
1218 * queue pointer should be safe from interruption.
1220 static int get_free_slot_v2_hw(struct hisi_hba
*hisi_hba
, u32 dev_id
,
1223 struct device
*dev
= &hisi_hba
->pdev
->dev
;
1224 struct hisi_sas_dq
*dq
;
1226 int queue
= dev_id
% hisi_hba
->queue_count
;
1228 dq
= &hisi_hba
->dq
[queue
];
1230 r
= hisi_sas_read32_relaxed(hisi_hba
,
1231 DLVRY_Q_0_RD_PTR
+ (queue
* 0x14));
1232 if (r
== (w
+1) % HISI_SAS_QUEUE_SLOTS
) {
1233 dev_warn(dev
, "full queue=%d r=%d w=%d\n\n",
1243 static void start_delivery_v2_hw(struct hisi_hba
*hisi_hba
)
1245 int dlvry_queue
= hisi_hba
->slot_prep
->dlvry_queue
;
1246 int dlvry_queue_slot
= hisi_hba
->slot_prep
->dlvry_queue_slot
;
1247 struct hisi_sas_dq
*dq
= &hisi_hba
->dq
[dlvry_queue
];
1249 dq
->wr_point
= ++dlvry_queue_slot
% HISI_SAS_QUEUE_SLOTS
;
1250 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_WR_PTR
+ (dlvry_queue
* 0x14),
1254 static int prep_prd_sge_v2_hw(struct hisi_hba
*hisi_hba
,
1255 struct hisi_sas_slot
*slot
,
1256 struct hisi_sas_cmd_hdr
*hdr
,
1257 struct scatterlist
*scatter
,
1260 struct device
*dev
= &hisi_hba
->pdev
->dev
;
1261 struct scatterlist
*sg
;
1264 if (n_elem
> HISI_SAS_SGE_PAGE_CNT
) {
1265 dev_err(dev
, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1270 slot
->sge_page
= dma_pool_alloc(hisi_hba
->sge_page_pool
, GFP_ATOMIC
,
1271 &slot
->sge_page_dma
);
1272 if (!slot
->sge_page
)
1275 for_each_sg(scatter
, sg
, n_elem
, i
) {
1276 struct hisi_sas_sge
*entry
= &slot
->sge_page
->sge
[i
];
1278 entry
->addr
= cpu_to_le64(sg_dma_address(sg
));
1279 entry
->page_ctrl_0
= entry
->page_ctrl_1
= 0;
1280 entry
->data_len
= cpu_to_le32(sg_dma_len(sg
));
1281 entry
->data_off
= 0;
1284 hdr
->prd_table_addr
= cpu_to_le64(slot
->sge_page_dma
);
1286 hdr
->sg_len
= cpu_to_le32(n_elem
<< CMD_HDR_DATA_SGL_LEN_OFF
);
1291 static int prep_smp_v2_hw(struct hisi_hba
*hisi_hba
,
1292 struct hisi_sas_slot
*slot
)
1294 struct sas_task
*task
= slot
->task
;
1295 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1296 struct domain_device
*device
= task
->dev
;
1297 struct device
*dev
= &hisi_hba
->pdev
->dev
;
1298 struct hisi_sas_port
*port
= slot
->port
;
1299 struct scatterlist
*sg_req
, *sg_resp
;
1300 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
1301 dma_addr_t req_dma_addr
;
1302 unsigned int req_len
, resp_len
;
1306 * DMA-map SMP request, response buffers
1309 sg_req
= &task
->smp_task
.smp_req
;
1310 elem
= dma_map_sg(dev
, sg_req
, 1, DMA_TO_DEVICE
);
1313 req_len
= sg_dma_len(sg_req
);
1314 req_dma_addr
= sg_dma_address(sg_req
);
1317 sg_resp
= &task
->smp_task
.smp_resp
;
1318 elem
= dma_map_sg(dev
, sg_resp
, 1, DMA_FROM_DEVICE
);
1323 resp_len
= sg_dma_len(sg_resp
);
1324 if ((req_len
& 0x3) || (resp_len
& 0x3)) {
1331 hdr
->dw0
= cpu_to_le32((port
->id
<< CMD_HDR_PORT_OFF
) |
1332 (1 << CMD_HDR_PRIORITY_OFF
) | /* high pri */
1333 (2 << CMD_HDR_CMD_OFF
)); /* smp */
1335 /* map itct entry */
1336 hdr
->dw1
= cpu_to_le32((sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
) |
1337 (1 << CMD_HDR_FRAME_TYPE_OFF
) |
1338 (DIR_NO_DATA
<< CMD_HDR_DIR_OFF
));
1341 hdr
->dw2
= cpu_to_le32((((req_len
- 4) / 4) << CMD_HDR_CFL_OFF
) |
1342 (HISI_SAS_MAX_SMP_RESP_SZ
/ 4 <<
1345 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
<< CMD_HDR_IPTT_OFF
);
1347 hdr
->cmd_table_addr
= cpu_to_le64(req_dma_addr
);
1348 hdr
->sts_buffer_addr
= cpu_to_le64(slot
->status_buffer_dma
);
1353 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_resp
, 1,
1356 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_req
, 1,
1361 static int prep_ssp_v2_hw(struct hisi_hba
*hisi_hba
,
1362 struct hisi_sas_slot
*slot
, int is_tmf
,
1363 struct hisi_sas_tmf_task
*tmf
)
1365 struct sas_task
*task
= slot
->task
;
1366 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1367 struct domain_device
*device
= task
->dev
;
1368 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
1369 struct hisi_sas_port
*port
= slot
->port
;
1370 struct sas_ssp_task
*ssp_task
= &task
->ssp_task
;
1371 struct scsi_cmnd
*scsi_cmnd
= ssp_task
->cmd
;
1372 int has_data
= 0, rc
, priority
= is_tmf
;
1374 u32 dw1
= 0, dw2
= 0;
1376 hdr
->dw0
= cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF
) |
1377 (2 << CMD_HDR_TLR_CTRL_OFF
) |
1378 (port
->id
<< CMD_HDR_PORT_OFF
) |
1379 (priority
<< CMD_HDR_PRIORITY_OFF
) |
1380 (1 << CMD_HDR_CMD_OFF
)); /* ssp */
1382 dw1
= 1 << CMD_HDR_VDTL_OFF
;
1384 dw1
|= 2 << CMD_HDR_FRAME_TYPE_OFF
;
1385 dw1
|= DIR_NO_DATA
<< CMD_HDR_DIR_OFF
;
1387 dw1
|= 1 << CMD_HDR_FRAME_TYPE_OFF
;
1388 switch (scsi_cmnd
->sc_data_direction
) {
1391 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
1393 case DMA_FROM_DEVICE
:
1395 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
1398 dw1
&= ~CMD_HDR_DIR_MSK
;
1402 /* map itct entry */
1403 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
1404 hdr
->dw1
= cpu_to_le32(dw1
);
1406 dw2
= (((sizeof(struct ssp_command_iu
) + sizeof(struct ssp_frame_hdr
)
1407 + 3) / 4) << CMD_HDR_CFL_OFF
) |
1408 ((HISI_SAS_MAX_SSP_RESP_SZ
/ 4) << CMD_HDR_MRFL_OFF
) |
1409 (2 << CMD_HDR_SG_MOD_OFF
);
1410 hdr
->dw2
= cpu_to_le32(dw2
);
1412 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
1415 rc
= prep_prd_sge_v2_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
1421 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
1422 hdr
->cmd_table_addr
= cpu_to_le64(slot
->command_table_dma
);
1423 hdr
->sts_buffer_addr
= cpu_to_le64(slot
->status_buffer_dma
);
1425 buf_cmd
= slot
->command_table
+ sizeof(struct ssp_frame_hdr
);
1427 memcpy(buf_cmd
, &task
->ssp_task
.LUN
, 8);
1429 buf_cmd
[9] = task
->ssp_task
.task_attr
|
1430 (task
->ssp_task
.task_prio
<< 3);
1431 memcpy(buf_cmd
+ 12, task
->ssp_task
.cmd
->cmnd
,
1432 task
->ssp_task
.cmd
->cmd_len
);
1434 buf_cmd
[10] = tmf
->tmf
;
1436 case TMF_ABORT_TASK
:
1437 case TMF_QUERY_TASK
:
1439 (tmf
->tag_of_task_to_be_managed
>> 8) & 0xff;
1441 tmf
->tag_of_task_to_be_managed
& 0xff;
1451 static void sata_done_v2_hw(struct hisi_hba
*hisi_hba
, struct sas_task
*task
,
1452 struct hisi_sas_slot
*slot
)
1454 struct task_status_struct
*ts
= &task
->task_status
;
1455 struct ata_task_resp
*resp
= (struct ata_task_resp
*)ts
->buf
;
1456 struct dev_to_host_fis
*d2h
= slot
->status_buffer
+
1457 sizeof(struct hisi_sas_err_record
);
1459 resp
->frame_len
= sizeof(struct dev_to_host_fis
);
1460 memcpy(&resp
->ending_fis
[0], d2h
, sizeof(struct dev_to_host_fis
));
1462 ts
->buf_valid_size
= sizeof(*resp
);
1465 #define TRANS_TX_ERR 0
1466 #define TRANS_RX_ERR 1
1467 #define DMA_TX_ERR 2
1468 #define SIPC_RX_ERR 3
1469 #define DMA_RX_ERR 4
1471 #define DMA_TX_ERR_OFF 0
1472 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1473 #define SIPC_RX_ERR_OFF 16
1474 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1476 static int parse_trans_tx_err_code_v2_hw(u32 err_msk
)
1478 const u8 trans_tx_err_code_prio
[] = {
1479 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
,
1480 TRANS_TX_ERR_PHY_NOT_ENABLE
,
1481 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
,
1482 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
,
1483 TRANS_TX_OPEN_CNX_ERR_BY_OTHER
,
1485 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
,
1486 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
,
1487 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
,
1488 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
,
1489 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
,
1490 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
,
1491 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
,
1492 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
,
1493 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
,
1494 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
,
1495 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
,
1496 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
,
1497 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
,
1498 TRANS_TX_ERR_WITH_CLOSE_COMINIT
,
1499 TRANS_TX_ERR_WITH_BREAK_TIMEOUT
,
1500 TRANS_TX_ERR_WITH_BREAK_REQUEST
,
1501 TRANS_TX_ERR_WITH_BREAK_RECEVIED
,
1502 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
,
1503 TRANS_TX_ERR_WITH_CLOSE_NORMAL
,
1504 TRANS_TX_ERR_WITH_NAK_RECEVIED
,
1505 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
,
1506 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
,
1507 TRANS_TX_ERR_WITH_IPTT_CONFLICT
,
1508 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS
,
1509 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
,
1513 for (i
= 0; i
< ARRAY_SIZE(trans_tx_err_code_prio
); i
++) {
1514 index
= trans_tx_err_code_prio
[i
] - TRANS_TX_FAIL_BASE
;
1515 if (err_msk
& (1 << index
))
1516 return trans_tx_err_code_prio
[i
];
1521 static int parse_trans_rx_err_code_v2_hw(u32 err_msk
)
1523 const u8 trans_rx_err_code_prio
[] = {
1524 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
,
1525 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
,
1526 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
,
1527 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
,
1528 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
,
1529 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
,
1530 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
,
1531 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
,
1532 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
,
1533 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
,
1534 TRANS_RX_ERR_WITH_CLOSE_COMINIT
,
1535 TRANS_RX_ERR_WITH_BREAK_TIMEOUT
,
1536 TRANS_RX_ERR_WITH_BREAK_REQUEST
,
1537 TRANS_RX_ERR_WITH_BREAK_RECEVIED
,
1539 TRANS_RX_ERR_WITH_CLOSE_NORMAL
,
1540 TRANS_RX_ERR_WITH_DATA_LEN0
,
1541 TRANS_RX_ERR_WITH_BAD_HASH
,
1542 TRANS_RX_XRDY_WLEN_ZERO_ERR
,
1543 TRANS_RX_SSP_FRM_LEN_ERR
,
1548 TRANS_RX_ERR_WITH_BAD_FRM_TYPE
,
1549 TRANS_RX_SMP_FRM_LEN_ERR
,
1550 TRANS_RX_SMP_RESP_TIMEOUT_ERR
,
1559 for (i
= 0; i
< ARRAY_SIZE(trans_rx_err_code_prio
); i
++) {
1560 index
= trans_rx_err_code_prio
[i
] - TRANS_RX_FAIL_BASE
;
1561 if (err_msk
& (1 << index
))
1562 return trans_rx_err_code_prio
[i
];
1567 static int parse_dma_tx_err_code_v2_hw(u32 err_msk
)
1569 const u8 dma_tx_err_code_prio
[] = {
1570 DMA_TX_UNEXP_XFER_ERR
,
1571 DMA_TX_UNEXP_RETRANS_ERR
,
1572 DMA_TX_XFER_LEN_OVERFLOW
,
1573 DMA_TX_XFER_OFFSET_ERR
,
1575 DMA_TX_DIF_LEN_ALIGN_ERR
,
1579 DMA_TX_DATA_SGL_OVERFLOW
,
1580 DMA_TX_DIF_SGL_OVERFLOW
,
1584 for (i
= 0; i
< ARRAY_SIZE(dma_tx_err_code_prio
); i
++) {
1585 index
= dma_tx_err_code_prio
[i
] - DMA_TX_ERR_BASE
;
1586 err_msk
= err_msk
& DMA_TX_ERR_MSK
;
1587 if (err_msk
& (1 << index
))
1588 return dma_tx_err_code_prio
[i
];
1593 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk
)
1595 const u8 sipc_rx_err_code_prio
[] = {
1596 SIPC_RX_FIS_STATUS_ERR_BIT_VLD
,
1597 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR
,
1598 SIPC_RX_FIS_STATUS_BSY_BIT_ERR
,
1599 SIPC_RX_WRSETUP_LEN_ODD_ERR
,
1600 SIPC_RX_WRSETUP_LEN_ZERO_ERR
,
1601 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR
,
1602 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR
,
1603 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR
,
1604 SIPC_RX_SATA_UNEXP_FIS_ERR
,
1605 SIPC_RX_WRSETUP_ESTATUS_ERR
,
1606 SIPC_RX_DATA_UNDERFLOW_ERR
,
1610 for (i
= 0; i
< ARRAY_SIZE(sipc_rx_err_code_prio
); i
++) {
1611 index
= sipc_rx_err_code_prio
[i
] - SIPC_RX_ERR_BASE
;
1612 err_msk
= err_msk
& SIPC_RX_ERR_MSK
;
1613 if (err_msk
& (1 << (index
+ 0x10)))
1614 return sipc_rx_err_code_prio
[i
];
1619 static int parse_dma_rx_err_code_v2_hw(u32 err_msk
)
1621 const u8 dma_rx_err_code_prio
[] = {
1622 DMA_RX_UNKNOWN_FRM_ERR
,
1623 DMA_RX_DATA_LEN_OVERFLOW
,
1624 DMA_RX_DATA_LEN_UNDERFLOW
,
1625 DMA_RX_DATA_OFFSET_ERR
,
1627 DMA_RX_SATA_FRAME_TYPE_ERR
,
1628 DMA_RX_RESP_BUF_OVERFLOW
,
1629 DMA_RX_UNEXP_RETRANS_RESP_ERR
,
1630 DMA_RX_UNEXP_NORM_RESP_ERR
,
1631 DMA_RX_UNEXP_RDFRAME_ERR
,
1632 DMA_RX_PIO_DATA_LEN_ERR
,
1633 DMA_RX_RDSETUP_STATUS_ERR
,
1634 DMA_RX_RDSETUP_STATUS_DRQ_ERR
,
1635 DMA_RX_RDSETUP_STATUS_BSY_ERR
,
1636 DMA_RX_RDSETUP_LEN_ODD_ERR
,
1637 DMA_RX_RDSETUP_LEN_ZERO_ERR
,
1638 DMA_RX_RDSETUP_LEN_OVER_ERR
,
1639 DMA_RX_RDSETUP_OFFSET_ERR
,
1640 DMA_RX_RDSETUP_ACTIVE_ERR
,
1641 DMA_RX_RDSETUP_ESTATUS_ERR
,
1646 DMA_RX_DATA_SGL_OVERFLOW
,
1647 DMA_RX_DIF_SGL_OVERFLOW
,
1651 for (i
= 0; i
< ARRAY_SIZE(dma_rx_err_code_prio
); i
++) {
1652 index
= dma_rx_err_code_prio
[i
] - DMA_RX_ERR_BASE
;
1653 if (err_msk
& (1 << index
))
1654 return dma_rx_err_code_prio
[i
];
1659 /* by default, task resp is complete */
1660 static void slot_err_v2_hw(struct hisi_hba
*hisi_hba
,
1661 struct sas_task
*task
,
1662 struct hisi_sas_slot
*slot
,
1665 struct task_status_struct
*ts
= &task
->task_status
;
1666 struct hisi_sas_err_record_v2
*err_record
= slot
->status_buffer
;
1667 u32 trans_tx_fail_type
= cpu_to_le32(err_record
->trans_tx_fail_type
);
1668 u32 trans_rx_fail_type
= cpu_to_le32(err_record
->trans_rx_fail_type
);
1669 u16 dma_tx_err_type
= cpu_to_le16(err_record
->dma_tx_err_type
);
1670 u16 sipc_rx_err_type
= cpu_to_le16(err_record
->sipc_rx_err_type
);
1671 u32 dma_rx_err_type
= cpu_to_le32(err_record
->dma_rx_err_type
);
1674 if (err_phase
== 1) {
1675 /* error in TX phase, the priority of error is: DW2 > DW0 */
1676 error
= parse_dma_tx_err_code_v2_hw(dma_tx_err_type
);
1678 error
= parse_trans_tx_err_code_v2_hw(
1679 trans_tx_fail_type
);
1680 } else if (err_phase
== 2) {
1681 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
1682 error
= parse_trans_rx_err_code_v2_hw(
1683 trans_rx_fail_type
);
1685 error
= parse_dma_rx_err_code_v2_hw(
1688 error
= parse_sipc_rx_err_code_v2_hw(
1693 switch (task
->task_proto
) {
1694 case SAS_PROTOCOL_SSP
:
1697 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
:
1699 ts
->stat
= SAS_OPEN_REJECT
;
1700 ts
->open_rej_reason
= SAS_OREJ_NO_DEST
;
1702 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
:
1704 ts
->stat
= SAS_OPEN_REJECT
;
1705 ts
->open_rej_reason
= SAS_OREJ_EPROTO
;
1708 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
:
1710 ts
->stat
= SAS_OPEN_REJECT
;
1711 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
1714 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
:
1716 ts
->stat
= SAS_OPEN_REJECT
;
1717 ts
->open_rej_reason
= SAS_OREJ_BAD_DEST
;
1720 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
:
1722 ts
->stat
= SAS_OPEN_REJECT
;
1723 ts
->open_rej_reason
= SAS_OREJ_WRONG_DEST
;
1726 case DMA_RX_UNEXP_NORM_RESP_ERR
:
1727 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
:
1728 case DMA_RX_RESP_BUF_OVERFLOW
:
1730 ts
->stat
= SAS_OPEN_REJECT
;
1731 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
1734 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
:
1737 ts
->stat
= SAS_DEV_NO_RESPONSE
;
1740 case DMA_RX_DATA_LEN_OVERFLOW
:
1742 ts
->stat
= SAS_DATA_OVERRUN
;
1746 case DMA_RX_DATA_LEN_UNDERFLOW
:
1748 ts
->residual
= dma_rx_err_type
;
1749 ts
->stat
= SAS_DATA_UNDERRUN
;
1752 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
:
1753 case TRANS_TX_ERR_PHY_NOT_ENABLE
:
1754 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER
:
1755 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
:
1756 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
:
1757 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
:
1758 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
:
1759 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
:
1760 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT
:
1761 case TRANS_TX_ERR_WITH_BREAK_REQUEST
:
1762 case TRANS_TX_ERR_WITH_BREAK_RECEVIED
:
1763 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
:
1764 case TRANS_TX_ERR_WITH_CLOSE_NORMAL
:
1765 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
:
1766 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
1767 case TRANS_TX_ERR_WITH_CLOSE_COMINIT
:
1768 case TRANS_TX_ERR_WITH_NAK_RECEVIED
:
1769 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
:
1770 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
:
1771 case TRANS_TX_ERR_WITH_IPTT_CONFLICT
:
1772 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
:
1773 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
:
1774 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
:
1775 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
:
1776 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT
:
1777 case TRANS_RX_ERR_WITH_BREAK_REQUEST
:
1778 case TRANS_RX_ERR_WITH_BREAK_RECEVIED
:
1779 case TRANS_RX_ERR_WITH_CLOSE_NORMAL
:
1780 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
1781 case TRANS_RX_ERR_WITH_CLOSE_COMINIT
:
1782 case TRANS_TX_ERR_FRAME_TXED
:
1783 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
:
1784 case TRANS_RX_ERR_WITH_DATA_LEN0
:
1785 case TRANS_RX_ERR_WITH_BAD_HASH
:
1786 case TRANS_RX_XRDY_WLEN_ZERO_ERR
:
1787 case TRANS_RX_SSP_FRM_LEN_ERR
:
1788 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE
:
1789 case DMA_TX_DATA_SGL_OVERFLOW
:
1790 case DMA_TX_UNEXP_XFER_ERR
:
1791 case DMA_TX_UNEXP_RETRANS_ERR
:
1792 case DMA_TX_XFER_LEN_OVERFLOW
:
1793 case DMA_TX_XFER_OFFSET_ERR
:
1794 case SIPC_RX_DATA_UNDERFLOW_ERR
:
1795 case DMA_RX_DATA_SGL_OVERFLOW
:
1796 case DMA_RX_DATA_OFFSET_ERR
:
1797 case DMA_RX_RDSETUP_LEN_ODD_ERR
:
1798 case DMA_RX_RDSETUP_LEN_ZERO_ERR
:
1799 case DMA_RX_RDSETUP_LEN_OVER_ERR
:
1800 case DMA_RX_SATA_FRAME_TYPE_ERR
:
1801 case DMA_RX_UNKNOWN_FRM_ERR
:
1803 /* This will request a retry */
1804 ts
->stat
= SAS_QUEUE_FULL
;
1813 case SAS_PROTOCOL_SMP
:
1814 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
1817 case SAS_PROTOCOL_SATA
:
1818 case SAS_PROTOCOL_STP
:
1819 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
1822 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
:
1824 ts
->stat
= SAS_OPEN_REJECT
;
1825 ts
->open_rej_reason
= SAS_OREJ_NO_DEST
;
1828 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
:
1830 ts
->resp
= SAS_TASK_UNDELIVERED
;
1831 ts
->stat
= SAS_DEV_NO_RESPONSE
;
1834 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
:
1836 ts
->stat
= SAS_OPEN_REJECT
;
1837 ts
->open_rej_reason
= SAS_OREJ_EPROTO
;
1840 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
:
1842 ts
->stat
= SAS_OPEN_REJECT
;
1843 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
1846 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
:
1848 ts
->stat
= SAS_OPEN_REJECT
;
1849 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
1852 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
:
1854 ts
->stat
= SAS_OPEN_REJECT
;
1855 ts
->open_rej_reason
= SAS_OREJ_WRONG_DEST
;
1858 case DMA_RX_RESP_BUF_OVERFLOW
:
1859 case DMA_RX_UNEXP_NORM_RESP_ERR
:
1860 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
:
1862 ts
->stat
= SAS_OPEN_REJECT
;
1863 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
1866 case DMA_RX_DATA_LEN_OVERFLOW
:
1868 ts
->stat
= SAS_DATA_OVERRUN
;
1872 case DMA_RX_DATA_LEN_UNDERFLOW
:
1874 ts
->residual
= dma_rx_err_type
;
1875 ts
->stat
= SAS_DATA_UNDERRUN
;
1878 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
:
1879 case TRANS_TX_ERR_PHY_NOT_ENABLE
:
1880 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER
:
1881 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
:
1882 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
:
1883 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
:
1884 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
:
1885 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
:
1886 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT
:
1887 case TRANS_TX_ERR_WITH_BREAK_REQUEST
:
1888 case TRANS_TX_ERR_WITH_BREAK_RECEVIED
:
1889 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
:
1890 case TRANS_TX_ERR_WITH_CLOSE_NORMAL
:
1891 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
:
1892 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
1893 case TRANS_TX_ERR_WITH_CLOSE_COMINIT
:
1894 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
:
1895 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
:
1896 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS
:
1897 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
:
1898 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
:
1899 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
:
1900 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
:
1901 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
:
1902 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
:
1903 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
:
1904 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
:
1905 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT
:
1906 case TRANS_RX_ERR_WITH_BREAK_REQUEST
:
1907 case TRANS_RX_ERR_WITH_BREAK_RECEVIED
:
1908 case TRANS_RX_ERR_WITH_CLOSE_NORMAL
:
1909 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
:
1910 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
1911 case TRANS_RX_ERR_WITH_CLOSE_COMINIT
:
1912 case TRANS_RX_ERR_WITH_DATA_LEN0
:
1913 case TRANS_RX_ERR_WITH_BAD_HASH
:
1914 case TRANS_RX_XRDY_WLEN_ZERO_ERR
:
1915 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE
:
1916 case DMA_TX_DATA_SGL_OVERFLOW
:
1917 case DMA_TX_UNEXP_XFER_ERR
:
1918 case DMA_TX_UNEXP_RETRANS_ERR
:
1919 case DMA_TX_XFER_LEN_OVERFLOW
:
1920 case DMA_TX_XFER_OFFSET_ERR
:
1921 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD
:
1922 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR
:
1923 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR
:
1924 case SIPC_RX_WRSETUP_LEN_ODD_ERR
:
1925 case SIPC_RX_WRSETUP_LEN_ZERO_ERR
:
1926 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR
:
1927 case SIPC_RX_SATA_UNEXP_FIS_ERR
:
1928 case DMA_RX_DATA_SGL_OVERFLOW
:
1929 case DMA_RX_DATA_OFFSET_ERR
:
1930 case DMA_RX_SATA_FRAME_TYPE_ERR
:
1931 case DMA_RX_UNEXP_RDFRAME_ERR
:
1932 case DMA_RX_PIO_DATA_LEN_ERR
:
1933 case DMA_RX_RDSETUP_STATUS_ERR
:
1934 case DMA_RX_RDSETUP_STATUS_DRQ_ERR
:
1935 case DMA_RX_RDSETUP_STATUS_BSY_ERR
:
1936 case DMA_RX_RDSETUP_LEN_ODD_ERR
:
1937 case DMA_RX_RDSETUP_LEN_ZERO_ERR
:
1938 case DMA_RX_RDSETUP_LEN_OVER_ERR
:
1939 case DMA_RX_RDSETUP_OFFSET_ERR
:
1940 case DMA_RX_RDSETUP_ACTIVE_ERR
:
1941 case DMA_RX_RDSETUP_ESTATUS_ERR
:
1942 case DMA_RX_UNKNOWN_FRM_ERR
:
1943 case TRANS_RX_SSP_FRM_LEN_ERR
:
1944 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
:
1947 ts
->stat
= SAS_PHY_DOWN
;
1952 ts
->stat
= SAS_PROTO_RESPONSE
;
1956 sata_done_v2_hw(hisi_hba
, task
, slot
);
1965 slot_complete_v2_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_slot
*slot
)
1967 struct sas_task
*task
= slot
->task
;
1968 struct hisi_sas_device
*sas_dev
;
1969 struct device
*dev
= &hisi_hba
->pdev
->dev
;
1970 struct task_status_struct
*ts
;
1971 struct domain_device
*device
;
1972 enum exec_status sts
;
1973 struct hisi_sas_complete_v2_hdr
*complete_queue
=
1974 hisi_hba
->complete_hdr
[slot
->cmplt_queue
];
1975 struct hisi_sas_complete_v2_hdr
*complete_hdr
=
1976 &complete_queue
[slot
->cmplt_queue_slot
];
1977 unsigned long flags
;
1980 if (unlikely(!task
|| !task
->lldd_task
|| !task
->dev
))
1983 ts
= &task
->task_status
;
1985 sas_dev
= device
->lldd_dev
;
1987 spin_lock_irqsave(&task
->task_state_lock
, flags
);
1988 aborted
= task
->task_state_flags
& SAS_TASK_STATE_ABORTED
;
1989 task
->task_state_flags
&=
1990 ~(SAS_TASK_STATE_PENDING
| SAS_TASK_AT_INITIATOR
);
1991 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
1993 memset(ts
, 0, sizeof(*ts
));
1994 ts
->resp
= SAS_TASK_COMPLETE
;
1996 if (unlikely(aborted
)) {
1997 ts
->stat
= SAS_ABORTED_TASK
;
1998 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
2002 if (unlikely(!sas_dev
)) {
2003 dev_dbg(dev
, "slot complete: port has no device\n");
2004 ts
->stat
= SAS_PHY_DOWN
;
2008 /* Use SAS+TMF status codes */
2009 switch ((complete_hdr
->dw0
& CMPLT_HDR_ABORT_STAT_MSK
)
2010 >> CMPLT_HDR_ABORT_STAT_OFF
) {
2011 case STAT_IO_ABORTED
:
2012 /* this io has been aborted by abort command */
2013 ts
->stat
= SAS_ABORTED_TASK
;
2015 case STAT_IO_COMPLETE
:
2016 /* internal abort command complete */
2017 ts
->stat
= TMF_RESP_FUNC_SUCC
;
2019 case STAT_IO_NO_DEVICE
:
2020 ts
->stat
= TMF_RESP_FUNC_COMPLETE
;
2022 case STAT_IO_NOT_VALID
:
2023 /* abort single io, controller don't find
2024 * the io need to abort
2026 ts
->stat
= TMF_RESP_FUNC_FAILED
;
2032 if ((complete_hdr
->dw0
& CMPLT_HDR_ERX_MSK
) &&
2033 (!(complete_hdr
->dw0
& CMPLT_HDR_RSPNS_XFRD_MSK
))) {
2034 u32 err_phase
= (complete_hdr
->dw0
& CMPLT_HDR_ERR_PHASE_MSK
)
2035 >> CMPLT_HDR_ERR_PHASE_OFF
;
2037 /* Analyse error happens on which phase TX or RX */
2038 if (ERR_ON_TX_PHASE(err_phase
))
2039 slot_err_v2_hw(hisi_hba
, task
, slot
, 1);
2040 else if (ERR_ON_RX_PHASE(err_phase
))
2041 slot_err_v2_hw(hisi_hba
, task
, slot
, 2);
2043 if (unlikely(slot
->abort
))
2048 switch (task
->task_proto
) {
2049 case SAS_PROTOCOL_SSP
:
2051 struct ssp_response_iu
*iu
= slot
->status_buffer
+
2052 sizeof(struct hisi_sas_err_record
);
2054 sas_ssp_task_response(dev
, task
, iu
);
2057 case SAS_PROTOCOL_SMP
:
2059 struct scatterlist
*sg_resp
= &task
->smp_task
.smp_resp
;
2062 ts
->stat
= SAM_STAT_GOOD
;
2063 to
= kmap_atomic(sg_page(sg_resp
));
2065 dma_unmap_sg(dev
, &task
->smp_task
.smp_resp
, 1,
2067 dma_unmap_sg(dev
, &task
->smp_task
.smp_req
, 1,
2069 memcpy(to
+ sg_resp
->offset
,
2070 slot
->status_buffer
+
2071 sizeof(struct hisi_sas_err_record
),
2072 sg_dma_len(sg_resp
));
2076 case SAS_PROTOCOL_SATA
:
2077 case SAS_PROTOCOL_STP
:
2078 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
2080 ts
->stat
= SAM_STAT_GOOD
;
2081 sata_done_v2_hw(hisi_hba
, task
, slot
);
2085 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
2089 if (!slot
->port
->port_attached
) {
2090 dev_err(dev
, "slot complete: port %d has removed\n",
2091 slot
->port
->sas_port
.id
);
2092 ts
->stat
= SAS_PHY_DOWN
;
2096 spin_lock_irqsave(&task
->task_state_lock
, flags
);
2097 task
->task_state_flags
|= SAS_TASK_STATE_DONE
;
2098 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
2099 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
2102 if (task
->task_done
)
2103 task
->task_done(task
);
2108 static u8
get_ata_protocol(u8 cmd
, int direction
)
2111 case ATA_CMD_FPDMA_WRITE
:
2112 case ATA_CMD_FPDMA_READ
:
2113 case ATA_CMD_FPDMA_RECV
:
2114 case ATA_CMD_FPDMA_SEND
:
2115 case ATA_CMD_NCQ_NON_DATA
:
2116 return SATA_PROTOCOL_FPDMA
;
2118 case ATA_CMD_DOWNLOAD_MICRO
:
2119 case ATA_CMD_ID_ATA
:
2120 case ATA_CMD_PMP_READ
:
2121 case ATA_CMD_READ_LOG_EXT
:
2122 case ATA_CMD_PIO_READ
:
2123 case ATA_CMD_PIO_READ_EXT
:
2124 case ATA_CMD_PMP_WRITE
:
2125 case ATA_CMD_WRITE_LOG_EXT
:
2126 case ATA_CMD_PIO_WRITE
:
2127 case ATA_CMD_PIO_WRITE_EXT
:
2128 return SATA_PROTOCOL_PIO
;
2131 case ATA_CMD_DOWNLOAD_MICRO_DMA
:
2132 case ATA_CMD_PMP_READ_DMA
:
2133 case ATA_CMD_PMP_WRITE_DMA
:
2135 case ATA_CMD_READ_EXT
:
2136 case ATA_CMD_READ_LOG_DMA_EXT
:
2137 case ATA_CMD_READ_STREAM_DMA_EXT
:
2138 case ATA_CMD_TRUSTED_RCV_DMA
:
2139 case ATA_CMD_TRUSTED_SND_DMA
:
2141 case ATA_CMD_WRITE_EXT
:
2142 case ATA_CMD_WRITE_FUA_EXT
:
2143 case ATA_CMD_WRITE_QUEUED
:
2144 case ATA_CMD_WRITE_LOG_DMA_EXT
:
2145 case ATA_CMD_WRITE_STREAM_DMA_EXT
:
2146 return SATA_PROTOCOL_DMA
;
2148 case ATA_CMD_CHK_POWER
:
2149 case ATA_CMD_DEV_RESET
:
2152 case ATA_CMD_FLUSH_EXT
:
2153 case ATA_CMD_VERIFY
:
2154 case ATA_CMD_VERIFY_EXT
:
2155 case ATA_CMD_SET_FEATURES
:
2156 case ATA_CMD_STANDBY
:
2157 case ATA_CMD_STANDBYNOW1
:
2158 return SATA_PROTOCOL_NONDATA
;
2160 if (direction
== DMA_NONE
)
2161 return SATA_PROTOCOL_NONDATA
;
2162 return SATA_PROTOCOL_PIO
;
2166 static int get_ncq_tag_v2_hw(struct sas_task
*task
, u32
*tag
)
2168 struct ata_queued_cmd
*qc
= task
->uldd_task
;
2171 if (qc
->tf
.command
== ATA_CMD_FPDMA_WRITE
||
2172 qc
->tf
.command
== ATA_CMD_FPDMA_READ
) {
2180 static int prep_ata_v2_hw(struct hisi_hba
*hisi_hba
,
2181 struct hisi_sas_slot
*slot
)
2183 struct sas_task
*task
= slot
->task
;
2184 struct domain_device
*device
= task
->dev
;
2185 struct domain_device
*parent_dev
= device
->parent
;
2186 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
2187 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
2188 struct asd_sas_port
*sas_port
= device
->port
;
2189 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
2191 int has_data
= 0, rc
= 0, hdr_tag
= 0;
2192 u32 dw1
= 0, dw2
= 0;
2196 hdr
->dw0
= cpu_to_le32(port
->id
<< CMD_HDR_PORT_OFF
);
2197 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
2198 hdr
->dw0
|= cpu_to_le32(3 << CMD_HDR_CMD_OFF
);
2200 hdr
->dw0
|= cpu_to_le32(4 << CMD_HDR_CMD_OFF
);
2203 switch (task
->data_dir
) {
2206 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
2208 case DMA_FROM_DEVICE
:
2210 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
2213 dw1
&= ~CMD_HDR_DIR_MSK
;
2216 if ((task
->ata_task
.fis
.command
== ATA_CMD_DEV_RESET
) &&
2217 (task
->ata_task
.fis
.control
& ATA_SRST
))
2218 dw1
|= 1 << CMD_HDR_RESET_OFF
;
2220 dw1
|= (get_ata_protocol(task
->ata_task
.fis
.command
, task
->data_dir
))
2221 << CMD_HDR_FRAME_TYPE_OFF
;
2222 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
2223 hdr
->dw1
= cpu_to_le32(dw1
);
2226 if (task
->ata_task
.use_ncq
&& get_ncq_tag_v2_hw(task
, &hdr_tag
)) {
2227 task
->ata_task
.fis
.sector_count
|= (u8
) (hdr_tag
<< 3);
2228 dw2
|= hdr_tag
<< CMD_HDR_NCQ_TAG_OFF
;
2231 dw2
|= (HISI_SAS_MAX_STP_RESP_SZ
/ 4) << CMD_HDR_CFL_OFF
|
2232 2 << CMD_HDR_SG_MOD_OFF
;
2233 hdr
->dw2
= cpu_to_le32(dw2
);
2236 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
2239 rc
= prep_prd_sge_v2_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
2246 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
2247 hdr
->cmd_table_addr
= cpu_to_le64(slot
->command_table_dma
);
2248 hdr
->sts_buffer_addr
= cpu_to_le64(slot
->status_buffer_dma
);
2250 buf_cmd
= slot
->command_table
;
2252 if (likely(!task
->ata_task
.device_control_reg_update
))
2253 task
->ata_task
.fis
.flags
|= 0x80; /* C=1: update ATA cmd reg */
2254 /* fill in command FIS */
2255 memcpy(buf_cmd
, &task
->ata_task
.fis
, sizeof(struct host_to_dev_fis
));
2260 static int prep_abort_v2_hw(struct hisi_hba
*hisi_hba
,
2261 struct hisi_sas_slot
*slot
,
2262 int device_id
, int abort_flag
, int tag_to_abort
)
2264 struct sas_task
*task
= slot
->task
;
2265 struct domain_device
*dev
= task
->dev
;
2266 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
2267 struct hisi_sas_port
*port
= slot
->port
;
2270 hdr
->dw0
= cpu_to_le32((5 << CMD_HDR_CMD_OFF
) | /*abort*/
2271 (port
->id
<< CMD_HDR_PORT_OFF
) |
2272 ((dev_is_sata(dev
) ? 1:0) <<
2273 CMD_HDR_ABORT_DEVICE_TYPE_OFF
) |
2274 (abort_flag
<< CMD_HDR_ABORT_FLAG_OFF
));
2277 hdr
->dw1
= cpu_to_le32(device_id
<< CMD_HDR_DEV_ID_OFF
);
2280 hdr
->dw7
= cpu_to_le32(tag_to_abort
<< CMD_HDR_ABORT_IPTT_OFF
);
2281 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
2286 static int phy_up_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2289 u32 context
, port_id
, link_rate
, hard_phy_linkrate
;
2290 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2291 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
2292 struct device
*dev
= &hisi_hba
->pdev
->dev
;
2293 u32
*frame_rcvd
= (u32
*)sas_phy
->frame_rcvd
;
2294 struct sas_identify_frame
*id
= (struct sas_identify_frame
*)frame_rcvd
;
2296 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 1);
2298 /* Check for SATA dev */
2299 context
= hisi_sas_read32(hisi_hba
, PHY_CONTEXT
);
2300 if (context
& (1 << phy_no
))
2304 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
2306 port_id
= (port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
2307 PORT_STATE_PHY8_PORT_NUM_OFF
;
2308 link_rate
= (port_state
& PORT_STATE_PHY8_CONN_RATE_MSK
) >>
2309 PORT_STATE_PHY8_CONN_RATE_OFF
;
2311 port_id
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
2312 port_id
= (port_id
>> (4 * phy_no
)) & 0xf;
2313 link_rate
= hisi_sas_read32(hisi_hba
, PHY_CONN_RATE
);
2314 link_rate
= (link_rate
>> (phy_no
* 4)) & 0xf;
2317 if (port_id
== 0xf) {
2318 dev_err(dev
, "phyup: phy%d invalid portid\n", phy_no
);
2323 for (i
= 0; i
< 6; i
++) {
2324 u32 idaf
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2325 RX_IDAF_DWORD0
+ (i
* 4));
2326 frame_rcvd
[i
] = __swab32(idaf
);
2329 sas_phy
->linkrate
= link_rate
;
2330 hard_phy_linkrate
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2332 phy
->maximum_linkrate
= hard_phy_linkrate
& 0xf;
2333 phy
->minimum_linkrate
= (hard_phy_linkrate
>> 4) & 0xf;
2335 sas_phy
->oob_mode
= SAS_OOB_MODE
;
2336 memcpy(sas_phy
->attached_sas_addr
, &id
->sas_addr
, SAS_ADDR_SIZE
);
2337 dev_info(dev
, "phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
2338 phy
->port_id
= port_id
;
2339 phy
->phy_type
&= ~(PORT_TYPE_SAS
| PORT_TYPE_SATA
);
2340 phy
->phy_type
|= PORT_TYPE_SAS
;
2341 phy
->phy_attached
= 1;
2342 phy
->identify
.device_type
= id
->dev_type
;
2343 phy
->frame_rcvd_size
= sizeof(struct sas_identify_frame
);
2344 if (phy
->identify
.device_type
== SAS_END_DEVICE
)
2345 phy
->identify
.target_port_protocols
=
2347 else if (phy
->identify
.device_type
!= SAS_PHY_UNUSED
) {
2348 phy
->identify
.target_port_protocols
=
2350 if (!timer_pending(&hisi_hba
->timer
))
2351 set_link_timer_quirk(hisi_hba
);
2353 queue_work(hisi_hba
->wq
, &phy
->phyup_ws
);
2356 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
2357 CHL_INT0_SL_PHY_ENABLE_MSK
);
2358 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 0);
2363 static bool check_any_wideports_v2_hw(struct hisi_hba
*hisi_hba
)
2367 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
2368 if (port_state
& 0x1ff)
2374 static int phy_down_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2377 u32 phy_state
, sl_ctrl
, txid_auto
;
2378 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2379 struct hisi_sas_port
*port
= phy
->port
;
2381 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 1);
2383 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
2384 hisi_sas_phy_down(hisi_hba
, phy_no
, (phy_state
& 1 << phy_no
) ? 1 : 0);
2386 sl_ctrl
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
2387 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
,
2388 sl_ctrl
& ~SL_CONTROL_CTA_MSK
);
2389 if (port
&& !get_wideport_bitmap_v2_hw(hisi_hba
, port
->id
))
2390 if (!check_any_wideports_v2_hw(hisi_hba
) &&
2391 timer_pending(&hisi_hba
->timer
))
2392 del_timer(&hisi_hba
->timer
);
2394 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
2395 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
2396 txid_auto
| TXID_AUTO_CT3_MSK
);
2398 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
, CHL_INT0_NOT_RDY_MSK
);
2399 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 0);
2404 static irqreturn_t
int_phy_updown_v2_hw(int irq_no
, void *p
)
2406 struct hisi_hba
*hisi_hba
= p
;
2409 irqreturn_t res
= IRQ_HANDLED
;
2411 irq_msk
= (hisi_sas_read32(hisi_hba
, HGC_INVLD_DQE_INFO
)
2412 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF
) & 0x1ff;
2415 u32 irq_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2418 if (irq_value
& CHL_INT0_SL_PHY_ENABLE_MSK
)
2420 if (phy_up_v2_hw(phy_no
, hisi_hba
)) {
2425 if (irq_value
& CHL_INT0_NOT_RDY_MSK
)
2427 if (phy_down_v2_hw(phy_no
, hisi_hba
)) {
2440 static void phy_bcast_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2442 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2443 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
2444 struct sas_ha_struct
*sas_ha
= &hisi_hba
->sha
;
2447 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 1);
2448 bcast_status
= hisi_sas_phy_read32(hisi_hba
, phy_no
, RX_PRIMS_STATUS
);
2449 if (bcast_status
& RX_BCAST_CHG_MSK
)
2450 sas_ha
->notify_port_event(sas_phy
, PORTE_BROADCAST_RCVD
);
2451 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
2452 CHL_INT0_SL_RX_BCST_ACK_MSK
);
2453 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 0);
2456 static irqreturn_t
int_chnl_int_v2_hw(int irq_no
, void *p
)
2458 struct hisi_hba
*hisi_hba
= p
;
2459 struct device
*dev
= &hisi_hba
->pdev
->dev
;
2460 u32 ent_msk
, ent_tmp
, irq_msk
;
2463 ent_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
2465 ent_msk
|= ENT_INT_SRC_MSK3_ENT95_MSK_MSK
;
2466 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_msk
);
2468 irq_msk
= (hisi_sas_read32(hisi_hba
, HGC_INVLD_DQE_INFO
) >>
2469 HGC_INVLD_DQE_INFO_FB_CH3_OFF
) & 0x1ff;
2472 if (irq_msk
& (1 << phy_no
)) {
2473 u32 irq_value0
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2475 u32 irq_value1
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2477 u32 irq_value2
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2481 if (irq_value1
& (CHL_INT1_DMAC_RX_ECC_ERR_MSK
|
2482 CHL_INT1_DMAC_TX_ECC_ERR_MSK
))
2483 panic("%s: DMAC RX/TX ecc bad error!\
2485 dev_name(dev
), irq_value1
);
2487 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2488 CHL_INT1
, irq_value1
);
2492 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2493 CHL_INT2
, irq_value2
);
2497 if (irq_value0
& CHL_INT0_SL_RX_BCST_ACK_MSK
)
2498 phy_bcast_v2_hw(phy_no
, hisi_hba
);
2500 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2501 CHL_INT0
, irq_value0
2502 & (~CHL_INT0_HOTPLUG_TOUT_MSK
)
2503 & (~CHL_INT0_SL_PHY_ENABLE_MSK
)
2504 & (~CHL_INT0_NOT_RDY_MSK
));
2507 irq_msk
&= ~(1 << phy_no
);
2511 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_tmp
);
2517 one_bit_ecc_error_process_v2_hw(struct hisi_hba
*hisi_hba
, u32 irq_value
)
2519 struct device
*dev
= &hisi_hba
->pdev
->dev
;
2522 if (irq_value
& BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF
)) {
2523 reg_val
= hisi_sas_read32(hisi_hba
, HGC_DQE_ECC_ADDR
);
2524 dev_warn(dev
, "hgc_dqe_acc1b_intr found: \
2525 Ram address is 0x%08X\n",
2526 (reg_val
& HGC_DQE_ECC_1B_ADDR_MSK
) >>
2527 HGC_DQE_ECC_1B_ADDR_OFF
);
2530 if (irq_value
& BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF
)) {
2531 reg_val
= hisi_sas_read32(hisi_hba
, HGC_IOST_ECC_ADDR
);
2532 dev_warn(dev
, "hgc_iost_acc1b_intr found: \
2533 Ram address is 0x%08X\n",
2534 (reg_val
& HGC_IOST_ECC_1B_ADDR_MSK
) >>
2535 HGC_IOST_ECC_1B_ADDR_OFF
);
2538 if (irq_value
& BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF
)) {
2539 reg_val
= hisi_sas_read32(hisi_hba
, HGC_ITCT_ECC_ADDR
);
2540 dev_warn(dev
, "hgc_itct_acc1b_intr found: \
2541 Ram address is 0x%08X\n",
2542 (reg_val
& HGC_ITCT_ECC_1B_ADDR_MSK
) >>
2543 HGC_ITCT_ECC_1B_ADDR_OFF
);
2546 if (irq_value
& BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF
)) {
2547 reg_val
= hisi_sas_read32(hisi_hba
, HGC_LM_DFX_STATUS2
);
2548 dev_warn(dev
, "hgc_iostl_acc1b_intr found: \
2549 memory address is 0x%08X\n",
2550 (reg_val
& HGC_LM_DFX_STATUS2_IOSTLIST_MSK
) >>
2551 HGC_LM_DFX_STATUS2_IOSTLIST_OFF
);
2554 if (irq_value
& BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF
)) {
2555 reg_val
= hisi_sas_read32(hisi_hba
, HGC_LM_DFX_STATUS2
);
2556 dev_warn(dev
, "hgc_itctl_acc1b_intr found: \
2557 memory address is 0x%08X\n",
2558 (reg_val
& HGC_LM_DFX_STATUS2_ITCTLIST_MSK
) >>
2559 HGC_LM_DFX_STATUS2_ITCTLIST_OFF
);
2562 if (irq_value
& BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF
)) {
2563 reg_val
= hisi_sas_read32(hisi_hba
, HGC_CQE_ECC_ADDR
);
2564 dev_warn(dev
, "hgc_cqe_acc1b_intr found: \
2565 Ram address is 0x%08X\n",
2566 (reg_val
& HGC_CQE_ECC_1B_ADDR_MSK
) >>
2567 HGC_CQE_ECC_1B_ADDR_OFF
);
2570 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF
)) {
2571 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS14
);
2572 dev_warn(dev
, "rxm_mem0_acc1b_intr found: \
2573 memory address is 0x%08X\n",
2574 (reg_val
& HGC_RXM_DFX_STATUS14_MEM0_MSK
) >>
2575 HGC_RXM_DFX_STATUS14_MEM0_OFF
);
2578 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF
)) {
2579 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS14
);
2580 dev_warn(dev
, "rxm_mem1_acc1b_intr found: \
2581 memory address is 0x%08X\n",
2582 (reg_val
& HGC_RXM_DFX_STATUS14_MEM1_MSK
) >>
2583 HGC_RXM_DFX_STATUS14_MEM1_OFF
);
2586 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF
)) {
2587 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS14
);
2588 dev_warn(dev
, "rxm_mem2_acc1b_intr found: \
2589 memory address is 0x%08X\n",
2590 (reg_val
& HGC_RXM_DFX_STATUS14_MEM2_MSK
) >>
2591 HGC_RXM_DFX_STATUS14_MEM2_OFF
);
2594 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF
)) {
2595 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS15
);
2596 dev_warn(dev
, "rxm_mem3_acc1b_intr found: \
2597 memory address is 0x%08X\n",
2598 (reg_val
& HGC_RXM_DFX_STATUS15_MEM3_MSK
) >>
2599 HGC_RXM_DFX_STATUS15_MEM3_OFF
);
2604 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba
*hisi_hba
,
2608 struct device
*dev
= &hisi_hba
->pdev
->dev
;
2610 if (irq_value
& BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF
)) {
2611 reg_val
= hisi_sas_read32(hisi_hba
, HGC_DQE_ECC_ADDR
);
2612 panic("%s: hgc_dqe_accbad_intr (0x%x) found: \
2613 Ram address is 0x%08X\n",
2614 dev_name(dev
), irq_value
,
2615 (reg_val
& HGC_DQE_ECC_MB_ADDR_MSK
) >>
2616 HGC_DQE_ECC_MB_ADDR_OFF
);
2619 if (irq_value
& BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF
)) {
2620 reg_val
= hisi_sas_read32(hisi_hba
, HGC_IOST_ECC_ADDR
);
2621 panic("%s: hgc_iost_accbad_intr (0x%x) found: \
2622 Ram address is 0x%08X\n",
2623 dev_name(dev
), irq_value
,
2624 (reg_val
& HGC_IOST_ECC_MB_ADDR_MSK
) >>
2625 HGC_IOST_ECC_MB_ADDR_OFF
);
2628 if (irq_value
& BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF
)) {
2629 reg_val
= hisi_sas_read32(hisi_hba
, HGC_ITCT_ECC_ADDR
);
2630 panic("%s: hgc_itct_accbad_intr (0x%x) found: \
2631 Ram address is 0x%08X\n",
2632 dev_name(dev
), irq_value
,
2633 (reg_val
& HGC_ITCT_ECC_MB_ADDR_MSK
) >>
2634 HGC_ITCT_ECC_MB_ADDR_OFF
);
2637 if (irq_value
& BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF
)) {
2638 reg_val
= hisi_sas_read32(hisi_hba
, HGC_LM_DFX_STATUS2
);
2639 panic("%s: hgc_iostl_accbad_intr (0x%x) found: \
2640 memory address is 0x%08X\n",
2641 dev_name(dev
), irq_value
,
2642 (reg_val
& HGC_LM_DFX_STATUS2_IOSTLIST_MSK
) >>
2643 HGC_LM_DFX_STATUS2_IOSTLIST_OFF
);
2646 if (irq_value
& BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF
)) {
2647 reg_val
= hisi_sas_read32(hisi_hba
, HGC_LM_DFX_STATUS2
);
2648 panic("%s: hgc_itctl_accbad_intr (0x%x) found: \
2649 memory address is 0x%08X\n",
2650 dev_name(dev
), irq_value
,
2651 (reg_val
& HGC_LM_DFX_STATUS2_ITCTLIST_MSK
) >>
2652 HGC_LM_DFX_STATUS2_ITCTLIST_OFF
);
2655 if (irq_value
& BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF
)) {
2656 reg_val
= hisi_sas_read32(hisi_hba
, HGC_CQE_ECC_ADDR
);
2657 panic("%s: hgc_cqe_accbad_intr (0x%x) found: \
2658 Ram address is 0x%08X\n",
2659 dev_name(dev
), irq_value
,
2660 (reg_val
& HGC_CQE_ECC_MB_ADDR_MSK
) >>
2661 HGC_CQE_ECC_MB_ADDR_OFF
);
2664 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF
)) {
2665 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS14
);
2666 panic("%s: rxm_mem0_accbad_intr (0x%x) found: \
2667 memory address is 0x%08X\n",
2668 dev_name(dev
), irq_value
,
2669 (reg_val
& HGC_RXM_DFX_STATUS14_MEM0_MSK
) >>
2670 HGC_RXM_DFX_STATUS14_MEM0_OFF
);
2673 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF
)) {
2674 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS14
);
2675 panic("%s: rxm_mem1_accbad_intr (0x%x) found: \
2676 memory address is 0x%08X\n",
2677 dev_name(dev
), irq_value
,
2678 (reg_val
& HGC_RXM_DFX_STATUS14_MEM1_MSK
) >>
2679 HGC_RXM_DFX_STATUS14_MEM1_OFF
);
2682 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF
)) {
2683 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS14
);
2684 panic("%s: rxm_mem2_accbad_intr (0x%x) found: \
2685 memory address is 0x%08X\n",
2686 dev_name(dev
), irq_value
,
2687 (reg_val
& HGC_RXM_DFX_STATUS14_MEM2_MSK
) >>
2688 HGC_RXM_DFX_STATUS14_MEM2_OFF
);
2691 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF
)) {
2692 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS15
);
2693 panic("%s: rxm_mem3_accbad_intr (0x%x) found: \
2694 memory address is 0x%08X\n",
2695 dev_name(dev
), irq_value
,
2696 (reg_val
& HGC_RXM_DFX_STATUS15_MEM3_MSK
) >>
2697 HGC_RXM_DFX_STATUS15_MEM3_OFF
);
2702 static irqreturn_t
fatal_ecc_int_v2_hw(int irq_no
, void *p
)
2704 struct hisi_hba
*hisi_hba
= p
;
2705 u32 irq_value
, irq_msk
;
2707 irq_msk
= hisi_sas_read32(hisi_hba
, SAS_ECC_INTR_MSK
);
2708 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, irq_msk
| 0xffffffff);
2710 irq_value
= hisi_sas_read32(hisi_hba
, SAS_ECC_INTR
);
2712 one_bit_ecc_error_process_v2_hw(hisi_hba
, irq_value
);
2713 multi_bit_ecc_error_process_v2_hw(hisi_hba
, irq_value
);
2716 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR
, irq_value
);
2717 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, irq_msk
);
2722 #define AXI_ERR_NR 8
2723 static const char axi_err_info
[AXI_ERR_NR
][32] = {
2734 #define FIFO_ERR_NR 5
2735 static const char fifo_err_info
[FIFO_ERR_NR
][32] = {
2743 static irqreturn_t
fatal_axi_int_v2_hw(int irq_no
, void *p
)
2745 struct hisi_hba
*hisi_hba
= p
;
2746 u32 irq_value
, irq_msk
, err_value
;
2747 struct device
*dev
= &hisi_hba
->pdev
->dev
;
2749 irq_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
2750 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, irq_msk
| 0xfffffffe);
2752 irq_value
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
2754 if (irq_value
& BIT(ENT_INT_SRC3_WP_DEPTH_OFF
)) {
2755 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
2756 1 << ENT_INT_SRC3_WP_DEPTH_OFF
);
2757 panic("%s: write pointer and depth error (0x%x) \
2759 dev_name(dev
), irq_value
);
2762 if (irq_value
& BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF
)) {
2763 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
2765 ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF
);
2766 panic("%s: iptt no match slot error (0x%x) found!\n",
2767 dev_name(dev
), irq_value
);
2770 if (irq_value
& BIT(ENT_INT_SRC3_RP_DEPTH_OFF
))
2771 panic("%s: read pointer and depth error (0x%x) \
2773 dev_name(dev
), irq_value
);
2775 if (irq_value
& BIT(ENT_INT_SRC3_AXI_OFF
)) {
2778 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
2779 1 << ENT_INT_SRC3_AXI_OFF
);
2780 err_value
= hisi_sas_read32(hisi_hba
,
2781 HGC_AXI_FIFO_ERR_INFO
);
2783 for (i
= 0; i
< AXI_ERR_NR
; i
++) {
2784 if (err_value
& BIT(i
))
2785 panic("%s: %s (0x%x) found!\n",
2787 axi_err_info
[i
], irq_value
);
2791 if (irq_value
& BIT(ENT_INT_SRC3_FIFO_OFF
)) {
2794 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
2795 1 << ENT_INT_SRC3_FIFO_OFF
);
2796 err_value
= hisi_sas_read32(hisi_hba
,
2797 HGC_AXI_FIFO_ERR_INFO
);
2799 for (i
= 0; i
< FIFO_ERR_NR
; i
++) {
2800 if (err_value
& BIT(AXI_ERR_NR
+ i
))
2801 panic("%s: %s (0x%x) found!\n",
2803 fifo_err_info
[i
], irq_value
);
2808 if (irq_value
& BIT(ENT_INT_SRC3_LM_OFF
)) {
2809 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
2810 1 << ENT_INT_SRC3_LM_OFF
);
2811 panic("%s: LM add/fetch list error (0x%x) found!\n",
2812 dev_name(dev
), irq_value
);
2815 if (irq_value
& BIT(ENT_INT_SRC3_ABT_OFF
)) {
2816 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
2817 1 << ENT_INT_SRC3_ABT_OFF
);
2818 panic("%s: SAS_HGC_ABT fetch LM list error (0x%x) found!\n",
2819 dev_name(dev
), irq_value
);
2823 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, irq_msk
);
2828 static void cq_tasklet_v2_hw(unsigned long val
)
2830 struct hisi_sas_cq
*cq
= (struct hisi_sas_cq
*)val
;
2831 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
2832 struct hisi_sas_slot
*slot
;
2833 struct hisi_sas_itct
*itct
;
2834 struct hisi_sas_complete_v2_hdr
*complete_queue
;
2835 u32 rd_point
= cq
->rd_point
, wr_point
, dev_id
;
2838 complete_queue
= hisi_hba
->complete_hdr
[queue
];
2840 spin_lock(&hisi_hba
->lock
);
2841 wr_point
= hisi_sas_read32(hisi_hba
, COMPL_Q_0_WR_PTR
+
2844 while (rd_point
!= wr_point
) {
2845 struct hisi_sas_complete_v2_hdr
*complete_hdr
;
2848 complete_hdr
= &complete_queue
[rd_point
];
2850 /* Check for NCQ completion */
2851 if (complete_hdr
->act
) {
2852 u32 act_tmp
= complete_hdr
->act
;
2853 int ncq_tag_count
= ffs(act_tmp
);
2855 dev_id
= (complete_hdr
->dw1
& CMPLT_HDR_DEV_ID_MSK
) >>
2856 CMPLT_HDR_DEV_ID_OFF
;
2857 itct
= &hisi_hba
->itct
[dev_id
];
2859 /* The NCQ tags are held in the itct header */
2860 while (ncq_tag_count
) {
2861 __le64
*ncq_tag
= &itct
->qw4_15
[0];
2864 iptt
= (ncq_tag
[ncq_tag_count
/ 5]
2865 >> (ncq_tag_count
% 5) * 12) & 0xfff;
2867 slot
= &hisi_hba
->slot_info
[iptt
];
2868 slot
->cmplt_queue_slot
= rd_point
;
2869 slot
->cmplt_queue
= queue
;
2870 slot_complete_v2_hw(hisi_hba
, slot
);
2872 act_tmp
&= ~(1 << ncq_tag_count
);
2873 ncq_tag_count
= ffs(act_tmp
);
2876 iptt
= (complete_hdr
->dw1
) & CMPLT_HDR_IPTT_MSK
;
2877 slot
= &hisi_hba
->slot_info
[iptt
];
2878 slot
->cmplt_queue_slot
= rd_point
;
2879 slot
->cmplt_queue
= queue
;
2880 slot_complete_v2_hw(hisi_hba
, slot
);
2883 if (++rd_point
>= HISI_SAS_QUEUE_SLOTS
)
2887 /* update rd_point */
2888 cq
->rd_point
= rd_point
;
2889 hisi_sas_write32(hisi_hba
, COMPL_Q_0_RD_PTR
+ (0x14 * queue
), rd_point
);
2890 spin_unlock(&hisi_hba
->lock
);
2893 static irqreturn_t
cq_interrupt_v2_hw(int irq_no
, void *p
)
2895 struct hisi_sas_cq
*cq
= p
;
2896 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
2899 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 1 << queue
);
2901 tasklet_schedule(&cq
->tasklet
);
2906 static irqreturn_t
sata_int_v2_hw(int irq_no
, void *p
)
2908 struct hisi_sas_phy
*phy
= p
;
2909 struct hisi_hba
*hisi_hba
= phy
->hisi_hba
;
2910 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
2911 struct device
*dev
= &hisi_hba
->pdev
->dev
;
2912 struct hisi_sas_initial_fis
*initial_fis
;
2913 struct dev_to_host_fis
*fis
;
2914 u32 ent_tmp
, ent_msk
, ent_int
, port_id
, link_rate
, hard_phy_linkrate
;
2915 irqreturn_t res
= IRQ_HANDLED
;
2916 u8 attached_sas_addr
[SAS_ADDR_SIZE
] = {0};
2919 phy_no
= sas_phy
->id
;
2920 initial_fis
= &hisi_hba
->initial_fis
[phy_no
];
2921 fis
= &initial_fis
->fis
;
2923 offset
= 4 * (phy_no
/ 4);
2924 ent_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
);
2925 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
,
2926 ent_msk
| 1 << ((phy_no
% 4) * 8));
2928 ent_int
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC1
+ offset
);
2929 ent_tmp
= ent_int
& (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF
*
2931 ent_int
>>= ENT_INT_SRC1_D2H_FIS_CH1_OFF
* (phy_no
% 4);
2932 if ((ent_int
& ENT_INT_SRC1_D2H_FIS_CH0_MSK
) == 0) {
2933 dev_warn(dev
, "sata int: phy%d did not receive FIS\n", phy_no
);
2938 /* check ERR bit of Status Register */
2939 if (fis
->status
& ATA_ERR
) {
2940 dev_warn(dev
, "sata int: phy%d FIS status: 0x%x\n", phy_no
,
2942 disable_phy_v2_hw(hisi_hba
, phy_no
);
2943 enable_phy_v2_hw(hisi_hba
, phy_no
);
2948 if (unlikely(phy_no
== 8)) {
2949 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
2951 port_id
= (port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
2952 PORT_STATE_PHY8_PORT_NUM_OFF
;
2953 link_rate
= (port_state
& PORT_STATE_PHY8_CONN_RATE_MSK
) >>
2954 PORT_STATE_PHY8_CONN_RATE_OFF
;
2956 port_id
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
2957 port_id
= (port_id
>> (4 * phy_no
)) & 0xf;
2958 link_rate
= hisi_sas_read32(hisi_hba
, PHY_CONN_RATE
);
2959 link_rate
= (link_rate
>> (phy_no
* 4)) & 0xf;
2962 if (port_id
== 0xf) {
2963 dev_err(dev
, "sata int: phy%d invalid portid\n", phy_no
);
2968 sas_phy
->linkrate
= link_rate
;
2969 hard_phy_linkrate
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2971 phy
->maximum_linkrate
= hard_phy_linkrate
& 0xf;
2972 phy
->minimum_linkrate
= (hard_phy_linkrate
>> 4) & 0xf;
2974 sas_phy
->oob_mode
= SATA_OOB_MODE
;
2975 /* Make up some unique SAS address */
2976 attached_sas_addr
[0] = 0x50;
2977 attached_sas_addr
[7] = phy_no
;
2978 memcpy(sas_phy
->attached_sas_addr
, attached_sas_addr
, SAS_ADDR_SIZE
);
2979 memcpy(sas_phy
->frame_rcvd
, fis
, sizeof(struct dev_to_host_fis
));
2980 dev_info(dev
, "sata int phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
2981 phy
->phy_type
&= ~(PORT_TYPE_SAS
| PORT_TYPE_SATA
);
2982 phy
->port_id
= port_id
;
2983 phy
->phy_type
|= PORT_TYPE_SATA
;
2984 phy
->phy_attached
= 1;
2985 phy
->identify
.device_type
= SAS_SATA_DEV
;
2986 phy
->frame_rcvd_size
= sizeof(struct dev_to_host_fis
);
2987 phy
->identify
.target_port_protocols
= SAS_PROTOCOL_SATA
;
2988 queue_work(hisi_hba
->wq
, &phy
->phyup_ws
);
2991 hisi_sas_write32(hisi_hba
, ENT_INT_SRC1
+ offset
, ent_tmp
);
2992 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
, ent_msk
);
2997 static irq_handler_t phy_interrupts
[HISI_SAS_PHY_INT_NR
] = {
2998 int_phy_updown_v2_hw
,
3002 static irq_handler_t fatal_interrupts
[HISI_SAS_FATAL_INT_NR
] = {
3003 fatal_ecc_int_v2_hw
,
3008 * There is a limitation in the hip06 chipset that we need
3009 * to map in all mbigen interrupts, even if they are not used.
3011 static int interrupt_init_v2_hw(struct hisi_hba
*hisi_hba
)
3013 struct platform_device
*pdev
= hisi_hba
->pdev
;
3014 struct device
*dev
= &pdev
->dev
;
3015 int i
, irq
, rc
, irq_map
[128];
3018 for (i
= 0; i
< 128; i
++)
3019 irq_map
[i
] = platform_get_irq(pdev
, i
);
3021 for (i
= 0; i
< HISI_SAS_PHY_INT_NR
; i
++) {
3024 irq
= irq_map
[idx
+ 1]; /* Phy up/down is irq1 */
3026 dev_err(dev
, "irq init: fail map phy interrupt %d\n",
3031 rc
= devm_request_irq(dev
, irq
, phy_interrupts
[i
], 0,
3032 DRV_NAME
" phy", hisi_hba
);
3034 dev_err(dev
, "irq init: could not request "
3035 "phy interrupt %d, rc=%d\n",
3041 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
3042 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[i
];
3043 int idx
= i
+ 72; /* First SATA interrupt is irq72 */
3047 dev_err(dev
, "irq init: fail map phy interrupt %d\n",
3052 rc
= devm_request_irq(dev
, irq
, sata_int_v2_hw
, 0,
3053 DRV_NAME
" sata", phy
);
3055 dev_err(dev
, "irq init: could not request "
3056 "sata interrupt %d, rc=%d\n",
3062 for (i
= 0; i
< HISI_SAS_FATAL_INT_NR
; i
++) {
3065 irq
= irq_map
[idx
+ 81];
3067 dev_err(dev
, "irq init: fail map fatal interrupt %d\n",
3072 rc
= devm_request_irq(dev
, irq
, fatal_interrupts
[i
], 0,
3073 DRV_NAME
" fatal", hisi_hba
);
3076 "irq init: could not request fatal interrupt %d, rc=%d\n",
3082 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
3083 int idx
= i
+ 96; /* First cq interrupt is irq96 */
3084 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[i
];
3085 struct tasklet_struct
*t
= &cq
->tasklet
;
3090 "irq init: could not map cq interrupt %d\n",
3094 rc
= devm_request_irq(dev
, irq
, cq_interrupt_v2_hw
, 0,
3095 DRV_NAME
" cq", &hisi_hba
->cq
[i
]);
3098 "irq init: could not request cq interrupt %d, rc=%d\n",
3102 tasklet_init(t
, cq_tasklet_v2_hw
, (unsigned long)cq
);
3108 static int hisi_sas_v2_init(struct hisi_hba
*hisi_hba
)
3112 rc
= hw_init_v2_hw(hisi_hba
);
3116 rc
= interrupt_init_v2_hw(hisi_hba
);
3123 static void interrupt_disable_v2_hw(struct hisi_hba
*hisi_hba
)
3125 struct platform_device
*pdev
= hisi_hba
->pdev
;
3128 for (i
= 0; i
< hisi_hba
->queue_count
; i
++)
3129 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+ 0x4 * i
, 0x1);
3131 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0xffffffff);
3132 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0xffffffff);
3133 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0xffffffff);
3134 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0xffffffff);
3136 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
3137 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xffffffff);
3138 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0xffffffff);
3141 for (i
= 0; i
< 128; i
++)
3142 synchronize_irq(platform_get_irq(pdev
, i
));
3145 static int soft_reset_v2_hw(struct hisi_hba
*hisi_hba
)
3147 struct device
*dev
= &hisi_hba
->pdev
->dev
;
3148 u32 old_state
, state
;
3152 old_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
3154 interrupt_disable_v2_hw(hisi_hba
);
3155 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0x0);
3157 stop_phys_v2_hw(hisi_hba
);
3161 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
+ AM_CTRL_GLOBAL
, 0x1);
3163 /* wait until bus idle */
3166 u32 status
= hisi_sas_read32_relaxed(hisi_hba
,
3167 AXI_MASTER_CFG_BASE
+ AM_CURR_TRANS_RETURN
);
3174 dev_info(dev
, "wait axi bus state to idle timeout!\n");
3179 hisi_sas_init_mem(hisi_hba
);
3181 rc
= hw_init_v2_hw(hisi_hba
);
3185 /* Re-enable the PHYs */
3186 for (phy_no
= 0; phy_no
< hisi_hba
->n_phy
; phy_no
++) {
3187 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
3188 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
3190 if (sas_phy
->enabled
)
3191 start_phy_v2_hw(hisi_hba
, phy_no
);
3194 /* Wait for the PHYs to come up and read the PHY state */
3197 state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
3199 hisi_sas_rescan_topology(hisi_hba
, old_state
, state
);
3204 static const struct hisi_sas_hw hisi_sas_v2_hw
= {
3205 .hw_init
= hisi_sas_v2_init
,
3206 .setup_itct
= setup_itct_v2_hw
,
3207 .slot_index_alloc
= slot_index_alloc_quirk_v2_hw
,
3208 .alloc_dev
= alloc_dev_quirk_v2_hw
,
3209 .sl_notify
= sl_notify_v2_hw
,
3210 .get_wideport_bitmap
= get_wideport_bitmap_v2_hw
,
3211 .free_device
= free_device_v2_hw
,
3212 .prep_smp
= prep_smp_v2_hw
,
3213 .prep_ssp
= prep_ssp_v2_hw
,
3214 .prep_stp
= prep_ata_v2_hw
,
3215 .prep_abort
= prep_abort_v2_hw
,
3216 .get_free_slot
= get_free_slot_v2_hw
,
3217 .start_delivery
= start_delivery_v2_hw
,
3218 .slot_complete
= slot_complete_v2_hw
,
3219 .phys_init
= phys_init_v2_hw
,
3220 .phy_enable
= enable_phy_v2_hw
,
3221 .phy_disable
= disable_phy_v2_hw
,
3222 .phy_hard_reset
= phy_hard_reset_v2_hw
,
3223 .phy_set_linkrate
= phy_set_linkrate_v2_hw
,
3224 .phy_get_max_linkrate
= phy_get_max_linkrate_v2_hw
,
3225 .max_command_entries
= HISI_SAS_COMMAND_ENTRIES_V2_HW
,
3226 .complete_hdr_size
= sizeof(struct hisi_sas_complete_v2_hdr
),
3227 .soft_reset
= soft_reset_v2_hw
,
3230 static int hisi_sas_v2_probe(struct platform_device
*pdev
)
3233 * Check if we should defer the probe before we probe the
3234 * upper layer, as it's hard to defer later on.
3236 int ret
= platform_get_irq(pdev
, 0);
3239 if (ret
!= -EPROBE_DEFER
)
3240 dev_err(&pdev
->dev
, "cannot obtain irq\n");
3244 return hisi_sas_probe(pdev
, &hisi_sas_v2_hw
);
3247 static int hisi_sas_v2_remove(struct platform_device
*pdev
)
3249 struct sas_ha_struct
*sha
= platform_get_drvdata(pdev
);
3250 struct hisi_hba
*hisi_hba
= sha
->lldd_ha
;
3252 if (timer_pending(&hisi_hba
->timer
))
3253 del_timer(&hisi_hba
->timer
);
3255 return hisi_sas_remove(pdev
);
3258 static const struct of_device_id sas_v2_of_match
[] = {
3259 { .compatible
= "hisilicon,hip06-sas-v2",},
3260 { .compatible
= "hisilicon,hip07-sas-v2",},
3263 MODULE_DEVICE_TABLE(of
, sas_v2_of_match
);
3265 static const struct acpi_device_id sas_v2_acpi_match
[] = {
3270 MODULE_DEVICE_TABLE(acpi
, sas_v2_acpi_match
);
3272 static struct platform_driver hisi_sas_v2_driver
= {
3273 .probe
= hisi_sas_v2_probe
,
3274 .remove
= hisi_sas_v2_remove
,
3277 .of_match_table
= sas_v2_of_match
,
3278 .acpi_match_table
= ACPI_PTR(sas_v2_acpi_match
),
3282 module_platform_driver(hisi_sas_v2_driver
);
3284 MODULE_LICENSE("GPL");
3285 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3286 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3287 MODULE_ALIAS("platform:" DRV_NAME
);