2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
13 #define DRV_NAME "hisi_sas_v2_hw"
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
148 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
149 #define DLVRY_Q_0_DEPTH 0x268
150 #define DLVRY_Q_0_WR_PTR 0x26c
151 #define DLVRY_Q_0_RD_PTR 0x270
152 #define HYPER_STREAM_ID_EN_CFG 0xc80
153 #define OQ0_INT_SRC_MSK 0xc90
154 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
155 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
156 #define COMPL_Q_0_DEPTH 0x4e8
157 #define COMPL_Q_0_WR_PTR 0x4ec
158 #define COMPL_Q_0_RD_PTR 0x4f0
159 #define HGC_RXM_DFX_STATUS14 0xae8
160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
162 HGC_RXM_DFX_STATUS14_MEM0_OFF)
163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM1_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM2_OFF)
169 #define HGC_RXM_DFX_STATUS15 0xaec
170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
172 HGC_RXM_DFX_STATUS15_MEM3_OFF)
173 /* phy registers need init */
174 #define PORT_BASE (0x2000)
176 #define PHY_CFG (PORT_BASE + 0x0)
177 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PHY_CFG_ENA_OFF 0
179 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
180 #define PHY_CFG_DC_OPT_OFF 2
181 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
182 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
183 #define PROG_PHY_LINK_RATE_MAX_OFF 0
184 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
185 #define PHY_CTRL (PORT_BASE + 0x14)
186 #define PHY_CTRL_RESET_OFF 0
187 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
188 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
189 #define SL_CFG (PORT_BASE + 0x84)
190 #define PHY_PCN (PORT_BASE + 0x44)
191 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
192 #define SL_CONTROL (PORT_BASE + 0x94)
193 #define SL_CONTROL_NOTIFY_EN_OFF 0
194 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
195 #define SL_CONTROL_CTA_OFF 17
196 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
197 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
198 #define RX_BCAST_CHG_OFF 1
199 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
200 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
201 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
202 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
203 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
204 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
205 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
206 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
207 #define TXID_AUTO (PORT_BASE + 0xb8)
208 #define TXID_AUTO_CT3_OFF 1
209 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
210 #define TXID_AUTO_CTB_OFF 11
211 #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
212 #define TX_HARDRST_OFF 2
213 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
214 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
215 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
216 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
217 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
218 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
219 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
220 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
221 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
222 #define CON_CONTROL (PORT_BASE + 0x118)
223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
225 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
226 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
227 #define CHL_INT0 (PORT_BASE + 0x1b4)
228 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
229 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
230 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
231 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
232 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
233 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
234 #define CHL_INT0_NOT_RDY_OFF 4
235 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
236 #define CHL_INT0_PHY_RDY_OFF 5
237 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
238 #define CHL_INT1 (PORT_BASE + 0x1b8)
239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
243 #define CHL_INT2 (PORT_BASE + 0x1bc)
244 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
245 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
246 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
247 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
248 #define DMA_TX_DFX0 (PORT_BASE + 0x200)
249 #define DMA_TX_DFX1 (PORT_BASE + 0x204)
250 #define DMA_TX_DFX1_IPTT_OFF 0
251 #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
252 #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
253 #define PORT_DFX0 (PORT_BASE + 0x258)
254 #define LINK_DFX2 (PORT_BASE + 0X264)
255 #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
256 #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
257 #define LINK_DFX2_SEND_HOLD_STS_OFF 10
258 #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
259 #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
260 #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
261 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
262 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
263 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
264 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
265 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
266 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
267 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
268 #define DMA_TX_STATUS_BUSY_OFF 0
269 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
270 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
271 #define DMA_RX_STATUS_BUSY_OFF 0
272 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
274 #define AXI_CFG (0x5100)
275 #define AM_CFG_MAX_TRANS (0x5010)
276 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
278 #define AXI_MASTER_CFG_BASE (0x5000)
279 #define AM_CTRL_GLOBAL (0x0)
280 #define AM_CURR_TRANS_RETURN (0x150)
282 /* HW dma structures */
283 /* Delivery queue header */
285 #define CMD_HDR_ABORT_FLAG_OFF 0
286 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
287 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
288 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
289 #define CMD_HDR_RESP_REPORT_OFF 5
290 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
291 #define CMD_HDR_TLR_CTRL_OFF 6
292 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
293 #define CMD_HDR_PORT_OFF 18
294 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
295 #define CMD_HDR_PRIORITY_OFF 27
296 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
297 #define CMD_HDR_CMD_OFF 29
298 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
300 #define CMD_HDR_DIR_OFF 5
301 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
302 #define CMD_HDR_RESET_OFF 7
303 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
304 #define CMD_HDR_VDTL_OFF 10
305 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
306 #define CMD_HDR_FRAME_TYPE_OFF 11
307 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
308 #define CMD_HDR_DEV_ID_OFF 16
309 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
311 #define CMD_HDR_CFL_OFF 0
312 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
313 #define CMD_HDR_NCQ_TAG_OFF 10
314 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
315 #define CMD_HDR_MRFL_OFF 15
316 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
317 #define CMD_HDR_SG_MOD_OFF 24
318 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
319 #define CMD_HDR_FIRST_BURST_OFF 26
320 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
322 #define CMD_HDR_IPTT_OFF 0
323 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
325 #define CMD_HDR_DIF_SGL_LEN_OFF 0
326 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
327 #define CMD_HDR_DATA_SGL_LEN_OFF 16
328 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
329 #define CMD_HDR_ABORT_IPTT_OFF 16
330 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
332 /* Completion header */
334 #define CMPLT_HDR_ERR_PHASE_OFF 2
335 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
336 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
337 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
338 #define CMPLT_HDR_ERX_OFF 12
339 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
340 #define CMPLT_HDR_ABORT_STAT_OFF 13
341 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
343 #define STAT_IO_NOT_VALID 0x1
344 #define STAT_IO_NO_DEVICE 0x2
345 #define STAT_IO_COMPLETE 0x3
346 #define STAT_IO_ABORTED 0x4
348 #define CMPLT_HDR_IPTT_OFF 0
349 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
350 #define CMPLT_HDR_DEV_ID_OFF 16
351 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
355 #define ITCT_HDR_DEV_TYPE_OFF 0
356 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
357 #define ITCT_HDR_VALID_OFF 2
358 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
359 #define ITCT_HDR_MCR_OFF 5
360 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
361 #define ITCT_HDR_VLN_OFF 9
362 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
363 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
364 #define ITCT_HDR_SMP_TIMEOUT_8US 1
365 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
367 #define ITCT_HDR_AWT_CONTINUE_OFF 25
368 #define ITCT_HDR_PORT_ID_OFF 28
369 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
371 #define ITCT_HDR_INLT_OFF 0
372 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
373 #define ITCT_HDR_BITLT_OFF 16
374 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
375 #define ITCT_HDR_MCTLT_OFF 32
376 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
377 #define ITCT_HDR_RTOLT_OFF 48
378 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
380 #define HISI_SAS_FATAL_INT_NR 2
382 struct hisi_sas_complete_v2_hdr
{
389 struct hisi_sas_err_record_v2
{
391 __le32 trans_tx_fail_type
;
394 __le32 trans_rx_fail_type
;
397 __le16 dma_tx_err_type
;
398 __le16 sipc_rx_err_type
;
401 __le32 dma_rx_err_type
;
404 static const struct hisi_sas_hw_error one_bit_ecc_errors
[] = {
406 .irq_msk
= BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF
),
407 .msk
= HGC_DQE_ECC_1B_ADDR_MSK
,
408 .shift
= HGC_DQE_ECC_1B_ADDR_OFF
,
409 .msg
= "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
410 .reg
= HGC_DQE_ECC_ADDR
,
413 .irq_msk
= BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF
),
414 .msk
= HGC_IOST_ECC_1B_ADDR_MSK
,
415 .shift
= HGC_IOST_ECC_1B_ADDR_OFF
,
416 .msg
= "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
417 .reg
= HGC_IOST_ECC_ADDR
,
420 .irq_msk
= BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF
),
421 .msk
= HGC_ITCT_ECC_1B_ADDR_MSK
,
422 .shift
= HGC_ITCT_ECC_1B_ADDR_OFF
,
423 .msg
= "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
424 .reg
= HGC_ITCT_ECC_ADDR
,
427 .irq_msk
= BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF
),
428 .msk
= HGC_LM_DFX_STATUS2_IOSTLIST_MSK
,
429 .shift
= HGC_LM_DFX_STATUS2_IOSTLIST_OFF
,
430 .msg
= "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
431 .reg
= HGC_LM_DFX_STATUS2
,
434 .irq_msk
= BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF
),
435 .msk
= HGC_LM_DFX_STATUS2_ITCTLIST_MSK
,
436 .shift
= HGC_LM_DFX_STATUS2_ITCTLIST_OFF
,
437 .msg
= "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
438 .reg
= HGC_LM_DFX_STATUS2
,
441 .irq_msk
= BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF
),
442 .msk
= HGC_CQE_ECC_1B_ADDR_MSK
,
443 .shift
= HGC_CQE_ECC_1B_ADDR_OFF
,
444 .msg
= "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
445 .reg
= HGC_CQE_ECC_ADDR
,
448 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF
),
449 .msk
= HGC_RXM_DFX_STATUS14_MEM0_MSK
,
450 .shift
= HGC_RXM_DFX_STATUS14_MEM0_OFF
,
451 .msg
= "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
452 .reg
= HGC_RXM_DFX_STATUS14
,
455 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF
),
456 .msk
= HGC_RXM_DFX_STATUS14_MEM1_MSK
,
457 .shift
= HGC_RXM_DFX_STATUS14_MEM1_OFF
,
458 .msg
= "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
459 .reg
= HGC_RXM_DFX_STATUS14
,
462 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF
),
463 .msk
= HGC_RXM_DFX_STATUS14_MEM2_MSK
,
464 .shift
= HGC_RXM_DFX_STATUS14_MEM2_OFF
,
465 .msg
= "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
466 .reg
= HGC_RXM_DFX_STATUS14
,
469 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF
),
470 .msk
= HGC_RXM_DFX_STATUS15_MEM3_MSK
,
471 .shift
= HGC_RXM_DFX_STATUS15_MEM3_OFF
,
472 .msg
= "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
473 .reg
= HGC_RXM_DFX_STATUS15
,
477 static const struct hisi_sas_hw_error multi_bit_ecc_errors
[] = {
479 .irq_msk
= BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF
),
480 .msk
= HGC_DQE_ECC_MB_ADDR_MSK
,
481 .shift
= HGC_DQE_ECC_MB_ADDR_OFF
,
482 .msg
= "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
483 .reg
= HGC_DQE_ECC_ADDR
,
486 .irq_msk
= BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF
),
487 .msk
= HGC_IOST_ECC_MB_ADDR_MSK
,
488 .shift
= HGC_IOST_ECC_MB_ADDR_OFF
,
489 .msg
= "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
490 .reg
= HGC_IOST_ECC_ADDR
,
493 .irq_msk
= BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF
),
494 .msk
= HGC_ITCT_ECC_MB_ADDR_MSK
,
495 .shift
= HGC_ITCT_ECC_MB_ADDR_OFF
,
496 .msg
= "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
497 .reg
= HGC_ITCT_ECC_ADDR
,
500 .irq_msk
= BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF
),
501 .msk
= HGC_LM_DFX_STATUS2_IOSTLIST_MSK
,
502 .shift
= HGC_LM_DFX_STATUS2_IOSTLIST_OFF
,
503 .msg
= "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
504 .reg
= HGC_LM_DFX_STATUS2
,
507 .irq_msk
= BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF
),
508 .msk
= HGC_LM_DFX_STATUS2_ITCTLIST_MSK
,
509 .shift
= HGC_LM_DFX_STATUS2_ITCTLIST_OFF
,
510 .msg
= "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
511 .reg
= HGC_LM_DFX_STATUS2
,
514 .irq_msk
= BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF
),
515 .msk
= HGC_CQE_ECC_MB_ADDR_MSK
,
516 .shift
= HGC_CQE_ECC_MB_ADDR_OFF
,
517 .msg
= "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
518 .reg
= HGC_CQE_ECC_ADDR
,
521 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF
),
522 .msk
= HGC_RXM_DFX_STATUS14_MEM0_MSK
,
523 .shift
= HGC_RXM_DFX_STATUS14_MEM0_OFF
,
524 .msg
= "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
525 .reg
= HGC_RXM_DFX_STATUS14
,
528 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF
),
529 .msk
= HGC_RXM_DFX_STATUS14_MEM1_MSK
,
530 .shift
= HGC_RXM_DFX_STATUS14_MEM1_OFF
,
531 .msg
= "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
532 .reg
= HGC_RXM_DFX_STATUS14
,
535 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF
),
536 .msk
= HGC_RXM_DFX_STATUS14_MEM2_MSK
,
537 .shift
= HGC_RXM_DFX_STATUS14_MEM2_OFF
,
538 .msg
= "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
539 .reg
= HGC_RXM_DFX_STATUS14
,
542 .irq_msk
= BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF
),
543 .msk
= HGC_RXM_DFX_STATUS15_MEM3_MSK
,
544 .shift
= HGC_RXM_DFX_STATUS15_MEM3_OFF
,
545 .msg
= "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
546 .reg
= HGC_RXM_DFX_STATUS15
,
551 HISI_SAS_PHY_PHY_UPDOWN
,
552 HISI_SAS_PHY_CHNL_INT
,
557 TRANS_TX_FAIL_BASE
= 0x0, /* dw0 */
558 TRANS_RX_FAIL_BASE
= 0x20, /* dw1 */
559 DMA_TX_ERR_BASE
= 0x40, /* dw2 bit 15-0 */
560 SIPC_RX_ERR_BASE
= 0x50, /* dw2 bit 31-16*/
561 DMA_RX_ERR_BASE
= 0x60, /* dw3 */
564 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
= TRANS_TX_FAIL_BASE
, /* 0x0 */
565 TRANS_TX_ERR_PHY_NOT_ENABLE
, /* 0x1 */
566 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
, /* 0x2 */
567 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
, /* 0x3 */
568 TRANS_TX_OPEN_CNX_ERR_BY_OTHER
, /* 0x4 */
570 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
, /* 0x6 */
571 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
, /* 0x7 */
572 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
, /* 0x8 */
573 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
, /* 0x9 */
574 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
, /* 0xa */
575 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
, /* 0xb */
576 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
, /* 0xc */
577 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
, /* 0xd */
578 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
, /* 0xe */
579 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
, /* 0xf */
580 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
, /* 0x10 */
581 TRANS_TX_ERR_FRAME_TXED
, /* 0x11 */
582 TRANS_TX_ERR_WITH_BREAK_TIMEOUT
, /* 0x12 */
583 TRANS_TX_ERR_WITH_BREAK_REQUEST
, /* 0x13 */
584 TRANS_TX_ERR_WITH_BREAK_RECEVIED
, /* 0x14 */
585 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
, /* 0x15 */
586 TRANS_TX_ERR_WITH_CLOSE_NORMAL
, /* 0x16 for ssp*/
587 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
, /* 0x17 */
588 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
, /* 0x18 */
589 TRANS_TX_ERR_WITH_CLOSE_COMINIT
, /* 0x19 */
590 TRANS_TX_ERR_WITH_NAK_RECEVIED
, /* 0x1a for ssp*/
591 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
, /* 0x1b for ssp*/
592 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
593 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
, /* 0x1c for ssp */
594 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
595 TRANS_TX_ERR_WITH_IPTT_CONFLICT
, /* 0x1d for ssp/smp */
596 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS
, /* 0x1e */
597 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
598 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
, /* 0x1f for sata/stp */
601 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
= TRANS_RX_FAIL_BASE
, /* 0x20 */
602 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
, /* 0x21 for sata/stp */
603 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
, /* 0x22 for ssp/smp */
604 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
605 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
, /* 0x23 for sata/stp */
606 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
, /* 0x24 for sata/stp */
607 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
, /* 0x25 for smp */
608 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
609 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
, /* 0x26 for sata/stp*/
610 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
, /* 0x27 */
611 TRANS_RX_ERR_WITH_BREAK_TIMEOUT
, /* 0x28 */
612 TRANS_RX_ERR_WITH_BREAK_REQUEST
, /* 0x29 */
613 TRANS_RX_ERR_WITH_BREAK_RECEVIED
, /* 0x2a */
614 RESERVED1
, /* 0x2b */
615 TRANS_RX_ERR_WITH_CLOSE_NORMAL
, /* 0x2c */
616 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
, /* 0x2d */
617 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
, /* 0x2e */
618 TRANS_RX_ERR_WITH_CLOSE_COMINIT
, /* 0x2f */
619 TRANS_RX_ERR_WITH_DATA_LEN0
, /* 0x30 for ssp/smp */
620 TRANS_RX_ERR_WITH_BAD_HASH
, /* 0x31 for ssp */
621 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
622 TRANS_RX_XRDY_WLEN_ZERO_ERR
, /* 0x32 for ssp*/
623 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
624 TRANS_RX_SSP_FRM_LEN_ERR
, /* 0x33 for ssp */
625 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
626 RESERVED2
, /* 0x34 */
627 RESERVED3
, /* 0x35 */
628 RESERVED4
, /* 0x36 */
629 RESERVED5
, /* 0x37 */
630 TRANS_RX_ERR_WITH_BAD_FRM_TYPE
, /* 0x38 */
631 TRANS_RX_SMP_FRM_LEN_ERR
, /* 0x39 */
632 TRANS_RX_SMP_RESP_TIMEOUT_ERR
, /* 0x3a */
633 RESERVED6
, /* 0x3b */
634 RESERVED7
, /* 0x3c */
635 RESERVED8
, /* 0x3d */
636 RESERVED9
, /* 0x3e */
637 TRANS_RX_R_ERR
, /* 0x3f */
640 DMA_TX_DIF_CRC_ERR
= DMA_TX_ERR_BASE
, /* 0x40 */
641 DMA_TX_DIF_APP_ERR
, /* 0x41 */
642 DMA_TX_DIF_RPP_ERR
, /* 0x42 */
643 DMA_TX_DATA_SGL_OVERFLOW
, /* 0x43 */
644 DMA_TX_DIF_SGL_OVERFLOW
, /* 0x44 */
645 DMA_TX_UNEXP_XFER_ERR
, /* 0x45 */
646 DMA_TX_UNEXP_RETRANS_ERR
, /* 0x46 */
647 DMA_TX_XFER_LEN_OVERFLOW
, /* 0x47 */
648 DMA_TX_XFER_OFFSET_ERR
, /* 0x48 */
649 DMA_TX_RAM_ECC_ERR
, /* 0x49 */
650 DMA_TX_DIF_LEN_ALIGN_ERR
, /* 0x4a */
654 SIPC_RX_FIS_STATUS_ERR_BIT_VLD
= SIPC_RX_ERR_BASE
, /* 0x50 */
655 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR
, /* 0x51 */
656 SIPC_RX_FIS_STATUS_BSY_BIT_ERR
, /* 0x52 */
657 SIPC_RX_WRSETUP_LEN_ODD_ERR
, /* 0x53 */
658 SIPC_RX_WRSETUP_LEN_ZERO_ERR
, /* 0x54 */
659 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR
, /* 0x55 */
660 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR
, /* 0x56 */
661 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR
, /* 0x57 */
662 SIPC_RX_SATA_UNEXP_FIS_ERR
, /* 0x58 */
663 SIPC_RX_WRSETUP_ESTATUS_ERR
, /* 0x59 */
664 SIPC_RX_DATA_UNDERFLOW_ERR
, /* 0x5a */
665 SIPC_RX_MAX_ERR_CODE
,
668 DMA_RX_DIF_CRC_ERR
= DMA_RX_ERR_BASE
, /* 0x60 */
669 DMA_RX_DIF_APP_ERR
, /* 0x61 */
670 DMA_RX_DIF_RPP_ERR
, /* 0x62 */
671 DMA_RX_DATA_SGL_OVERFLOW
, /* 0x63 */
672 DMA_RX_DIF_SGL_OVERFLOW
, /* 0x64 */
673 DMA_RX_DATA_LEN_OVERFLOW
, /* 0x65 */
674 DMA_RX_DATA_LEN_UNDERFLOW
, /* 0x66 */
675 DMA_RX_DATA_OFFSET_ERR
, /* 0x67 */
676 RESERVED10
, /* 0x68 */
677 DMA_RX_SATA_FRAME_TYPE_ERR
, /* 0x69 */
678 DMA_RX_RESP_BUF_OVERFLOW
, /* 0x6a */
679 DMA_RX_UNEXP_RETRANS_RESP_ERR
, /* 0x6b */
680 DMA_RX_UNEXP_NORM_RESP_ERR
, /* 0x6c */
681 DMA_RX_UNEXP_RDFRAME_ERR
, /* 0x6d */
682 DMA_RX_PIO_DATA_LEN_ERR
, /* 0x6e */
683 DMA_RX_RDSETUP_STATUS_ERR
, /* 0x6f */
684 DMA_RX_RDSETUP_STATUS_DRQ_ERR
, /* 0x70 */
685 DMA_RX_RDSETUP_STATUS_BSY_ERR
, /* 0x71 */
686 DMA_RX_RDSETUP_LEN_ODD_ERR
, /* 0x72 */
687 DMA_RX_RDSETUP_LEN_ZERO_ERR
, /* 0x73 */
688 DMA_RX_RDSETUP_LEN_OVER_ERR
, /* 0x74 */
689 DMA_RX_RDSETUP_OFFSET_ERR
, /* 0x75 */
690 DMA_RX_RDSETUP_ACTIVE_ERR
, /* 0x76 */
691 DMA_RX_RDSETUP_ESTATUS_ERR
, /* 0x77 */
692 DMA_RX_RAM_ECC_ERR
, /* 0x78 */
693 DMA_RX_UNKNOWN_FRM_ERR
, /* 0x79 */
697 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
698 #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
700 #define DIR_NO_DATA 0
702 #define DIR_TO_DEVICE 2
703 #define DIR_RESERVED 3
705 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
706 err_phase == 0x4 || err_phase == 0x8 ||\
707 err_phase == 0x6 || err_phase == 0xa)
708 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
709 err_phase == 0x20 || err_phase == 0x40)
711 static void link_timeout_disable_link(struct timer_list
*t
);
713 static u32
hisi_sas_read32(struct hisi_hba
*hisi_hba
, u32 off
)
715 void __iomem
*regs
= hisi_hba
->regs
+ off
;
720 static u32
hisi_sas_read32_relaxed(struct hisi_hba
*hisi_hba
, u32 off
)
722 void __iomem
*regs
= hisi_hba
->regs
+ off
;
724 return readl_relaxed(regs
);
727 static void hisi_sas_write32(struct hisi_hba
*hisi_hba
, u32 off
, u32 val
)
729 void __iomem
*regs
= hisi_hba
->regs
+ off
;
734 static void hisi_sas_phy_write32(struct hisi_hba
*hisi_hba
, int phy_no
,
737 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
742 static u32
hisi_sas_phy_read32(struct hisi_hba
*hisi_hba
,
745 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
750 /* This function needs to be protected from pre-emption. */
752 slot_index_alloc_quirk_v2_hw(struct hisi_hba
*hisi_hba
, int *slot_idx
,
753 struct domain_device
*device
)
755 int sata_dev
= dev_is_sata(device
);
756 void *bitmap
= hisi_hba
->slot_index_tags
;
757 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
758 int sata_idx
= sas_dev
->sata_idx
;
763 * STP link SoC bug workaround: index starts from 1.
764 * additionally, we can only allocate odd IPTT(1~4095)
765 * for SAS/SMP device.
768 end
= hisi_hba
->slot_index_count
;
770 if (sata_idx
>= HISI_MAX_SATA_SUPPORT_V2_HW
)
774 * For SATA device: allocate even IPTT in this interval
775 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
776 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
777 * SoC bug workaround. So we ignore the first 32 even IPTTs.
779 start
= 64 * (sata_idx
+ 1);
780 end
= 64 * (sata_idx
+ 2);
784 start
= find_next_zero_bit(bitmap
,
785 hisi_hba
->slot_index_count
, start
);
787 return -SAS_QUEUE_FULL
;
789 * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
791 if (sata_dev
^ (start
& 1))
796 set_bit(start
, bitmap
);
801 static bool sata_index_alloc_v2_hw(struct hisi_hba
*hisi_hba
, int *idx
)
804 struct device
*dev
= hisi_hba
->dev
;
805 void *bitmap
= hisi_hba
->sata_dev_bitmap
;
807 index
= find_first_zero_bit(bitmap
, HISI_MAX_SATA_SUPPORT_V2_HW
);
808 if (index
>= HISI_MAX_SATA_SUPPORT_V2_HW
) {
809 dev_warn(dev
, "alloc sata index failed, index=%d\n", index
);
813 set_bit(index
, bitmap
);
820 hisi_sas_device
*alloc_dev_quirk_v2_hw(struct domain_device
*device
)
822 struct hisi_hba
*hisi_hba
= device
->port
->ha
->lldd_ha
;
823 struct hisi_sas_device
*sas_dev
= NULL
;
824 int i
, sata_dev
= dev_is_sata(device
);
828 spin_lock_irqsave(&hisi_hba
->lock
, flags
);
831 if (!sata_index_alloc_v2_hw(hisi_hba
, &sata_idx
))
834 for (i
= 0; i
< HISI_SAS_MAX_DEVICES
; i
++) {
836 * SATA device id bit0 should be 0
838 if (sata_dev
&& (i
& 1))
840 if (hisi_hba
->devices
[i
].dev_type
== SAS_PHY_UNUSED
) {
841 int queue
= i
% hisi_hba
->queue_count
;
842 struct hisi_sas_dq
*dq
= &hisi_hba
->dq
[queue
];
844 hisi_hba
->devices
[i
].device_id
= i
;
845 sas_dev
= &hisi_hba
->devices
[i
];
846 sas_dev
->dev_status
= HISI_SAS_DEV_NORMAL
;
847 sas_dev
->dev_type
= device
->dev_type
;
848 sas_dev
->hisi_hba
= hisi_hba
;
849 sas_dev
->sas_device
= device
;
850 sas_dev
->sata_idx
= sata_idx
;
852 INIT_LIST_HEAD(&hisi_hba
->devices
[i
].list
);
858 spin_unlock_irqrestore(&hisi_hba
->lock
, flags
);
863 static void config_phy_opt_mode_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
865 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
867 cfg
&= ~PHY_CFG_DC_OPT_MSK
;
868 cfg
|= 1 << PHY_CFG_DC_OPT_OFF
;
869 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
872 static void config_id_frame_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
874 struct sas_identify_frame identify_frame
;
875 u32
*identify_buffer
;
877 memset(&identify_frame
, 0, sizeof(identify_frame
));
878 identify_frame
.dev_type
= SAS_END_DEVICE
;
879 identify_frame
.frame_type
= 0;
880 identify_frame
._un1
= 1;
881 identify_frame
.initiator_bits
= SAS_PROTOCOL_ALL
;
882 identify_frame
.target_bits
= SAS_PROTOCOL_NONE
;
883 memcpy(&identify_frame
._un4_11
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
884 memcpy(&identify_frame
.sas_addr
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
885 identify_frame
.phy_id
= phy_no
;
886 identify_buffer
= (u32
*)(&identify_frame
);
888 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD0
,
889 __swab32(identify_buffer
[0]));
890 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD1
,
891 __swab32(identify_buffer
[1]));
892 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD2
,
893 __swab32(identify_buffer
[2]));
894 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD3
,
895 __swab32(identify_buffer
[3]));
896 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD4
,
897 __swab32(identify_buffer
[4]));
898 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD5
,
899 __swab32(identify_buffer
[5]));
902 static void setup_itct_v2_hw(struct hisi_hba
*hisi_hba
,
903 struct hisi_sas_device
*sas_dev
)
905 struct domain_device
*device
= sas_dev
->sas_device
;
906 struct device
*dev
= hisi_hba
->dev
;
907 u64 qw0
, device_id
= sas_dev
->device_id
;
908 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[device_id
];
909 struct domain_device
*parent_dev
= device
->parent
;
910 struct asd_sas_port
*sas_port
= device
->port
;
911 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
913 memset(itct
, 0, sizeof(*itct
));
917 switch (sas_dev
->dev_type
) {
919 case SAS_EDGE_EXPANDER_DEVICE
:
920 case SAS_FANOUT_EXPANDER_DEVICE
:
921 qw0
= HISI_SAS_DEV_TYPE_SSP
<< ITCT_HDR_DEV_TYPE_OFF
;
924 case SAS_SATA_PENDING
:
925 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
926 qw0
= HISI_SAS_DEV_TYPE_STP
<< ITCT_HDR_DEV_TYPE_OFF
;
928 qw0
= HISI_SAS_DEV_TYPE_SATA
<< ITCT_HDR_DEV_TYPE_OFF
;
931 dev_warn(dev
, "setup itct: unsupported dev type (%d)\n",
935 qw0
|= ((1 << ITCT_HDR_VALID_OFF
) |
936 (device
->linkrate
<< ITCT_HDR_MCR_OFF
) |
937 (1 << ITCT_HDR_VLN_OFF
) |
938 (ITCT_HDR_SMP_TIMEOUT
<< ITCT_HDR_SMP_TIMEOUT_OFF
) |
939 (1 << ITCT_HDR_AWT_CONTINUE_OFF
) |
940 (port
->id
<< ITCT_HDR_PORT_ID_OFF
));
941 itct
->qw0
= cpu_to_le64(qw0
);
944 memcpy(&itct
->sas_addr
, device
->sas_addr
, SAS_ADDR_SIZE
);
945 itct
->sas_addr
= __swab64(itct
->sas_addr
);
948 if (!dev_is_sata(device
))
949 itct
->qw2
= cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF
) |
950 (0x1ULL
<< ITCT_HDR_BITLT_OFF
) |
951 (0x32ULL
<< ITCT_HDR_MCTLT_OFF
) |
952 (0x1ULL
<< ITCT_HDR_RTOLT_OFF
));
955 static void clear_itct_v2_hw(struct hisi_hba
*hisi_hba
,
956 struct hisi_sas_device
*sas_dev
)
958 DECLARE_COMPLETION_ONSTACK(completion
);
959 u64 dev_id
= sas_dev
->device_id
;
960 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[dev_id
];
961 u32 reg_val
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
964 sas_dev
->completion
= &completion
;
966 /* clear the itct interrupt state */
967 if (ENT_INT_SRC3_ITC_INT_MSK
& reg_val
)
968 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
969 ENT_INT_SRC3_ITC_INT_MSK
);
971 for (i
= 0; i
< 2; i
++) {
972 reg_val
= ITCT_CLR_EN_MSK
| (dev_id
& ITCT_DEV_MSK
);
973 hisi_sas_write32(hisi_hba
, ITCT_CLR
, reg_val
);
974 wait_for_completion(sas_dev
->completion
);
976 memset(itct
, 0, sizeof(struct hisi_sas_itct
));
980 static void free_device_v2_hw(struct hisi_sas_device
*sas_dev
)
982 struct hisi_hba
*hisi_hba
= sas_dev
->hisi_hba
;
984 /* SoC bug workaround */
985 if (dev_is_sata(sas_dev
->sas_device
))
986 clear_bit(sas_dev
->sata_idx
, hisi_hba
->sata_dev_bitmap
);
989 static int reset_hw_v2_hw(struct hisi_hba
*hisi_hba
)
993 unsigned long end_time
;
994 struct device
*dev
= hisi_hba
->dev
;
996 /* The mask needs to be set depending on the number of phys */
997 if (hisi_hba
->n_phy
== 9)
998 reset_val
= 0x1fffff;
1000 reset_val
= 0x7ffff;
1002 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0);
1004 /* Disable all of the PHYs */
1005 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1006 u32 phy_cfg
= hisi_sas_phy_read32(hisi_hba
, i
, PHY_CFG
);
1008 phy_cfg
&= ~PHY_CTRL_RESET_MSK
;
1009 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CFG
, phy_cfg
);
1013 /* Ensure DMA tx & rx idle */
1014 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1015 u32 dma_tx_status
, dma_rx_status
;
1017 end_time
= jiffies
+ msecs_to_jiffies(1000);
1020 dma_tx_status
= hisi_sas_phy_read32(hisi_hba
, i
,
1022 dma_rx_status
= hisi_sas_phy_read32(hisi_hba
, i
,
1025 if (!(dma_tx_status
& DMA_TX_STATUS_BUSY_MSK
) &&
1026 !(dma_rx_status
& DMA_RX_STATUS_BUSY_MSK
))
1030 if (time_after(jiffies
, end_time
))
1035 /* Ensure axi bus idle */
1036 end_time
= jiffies
+ msecs_to_jiffies(1000);
1039 hisi_sas_read32(hisi_hba
, AXI_CFG
);
1041 if (axi_status
== 0)
1045 if (time_after(jiffies
, end_time
))
1049 if (ACPI_HANDLE(dev
)) {
1052 s
= acpi_evaluate_object(ACPI_HANDLE(dev
), "_RST", NULL
, NULL
);
1053 if (ACPI_FAILURE(s
)) {
1054 dev_err(dev
, "Reset failed\n");
1057 } else if (hisi_hba
->ctrl
) {
1058 /* reset and disable clock*/
1059 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_reg
,
1061 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_clock_ena_reg
+ 4,
1064 regmap_read(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_sts_reg
, &val
);
1065 if (reset_val
!= (val
& reset_val
)) {
1066 dev_err(dev
, "SAS reset fail.\n");
1070 /* De-reset and enable clock*/
1071 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_reg
+ 4,
1073 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_clock_ena_reg
,
1076 regmap_read(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_sts_reg
,
1078 if (val
& reset_val
) {
1079 dev_err(dev
, "SAS de-reset fail.\n");
1083 dev_warn(dev
, "no reset method\n");
1088 /* This function needs to be called after resetting SAS controller. */
1089 static void phys_reject_stp_links_v2_hw(struct hisi_hba
*hisi_hba
)
1094 hisi_hba
->reject_stp_links_msk
= (1 << hisi_hba
->n_phy
) - 1;
1095 for (phy_no
= 0; phy_no
< hisi_hba
->n_phy
; phy_no
++) {
1096 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, CON_CONTROL
);
1097 if (!(cfg
& CON_CONTROL_CFG_OPEN_ACC_STP_MSK
))
1100 cfg
&= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK
;
1101 hisi_sas_phy_write32(hisi_hba
, phy_no
, CON_CONTROL
, cfg
);
1105 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba
*hisi_hba
)
1110 for (phy_no
= 0; phy_no
< hisi_hba
->n_phy
; phy_no
++) {
1111 if (!(hisi_hba
->reject_stp_links_msk
& BIT(phy_no
)))
1114 dma_tx_dfx1
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1116 if (dma_tx_dfx1
& DMA_TX_DFX1_IPTT_MSK
) {
1117 u32 cfg
= hisi_sas_phy_read32(hisi_hba
,
1118 phy_no
, CON_CONTROL
);
1120 cfg
|= CON_CONTROL_CFG_OPEN_ACC_STP_MSK
;
1121 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1123 clear_bit(phy_no
, &hisi_hba
->reject_stp_links_msk
);
1128 static void init_reg_v2_hw(struct hisi_hba
*hisi_hba
)
1130 struct device
*dev
= hisi_hba
->dev
;
1133 /* Global registers init */
1135 /* Deal with am-max-transmissions quirk */
1136 if (device_property_present(dev
, "hip06-sas-v2-quirk-amt")) {
1137 hisi_sas_write32(hisi_hba
, AM_CFG_MAX_TRANS
, 0x2020);
1138 hisi_sas_write32(hisi_hba
, AM_CFG_SINGLE_PORT_MAX_TRANS
,
1140 } /* Else, use defaults -> do nothing */
1142 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
,
1143 (u32
)((1ULL << hisi_hba
->queue_count
) - 1));
1144 hisi_sas_write32(hisi_hba
, AXI_USER1
, 0xc0000000);
1145 hisi_sas_write32(hisi_hba
, AXI_USER2
, 0x10000);
1146 hisi_sas_write32(hisi_hba
, HGC_SAS_TXFAIL_RETRY_CTRL
, 0x0);
1147 hisi_sas_write32(hisi_hba
, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL
, 0x7FF);
1148 hisi_sas_write32(hisi_hba
, OPENA_WT_CONTI_TIME
, 0x1);
1149 hisi_sas_write32(hisi_hba
, I_T_NEXUS_LOSS_TIME
, 0x1F4);
1150 hisi_sas_write32(hisi_hba
, MAX_CON_TIME_LIMIT_TIME
, 0x32);
1151 hisi_sas_write32(hisi_hba
, BUS_INACTIVE_LIMIT_TIME
, 0x1);
1152 hisi_sas_write32(hisi_hba
, CFG_AGING_TIME
, 0x1);
1153 hisi_sas_write32(hisi_hba
, HGC_ERR_STAT_EN
, 0x1);
1154 hisi_sas_write32(hisi_hba
, HGC_GET_ITV_TIME
, 0x1);
1155 hisi_sas_write32(hisi_hba
, INT_COAL_EN
, 0xc);
1156 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_TIME
, 0x60);
1157 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_CNT
, 0x3);
1158 hisi_sas_write32(hisi_hba
, ENT_INT_COAL_TIME
, 0x1);
1159 hisi_sas_write32(hisi_hba
, ENT_INT_COAL_CNT
, 0x1);
1160 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 0x0);
1161 hisi_sas_write32(hisi_hba
, ENT_INT_SRC1
, 0xffffffff);
1162 hisi_sas_write32(hisi_hba
, ENT_INT_SRC2
, 0xffffffff);
1163 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
, 0xffffffff);
1164 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0x7efefefe);
1165 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0x7efefefe);
1166 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0x7ffe20fe);
1167 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0xfff00c30);
1168 for (i
= 0; i
< hisi_hba
->queue_count
; i
++)
1169 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+0x4*i
, 0);
1171 hisi_sas_write32(hisi_hba
, AXI_AHB_CLK_CFG
, 1);
1172 hisi_sas_write32(hisi_hba
, HYPER_STREAM_ID_EN_CFG
, 1);
1174 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1175 hisi_sas_phy_write32(hisi_hba
, i
, PROG_PHY_LINK_RATE
, 0x855);
1176 hisi_sas_phy_write32(hisi_hba
, i
, SAS_PHY_CTRL
, 0x30b9908);
1177 hisi_sas_phy_write32(hisi_hba
, i
, SL_TOUT_CFG
, 0x7d7d7d7d);
1178 hisi_sas_phy_write32(hisi_hba
, i
, SL_CONTROL
, 0x0);
1179 hisi_sas_phy_write32(hisi_hba
, i
, TXID_AUTO
, 0x2);
1180 hisi_sas_phy_write32(hisi_hba
, i
, DONE_RECEIVED_TIME
, 0x8);
1181 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT0
, 0xffffffff);
1182 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1
, 0xffffffff);
1183 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2
, 0xfff87fff);
1184 hisi_sas_phy_write32(hisi_hba
, i
, RXOP_CHECK_CFG_H
, 0x1000);
1185 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xffffffff);
1186 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0x8ffffbff);
1187 hisi_sas_phy_write32(hisi_hba
, i
, SL_CFG
, 0x13f801fc);
1188 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL_RDY_MSK
, 0x0);
1189 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_NOT_RDY_MSK
, 0x0);
1190 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_DWS_RESET_MSK
, 0x0);
1191 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_PHY_ENA_MSK
, 0x0);
1192 hisi_sas_phy_write32(hisi_hba
, i
, SL_RX_BCAST_CHK_MSK
, 0x0);
1193 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT_COAL_EN
, 0x0);
1194 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_OOB_RESTART_MSK
, 0x0);
1195 if (hisi_hba
->refclk_frequency_mhz
== 66)
1196 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL
, 0x199B694);
1197 /* else, do nothing -> leave it how you found it */
1200 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
1201 /* Delivery queue */
1202 hisi_sas_write32(hisi_hba
,
1203 DLVRY_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
1204 upper_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
1206 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
1207 lower_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
1209 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_DEPTH
+ (i
* 0x14),
1210 HISI_SAS_QUEUE_SLOTS
);
1212 /* Completion queue */
1213 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
1214 upper_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
1216 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
1217 lower_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
1219 hisi_sas_write32(hisi_hba
, COMPL_Q_0_DEPTH
+ (i
* 0x14),
1220 HISI_SAS_QUEUE_SLOTS
);
1224 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_LO
,
1225 lower_32_bits(hisi_hba
->itct_dma
));
1227 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_HI
,
1228 upper_32_bits(hisi_hba
->itct_dma
));
1231 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_LO
,
1232 lower_32_bits(hisi_hba
->iost_dma
));
1234 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_HI
,
1235 upper_32_bits(hisi_hba
->iost_dma
));
1238 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_LO
,
1239 lower_32_bits(hisi_hba
->breakpoint_dma
));
1241 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_HI
,
1242 upper_32_bits(hisi_hba
->breakpoint_dma
));
1244 /* SATA broken msg */
1245 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_LO
,
1246 lower_32_bits(hisi_hba
->sata_breakpoint_dma
));
1248 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_HI
,
1249 upper_32_bits(hisi_hba
->sata_breakpoint_dma
));
1251 /* SATA initial fis */
1252 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_LO
,
1253 lower_32_bits(hisi_hba
->initial_fis_dma
));
1255 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_HI
,
1256 upper_32_bits(hisi_hba
->initial_fis_dma
));
1259 static void link_timeout_enable_link(struct timer_list
*t
)
1261 struct hisi_hba
*hisi_hba
= from_timer(hisi_hba
, t
, timer
);
1264 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1265 if (hisi_hba
->reject_stp_links_msk
& BIT(i
))
1268 reg_val
= hisi_sas_phy_read32(hisi_hba
, i
, CON_CONTROL
);
1269 if (!(reg_val
& BIT(0))) {
1270 hisi_sas_phy_write32(hisi_hba
, i
,
1276 hisi_hba
->timer
.function
= link_timeout_disable_link
;
1277 mod_timer(&hisi_hba
->timer
, jiffies
+ msecs_to_jiffies(900));
1280 static void link_timeout_disable_link(struct timer_list
*t
)
1282 struct hisi_hba
*hisi_hba
= from_timer(hisi_hba
, t
, timer
);
1285 reg_val
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1286 for (i
= 0; i
< hisi_hba
->n_phy
&& reg_val
; i
++) {
1287 if (hisi_hba
->reject_stp_links_msk
& BIT(i
))
1290 if (reg_val
& BIT(i
)) {
1291 hisi_sas_phy_write32(hisi_hba
, i
,
1297 hisi_hba
->timer
.function
= link_timeout_enable_link
;
1298 mod_timer(&hisi_hba
->timer
, jiffies
+ msecs_to_jiffies(100));
1301 static void set_link_timer_quirk(struct hisi_hba
*hisi_hba
)
1303 hisi_hba
->timer
.function
= link_timeout_disable_link
;
1304 hisi_hba
->timer
.expires
= jiffies
+ msecs_to_jiffies(1000);
1305 add_timer(&hisi_hba
->timer
);
1308 static int hw_init_v2_hw(struct hisi_hba
*hisi_hba
)
1310 struct device
*dev
= hisi_hba
->dev
;
1313 rc
= reset_hw_v2_hw(hisi_hba
);
1315 dev_err(dev
, "hisi_sas_reset_hw failed, rc=%d", rc
);
1320 init_reg_v2_hw(hisi_hba
);
1325 static void enable_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1327 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
1329 cfg
|= PHY_CFG_ENA_MSK
;
1330 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
1333 static bool is_sata_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1337 context
= hisi_sas_read32(hisi_hba
, PHY_CONTEXT
);
1338 if (context
& (1 << phy_no
))
1344 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1348 dfx_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, DMA_TX_DFX1
);
1350 if (dfx_val
& BIT(16))
1356 static bool axi_bus_is_idle_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1358 int i
, max_loop
= 1000;
1359 struct device
*dev
= hisi_hba
->dev
;
1360 u32 status
, axi_status
, dfx_val
, dfx_tx_val
;
1362 for (i
= 0; i
< max_loop
; i
++) {
1363 status
= hisi_sas_read32_relaxed(hisi_hba
,
1364 AXI_MASTER_CFG_BASE
+ AM_CURR_TRANS_RETURN
);
1366 axi_status
= hisi_sas_read32(hisi_hba
, AXI_CFG
);
1367 dfx_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, DMA_TX_DFX1
);
1368 dfx_tx_val
= hisi_sas_phy_read32(hisi_hba
,
1369 phy_no
, DMA_TX_FIFO_DFX0
);
1371 if ((status
== 0x3) && (axi_status
== 0x0) &&
1372 (dfx_val
& BIT(20)) && (dfx_tx_val
& BIT(10)))
1376 dev_err(dev
, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1377 phy_no
, status
, axi_status
,
1378 dfx_val
, dfx_tx_val
);
1382 static bool wait_io_done_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1384 int i
, max_loop
= 1000;
1385 struct device
*dev
= hisi_hba
->dev
;
1386 u32 status
, tx_dfx0
;
1388 for (i
= 0; i
< max_loop
; i
++) {
1389 status
= hisi_sas_phy_read32(hisi_hba
, phy_no
, LINK_DFX2
);
1390 status
= (status
& 0x3fc0) >> 6;
1395 tx_dfx0
= hisi_sas_phy_read32(hisi_hba
, phy_no
, DMA_TX_DFX0
);
1396 if ((tx_dfx0
& 0x1ff) == 0x2)
1400 dev_err(dev
, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1401 phy_no
, status
, tx_dfx0
);
1405 static bool allowed_disable_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1407 if (tx_fifo_is_empty_v2_hw(hisi_hba
, phy_no
))
1410 if (!axi_bus_is_idle_v2_hw(hisi_hba
, phy_no
))
1413 if (!wait_io_done_v2_hw(hisi_hba
, phy_no
))
1420 static void disable_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1422 u32 cfg
, axi_val
, dfx0_val
, txid_auto
;
1423 struct device
*dev
= hisi_hba
->dev
;
1425 /* Close axi bus. */
1426 axi_val
= hisi_sas_read32(hisi_hba
, AXI_MASTER_CFG_BASE
+
1429 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
+
1430 AM_CTRL_GLOBAL
, axi_val
);
1432 if (is_sata_phy_v2_hw(hisi_hba
, phy_no
)) {
1433 if (allowed_disable_phy_v2_hw(hisi_hba
, phy_no
))
1436 /* Reset host controller. */
1437 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
1441 dfx0_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PORT_DFX0
);
1442 dfx0_val
= (dfx0_val
& 0x1fc0) >> 6;
1443 if (dfx0_val
!= 0x4)
1446 if (!tx_fifo_is_empty_v2_hw(hisi_hba
, phy_no
)) {
1447 dev_warn(dev
, "phy%d, wait tx fifo need send break\n",
1449 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1451 txid_auto
|= TXID_AUTO_CTB_MSK
;
1452 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
1457 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
1458 cfg
&= ~PHY_CFG_ENA_MSK
;
1459 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
1463 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
+
1464 AM_CTRL_GLOBAL
, axi_val
);
1467 static void start_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1469 config_id_frame_v2_hw(hisi_hba
, phy_no
);
1470 config_phy_opt_mode_v2_hw(hisi_hba
, phy_no
);
1471 enable_phy_v2_hw(hisi_hba
, phy_no
);
1474 static void phy_hard_reset_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1476 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1479 disable_phy_v2_hw(hisi_hba
, phy_no
);
1480 if (phy
->identify
.device_type
== SAS_END_DEVICE
) {
1481 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
1482 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
1483 txid_auto
| TX_HARDRST_MSK
);
1486 start_phy_v2_hw(hisi_hba
, phy_no
);
1489 static void phy_get_events_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1491 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1492 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1493 struct sas_phy
*sphy
= sas_phy
->phy
;
1494 u32 err4_reg_val
, err6_reg_val
;
1496 /* loss dword syn, phy reset problem */
1497 err4_reg_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SAS_ERR_CNT4_REG
);
1499 /* disparity err, invalid dword */
1500 err6_reg_val
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SAS_ERR_CNT6_REG
);
1502 sphy
->loss_of_dword_sync_count
+= (err4_reg_val
>> 16) & 0xFFFF;
1503 sphy
->phy_reset_problem_count
+= err4_reg_val
& 0xFFFF;
1504 sphy
->invalid_dword_count
+= (err6_reg_val
& 0xFF0000) >> 16;
1505 sphy
->running_disparity_error_count
+= err6_reg_val
& 0xFF;
1508 static void phys_init_v2_hw(struct hisi_hba
*hisi_hba
)
1512 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1513 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[i
];
1514 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1516 if (!sas_phy
->phy
->enabled
)
1519 start_phy_v2_hw(hisi_hba
, i
);
1523 static void sl_notify_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1527 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
1528 sl_control
|= SL_CONTROL_NOTIFY_EN_MSK
;
1529 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
1531 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
1532 sl_control
&= ~SL_CONTROL_NOTIFY_EN_MSK
;
1533 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
1536 static enum sas_linkrate
phy_get_max_linkrate_v2_hw(void)
1538 return SAS_LINK_RATE_12_0_GBPS
;
1541 static void phy_set_linkrate_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
,
1542 struct sas_phy_linkrates
*r
)
1544 u32 prog_phy_link_rate
=
1545 hisi_sas_phy_read32(hisi_hba
, phy_no
, PROG_PHY_LINK_RATE
);
1546 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1547 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1549 enum sas_linkrate min
, max
;
1552 if (r
->maximum_linkrate
== SAS_LINK_RATE_UNKNOWN
) {
1553 max
= sas_phy
->phy
->maximum_linkrate
;
1554 min
= r
->minimum_linkrate
;
1555 } else if (r
->minimum_linkrate
== SAS_LINK_RATE_UNKNOWN
) {
1556 max
= r
->maximum_linkrate
;
1557 min
= sas_phy
->phy
->minimum_linkrate
;
1561 sas_phy
->phy
->maximum_linkrate
= max
;
1562 sas_phy
->phy
->minimum_linkrate
= min
;
1564 min
-= SAS_LINK_RATE_1_5_GBPS
;
1565 max
-= SAS_LINK_RATE_1_5_GBPS
;
1567 for (i
= 0; i
<= max
; i
++)
1568 rate_mask
|= 1 << (i
* 2);
1570 prog_phy_link_rate
&= ~0xff;
1571 prog_phy_link_rate
|= rate_mask
;
1573 hisi_sas_phy_write32(hisi_hba
, phy_no
, PROG_PHY_LINK_RATE
,
1574 prog_phy_link_rate
);
1576 phy_hard_reset_v2_hw(hisi_hba
, phy_no
);
1579 static int get_wideport_bitmap_v2_hw(struct hisi_hba
*hisi_hba
, int port_id
)
1582 u32 phy_port_num_ma
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
1583 u32 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1585 for (i
= 0; i
< (hisi_hba
->n_phy
< 9 ? hisi_hba
->n_phy
: 8); i
++)
1586 if (phy_state
& 1 << i
)
1587 if (((phy_port_num_ma
>> (i
* 4)) & 0xf) == port_id
)
1590 if (hisi_hba
->n_phy
== 9) {
1591 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
1593 if (phy_state
& 1 << 8)
1594 if (((port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
1595 PORT_STATE_PHY8_PORT_NUM_OFF
) == port_id
)
1603 * The callpath to this function and upto writing the write
1604 * queue pointer should be safe from interruption.
1607 get_free_slot_v2_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_dq
*dq
)
1609 struct device
*dev
= hisi_hba
->dev
;
1614 r
= hisi_sas_read32_relaxed(hisi_hba
,
1615 DLVRY_Q_0_RD_PTR
+ (queue
* 0x14));
1616 if (r
== (w
+1) % HISI_SAS_QUEUE_SLOTS
) {
1617 dev_warn(dev
, "full queue=%d r=%d w=%d\n\n",
1625 static void start_delivery_v2_hw(struct hisi_sas_dq
*dq
)
1627 struct hisi_hba
*hisi_hba
= dq
->hisi_hba
;
1628 int dlvry_queue
= dq
->slot_prep
->dlvry_queue
;
1629 int dlvry_queue_slot
= dq
->slot_prep
->dlvry_queue_slot
;
1631 dq
->wr_point
= ++dlvry_queue_slot
% HISI_SAS_QUEUE_SLOTS
;
1632 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_WR_PTR
+ (dlvry_queue
* 0x14),
1636 static int prep_prd_sge_v2_hw(struct hisi_hba
*hisi_hba
,
1637 struct hisi_sas_slot
*slot
,
1638 struct hisi_sas_cmd_hdr
*hdr
,
1639 struct scatterlist
*scatter
,
1642 struct hisi_sas_sge_page
*sge_page
= hisi_sas_sge_addr_mem(slot
);
1643 struct device
*dev
= hisi_hba
->dev
;
1644 struct scatterlist
*sg
;
1647 if (n_elem
> HISI_SAS_SGE_PAGE_CNT
) {
1648 dev_err(dev
, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1653 for_each_sg(scatter
, sg
, n_elem
, i
) {
1654 struct hisi_sas_sge
*entry
= &sge_page
->sge
[i
];
1656 entry
->addr
= cpu_to_le64(sg_dma_address(sg
));
1657 entry
->page_ctrl_0
= entry
->page_ctrl_1
= 0;
1658 entry
->data_len
= cpu_to_le32(sg_dma_len(sg
));
1659 entry
->data_off
= 0;
1662 hdr
->prd_table_addr
= cpu_to_le64(hisi_sas_sge_addr_dma(slot
));
1664 hdr
->sg_len
= cpu_to_le32(n_elem
<< CMD_HDR_DATA_SGL_LEN_OFF
);
1669 static int prep_smp_v2_hw(struct hisi_hba
*hisi_hba
,
1670 struct hisi_sas_slot
*slot
)
1672 struct sas_task
*task
= slot
->task
;
1673 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1674 struct domain_device
*device
= task
->dev
;
1675 struct device
*dev
= hisi_hba
->dev
;
1676 struct hisi_sas_port
*port
= slot
->port
;
1677 struct scatterlist
*sg_req
, *sg_resp
;
1678 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
1679 dma_addr_t req_dma_addr
;
1680 unsigned int req_len
, resp_len
;
1684 * DMA-map SMP request, response buffers
1687 sg_req
= &task
->smp_task
.smp_req
;
1688 elem
= dma_map_sg(dev
, sg_req
, 1, DMA_TO_DEVICE
);
1691 req_len
= sg_dma_len(sg_req
);
1692 req_dma_addr
= sg_dma_address(sg_req
);
1695 sg_resp
= &task
->smp_task
.smp_resp
;
1696 elem
= dma_map_sg(dev
, sg_resp
, 1, DMA_FROM_DEVICE
);
1701 resp_len
= sg_dma_len(sg_resp
);
1702 if ((req_len
& 0x3) || (resp_len
& 0x3)) {
1709 hdr
->dw0
= cpu_to_le32((port
->id
<< CMD_HDR_PORT_OFF
) |
1710 (1 << CMD_HDR_PRIORITY_OFF
) | /* high pri */
1711 (2 << CMD_HDR_CMD_OFF
)); /* smp */
1713 /* map itct entry */
1714 hdr
->dw1
= cpu_to_le32((sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
) |
1715 (1 << CMD_HDR_FRAME_TYPE_OFF
) |
1716 (DIR_NO_DATA
<< CMD_HDR_DIR_OFF
));
1719 hdr
->dw2
= cpu_to_le32((((req_len
- 4) / 4) << CMD_HDR_CFL_OFF
) |
1720 (HISI_SAS_MAX_SMP_RESP_SZ
/ 4 <<
1723 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
<< CMD_HDR_IPTT_OFF
);
1725 hdr
->cmd_table_addr
= cpu_to_le64(req_dma_addr
);
1726 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
1731 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_resp
, 1,
1734 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_req
, 1,
1739 static int prep_ssp_v2_hw(struct hisi_hba
*hisi_hba
,
1740 struct hisi_sas_slot
*slot
, int is_tmf
,
1741 struct hisi_sas_tmf_task
*tmf
)
1743 struct sas_task
*task
= slot
->task
;
1744 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1745 struct domain_device
*device
= task
->dev
;
1746 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
1747 struct hisi_sas_port
*port
= slot
->port
;
1748 struct sas_ssp_task
*ssp_task
= &task
->ssp_task
;
1749 struct scsi_cmnd
*scsi_cmnd
= ssp_task
->cmd
;
1750 int has_data
= 0, rc
, priority
= is_tmf
;
1752 u32 dw1
= 0, dw2
= 0;
1754 hdr
->dw0
= cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF
) |
1755 (2 << CMD_HDR_TLR_CTRL_OFF
) |
1756 (port
->id
<< CMD_HDR_PORT_OFF
) |
1757 (priority
<< CMD_HDR_PRIORITY_OFF
) |
1758 (1 << CMD_HDR_CMD_OFF
)); /* ssp */
1760 dw1
= 1 << CMD_HDR_VDTL_OFF
;
1762 dw1
|= 2 << CMD_HDR_FRAME_TYPE_OFF
;
1763 dw1
|= DIR_NO_DATA
<< CMD_HDR_DIR_OFF
;
1765 dw1
|= 1 << CMD_HDR_FRAME_TYPE_OFF
;
1766 switch (scsi_cmnd
->sc_data_direction
) {
1769 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
1771 case DMA_FROM_DEVICE
:
1773 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
1776 dw1
&= ~CMD_HDR_DIR_MSK
;
1780 /* map itct entry */
1781 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
1782 hdr
->dw1
= cpu_to_le32(dw1
);
1784 dw2
= (((sizeof(struct ssp_command_iu
) + sizeof(struct ssp_frame_hdr
)
1785 + 3) / 4) << CMD_HDR_CFL_OFF
) |
1786 ((HISI_SAS_MAX_SSP_RESP_SZ
/ 4) << CMD_HDR_MRFL_OFF
) |
1787 (2 << CMD_HDR_SG_MOD_OFF
);
1788 hdr
->dw2
= cpu_to_le32(dw2
);
1790 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
1793 rc
= prep_prd_sge_v2_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
1799 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
1800 hdr
->cmd_table_addr
= cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot
));
1801 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
1803 buf_cmd
= hisi_sas_cmd_hdr_addr_mem(slot
) +
1804 sizeof(struct ssp_frame_hdr
);
1806 memcpy(buf_cmd
, &task
->ssp_task
.LUN
, 8);
1808 buf_cmd
[9] = task
->ssp_task
.task_attr
|
1809 (task
->ssp_task
.task_prio
<< 3);
1810 memcpy(buf_cmd
+ 12, task
->ssp_task
.cmd
->cmnd
,
1811 task
->ssp_task
.cmd
->cmd_len
);
1813 buf_cmd
[10] = tmf
->tmf
;
1815 case TMF_ABORT_TASK
:
1816 case TMF_QUERY_TASK
:
1818 (tmf
->tag_of_task_to_be_managed
>> 8) & 0xff;
1820 tmf
->tag_of_task_to_be_managed
& 0xff;
1830 #define TRANS_TX_ERR 0
1831 #define TRANS_RX_ERR 1
1832 #define DMA_TX_ERR 2
1833 #define SIPC_RX_ERR 3
1834 #define DMA_RX_ERR 4
1836 #define DMA_TX_ERR_OFF 0
1837 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1838 #define SIPC_RX_ERR_OFF 16
1839 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1841 static int parse_trans_tx_err_code_v2_hw(u32 err_msk
)
1843 static const u8 trans_tx_err_code_prio
[] = {
1844 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
,
1845 TRANS_TX_ERR_PHY_NOT_ENABLE
,
1846 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
,
1847 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
,
1848 TRANS_TX_OPEN_CNX_ERR_BY_OTHER
,
1850 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
,
1851 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
,
1852 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
,
1853 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
,
1854 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
,
1855 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
,
1856 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
,
1857 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
,
1858 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
,
1859 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
,
1860 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
,
1861 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
,
1862 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
,
1863 TRANS_TX_ERR_WITH_CLOSE_COMINIT
,
1864 TRANS_TX_ERR_WITH_BREAK_TIMEOUT
,
1865 TRANS_TX_ERR_WITH_BREAK_REQUEST
,
1866 TRANS_TX_ERR_WITH_BREAK_RECEVIED
,
1867 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
,
1868 TRANS_TX_ERR_WITH_CLOSE_NORMAL
,
1869 TRANS_TX_ERR_WITH_NAK_RECEVIED
,
1870 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
,
1871 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
,
1872 TRANS_TX_ERR_WITH_IPTT_CONFLICT
,
1873 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS
,
1874 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
,
1878 for (i
= 0; i
< ARRAY_SIZE(trans_tx_err_code_prio
); i
++) {
1879 index
= trans_tx_err_code_prio
[i
] - TRANS_TX_FAIL_BASE
;
1880 if (err_msk
& (1 << index
))
1881 return trans_tx_err_code_prio
[i
];
1886 static int parse_trans_rx_err_code_v2_hw(u32 err_msk
)
1888 static const u8 trans_rx_err_code_prio
[] = {
1889 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
,
1890 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
,
1891 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
,
1892 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
,
1893 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
,
1894 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
,
1895 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
,
1896 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
,
1897 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
,
1898 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
,
1899 TRANS_RX_ERR_WITH_CLOSE_COMINIT
,
1900 TRANS_RX_ERR_WITH_BREAK_TIMEOUT
,
1901 TRANS_RX_ERR_WITH_BREAK_REQUEST
,
1902 TRANS_RX_ERR_WITH_BREAK_RECEVIED
,
1904 TRANS_RX_ERR_WITH_CLOSE_NORMAL
,
1905 TRANS_RX_ERR_WITH_DATA_LEN0
,
1906 TRANS_RX_ERR_WITH_BAD_HASH
,
1907 TRANS_RX_XRDY_WLEN_ZERO_ERR
,
1908 TRANS_RX_SSP_FRM_LEN_ERR
,
1913 TRANS_RX_ERR_WITH_BAD_FRM_TYPE
,
1914 TRANS_RX_SMP_FRM_LEN_ERR
,
1915 TRANS_RX_SMP_RESP_TIMEOUT_ERR
,
1924 for (i
= 0; i
< ARRAY_SIZE(trans_rx_err_code_prio
); i
++) {
1925 index
= trans_rx_err_code_prio
[i
] - TRANS_RX_FAIL_BASE
;
1926 if (err_msk
& (1 << index
))
1927 return trans_rx_err_code_prio
[i
];
1932 static int parse_dma_tx_err_code_v2_hw(u32 err_msk
)
1934 static const u8 dma_tx_err_code_prio
[] = {
1935 DMA_TX_UNEXP_XFER_ERR
,
1936 DMA_TX_UNEXP_RETRANS_ERR
,
1937 DMA_TX_XFER_LEN_OVERFLOW
,
1938 DMA_TX_XFER_OFFSET_ERR
,
1940 DMA_TX_DIF_LEN_ALIGN_ERR
,
1944 DMA_TX_DATA_SGL_OVERFLOW
,
1945 DMA_TX_DIF_SGL_OVERFLOW
,
1949 for (i
= 0; i
< ARRAY_SIZE(dma_tx_err_code_prio
); i
++) {
1950 index
= dma_tx_err_code_prio
[i
] - DMA_TX_ERR_BASE
;
1951 err_msk
= err_msk
& DMA_TX_ERR_MSK
;
1952 if (err_msk
& (1 << index
))
1953 return dma_tx_err_code_prio
[i
];
1958 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk
)
1960 static const u8 sipc_rx_err_code_prio
[] = {
1961 SIPC_RX_FIS_STATUS_ERR_BIT_VLD
,
1962 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR
,
1963 SIPC_RX_FIS_STATUS_BSY_BIT_ERR
,
1964 SIPC_RX_WRSETUP_LEN_ODD_ERR
,
1965 SIPC_RX_WRSETUP_LEN_ZERO_ERR
,
1966 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR
,
1967 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR
,
1968 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR
,
1969 SIPC_RX_SATA_UNEXP_FIS_ERR
,
1970 SIPC_RX_WRSETUP_ESTATUS_ERR
,
1971 SIPC_RX_DATA_UNDERFLOW_ERR
,
1975 for (i
= 0; i
< ARRAY_SIZE(sipc_rx_err_code_prio
); i
++) {
1976 index
= sipc_rx_err_code_prio
[i
] - SIPC_RX_ERR_BASE
;
1977 err_msk
= err_msk
& SIPC_RX_ERR_MSK
;
1978 if (err_msk
& (1 << (index
+ 0x10)))
1979 return sipc_rx_err_code_prio
[i
];
1984 static int parse_dma_rx_err_code_v2_hw(u32 err_msk
)
1986 static const u8 dma_rx_err_code_prio
[] = {
1987 DMA_RX_UNKNOWN_FRM_ERR
,
1988 DMA_RX_DATA_LEN_OVERFLOW
,
1989 DMA_RX_DATA_LEN_UNDERFLOW
,
1990 DMA_RX_DATA_OFFSET_ERR
,
1992 DMA_RX_SATA_FRAME_TYPE_ERR
,
1993 DMA_RX_RESP_BUF_OVERFLOW
,
1994 DMA_RX_UNEXP_RETRANS_RESP_ERR
,
1995 DMA_RX_UNEXP_NORM_RESP_ERR
,
1996 DMA_RX_UNEXP_RDFRAME_ERR
,
1997 DMA_RX_PIO_DATA_LEN_ERR
,
1998 DMA_RX_RDSETUP_STATUS_ERR
,
1999 DMA_RX_RDSETUP_STATUS_DRQ_ERR
,
2000 DMA_RX_RDSETUP_STATUS_BSY_ERR
,
2001 DMA_RX_RDSETUP_LEN_ODD_ERR
,
2002 DMA_RX_RDSETUP_LEN_ZERO_ERR
,
2003 DMA_RX_RDSETUP_LEN_OVER_ERR
,
2004 DMA_RX_RDSETUP_OFFSET_ERR
,
2005 DMA_RX_RDSETUP_ACTIVE_ERR
,
2006 DMA_RX_RDSETUP_ESTATUS_ERR
,
2011 DMA_RX_DATA_SGL_OVERFLOW
,
2012 DMA_RX_DIF_SGL_OVERFLOW
,
2016 for (i
= 0; i
< ARRAY_SIZE(dma_rx_err_code_prio
); i
++) {
2017 index
= dma_rx_err_code_prio
[i
] - DMA_RX_ERR_BASE
;
2018 if (err_msk
& (1 << index
))
2019 return dma_rx_err_code_prio
[i
];
2024 /* by default, task resp is complete */
2025 static void slot_err_v2_hw(struct hisi_hba
*hisi_hba
,
2026 struct sas_task
*task
,
2027 struct hisi_sas_slot
*slot
,
2030 struct task_status_struct
*ts
= &task
->task_status
;
2031 struct hisi_sas_err_record_v2
*err_record
=
2032 hisi_sas_status_buf_addr_mem(slot
);
2033 u32 trans_tx_fail_type
= cpu_to_le32(err_record
->trans_tx_fail_type
);
2034 u32 trans_rx_fail_type
= cpu_to_le32(err_record
->trans_rx_fail_type
);
2035 u16 dma_tx_err_type
= cpu_to_le16(err_record
->dma_tx_err_type
);
2036 u16 sipc_rx_err_type
= cpu_to_le16(err_record
->sipc_rx_err_type
);
2037 u32 dma_rx_err_type
= cpu_to_le32(err_record
->dma_rx_err_type
);
2040 if (err_phase
== 1) {
2041 /* error in TX phase, the priority of error is: DW2 > DW0 */
2042 error
= parse_dma_tx_err_code_v2_hw(dma_tx_err_type
);
2044 error
= parse_trans_tx_err_code_v2_hw(
2045 trans_tx_fail_type
);
2046 } else if (err_phase
== 2) {
2047 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2048 error
= parse_trans_rx_err_code_v2_hw(
2049 trans_rx_fail_type
);
2051 error
= parse_dma_rx_err_code_v2_hw(
2054 error
= parse_sipc_rx_err_code_v2_hw(
2059 switch (task
->task_proto
) {
2060 case SAS_PROTOCOL_SSP
:
2063 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
:
2065 ts
->stat
= SAS_OPEN_REJECT
;
2066 ts
->open_rej_reason
= SAS_OREJ_NO_DEST
;
2069 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
:
2071 ts
->stat
= SAS_OPEN_REJECT
;
2072 ts
->open_rej_reason
= SAS_OREJ_EPROTO
;
2075 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
:
2077 ts
->stat
= SAS_OPEN_REJECT
;
2078 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
2081 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
:
2083 ts
->stat
= SAS_OPEN_REJECT
;
2084 ts
->open_rej_reason
= SAS_OREJ_BAD_DEST
;
2087 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
:
2089 ts
->stat
= SAS_OPEN_REJECT
;
2090 ts
->open_rej_reason
= SAS_OREJ_WRONG_DEST
;
2093 case DMA_RX_UNEXP_NORM_RESP_ERR
:
2094 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
:
2095 case DMA_RX_RESP_BUF_OVERFLOW
:
2097 ts
->stat
= SAS_OPEN_REJECT
;
2098 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
2101 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
:
2104 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2107 case DMA_RX_DATA_LEN_OVERFLOW
:
2109 ts
->stat
= SAS_DATA_OVERRUN
;
2113 case DMA_RX_DATA_LEN_UNDERFLOW
:
2115 ts
->residual
= trans_tx_fail_type
;
2116 ts
->stat
= SAS_DATA_UNDERRUN
;
2119 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
:
2120 case TRANS_TX_ERR_PHY_NOT_ENABLE
:
2121 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER
:
2122 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
:
2123 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
:
2124 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
:
2125 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
:
2126 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
:
2127 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT
:
2128 case TRANS_TX_ERR_WITH_BREAK_REQUEST
:
2129 case TRANS_TX_ERR_WITH_BREAK_RECEVIED
:
2130 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
:
2131 case TRANS_TX_ERR_WITH_CLOSE_NORMAL
:
2132 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
:
2133 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
2134 case TRANS_TX_ERR_WITH_CLOSE_COMINIT
:
2135 case TRANS_TX_ERR_WITH_NAK_RECEVIED
:
2136 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
:
2137 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
:
2138 case TRANS_TX_ERR_WITH_IPTT_CONFLICT
:
2139 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
:
2140 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
:
2141 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
:
2142 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
:
2143 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT
:
2144 case TRANS_RX_ERR_WITH_BREAK_REQUEST
:
2145 case TRANS_RX_ERR_WITH_BREAK_RECEVIED
:
2146 case TRANS_RX_ERR_WITH_CLOSE_NORMAL
:
2147 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
2148 case TRANS_RX_ERR_WITH_CLOSE_COMINIT
:
2149 case TRANS_TX_ERR_FRAME_TXED
:
2150 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
:
2151 case TRANS_RX_ERR_WITH_DATA_LEN0
:
2152 case TRANS_RX_ERR_WITH_BAD_HASH
:
2153 case TRANS_RX_XRDY_WLEN_ZERO_ERR
:
2154 case TRANS_RX_SSP_FRM_LEN_ERR
:
2155 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE
:
2156 case DMA_TX_DATA_SGL_OVERFLOW
:
2157 case DMA_TX_UNEXP_XFER_ERR
:
2158 case DMA_TX_UNEXP_RETRANS_ERR
:
2159 case DMA_TX_XFER_LEN_OVERFLOW
:
2160 case DMA_TX_XFER_OFFSET_ERR
:
2161 case SIPC_RX_DATA_UNDERFLOW_ERR
:
2162 case DMA_RX_DATA_SGL_OVERFLOW
:
2163 case DMA_RX_DATA_OFFSET_ERR
:
2164 case DMA_RX_RDSETUP_LEN_ODD_ERR
:
2165 case DMA_RX_RDSETUP_LEN_ZERO_ERR
:
2166 case DMA_RX_RDSETUP_LEN_OVER_ERR
:
2167 case DMA_RX_SATA_FRAME_TYPE_ERR
:
2168 case DMA_RX_UNKNOWN_FRM_ERR
:
2170 /* This will request a retry */
2171 ts
->stat
= SAS_QUEUE_FULL
;
2180 case SAS_PROTOCOL_SMP
:
2181 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
2184 case SAS_PROTOCOL_SATA
:
2185 case SAS_PROTOCOL_STP
:
2186 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
2189 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
:
2191 ts
->stat
= SAS_OPEN_REJECT
;
2192 ts
->open_rej_reason
= SAS_OREJ_NO_DEST
;
2195 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
:
2197 ts
->resp
= SAS_TASK_UNDELIVERED
;
2198 ts
->stat
= SAS_DEV_NO_RESPONSE
;
2201 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
:
2203 ts
->stat
= SAS_OPEN_REJECT
;
2204 ts
->open_rej_reason
= SAS_OREJ_EPROTO
;
2207 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
:
2209 ts
->stat
= SAS_OPEN_REJECT
;
2210 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
2213 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
:
2215 ts
->stat
= SAS_OPEN_REJECT
;
2216 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
2219 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
:
2221 ts
->stat
= SAS_OPEN_REJECT
;
2222 ts
->open_rej_reason
= SAS_OREJ_WRONG_DEST
;
2225 case DMA_RX_RESP_BUF_OVERFLOW
:
2226 case DMA_RX_UNEXP_NORM_RESP_ERR
:
2227 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
:
2229 ts
->stat
= SAS_OPEN_REJECT
;
2230 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
2233 case DMA_RX_DATA_LEN_OVERFLOW
:
2235 ts
->stat
= SAS_DATA_OVERRUN
;
2239 case DMA_RX_DATA_LEN_UNDERFLOW
:
2241 ts
->residual
= trans_tx_fail_type
;
2242 ts
->stat
= SAS_DATA_UNDERRUN
;
2245 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
:
2246 case TRANS_TX_ERR_PHY_NOT_ENABLE
:
2247 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER
:
2248 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
:
2249 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
:
2250 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
:
2251 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
:
2252 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
:
2253 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT
:
2254 case TRANS_TX_ERR_WITH_BREAK_REQUEST
:
2255 case TRANS_TX_ERR_WITH_BREAK_RECEVIED
:
2256 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
:
2257 case TRANS_TX_ERR_WITH_CLOSE_NORMAL
:
2258 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
:
2259 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
2260 case TRANS_TX_ERR_WITH_CLOSE_COMINIT
:
2261 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
:
2262 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
:
2263 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS
:
2264 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
:
2265 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
:
2266 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
:
2267 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
:
2268 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
:
2269 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
:
2270 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
:
2271 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
:
2272 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT
:
2273 case TRANS_RX_ERR_WITH_BREAK_REQUEST
:
2274 case TRANS_RX_ERR_WITH_BREAK_RECEVIED
:
2275 case TRANS_RX_ERR_WITH_CLOSE_NORMAL
:
2276 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
:
2277 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
2278 case TRANS_RX_ERR_WITH_CLOSE_COMINIT
:
2279 case TRANS_RX_ERR_WITH_DATA_LEN0
:
2280 case TRANS_RX_ERR_WITH_BAD_HASH
:
2281 case TRANS_RX_XRDY_WLEN_ZERO_ERR
:
2282 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE
:
2283 case DMA_TX_DATA_SGL_OVERFLOW
:
2284 case DMA_TX_UNEXP_XFER_ERR
:
2285 case DMA_TX_UNEXP_RETRANS_ERR
:
2286 case DMA_TX_XFER_LEN_OVERFLOW
:
2287 case DMA_TX_XFER_OFFSET_ERR
:
2288 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD
:
2289 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR
:
2290 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR
:
2291 case SIPC_RX_WRSETUP_LEN_ODD_ERR
:
2292 case SIPC_RX_WRSETUP_LEN_ZERO_ERR
:
2293 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR
:
2294 case SIPC_RX_SATA_UNEXP_FIS_ERR
:
2295 case DMA_RX_DATA_SGL_OVERFLOW
:
2296 case DMA_RX_DATA_OFFSET_ERR
:
2297 case DMA_RX_SATA_FRAME_TYPE_ERR
:
2298 case DMA_RX_UNEXP_RDFRAME_ERR
:
2299 case DMA_RX_PIO_DATA_LEN_ERR
:
2300 case DMA_RX_RDSETUP_STATUS_ERR
:
2301 case DMA_RX_RDSETUP_STATUS_DRQ_ERR
:
2302 case DMA_RX_RDSETUP_STATUS_BSY_ERR
:
2303 case DMA_RX_RDSETUP_LEN_ODD_ERR
:
2304 case DMA_RX_RDSETUP_LEN_ZERO_ERR
:
2305 case DMA_RX_RDSETUP_LEN_OVER_ERR
:
2306 case DMA_RX_RDSETUP_OFFSET_ERR
:
2307 case DMA_RX_RDSETUP_ACTIVE_ERR
:
2308 case DMA_RX_RDSETUP_ESTATUS_ERR
:
2309 case DMA_RX_UNKNOWN_FRM_ERR
:
2310 case TRANS_RX_SSP_FRM_LEN_ERR
:
2311 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
:
2314 ts
->stat
= SAS_PHY_DOWN
;
2319 ts
->stat
= SAS_PROTO_RESPONSE
;
2323 hisi_sas_sata_done(task
, slot
);
2332 slot_complete_v2_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_slot
*slot
)
2334 struct sas_task
*task
= slot
->task
;
2335 struct hisi_sas_device
*sas_dev
;
2336 struct device
*dev
= hisi_hba
->dev
;
2337 struct task_status_struct
*ts
;
2338 struct domain_device
*device
;
2339 enum exec_status sts
;
2340 struct hisi_sas_complete_v2_hdr
*complete_queue
=
2341 hisi_hba
->complete_hdr
[slot
->cmplt_queue
];
2342 struct hisi_sas_complete_v2_hdr
*complete_hdr
=
2343 &complete_queue
[slot
->cmplt_queue_slot
];
2344 unsigned long flags
;
2347 if (unlikely(!task
|| !task
->lldd_task
|| !task
->dev
))
2350 ts
= &task
->task_status
;
2352 sas_dev
= device
->lldd_dev
;
2354 spin_lock_irqsave(&task
->task_state_lock
, flags
);
2355 aborted
= task
->task_state_flags
& SAS_TASK_STATE_ABORTED
;
2356 task
->task_state_flags
&=
2357 ~(SAS_TASK_STATE_PENDING
| SAS_TASK_AT_INITIATOR
);
2358 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
2360 memset(ts
, 0, sizeof(*ts
));
2361 ts
->resp
= SAS_TASK_COMPLETE
;
2363 if (unlikely(aborted
)) {
2364 dev_dbg(dev
, "slot_complete: task(%p) aborted\n", task
);
2365 ts
->stat
= SAS_ABORTED_TASK
;
2366 spin_lock_irqsave(&hisi_hba
->lock
, flags
);
2367 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
2368 spin_unlock_irqrestore(&hisi_hba
->lock
, flags
);
2372 if (unlikely(!sas_dev
)) {
2373 dev_dbg(dev
, "slot complete: port has no device\n");
2374 ts
->stat
= SAS_PHY_DOWN
;
2378 /* Use SAS+TMF status codes */
2379 switch ((complete_hdr
->dw0
& CMPLT_HDR_ABORT_STAT_MSK
)
2380 >> CMPLT_HDR_ABORT_STAT_OFF
) {
2381 case STAT_IO_ABORTED
:
2382 /* this io has been aborted by abort command */
2383 ts
->stat
= SAS_ABORTED_TASK
;
2385 case STAT_IO_COMPLETE
:
2386 /* internal abort command complete */
2387 ts
->stat
= TMF_RESP_FUNC_SUCC
;
2388 del_timer(&slot
->internal_abort_timer
);
2390 case STAT_IO_NO_DEVICE
:
2391 ts
->stat
= TMF_RESP_FUNC_COMPLETE
;
2392 del_timer(&slot
->internal_abort_timer
);
2394 case STAT_IO_NOT_VALID
:
2395 /* abort single io, controller don't find
2396 * the io need to abort
2398 ts
->stat
= TMF_RESP_FUNC_FAILED
;
2399 del_timer(&slot
->internal_abort_timer
);
2405 if ((complete_hdr
->dw0
& CMPLT_HDR_ERX_MSK
) &&
2406 (!(complete_hdr
->dw0
& CMPLT_HDR_RSPNS_XFRD_MSK
))) {
2407 u32 err_phase
= (complete_hdr
->dw0
& CMPLT_HDR_ERR_PHASE_MSK
)
2408 >> CMPLT_HDR_ERR_PHASE_OFF
;
2409 u32
*error_info
= hisi_sas_status_buf_addr_mem(slot
);
2411 /* Analyse error happens on which phase TX or RX */
2412 if (ERR_ON_TX_PHASE(err_phase
))
2413 slot_err_v2_hw(hisi_hba
, task
, slot
, 1);
2414 else if (ERR_ON_RX_PHASE(err_phase
))
2415 slot_err_v2_hw(hisi_hba
, task
, slot
, 2);
2417 if (ts
->stat
!= SAS_DATA_UNDERRUN
)
2418 dev_info(dev
, "erroneous completion iptt=%d task=%p "
2419 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
2420 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
2422 complete_hdr
->dw0
, complete_hdr
->dw1
,
2423 complete_hdr
->act
, complete_hdr
->dw3
,
2424 error_info
[0], error_info
[1],
2425 error_info
[2], error_info
[3]);
2427 if (unlikely(slot
->abort
))
2432 switch (task
->task_proto
) {
2433 case SAS_PROTOCOL_SSP
:
2435 struct hisi_sas_status_buffer
*status_buffer
=
2436 hisi_sas_status_buf_addr_mem(slot
);
2437 struct ssp_response_iu
*iu
= (struct ssp_response_iu
*)
2438 &status_buffer
->iu
[0];
2440 sas_ssp_task_response(dev
, task
, iu
);
2443 case SAS_PROTOCOL_SMP
:
2445 struct scatterlist
*sg_resp
= &task
->smp_task
.smp_resp
;
2448 ts
->stat
= SAM_STAT_GOOD
;
2449 to
= kmap_atomic(sg_page(sg_resp
));
2451 dma_unmap_sg(dev
, &task
->smp_task
.smp_resp
, 1,
2453 dma_unmap_sg(dev
, &task
->smp_task
.smp_req
, 1,
2455 memcpy(to
+ sg_resp
->offset
,
2456 hisi_sas_status_buf_addr_mem(slot
) +
2457 sizeof(struct hisi_sas_err_record
),
2458 sg_dma_len(sg_resp
));
2462 case SAS_PROTOCOL_SATA
:
2463 case SAS_PROTOCOL_STP
:
2464 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
2466 ts
->stat
= SAM_STAT_GOOD
;
2467 hisi_sas_sata_done(task
, slot
);
2471 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
2475 if (!slot
->port
->port_attached
) {
2476 dev_warn(dev
, "slot complete: port %d has removed\n",
2477 slot
->port
->sas_port
.id
);
2478 ts
->stat
= SAS_PHY_DOWN
;
2482 spin_lock_irqsave(&task
->task_state_lock
, flags
);
2483 task
->task_state_flags
|= SAS_TASK_STATE_DONE
;
2484 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
2485 spin_lock_irqsave(&hisi_hba
->lock
, flags
);
2486 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
2487 spin_unlock_irqrestore(&hisi_hba
->lock
, flags
);
2490 if (task
->task_done
)
2491 task
->task_done(task
);
2496 static int prep_ata_v2_hw(struct hisi_hba
*hisi_hba
,
2497 struct hisi_sas_slot
*slot
)
2499 struct sas_task
*task
= slot
->task
;
2500 struct domain_device
*device
= task
->dev
;
2501 struct domain_device
*parent_dev
= device
->parent
;
2502 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
2503 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
2504 struct asd_sas_port
*sas_port
= device
->port
;
2505 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
2507 int has_data
= 0, rc
= 0, hdr_tag
= 0;
2508 u32 dw1
= 0, dw2
= 0;
2512 hdr
->dw0
= cpu_to_le32(port
->id
<< CMD_HDR_PORT_OFF
);
2513 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
2514 hdr
->dw0
|= cpu_to_le32(3 << CMD_HDR_CMD_OFF
);
2516 hdr
->dw0
|= cpu_to_le32(4 << CMD_HDR_CMD_OFF
);
2519 switch (task
->data_dir
) {
2522 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
2524 case DMA_FROM_DEVICE
:
2526 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
2529 dw1
&= ~CMD_HDR_DIR_MSK
;
2532 if ((task
->ata_task
.fis
.command
== ATA_CMD_DEV_RESET
) &&
2533 (task
->ata_task
.fis
.control
& ATA_SRST
))
2534 dw1
|= 1 << CMD_HDR_RESET_OFF
;
2536 dw1
|= (hisi_sas_get_ata_protocol(
2537 task
->ata_task
.fis
.command
, task
->data_dir
))
2538 << CMD_HDR_FRAME_TYPE_OFF
;
2539 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
2540 hdr
->dw1
= cpu_to_le32(dw1
);
2543 if (task
->ata_task
.use_ncq
&& hisi_sas_get_ncq_tag(task
, &hdr_tag
)) {
2544 task
->ata_task
.fis
.sector_count
|= (u8
) (hdr_tag
<< 3);
2545 dw2
|= hdr_tag
<< CMD_HDR_NCQ_TAG_OFF
;
2548 dw2
|= (HISI_SAS_MAX_STP_RESP_SZ
/ 4) << CMD_HDR_CFL_OFF
|
2549 2 << CMD_HDR_SG_MOD_OFF
;
2550 hdr
->dw2
= cpu_to_le32(dw2
);
2553 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
2556 rc
= prep_prd_sge_v2_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
2562 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
2563 hdr
->cmd_table_addr
= cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot
));
2564 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
2566 buf_cmd
= hisi_sas_cmd_hdr_addr_mem(slot
);
2568 if (likely(!task
->ata_task
.device_control_reg_update
))
2569 task
->ata_task
.fis
.flags
|= 0x80; /* C=1: update ATA cmd reg */
2570 /* fill in command FIS */
2571 memcpy(buf_cmd
, &task
->ata_task
.fis
, sizeof(struct host_to_dev_fis
));
2576 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list
*t
)
2578 struct hisi_sas_slot
*slot
= from_timer(slot
, t
, internal_abort_timer
);
2579 struct hisi_sas_port
*port
= slot
->port
;
2580 struct asd_sas_port
*asd_sas_port
;
2581 struct asd_sas_phy
*sas_phy
;
2586 asd_sas_port
= &port
->sas_port
;
2588 /* Kick the hardware - send break command */
2589 list_for_each_entry(sas_phy
, &asd_sas_port
->phy_list
, port_phy_el
) {
2590 struct hisi_sas_phy
*phy
= sas_phy
->lldd_phy
;
2591 struct hisi_hba
*hisi_hba
= phy
->hisi_hba
;
2592 int phy_no
= sas_phy
->id
;
2595 link_dfx2
= hisi_sas_phy_read32(hisi_hba
, phy_no
, LINK_DFX2
);
2596 if ((link_dfx2
== LINK_DFX2_RCVR_HOLD_STS_MSK
) ||
2597 (link_dfx2
& LINK_DFX2_SEND_HOLD_STS_MSK
)) {
2600 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2602 txid_auto
|= TXID_AUTO_CTB_MSK
;
2603 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
2610 static int prep_abort_v2_hw(struct hisi_hba
*hisi_hba
,
2611 struct hisi_sas_slot
*slot
,
2612 int device_id
, int abort_flag
, int tag_to_abort
)
2614 struct sas_task
*task
= slot
->task
;
2615 struct domain_device
*dev
= task
->dev
;
2616 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
2617 struct hisi_sas_port
*port
= slot
->port
;
2618 struct timer_list
*timer
= &slot
->internal_abort_timer
;
2620 /* setup the quirk timer */
2621 timer_setup(timer
, hisi_sas_internal_abort_quirk_timeout
, 0);
2622 /* Set the timeout to 10ms less than internal abort timeout */
2623 mod_timer(timer
, jiffies
+ msecs_to_jiffies(100));
2626 hdr
->dw0
= cpu_to_le32((5 << CMD_HDR_CMD_OFF
) | /*abort*/
2627 (port
->id
<< CMD_HDR_PORT_OFF
) |
2628 ((dev_is_sata(dev
) ? 1:0) <<
2629 CMD_HDR_ABORT_DEVICE_TYPE_OFF
) |
2630 (abort_flag
<< CMD_HDR_ABORT_FLAG_OFF
));
2633 hdr
->dw1
= cpu_to_le32(device_id
<< CMD_HDR_DEV_ID_OFF
);
2636 hdr
->dw7
= cpu_to_le32(tag_to_abort
<< CMD_HDR_ABORT_IPTT_OFF
);
2637 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
2642 static int phy_up_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2644 int i
, res
= IRQ_HANDLED
;
2645 u32 port_id
, link_rate
, hard_phy_linkrate
;
2646 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2647 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
2648 struct device
*dev
= hisi_hba
->dev
;
2649 u32
*frame_rcvd
= (u32
*)sas_phy
->frame_rcvd
;
2650 struct sas_identify_frame
*id
= (struct sas_identify_frame
*)frame_rcvd
;
2652 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 1);
2654 if (is_sata_phy_v2_hw(hisi_hba
, phy_no
))
2658 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
2660 port_id
= (port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
2661 PORT_STATE_PHY8_PORT_NUM_OFF
;
2662 link_rate
= (port_state
& PORT_STATE_PHY8_CONN_RATE_MSK
) >>
2663 PORT_STATE_PHY8_CONN_RATE_OFF
;
2665 port_id
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
2666 port_id
= (port_id
>> (4 * phy_no
)) & 0xf;
2667 link_rate
= hisi_sas_read32(hisi_hba
, PHY_CONN_RATE
);
2668 link_rate
= (link_rate
>> (phy_no
* 4)) & 0xf;
2671 if (port_id
== 0xf) {
2672 dev_err(dev
, "phyup: phy%d invalid portid\n", phy_no
);
2677 for (i
= 0; i
< 6; i
++) {
2678 u32 idaf
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2679 RX_IDAF_DWORD0
+ (i
* 4));
2680 frame_rcvd
[i
] = __swab32(idaf
);
2683 sas_phy
->linkrate
= link_rate
;
2684 hard_phy_linkrate
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2686 phy
->maximum_linkrate
= hard_phy_linkrate
& 0xf;
2687 phy
->minimum_linkrate
= (hard_phy_linkrate
>> 4) & 0xf;
2689 sas_phy
->oob_mode
= SAS_OOB_MODE
;
2690 memcpy(sas_phy
->attached_sas_addr
, &id
->sas_addr
, SAS_ADDR_SIZE
);
2691 dev_info(dev
, "phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
2692 phy
->port_id
= port_id
;
2693 phy
->phy_type
&= ~(PORT_TYPE_SAS
| PORT_TYPE_SATA
);
2694 phy
->phy_type
|= PORT_TYPE_SAS
;
2695 phy
->phy_attached
= 1;
2696 phy
->identify
.device_type
= id
->dev_type
;
2697 phy
->frame_rcvd_size
= sizeof(struct sas_identify_frame
);
2698 if (phy
->identify
.device_type
== SAS_END_DEVICE
)
2699 phy
->identify
.target_port_protocols
=
2701 else if (phy
->identify
.device_type
!= SAS_PHY_UNUSED
) {
2702 phy
->identify
.target_port_protocols
=
2704 if (!timer_pending(&hisi_hba
->timer
))
2705 set_link_timer_quirk(hisi_hba
);
2707 queue_work(hisi_hba
->wq
, &phy
->phyup_ws
);
2710 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
2711 CHL_INT0_SL_PHY_ENABLE_MSK
);
2712 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 0);
2717 static bool check_any_wideports_v2_hw(struct hisi_hba
*hisi_hba
)
2721 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
2722 if (port_state
& 0x1ff)
2728 static int phy_down_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2730 u32 phy_state
, sl_ctrl
, txid_auto
;
2731 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2732 struct hisi_sas_port
*port
= phy
->port
;
2733 struct device
*dev
= hisi_hba
->dev
;
2735 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 1);
2737 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
2738 dev_info(dev
, "phydown: phy%d phy_state=0x%x\n", phy_no
, phy_state
);
2739 hisi_sas_phy_down(hisi_hba
, phy_no
, (phy_state
& 1 << phy_no
) ? 1 : 0);
2741 sl_ctrl
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
2742 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
,
2743 sl_ctrl
& ~SL_CONTROL_CTA_MSK
);
2744 if (port
&& !get_wideport_bitmap_v2_hw(hisi_hba
, port
->id
))
2745 if (!check_any_wideports_v2_hw(hisi_hba
) &&
2746 timer_pending(&hisi_hba
->timer
))
2747 del_timer(&hisi_hba
->timer
);
2749 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
2750 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
2751 txid_auto
| TXID_AUTO_CT3_MSK
);
2753 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
, CHL_INT0_NOT_RDY_MSK
);
2754 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 0);
2759 static irqreturn_t
int_phy_updown_v2_hw(int irq_no
, void *p
)
2761 struct hisi_hba
*hisi_hba
= p
;
2764 irqreturn_t res
= IRQ_NONE
;
2766 irq_msk
= (hisi_sas_read32(hisi_hba
, HGC_INVLD_DQE_INFO
)
2767 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF
) & 0x1ff;
2770 u32 reg_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2773 switch (reg_value
& (CHL_INT0_NOT_RDY_MSK
|
2774 CHL_INT0_SL_PHY_ENABLE_MSK
)) {
2776 case CHL_INT0_SL_PHY_ENABLE_MSK
:
2778 if (phy_up_v2_hw(phy_no
, hisi_hba
) ==
2783 case CHL_INT0_NOT_RDY_MSK
:
2785 if (phy_down_v2_hw(phy_no
, hisi_hba
) ==
2790 case (CHL_INT0_NOT_RDY_MSK
|
2791 CHL_INT0_SL_PHY_ENABLE_MSK
):
2792 reg_value
= hisi_sas_read32(hisi_hba
,
2794 if (reg_value
& BIT(phy_no
)) {
2796 if (phy_up_v2_hw(phy_no
, hisi_hba
) ==
2801 if (phy_down_v2_hw(phy_no
, hisi_hba
) ==
2819 static void phy_bcast_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2821 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2822 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
2823 struct sas_ha_struct
*sas_ha
= &hisi_hba
->sha
;
2826 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 1);
2827 bcast_status
= hisi_sas_phy_read32(hisi_hba
, phy_no
, RX_PRIMS_STATUS
);
2828 if (bcast_status
& RX_BCAST_CHG_MSK
)
2829 sas_ha
->notify_port_event(sas_phy
, PORTE_BROADCAST_RCVD
);
2830 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
2831 CHL_INT0_SL_RX_BCST_ACK_MSK
);
2832 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 0);
2835 static irqreturn_t
int_chnl_int_v2_hw(int irq_no
, void *p
)
2837 struct hisi_hba
*hisi_hba
= p
;
2838 struct device
*dev
= hisi_hba
->dev
;
2839 u32 ent_msk
, ent_tmp
, irq_msk
;
2842 ent_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
2844 ent_msk
|= ENT_INT_SRC_MSK3_ENT95_MSK_MSK
;
2845 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_msk
);
2847 irq_msk
= (hisi_sas_read32(hisi_hba
, HGC_INVLD_DQE_INFO
) >>
2848 HGC_INVLD_DQE_INFO_FB_CH3_OFF
) & 0x1ff;
2851 if (irq_msk
& (1 << phy_no
)) {
2852 u32 irq_value0
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2854 u32 irq_value1
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2856 u32 irq_value2
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2860 if (irq_value1
& (CHL_INT1_DMAC_RX_ECC_ERR_MSK
|
2861 CHL_INT1_DMAC_TX_ECC_ERR_MSK
))
2862 panic("%s: DMAC RX/TX ecc bad error!\
2864 dev_name(dev
), irq_value1
);
2866 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2867 CHL_INT1
, irq_value1
);
2871 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2872 CHL_INT2
, irq_value2
);
2876 if (irq_value0
& CHL_INT0_SL_RX_BCST_ACK_MSK
)
2877 phy_bcast_v2_hw(phy_no
, hisi_hba
);
2879 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2880 CHL_INT0
, irq_value0
2881 & (~CHL_INT0_HOTPLUG_TOUT_MSK
)
2882 & (~CHL_INT0_SL_PHY_ENABLE_MSK
)
2883 & (~CHL_INT0_NOT_RDY_MSK
));
2886 irq_msk
&= ~(1 << phy_no
);
2890 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_tmp
);
2896 one_bit_ecc_error_process_v2_hw(struct hisi_hba
*hisi_hba
, u32 irq_value
)
2898 struct device
*dev
= hisi_hba
->dev
;
2899 const struct hisi_sas_hw_error
*ecc_error
;
2903 for (i
= 0; i
< ARRAY_SIZE(one_bit_ecc_errors
); i
++) {
2904 ecc_error
= &one_bit_ecc_errors
[i
];
2905 if (irq_value
& ecc_error
->irq_msk
) {
2906 val
= hisi_sas_read32(hisi_hba
, ecc_error
->reg
);
2907 val
&= ecc_error
->msk
;
2908 val
>>= ecc_error
->shift
;
2909 dev_warn(dev
, ecc_error
->msg
, val
);
2914 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba
*hisi_hba
,
2917 struct device
*dev
= hisi_hba
->dev
;
2918 const struct hisi_sas_hw_error
*ecc_error
;
2922 for (i
= 0; i
< ARRAY_SIZE(multi_bit_ecc_errors
); i
++) {
2923 ecc_error
= &multi_bit_ecc_errors
[i
];
2924 if (irq_value
& ecc_error
->irq_msk
) {
2925 val
= hisi_sas_read32(hisi_hba
, ecc_error
->reg
);
2926 val
&= ecc_error
->msk
;
2927 val
>>= ecc_error
->shift
;
2928 dev_err(dev
, ecc_error
->msg
, irq_value
, val
);
2929 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
2936 static irqreturn_t
fatal_ecc_int_v2_hw(int irq_no
, void *p
)
2938 struct hisi_hba
*hisi_hba
= p
;
2939 u32 irq_value
, irq_msk
;
2941 irq_msk
= hisi_sas_read32(hisi_hba
, SAS_ECC_INTR_MSK
);
2942 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, irq_msk
| 0xffffffff);
2944 irq_value
= hisi_sas_read32(hisi_hba
, SAS_ECC_INTR
);
2946 one_bit_ecc_error_process_v2_hw(hisi_hba
, irq_value
);
2947 multi_bit_ecc_error_process_v2_hw(hisi_hba
, irq_value
);
2950 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR
, irq_value
);
2951 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, irq_msk
);
2956 static const struct hisi_sas_hw_error axi_error
[] = {
2957 { .msk
= BIT(0), .msg
= "IOST_AXI_W_ERR" },
2958 { .msk
= BIT(1), .msg
= "IOST_AXI_R_ERR" },
2959 { .msk
= BIT(2), .msg
= "ITCT_AXI_W_ERR" },
2960 { .msk
= BIT(3), .msg
= "ITCT_AXI_R_ERR" },
2961 { .msk
= BIT(4), .msg
= "SATA_AXI_W_ERR" },
2962 { .msk
= BIT(5), .msg
= "SATA_AXI_R_ERR" },
2963 { .msk
= BIT(6), .msg
= "DQE_AXI_R_ERR" },
2964 { .msk
= BIT(7), .msg
= "CQE_AXI_W_ERR" },
2968 static const struct hisi_sas_hw_error fifo_error
[] = {
2969 { .msk
= BIT(8), .msg
= "CQE_WINFO_FIFO" },
2970 { .msk
= BIT(9), .msg
= "CQE_MSG_FIFIO" },
2971 { .msk
= BIT(10), .msg
= "GETDQE_FIFO" },
2972 { .msk
= BIT(11), .msg
= "CMDP_FIFO" },
2973 { .msk
= BIT(12), .msg
= "AWTCTRL_FIFO" },
2977 static const struct hisi_sas_hw_error fatal_axi_errors
[] = {
2979 .irq_msk
= BIT(ENT_INT_SRC3_WP_DEPTH_OFF
),
2980 .msg
= "write pointer and depth",
2983 .irq_msk
= BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF
),
2984 .msg
= "iptt no match slot",
2987 .irq_msk
= BIT(ENT_INT_SRC3_RP_DEPTH_OFF
),
2988 .msg
= "read pointer and depth",
2991 .irq_msk
= BIT(ENT_INT_SRC3_AXI_OFF
),
2992 .reg
= HGC_AXI_FIFO_ERR_INFO
,
2996 .irq_msk
= BIT(ENT_INT_SRC3_FIFO_OFF
),
2997 .reg
= HGC_AXI_FIFO_ERR_INFO
,
3001 .irq_msk
= BIT(ENT_INT_SRC3_LM_OFF
),
3002 .msg
= "LM add/fetch list",
3005 .irq_msk
= BIT(ENT_INT_SRC3_ABT_OFF
),
3006 .msg
= "SAS_HGC_ABT fetch LM list",
3010 static irqreturn_t
fatal_axi_int_v2_hw(int irq_no
, void *p
)
3012 struct hisi_hba
*hisi_hba
= p
;
3013 u32 irq_value
, irq_msk
, err_value
;
3014 struct device
*dev
= hisi_hba
->dev
;
3015 const struct hisi_sas_hw_error
*axi_error
;
3018 irq_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
3019 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, irq_msk
| 0xfffffffe);
3021 irq_value
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
3023 for (i
= 0; i
< ARRAY_SIZE(fatal_axi_errors
); i
++) {
3024 axi_error
= &fatal_axi_errors
[i
];
3025 if (!(irq_value
& axi_error
->irq_msk
))
3028 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
3029 1 << axi_error
->shift
);
3030 if (axi_error
->sub
) {
3031 const struct hisi_sas_hw_error
*sub
= axi_error
->sub
;
3033 err_value
= hisi_sas_read32(hisi_hba
, axi_error
->reg
);
3034 for (; sub
->msk
|| sub
->msg
; sub
++) {
3035 if (!(err_value
& sub
->msk
))
3037 dev_err(dev
, "%s (0x%x) found!\n",
3038 sub
->msg
, irq_value
);
3039 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
3042 dev_err(dev
, "%s (0x%x) found!\n",
3043 axi_error
->msg
, irq_value
);
3044 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
3048 if (irq_value
& BIT(ENT_INT_SRC3_ITC_INT_OFF
)) {
3049 u32 reg_val
= hisi_sas_read32(hisi_hba
, ITCT_CLR
);
3050 u32 dev_id
= reg_val
& ITCT_DEV_MSK
;
3051 struct hisi_sas_device
*sas_dev
= &hisi_hba
->devices
[dev_id
];
3053 hisi_sas_write32(hisi_hba
, ITCT_CLR
, 0);
3054 dev_dbg(dev
, "clear ITCT ok\n");
3055 complete(sas_dev
->completion
);
3058 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
, irq_value
);
3059 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, irq_msk
);
3064 static void cq_tasklet_v2_hw(unsigned long val
)
3066 struct hisi_sas_cq
*cq
= (struct hisi_sas_cq
*)val
;
3067 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
3068 struct hisi_sas_slot
*slot
;
3069 struct hisi_sas_itct
*itct
;
3070 struct hisi_sas_complete_v2_hdr
*complete_queue
;
3071 u32 rd_point
= cq
->rd_point
, wr_point
, dev_id
;
3073 struct hisi_sas_dq
*dq
= &hisi_hba
->dq
[queue
];
3075 if (unlikely(hisi_hba
->reject_stp_links_msk
))
3076 phys_try_accept_stp_links_v2_hw(hisi_hba
);
3078 complete_queue
= hisi_hba
->complete_hdr
[queue
];
3080 spin_lock(&dq
->lock
);
3081 wr_point
= hisi_sas_read32(hisi_hba
, COMPL_Q_0_WR_PTR
+
3084 while (rd_point
!= wr_point
) {
3085 struct hisi_sas_complete_v2_hdr
*complete_hdr
;
3088 complete_hdr
= &complete_queue
[rd_point
];
3090 /* Check for NCQ completion */
3091 if (complete_hdr
->act
) {
3092 u32 act_tmp
= complete_hdr
->act
;
3093 int ncq_tag_count
= ffs(act_tmp
);
3095 dev_id
= (complete_hdr
->dw1
& CMPLT_HDR_DEV_ID_MSK
) >>
3096 CMPLT_HDR_DEV_ID_OFF
;
3097 itct
= &hisi_hba
->itct
[dev_id
];
3099 /* The NCQ tags are held in the itct header */
3100 while (ncq_tag_count
) {
3101 __le64
*ncq_tag
= &itct
->qw4_15
[0];
3104 iptt
= (ncq_tag
[ncq_tag_count
/ 5]
3105 >> (ncq_tag_count
% 5) * 12) & 0xfff;
3107 slot
= &hisi_hba
->slot_info
[iptt
];
3108 slot
->cmplt_queue_slot
= rd_point
;
3109 slot
->cmplt_queue
= queue
;
3110 slot_complete_v2_hw(hisi_hba
, slot
);
3112 act_tmp
&= ~(1 << ncq_tag_count
);
3113 ncq_tag_count
= ffs(act_tmp
);
3116 iptt
= (complete_hdr
->dw1
) & CMPLT_HDR_IPTT_MSK
;
3117 slot
= &hisi_hba
->slot_info
[iptt
];
3118 slot
->cmplt_queue_slot
= rd_point
;
3119 slot
->cmplt_queue
= queue
;
3120 slot_complete_v2_hw(hisi_hba
, slot
);
3123 if (++rd_point
>= HISI_SAS_QUEUE_SLOTS
)
3127 /* update rd_point */
3128 cq
->rd_point
= rd_point
;
3129 hisi_sas_write32(hisi_hba
, COMPL_Q_0_RD_PTR
+ (0x14 * queue
), rd_point
);
3130 spin_unlock(&dq
->lock
);
3133 static irqreturn_t
cq_interrupt_v2_hw(int irq_no
, void *p
)
3135 struct hisi_sas_cq
*cq
= p
;
3136 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
3139 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 1 << queue
);
3141 tasklet_schedule(&cq
->tasklet
);
3146 static irqreturn_t
sata_int_v2_hw(int irq_no
, void *p
)
3148 struct hisi_sas_phy
*phy
= p
;
3149 struct hisi_hba
*hisi_hba
= phy
->hisi_hba
;
3150 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
3151 struct device
*dev
= hisi_hba
->dev
;
3152 struct hisi_sas_initial_fis
*initial_fis
;
3153 struct dev_to_host_fis
*fis
;
3154 u32 ent_tmp
, ent_msk
, ent_int
, port_id
, link_rate
, hard_phy_linkrate
;
3155 irqreturn_t res
= IRQ_HANDLED
;
3156 u8 attached_sas_addr
[SAS_ADDR_SIZE
] = {0};
3159 phy_no
= sas_phy
->id
;
3160 initial_fis
= &hisi_hba
->initial_fis
[phy_no
];
3161 fis
= &initial_fis
->fis
;
3163 offset
= 4 * (phy_no
/ 4);
3164 ent_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
);
3165 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
,
3166 ent_msk
| 1 << ((phy_no
% 4) * 8));
3168 ent_int
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC1
+ offset
);
3169 ent_tmp
= ent_int
& (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF
*
3171 ent_int
>>= ENT_INT_SRC1_D2H_FIS_CH1_OFF
* (phy_no
% 4);
3172 if ((ent_int
& ENT_INT_SRC1_D2H_FIS_CH0_MSK
) == 0) {
3173 dev_warn(dev
, "sata int: phy%d did not receive FIS\n", phy_no
);
3178 /* check ERR bit of Status Register */
3179 if (fis
->status
& ATA_ERR
) {
3180 dev_warn(dev
, "sata int: phy%d FIS status: 0x%x\n", phy_no
,
3182 disable_phy_v2_hw(hisi_hba
, phy_no
);
3183 enable_phy_v2_hw(hisi_hba
, phy_no
);
3188 if (unlikely(phy_no
== 8)) {
3189 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
3191 port_id
= (port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
3192 PORT_STATE_PHY8_PORT_NUM_OFF
;
3193 link_rate
= (port_state
& PORT_STATE_PHY8_CONN_RATE_MSK
) >>
3194 PORT_STATE_PHY8_CONN_RATE_OFF
;
3196 port_id
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
3197 port_id
= (port_id
>> (4 * phy_no
)) & 0xf;
3198 link_rate
= hisi_sas_read32(hisi_hba
, PHY_CONN_RATE
);
3199 link_rate
= (link_rate
>> (phy_no
* 4)) & 0xf;
3202 if (port_id
== 0xf) {
3203 dev_err(dev
, "sata int: phy%d invalid portid\n", phy_no
);
3208 sas_phy
->linkrate
= link_rate
;
3209 hard_phy_linkrate
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
3211 phy
->maximum_linkrate
= hard_phy_linkrate
& 0xf;
3212 phy
->minimum_linkrate
= (hard_phy_linkrate
>> 4) & 0xf;
3214 sas_phy
->oob_mode
= SATA_OOB_MODE
;
3215 /* Make up some unique SAS address */
3216 attached_sas_addr
[0] = 0x50;
3217 attached_sas_addr
[7] = phy_no
;
3218 memcpy(sas_phy
->attached_sas_addr
, attached_sas_addr
, SAS_ADDR_SIZE
);
3219 memcpy(sas_phy
->frame_rcvd
, fis
, sizeof(struct dev_to_host_fis
));
3220 dev_info(dev
, "sata int phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
3221 phy
->phy_type
&= ~(PORT_TYPE_SAS
| PORT_TYPE_SATA
);
3222 phy
->port_id
= port_id
;
3223 phy
->phy_type
|= PORT_TYPE_SATA
;
3224 phy
->phy_attached
= 1;
3225 phy
->identify
.device_type
= SAS_SATA_DEV
;
3226 phy
->frame_rcvd_size
= sizeof(struct dev_to_host_fis
);
3227 phy
->identify
.target_port_protocols
= SAS_PROTOCOL_SATA
;
3228 queue_work(hisi_hba
->wq
, &phy
->phyup_ws
);
3231 hisi_sas_write32(hisi_hba
, ENT_INT_SRC1
+ offset
, ent_tmp
);
3232 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
, ent_msk
);
3237 static irq_handler_t phy_interrupts
[HISI_SAS_PHY_INT_NR
] = {
3238 int_phy_updown_v2_hw
,
3242 static irq_handler_t fatal_interrupts
[HISI_SAS_FATAL_INT_NR
] = {
3243 fatal_ecc_int_v2_hw
,
3248 * There is a limitation in the hip06 chipset that we need
3249 * to map in all mbigen interrupts, even if they are not used.
3251 static int interrupt_init_v2_hw(struct hisi_hba
*hisi_hba
)
3253 struct platform_device
*pdev
= hisi_hba
->platform_dev
;
3254 struct device
*dev
= &pdev
->dev
;
3255 int irq
, rc
, irq_map
[128];
3256 int i
, phy_no
, fatal_no
, queue_no
, k
;
3258 for (i
= 0; i
< 128; i
++)
3259 irq_map
[i
] = platform_get_irq(pdev
, i
);
3261 for (i
= 0; i
< HISI_SAS_PHY_INT_NR
; i
++) {
3262 irq
= irq_map
[i
+ 1]; /* Phy up/down is irq1 */
3263 rc
= devm_request_irq(dev
, irq
, phy_interrupts
[i
], 0,
3264 DRV_NAME
" phy", hisi_hba
);
3266 dev_err(dev
, "irq init: could not request "
3267 "phy interrupt %d, rc=%d\n",
3270 goto free_phy_int_irqs
;
3274 for (phy_no
= 0; phy_no
< hisi_hba
->n_phy
; phy_no
++) {
3275 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
3277 irq
= irq_map
[phy_no
+ 72];
3278 rc
= devm_request_irq(dev
, irq
, sata_int_v2_hw
, 0,
3279 DRV_NAME
" sata", phy
);
3281 dev_err(dev
, "irq init: could not request "
3282 "sata interrupt %d, rc=%d\n",
3285 goto free_sata_int_irqs
;
3289 for (fatal_no
= 0; fatal_no
< HISI_SAS_FATAL_INT_NR
; fatal_no
++) {
3290 irq
= irq_map
[fatal_no
+ 81];
3291 rc
= devm_request_irq(dev
, irq
, fatal_interrupts
[fatal_no
], 0,
3292 DRV_NAME
" fatal", hisi_hba
);
3295 "irq init: could not request fatal interrupt %d, rc=%d\n",
3298 goto free_fatal_int_irqs
;
3302 for (queue_no
= 0; queue_no
< hisi_hba
->queue_count
; queue_no
++) {
3303 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[queue_no
];
3304 struct tasklet_struct
*t
= &cq
->tasklet
;
3306 irq
= irq_map
[queue_no
+ 96];
3307 rc
= devm_request_irq(dev
, irq
, cq_interrupt_v2_hw
, 0,
3308 DRV_NAME
" cq", cq
);
3311 "irq init: could not request cq interrupt %d, rc=%d\n",
3314 goto free_cq_int_irqs
;
3316 tasklet_init(t
, cq_tasklet_v2_hw
, (unsigned long)cq
);
3322 for (k
= 0; k
< queue_no
; k
++) {
3323 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[k
];
3325 free_irq(irq_map
[k
+ 96], cq
);
3326 tasklet_kill(&cq
->tasklet
);
3328 free_fatal_int_irqs
:
3329 for (k
= 0; k
< fatal_no
; k
++)
3330 free_irq(irq_map
[k
+ 81], hisi_hba
);
3332 for (k
= 0; k
< phy_no
; k
++) {
3333 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[k
];
3335 free_irq(irq_map
[k
+ 72], phy
);
3338 for (k
= 0; k
< i
; k
++)
3339 free_irq(irq_map
[k
+ 1], hisi_hba
);
3343 static int hisi_sas_v2_init(struct hisi_hba
*hisi_hba
)
3347 memset(hisi_hba
->sata_dev_bitmap
, 0, sizeof(hisi_hba
->sata_dev_bitmap
));
3349 rc
= hw_init_v2_hw(hisi_hba
);
3353 rc
= interrupt_init_v2_hw(hisi_hba
);
3360 static void interrupt_disable_v2_hw(struct hisi_hba
*hisi_hba
)
3362 struct platform_device
*pdev
= hisi_hba
->platform_dev
;
3365 for (i
= 0; i
< hisi_hba
->queue_count
; i
++)
3366 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+ 0x4 * i
, 0x1);
3368 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0xffffffff);
3369 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0xffffffff);
3370 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0xffffffff);
3371 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0xffffffff);
3373 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
3374 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xffffffff);
3375 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0xffffffff);
3378 for (i
= 0; i
< 128; i
++)
3379 synchronize_irq(platform_get_irq(pdev
, i
));
3383 static u32
get_phys_state_v2_hw(struct hisi_hba
*hisi_hba
)
3385 return hisi_sas_read32(hisi_hba
, PHY_STATE
);
3388 static int soft_reset_v2_hw(struct hisi_hba
*hisi_hba
)
3390 struct device
*dev
= hisi_hba
->dev
;
3393 interrupt_disable_v2_hw(hisi_hba
);
3394 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0x0);
3395 hisi_sas_kill_tasklets(hisi_hba
);
3397 hisi_sas_stop_phys(hisi_hba
);
3401 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
+ AM_CTRL_GLOBAL
, 0x1);
3403 /* wait until bus idle */
3406 u32 status
= hisi_sas_read32_relaxed(hisi_hba
,
3407 AXI_MASTER_CFG_BASE
+ AM_CURR_TRANS_RETURN
);
3414 dev_err(dev
, "wait axi bus state to idle timeout!\n");
3419 hisi_sas_init_mem(hisi_hba
);
3421 rc
= hw_init_v2_hw(hisi_hba
);
3425 phys_reject_stp_links_v2_hw(hisi_hba
);
3430 static int write_gpio_v2_hw(struct hisi_hba
*hisi_hba
, u8 reg_type
,
3431 u8 reg_index
, u8 reg_count
, u8
*write_data
)
3433 struct device
*dev
= hisi_hba
->dev
;
3436 if (!hisi_hba
->sgpio_regs
)
3440 case SAS_GPIO_REG_TX
:
3441 count
= reg_count
* 4;
3442 count
= min(count
, hisi_hba
->n_phy
);
3444 for (phy_no
= 0; phy_no
< count
; phy_no
++) {
3446 * GPIO_TX[n] register has the highest numbered drive
3447 * of the four in the first byte and the lowest
3448 * numbered drive in the fourth byte.
3449 * See SFF-8485 Rev. 0.7 Table 24.
3451 void __iomem
*reg_addr
= hisi_hba
->sgpio_regs
+
3452 reg_index
* 4 + phy_no
;
3453 int data_idx
= phy_no
+ 3 - (phy_no
% 4) * 2;
3455 writeb(write_data
[data_idx
], reg_addr
);
3460 dev_err(dev
, "write gpio: unsupported or bad reg type %d\n",
3468 static const struct hisi_sas_hw hisi_sas_v2_hw
= {
3469 .hw_init
= hisi_sas_v2_init
,
3470 .setup_itct
= setup_itct_v2_hw
,
3471 .slot_index_alloc
= slot_index_alloc_quirk_v2_hw
,
3472 .alloc_dev
= alloc_dev_quirk_v2_hw
,
3473 .sl_notify
= sl_notify_v2_hw
,
3474 .get_wideport_bitmap
= get_wideport_bitmap_v2_hw
,
3475 .clear_itct
= clear_itct_v2_hw
,
3476 .free_device
= free_device_v2_hw
,
3477 .prep_smp
= prep_smp_v2_hw
,
3478 .prep_ssp
= prep_ssp_v2_hw
,
3479 .prep_stp
= prep_ata_v2_hw
,
3480 .prep_abort
= prep_abort_v2_hw
,
3481 .get_free_slot
= get_free_slot_v2_hw
,
3482 .start_delivery
= start_delivery_v2_hw
,
3483 .slot_complete
= slot_complete_v2_hw
,
3484 .phys_init
= phys_init_v2_hw
,
3485 .phy_start
= start_phy_v2_hw
,
3486 .phy_disable
= disable_phy_v2_hw
,
3487 .phy_hard_reset
= phy_hard_reset_v2_hw
,
3488 .get_events
= phy_get_events_v2_hw
,
3489 .phy_set_linkrate
= phy_set_linkrate_v2_hw
,
3490 .phy_get_max_linkrate
= phy_get_max_linkrate_v2_hw
,
3491 .max_command_entries
= HISI_SAS_COMMAND_ENTRIES_V2_HW
,
3492 .complete_hdr_size
= sizeof(struct hisi_sas_complete_v2_hdr
),
3493 .soft_reset
= soft_reset_v2_hw
,
3494 .get_phys_state
= get_phys_state_v2_hw
,
3495 .write_gpio
= write_gpio_v2_hw
,
3498 static int hisi_sas_v2_probe(struct platform_device
*pdev
)
3501 * Check if we should defer the probe before we probe the
3502 * upper layer, as it's hard to defer later on.
3504 int ret
= platform_get_irq(pdev
, 0);
3507 if (ret
!= -EPROBE_DEFER
)
3508 dev_err(&pdev
->dev
, "cannot obtain irq\n");
3512 return hisi_sas_probe(pdev
, &hisi_sas_v2_hw
);
3515 static int hisi_sas_v2_remove(struct platform_device
*pdev
)
3517 struct sas_ha_struct
*sha
= platform_get_drvdata(pdev
);
3518 struct hisi_hba
*hisi_hba
= sha
->lldd_ha
;
3520 if (timer_pending(&hisi_hba
->timer
))
3521 del_timer(&hisi_hba
->timer
);
3523 hisi_sas_kill_tasklets(hisi_hba
);
3525 return hisi_sas_remove(pdev
);
3528 static const struct of_device_id sas_v2_of_match
[] = {
3529 { .compatible
= "hisilicon,hip06-sas-v2",},
3530 { .compatible
= "hisilicon,hip07-sas-v2",},
3533 MODULE_DEVICE_TABLE(of
, sas_v2_of_match
);
3535 static const struct acpi_device_id sas_v2_acpi_match
[] = {
3540 MODULE_DEVICE_TABLE(acpi
, sas_v2_acpi_match
);
3542 static struct platform_driver hisi_sas_v2_driver
= {
3543 .probe
= hisi_sas_v2_probe
,
3544 .remove
= hisi_sas_v2_remove
,
3547 .of_match_table
= sas_v2_of_match
,
3548 .acpi_match_table
= ACPI_PTR(sas_v2_acpi_match
),
3552 module_platform_driver(hisi_sas_v2_driver
);
3554 MODULE_LICENSE("GPL");
3555 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3556 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3557 MODULE_ALIAS("platform:" DRV_NAME
);