2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
13 #define DRV_NAME "hisi_sas_v2_hw"
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
148 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
149 #define DLVRY_Q_0_DEPTH 0x268
150 #define DLVRY_Q_0_WR_PTR 0x26c
151 #define DLVRY_Q_0_RD_PTR 0x270
152 #define HYPER_STREAM_ID_EN_CFG 0xc80
153 #define OQ0_INT_SRC_MSK 0xc90
154 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
155 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
156 #define COMPL_Q_0_DEPTH 0x4e8
157 #define COMPL_Q_0_WR_PTR 0x4ec
158 #define COMPL_Q_0_RD_PTR 0x4f0
159 #define HGC_RXM_DFX_STATUS14 0xae8
160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
162 HGC_RXM_DFX_STATUS14_MEM0_OFF)
163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM1_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM2_OFF)
169 #define HGC_RXM_DFX_STATUS15 0xaec
170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
172 HGC_RXM_DFX_STATUS15_MEM3_OFF)
173 /* phy registers need init */
174 #define PORT_BASE (0x2000)
176 #define PHY_CFG (PORT_BASE + 0x0)
177 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PHY_CFG_ENA_OFF 0
179 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
180 #define PHY_CFG_DC_OPT_OFF 2
181 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
182 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
183 #define PROG_PHY_LINK_RATE_MAX_OFF 0
184 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
185 #define PHY_CTRL (PORT_BASE + 0x14)
186 #define PHY_CTRL_RESET_OFF 0
187 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
188 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
189 #define SL_CFG (PORT_BASE + 0x84)
190 #define PHY_PCN (PORT_BASE + 0x44)
191 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
192 #define SL_CONTROL (PORT_BASE + 0x94)
193 #define SL_CONTROL_NOTIFY_EN_OFF 0
194 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
195 #define SL_CONTROL_CTA_OFF 17
196 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
197 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
198 #define RX_BCAST_CHG_OFF 1
199 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
200 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
201 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
202 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
203 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
204 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
205 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
206 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
207 #define TXID_AUTO (PORT_BASE + 0xb8)
208 #define TXID_AUTO_CT3_OFF 1
209 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
210 #define TX_HARDRST_OFF 2
211 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
212 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
213 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
214 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
215 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
216 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
217 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
218 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
219 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
220 #define CON_CONTROL (PORT_BASE + 0x118)
221 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
222 #define CHL_INT0 (PORT_BASE + 0x1b4)
223 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
224 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
225 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
226 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
227 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
228 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
229 #define CHL_INT0_NOT_RDY_OFF 4
230 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
231 #define CHL_INT0_PHY_RDY_OFF 5
232 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
233 #define CHL_INT1 (PORT_BASE + 0x1b8)
234 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
235 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
236 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
237 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
238 #define CHL_INT2 (PORT_BASE + 0x1bc)
239 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
240 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
241 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
242 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
243 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
244 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
245 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
246 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
247 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
248 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
249 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
250 #define DMA_TX_STATUS_BUSY_OFF 0
251 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
252 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
253 #define DMA_RX_STATUS_BUSY_OFF 0
254 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
256 #define AXI_CFG (0x5100)
257 #define AM_CFG_MAX_TRANS (0x5010)
258 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
260 /* HW dma structures */
261 /* Delivery queue header */
263 #define CMD_HDR_ABORT_FLAG_OFF 0
264 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
265 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
266 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
267 #define CMD_HDR_RESP_REPORT_OFF 5
268 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
269 #define CMD_HDR_TLR_CTRL_OFF 6
270 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
271 #define CMD_HDR_PORT_OFF 18
272 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
273 #define CMD_HDR_PRIORITY_OFF 27
274 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
275 #define CMD_HDR_CMD_OFF 29
276 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
278 #define CMD_HDR_DIR_OFF 5
279 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
280 #define CMD_HDR_RESET_OFF 7
281 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
282 #define CMD_HDR_VDTL_OFF 10
283 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
284 #define CMD_HDR_FRAME_TYPE_OFF 11
285 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
286 #define CMD_HDR_DEV_ID_OFF 16
287 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
289 #define CMD_HDR_CFL_OFF 0
290 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
291 #define CMD_HDR_NCQ_TAG_OFF 10
292 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
293 #define CMD_HDR_MRFL_OFF 15
294 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
295 #define CMD_HDR_SG_MOD_OFF 24
296 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
297 #define CMD_HDR_FIRST_BURST_OFF 26
298 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
300 #define CMD_HDR_IPTT_OFF 0
301 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
303 #define CMD_HDR_DIF_SGL_LEN_OFF 0
304 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
305 #define CMD_HDR_DATA_SGL_LEN_OFF 16
306 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
307 #define CMD_HDR_ABORT_IPTT_OFF 16
308 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
310 /* Completion header */
312 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
313 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
314 #define CMPLT_HDR_ERX_OFF 12
315 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
316 #define CMPLT_HDR_ABORT_STAT_OFF 13
317 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
319 #define STAT_IO_NOT_VALID 0x1
320 #define STAT_IO_NO_DEVICE 0x2
321 #define STAT_IO_COMPLETE 0x3
322 #define STAT_IO_ABORTED 0x4
324 #define CMPLT_HDR_IPTT_OFF 0
325 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
326 #define CMPLT_HDR_DEV_ID_OFF 16
327 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
331 #define ITCT_HDR_DEV_TYPE_OFF 0
332 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
333 #define ITCT_HDR_VALID_OFF 2
334 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
335 #define ITCT_HDR_MCR_OFF 5
336 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
337 #define ITCT_HDR_VLN_OFF 9
338 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
339 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
340 #define ITCT_HDR_SMP_TIMEOUT_8US 1
341 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
343 #define ITCT_HDR_AWT_CONTINUE_OFF 25
344 #define ITCT_HDR_PORT_ID_OFF 28
345 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
347 #define ITCT_HDR_INLT_OFF 0
348 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
349 #define ITCT_HDR_BITLT_OFF 16
350 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
351 #define ITCT_HDR_MCTLT_OFF 32
352 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
353 #define ITCT_HDR_RTOLT_OFF 48
354 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
356 #define HISI_SAS_FATAL_INT_NR 2
358 struct hisi_sas_complete_v2_hdr
{
365 struct hisi_sas_err_record_v2
{
367 __le32 trans_tx_fail_type
;
370 __le32 trans_rx_fail_type
;
373 __le16 dma_tx_err_type
;
374 __le16 sipc_rx_err_type
;
377 __le32 dma_rx_err_type
;
381 HISI_SAS_PHY_PHY_UPDOWN
,
382 HISI_SAS_PHY_CHNL_INT
,
387 TRANS_TX_FAIL_BASE
= 0x0, /* dw0 */
388 TRANS_RX_FAIL_BASE
= 0x100, /* dw1 */
389 DMA_TX_ERR_BASE
= 0x200, /* dw2 bit 15-0 */
390 SIPC_RX_ERR_BASE
= 0x300, /* dw2 bit 31-16*/
391 DMA_RX_ERR_BASE
= 0x400, /* dw3 */
394 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
= TRANS_TX_FAIL_BASE
, /* 0x0 */
395 TRANS_TX_ERR_PHY_NOT_ENABLE
, /* 0x1 */
396 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
, /* 0x2 */
397 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
, /* 0x3 */
398 TRANS_TX_OPEN_CNX_ERR_BY_OTHER
, /* 0x4 */
400 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
, /* 0x6 */
401 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
, /* 0x7 */
402 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
, /* 0x8 */
403 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
, /* 0x9 */
404 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
, /* 0xa */
405 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
, /* 0xb */
406 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
, /* 0xc */
407 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
, /* 0xd */
408 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
, /* 0xe */
409 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
, /* 0xf */
410 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
, /* 0x10 */
411 TRANS_TX_ERR_FRAME_TXED
, /* 0x11 */
412 TRANS_TX_ERR_WITH_BREAK_TIMEOUT
, /* 0x12 */
413 TRANS_TX_ERR_WITH_BREAK_REQUEST
, /* 0x13 */
414 TRANS_TX_ERR_WITH_BREAK_RECEVIED
, /* 0x14 */
415 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
, /* 0x15 */
416 TRANS_TX_ERR_WITH_CLOSE_NORMAL
, /* 0x16 for ssp*/
417 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
, /* 0x17 */
418 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
, /* 0x18 */
419 TRANS_TX_ERR_WITH_CLOSE_COMINIT
, /* 0x19 */
420 TRANS_TX_ERR_WITH_NAK_RECEVIED
, /* 0x1a for ssp*/
421 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
, /* 0x1b for ssp*/
422 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
423 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
, /* 0x1c for ssp */
424 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
425 TRANS_TX_ERR_WITH_IPTT_CONFLICT
, /* 0x1d for ssp/smp */
426 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS
, /* 0x1e */
427 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
428 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
, /* 0x1f for sata/stp */
431 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
= TRANS_RX_FAIL_BASE
, /* 0x100 */
432 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
, /* 0x101 for sata/stp */
433 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
, /* 0x102 for ssp/smp */
434 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x102 <] for sata/stp */
435 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
, /* 0x103 for sata/stp */
436 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
, /* 0x104 for sata/stp */
437 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
, /* 0x105 for smp */
438 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x105 <] for sata/stp */
439 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
, /* 0x106 for sata/stp*/
440 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
, /* 0x107 */
441 TRANS_RX_ERR_WITH_BREAK_TIMEOUT
, /* 0x108 */
442 TRANS_RX_ERR_WITH_BREAK_REQUEST
, /* 0x109 */
443 TRANS_RX_ERR_WITH_BREAK_RECEVIED
, /* 0x10a */
444 RESERVED1
, /* 0x10b */
445 TRANS_RX_ERR_WITH_CLOSE_NORMAL
, /* 0x10c */
446 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
, /* 0x10d */
447 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
, /* 0x10e */
448 TRANS_RX_ERR_WITH_CLOSE_COMINIT
, /* 0x10f */
449 TRANS_RX_ERR_WITH_DATA_LEN0
, /* 0x110 for ssp/smp */
450 TRANS_RX_ERR_WITH_BAD_HASH
, /* 0x111 for ssp */
451 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x111 <] for sata/stp */
452 TRANS_RX_XRDY_WLEN_ZERO_ERR
, /* 0x112 for ssp*/
453 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x112 <] for sata/stp */
454 TRANS_RX_SSP_FRM_LEN_ERR
, /* 0x113 for ssp */
455 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x113 <] for sata */
456 RESERVED2
, /* 0x114 */
457 RESERVED3
, /* 0x115 */
458 RESERVED4
, /* 0x116 */
459 RESERVED5
, /* 0x117 */
460 TRANS_RX_ERR_WITH_BAD_FRM_TYPE
, /* 0x118 */
461 TRANS_RX_SMP_FRM_LEN_ERR
, /* 0x119 */
462 TRANS_RX_SMP_RESP_TIMEOUT_ERR
, /* 0x11a */
463 RESERVED6
, /* 0x11b */
464 RESERVED7
, /* 0x11c */
465 RESERVED8
, /* 0x11d */
466 RESERVED9
, /* 0x11e */
467 TRANS_RX_R_ERR
, /* 0x11f */
470 DMA_TX_DIF_CRC_ERR
= DMA_TX_ERR_BASE
, /* 0x200 */
471 DMA_TX_DIF_APP_ERR
, /* 0x201 */
472 DMA_TX_DIF_RPP_ERR
, /* 0x202 */
473 DMA_TX_DATA_SGL_OVERFLOW
, /* 0x203 */
474 DMA_TX_DIF_SGL_OVERFLOW
, /* 0x204 */
475 DMA_TX_UNEXP_XFER_ERR
, /* 0x205 */
476 DMA_TX_UNEXP_RETRANS_ERR
, /* 0x206 */
477 DMA_TX_XFER_LEN_OVERFLOW
, /* 0x207 */
478 DMA_TX_XFER_OFFSET_ERR
, /* 0x208 */
479 DMA_TX_RAM_ECC_ERR
, /* 0x209 */
480 DMA_TX_DIF_LEN_ALIGN_ERR
, /* 0x20a */
483 SIPC_RX_FIS_STATUS_ERR_BIT_VLD
= SIPC_RX_ERR_BASE
, /* 0x300 */
484 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR
, /* 0x301 */
485 SIPC_RX_FIS_STATUS_BSY_BIT_ERR
, /* 0x302 */
486 SIPC_RX_WRSETUP_LEN_ODD_ERR
, /* 0x303 */
487 SIPC_RX_WRSETUP_LEN_ZERO_ERR
, /* 0x304 */
488 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR
, /* 0x305 */
489 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR
, /* 0x306 */
490 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR
, /* 0x307 */
491 SIPC_RX_SATA_UNEXP_FIS_ERR
, /* 0x308 */
492 SIPC_RX_WRSETUP_ESTATUS_ERR
, /* 0x309 */
493 SIPC_RX_DATA_UNDERFLOW_ERR
, /* 0x30a */
496 DMA_RX_DIF_CRC_ERR
= DMA_RX_ERR_BASE
, /* 0x400 */
497 DMA_RX_DIF_APP_ERR
, /* 0x401 */
498 DMA_RX_DIF_RPP_ERR
, /* 0x402 */
499 DMA_RX_DATA_SGL_OVERFLOW
, /* 0x403 */
500 DMA_RX_DIF_SGL_OVERFLOW
, /* 0x404 */
501 DMA_RX_DATA_LEN_OVERFLOW
, /* 0x405 */
502 DMA_RX_DATA_LEN_UNDERFLOW
, /* 0x406 */
503 DMA_RX_DATA_OFFSET_ERR
, /* 0x407 */
504 RESERVED10
, /* 0x408 */
505 DMA_RX_SATA_FRAME_TYPE_ERR
, /* 0x409 */
506 DMA_RX_RESP_BUF_OVERFLOW
, /* 0x40a */
507 DMA_RX_UNEXP_RETRANS_RESP_ERR
, /* 0x40b */
508 DMA_RX_UNEXP_NORM_RESP_ERR
, /* 0x40c */
509 DMA_RX_UNEXP_RDFRAME_ERR
, /* 0x40d */
510 DMA_RX_PIO_DATA_LEN_ERR
, /* 0x40e */
511 DMA_RX_RDSETUP_STATUS_ERR
, /* 0x40f */
512 DMA_RX_RDSETUP_STATUS_DRQ_ERR
, /* 0x410 */
513 DMA_RX_RDSETUP_STATUS_BSY_ERR
, /* 0x411 */
514 DMA_RX_RDSETUP_LEN_ODD_ERR
, /* 0x412 */
515 DMA_RX_RDSETUP_LEN_ZERO_ERR
, /* 0x413 */
516 DMA_RX_RDSETUP_LEN_OVER_ERR
, /* 0x414 */
517 DMA_RX_RDSETUP_OFFSET_ERR
, /* 0x415 */
518 DMA_RX_RDSETUP_ACTIVE_ERR
, /* 0x416 */
519 DMA_RX_RDSETUP_ESTATUS_ERR
, /* 0x417 */
520 DMA_RX_RAM_ECC_ERR
, /* 0x418 */
521 DMA_RX_UNKNOWN_FRM_ERR
, /* 0x419 */
524 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
526 #define DIR_NO_DATA 0
528 #define DIR_TO_DEVICE 2
529 #define DIR_RESERVED 3
531 #define SATA_PROTOCOL_NONDATA 0x1
532 #define SATA_PROTOCOL_PIO 0x2
533 #define SATA_PROTOCOL_DMA 0x4
534 #define SATA_PROTOCOL_FPDMA 0x8
535 #define SATA_PROTOCOL_ATAPI 0x10
537 static void hisi_sas_link_timeout_disable_link(unsigned long data
);
539 static u32
hisi_sas_read32(struct hisi_hba
*hisi_hba
, u32 off
)
541 void __iomem
*regs
= hisi_hba
->regs
+ off
;
546 static u32
hisi_sas_read32_relaxed(struct hisi_hba
*hisi_hba
, u32 off
)
548 void __iomem
*regs
= hisi_hba
->regs
+ off
;
550 return readl_relaxed(regs
);
553 static void hisi_sas_write32(struct hisi_hba
*hisi_hba
, u32 off
, u32 val
)
555 void __iomem
*regs
= hisi_hba
->regs
+ off
;
560 static void hisi_sas_phy_write32(struct hisi_hba
*hisi_hba
, int phy_no
,
563 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
568 static u32
hisi_sas_phy_read32(struct hisi_hba
*hisi_hba
,
571 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
576 /* This function needs to be protected from pre-emption. */
578 slot_index_alloc_quirk_v2_hw(struct hisi_hba
*hisi_hba
, int *slot_idx
,
579 struct domain_device
*device
)
581 unsigned int index
= 0;
582 void *bitmap
= hisi_hba
->slot_index_tags
;
583 int sata_dev
= dev_is_sata(device
);
586 index
= find_next_zero_bit(bitmap
, hisi_hba
->slot_index_count
,
588 if (index
>= hisi_hba
->slot_index_count
)
589 return -SAS_QUEUE_FULL
;
591 * SAS IPTT bit0 should be 1
593 if (sata_dev
|| (index
& 1))
598 set_bit(index
, bitmap
);
604 hisi_sas_device
*alloc_dev_quirk_v2_hw(struct domain_device
*device
)
606 struct hisi_hba
*hisi_hba
= device
->port
->ha
->lldd_ha
;
607 struct hisi_sas_device
*sas_dev
= NULL
;
608 int i
, sata_dev
= dev_is_sata(device
);
610 spin_lock(&hisi_hba
->lock
);
611 for (i
= 0; i
< HISI_SAS_MAX_DEVICES
; i
++) {
613 * SATA device id bit0 should be 0
615 if (sata_dev
&& (i
& 1))
617 if (hisi_hba
->devices
[i
].dev_type
== SAS_PHY_UNUSED
) {
618 hisi_hba
->devices
[i
].device_id
= i
;
619 sas_dev
= &hisi_hba
->devices
[i
];
620 sas_dev
->dev_status
= HISI_SAS_DEV_NORMAL
;
621 sas_dev
->dev_type
= device
->dev_type
;
622 sas_dev
->hisi_hba
= hisi_hba
;
623 sas_dev
->sas_device
= device
;
627 spin_unlock(&hisi_hba
->lock
);
632 static void config_phy_opt_mode_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
634 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
636 cfg
&= ~PHY_CFG_DC_OPT_MSK
;
637 cfg
|= 1 << PHY_CFG_DC_OPT_OFF
;
638 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
641 static void config_id_frame_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
643 struct sas_identify_frame identify_frame
;
644 u32
*identify_buffer
;
646 memset(&identify_frame
, 0, sizeof(identify_frame
));
647 identify_frame
.dev_type
= SAS_END_DEVICE
;
648 identify_frame
.frame_type
= 0;
649 identify_frame
._un1
= 1;
650 identify_frame
.initiator_bits
= SAS_PROTOCOL_ALL
;
651 identify_frame
.target_bits
= SAS_PROTOCOL_NONE
;
652 memcpy(&identify_frame
._un4_11
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
653 memcpy(&identify_frame
.sas_addr
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
654 identify_frame
.phy_id
= phy_no
;
655 identify_buffer
= (u32
*)(&identify_frame
);
657 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD0
,
658 __swab32(identify_buffer
[0]));
659 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD1
,
660 __swab32(identify_buffer
[1]));
661 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD2
,
662 __swab32(identify_buffer
[2]));
663 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD3
,
664 __swab32(identify_buffer
[3]));
665 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD4
,
666 __swab32(identify_buffer
[4]));
667 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD5
,
668 __swab32(identify_buffer
[5]));
671 static void setup_itct_v2_hw(struct hisi_hba
*hisi_hba
,
672 struct hisi_sas_device
*sas_dev
)
674 struct domain_device
*device
= sas_dev
->sas_device
;
675 struct device
*dev
= &hisi_hba
->pdev
->dev
;
676 u64 qw0
, device_id
= sas_dev
->device_id
;
677 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[device_id
];
678 struct domain_device
*parent_dev
= device
->parent
;
679 struct asd_sas_port
*sas_port
= device
->port
;
680 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
682 memset(itct
, 0, sizeof(*itct
));
686 switch (sas_dev
->dev_type
) {
688 case SAS_EDGE_EXPANDER_DEVICE
:
689 case SAS_FANOUT_EXPANDER_DEVICE
:
690 qw0
= HISI_SAS_DEV_TYPE_SSP
<< ITCT_HDR_DEV_TYPE_OFF
;
693 case SAS_SATA_PENDING
:
694 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
695 qw0
= HISI_SAS_DEV_TYPE_STP
<< ITCT_HDR_DEV_TYPE_OFF
;
697 qw0
= HISI_SAS_DEV_TYPE_SATA
<< ITCT_HDR_DEV_TYPE_OFF
;
700 dev_warn(dev
, "setup itct: unsupported dev type (%d)\n",
704 qw0
|= ((1 << ITCT_HDR_VALID_OFF
) |
705 (device
->linkrate
<< ITCT_HDR_MCR_OFF
) |
706 (1 << ITCT_HDR_VLN_OFF
) |
707 (ITCT_HDR_SMP_TIMEOUT
<< ITCT_HDR_SMP_TIMEOUT_OFF
) |
708 (1 << ITCT_HDR_AWT_CONTINUE_OFF
) |
709 (port
->id
<< ITCT_HDR_PORT_ID_OFF
));
710 itct
->qw0
= cpu_to_le64(qw0
);
713 memcpy(&itct
->sas_addr
, device
->sas_addr
, SAS_ADDR_SIZE
);
714 itct
->sas_addr
= __swab64(itct
->sas_addr
);
717 if (!dev_is_sata(device
))
718 itct
->qw2
= cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF
) |
719 (0x1ULL
<< ITCT_HDR_BITLT_OFF
) |
720 (0x32ULL
<< ITCT_HDR_MCTLT_OFF
) |
721 (0x1ULL
<< ITCT_HDR_RTOLT_OFF
));
724 static void free_device_v2_hw(struct hisi_hba
*hisi_hba
,
725 struct hisi_sas_device
*sas_dev
)
727 u64 dev_id
= sas_dev
->device_id
;
728 struct device
*dev
= &hisi_hba
->pdev
->dev
;
729 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[dev_id
];
730 u32 reg_val
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
733 /* clear the itct interrupt state */
734 if (ENT_INT_SRC3_ITC_INT_MSK
& reg_val
)
735 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
736 ENT_INT_SRC3_ITC_INT_MSK
);
738 /* clear the itct int*/
739 for (i
= 0; i
< 2; i
++) {
740 /* clear the itct table*/
741 reg_val
= hisi_sas_read32(hisi_hba
, ITCT_CLR
);
742 reg_val
|= ITCT_CLR_EN_MSK
| (dev_id
& ITCT_DEV_MSK
);
743 hisi_sas_write32(hisi_hba
, ITCT_CLR
, reg_val
);
746 reg_val
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
747 if (ENT_INT_SRC3_ITC_INT_MSK
& reg_val
) {
748 dev_dbg(dev
, "got clear ITCT done interrupt\n");
750 /* invalid the itct state*/
751 memset(itct
, 0, sizeof(struct hisi_sas_itct
));
752 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
753 ENT_INT_SRC3_ITC_INT_MSK
);
756 hisi_sas_write32(hisi_hba
, ITCT_CLR
, 0);
757 dev_dbg(dev
, "clear ITCT ok\n");
763 static int reset_hw_v2_hw(struct hisi_hba
*hisi_hba
)
767 unsigned long end_time
;
768 struct device
*dev
= &hisi_hba
->pdev
->dev
;
770 /* The mask needs to be set depending on the number of phys */
771 if (hisi_hba
->n_phy
== 9)
772 reset_val
= 0x1fffff;
776 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0);
778 /* Disable all of the PHYs */
779 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
780 u32 phy_cfg
= hisi_sas_phy_read32(hisi_hba
, i
, PHY_CFG
);
782 phy_cfg
&= ~PHY_CTRL_RESET_MSK
;
783 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CFG
, phy_cfg
);
787 /* Ensure DMA tx & rx idle */
788 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
789 u32 dma_tx_status
, dma_rx_status
;
791 end_time
= jiffies
+ msecs_to_jiffies(1000);
794 dma_tx_status
= hisi_sas_phy_read32(hisi_hba
, i
,
796 dma_rx_status
= hisi_sas_phy_read32(hisi_hba
, i
,
799 if (!(dma_tx_status
& DMA_TX_STATUS_BUSY_MSK
) &&
800 !(dma_rx_status
& DMA_RX_STATUS_BUSY_MSK
))
804 if (time_after(jiffies
, end_time
))
809 /* Ensure axi bus idle */
810 end_time
= jiffies
+ msecs_to_jiffies(1000);
813 hisi_sas_read32(hisi_hba
, AXI_CFG
);
819 if (time_after(jiffies
, end_time
))
823 if (ACPI_HANDLE(dev
)) {
826 s
= acpi_evaluate_object(ACPI_HANDLE(dev
), "_RST", NULL
, NULL
);
827 if (ACPI_FAILURE(s
)) {
828 dev_err(dev
, "Reset failed\n");
831 } else if (hisi_hba
->ctrl
) {
832 /* reset and disable clock*/
833 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_reg
,
835 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_clock_ena_reg
+ 4,
838 regmap_read(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_sts_reg
, &val
);
839 if (reset_val
!= (val
& reset_val
)) {
840 dev_err(dev
, "SAS reset fail.\n");
844 /* De-reset and enable clock*/
845 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_reg
+ 4,
847 regmap_write(hisi_hba
->ctrl
, hisi_hba
->ctrl_clock_ena_reg
,
850 regmap_read(hisi_hba
->ctrl
, hisi_hba
->ctrl_reset_sts_reg
,
852 if (val
& reset_val
) {
853 dev_err(dev
, "SAS de-reset fail.\n");
857 dev_warn(dev
, "no reset method\n");
862 static void init_reg_v2_hw(struct hisi_hba
*hisi_hba
)
864 struct device
*dev
= &hisi_hba
->pdev
->dev
;
867 /* Global registers init */
869 /* Deal with am-max-transmissions quirk */
870 if (device_property_present(dev
, "hip06-sas-v2-quirk-amt")) {
871 hisi_sas_write32(hisi_hba
, AM_CFG_MAX_TRANS
, 0x2020);
872 hisi_sas_write32(hisi_hba
, AM_CFG_SINGLE_PORT_MAX_TRANS
,
874 } /* Else, use defaults -> do nothing */
876 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
,
877 (u32
)((1ULL << hisi_hba
->queue_count
) - 1));
878 hisi_sas_write32(hisi_hba
, AXI_USER1
, 0xc0000000);
879 hisi_sas_write32(hisi_hba
, AXI_USER2
, 0x10000);
880 hisi_sas_write32(hisi_hba
, HGC_SAS_TXFAIL_RETRY_CTRL
, 0x108);
881 hisi_sas_write32(hisi_hba
, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL
, 0x7FF);
882 hisi_sas_write32(hisi_hba
, OPENA_WT_CONTI_TIME
, 0x1);
883 hisi_sas_write32(hisi_hba
, I_T_NEXUS_LOSS_TIME
, 0x1F4);
884 hisi_sas_write32(hisi_hba
, MAX_CON_TIME_LIMIT_TIME
, 0x32);
885 hisi_sas_write32(hisi_hba
, BUS_INACTIVE_LIMIT_TIME
, 0x1);
886 hisi_sas_write32(hisi_hba
, CFG_AGING_TIME
, 0x1);
887 hisi_sas_write32(hisi_hba
, HGC_ERR_STAT_EN
, 0x1);
888 hisi_sas_write32(hisi_hba
, HGC_GET_ITV_TIME
, 0x1);
889 hisi_sas_write32(hisi_hba
, INT_COAL_EN
, 0x1);
890 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_TIME
, 0x1);
891 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_CNT
, 0x1);
892 hisi_sas_write32(hisi_hba
, ENT_INT_COAL_TIME
, 0x1);
893 hisi_sas_write32(hisi_hba
, ENT_INT_COAL_CNT
, 0x1);
894 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 0x0);
895 hisi_sas_write32(hisi_hba
, ENT_INT_SRC1
, 0xffffffff);
896 hisi_sas_write32(hisi_hba
, ENT_INT_SRC2
, 0xffffffff);
897 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
, 0xffffffff);
898 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0x7efefefe);
899 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0x7efefefe);
900 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0x7ffffffe);
901 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0xfff00c30);
902 for (i
= 0; i
< hisi_hba
->queue_count
; i
++)
903 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+0x4*i
, 0);
905 hisi_sas_write32(hisi_hba
, AXI_AHB_CLK_CFG
, 1);
906 hisi_sas_write32(hisi_hba
, HYPER_STREAM_ID_EN_CFG
, 1);
908 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
909 hisi_sas_phy_write32(hisi_hba
, i
, PROG_PHY_LINK_RATE
, 0x855);
910 hisi_sas_phy_write32(hisi_hba
, i
, SAS_PHY_CTRL
, 0x30b9908);
911 hisi_sas_phy_write32(hisi_hba
, i
, SL_TOUT_CFG
, 0x7d7d7d7d);
912 hisi_sas_phy_write32(hisi_hba
, i
, SL_CONTROL
, 0x0);
913 hisi_sas_phy_write32(hisi_hba
, i
, TXID_AUTO
, 0x2);
914 hisi_sas_phy_write32(hisi_hba
, i
, DONE_RECEIVED_TIME
, 0x10);
915 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT0
, 0xffffffff);
916 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1
, 0xffffffff);
917 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2
, 0xfff87fff);
918 hisi_sas_phy_write32(hisi_hba
, i
, RXOP_CHECK_CFG_H
, 0x1000);
919 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xffffffff);
920 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0x8ffffbff);
921 hisi_sas_phy_write32(hisi_hba
, i
, SL_CFG
, 0x23f801fc);
922 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL_RDY_MSK
, 0x0);
923 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_NOT_RDY_MSK
, 0x0);
924 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_DWS_RESET_MSK
, 0x0);
925 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_PHY_ENA_MSK
, 0x0);
926 hisi_sas_phy_write32(hisi_hba
, i
, SL_RX_BCAST_CHK_MSK
, 0x0);
927 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT_COAL_EN
, 0x0);
928 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_OOB_RESTART_MSK
, 0x0);
929 if (hisi_hba
->refclk_frequency_mhz
== 66)
930 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL
, 0x199B694);
931 /* else, do nothing -> leave it how you found it */
934 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
936 hisi_sas_write32(hisi_hba
,
937 DLVRY_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
938 upper_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
940 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
941 lower_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
943 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_DEPTH
+ (i
* 0x14),
944 HISI_SAS_QUEUE_SLOTS
);
946 /* Completion queue */
947 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
948 upper_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
950 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
951 lower_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
953 hisi_sas_write32(hisi_hba
, COMPL_Q_0_DEPTH
+ (i
* 0x14),
954 HISI_SAS_QUEUE_SLOTS
);
958 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_LO
,
959 lower_32_bits(hisi_hba
->itct_dma
));
961 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_HI
,
962 upper_32_bits(hisi_hba
->itct_dma
));
965 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_LO
,
966 lower_32_bits(hisi_hba
->iost_dma
));
968 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_HI
,
969 upper_32_bits(hisi_hba
->iost_dma
));
972 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_LO
,
973 lower_32_bits(hisi_hba
->breakpoint_dma
));
975 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_HI
,
976 upper_32_bits(hisi_hba
->breakpoint_dma
));
978 /* SATA broken msg */
979 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_LO
,
980 lower_32_bits(hisi_hba
->sata_breakpoint_dma
));
982 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_HI
,
983 upper_32_bits(hisi_hba
->sata_breakpoint_dma
));
985 /* SATA initial fis */
986 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_LO
,
987 lower_32_bits(hisi_hba
->initial_fis_dma
));
989 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_HI
,
990 upper_32_bits(hisi_hba
->initial_fis_dma
));
993 static void hisi_sas_link_timeout_enable_link(unsigned long data
)
995 struct hisi_hba
*hisi_hba
= (struct hisi_hba
*)data
;
998 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
999 reg_val
= hisi_sas_phy_read32(hisi_hba
, i
, CON_CONTROL
);
1000 if (!(reg_val
& BIT(0))) {
1001 hisi_sas_phy_write32(hisi_hba
, i
,
1007 hisi_hba
->timer
.function
= hisi_sas_link_timeout_disable_link
;
1008 mod_timer(&hisi_hba
->timer
, jiffies
+ msecs_to_jiffies(900));
1011 static void hisi_sas_link_timeout_disable_link(unsigned long data
)
1013 struct hisi_hba
*hisi_hba
= (struct hisi_hba
*)data
;
1016 reg_val
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1017 for (i
= 0; i
< hisi_hba
->n_phy
&& reg_val
; i
++) {
1018 if (reg_val
& BIT(i
)) {
1019 hisi_sas_phy_write32(hisi_hba
, i
,
1025 hisi_hba
->timer
.function
= hisi_sas_link_timeout_enable_link
;
1026 mod_timer(&hisi_hba
->timer
, jiffies
+ msecs_to_jiffies(100));
1029 static void set_link_timer_quirk(struct hisi_hba
*hisi_hba
)
1031 hisi_hba
->timer
.data
= (unsigned long)hisi_hba
;
1032 hisi_hba
->timer
.function
= hisi_sas_link_timeout_disable_link
;
1033 hisi_hba
->timer
.expires
= jiffies
+ msecs_to_jiffies(1000);
1034 add_timer(&hisi_hba
->timer
);
1037 static int hw_init_v2_hw(struct hisi_hba
*hisi_hba
)
1039 struct device
*dev
= &hisi_hba
->pdev
->dev
;
1042 rc
= reset_hw_v2_hw(hisi_hba
);
1044 dev_err(dev
, "hisi_sas_reset_hw failed, rc=%d", rc
);
1049 init_reg_v2_hw(hisi_hba
);
1054 static void enable_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1056 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
1058 cfg
|= PHY_CFG_ENA_MSK
;
1059 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
1062 static void disable_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1064 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
1066 cfg
&= ~PHY_CFG_ENA_MSK
;
1067 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
1070 static void start_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1072 config_id_frame_v2_hw(hisi_hba
, phy_no
);
1073 config_phy_opt_mode_v2_hw(hisi_hba
, phy_no
);
1074 enable_phy_v2_hw(hisi_hba
, phy_no
);
1077 static void stop_phy_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1079 disable_phy_v2_hw(hisi_hba
, phy_no
);
1082 static void phy_hard_reset_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1084 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1087 stop_phy_v2_hw(hisi_hba
, phy_no
);
1088 if (phy
->identify
.device_type
== SAS_END_DEVICE
) {
1089 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
1090 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
1091 txid_auto
| TX_HARDRST_MSK
);
1094 start_phy_v2_hw(hisi_hba
, phy_no
);
1097 static void start_phys_v2_hw(struct hisi_hba
*hisi_hba
)
1101 for (i
= 0; i
< hisi_hba
->n_phy
; i
++)
1102 start_phy_v2_hw(hisi_hba
, i
);
1105 static void phys_init_v2_hw(struct hisi_hba
*hisi_hba
)
1107 start_phys_v2_hw(hisi_hba
);
1110 static void sl_notify_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1114 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
1115 sl_control
|= SL_CONTROL_NOTIFY_EN_MSK
;
1116 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
1118 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
1119 sl_control
&= ~SL_CONTROL_NOTIFY_EN_MSK
;
1120 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
1123 static enum sas_linkrate
phy_get_max_linkrate_v2_hw(void)
1125 return SAS_LINK_RATE_12_0_GBPS
;
1128 static void phy_set_linkrate_v2_hw(struct hisi_hba
*hisi_hba
, int phy_no
,
1129 struct sas_phy_linkrates
*r
)
1131 u32 prog_phy_link_rate
=
1132 hisi_sas_phy_read32(hisi_hba
, phy_no
, PROG_PHY_LINK_RATE
);
1133 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1134 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1136 enum sas_linkrate min
, max
;
1139 if (r
->maximum_linkrate
== SAS_LINK_RATE_UNKNOWN
) {
1140 max
= sas_phy
->phy
->maximum_linkrate
;
1141 min
= r
->minimum_linkrate
;
1142 } else if (r
->minimum_linkrate
== SAS_LINK_RATE_UNKNOWN
) {
1143 max
= r
->maximum_linkrate
;
1144 min
= sas_phy
->phy
->minimum_linkrate
;
1148 sas_phy
->phy
->maximum_linkrate
= max
;
1149 sas_phy
->phy
->minimum_linkrate
= min
;
1151 min
-= SAS_LINK_RATE_1_5_GBPS
;
1152 max
-= SAS_LINK_RATE_1_5_GBPS
;
1154 for (i
= 0; i
<= max
; i
++)
1155 rate_mask
|= 1 << (i
* 2);
1157 prog_phy_link_rate
&= ~0xff;
1158 prog_phy_link_rate
|= rate_mask
;
1160 hisi_sas_phy_write32(hisi_hba
, phy_no
, PROG_PHY_LINK_RATE
,
1161 prog_phy_link_rate
);
1163 phy_hard_reset_v2_hw(hisi_hba
, phy_no
);
1166 static int get_wideport_bitmap_v2_hw(struct hisi_hba
*hisi_hba
, int port_id
)
1169 u32 phy_port_num_ma
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
1170 u32 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1172 for (i
= 0; i
< (hisi_hba
->n_phy
< 9 ? hisi_hba
->n_phy
: 8); i
++)
1173 if (phy_state
& 1 << i
)
1174 if (((phy_port_num_ma
>> (i
* 4)) & 0xf) == port_id
)
1177 if (hisi_hba
->n_phy
== 9) {
1178 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
1180 if (phy_state
& 1 << 8)
1181 if (((port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
1182 PORT_STATE_PHY8_PORT_NUM_OFF
) == port_id
)
1190 * This function allocates across all queues to load balance.
1191 * Slots are allocated from queues in a round-robin fashion.
1193 * The callpath to this function and upto writing the write
1194 * queue pointer should be safe from interruption.
1196 static int get_free_slot_v2_hw(struct hisi_hba
*hisi_hba
, u32 dev_id
,
1199 struct device
*dev
= &hisi_hba
->pdev
->dev
;
1200 struct hisi_sas_dq
*dq
;
1202 int queue
= dev_id
% hisi_hba
->queue_count
;
1204 dq
= &hisi_hba
->dq
[queue
];
1206 r
= hisi_sas_read32_relaxed(hisi_hba
,
1207 DLVRY_Q_0_RD_PTR
+ (queue
* 0x14));
1208 if (r
== (w
+1) % HISI_SAS_QUEUE_SLOTS
) {
1209 dev_warn(dev
, "full queue=%d r=%d w=%d\n\n",
1219 static void start_delivery_v2_hw(struct hisi_hba
*hisi_hba
)
1221 int dlvry_queue
= hisi_hba
->slot_prep
->dlvry_queue
;
1222 int dlvry_queue_slot
= hisi_hba
->slot_prep
->dlvry_queue_slot
;
1223 struct hisi_sas_dq
*dq
= &hisi_hba
->dq
[dlvry_queue
];
1225 dq
->wr_point
= ++dlvry_queue_slot
% HISI_SAS_QUEUE_SLOTS
;
1226 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_WR_PTR
+ (dlvry_queue
* 0x14),
1230 static int prep_prd_sge_v2_hw(struct hisi_hba
*hisi_hba
,
1231 struct hisi_sas_slot
*slot
,
1232 struct hisi_sas_cmd_hdr
*hdr
,
1233 struct scatterlist
*scatter
,
1236 struct device
*dev
= &hisi_hba
->pdev
->dev
;
1237 struct scatterlist
*sg
;
1240 if (n_elem
> HISI_SAS_SGE_PAGE_CNT
) {
1241 dev_err(dev
, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1246 slot
->sge_page
= dma_pool_alloc(hisi_hba
->sge_page_pool
, GFP_ATOMIC
,
1247 &slot
->sge_page_dma
);
1248 if (!slot
->sge_page
)
1251 for_each_sg(scatter
, sg
, n_elem
, i
) {
1252 struct hisi_sas_sge
*entry
= &slot
->sge_page
->sge
[i
];
1254 entry
->addr
= cpu_to_le64(sg_dma_address(sg
));
1255 entry
->page_ctrl_0
= entry
->page_ctrl_1
= 0;
1256 entry
->data_len
= cpu_to_le32(sg_dma_len(sg
));
1257 entry
->data_off
= 0;
1260 hdr
->prd_table_addr
= cpu_to_le64(slot
->sge_page_dma
);
1262 hdr
->sg_len
= cpu_to_le32(n_elem
<< CMD_HDR_DATA_SGL_LEN_OFF
);
1267 static int prep_smp_v2_hw(struct hisi_hba
*hisi_hba
,
1268 struct hisi_sas_slot
*slot
)
1270 struct sas_task
*task
= slot
->task
;
1271 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1272 struct domain_device
*device
= task
->dev
;
1273 struct device
*dev
= &hisi_hba
->pdev
->dev
;
1274 struct hisi_sas_port
*port
= slot
->port
;
1275 struct scatterlist
*sg_req
, *sg_resp
;
1276 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
1277 dma_addr_t req_dma_addr
;
1278 unsigned int req_len
, resp_len
;
1282 * DMA-map SMP request, response buffers
1285 sg_req
= &task
->smp_task
.smp_req
;
1286 elem
= dma_map_sg(dev
, sg_req
, 1, DMA_TO_DEVICE
);
1289 req_len
= sg_dma_len(sg_req
);
1290 req_dma_addr
= sg_dma_address(sg_req
);
1293 sg_resp
= &task
->smp_task
.smp_resp
;
1294 elem
= dma_map_sg(dev
, sg_resp
, 1, DMA_FROM_DEVICE
);
1299 resp_len
= sg_dma_len(sg_resp
);
1300 if ((req_len
& 0x3) || (resp_len
& 0x3)) {
1307 hdr
->dw0
= cpu_to_le32((port
->id
<< CMD_HDR_PORT_OFF
) |
1308 (1 << CMD_HDR_PRIORITY_OFF
) | /* high pri */
1309 (2 << CMD_HDR_CMD_OFF
)); /* smp */
1311 /* map itct entry */
1312 hdr
->dw1
= cpu_to_le32((sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
) |
1313 (1 << CMD_HDR_FRAME_TYPE_OFF
) |
1314 (DIR_NO_DATA
<< CMD_HDR_DIR_OFF
));
1317 hdr
->dw2
= cpu_to_le32((((req_len
- 4) / 4) << CMD_HDR_CFL_OFF
) |
1318 (HISI_SAS_MAX_SMP_RESP_SZ
/ 4 <<
1321 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
<< CMD_HDR_IPTT_OFF
);
1323 hdr
->cmd_table_addr
= cpu_to_le64(req_dma_addr
);
1324 hdr
->sts_buffer_addr
= cpu_to_le64(slot
->status_buffer_dma
);
1329 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_resp
, 1,
1332 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_req
, 1,
1337 static int prep_ssp_v2_hw(struct hisi_hba
*hisi_hba
,
1338 struct hisi_sas_slot
*slot
, int is_tmf
,
1339 struct hisi_sas_tmf_task
*tmf
)
1341 struct sas_task
*task
= slot
->task
;
1342 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1343 struct domain_device
*device
= task
->dev
;
1344 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
1345 struct hisi_sas_port
*port
= slot
->port
;
1346 struct sas_ssp_task
*ssp_task
= &task
->ssp_task
;
1347 struct scsi_cmnd
*scsi_cmnd
= ssp_task
->cmd
;
1348 int has_data
= 0, rc
, priority
= is_tmf
;
1350 u32 dw1
= 0, dw2
= 0;
1352 hdr
->dw0
= cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF
) |
1353 (2 << CMD_HDR_TLR_CTRL_OFF
) |
1354 (port
->id
<< CMD_HDR_PORT_OFF
) |
1355 (priority
<< CMD_HDR_PRIORITY_OFF
) |
1356 (1 << CMD_HDR_CMD_OFF
)); /* ssp */
1358 dw1
= 1 << CMD_HDR_VDTL_OFF
;
1360 dw1
|= 2 << CMD_HDR_FRAME_TYPE_OFF
;
1361 dw1
|= DIR_NO_DATA
<< CMD_HDR_DIR_OFF
;
1363 dw1
|= 1 << CMD_HDR_FRAME_TYPE_OFF
;
1364 switch (scsi_cmnd
->sc_data_direction
) {
1367 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
1369 case DMA_FROM_DEVICE
:
1371 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
1374 dw1
&= ~CMD_HDR_DIR_MSK
;
1378 /* map itct entry */
1379 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
1380 hdr
->dw1
= cpu_to_le32(dw1
);
1382 dw2
= (((sizeof(struct ssp_command_iu
) + sizeof(struct ssp_frame_hdr
)
1383 + 3) / 4) << CMD_HDR_CFL_OFF
) |
1384 ((HISI_SAS_MAX_SSP_RESP_SZ
/ 4) << CMD_HDR_MRFL_OFF
) |
1385 (2 << CMD_HDR_SG_MOD_OFF
);
1386 hdr
->dw2
= cpu_to_le32(dw2
);
1388 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
1391 rc
= prep_prd_sge_v2_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
1397 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
1398 hdr
->cmd_table_addr
= cpu_to_le64(slot
->command_table_dma
);
1399 hdr
->sts_buffer_addr
= cpu_to_le64(slot
->status_buffer_dma
);
1401 buf_cmd
= slot
->command_table
+ sizeof(struct ssp_frame_hdr
);
1403 memcpy(buf_cmd
, &task
->ssp_task
.LUN
, 8);
1405 buf_cmd
[9] = task
->ssp_task
.task_attr
|
1406 (task
->ssp_task
.task_prio
<< 3);
1407 memcpy(buf_cmd
+ 12, task
->ssp_task
.cmd
->cmnd
,
1408 task
->ssp_task
.cmd
->cmd_len
);
1410 buf_cmd
[10] = tmf
->tmf
;
1412 case TMF_ABORT_TASK
:
1413 case TMF_QUERY_TASK
:
1415 (tmf
->tag_of_task_to_be_managed
>> 8) & 0xff;
1417 tmf
->tag_of_task_to_be_managed
& 0xff;
1427 static void sata_done_v2_hw(struct hisi_hba
*hisi_hba
, struct sas_task
*task
,
1428 struct hisi_sas_slot
*slot
)
1430 struct task_status_struct
*ts
= &task
->task_status
;
1431 struct ata_task_resp
*resp
= (struct ata_task_resp
*)ts
->buf
;
1432 struct dev_to_host_fis
*d2h
= slot
->status_buffer
+
1433 sizeof(struct hisi_sas_err_record
);
1435 resp
->frame_len
= sizeof(struct dev_to_host_fis
);
1436 memcpy(&resp
->ending_fis
[0], d2h
, sizeof(struct dev_to_host_fis
));
1438 ts
->buf_valid_size
= sizeof(*resp
);
1441 /* by default, task resp is complete */
1442 static void slot_err_v2_hw(struct hisi_hba
*hisi_hba
,
1443 struct sas_task
*task
,
1444 struct hisi_sas_slot
*slot
)
1446 struct task_status_struct
*ts
= &task
->task_status
;
1447 struct hisi_sas_err_record_v2
*err_record
= slot
->status_buffer
;
1448 u32 trans_tx_fail_type
= cpu_to_le32(err_record
->trans_tx_fail_type
);
1449 u32 trans_rx_fail_type
= cpu_to_le32(err_record
->trans_rx_fail_type
);
1450 u16 dma_tx_err_type
= cpu_to_le16(err_record
->dma_tx_err_type
);
1451 u16 sipc_rx_err_type
= cpu_to_le16(err_record
->sipc_rx_err_type
);
1452 u32 dma_rx_err_type
= cpu_to_le32(err_record
->dma_rx_err_type
);
1455 if (dma_rx_err_type
) {
1456 error
= ffs(dma_rx_err_type
)
1457 - 1 + DMA_RX_ERR_BASE
;
1458 } else if (sipc_rx_err_type
) {
1459 error
= ffs(sipc_rx_err_type
)
1460 - 1 + SIPC_RX_ERR_BASE
;
1461 } else if (dma_tx_err_type
) {
1462 error
= ffs(dma_tx_err_type
)
1463 - 1 + DMA_TX_ERR_BASE
;
1464 } else if (trans_rx_fail_type
) {
1465 error
= ffs(trans_rx_fail_type
)
1466 - 1 + TRANS_RX_FAIL_BASE
;
1467 } else if (trans_tx_fail_type
) {
1468 error
= ffs(trans_tx_fail_type
)
1469 - 1 + TRANS_TX_FAIL_BASE
;
1472 switch (task
->task_proto
) {
1473 case SAS_PROTOCOL_SSP
:
1476 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
:
1478 ts
->stat
= SAS_OPEN_REJECT
;
1479 ts
->open_rej_reason
= SAS_OREJ_NO_DEST
;
1482 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
:
1484 ts
->stat
= SAS_OPEN_REJECT
;
1485 ts
->open_rej_reason
= SAS_OREJ_PATH_BLOCKED
;
1488 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
:
1490 ts
->stat
= SAS_OPEN_REJECT
;
1491 ts
->open_rej_reason
= SAS_OREJ_EPROTO
;
1494 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
:
1496 ts
->stat
= SAS_OPEN_REJECT
;
1497 ts
->open_rej_reason
= SAS_OREJ_CONN_RATE
;
1500 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
:
1502 ts
->stat
= SAS_OPEN_REJECT
;
1503 ts
->open_rej_reason
= SAS_OREJ_BAD_DEST
;
1506 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
:
1508 ts
->stat
= SAS_OPEN_REJECT
;
1509 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
1512 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
:
1514 ts
->stat
= SAS_OPEN_REJECT
;
1515 ts
->open_rej_reason
= SAS_OREJ_WRONG_DEST
;
1518 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
:
1520 ts
->stat
= SAS_OPEN_REJECT
;
1521 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
1524 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
:
1527 ts
->stat
= SAS_DEV_NO_RESPONSE
;
1530 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
:
1532 ts
->stat
= SAS_PHY_DOWN
;
1535 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
:
1537 ts
->stat
= SAS_OPEN_TO
;
1540 case DMA_RX_DATA_LEN_OVERFLOW
:
1542 ts
->stat
= SAS_DATA_OVERRUN
;
1546 case DMA_RX_DATA_LEN_UNDERFLOW
:
1547 case SIPC_RX_DATA_UNDERFLOW_ERR
:
1549 ts
->residual
= trans_tx_fail_type
;
1550 ts
->stat
= SAS_DATA_UNDERRUN
;
1553 case TRANS_TX_ERR_FRAME_TXED
:
1555 /* This will request a retry */
1556 ts
->stat
= SAS_QUEUE_FULL
;
1560 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
:
1561 case TRANS_TX_ERR_PHY_NOT_ENABLE
:
1562 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER
:
1563 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
:
1564 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
:
1565 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT
:
1566 case TRANS_TX_ERR_WITH_BREAK_REQUEST
:
1567 case TRANS_TX_ERR_WITH_BREAK_RECEVIED
:
1568 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
:
1569 case TRANS_TX_ERR_WITH_CLOSE_NORMAL
:
1570 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
1571 case TRANS_TX_ERR_WITH_CLOSE_COMINIT
:
1572 case TRANS_TX_ERR_WITH_NAK_RECEVIED
:
1573 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
:
1574 case TRANS_TX_ERR_WITH_IPTT_CONFLICT
:
1575 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
:
1576 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
:
1577 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
:
1578 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
:
1579 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT
:
1580 case TRANS_RX_ERR_WITH_BREAK_REQUEST
:
1581 case TRANS_RX_ERR_WITH_BREAK_RECEVIED
:
1582 case TRANS_RX_ERR_WITH_CLOSE_NORMAL
:
1583 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
1584 case TRANS_RX_ERR_WITH_CLOSE_COMINIT
:
1585 case TRANS_RX_ERR_WITH_DATA_LEN0
:
1586 case TRANS_RX_ERR_WITH_BAD_HASH
:
1587 case TRANS_RX_XRDY_WLEN_ZERO_ERR
:
1588 case TRANS_RX_SSP_FRM_LEN_ERR
:
1589 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE
:
1590 case DMA_TX_UNEXP_XFER_ERR
:
1591 case DMA_TX_UNEXP_RETRANS_ERR
:
1592 case DMA_TX_XFER_LEN_OVERFLOW
:
1593 case DMA_TX_XFER_OFFSET_ERR
:
1594 case DMA_RX_DATA_OFFSET_ERR
:
1595 case DMA_RX_UNEXP_NORM_RESP_ERR
:
1596 case DMA_RX_UNEXP_RDFRAME_ERR
:
1597 case DMA_RX_UNKNOWN_FRM_ERR
:
1599 ts
->stat
= SAS_OPEN_REJECT
;
1600 ts
->open_rej_reason
= SAS_OREJ_UNKNOWN
;
1608 case SAS_PROTOCOL_SMP
:
1609 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
1612 case SAS_PROTOCOL_SATA
:
1613 case SAS_PROTOCOL_STP
:
1614 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
1617 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
:
1618 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
:
1619 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
:
1621 ts
->resp
= SAS_TASK_UNDELIVERED
;
1622 ts
->stat
= SAS_DEV_NO_RESPONSE
;
1625 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
:
1626 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
:
1627 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
:
1628 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
:
1629 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
:
1630 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
:
1631 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
:
1633 ts
->stat
= SAS_OPEN_REJECT
;
1636 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
:
1638 ts
->stat
= SAS_OPEN_TO
;
1641 case DMA_RX_DATA_LEN_OVERFLOW
:
1643 ts
->stat
= SAS_DATA_OVERRUN
;
1646 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
:
1647 case TRANS_TX_ERR_PHY_NOT_ENABLE
:
1648 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER
:
1649 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
:
1650 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
:
1651 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT
:
1652 case TRANS_TX_ERR_WITH_BREAK_REQUEST
:
1653 case TRANS_TX_ERR_WITH_BREAK_RECEVIED
:
1654 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
:
1655 case TRANS_TX_ERR_WITH_CLOSE_NORMAL
:
1656 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
1657 case TRANS_TX_ERR_WITH_CLOSE_COMINIT
:
1658 case TRANS_TX_ERR_WITH_NAK_RECEVIED
:
1659 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
:
1660 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
:
1661 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
:
1662 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
:
1663 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
:
1664 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
:
1665 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
:
1666 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
:
1667 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
:
1668 case TRANS_RX_ERR_WITH_CLOSE_NORMAL
:
1669 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
:
1670 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
:
1671 case TRANS_RX_ERR_WITH_CLOSE_COMINIT
:
1672 case TRANS_RX_ERR_WITH_DATA_LEN0
:
1673 case TRANS_RX_ERR_WITH_BAD_HASH
:
1674 case TRANS_RX_XRDY_WLEN_ZERO_ERR
:
1675 case TRANS_RX_SSP_FRM_LEN_ERR
:
1676 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD
:
1677 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR
:
1678 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR
:
1679 case SIPC_RX_WRSETUP_LEN_ODD_ERR
:
1680 case SIPC_RX_WRSETUP_LEN_ZERO_ERR
:
1681 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR
:
1682 case SIPC_RX_SATA_UNEXP_FIS_ERR
:
1683 case DMA_RX_SATA_FRAME_TYPE_ERR
:
1684 case DMA_RX_UNEXP_RDFRAME_ERR
:
1685 case DMA_RX_PIO_DATA_LEN_ERR
:
1686 case DMA_RX_RDSETUP_STATUS_ERR
:
1687 case DMA_RX_RDSETUP_STATUS_DRQ_ERR
:
1688 case DMA_RX_RDSETUP_STATUS_BSY_ERR
:
1689 case DMA_RX_RDSETUP_LEN_ODD_ERR
:
1690 case DMA_RX_RDSETUP_LEN_ZERO_ERR
:
1691 case DMA_RX_RDSETUP_LEN_OVER_ERR
:
1692 case DMA_RX_RDSETUP_OFFSET_ERR
:
1693 case DMA_RX_RDSETUP_ACTIVE_ERR
:
1694 case DMA_RX_RDSETUP_ESTATUS_ERR
:
1695 case DMA_RX_UNKNOWN_FRM_ERR
:
1697 ts
->stat
= SAS_OPEN_REJECT
;
1702 ts
->stat
= SAS_PROTO_RESPONSE
;
1706 sata_done_v2_hw(hisi_hba
, task
, slot
);
1715 slot_complete_v2_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_slot
*slot
,
1718 struct sas_task
*task
= slot
->task
;
1719 struct hisi_sas_device
*sas_dev
;
1720 struct device
*dev
= &hisi_hba
->pdev
->dev
;
1721 struct task_status_struct
*ts
;
1722 struct domain_device
*device
;
1723 enum exec_status sts
;
1724 struct hisi_sas_complete_v2_hdr
*complete_queue
=
1725 hisi_hba
->complete_hdr
[slot
->cmplt_queue
];
1726 struct hisi_sas_complete_v2_hdr
*complete_hdr
=
1727 &complete_queue
[slot
->cmplt_queue_slot
];
1729 if (unlikely(!task
|| !task
->lldd_task
|| !task
->dev
))
1732 ts
= &task
->task_status
;
1734 sas_dev
= device
->lldd_dev
;
1736 task
->task_state_flags
&=
1737 ~(SAS_TASK_STATE_PENDING
| SAS_TASK_AT_INITIATOR
);
1738 task
->task_state_flags
|= SAS_TASK_STATE_DONE
;
1740 memset(ts
, 0, sizeof(*ts
));
1741 ts
->resp
= SAS_TASK_COMPLETE
;
1743 if (unlikely(!sas_dev
|| abort
)) {
1745 dev_dbg(dev
, "slot complete: port has not device\n");
1746 ts
->stat
= SAS_PHY_DOWN
;
1750 /* Use SAS+TMF status codes */
1751 switch ((complete_hdr
->dw0
& CMPLT_HDR_ABORT_STAT_MSK
)
1752 >> CMPLT_HDR_ABORT_STAT_OFF
) {
1753 case STAT_IO_ABORTED
:
1754 /* this io has been aborted by abort command */
1755 ts
->stat
= SAS_ABORTED_TASK
;
1757 case STAT_IO_COMPLETE
:
1758 /* internal abort command complete */
1759 ts
->stat
= TMF_RESP_FUNC_COMPLETE
;
1761 case STAT_IO_NO_DEVICE
:
1762 ts
->stat
= TMF_RESP_FUNC_COMPLETE
;
1764 case STAT_IO_NOT_VALID
:
1765 /* abort single io, controller don't find
1766 * the io need to abort
1768 ts
->stat
= TMF_RESP_FUNC_FAILED
;
1774 if ((complete_hdr
->dw0
& CMPLT_HDR_ERX_MSK
) &&
1775 (!(complete_hdr
->dw0
& CMPLT_HDR_RSPNS_XFRD_MSK
))) {
1777 slot_err_v2_hw(hisi_hba
, task
, slot
);
1778 if (unlikely(slot
->abort
)) {
1779 queue_work(hisi_hba
->wq
, &slot
->abort_slot
);
1780 /* immediately return and do not complete */
1786 switch (task
->task_proto
) {
1787 case SAS_PROTOCOL_SSP
:
1789 struct ssp_response_iu
*iu
= slot
->status_buffer
+
1790 sizeof(struct hisi_sas_err_record
);
1792 sas_ssp_task_response(dev
, task
, iu
);
1795 case SAS_PROTOCOL_SMP
:
1797 struct scatterlist
*sg_resp
= &task
->smp_task
.smp_resp
;
1800 ts
->stat
= SAM_STAT_GOOD
;
1801 to
= kmap_atomic(sg_page(sg_resp
));
1803 dma_unmap_sg(dev
, &task
->smp_task
.smp_resp
, 1,
1805 dma_unmap_sg(dev
, &task
->smp_task
.smp_req
, 1,
1807 memcpy(to
+ sg_resp
->offset
,
1808 slot
->status_buffer
+
1809 sizeof(struct hisi_sas_err_record
),
1810 sg_dma_len(sg_resp
));
1814 case SAS_PROTOCOL_SATA
:
1815 case SAS_PROTOCOL_STP
:
1816 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
1818 ts
->stat
= SAM_STAT_GOOD
;
1819 sata_done_v2_hw(hisi_hba
, task
, slot
);
1823 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
1827 if (!slot
->port
->port_attached
) {
1828 dev_err(dev
, "slot complete: port %d has removed\n",
1829 slot
->port
->sas_port
.id
);
1830 ts
->stat
= SAS_PHY_DOWN
;
1835 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
1838 if (task
->task_done
)
1839 task
->task_done(task
);
1844 static u8
get_ata_protocol(u8 cmd
, int direction
)
1847 case ATA_CMD_FPDMA_WRITE
:
1848 case ATA_CMD_FPDMA_READ
:
1849 case ATA_CMD_FPDMA_RECV
:
1850 case ATA_CMD_FPDMA_SEND
:
1851 case ATA_CMD_NCQ_NON_DATA
:
1852 return SATA_PROTOCOL_FPDMA
;
1854 case ATA_CMD_DOWNLOAD_MICRO
:
1855 case ATA_CMD_ID_ATA
:
1856 case ATA_CMD_PMP_READ
:
1857 case ATA_CMD_READ_LOG_EXT
:
1858 case ATA_CMD_PIO_READ
:
1859 case ATA_CMD_PIO_READ_EXT
:
1860 case ATA_CMD_PMP_WRITE
:
1861 case ATA_CMD_WRITE_LOG_EXT
:
1862 case ATA_CMD_PIO_WRITE
:
1863 case ATA_CMD_PIO_WRITE_EXT
:
1864 return SATA_PROTOCOL_PIO
;
1867 case ATA_CMD_DOWNLOAD_MICRO_DMA
:
1868 case ATA_CMD_PMP_READ_DMA
:
1869 case ATA_CMD_PMP_WRITE_DMA
:
1871 case ATA_CMD_READ_EXT
:
1872 case ATA_CMD_READ_LOG_DMA_EXT
:
1873 case ATA_CMD_READ_STREAM_DMA_EXT
:
1874 case ATA_CMD_TRUSTED_RCV_DMA
:
1875 case ATA_CMD_TRUSTED_SND_DMA
:
1877 case ATA_CMD_WRITE_EXT
:
1878 case ATA_CMD_WRITE_FUA_EXT
:
1879 case ATA_CMD_WRITE_QUEUED
:
1880 case ATA_CMD_WRITE_LOG_DMA_EXT
:
1881 case ATA_CMD_WRITE_STREAM_DMA_EXT
:
1882 return SATA_PROTOCOL_DMA
;
1884 case ATA_CMD_CHK_POWER
:
1885 case ATA_CMD_DEV_RESET
:
1888 case ATA_CMD_FLUSH_EXT
:
1889 case ATA_CMD_VERIFY
:
1890 case ATA_CMD_VERIFY_EXT
:
1891 case ATA_CMD_SET_FEATURES
:
1892 case ATA_CMD_STANDBY
:
1893 case ATA_CMD_STANDBYNOW1
:
1894 return SATA_PROTOCOL_NONDATA
;
1896 if (direction
== DMA_NONE
)
1897 return SATA_PROTOCOL_NONDATA
;
1898 return SATA_PROTOCOL_PIO
;
1902 static int get_ncq_tag_v2_hw(struct sas_task
*task
, u32
*tag
)
1904 struct ata_queued_cmd
*qc
= task
->uldd_task
;
1907 if (qc
->tf
.command
== ATA_CMD_FPDMA_WRITE
||
1908 qc
->tf
.command
== ATA_CMD_FPDMA_READ
) {
1916 static int prep_ata_v2_hw(struct hisi_hba
*hisi_hba
,
1917 struct hisi_sas_slot
*slot
)
1919 struct sas_task
*task
= slot
->task
;
1920 struct domain_device
*device
= task
->dev
;
1921 struct domain_device
*parent_dev
= device
->parent
;
1922 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
1923 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1924 struct asd_sas_port
*sas_port
= device
->port
;
1925 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
1927 int has_data
= 0, rc
= 0, hdr_tag
= 0;
1928 u32 dw1
= 0, dw2
= 0;
1932 hdr
->dw0
= cpu_to_le32(port
->id
<< CMD_HDR_PORT_OFF
);
1933 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
1934 hdr
->dw0
|= cpu_to_le32(3 << CMD_HDR_CMD_OFF
);
1936 hdr
->dw0
|= cpu_to_le32(4 << CMD_HDR_CMD_OFF
);
1939 switch (task
->data_dir
) {
1942 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
1944 case DMA_FROM_DEVICE
:
1946 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
1949 dw1
&= ~CMD_HDR_DIR_MSK
;
1952 if (0 == task
->ata_task
.fis
.command
)
1953 dw1
|= 1 << CMD_HDR_RESET_OFF
;
1955 dw1
|= (get_ata_protocol(task
->ata_task
.fis
.command
, task
->data_dir
))
1956 << CMD_HDR_FRAME_TYPE_OFF
;
1957 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
1958 hdr
->dw1
= cpu_to_le32(dw1
);
1961 if (task
->ata_task
.use_ncq
&& get_ncq_tag_v2_hw(task
, &hdr_tag
)) {
1962 task
->ata_task
.fis
.sector_count
|= (u8
) (hdr_tag
<< 3);
1963 dw2
|= hdr_tag
<< CMD_HDR_NCQ_TAG_OFF
;
1966 dw2
|= (HISI_SAS_MAX_STP_RESP_SZ
/ 4) << CMD_HDR_CFL_OFF
|
1967 2 << CMD_HDR_SG_MOD_OFF
;
1968 hdr
->dw2
= cpu_to_le32(dw2
);
1971 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
1974 rc
= prep_prd_sge_v2_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
1981 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
1982 hdr
->cmd_table_addr
= cpu_to_le64(slot
->command_table_dma
);
1983 hdr
->sts_buffer_addr
= cpu_to_le64(slot
->status_buffer_dma
);
1985 buf_cmd
= slot
->command_table
;
1987 if (likely(!task
->ata_task
.device_control_reg_update
))
1988 task
->ata_task
.fis
.flags
|= 0x80; /* C=1: update ATA cmd reg */
1989 /* fill in command FIS */
1990 memcpy(buf_cmd
, &task
->ata_task
.fis
, sizeof(struct host_to_dev_fis
));
1995 static int prep_abort_v2_hw(struct hisi_hba
*hisi_hba
,
1996 struct hisi_sas_slot
*slot
,
1997 int device_id
, int abort_flag
, int tag_to_abort
)
1999 struct sas_task
*task
= slot
->task
;
2000 struct domain_device
*dev
= task
->dev
;
2001 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
2002 struct hisi_sas_port
*port
= slot
->port
;
2005 hdr
->dw0
= cpu_to_le32((5 << CMD_HDR_CMD_OFF
) | /*abort*/
2006 (port
->id
<< CMD_HDR_PORT_OFF
) |
2007 ((dev_is_sata(dev
) ? 1:0) <<
2008 CMD_HDR_ABORT_DEVICE_TYPE_OFF
) |
2009 (abort_flag
<< CMD_HDR_ABORT_FLAG_OFF
));
2012 hdr
->dw1
= cpu_to_le32(device_id
<< CMD_HDR_DEV_ID_OFF
);
2015 hdr
->dw7
= cpu_to_le32(tag_to_abort
<< CMD_HDR_ABORT_IPTT_OFF
);
2016 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
2021 static int phy_up_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2024 u32 context
, port_id
, link_rate
, hard_phy_linkrate
;
2025 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2026 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
2027 struct device
*dev
= &hisi_hba
->pdev
->dev
;
2028 u32
*frame_rcvd
= (u32
*)sas_phy
->frame_rcvd
;
2029 struct sas_identify_frame
*id
= (struct sas_identify_frame
*)frame_rcvd
;
2031 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 1);
2033 /* Check for SATA dev */
2034 context
= hisi_sas_read32(hisi_hba
, PHY_CONTEXT
);
2035 if (context
& (1 << phy_no
))
2039 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
2041 port_id
= (port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
2042 PORT_STATE_PHY8_PORT_NUM_OFF
;
2043 link_rate
= (port_state
& PORT_STATE_PHY8_CONN_RATE_MSK
) >>
2044 PORT_STATE_PHY8_CONN_RATE_OFF
;
2046 port_id
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
2047 port_id
= (port_id
>> (4 * phy_no
)) & 0xf;
2048 link_rate
= hisi_sas_read32(hisi_hba
, PHY_CONN_RATE
);
2049 link_rate
= (link_rate
>> (phy_no
* 4)) & 0xf;
2052 if (port_id
== 0xf) {
2053 dev_err(dev
, "phyup: phy%d invalid portid\n", phy_no
);
2058 for (i
= 0; i
< 6; i
++) {
2059 u32 idaf
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2060 RX_IDAF_DWORD0
+ (i
* 4));
2061 frame_rcvd
[i
] = __swab32(idaf
);
2064 sas_phy
->linkrate
= link_rate
;
2065 hard_phy_linkrate
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2067 phy
->maximum_linkrate
= hard_phy_linkrate
& 0xf;
2068 phy
->minimum_linkrate
= (hard_phy_linkrate
>> 4) & 0xf;
2070 sas_phy
->oob_mode
= SAS_OOB_MODE
;
2071 memcpy(sas_phy
->attached_sas_addr
, &id
->sas_addr
, SAS_ADDR_SIZE
);
2072 dev_info(dev
, "phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
2073 phy
->port_id
= port_id
;
2074 phy
->phy_type
&= ~(PORT_TYPE_SAS
| PORT_TYPE_SATA
);
2075 phy
->phy_type
|= PORT_TYPE_SAS
;
2076 phy
->phy_attached
= 1;
2077 phy
->identify
.device_type
= id
->dev_type
;
2078 phy
->frame_rcvd_size
= sizeof(struct sas_identify_frame
);
2079 if (phy
->identify
.device_type
== SAS_END_DEVICE
)
2080 phy
->identify
.target_port_protocols
=
2082 else if (phy
->identify
.device_type
!= SAS_PHY_UNUSED
) {
2083 phy
->identify
.target_port_protocols
=
2085 if (!timer_pending(&hisi_hba
->timer
))
2086 set_link_timer_quirk(hisi_hba
);
2088 queue_work(hisi_hba
->wq
, &phy
->phyup_ws
);
2091 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
2092 CHL_INT0_SL_PHY_ENABLE_MSK
);
2093 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 0);
2098 static bool check_any_wideports_v2_hw(struct hisi_hba
*hisi_hba
)
2102 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
2103 if (port_state
& 0x1ff)
2109 static int phy_down_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2112 u32 phy_state
, sl_ctrl
, txid_auto
;
2113 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2114 struct hisi_sas_port
*port
= phy
->port
;
2116 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 1);
2118 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
2119 hisi_sas_phy_down(hisi_hba
, phy_no
, (phy_state
& 1 << phy_no
) ? 1 : 0);
2121 sl_ctrl
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
2122 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
,
2123 sl_ctrl
& ~SL_CONTROL_CTA_MSK
);
2124 if (port
&& !get_wideport_bitmap_v2_hw(hisi_hba
, port
->id
))
2125 if (!check_any_wideports_v2_hw(hisi_hba
) &&
2126 timer_pending(&hisi_hba
->timer
))
2127 del_timer(&hisi_hba
->timer
);
2129 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
2130 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
2131 txid_auto
| TXID_AUTO_CT3_MSK
);
2133 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
, CHL_INT0_NOT_RDY_MSK
);
2134 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 0);
2139 static irqreturn_t
int_phy_updown_v2_hw(int irq_no
, void *p
)
2141 struct hisi_hba
*hisi_hba
= p
;
2144 irqreturn_t res
= IRQ_HANDLED
;
2146 irq_msk
= (hisi_sas_read32(hisi_hba
, HGC_INVLD_DQE_INFO
)
2147 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF
) & 0x1ff;
2150 u32 irq_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2153 if (irq_value
& CHL_INT0_SL_PHY_ENABLE_MSK
)
2155 if (phy_up_v2_hw(phy_no
, hisi_hba
)) {
2160 if (irq_value
& CHL_INT0_NOT_RDY_MSK
)
2162 if (phy_down_v2_hw(phy_no
, hisi_hba
)) {
2175 static void phy_bcast_v2_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
2177 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
2178 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
2179 struct sas_ha_struct
*sas_ha
= &hisi_hba
->sha
;
2182 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 1);
2183 bcast_status
= hisi_sas_phy_read32(hisi_hba
, phy_no
, RX_PRIMS_STATUS
);
2184 if (bcast_status
& RX_BCAST_CHG_MSK
)
2185 sas_ha
->notify_port_event(sas_phy
, PORTE_BROADCAST_RCVD
);
2186 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
2187 CHL_INT0_SL_RX_BCST_ACK_MSK
);
2188 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 0);
2191 static irqreturn_t
int_chnl_int_v2_hw(int irq_no
, void *p
)
2193 struct hisi_hba
*hisi_hba
= p
;
2194 struct device
*dev
= &hisi_hba
->pdev
->dev
;
2195 u32 ent_msk
, ent_tmp
, irq_msk
;
2198 ent_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
2200 ent_msk
|= ENT_INT_SRC_MSK3_ENT95_MSK_MSK
;
2201 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_msk
);
2203 irq_msk
= (hisi_sas_read32(hisi_hba
, HGC_INVLD_DQE_INFO
) >>
2204 HGC_INVLD_DQE_INFO_FB_CH3_OFF
) & 0x1ff;
2207 if (irq_msk
& (1 << phy_no
)) {
2208 u32 irq_value0
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2210 u32 irq_value1
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2212 u32 irq_value2
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2216 if (irq_value1
& (CHL_INT1_DMAC_RX_ECC_ERR_MSK
|
2217 CHL_INT1_DMAC_TX_ECC_ERR_MSK
))
2218 panic("%s: DMAC RX/TX ecc bad error!\
2220 dev_name(dev
), irq_value1
);
2222 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2223 CHL_INT1
, irq_value1
);
2227 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2228 CHL_INT2
, irq_value2
);
2232 if (irq_value0
& CHL_INT0_SL_RX_BCST_ACK_MSK
)
2233 phy_bcast_v2_hw(phy_no
, hisi_hba
);
2235 hisi_sas_phy_write32(hisi_hba
, phy_no
,
2236 CHL_INT0
, irq_value0
2237 & (~CHL_INT0_HOTPLUG_TOUT_MSK
)
2238 & (~CHL_INT0_SL_PHY_ENABLE_MSK
)
2239 & (~CHL_INT0_NOT_RDY_MSK
));
2242 irq_msk
&= ~(1 << phy_no
);
2246 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_tmp
);
2252 one_bit_ecc_error_process_v2_hw(struct hisi_hba
*hisi_hba
, u32 irq_value
)
2254 struct device
*dev
= &hisi_hba
->pdev
->dev
;
2257 if (irq_value
& BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF
)) {
2258 reg_val
= hisi_sas_read32(hisi_hba
, HGC_DQE_ECC_ADDR
);
2259 dev_warn(dev
, "hgc_dqe_acc1b_intr found: \
2260 Ram address is 0x%08X\n",
2261 (reg_val
& HGC_DQE_ECC_1B_ADDR_MSK
) >>
2262 HGC_DQE_ECC_1B_ADDR_OFF
);
2265 if (irq_value
& BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF
)) {
2266 reg_val
= hisi_sas_read32(hisi_hba
, HGC_IOST_ECC_ADDR
);
2267 dev_warn(dev
, "hgc_iost_acc1b_intr found: \
2268 Ram address is 0x%08X\n",
2269 (reg_val
& HGC_IOST_ECC_1B_ADDR_MSK
) >>
2270 HGC_IOST_ECC_1B_ADDR_OFF
);
2273 if (irq_value
& BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF
)) {
2274 reg_val
= hisi_sas_read32(hisi_hba
, HGC_ITCT_ECC_ADDR
);
2275 dev_warn(dev
, "hgc_itct_acc1b_intr found: \
2276 Ram address is 0x%08X\n",
2277 (reg_val
& HGC_ITCT_ECC_1B_ADDR_MSK
) >>
2278 HGC_ITCT_ECC_1B_ADDR_OFF
);
2281 if (irq_value
& BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF
)) {
2282 reg_val
= hisi_sas_read32(hisi_hba
, HGC_LM_DFX_STATUS2
);
2283 dev_warn(dev
, "hgc_iostl_acc1b_intr found: \
2284 memory address is 0x%08X\n",
2285 (reg_val
& HGC_LM_DFX_STATUS2_IOSTLIST_MSK
) >>
2286 HGC_LM_DFX_STATUS2_IOSTLIST_OFF
);
2289 if (irq_value
& BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF
)) {
2290 reg_val
= hisi_sas_read32(hisi_hba
, HGC_LM_DFX_STATUS2
);
2291 dev_warn(dev
, "hgc_itctl_acc1b_intr found: \
2292 memory address is 0x%08X\n",
2293 (reg_val
& HGC_LM_DFX_STATUS2_ITCTLIST_MSK
) >>
2294 HGC_LM_DFX_STATUS2_ITCTLIST_OFF
);
2297 if (irq_value
& BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF
)) {
2298 reg_val
= hisi_sas_read32(hisi_hba
, HGC_CQE_ECC_ADDR
);
2299 dev_warn(dev
, "hgc_cqe_acc1b_intr found: \
2300 Ram address is 0x%08X\n",
2301 (reg_val
& HGC_CQE_ECC_1B_ADDR_MSK
) >>
2302 HGC_CQE_ECC_1B_ADDR_OFF
);
2305 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF
)) {
2306 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS14
);
2307 dev_warn(dev
, "rxm_mem0_acc1b_intr found: \
2308 memory address is 0x%08X\n",
2309 (reg_val
& HGC_RXM_DFX_STATUS14_MEM0_MSK
) >>
2310 HGC_RXM_DFX_STATUS14_MEM0_OFF
);
2313 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF
)) {
2314 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS14
);
2315 dev_warn(dev
, "rxm_mem1_acc1b_intr found: \
2316 memory address is 0x%08X\n",
2317 (reg_val
& HGC_RXM_DFX_STATUS14_MEM1_MSK
) >>
2318 HGC_RXM_DFX_STATUS14_MEM1_OFF
);
2321 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF
)) {
2322 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS14
);
2323 dev_warn(dev
, "rxm_mem2_acc1b_intr found: \
2324 memory address is 0x%08X\n",
2325 (reg_val
& HGC_RXM_DFX_STATUS14_MEM2_MSK
) >>
2326 HGC_RXM_DFX_STATUS14_MEM2_OFF
);
2329 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF
)) {
2330 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS15
);
2331 dev_warn(dev
, "rxm_mem3_acc1b_intr found: \
2332 memory address is 0x%08X\n",
2333 (reg_val
& HGC_RXM_DFX_STATUS15_MEM3_MSK
) >>
2334 HGC_RXM_DFX_STATUS15_MEM3_OFF
);
2339 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba
*hisi_hba
,
2343 struct device
*dev
= &hisi_hba
->pdev
->dev
;
2345 if (irq_value
& BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF
)) {
2346 reg_val
= hisi_sas_read32(hisi_hba
, HGC_DQE_ECC_ADDR
);
2347 panic("%s: hgc_dqe_accbad_intr (0x%x) found: \
2348 Ram address is 0x%08X\n",
2349 dev_name(dev
), irq_value
,
2350 (reg_val
& HGC_DQE_ECC_MB_ADDR_MSK
) >>
2351 HGC_DQE_ECC_MB_ADDR_OFF
);
2354 if (irq_value
& BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF
)) {
2355 reg_val
= hisi_sas_read32(hisi_hba
, HGC_IOST_ECC_ADDR
);
2356 panic("%s: hgc_iost_accbad_intr (0x%x) found: \
2357 Ram address is 0x%08X\n",
2358 dev_name(dev
), irq_value
,
2359 (reg_val
& HGC_IOST_ECC_MB_ADDR_MSK
) >>
2360 HGC_IOST_ECC_MB_ADDR_OFF
);
2363 if (irq_value
& BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF
)) {
2364 reg_val
= hisi_sas_read32(hisi_hba
, HGC_ITCT_ECC_ADDR
);
2365 panic("%s: hgc_itct_accbad_intr (0x%x) found: \
2366 Ram address is 0x%08X\n",
2367 dev_name(dev
), irq_value
,
2368 (reg_val
& HGC_ITCT_ECC_MB_ADDR_MSK
) >>
2369 HGC_ITCT_ECC_MB_ADDR_OFF
);
2372 if (irq_value
& BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF
)) {
2373 reg_val
= hisi_sas_read32(hisi_hba
, HGC_LM_DFX_STATUS2
);
2374 panic("%s: hgc_iostl_accbad_intr (0x%x) found: \
2375 memory address is 0x%08X\n",
2376 dev_name(dev
), irq_value
,
2377 (reg_val
& HGC_LM_DFX_STATUS2_IOSTLIST_MSK
) >>
2378 HGC_LM_DFX_STATUS2_IOSTLIST_OFF
);
2381 if (irq_value
& BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF
)) {
2382 reg_val
= hisi_sas_read32(hisi_hba
, HGC_LM_DFX_STATUS2
);
2383 panic("%s: hgc_itctl_accbad_intr (0x%x) found: \
2384 memory address is 0x%08X\n",
2385 dev_name(dev
), irq_value
,
2386 (reg_val
& HGC_LM_DFX_STATUS2_ITCTLIST_MSK
) >>
2387 HGC_LM_DFX_STATUS2_ITCTLIST_OFF
);
2390 if (irq_value
& BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF
)) {
2391 reg_val
= hisi_sas_read32(hisi_hba
, HGC_CQE_ECC_ADDR
);
2392 panic("%s: hgc_cqe_accbad_intr (0x%x) found: \
2393 Ram address is 0x%08X\n",
2394 dev_name(dev
), irq_value
,
2395 (reg_val
& HGC_CQE_ECC_MB_ADDR_MSK
) >>
2396 HGC_CQE_ECC_MB_ADDR_OFF
);
2399 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF
)) {
2400 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS14
);
2401 panic("%s: rxm_mem0_accbad_intr (0x%x) found: \
2402 memory address is 0x%08X\n",
2403 dev_name(dev
), irq_value
,
2404 (reg_val
& HGC_RXM_DFX_STATUS14_MEM0_MSK
) >>
2405 HGC_RXM_DFX_STATUS14_MEM0_OFF
);
2408 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF
)) {
2409 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS14
);
2410 panic("%s: rxm_mem1_accbad_intr (0x%x) found: \
2411 memory address is 0x%08X\n",
2412 dev_name(dev
), irq_value
,
2413 (reg_val
& HGC_RXM_DFX_STATUS14_MEM1_MSK
) >>
2414 HGC_RXM_DFX_STATUS14_MEM1_OFF
);
2417 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF
)) {
2418 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS14
);
2419 panic("%s: rxm_mem2_accbad_intr (0x%x) found: \
2420 memory address is 0x%08X\n",
2421 dev_name(dev
), irq_value
,
2422 (reg_val
& HGC_RXM_DFX_STATUS14_MEM2_MSK
) >>
2423 HGC_RXM_DFX_STATUS14_MEM2_OFF
);
2426 if (irq_value
& BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF
)) {
2427 reg_val
= hisi_sas_read32(hisi_hba
, HGC_RXM_DFX_STATUS15
);
2428 panic("%s: rxm_mem3_accbad_intr (0x%x) found: \
2429 memory address is 0x%08X\n",
2430 dev_name(dev
), irq_value
,
2431 (reg_val
& HGC_RXM_DFX_STATUS15_MEM3_MSK
) >>
2432 HGC_RXM_DFX_STATUS15_MEM3_OFF
);
2437 static irqreturn_t
fatal_ecc_int_v2_hw(int irq_no
, void *p
)
2439 struct hisi_hba
*hisi_hba
= p
;
2440 u32 irq_value
, irq_msk
;
2442 irq_msk
= hisi_sas_read32(hisi_hba
, SAS_ECC_INTR_MSK
);
2443 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, irq_msk
| 0xffffffff);
2445 irq_value
= hisi_sas_read32(hisi_hba
, SAS_ECC_INTR
);
2447 one_bit_ecc_error_process_v2_hw(hisi_hba
, irq_value
);
2448 multi_bit_ecc_error_process_v2_hw(hisi_hba
, irq_value
);
2451 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR
, irq_value
);
2452 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, irq_msk
);
2457 #define AXI_ERR_NR 8
2458 static const char axi_err_info
[AXI_ERR_NR
][32] = {
2469 #define FIFO_ERR_NR 5
2470 static const char fifo_err_info
[FIFO_ERR_NR
][32] = {
2478 static irqreturn_t
fatal_axi_int_v2_hw(int irq_no
, void *p
)
2480 struct hisi_hba
*hisi_hba
= p
;
2481 u32 irq_value
, irq_msk
, err_value
;
2482 struct device
*dev
= &hisi_hba
->pdev
->dev
;
2484 irq_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
2485 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, irq_msk
| 0xfffffffe);
2487 irq_value
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
2489 if (irq_value
& BIT(ENT_INT_SRC3_WP_DEPTH_OFF
)) {
2490 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
2491 1 << ENT_INT_SRC3_WP_DEPTH_OFF
);
2492 panic("%s: write pointer and depth error (0x%x) \
2494 dev_name(dev
), irq_value
);
2497 if (irq_value
& BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF
)) {
2498 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
2500 ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF
);
2501 panic("%s: iptt no match slot error (0x%x) found!\n",
2502 dev_name(dev
), irq_value
);
2505 if (irq_value
& BIT(ENT_INT_SRC3_RP_DEPTH_OFF
))
2506 panic("%s: read pointer and depth error (0x%x) \
2508 dev_name(dev
), irq_value
);
2510 if (irq_value
& BIT(ENT_INT_SRC3_AXI_OFF
)) {
2513 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
2514 1 << ENT_INT_SRC3_AXI_OFF
);
2515 err_value
= hisi_sas_read32(hisi_hba
,
2516 HGC_AXI_FIFO_ERR_INFO
);
2518 for (i
= 0; i
< AXI_ERR_NR
; i
++) {
2519 if (err_value
& BIT(i
))
2520 panic("%s: %s (0x%x) found!\n",
2522 axi_err_info
[i
], irq_value
);
2526 if (irq_value
& BIT(ENT_INT_SRC3_FIFO_OFF
)) {
2529 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
2530 1 << ENT_INT_SRC3_FIFO_OFF
);
2531 err_value
= hisi_sas_read32(hisi_hba
,
2532 HGC_AXI_FIFO_ERR_INFO
);
2534 for (i
= 0; i
< FIFO_ERR_NR
; i
++) {
2535 if (err_value
& BIT(AXI_ERR_NR
+ i
))
2536 panic("%s: %s (0x%x) found!\n",
2538 fifo_err_info
[i
], irq_value
);
2543 if (irq_value
& BIT(ENT_INT_SRC3_LM_OFF
)) {
2544 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
2545 1 << ENT_INT_SRC3_LM_OFF
);
2546 panic("%s: LM add/fetch list error (0x%x) found!\n",
2547 dev_name(dev
), irq_value
);
2550 if (irq_value
& BIT(ENT_INT_SRC3_ABT_OFF
)) {
2551 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
2552 1 << ENT_INT_SRC3_ABT_OFF
);
2553 panic("%s: SAS_HGC_ABT fetch LM list error (0x%x) found!\n",
2554 dev_name(dev
), irq_value
);
2558 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, irq_msk
);
2563 static void cq_tasklet_v2_hw(unsigned long val
)
2565 struct hisi_sas_cq
*cq
= (struct hisi_sas_cq
*)val
;
2566 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
2567 struct hisi_sas_slot
*slot
;
2568 struct hisi_sas_itct
*itct
;
2569 struct hisi_sas_complete_v2_hdr
*complete_queue
;
2570 u32 rd_point
= cq
->rd_point
, wr_point
, dev_id
;
2573 complete_queue
= hisi_hba
->complete_hdr
[queue
];
2575 spin_lock(&hisi_hba
->lock
);
2576 wr_point
= hisi_sas_read32(hisi_hba
, COMPL_Q_0_WR_PTR
+
2579 while (rd_point
!= wr_point
) {
2580 struct hisi_sas_complete_v2_hdr
*complete_hdr
;
2583 complete_hdr
= &complete_queue
[rd_point
];
2585 /* Check for NCQ completion */
2586 if (complete_hdr
->act
) {
2587 u32 act_tmp
= complete_hdr
->act
;
2588 int ncq_tag_count
= ffs(act_tmp
);
2590 dev_id
= (complete_hdr
->dw1
& CMPLT_HDR_DEV_ID_MSK
) >>
2591 CMPLT_HDR_DEV_ID_OFF
;
2592 itct
= &hisi_hba
->itct
[dev_id
];
2594 /* The NCQ tags are held in the itct header */
2595 while (ncq_tag_count
) {
2596 __le64
*ncq_tag
= &itct
->qw4_15
[0];
2599 iptt
= (ncq_tag
[ncq_tag_count
/ 5]
2600 >> (ncq_tag_count
% 5) * 12) & 0xfff;
2602 slot
= &hisi_hba
->slot_info
[iptt
];
2603 slot
->cmplt_queue_slot
= rd_point
;
2604 slot
->cmplt_queue
= queue
;
2605 slot_complete_v2_hw(hisi_hba
, slot
, 0);
2607 act_tmp
&= ~(1 << ncq_tag_count
);
2608 ncq_tag_count
= ffs(act_tmp
);
2611 iptt
= (complete_hdr
->dw1
) & CMPLT_HDR_IPTT_MSK
;
2612 slot
= &hisi_hba
->slot_info
[iptt
];
2613 slot
->cmplt_queue_slot
= rd_point
;
2614 slot
->cmplt_queue
= queue
;
2615 slot_complete_v2_hw(hisi_hba
, slot
, 0);
2618 if (++rd_point
>= HISI_SAS_QUEUE_SLOTS
)
2622 /* update rd_point */
2623 cq
->rd_point
= rd_point
;
2624 hisi_sas_write32(hisi_hba
, COMPL_Q_0_RD_PTR
+ (0x14 * queue
), rd_point
);
2625 spin_unlock(&hisi_hba
->lock
);
2628 static irqreturn_t
cq_interrupt_v2_hw(int irq_no
, void *p
)
2630 struct hisi_sas_cq
*cq
= p
;
2631 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
2634 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 1 << queue
);
2636 tasklet_schedule(&cq
->tasklet
);
2641 static irqreturn_t
sata_int_v2_hw(int irq_no
, void *p
)
2643 struct hisi_sas_phy
*phy
= p
;
2644 struct hisi_hba
*hisi_hba
= phy
->hisi_hba
;
2645 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
2646 struct device
*dev
= &hisi_hba
->pdev
->dev
;
2647 struct hisi_sas_initial_fis
*initial_fis
;
2648 struct dev_to_host_fis
*fis
;
2649 u32 ent_tmp
, ent_msk
, ent_int
, port_id
, link_rate
, hard_phy_linkrate
;
2650 irqreturn_t res
= IRQ_HANDLED
;
2651 u8 attached_sas_addr
[SAS_ADDR_SIZE
] = {0};
2654 phy_no
= sas_phy
->id
;
2655 initial_fis
= &hisi_hba
->initial_fis
[phy_no
];
2656 fis
= &initial_fis
->fis
;
2658 offset
= 4 * (phy_no
/ 4);
2659 ent_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
);
2660 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
,
2661 ent_msk
| 1 << ((phy_no
% 4) * 8));
2663 ent_int
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC1
+ offset
);
2664 ent_tmp
= ent_int
& (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF
*
2666 ent_int
>>= ENT_INT_SRC1_D2H_FIS_CH1_OFF
* (phy_no
% 4);
2667 if ((ent_int
& ENT_INT_SRC1_D2H_FIS_CH0_MSK
) == 0) {
2668 dev_warn(dev
, "sata int: phy%d did not receive FIS\n", phy_no
);
2673 /* check ERR bit of Status Register */
2674 if (fis
->status
& ATA_ERR
) {
2675 dev_warn(dev
, "sata int: phy%d FIS status: 0x%x\n", phy_no
,
2677 disable_phy_v2_hw(hisi_hba
, phy_no
);
2678 enable_phy_v2_hw(hisi_hba
, phy_no
);
2683 if (unlikely(phy_no
== 8)) {
2684 u32 port_state
= hisi_sas_read32(hisi_hba
, PORT_STATE
);
2686 port_id
= (port_state
& PORT_STATE_PHY8_PORT_NUM_MSK
) >>
2687 PORT_STATE_PHY8_PORT_NUM_OFF
;
2688 link_rate
= (port_state
& PORT_STATE_PHY8_CONN_RATE_MSK
) >>
2689 PORT_STATE_PHY8_CONN_RATE_OFF
;
2691 port_id
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
2692 port_id
= (port_id
>> (4 * phy_no
)) & 0xf;
2693 link_rate
= hisi_sas_read32(hisi_hba
, PHY_CONN_RATE
);
2694 link_rate
= (link_rate
>> (phy_no
* 4)) & 0xf;
2697 if (port_id
== 0xf) {
2698 dev_err(dev
, "sata int: phy%d invalid portid\n", phy_no
);
2703 sas_phy
->linkrate
= link_rate
;
2704 hard_phy_linkrate
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
2706 phy
->maximum_linkrate
= hard_phy_linkrate
& 0xf;
2707 phy
->minimum_linkrate
= (hard_phy_linkrate
>> 4) & 0xf;
2709 sas_phy
->oob_mode
= SATA_OOB_MODE
;
2710 /* Make up some unique SAS address */
2711 attached_sas_addr
[0] = 0x50;
2712 attached_sas_addr
[7] = phy_no
;
2713 memcpy(sas_phy
->attached_sas_addr
, attached_sas_addr
, SAS_ADDR_SIZE
);
2714 memcpy(sas_phy
->frame_rcvd
, fis
, sizeof(struct dev_to_host_fis
));
2715 dev_info(dev
, "sata int phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
2716 phy
->phy_type
&= ~(PORT_TYPE_SAS
| PORT_TYPE_SATA
);
2717 phy
->port_id
= port_id
;
2718 phy
->phy_type
|= PORT_TYPE_SATA
;
2719 phy
->phy_attached
= 1;
2720 phy
->identify
.device_type
= SAS_SATA_DEV
;
2721 phy
->frame_rcvd_size
= sizeof(struct dev_to_host_fis
);
2722 phy
->identify
.target_port_protocols
= SAS_PROTOCOL_SATA
;
2723 queue_work(hisi_hba
->wq
, &phy
->phyup_ws
);
2726 hisi_sas_write32(hisi_hba
, ENT_INT_SRC1
+ offset
, ent_tmp
);
2727 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
+ offset
, ent_msk
);
2732 static irq_handler_t phy_interrupts
[HISI_SAS_PHY_INT_NR
] = {
2733 int_phy_updown_v2_hw
,
2737 static irq_handler_t fatal_interrupts
[HISI_SAS_FATAL_INT_NR
] = {
2738 fatal_ecc_int_v2_hw
,
2743 * There is a limitation in the hip06 chipset that we need
2744 * to map in all mbigen interrupts, even if they are not used.
2746 static int interrupt_init_v2_hw(struct hisi_hba
*hisi_hba
)
2748 struct platform_device
*pdev
= hisi_hba
->pdev
;
2749 struct device
*dev
= &pdev
->dev
;
2750 int i
, irq
, rc
, irq_map
[128];
2753 for (i
= 0; i
< 128; i
++)
2754 irq_map
[i
] = platform_get_irq(pdev
, i
);
2756 for (i
= 0; i
< HISI_SAS_PHY_INT_NR
; i
++) {
2759 irq
= irq_map
[idx
+ 1]; /* Phy up/down is irq1 */
2761 dev_err(dev
, "irq init: fail map phy interrupt %d\n",
2766 rc
= devm_request_irq(dev
, irq
, phy_interrupts
[i
], 0,
2767 DRV_NAME
" phy", hisi_hba
);
2769 dev_err(dev
, "irq init: could not request "
2770 "phy interrupt %d, rc=%d\n",
2776 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
2777 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[i
];
2778 int idx
= i
+ 72; /* First SATA interrupt is irq72 */
2782 dev_err(dev
, "irq init: fail map phy interrupt %d\n",
2787 rc
= devm_request_irq(dev
, irq
, sata_int_v2_hw
, 0,
2788 DRV_NAME
" sata", phy
);
2790 dev_err(dev
, "irq init: could not request "
2791 "sata interrupt %d, rc=%d\n",
2797 for (i
= 0; i
< HISI_SAS_FATAL_INT_NR
; i
++) {
2800 irq
= irq_map
[idx
+ 81];
2802 dev_err(dev
, "irq init: fail map fatal interrupt %d\n",
2807 rc
= devm_request_irq(dev
, irq
, fatal_interrupts
[i
], 0,
2808 DRV_NAME
" fatal", hisi_hba
);
2811 "irq init: could not request fatal interrupt %d, rc=%d\n",
2817 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
2818 int idx
= i
+ 96; /* First cq interrupt is irq96 */
2819 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[i
];
2820 struct tasklet_struct
*t
= &cq
->tasklet
;
2825 "irq init: could not map cq interrupt %d\n",
2829 rc
= devm_request_irq(dev
, irq
, cq_interrupt_v2_hw
, 0,
2830 DRV_NAME
" cq", &hisi_hba
->cq
[i
]);
2833 "irq init: could not request cq interrupt %d, rc=%d\n",
2837 tasklet_init(t
, cq_tasklet_v2_hw
, (unsigned long)cq
);
2843 static int hisi_sas_v2_init(struct hisi_hba
*hisi_hba
)
2847 rc
= hw_init_v2_hw(hisi_hba
);
2851 rc
= interrupt_init_v2_hw(hisi_hba
);
2855 phys_init_v2_hw(hisi_hba
);
2860 static const struct hisi_sas_hw hisi_sas_v2_hw
= {
2861 .hw_init
= hisi_sas_v2_init
,
2862 .setup_itct
= setup_itct_v2_hw
,
2863 .slot_index_alloc
= slot_index_alloc_quirk_v2_hw
,
2864 .alloc_dev
= alloc_dev_quirk_v2_hw
,
2865 .sl_notify
= sl_notify_v2_hw
,
2866 .get_wideport_bitmap
= get_wideport_bitmap_v2_hw
,
2867 .free_device
= free_device_v2_hw
,
2868 .prep_smp
= prep_smp_v2_hw
,
2869 .prep_ssp
= prep_ssp_v2_hw
,
2870 .prep_stp
= prep_ata_v2_hw
,
2871 .prep_abort
= prep_abort_v2_hw
,
2872 .get_free_slot
= get_free_slot_v2_hw
,
2873 .start_delivery
= start_delivery_v2_hw
,
2874 .slot_complete
= slot_complete_v2_hw
,
2875 .phy_enable
= enable_phy_v2_hw
,
2876 .phy_disable
= disable_phy_v2_hw
,
2877 .phy_hard_reset
= phy_hard_reset_v2_hw
,
2878 .phy_set_linkrate
= phy_set_linkrate_v2_hw
,
2879 .phy_get_max_linkrate
= phy_get_max_linkrate_v2_hw
,
2880 .max_command_entries
= HISI_SAS_COMMAND_ENTRIES_V2_HW
,
2881 .complete_hdr_size
= sizeof(struct hisi_sas_complete_v2_hdr
),
2884 static int hisi_sas_v2_probe(struct platform_device
*pdev
)
2887 * Check if we should defer the probe before we probe the
2888 * upper layer, as it's hard to defer later on.
2890 int ret
= platform_get_irq(pdev
, 0);
2893 if (ret
!= -EPROBE_DEFER
)
2894 dev_err(&pdev
->dev
, "cannot obtain irq\n");
2898 return hisi_sas_probe(pdev
, &hisi_sas_v2_hw
);
2901 static int hisi_sas_v2_remove(struct platform_device
*pdev
)
2903 struct sas_ha_struct
*sha
= platform_get_drvdata(pdev
);
2904 struct hisi_hba
*hisi_hba
= sha
->lldd_ha
;
2906 if (timer_pending(&hisi_hba
->timer
))
2907 del_timer(&hisi_hba
->timer
);
2909 return hisi_sas_remove(pdev
);
2912 static const struct of_device_id sas_v2_of_match
[] = {
2913 { .compatible
= "hisilicon,hip06-sas-v2",},
2914 { .compatible
= "hisilicon,hip07-sas-v2",},
2917 MODULE_DEVICE_TABLE(of
, sas_v2_of_match
);
2919 static const struct acpi_device_id sas_v2_acpi_match
[] = {
2924 MODULE_DEVICE_TABLE(acpi
, sas_v2_acpi_match
);
2926 static struct platform_driver hisi_sas_v2_driver
= {
2927 .probe
= hisi_sas_v2_probe
,
2928 .remove
= hisi_sas_v2_remove
,
2931 .of_match_table
= sas_v2_of_match
,
2932 .acpi_match_table
= ACPI_PTR(sas_v2_acpi_match
),
2936 module_platform_driver(hisi_sas_v2_driver
);
2938 MODULE_LICENSE("GPL");
2939 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2940 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
2941 MODULE_ALIAS("platform:" DRV_NAME
);