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scsi: hisi_sas: add irq and tasklet cleanup in v2 hw
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
1 /*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12 #include "hisi_sas.h"
13 #define DRV_NAME "hisi_sas_v2_hw"
14
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
34 #define ITCT_CLR 0x44
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
148 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
149 #define DLVRY_Q_0_DEPTH 0x268
150 #define DLVRY_Q_0_WR_PTR 0x26c
151 #define DLVRY_Q_0_RD_PTR 0x270
152 #define HYPER_STREAM_ID_EN_CFG 0xc80
153 #define OQ0_INT_SRC_MSK 0xc90
154 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
155 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
156 #define COMPL_Q_0_DEPTH 0x4e8
157 #define COMPL_Q_0_WR_PTR 0x4ec
158 #define COMPL_Q_0_RD_PTR 0x4f0
159 #define HGC_RXM_DFX_STATUS14 0xae8
160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
162 HGC_RXM_DFX_STATUS14_MEM0_OFF)
163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM1_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM2_OFF)
169 #define HGC_RXM_DFX_STATUS15 0xaec
170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
172 HGC_RXM_DFX_STATUS15_MEM3_OFF)
173 /* phy registers need init */
174 #define PORT_BASE (0x2000)
175
176 #define PHY_CFG (PORT_BASE + 0x0)
177 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PHY_CFG_ENA_OFF 0
179 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
180 #define PHY_CFG_DC_OPT_OFF 2
181 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
182 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
183 #define PROG_PHY_LINK_RATE_MAX_OFF 0
184 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
185 #define PHY_CTRL (PORT_BASE + 0x14)
186 #define PHY_CTRL_RESET_OFF 0
187 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
188 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
189 #define SL_CFG (PORT_BASE + 0x84)
190 #define PHY_PCN (PORT_BASE + 0x44)
191 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
192 #define SL_CONTROL (PORT_BASE + 0x94)
193 #define SL_CONTROL_NOTIFY_EN_OFF 0
194 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
195 #define SL_CONTROL_CTA_OFF 17
196 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
197 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
198 #define RX_BCAST_CHG_OFF 1
199 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
200 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
201 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
202 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
203 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
204 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
205 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
206 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
207 #define TXID_AUTO (PORT_BASE + 0xb8)
208 #define TXID_AUTO_CT3_OFF 1
209 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
210 #define TXID_AUTO_CTB_OFF 11
211 #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
212 #define TX_HARDRST_OFF 2
213 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
214 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
215 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
216 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
217 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
218 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
219 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
220 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
221 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
222 #define CON_CONTROL (PORT_BASE + 0x118)
223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
225 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
226 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
227 #define CHL_INT0 (PORT_BASE + 0x1b4)
228 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
229 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
230 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
231 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
232 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
233 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
234 #define CHL_INT0_NOT_RDY_OFF 4
235 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
236 #define CHL_INT0_PHY_RDY_OFF 5
237 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
238 #define CHL_INT1 (PORT_BASE + 0x1b8)
239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
243 #define CHL_INT2 (PORT_BASE + 0x1bc)
244 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
245 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
246 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
247 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
248 #define DMA_TX_DFX0 (PORT_BASE + 0x200)
249 #define DMA_TX_DFX1 (PORT_BASE + 0x204)
250 #define DMA_TX_DFX1_IPTT_OFF 0
251 #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
252 #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
253 #define PORT_DFX0 (PORT_BASE + 0x258)
254 #define LINK_DFX2 (PORT_BASE + 0X264)
255 #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
256 #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
257 #define LINK_DFX2_SEND_HOLD_STS_OFF 10
258 #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
259 #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
260 #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
261 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
262 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
263 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
264 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
265 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
266 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
267 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
268 #define DMA_TX_STATUS_BUSY_OFF 0
269 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
270 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
271 #define DMA_RX_STATUS_BUSY_OFF 0
272 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
273
274 #define AXI_CFG (0x5100)
275 #define AM_CFG_MAX_TRANS (0x5010)
276 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
277
278 #define AXI_MASTER_CFG_BASE (0x5000)
279 #define AM_CTRL_GLOBAL (0x0)
280 #define AM_CURR_TRANS_RETURN (0x150)
281
282 /* HW dma structures */
283 /* Delivery queue header */
284 /* dw0 */
285 #define CMD_HDR_ABORT_FLAG_OFF 0
286 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
287 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
288 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
289 #define CMD_HDR_RESP_REPORT_OFF 5
290 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
291 #define CMD_HDR_TLR_CTRL_OFF 6
292 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
293 #define CMD_HDR_PORT_OFF 18
294 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
295 #define CMD_HDR_PRIORITY_OFF 27
296 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
297 #define CMD_HDR_CMD_OFF 29
298 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
299 /* dw1 */
300 #define CMD_HDR_DIR_OFF 5
301 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
302 #define CMD_HDR_RESET_OFF 7
303 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
304 #define CMD_HDR_VDTL_OFF 10
305 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
306 #define CMD_HDR_FRAME_TYPE_OFF 11
307 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
308 #define CMD_HDR_DEV_ID_OFF 16
309 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
310 /* dw2 */
311 #define CMD_HDR_CFL_OFF 0
312 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
313 #define CMD_HDR_NCQ_TAG_OFF 10
314 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
315 #define CMD_HDR_MRFL_OFF 15
316 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
317 #define CMD_HDR_SG_MOD_OFF 24
318 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
319 #define CMD_HDR_FIRST_BURST_OFF 26
320 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
321 /* dw3 */
322 #define CMD_HDR_IPTT_OFF 0
323 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
324 /* dw6 */
325 #define CMD_HDR_DIF_SGL_LEN_OFF 0
326 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
327 #define CMD_HDR_DATA_SGL_LEN_OFF 16
328 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
329 #define CMD_HDR_ABORT_IPTT_OFF 16
330 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
331
332 /* Completion header */
333 /* dw0 */
334 #define CMPLT_HDR_ERR_PHASE_OFF 2
335 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
336 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
337 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
338 #define CMPLT_HDR_ERX_OFF 12
339 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
340 #define CMPLT_HDR_ABORT_STAT_OFF 13
341 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
342 /* abort_stat */
343 #define STAT_IO_NOT_VALID 0x1
344 #define STAT_IO_NO_DEVICE 0x2
345 #define STAT_IO_COMPLETE 0x3
346 #define STAT_IO_ABORTED 0x4
347 /* dw1 */
348 #define CMPLT_HDR_IPTT_OFF 0
349 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
350 #define CMPLT_HDR_DEV_ID_OFF 16
351 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
352
353 /* ITCT header */
354 /* qw0 */
355 #define ITCT_HDR_DEV_TYPE_OFF 0
356 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
357 #define ITCT_HDR_VALID_OFF 2
358 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
359 #define ITCT_HDR_MCR_OFF 5
360 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
361 #define ITCT_HDR_VLN_OFF 9
362 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
363 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
364 #define ITCT_HDR_SMP_TIMEOUT_8US 1
365 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
366 250) /* 2ms */
367 #define ITCT_HDR_AWT_CONTINUE_OFF 25
368 #define ITCT_HDR_PORT_ID_OFF 28
369 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
370 /* qw2 */
371 #define ITCT_HDR_INLT_OFF 0
372 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
373 #define ITCT_HDR_BITLT_OFF 16
374 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
375 #define ITCT_HDR_MCTLT_OFF 32
376 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
377 #define ITCT_HDR_RTOLT_OFF 48
378 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
379
380 #define HISI_SAS_FATAL_INT_NR 2
381
382 struct hisi_sas_complete_v2_hdr {
383 __le32 dw0;
384 __le32 dw1;
385 __le32 act;
386 __le32 dw3;
387 };
388
389 struct hisi_sas_err_record_v2 {
390 /* dw0 */
391 __le32 trans_tx_fail_type;
392
393 /* dw1 */
394 __le32 trans_rx_fail_type;
395
396 /* dw2 */
397 __le16 dma_tx_err_type;
398 __le16 sipc_rx_err_type;
399
400 /* dw3 */
401 __le32 dma_rx_err_type;
402 };
403
404 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
405 {
406 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
407 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
408 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
409 .msg = "hgc_dqe_acc1b_intr found: \
410 Ram address is 0x%08X\n",
411 .reg = HGC_DQE_ECC_ADDR,
412 },
413 {
414 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
415 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
416 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
417 .msg = "hgc_iost_acc1b_intr found: \
418 Ram address is 0x%08X\n",
419 .reg = HGC_IOST_ECC_ADDR,
420 },
421 {
422 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
423 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
424 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
425 .msg = "hgc_itct_acc1b_intr found: \
426 Ram address is 0x%08X\n",
427 .reg = HGC_ITCT_ECC_ADDR,
428 },
429 {
430 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
431 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
432 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
433 .msg = "hgc_iostl_acc1b_intr found: \
434 memory address is 0x%08X\n",
435 .reg = HGC_LM_DFX_STATUS2,
436 },
437 {
438 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
439 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
440 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
441 .msg = "hgc_itctl_acc1b_intr found: \
442 memory address is 0x%08X\n",
443 .reg = HGC_LM_DFX_STATUS2,
444 },
445 {
446 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
447 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
448 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
449 .msg = "hgc_cqe_acc1b_intr found: \
450 Ram address is 0x%08X\n",
451 .reg = HGC_CQE_ECC_ADDR,
452 },
453 {
454 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
455 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
456 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
457 .msg = "rxm_mem0_acc1b_intr found: \
458 memory address is 0x%08X\n",
459 .reg = HGC_RXM_DFX_STATUS14,
460 },
461 {
462 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
463 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
464 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
465 .msg = "rxm_mem1_acc1b_intr found: \
466 memory address is 0x%08X\n",
467 .reg = HGC_RXM_DFX_STATUS14,
468 },
469 {
470 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
471 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
472 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
473 .msg = "rxm_mem2_acc1b_intr found: \
474 memory address is 0x%08X\n",
475 .reg = HGC_RXM_DFX_STATUS14,
476 },
477 {
478 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
479 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
480 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
481 .msg = "rxm_mem3_acc1b_intr found: \
482 memory address is 0x%08X\n",
483 .reg = HGC_RXM_DFX_STATUS15,
484 },
485 };
486
487 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
488 {
489 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
490 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
491 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
492 .msg = "hgc_dqe_accbad_intr (0x%x) found: \
493 Ram address is 0x%08X\n",
494 .reg = HGC_DQE_ECC_ADDR,
495 },
496 {
497 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
498 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
499 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
500 .msg = "hgc_iost_accbad_intr (0x%x) found: \
501 Ram address is 0x%08X\n",
502 .reg = HGC_IOST_ECC_ADDR,
503 },
504 {
505 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
506 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
507 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
508 .msg = "hgc_itct_accbad_intr (0x%x) found: \
509 Ram address is 0x%08X\n",
510 .reg = HGC_ITCT_ECC_ADDR,
511 },
512 {
513 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
514 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
515 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
516 .msg = "hgc_iostl_accbad_intr (0x%x) found: \
517 memory address is 0x%08X\n",
518 .reg = HGC_LM_DFX_STATUS2,
519 },
520 {
521 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
522 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
523 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
524 .msg = "hgc_itctl_accbad_intr (0x%x) found: \
525 memory address is 0x%08X\n",
526 .reg = HGC_LM_DFX_STATUS2,
527 },
528 {
529 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
530 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
531 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
532 .msg = "hgc_cqe_accbad_intr (0x%x) found: \
533 Ram address is 0x%08X\n",
534 .reg = HGC_CQE_ECC_ADDR,
535 },
536 {
537 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
538 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
539 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
540 .msg = "rxm_mem0_accbad_intr (0x%x) found: \
541 memory address is 0x%08X\n",
542 .reg = HGC_RXM_DFX_STATUS14,
543 },
544 {
545 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
546 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
547 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
548 .msg = "rxm_mem1_accbad_intr (0x%x) found: \
549 memory address is 0x%08X\n",
550 .reg = HGC_RXM_DFX_STATUS14,
551 },
552 {
553 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
554 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
555 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
556 .msg = "rxm_mem2_accbad_intr (0x%x) found: \
557 memory address is 0x%08X\n",
558 .reg = HGC_RXM_DFX_STATUS14,
559 },
560 {
561 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
562 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
563 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
564 .msg = "rxm_mem3_accbad_intr (0x%x) found: \
565 memory address is 0x%08X\n",
566 .reg = HGC_RXM_DFX_STATUS15,
567 },
568 };
569
570 enum {
571 HISI_SAS_PHY_PHY_UPDOWN,
572 HISI_SAS_PHY_CHNL_INT,
573 HISI_SAS_PHY_INT_NR
574 };
575
576 enum {
577 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
578 TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
579 DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
580 SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
581 DMA_RX_ERR_BASE = 0x60, /* dw3 */
582
583 /* trans tx*/
584 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
585 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
586 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
587 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
588 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
589 RESERVED0, /* 0x5 */
590 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
591 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
592 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
593 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
594 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
595 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
596 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
597 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
598 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
599 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
600 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
601 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
602 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
603 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
604 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
605 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
606 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
607 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
608 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
609 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
610 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
611 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
612 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
613 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
614 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
615 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
616 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
617 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
618 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
619
620 /* trans rx */
621 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
622 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
623 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
624 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
625 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
626 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
627 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
628 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
629 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
630 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
631 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
632 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
633 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
634 RESERVED1, /* 0x2b */
635 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
636 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
637 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
638 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
639 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
640 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
641 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
642 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
643 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
644 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
645 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
646 RESERVED2, /* 0x34 */
647 RESERVED3, /* 0x35 */
648 RESERVED4, /* 0x36 */
649 RESERVED5, /* 0x37 */
650 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
651 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
652 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
653 RESERVED6, /* 0x3b */
654 RESERVED7, /* 0x3c */
655 RESERVED8, /* 0x3d */
656 RESERVED9, /* 0x3e */
657 TRANS_RX_R_ERR, /* 0x3f */
658
659 /* dma tx */
660 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
661 DMA_TX_DIF_APP_ERR, /* 0x41 */
662 DMA_TX_DIF_RPP_ERR, /* 0x42 */
663 DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
664 DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
665 DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
666 DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
667 DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
668 DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
669 DMA_TX_RAM_ECC_ERR, /* 0x49 */
670 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
671 DMA_TX_MAX_ERR_CODE,
672
673 /* sipc rx */
674 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
675 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
676 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
677 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
678 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
679 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
680 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
681 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
682 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
683 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
684 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
685 SIPC_RX_MAX_ERR_CODE,
686
687 /* dma rx */
688 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
689 DMA_RX_DIF_APP_ERR, /* 0x61 */
690 DMA_RX_DIF_RPP_ERR, /* 0x62 */
691 DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
692 DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
693 DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
694 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
695 DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
696 RESERVED10, /* 0x68 */
697 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
698 DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
699 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
700 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
701 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
702 DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
703 DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
704 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
705 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
706 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
707 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
708 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
709 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
710 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
711 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
712 DMA_RX_RAM_ECC_ERR, /* 0x78 */
713 DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
714 DMA_RX_MAX_ERR_CODE,
715 };
716
717 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
718 #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
719
720 #define DIR_NO_DATA 0
721 #define DIR_TO_INI 1
722 #define DIR_TO_DEVICE 2
723 #define DIR_RESERVED 3
724
725 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
726 err_phase == 0x4 || err_phase == 0x8 ||\
727 err_phase == 0x6 || err_phase == 0xa)
728 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
729 err_phase == 0x20 || err_phase == 0x40)
730
731 static void link_timeout_disable_link(unsigned long data);
732
733 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
734 {
735 void __iomem *regs = hisi_hba->regs + off;
736
737 return readl(regs);
738 }
739
740 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
741 {
742 void __iomem *regs = hisi_hba->regs + off;
743
744 return readl_relaxed(regs);
745 }
746
747 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
748 {
749 void __iomem *regs = hisi_hba->regs + off;
750
751 writel(val, regs);
752 }
753
754 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
755 u32 off, u32 val)
756 {
757 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
758
759 writel(val, regs);
760 }
761
762 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
763 int phy_no, u32 off)
764 {
765 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
766
767 return readl(regs);
768 }
769
770 /* This function needs to be protected from pre-emption. */
771 static int
772 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
773 struct domain_device *device)
774 {
775 int sata_dev = dev_is_sata(device);
776 void *bitmap = hisi_hba->slot_index_tags;
777 struct hisi_sas_device *sas_dev = device->lldd_dev;
778 int sata_idx = sas_dev->sata_idx;
779 int start, end;
780
781 if (!sata_dev) {
782 /*
783 * STP link SoC bug workaround: index starts from 1.
784 * additionally, we can only allocate odd IPTT(1~4095)
785 * for SAS/SMP device.
786 */
787 start = 1;
788 end = hisi_hba->slot_index_count;
789 } else {
790 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
791 return -EINVAL;
792
793 /*
794 * For SATA device: allocate even IPTT in this interval
795 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
796 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
797 * SoC bug workaround. So we ignore the first 32 even IPTTs.
798 */
799 start = 64 * (sata_idx + 1);
800 end = 64 * (sata_idx + 2);
801 }
802
803 while (1) {
804 start = find_next_zero_bit(bitmap,
805 hisi_hba->slot_index_count, start);
806 if (start >= end)
807 return -SAS_QUEUE_FULL;
808 /*
809 * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
810 */
811 if (sata_dev ^ (start & 1))
812 break;
813 start++;
814 }
815
816 set_bit(start, bitmap);
817 *slot_idx = start;
818 return 0;
819 }
820
821 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
822 {
823 unsigned int index;
824 struct device *dev = hisi_hba->dev;
825 void *bitmap = hisi_hba->sata_dev_bitmap;
826
827 index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
828 if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
829 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
830 return false;
831 }
832
833 set_bit(index, bitmap);
834 *idx = index;
835 return true;
836 }
837
838
839 static struct
840 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
841 {
842 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
843 struct hisi_sas_device *sas_dev = NULL;
844 int i, sata_dev = dev_is_sata(device);
845 int sata_idx = -1;
846
847 spin_lock(&hisi_hba->lock);
848
849 if (sata_dev)
850 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
851 goto out;
852
853 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
854 /*
855 * SATA device id bit0 should be 0
856 */
857 if (sata_dev && (i & 1))
858 continue;
859 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
860 int queue = i % hisi_hba->queue_count;
861 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
862
863 hisi_hba->devices[i].device_id = i;
864 sas_dev = &hisi_hba->devices[i];
865 sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
866 sas_dev->dev_type = device->dev_type;
867 sas_dev->hisi_hba = hisi_hba;
868 sas_dev->sas_device = device;
869 sas_dev->sata_idx = sata_idx;
870 sas_dev->dq = dq;
871 INIT_LIST_HEAD(&hisi_hba->devices[i].list);
872 break;
873 }
874 }
875
876 out:
877 spin_unlock(&hisi_hba->lock);
878
879 return sas_dev;
880 }
881
882 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
883 {
884 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
885
886 cfg &= ~PHY_CFG_DC_OPT_MSK;
887 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
888 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
889 }
890
891 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
892 {
893 struct sas_identify_frame identify_frame;
894 u32 *identify_buffer;
895
896 memset(&identify_frame, 0, sizeof(identify_frame));
897 identify_frame.dev_type = SAS_END_DEVICE;
898 identify_frame.frame_type = 0;
899 identify_frame._un1 = 1;
900 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
901 identify_frame.target_bits = SAS_PROTOCOL_NONE;
902 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
903 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
904 identify_frame.phy_id = phy_no;
905 identify_buffer = (u32 *)(&identify_frame);
906
907 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
908 __swab32(identify_buffer[0]));
909 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
910 __swab32(identify_buffer[1]));
911 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
912 __swab32(identify_buffer[2]));
913 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
914 __swab32(identify_buffer[3]));
915 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
916 __swab32(identify_buffer[4]));
917 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
918 __swab32(identify_buffer[5]));
919 }
920
921 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
922 struct hisi_sas_device *sas_dev)
923 {
924 struct domain_device *device = sas_dev->sas_device;
925 struct device *dev = hisi_hba->dev;
926 u64 qw0, device_id = sas_dev->device_id;
927 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
928 struct domain_device *parent_dev = device->parent;
929 struct asd_sas_port *sas_port = device->port;
930 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
931
932 memset(itct, 0, sizeof(*itct));
933
934 /* qw0 */
935 qw0 = 0;
936 switch (sas_dev->dev_type) {
937 case SAS_END_DEVICE:
938 case SAS_EDGE_EXPANDER_DEVICE:
939 case SAS_FANOUT_EXPANDER_DEVICE:
940 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
941 break;
942 case SAS_SATA_DEV:
943 case SAS_SATA_PENDING:
944 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
945 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
946 else
947 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
948 break;
949 default:
950 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
951 sas_dev->dev_type);
952 }
953
954 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
955 (device->linkrate << ITCT_HDR_MCR_OFF) |
956 (1 << ITCT_HDR_VLN_OFF) |
957 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
958 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
959 (port->id << ITCT_HDR_PORT_ID_OFF));
960 itct->qw0 = cpu_to_le64(qw0);
961
962 /* qw1 */
963 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
964 itct->sas_addr = __swab64(itct->sas_addr);
965
966 /* qw2 */
967 if (!dev_is_sata(device))
968 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
969 (0x1ULL << ITCT_HDR_BITLT_OFF) |
970 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
971 (0x1ULL << ITCT_HDR_RTOLT_OFF));
972 }
973
974 static void free_device_v2_hw(struct hisi_hba *hisi_hba,
975 struct hisi_sas_device *sas_dev)
976 {
977 u64 dev_id = sas_dev->device_id;
978 struct device *dev = hisi_hba->dev;
979 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
980 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
981 int i;
982
983 /* SoC bug workaround */
984 if (dev_is_sata(sas_dev->sas_device))
985 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
986
987 /* clear the itct interrupt state */
988 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
989 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
990 ENT_INT_SRC3_ITC_INT_MSK);
991
992 /* clear the itct int*/
993 for (i = 0; i < 2; i++) {
994 /* clear the itct table*/
995 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
996 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
997 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
998
999 udelay(10);
1000 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
1001 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
1002 dev_dbg(dev, "got clear ITCT done interrupt\n");
1003
1004 /* invalid the itct state*/
1005 memset(itct, 0, sizeof(struct hisi_sas_itct));
1006 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
1007 ENT_INT_SRC3_ITC_INT_MSK);
1008
1009 /* clear the itct */
1010 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
1011 dev_dbg(dev, "clear ITCT ok\n");
1012 break;
1013 }
1014 }
1015 }
1016
1017 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
1018 {
1019 int i, reset_val;
1020 u32 val;
1021 unsigned long end_time;
1022 struct device *dev = hisi_hba->dev;
1023
1024 /* The mask needs to be set depending on the number of phys */
1025 if (hisi_hba->n_phy == 9)
1026 reset_val = 0x1fffff;
1027 else
1028 reset_val = 0x7ffff;
1029
1030 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1031
1032 /* Disable all of the PHYs */
1033 for (i = 0; i < hisi_hba->n_phy; i++) {
1034 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1035
1036 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1037 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1038 }
1039 udelay(50);
1040
1041 /* Ensure DMA tx & rx idle */
1042 for (i = 0; i < hisi_hba->n_phy; i++) {
1043 u32 dma_tx_status, dma_rx_status;
1044
1045 end_time = jiffies + msecs_to_jiffies(1000);
1046
1047 while (1) {
1048 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1049 DMA_TX_STATUS);
1050 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1051 DMA_RX_STATUS);
1052
1053 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1054 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1055 break;
1056
1057 msleep(20);
1058 if (time_after(jiffies, end_time))
1059 return -EIO;
1060 }
1061 }
1062
1063 /* Ensure axi bus idle */
1064 end_time = jiffies + msecs_to_jiffies(1000);
1065 while (1) {
1066 u32 axi_status =
1067 hisi_sas_read32(hisi_hba, AXI_CFG);
1068
1069 if (axi_status == 0)
1070 break;
1071
1072 msleep(20);
1073 if (time_after(jiffies, end_time))
1074 return -EIO;
1075 }
1076
1077 if (ACPI_HANDLE(dev)) {
1078 acpi_status s;
1079
1080 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1081 if (ACPI_FAILURE(s)) {
1082 dev_err(dev, "Reset failed\n");
1083 return -EIO;
1084 }
1085 } else if (hisi_hba->ctrl) {
1086 /* reset and disable clock*/
1087 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1088 reset_val);
1089 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1090 reset_val);
1091 msleep(1);
1092 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1093 if (reset_val != (val & reset_val)) {
1094 dev_err(dev, "SAS reset fail.\n");
1095 return -EIO;
1096 }
1097
1098 /* De-reset and enable clock*/
1099 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1100 reset_val);
1101 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1102 reset_val);
1103 msleep(1);
1104 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1105 &val);
1106 if (val & reset_val) {
1107 dev_err(dev, "SAS de-reset fail.\n");
1108 return -EIO;
1109 }
1110 } else
1111 dev_warn(dev, "no reset method\n");
1112
1113 return 0;
1114 }
1115
1116 /* This function needs to be called after resetting SAS controller. */
1117 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1118 {
1119 u32 cfg;
1120 int phy_no;
1121
1122 hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1123 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1124 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1125 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1126 continue;
1127
1128 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1129 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1130 }
1131 }
1132
1133 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1134 {
1135 int phy_no;
1136 u32 dma_tx_dfx1;
1137
1138 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1139 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1140 continue;
1141
1142 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1143 DMA_TX_DFX1);
1144 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1145 u32 cfg = hisi_sas_phy_read32(hisi_hba,
1146 phy_no, CON_CONTROL);
1147
1148 cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1149 hisi_sas_phy_write32(hisi_hba, phy_no,
1150 CON_CONTROL, cfg);
1151 clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1152 }
1153 }
1154 }
1155
1156 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1157 {
1158 struct device *dev = hisi_hba->dev;
1159 int i;
1160
1161 /* Global registers init */
1162
1163 /* Deal with am-max-transmissions quirk */
1164 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1165 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1166 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1167 0x2020);
1168 } /* Else, use defaults -> do nothing */
1169
1170 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1171 (u32)((1ULL << hisi_hba->queue_count) - 1));
1172 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1173 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1174 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1175 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1176 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1177 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1178 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1179 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1180 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1181 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1182 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1183 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1184 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1185 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1186 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1187 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1188 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1189 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1190 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1191 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1192 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1193 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1194 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
1195 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1196 for (i = 0; i < hisi_hba->queue_count; i++)
1197 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1198
1199 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1200 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1201
1202 for (i = 0; i < hisi_hba->n_phy; i++) {
1203 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
1204 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
1205 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1206 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1207 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1208 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1209 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1210 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1211 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1212 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1213 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1214 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
1215 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1216 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1217 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1218 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1219 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1220 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1221 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1222 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1223 if (hisi_hba->refclk_frequency_mhz == 66)
1224 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1225 /* else, do nothing -> leave it how you found it */
1226 }
1227
1228 for (i = 0; i < hisi_hba->queue_count; i++) {
1229 /* Delivery queue */
1230 hisi_sas_write32(hisi_hba,
1231 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1232 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1233
1234 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1235 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1236
1237 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1238 HISI_SAS_QUEUE_SLOTS);
1239
1240 /* Completion queue */
1241 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1242 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1243
1244 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1245 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1246
1247 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1248 HISI_SAS_QUEUE_SLOTS);
1249 }
1250
1251 /* itct */
1252 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1253 lower_32_bits(hisi_hba->itct_dma));
1254
1255 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1256 upper_32_bits(hisi_hba->itct_dma));
1257
1258 /* iost */
1259 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1260 lower_32_bits(hisi_hba->iost_dma));
1261
1262 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1263 upper_32_bits(hisi_hba->iost_dma));
1264
1265 /* breakpoint */
1266 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1267 lower_32_bits(hisi_hba->breakpoint_dma));
1268
1269 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1270 upper_32_bits(hisi_hba->breakpoint_dma));
1271
1272 /* SATA broken msg */
1273 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1274 lower_32_bits(hisi_hba->sata_breakpoint_dma));
1275
1276 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1277 upper_32_bits(hisi_hba->sata_breakpoint_dma));
1278
1279 /* SATA initial fis */
1280 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1281 lower_32_bits(hisi_hba->initial_fis_dma));
1282
1283 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1284 upper_32_bits(hisi_hba->initial_fis_dma));
1285 }
1286
1287 static void link_timeout_enable_link(unsigned long data)
1288 {
1289 struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
1290 int i, reg_val;
1291
1292 for (i = 0; i < hisi_hba->n_phy; i++) {
1293 if (hisi_hba->reject_stp_links_msk & BIT(i))
1294 continue;
1295
1296 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1297 if (!(reg_val & BIT(0))) {
1298 hisi_sas_phy_write32(hisi_hba, i,
1299 CON_CONTROL, 0x7);
1300 break;
1301 }
1302 }
1303
1304 hisi_hba->timer.function = link_timeout_disable_link;
1305 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1306 }
1307
1308 static void link_timeout_disable_link(unsigned long data)
1309 {
1310 struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
1311 int i, reg_val;
1312
1313 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1314 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1315 if (hisi_hba->reject_stp_links_msk & BIT(i))
1316 continue;
1317
1318 if (reg_val & BIT(i)) {
1319 hisi_sas_phy_write32(hisi_hba, i,
1320 CON_CONTROL, 0x6);
1321 break;
1322 }
1323 }
1324
1325 hisi_hba->timer.function = link_timeout_enable_link;
1326 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1327 }
1328
1329 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1330 {
1331 hisi_hba->timer.data = (unsigned long)hisi_hba;
1332 hisi_hba->timer.function = link_timeout_disable_link;
1333 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1334 add_timer(&hisi_hba->timer);
1335 }
1336
1337 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1338 {
1339 struct device *dev = hisi_hba->dev;
1340 int rc;
1341
1342 rc = reset_hw_v2_hw(hisi_hba);
1343 if (rc) {
1344 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1345 return rc;
1346 }
1347
1348 msleep(100);
1349 init_reg_v2_hw(hisi_hba);
1350
1351 return 0;
1352 }
1353
1354 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1355 {
1356 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1357
1358 cfg |= PHY_CFG_ENA_MSK;
1359 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1360 }
1361
1362 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1363 {
1364 u32 context;
1365
1366 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1367 if (context & (1 << phy_no))
1368 return true;
1369
1370 return false;
1371 }
1372
1373 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1374 {
1375 u32 dfx_val;
1376
1377 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1378
1379 if (dfx_val & BIT(16))
1380 return false;
1381
1382 return true;
1383 }
1384
1385 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1386 {
1387 int i, max_loop = 1000;
1388 struct device *dev = hisi_hba->dev;
1389 u32 status, axi_status, dfx_val, dfx_tx_val;
1390
1391 for (i = 0; i < max_loop; i++) {
1392 status = hisi_sas_read32_relaxed(hisi_hba,
1393 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1394
1395 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1396 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1397 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1398 phy_no, DMA_TX_FIFO_DFX0);
1399
1400 if ((status == 0x3) && (axi_status == 0x0) &&
1401 (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1402 return true;
1403 udelay(10);
1404 }
1405 dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1406 phy_no, status, axi_status,
1407 dfx_val, dfx_tx_val);
1408 return false;
1409 }
1410
1411 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1412 {
1413 int i, max_loop = 1000;
1414 struct device *dev = hisi_hba->dev;
1415 u32 status, tx_dfx0;
1416
1417 for (i = 0; i < max_loop; i++) {
1418 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1419 status = (status & 0x3fc0) >> 6;
1420
1421 if (status != 0x1)
1422 return true;
1423
1424 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1425 if ((tx_dfx0 & 0x1ff) == 0x2)
1426 return true;
1427 udelay(10);
1428 }
1429 dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1430 phy_no, status, tx_dfx0);
1431 return false;
1432 }
1433
1434 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1435 {
1436 if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1437 return true;
1438
1439 if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1440 return false;
1441
1442 if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1443 return false;
1444
1445 return true;
1446 }
1447
1448
1449 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1450 {
1451 u32 cfg, axi_val, dfx0_val, txid_auto;
1452 struct device *dev = hisi_hba->dev;
1453
1454 /* Close axi bus. */
1455 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1456 AM_CTRL_GLOBAL);
1457 axi_val |= 0x1;
1458 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1459 AM_CTRL_GLOBAL, axi_val);
1460
1461 if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1462 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1463 goto do_disable;
1464
1465 /* Reset host controller. */
1466 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1467 return;
1468 }
1469
1470 dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1471 dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1472 if (dfx0_val != 0x4)
1473 goto do_disable;
1474
1475 if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1476 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1477 phy_no);
1478 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1479 TXID_AUTO);
1480 txid_auto |= TXID_AUTO_CTB_MSK;
1481 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1482 txid_auto);
1483 }
1484
1485 do_disable:
1486 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1487 cfg &= ~PHY_CFG_ENA_MSK;
1488 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1489
1490 /* Open axi bus. */
1491 axi_val &= ~0x1;
1492 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1493 AM_CTRL_GLOBAL, axi_val);
1494 }
1495
1496 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1497 {
1498 config_id_frame_v2_hw(hisi_hba, phy_no);
1499 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1500 enable_phy_v2_hw(hisi_hba, phy_no);
1501 }
1502
1503 static void stop_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1504 {
1505 disable_phy_v2_hw(hisi_hba, phy_no);
1506 }
1507
1508 static void stop_phys_v2_hw(struct hisi_hba *hisi_hba)
1509 {
1510 int i;
1511
1512 for (i = 0; i < hisi_hba->n_phy; i++)
1513 stop_phy_v2_hw(hisi_hba, i);
1514 }
1515
1516 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1517 {
1518 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1519 u32 txid_auto;
1520
1521 stop_phy_v2_hw(hisi_hba, phy_no);
1522 if (phy->identify.device_type == SAS_END_DEVICE) {
1523 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1524 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1525 txid_auto | TX_HARDRST_MSK);
1526 }
1527 msleep(100);
1528 start_phy_v2_hw(hisi_hba, phy_no);
1529 }
1530
1531 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1532 {
1533 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1534 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1535 struct sas_phy *sphy = sas_phy->phy;
1536 u32 err4_reg_val, err6_reg_val;
1537
1538 /* loss dword syn, phy reset problem */
1539 err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1540
1541 /* disparity err, invalid dword */
1542 err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1543
1544 sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1545 sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1546 sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1547 sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1548 }
1549
1550 static void start_phys_v2_hw(struct hisi_hba *hisi_hba)
1551 {
1552 int i;
1553
1554 for (i = 0; i < hisi_hba->n_phy; i++) {
1555 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1556 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1557
1558 if (!sas_phy->phy->enabled)
1559 continue;
1560
1561 start_phy_v2_hw(hisi_hba, i);
1562 }
1563 }
1564
1565 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1566 {
1567 start_phys_v2_hw(hisi_hba);
1568 }
1569
1570 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1571 {
1572 u32 sl_control;
1573
1574 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1575 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1576 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1577 msleep(1);
1578 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1579 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1580 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1581 }
1582
1583 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1584 {
1585 return SAS_LINK_RATE_12_0_GBPS;
1586 }
1587
1588 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1589 struct sas_phy_linkrates *r)
1590 {
1591 u32 prog_phy_link_rate =
1592 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1593 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1594 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1595 int i;
1596 enum sas_linkrate min, max;
1597 u32 rate_mask = 0;
1598
1599 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1600 max = sas_phy->phy->maximum_linkrate;
1601 min = r->minimum_linkrate;
1602 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1603 max = r->maximum_linkrate;
1604 min = sas_phy->phy->minimum_linkrate;
1605 } else
1606 return;
1607
1608 sas_phy->phy->maximum_linkrate = max;
1609 sas_phy->phy->minimum_linkrate = min;
1610
1611 min -= SAS_LINK_RATE_1_5_GBPS;
1612 max -= SAS_LINK_RATE_1_5_GBPS;
1613
1614 for (i = 0; i <= max; i++)
1615 rate_mask |= 1 << (i * 2);
1616
1617 prog_phy_link_rate &= ~0xff;
1618 prog_phy_link_rate |= rate_mask;
1619
1620 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1621 prog_phy_link_rate);
1622
1623 phy_hard_reset_v2_hw(hisi_hba, phy_no);
1624 }
1625
1626 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1627 {
1628 int i, bitmap = 0;
1629 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1630 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1631
1632 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1633 if (phy_state & 1 << i)
1634 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1635 bitmap |= 1 << i;
1636
1637 if (hisi_hba->n_phy == 9) {
1638 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1639
1640 if (phy_state & 1 << 8)
1641 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1642 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1643 bitmap |= 1 << 9;
1644 }
1645
1646 return bitmap;
1647 }
1648
1649 /*
1650 * The callpath to this function and upto writing the write
1651 * queue pointer should be safe from interruption.
1652 */
1653 static int
1654 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1655 {
1656 struct device *dev = hisi_hba->dev;
1657 int queue = dq->id;
1658 u32 r, w;
1659
1660 w = dq->wr_point;
1661 r = hisi_sas_read32_relaxed(hisi_hba,
1662 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1663 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1664 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
1665 queue, r, w);
1666 return -EAGAIN;
1667 }
1668
1669 return 0;
1670 }
1671
1672 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1673 {
1674 struct hisi_hba *hisi_hba = dq->hisi_hba;
1675 int dlvry_queue = dq->slot_prep->dlvry_queue;
1676 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
1677
1678 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1679 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1680 dq->wr_point);
1681 }
1682
1683 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1684 struct hisi_sas_slot *slot,
1685 struct hisi_sas_cmd_hdr *hdr,
1686 struct scatterlist *scatter,
1687 int n_elem)
1688 {
1689 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1690 struct device *dev = hisi_hba->dev;
1691 struct scatterlist *sg;
1692 int i;
1693
1694 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1695 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1696 n_elem);
1697 return -EINVAL;
1698 }
1699
1700 for_each_sg(scatter, sg, n_elem, i) {
1701 struct hisi_sas_sge *entry = &sge_page->sge[i];
1702
1703 entry->addr = cpu_to_le64(sg_dma_address(sg));
1704 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1705 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1706 entry->data_off = 0;
1707 }
1708
1709 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1710
1711 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1712
1713 return 0;
1714 }
1715
1716 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1717 struct hisi_sas_slot *slot)
1718 {
1719 struct sas_task *task = slot->task;
1720 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1721 struct domain_device *device = task->dev;
1722 struct device *dev = hisi_hba->dev;
1723 struct hisi_sas_port *port = slot->port;
1724 struct scatterlist *sg_req, *sg_resp;
1725 struct hisi_sas_device *sas_dev = device->lldd_dev;
1726 dma_addr_t req_dma_addr;
1727 unsigned int req_len, resp_len;
1728 int elem, rc;
1729
1730 /*
1731 * DMA-map SMP request, response buffers
1732 */
1733 /* req */
1734 sg_req = &task->smp_task.smp_req;
1735 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1736 if (!elem)
1737 return -ENOMEM;
1738 req_len = sg_dma_len(sg_req);
1739 req_dma_addr = sg_dma_address(sg_req);
1740
1741 /* resp */
1742 sg_resp = &task->smp_task.smp_resp;
1743 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1744 if (!elem) {
1745 rc = -ENOMEM;
1746 goto err_out_req;
1747 }
1748 resp_len = sg_dma_len(sg_resp);
1749 if ((req_len & 0x3) || (resp_len & 0x3)) {
1750 rc = -EINVAL;
1751 goto err_out_resp;
1752 }
1753
1754 /* create header */
1755 /* dw0 */
1756 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1757 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1758 (2 << CMD_HDR_CMD_OFF)); /* smp */
1759
1760 /* map itct entry */
1761 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1762 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1763 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1764
1765 /* dw2 */
1766 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1767 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1768 CMD_HDR_MRFL_OFF));
1769
1770 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1771
1772 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1773 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1774
1775 return 0;
1776
1777 err_out_resp:
1778 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1779 DMA_FROM_DEVICE);
1780 err_out_req:
1781 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1782 DMA_TO_DEVICE);
1783 return rc;
1784 }
1785
1786 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1787 struct hisi_sas_slot *slot, int is_tmf,
1788 struct hisi_sas_tmf_task *tmf)
1789 {
1790 struct sas_task *task = slot->task;
1791 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1792 struct domain_device *device = task->dev;
1793 struct hisi_sas_device *sas_dev = device->lldd_dev;
1794 struct hisi_sas_port *port = slot->port;
1795 struct sas_ssp_task *ssp_task = &task->ssp_task;
1796 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1797 int has_data = 0, rc, priority = is_tmf;
1798 u8 *buf_cmd;
1799 u32 dw1 = 0, dw2 = 0;
1800
1801 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1802 (2 << CMD_HDR_TLR_CTRL_OFF) |
1803 (port->id << CMD_HDR_PORT_OFF) |
1804 (priority << CMD_HDR_PRIORITY_OFF) |
1805 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1806
1807 dw1 = 1 << CMD_HDR_VDTL_OFF;
1808 if (is_tmf) {
1809 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1810 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1811 } else {
1812 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1813 switch (scsi_cmnd->sc_data_direction) {
1814 case DMA_TO_DEVICE:
1815 has_data = 1;
1816 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1817 break;
1818 case DMA_FROM_DEVICE:
1819 has_data = 1;
1820 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1821 break;
1822 default:
1823 dw1 &= ~CMD_HDR_DIR_MSK;
1824 }
1825 }
1826
1827 /* map itct entry */
1828 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1829 hdr->dw1 = cpu_to_le32(dw1);
1830
1831 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1832 + 3) / 4) << CMD_HDR_CFL_OFF) |
1833 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1834 (2 << CMD_HDR_SG_MOD_OFF);
1835 hdr->dw2 = cpu_to_le32(dw2);
1836
1837 hdr->transfer_tags = cpu_to_le32(slot->idx);
1838
1839 if (has_data) {
1840 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1841 slot->n_elem);
1842 if (rc)
1843 return rc;
1844 }
1845
1846 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1847 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1848 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1849
1850 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1851 sizeof(struct ssp_frame_hdr);
1852
1853 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1854 if (!is_tmf) {
1855 buf_cmd[9] = task->ssp_task.task_attr |
1856 (task->ssp_task.task_prio << 3);
1857 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1858 task->ssp_task.cmd->cmd_len);
1859 } else {
1860 buf_cmd[10] = tmf->tmf;
1861 switch (tmf->tmf) {
1862 case TMF_ABORT_TASK:
1863 case TMF_QUERY_TASK:
1864 buf_cmd[12] =
1865 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1866 buf_cmd[13] =
1867 tmf->tag_of_task_to_be_managed & 0xff;
1868 break;
1869 default:
1870 break;
1871 }
1872 }
1873
1874 return 0;
1875 }
1876
1877 #define TRANS_TX_ERR 0
1878 #define TRANS_RX_ERR 1
1879 #define DMA_TX_ERR 2
1880 #define SIPC_RX_ERR 3
1881 #define DMA_RX_ERR 4
1882
1883 #define DMA_TX_ERR_OFF 0
1884 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1885 #define SIPC_RX_ERR_OFF 16
1886 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1887
1888 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1889 {
1890 static const u8 trans_tx_err_code_prio[] = {
1891 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1892 TRANS_TX_ERR_PHY_NOT_ENABLE,
1893 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1894 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1895 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1896 RESERVED0,
1897 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1898 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1899 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1900 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1901 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1902 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1903 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1904 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1905 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1906 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1907 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1908 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1909 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1910 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1911 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1912 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1913 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1914 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1915 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1916 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1917 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1918 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1919 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1920 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1921 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1922 };
1923 int index, i;
1924
1925 for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1926 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1927 if (err_msk & (1 << index))
1928 return trans_tx_err_code_prio[i];
1929 }
1930 return -1;
1931 }
1932
1933 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1934 {
1935 static const u8 trans_rx_err_code_prio[] = {
1936 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1937 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1938 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1939 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1940 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1941 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1942 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1943 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1944 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1945 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1946 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1947 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1948 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1949 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1950 RESERVED1,
1951 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1952 TRANS_RX_ERR_WITH_DATA_LEN0,
1953 TRANS_RX_ERR_WITH_BAD_HASH,
1954 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1955 TRANS_RX_SSP_FRM_LEN_ERR,
1956 RESERVED2,
1957 RESERVED3,
1958 RESERVED4,
1959 RESERVED5,
1960 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1961 TRANS_RX_SMP_FRM_LEN_ERR,
1962 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1963 RESERVED6,
1964 RESERVED7,
1965 RESERVED8,
1966 RESERVED9,
1967 TRANS_RX_R_ERR,
1968 };
1969 int index, i;
1970
1971 for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1972 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1973 if (err_msk & (1 << index))
1974 return trans_rx_err_code_prio[i];
1975 }
1976 return -1;
1977 }
1978
1979 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1980 {
1981 static const u8 dma_tx_err_code_prio[] = {
1982 DMA_TX_UNEXP_XFER_ERR,
1983 DMA_TX_UNEXP_RETRANS_ERR,
1984 DMA_TX_XFER_LEN_OVERFLOW,
1985 DMA_TX_XFER_OFFSET_ERR,
1986 DMA_TX_RAM_ECC_ERR,
1987 DMA_TX_DIF_LEN_ALIGN_ERR,
1988 DMA_TX_DIF_CRC_ERR,
1989 DMA_TX_DIF_APP_ERR,
1990 DMA_TX_DIF_RPP_ERR,
1991 DMA_TX_DATA_SGL_OVERFLOW,
1992 DMA_TX_DIF_SGL_OVERFLOW,
1993 };
1994 int index, i;
1995
1996 for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1997 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1998 err_msk = err_msk & DMA_TX_ERR_MSK;
1999 if (err_msk & (1 << index))
2000 return dma_tx_err_code_prio[i];
2001 }
2002 return -1;
2003 }
2004
2005 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
2006 {
2007 static const u8 sipc_rx_err_code_prio[] = {
2008 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
2009 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
2010 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
2011 SIPC_RX_WRSETUP_LEN_ODD_ERR,
2012 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
2013 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
2014 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
2015 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
2016 SIPC_RX_SATA_UNEXP_FIS_ERR,
2017 SIPC_RX_WRSETUP_ESTATUS_ERR,
2018 SIPC_RX_DATA_UNDERFLOW_ERR,
2019 };
2020 int index, i;
2021
2022 for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
2023 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
2024 err_msk = err_msk & SIPC_RX_ERR_MSK;
2025 if (err_msk & (1 << (index + 0x10)))
2026 return sipc_rx_err_code_prio[i];
2027 }
2028 return -1;
2029 }
2030
2031 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
2032 {
2033 static const u8 dma_rx_err_code_prio[] = {
2034 DMA_RX_UNKNOWN_FRM_ERR,
2035 DMA_RX_DATA_LEN_OVERFLOW,
2036 DMA_RX_DATA_LEN_UNDERFLOW,
2037 DMA_RX_DATA_OFFSET_ERR,
2038 RESERVED10,
2039 DMA_RX_SATA_FRAME_TYPE_ERR,
2040 DMA_RX_RESP_BUF_OVERFLOW,
2041 DMA_RX_UNEXP_RETRANS_RESP_ERR,
2042 DMA_RX_UNEXP_NORM_RESP_ERR,
2043 DMA_RX_UNEXP_RDFRAME_ERR,
2044 DMA_RX_PIO_DATA_LEN_ERR,
2045 DMA_RX_RDSETUP_STATUS_ERR,
2046 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2047 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2048 DMA_RX_RDSETUP_LEN_ODD_ERR,
2049 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2050 DMA_RX_RDSETUP_LEN_OVER_ERR,
2051 DMA_RX_RDSETUP_OFFSET_ERR,
2052 DMA_RX_RDSETUP_ACTIVE_ERR,
2053 DMA_RX_RDSETUP_ESTATUS_ERR,
2054 DMA_RX_RAM_ECC_ERR,
2055 DMA_RX_DIF_CRC_ERR,
2056 DMA_RX_DIF_APP_ERR,
2057 DMA_RX_DIF_RPP_ERR,
2058 DMA_RX_DATA_SGL_OVERFLOW,
2059 DMA_RX_DIF_SGL_OVERFLOW,
2060 };
2061 int index, i;
2062
2063 for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2064 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2065 if (err_msk & (1 << index))
2066 return dma_rx_err_code_prio[i];
2067 }
2068 return -1;
2069 }
2070
2071 /* by default, task resp is complete */
2072 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2073 struct sas_task *task,
2074 struct hisi_sas_slot *slot,
2075 int err_phase)
2076 {
2077 struct task_status_struct *ts = &task->task_status;
2078 struct hisi_sas_err_record_v2 *err_record =
2079 hisi_sas_status_buf_addr_mem(slot);
2080 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2081 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2082 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2083 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2084 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2085 int error = -1;
2086
2087 if (err_phase == 1) {
2088 /* error in TX phase, the priority of error is: DW2 > DW0 */
2089 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2090 if (error == -1)
2091 error = parse_trans_tx_err_code_v2_hw(
2092 trans_tx_fail_type);
2093 } else if (err_phase == 2) {
2094 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2095 error = parse_trans_rx_err_code_v2_hw(
2096 trans_rx_fail_type);
2097 if (error == -1) {
2098 error = parse_dma_rx_err_code_v2_hw(
2099 dma_rx_err_type);
2100 if (error == -1)
2101 error = parse_sipc_rx_err_code_v2_hw(
2102 sipc_rx_err_type);
2103 }
2104 }
2105
2106 switch (task->task_proto) {
2107 case SAS_PROTOCOL_SSP:
2108 {
2109 switch (error) {
2110 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2111 {
2112 ts->stat = SAS_OPEN_REJECT;
2113 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2114 break;
2115 }
2116 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2117 {
2118 ts->stat = SAS_OPEN_REJECT;
2119 ts->open_rej_reason = SAS_OREJ_EPROTO;
2120 break;
2121 }
2122 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2123 {
2124 ts->stat = SAS_OPEN_REJECT;
2125 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2126 break;
2127 }
2128 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2129 {
2130 ts->stat = SAS_OPEN_REJECT;
2131 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2132 break;
2133 }
2134 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2135 {
2136 ts->stat = SAS_OPEN_REJECT;
2137 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2138 break;
2139 }
2140 case DMA_RX_UNEXP_NORM_RESP_ERR:
2141 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2142 case DMA_RX_RESP_BUF_OVERFLOW:
2143 {
2144 ts->stat = SAS_OPEN_REJECT;
2145 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2146 break;
2147 }
2148 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2149 {
2150 /* not sure */
2151 ts->stat = SAS_DEV_NO_RESPONSE;
2152 break;
2153 }
2154 case DMA_RX_DATA_LEN_OVERFLOW:
2155 {
2156 ts->stat = SAS_DATA_OVERRUN;
2157 ts->residual = 0;
2158 break;
2159 }
2160 case DMA_RX_DATA_LEN_UNDERFLOW:
2161 {
2162 ts->residual = trans_tx_fail_type;
2163 ts->stat = SAS_DATA_UNDERRUN;
2164 break;
2165 }
2166 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2167 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2168 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2169 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2170 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2171 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2172 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2173 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2174 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2175 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2176 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2177 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2178 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2179 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2180 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2181 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2182 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2183 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2184 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2185 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2186 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2187 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2188 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2189 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2190 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2191 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2192 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2193 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2194 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2195 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2196 case TRANS_TX_ERR_FRAME_TXED:
2197 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2198 case TRANS_RX_ERR_WITH_DATA_LEN0:
2199 case TRANS_RX_ERR_WITH_BAD_HASH:
2200 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2201 case TRANS_RX_SSP_FRM_LEN_ERR:
2202 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2203 case DMA_TX_DATA_SGL_OVERFLOW:
2204 case DMA_TX_UNEXP_XFER_ERR:
2205 case DMA_TX_UNEXP_RETRANS_ERR:
2206 case DMA_TX_XFER_LEN_OVERFLOW:
2207 case DMA_TX_XFER_OFFSET_ERR:
2208 case SIPC_RX_DATA_UNDERFLOW_ERR:
2209 case DMA_RX_DATA_SGL_OVERFLOW:
2210 case DMA_RX_DATA_OFFSET_ERR:
2211 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2212 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2213 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2214 case DMA_RX_SATA_FRAME_TYPE_ERR:
2215 case DMA_RX_UNKNOWN_FRM_ERR:
2216 {
2217 /* This will request a retry */
2218 ts->stat = SAS_QUEUE_FULL;
2219 slot->abort = 1;
2220 break;
2221 }
2222 default:
2223 break;
2224 }
2225 }
2226 break;
2227 case SAS_PROTOCOL_SMP:
2228 ts->stat = SAM_STAT_CHECK_CONDITION;
2229 break;
2230
2231 case SAS_PROTOCOL_SATA:
2232 case SAS_PROTOCOL_STP:
2233 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2234 {
2235 switch (error) {
2236 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2237 {
2238 ts->stat = SAS_OPEN_REJECT;
2239 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2240 break;
2241 }
2242 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2243 {
2244 ts->resp = SAS_TASK_UNDELIVERED;
2245 ts->stat = SAS_DEV_NO_RESPONSE;
2246 break;
2247 }
2248 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2249 {
2250 ts->stat = SAS_OPEN_REJECT;
2251 ts->open_rej_reason = SAS_OREJ_EPROTO;
2252 break;
2253 }
2254 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2255 {
2256 ts->stat = SAS_OPEN_REJECT;
2257 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2258 break;
2259 }
2260 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2261 {
2262 ts->stat = SAS_OPEN_REJECT;
2263 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2264 break;
2265 }
2266 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2267 {
2268 ts->stat = SAS_OPEN_REJECT;
2269 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2270 break;
2271 }
2272 case DMA_RX_RESP_BUF_OVERFLOW:
2273 case DMA_RX_UNEXP_NORM_RESP_ERR:
2274 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2275 {
2276 ts->stat = SAS_OPEN_REJECT;
2277 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2278 break;
2279 }
2280 case DMA_RX_DATA_LEN_OVERFLOW:
2281 {
2282 ts->stat = SAS_DATA_OVERRUN;
2283 ts->residual = 0;
2284 break;
2285 }
2286 case DMA_RX_DATA_LEN_UNDERFLOW:
2287 {
2288 ts->residual = trans_tx_fail_type;
2289 ts->stat = SAS_DATA_UNDERRUN;
2290 break;
2291 }
2292 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2293 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2294 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2295 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2296 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2297 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2298 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2299 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2300 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2301 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2302 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2303 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2304 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2305 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2306 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2307 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2308 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2309 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2310 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2311 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2312 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2313 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2314 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2315 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2316 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2317 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2318 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2319 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2320 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2321 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2322 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2323 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2324 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2325 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2326 case TRANS_RX_ERR_WITH_DATA_LEN0:
2327 case TRANS_RX_ERR_WITH_BAD_HASH:
2328 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2329 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2330 case DMA_TX_DATA_SGL_OVERFLOW:
2331 case DMA_TX_UNEXP_XFER_ERR:
2332 case DMA_TX_UNEXP_RETRANS_ERR:
2333 case DMA_TX_XFER_LEN_OVERFLOW:
2334 case DMA_TX_XFER_OFFSET_ERR:
2335 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2336 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2337 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2338 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2339 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2340 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2341 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2342 case DMA_RX_DATA_SGL_OVERFLOW:
2343 case DMA_RX_DATA_OFFSET_ERR:
2344 case DMA_RX_SATA_FRAME_TYPE_ERR:
2345 case DMA_RX_UNEXP_RDFRAME_ERR:
2346 case DMA_RX_PIO_DATA_LEN_ERR:
2347 case DMA_RX_RDSETUP_STATUS_ERR:
2348 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2349 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2350 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2351 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2352 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2353 case DMA_RX_RDSETUP_OFFSET_ERR:
2354 case DMA_RX_RDSETUP_ACTIVE_ERR:
2355 case DMA_RX_RDSETUP_ESTATUS_ERR:
2356 case DMA_RX_UNKNOWN_FRM_ERR:
2357 case TRANS_RX_SSP_FRM_LEN_ERR:
2358 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2359 {
2360 slot->abort = 1;
2361 ts->stat = SAS_PHY_DOWN;
2362 break;
2363 }
2364 default:
2365 {
2366 ts->stat = SAS_PROTO_RESPONSE;
2367 break;
2368 }
2369 }
2370 hisi_sas_sata_done(task, slot);
2371 }
2372 break;
2373 default:
2374 break;
2375 }
2376 }
2377
2378 static int
2379 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2380 {
2381 struct sas_task *task = slot->task;
2382 struct hisi_sas_device *sas_dev;
2383 struct device *dev = hisi_hba->dev;
2384 struct task_status_struct *ts;
2385 struct domain_device *device;
2386 enum exec_status sts;
2387 struct hisi_sas_complete_v2_hdr *complete_queue =
2388 hisi_hba->complete_hdr[slot->cmplt_queue];
2389 struct hisi_sas_complete_v2_hdr *complete_hdr =
2390 &complete_queue[slot->cmplt_queue_slot];
2391 unsigned long flags;
2392 int aborted;
2393
2394 if (unlikely(!task || !task->lldd_task || !task->dev))
2395 return -EINVAL;
2396
2397 ts = &task->task_status;
2398 device = task->dev;
2399 sas_dev = device->lldd_dev;
2400
2401 spin_lock_irqsave(&task->task_state_lock, flags);
2402 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
2403 task->task_state_flags &=
2404 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2405 spin_unlock_irqrestore(&task->task_state_lock, flags);
2406
2407 memset(ts, 0, sizeof(*ts));
2408 ts->resp = SAS_TASK_COMPLETE;
2409
2410 if (unlikely(aborted)) {
2411 ts->stat = SAS_ABORTED_TASK;
2412 hisi_sas_slot_task_free(hisi_hba, task, slot);
2413 return -1;
2414 }
2415
2416 if (unlikely(!sas_dev)) {
2417 dev_dbg(dev, "slot complete: port has no device\n");
2418 ts->stat = SAS_PHY_DOWN;
2419 goto out;
2420 }
2421
2422 /* Use SAS+TMF status codes */
2423 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2424 >> CMPLT_HDR_ABORT_STAT_OFF) {
2425 case STAT_IO_ABORTED:
2426 /* this io has been aborted by abort command */
2427 ts->stat = SAS_ABORTED_TASK;
2428 goto out;
2429 case STAT_IO_COMPLETE:
2430 /* internal abort command complete */
2431 ts->stat = TMF_RESP_FUNC_SUCC;
2432 del_timer(&slot->internal_abort_timer);
2433 goto out;
2434 case STAT_IO_NO_DEVICE:
2435 ts->stat = TMF_RESP_FUNC_COMPLETE;
2436 del_timer(&slot->internal_abort_timer);
2437 goto out;
2438 case STAT_IO_NOT_VALID:
2439 /* abort single io, controller don't find
2440 * the io need to abort
2441 */
2442 ts->stat = TMF_RESP_FUNC_FAILED;
2443 del_timer(&slot->internal_abort_timer);
2444 goto out;
2445 default:
2446 break;
2447 }
2448
2449 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2450 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2451 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2452 >> CMPLT_HDR_ERR_PHASE_OFF;
2453
2454 /* Analyse error happens on which phase TX or RX */
2455 if (ERR_ON_TX_PHASE(err_phase))
2456 slot_err_v2_hw(hisi_hba, task, slot, 1);
2457 else if (ERR_ON_RX_PHASE(err_phase))
2458 slot_err_v2_hw(hisi_hba, task, slot, 2);
2459
2460 if (unlikely(slot->abort))
2461 return ts->stat;
2462 goto out;
2463 }
2464
2465 switch (task->task_proto) {
2466 case SAS_PROTOCOL_SSP:
2467 {
2468 struct hisi_sas_status_buffer *status_buffer =
2469 hisi_sas_status_buf_addr_mem(slot);
2470 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2471 &status_buffer->iu[0];
2472
2473 sas_ssp_task_response(dev, task, iu);
2474 break;
2475 }
2476 case SAS_PROTOCOL_SMP:
2477 {
2478 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2479 void *to;
2480
2481 ts->stat = SAM_STAT_GOOD;
2482 to = kmap_atomic(sg_page(sg_resp));
2483
2484 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2485 DMA_FROM_DEVICE);
2486 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2487 DMA_TO_DEVICE);
2488 memcpy(to + sg_resp->offset,
2489 hisi_sas_status_buf_addr_mem(slot) +
2490 sizeof(struct hisi_sas_err_record),
2491 sg_dma_len(sg_resp));
2492 kunmap_atomic(to);
2493 break;
2494 }
2495 case SAS_PROTOCOL_SATA:
2496 case SAS_PROTOCOL_STP:
2497 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2498 {
2499 ts->stat = SAM_STAT_GOOD;
2500 hisi_sas_sata_done(task, slot);
2501 break;
2502 }
2503 default:
2504 ts->stat = SAM_STAT_CHECK_CONDITION;
2505 break;
2506 }
2507
2508 if (!slot->port->port_attached) {
2509 dev_err(dev, "slot complete: port %d has removed\n",
2510 slot->port->sas_port.id);
2511 ts->stat = SAS_PHY_DOWN;
2512 }
2513
2514 out:
2515 spin_lock_irqsave(&task->task_state_lock, flags);
2516 task->task_state_flags |= SAS_TASK_STATE_DONE;
2517 spin_unlock_irqrestore(&task->task_state_lock, flags);
2518 spin_lock_irqsave(&hisi_hba->lock, flags);
2519 hisi_sas_slot_task_free(hisi_hba, task, slot);
2520 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2521 sts = ts->stat;
2522
2523 if (task->task_done)
2524 task->task_done(task);
2525
2526 return sts;
2527 }
2528
2529 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2530 struct hisi_sas_slot *slot)
2531 {
2532 struct sas_task *task = slot->task;
2533 struct domain_device *device = task->dev;
2534 struct domain_device *parent_dev = device->parent;
2535 struct hisi_sas_device *sas_dev = device->lldd_dev;
2536 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2537 struct asd_sas_port *sas_port = device->port;
2538 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2539 u8 *buf_cmd;
2540 int has_data = 0, rc = 0, hdr_tag = 0;
2541 u32 dw1 = 0, dw2 = 0;
2542
2543 /* create header */
2544 /* dw0 */
2545 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2546 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2547 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2548 else
2549 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2550
2551 /* dw1 */
2552 switch (task->data_dir) {
2553 case DMA_TO_DEVICE:
2554 has_data = 1;
2555 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2556 break;
2557 case DMA_FROM_DEVICE:
2558 has_data = 1;
2559 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2560 break;
2561 default:
2562 dw1 &= ~CMD_HDR_DIR_MSK;
2563 }
2564
2565 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2566 (task->ata_task.fis.control & ATA_SRST))
2567 dw1 |= 1 << CMD_HDR_RESET_OFF;
2568
2569 dw1 |= (hisi_sas_get_ata_protocol(
2570 task->ata_task.fis.command, task->data_dir))
2571 << CMD_HDR_FRAME_TYPE_OFF;
2572 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2573 hdr->dw1 = cpu_to_le32(dw1);
2574
2575 /* dw2 */
2576 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2577 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2578 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2579 }
2580
2581 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2582 2 << CMD_HDR_SG_MOD_OFF;
2583 hdr->dw2 = cpu_to_le32(dw2);
2584
2585 /* dw3 */
2586 hdr->transfer_tags = cpu_to_le32(slot->idx);
2587
2588 if (has_data) {
2589 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2590 slot->n_elem);
2591 if (rc)
2592 return rc;
2593 }
2594
2595 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2596 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2597 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2598
2599 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2600
2601 if (likely(!task->ata_task.device_control_reg_update))
2602 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2603 /* fill in command FIS */
2604 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2605
2606 return 0;
2607 }
2608
2609 static void hisi_sas_internal_abort_quirk_timeout(unsigned long data)
2610 {
2611 struct hisi_sas_slot *slot = (struct hisi_sas_slot *)data;
2612 struct hisi_sas_port *port = slot->port;
2613 struct asd_sas_port *asd_sas_port;
2614 struct asd_sas_phy *sas_phy;
2615
2616 if (!port)
2617 return;
2618
2619 asd_sas_port = &port->sas_port;
2620
2621 /* Kick the hardware - send break command */
2622 list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2623 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2624 struct hisi_hba *hisi_hba = phy->hisi_hba;
2625 int phy_no = sas_phy->id;
2626 u32 link_dfx2;
2627
2628 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2629 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2630 (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2631 u32 txid_auto;
2632
2633 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2634 TXID_AUTO);
2635 txid_auto |= TXID_AUTO_CTB_MSK;
2636 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2637 txid_auto);
2638 return;
2639 }
2640 }
2641 }
2642
2643 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2644 struct hisi_sas_slot *slot,
2645 int device_id, int abort_flag, int tag_to_abort)
2646 {
2647 struct sas_task *task = slot->task;
2648 struct domain_device *dev = task->dev;
2649 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2650 struct hisi_sas_port *port = slot->port;
2651 struct timer_list *timer = &slot->internal_abort_timer;
2652
2653 /* setup the quirk timer */
2654 setup_timer(timer, hisi_sas_internal_abort_quirk_timeout,
2655 (unsigned long)slot);
2656 /* Set the timeout to 10ms less than internal abort timeout */
2657 mod_timer(timer, jiffies + msecs_to_jiffies(100));
2658
2659 /* dw0 */
2660 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2661 (port->id << CMD_HDR_PORT_OFF) |
2662 ((dev_is_sata(dev) ? 1:0) <<
2663 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2664 (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2665
2666 /* dw1 */
2667 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2668
2669 /* dw7 */
2670 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2671 hdr->transfer_tags = cpu_to_le32(slot->idx);
2672
2673 return 0;
2674 }
2675
2676 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2677 {
2678 int i, res = IRQ_HANDLED;
2679 u32 port_id, link_rate, hard_phy_linkrate;
2680 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2681 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2682 struct device *dev = hisi_hba->dev;
2683 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2684 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2685
2686 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2687
2688 if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2689 goto end;
2690
2691 if (phy_no == 8) {
2692 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2693
2694 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2695 PORT_STATE_PHY8_PORT_NUM_OFF;
2696 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2697 PORT_STATE_PHY8_CONN_RATE_OFF;
2698 } else {
2699 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2700 port_id = (port_id >> (4 * phy_no)) & 0xf;
2701 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2702 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2703 }
2704
2705 if (port_id == 0xf) {
2706 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2707 res = IRQ_NONE;
2708 goto end;
2709 }
2710
2711 for (i = 0; i < 6; i++) {
2712 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2713 RX_IDAF_DWORD0 + (i * 4));
2714 frame_rcvd[i] = __swab32(idaf);
2715 }
2716
2717 sas_phy->linkrate = link_rate;
2718 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2719 HARD_PHY_LINKRATE);
2720 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2721 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2722
2723 sas_phy->oob_mode = SAS_OOB_MODE;
2724 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2725 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2726 phy->port_id = port_id;
2727 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2728 phy->phy_type |= PORT_TYPE_SAS;
2729 phy->phy_attached = 1;
2730 phy->identify.device_type = id->dev_type;
2731 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
2732 if (phy->identify.device_type == SAS_END_DEVICE)
2733 phy->identify.target_port_protocols =
2734 SAS_PROTOCOL_SSP;
2735 else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2736 phy->identify.target_port_protocols =
2737 SAS_PROTOCOL_SMP;
2738 if (!timer_pending(&hisi_hba->timer))
2739 set_link_timer_quirk(hisi_hba);
2740 }
2741 queue_work(hisi_hba->wq, &phy->phyup_ws);
2742
2743 end:
2744 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2745 CHL_INT0_SL_PHY_ENABLE_MSK);
2746 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2747
2748 return res;
2749 }
2750
2751 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2752 {
2753 u32 port_state;
2754
2755 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2756 if (port_state & 0x1ff)
2757 return true;
2758
2759 return false;
2760 }
2761
2762 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2763 {
2764 u32 phy_state, sl_ctrl, txid_auto;
2765 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2766 struct hisi_sas_port *port = phy->port;
2767
2768 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2769
2770 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2771 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2772
2773 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2774 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2775 sl_ctrl & ~SL_CONTROL_CTA_MSK);
2776 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2777 if (!check_any_wideports_v2_hw(hisi_hba) &&
2778 timer_pending(&hisi_hba->timer))
2779 del_timer(&hisi_hba->timer);
2780
2781 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2782 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2783 txid_auto | TXID_AUTO_CT3_MSK);
2784
2785 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2786 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2787
2788 return IRQ_HANDLED;
2789 }
2790
2791 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2792 {
2793 struct hisi_hba *hisi_hba = p;
2794 u32 irq_msk;
2795 int phy_no = 0;
2796 irqreturn_t res = IRQ_NONE;
2797
2798 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2799 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2800 while (irq_msk) {
2801 if (irq_msk & 1) {
2802 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2803 CHL_INT0);
2804
2805 switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2806 CHL_INT0_SL_PHY_ENABLE_MSK)) {
2807
2808 case CHL_INT0_SL_PHY_ENABLE_MSK:
2809 /* phy up */
2810 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2811 IRQ_HANDLED)
2812 res = IRQ_HANDLED;
2813 break;
2814
2815 case CHL_INT0_NOT_RDY_MSK:
2816 /* phy down */
2817 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2818 IRQ_HANDLED)
2819 res = IRQ_HANDLED;
2820 break;
2821
2822 case (CHL_INT0_NOT_RDY_MSK |
2823 CHL_INT0_SL_PHY_ENABLE_MSK):
2824 reg_value = hisi_sas_read32(hisi_hba,
2825 PHY_STATE);
2826 if (reg_value & BIT(phy_no)) {
2827 /* phy up */
2828 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2829 IRQ_HANDLED)
2830 res = IRQ_HANDLED;
2831 } else {
2832 /* phy down */
2833 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2834 IRQ_HANDLED)
2835 res = IRQ_HANDLED;
2836 }
2837 break;
2838
2839 default:
2840 break;
2841 }
2842
2843 }
2844 irq_msk >>= 1;
2845 phy_no++;
2846 }
2847
2848 return res;
2849 }
2850
2851 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2852 {
2853 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2854 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2855 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2856 u32 bcast_status;
2857
2858 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2859 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2860 if (bcast_status & RX_BCAST_CHG_MSK)
2861 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2862 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2863 CHL_INT0_SL_RX_BCST_ACK_MSK);
2864 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2865 }
2866
2867 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2868 {
2869 struct hisi_hba *hisi_hba = p;
2870 struct device *dev = hisi_hba->dev;
2871 u32 ent_msk, ent_tmp, irq_msk;
2872 int phy_no = 0;
2873
2874 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2875 ent_tmp = ent_msk;
2876 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2877 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2878
2879 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2880 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2881
2882 while (irq_msk) {
2883 if (irq_msk & (1 << phy_no)) {
2884 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2885 CHL_INT0);
2886 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2887 CHL_INT1);
2888 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2889 CHL_INT2);
2890
2891 if (irq_value1) {
2892 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
2893 CHL_INT1_DMAC_TX_ECC_ERR_MSK))
2894 panic("%s: DMAC RX/TX ecc bad error!\
2895 (0x%x)",
2896 dev_name(dev), irq_value1);
2897
2898 hisi_sas_phy_write32(hisi_hba, phy_no,
2899 CHL_INT1, irq_value1);
2900 }
2901
2902 if (irq_value2)
2903 hisi_sas_phy_write32(hisi_hba, phy_no,
2904 CHL_INT2, irq_value2);
2905
2906
2907 if (irq_value0) {
2908 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2909 phy_bcast_v2_hw(phy_no, hisi_hba);
2910
2911 hisi_sas_phy_write32(hisi_hba, phy_no,
2912 CHL_INT0, irq_value0
2913 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2914 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2915 & (~CHL_INT0_NOT_RDY_MSK));
2916 }
2917 }
2918 irq_msk &= ~(1 << phy_no);
2919 phy_no++;
2920 }
2921
2922 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2923
2924 return IRQ_HANDLED;
2925 }
2926
2927 static void
2928 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2929 {
2930 struct device *dev = hisi_hba->dev;
2931 const struct hisi_sas_hw_error *ecc_error;
2932 u32 val;
2933 int i;
2934
2935 for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2936 ecc_error = &one_bit_ecc_errors[i];
2937 if (irq_value & ecc_error->irq_msk) {
2938 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2939 val &= ecc_error->msk;
2940 val >>= ecc_error->shift;
2941 dev_warn(dev, ecc_error->msg, val);
2942 }
2943 }
2944 }
2945
2946 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2947 u32 irq_value)
2948 {
2949 struct device *dev = hisi_hba->dev;
2950 const struct hisi_sas_hw_error *ecc_error;
2951 u32 val;
2952 int i;
2953
2954 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2955 ecc_error = &multi_bit_ecc_errors[i];
2956 if (irq_value & ecc_error->irq_msk) {
2957 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2958 val &= ecc_error->msk;
2959 val >>= ecc_error->shift;
2960 dev_warn(dev, ecc_error->msg, irq_value, val);
2961 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2962 }
2963 }
2964
2965 return;
2966 }
2967
2968 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
2969 {
2970 struct hisi_hba *hisi_hba = p;
2971 u32 irq_value, irq_msk;
2972
2973 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2974 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
2975
2976 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2977 if (irq_value) {
2978 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2979 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2980 }
2981
2982 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2983 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2984
2985 return IRQ_HANDLED;
2986 }
2987
2988 #define AXI_ERR_NR 8
2989 static const char axi_err_info[AXI_ERR_NR][32] = {
2990 "IOST_AXI_W_ERR",
2991 "IOST_AXI_R_ERR",
2992 "ITCT_AXI_W_ERR",
2993 "ITCT_AXI_R_ERR",
2994 "SATA_AXI_W_ERR",
2995 "SATA_AXI_R_ERR",
2996 "DQE_AXI_R_ERR",
2997 "CQE_AXI_W_ERR"
2998 };
2999
3000 #define FIFO_ERR_NR 5
3001 static const char fifo_err_info[FIFO_ERR_NR][32] = {
3002 "CQE_WINFO_FIFO",
3003 "CQE_MSG_FIFIO",
3004 "GETDQE_FIFO",
3005 "CMDP_FIFO",
3006 "AWTCTRL_FIFO"
3007 };
3008
3009 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
3010 {
3011 struct hisi_hba *hisi_hba = p;
3012 u32 irq_value, irq_msk, err_value;
3013 struct device *dev = hisi_hba->dev;
3014
3015 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3016 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3017
3018 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3019 if (irq_value) {
3020 if (irq_value & BIT(ENT_INT_SRC3_WP_DEPTH_OFF)) {
3021 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3022 1 << ENT_INT_SRC3_WP_DEPTH_OFF);
3023 dev_warn(dev, "write pointer and depth error (0x%x) \
3024 found!\n",
3025 irq_value);
3026 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3027 }
3028
3029 if (irq_value & BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF)) {
3030 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3031 1 <<
3032 ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF);
3033 dev_warn(dev, "iptt no match slot error (0x%x) found!\n",
3034 irq_value);
3035 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3036 }
3037
3038 if (irq_value & BIT(ENT_INT_SRC3_RP_DEPTH_OFF)) {
3039 dev_warn(dev, "read pointer and depth error (0x%x) \
3040 found!\n",
3041 irq_value);
3042 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3043 }
3044
3045 if (irq_value & BIT(ENT_INT_SRC3_AXI_OFF)) {
3046 int i;
3047
3048 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3049 1 << ENT_INT_SRC3_AXI_OFF);
3050 err_value = hisi_sas_read32(hisi_hba,
3051 HGC_AXI_FIFO_ERR_INFO);
3052
3053 for (i = 0; i < AXI_ERR_NR; i++) {
3054 if (err_value & BIT(i)) {
3055 dev_warn(dev, "%s (0x%x) found!\n",
3056 axi_err_info[i], irq_value);
3057 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3058 }
3059 }
3060 }
3061
3062 if (irq_value & BIT(ENT_INT_SRC3_FIFO_OFF)) {
3063 int i;
3064
3065 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3066 1 << ENT_INT_SRC3_FIFO_OFF);
3067 err_value = hisi_sas_read32(hisi_hba,
3068 HGC_AXI_FIFO_ERR_INFO);
3069
3070 for (i = 0; i < FIFO_ERR_NR; i++) {
3071 if (err_value & BIT(AXI_ERR_NR + i)) {
3072 dev_warn(dev, "%s (0x%x) found!\n",
3073 fifo_err_info[i], irq_value);
3074 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3075 }
3076 }
3077
3078 }
3079
3080 if (irq_value & BIT(ENT_INT_SRC3_LM_OFF)) {
3081 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3082 1 << ENT_INT_SRC3_LM_OFF);
3083 dev_warn(dev, "LM add/fetch list error (0x%x) found!\n",
3084 irq_value);
3085 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3086 }
3087
3088 if (irq_value & BIT(ENT_INT_SRC3_ABT_OFF)) {
3089 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3090 1 << ENT_INT_SRC3_ABT_OFF);
3091 dev_warn(dev, "SAS_HGC_ABT fetch LM list error (0x%x) found!\n",
3092 irq_value);
3093 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3094 }
3095 }
3096
3097 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3098
3099 return IRQ_HANDLED;
3100 }
3101
3102 static void cq_tasklet_v2_hw(unsigned long val)
3103 {
3104 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3105 struct hisi_hba *hisi_hba = cq->hisi_hba;
3106 struct hisi_sas_slot *slot;
3107 struct hisi_sas_itct *itct;
3108 struct hisi_sas_complete_v2_hdr *complete_queue;
3109 u32 rd_point = cq->rd_point, wr_point, dev_id;
3110 int queue = cq->id;
3111 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
3112
3113 if (unlikely(hisi_hba->reject_stp_links_msk))
3114 phys_try_accept_stp_links_v2_hw(hisi_hba);
3115
3116 complete_queue = hisi_hba->complete_hdr[queue];
3117
3118 spin_lock(&dq->lock);
3119 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3120 (0x14 * queue));
3121
3122 while (rd_point != wr_point) {
3123 struct hisi_sas_complete_v2_hdr *complete_hdr;
3124 int iptt;
3125
3126 complete_hdr = &complete_queue[rd_point];
3127
3128 /* Check for NCQ completion */
3129 if (complete_hdr->act) {
3130 u32 act_tmp = complete_hdr->act;
3131 int ncq_tag_count = ffs(act_tmp);
3132
3133 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3134 CMPLT_HDR_DEV_ID_OFF;
3135 itct = &hisi_hba->itct[dev_id];
3136
3137 /* The NCQ tags are held in the itct header */
3138 while (ncq_tag_count) {
3139 __le64 *ncq_tag = &itct->qw4_15[0];
3140
3141 ncq_tag_count -= 1;
3142 iptt = (ncq_tag[ncq_tag_count / 5]
3143 >> (ncq_tag_count % 5) * 12) & 0xfff;
3144
3145 slot = &hisi_hba->slot_info[iptt];
3146 slot->cmplt_queue_slot = rd_point;
3147 slot->cmplt_queue = queue;
3148 slot_complete_v2_hw(hisi_hba, slot);
3149
3150 act_tmp &= ~(1 << ncq_tag_count);
3151 ncq_tag_count = ffs(act_tmp);
3152 }
3153 } else {
3154 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3155 slot = &hisi_hba->slot_info[iptt];
3156 slot->cmplt_queue_slot = rd_point;
3157 slot->cmplt_queue = queue;
3158 slot_complete_v2_hw(hisi_hba, slot);
3159 }
3160
3161 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3162 rd_point = 0;
3163 }
3164
3165 /* update rd_point */
3166 cq->rd_point = rd_point;
3167 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3168 spin_unlock(&dq->lock);
3169 }
3170
3171 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3172 {
3173 struct hisi_sas_cq *cq = p;
3174 struct hisi_hba *hisi_hba = cq->hisi_hba;
3175 int queue = cq->id;
3176
3177 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3178
3179 tasklet_schedule(&cq->tasklet);
3180
3181 return IRQ_HANDLED;
3182 }
3183
3184 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3185 {
3186 struct hisi_sas_phy *phy = p;
3187 struct hisi_hba *hisi_hba = phy->hisi_hba;
3188 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3189 struct device *dev = hisi_hba->dev;
3190 struct hisi_sas_initial_fis *initial_fis;
3191 struct dev_to_host_fis *fis;
3192 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3193 irqreturn_t res = IRQ_HANDLED;
3194 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3195 int phy_no, offset;
3196
3197 phy_no = sas_phy->id;
3198 initial_fis = &hisi_hba->initial_fis[phy_no];
3199 fis = &initial_fis->fis;
3200
3201 offset = 4 * (phy_no / 4);
3202 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3203 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3204 ent_msk | 1 << ((phy_no % 4) * 8));
3205
3206 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3207 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3208 (phy_no % 4)));
3209 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3210 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3211 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3212 res = IRQ_NONE;
3213 goto end;
3214 }
3215
3216 /* check ERR bit of Status Register */
3217 if (fis->status & ATA_ERR) {
3218 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3219 fis->status);
3220 disable_phy_v2_hw(hisi_hba, phy_no);
3221 enable_phy_v2_hw(hisi_hba, phy_no);
3222 res = IRQ_NONE;
3223 goto end;
3224 }
3225
3226 if (unlikely(phy_no == 8)) {
3227 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3228
3229 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3230 PORT_STATE_PHY8_PORT_NUM_OFF;
3231 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3232 PORT_STATE_PHY8_CONN_RATE_OFF;
3233 } else {
3234 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3235 port_id = (port_id >> (4 * phy_no)) & 0xf;
3236 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3237 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3238 }
3239
3240 if (port_id == 0xf) {
3241 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3242 res = IRQ_NONE;
3243 goto end;
3244 }
3245
3246 sas_phy->linkrate = link_rate;
3247 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3248 HARD_PHY_LINKRATE);
3249 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3250 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3251
3252 sas_phy->oob_mode = SATA_OOB_MODE;
3253 /* Make up some unique SAS address */
3254 attached_sas_addr[0] = 0x50;
3255 attached_sas_addr[7] = phy_no;
3256 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3257 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3258 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3259 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3260 phy->port_id = port_id;
3261 phy->phy_type |= PORT_TYPE_SATA;
3262 phy->phy_attached = 1;
3263 phy->identify.device_type = SAS_SATA_DEV;
3264 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3265 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3266 queue_work(hisi_hba->wq, &phy->phyup_ws);
3267
3268 end:
3269 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3270 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3271
3272 return res;
3273 }
3274
3275 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3276 int_phy_updown_v2_hw,
3277 int_chnl_int_v2_hw,
3278 };
3279
3280 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3281 fatal_ecc_int_v2_hw,
3282 fatal_axi_int_v2_hw
3283 };
3284
3285 /**
3286 * There is a limitation in the hip06 chipset that we need
3287 * to map in all mbigen interrupts, even if they are not used.
3288 */
3289 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3290 {
3291 struct platform_device *pdev = hisi_hba->platform_dev;
3292 struct device *dev = &pdev->dev;
3293 int irq, rc, irq_map[128];
3294 int i, phy_no, fatal_no, queue_no, k;
3295
3296 for (i = 0; i < 128; i++)
3297 irq_map[i] = platform_get_irq(pdev, i);
3298
3299 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3300 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3301 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3302 DRV_NAME " phy", hisi_hba);
3303 if (rc) {
3304 dev_err(dev, "irq init: could not request "
3305 "phy interrupt %d, rc=%d\n",
3306 irq, rc);
3307 rc = -ENOENT;
3308 goto free_phy_int_irqs;
3309 }
3310 }
3311
3312 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3313 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3314
3315 irq = irq_map[phy_no + 72];
3316 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3317 DRV_NAME " sata", phy);
3318 if (rc) {
3319 dev_err(dev, "irq init: could not request "
3320 "sata interrupt %d, rc=%d\n",
3321 irq, rc);
3322 rc = -ENOENT;
3323 goto free_sata_int_irqs;
3324 }
3325 }
3326
3327 for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3328 irq = irq_map[fatal_no + 81];
3329 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3330 DRV_NAME " fatal", hisi_hba);
3331 if (rc) {
3332 dev_err(dev,
3333 "irq init: could not request fatal interrupt %d, rc=%d\n",
3334 irq, rc);
3335 rc = -ENOENT;
3336 goto free_fatal_int_irqs;
3337 }
3338 }
3339
3340 for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3341 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3342 struct tasklet_struct *t = &cq->tasklet;
3343
3344 irq = irq_map[queue_no + 96];
3345 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3346 DRV_NAME " cq", cq);
3347 if (rc) {
3348 dev_err(dev,
3349 "irq init: could not request cq interrupt %d, rc=%d\n",
3350 irq, rc);
3351 rc = -ENOENT;
3352 goto free_cq_int_irqs;
3353 }
3354 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3355 }
3356
3357 return 0;
3358
3359 free_cq_int_irqs:
3360 for (k = 0; k < queue_no; k++) {
3361 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3362
3363 free_irq(irq_map[k + 96], cq);
3364 tasklet_kill(&cq->tasklet);
3365 }
3366 free_fatal_int_irqs:
3367 for (k = 0; k < fatal_no; k++)
3368 free_irq(irq_map[k + 81], hisi_hba);
3369 free_sata_int_irqs:
3370 for (k = 0; k < phy_no; k++) {
3371 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3372
3373 free_irq(irq_map[k + 72], phy);
3374 }
3375 free_phy_int_irqs:
3376 for (k = 0; k < i; k++)
3377 free_irq(irq_map[k + 1], hisi_hba);
3378 return rc;
3379 }
3380
3381 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3382 {
3383 int rc;
3384
3385 memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3386
3387 rc = hw_init_v2_hw(hisi_hba);
3388 if (rc)
3389 return rc;
3390
3391 rc = interrupt_init_v2_hw(hisi_hba);
3392 if (rc)
3393 return rc;
3394
3395 return 0;
3396 }
3397
3398 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3399 {
3400 struct platform_device *pdev = hisi_hba->platform_dev;
3401 int i;
3402
3403 for (i = 0; i < hisi_hba->queue_count; i++)
3404 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3405
3406 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3407 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3408 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3409 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3410
3411 for (i = 0; i < hisi_hba->n_phy; i++) {
3412 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3413 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3414 }
3415
3416 for (i = 0; i < 128; i++)
3417 synchronize_irq(platform_get_irq(pdev, i));
3418 }
3419
3420
3421 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3422 {
3423 return hisi_sas_read32(hisi_hba, PHY_STATE);
3424 }
3425
3426 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3427 {
3428 struct device *dev = hisi_hba->dev;
3429 int rc, cnt;
3430
3431 interrupt_disable_v2_hw(hisi_hba);
3432 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3433
3434 stop_phys_v2_hw(hisi_hba);
3435
3436 mdelay(10);
3437
3438 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3439
3440 /* wait until bus idle */
3441 cnt = 0;
3442 while (1) {
3443 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3444 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3445
3446 if (status == 0x3)
3447 break;
3448
3449 udelay(10);
3450 if (cnt++ > 10) {
3451 dev_info(dev, "wait axi bus state to idle timeout!\n");
3452 return -1;
3453 }
3454 }
3455
3456 hisi_sas_init_mem(hisi_hba);
3457
3458 rc = hw_init_v2_hw(hisi_hba);
3459 if (rc)
3460 return rc;
3461
3462 phys_reject_stp_links_v2_hw(hisi_hba);
3463
3464 return 0;
3465 }
3466
3467 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3468 .hw_init = hisi_sas_v2_init,
3469 .setup_itct = setup_itct_v2_hw,
3470 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3471 .alloc_dev = alloc_dev_quirk_v2_hw,
3472 .sl_notify = sl_notify_v2_hw,
3473 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3474 .free_device = free_device_v2_hw,
3475 .prep_smp = prep_smp_v2_hw,
3476 .prep_ssp = prep_ssp_v2_hw,
3477 .prep_stp = prep_ata_v2_hw,
3478 .prep_abort = prep_abort_v2_hw,
3479 .get_free_slot = get_free_slot_v2_hw,
3480 .start_delivery = start_delivery_v2_hw,
3481 .slot_complete = slot_complete_v2_hw,
3482 .phys_init = phys_init_v2_hw,
3483 .phy_enable = enable_phy_v2_hw,
3484 .phy_disable = disable_phy_v2_hw,
3485 .phy_hard_reset = phy_hard_reset_v2_hw,
3486 .get_events = phy_get_events_v2_hw,
3487 .phy_set_linkrate = phy_set_linkrate_v2_hw,
3488 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3489 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3490 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3491 .soft_reset = soft_reset_v2_hw,
3492 .get_phys_state = get_phys_state_v2_hw,
3493 };
3494
3495 static int hisi_sas_v2_probe(struct platform_device *pdev)
3496 {
3497 /*
3498 * Check if we should defer the probe before we probe the
3499 * upper layer, as it's hard to defer later on.
3500 */
3501 int ret = platform_get_irq(pdev, 0);
3502
3503 if (ret < 0) {
3504 if (ret != -EPROBE_DEFER)
3505 dev_err(&pdev->dev, "cannot obtain irq\n");
3506 return ret;
3507 }
3508
3509 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3510 }
3511
3512 static int hisi_sas_v2_remove(struct platform_device *pdev)
3513 {
3514 struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3515 struct hisi_hba *hisi_hba = sha->lldd_ha;
3516 int i;
3517
3518 if (timer_pending(&hisi_hba->timer))
3519 del_timer(&hisi_hba->timer);
3520
3521 for (i = 0; i < hisi_hba->queue_count; i++) {
3522 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
3523
3524 tasklet_kill(&cq->tasklet);
3525 }
3526
3527 return hisi_sas_remove(pdev);
3528 }
3529
3530 static const struct of_device_id sas_v2_of_match[] = {
3531 { .compatible = "hisilicon,hip06-sas-v2",},
3532 { .compatible = "hisilicon,hip07-sas-v2",},
3533 {},
3534 };
3535 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3536
3537 static const struct acpi_device_id sas_v2_acpi_match[] = {
3538 { "HISI0162", 0 },
3539 { }
3540 };
3541
3542 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3543
3544 static struct platform_driver hisi_sas_v2_driver = {
3545 .probe = hisi_sas_v2_probe,
3546 .remove = hisi_sas_v2_remove,
3547 .driver = {
3548 .name = DRV_NAME,
3549 .of_match_table = sas_v2_of_match,
3550 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3551 },
3552 };
3553
3554 module_platform_driver(hisi_sas_v2_driver);
3555
3556 MODULE_LICENSE("GPL");
3557 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3558 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3559 MODULE_ALIAS("platform:" DRV_NAME);
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