]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
scsi: hisi_sas: add v2 hw port AXI error handling support
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
1 /*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12 #include "hisi_sas.h"
13 #define DRV_NAME "hisi_sas_v2_hw"
14
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
34 #define ITCT_CLR 0x44
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
148 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
149 #define DLVRY_Q_0_DEPTH 0x268
150 #define DLVRY_Q_0_WR_PTR 0x26c
151 #define DLVRY_Q_0_RD_PTR 0x270
152 #define HYPER_STREAM_ID_EN_CFG 0xc80
153 #define OQ0_INT_SRC_MSK 0xc90
154 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
155 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
156 #define COMPL_Q_0_DEPTH 0x4e8
157 #define COMPL_Q_0_WR_PTR 0x4ec
158 #define COMPL_Q_0_RD_PTR 0x4f0
159 #define HGC_RXM_DFX_STATUS14 0xae8
160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
162 HGC_RXM_DFX_STATUS14_MEM0_OFF)
163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM1_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM2_OFF)
169 #define HGC_RXM_DFX_STATUS15 0xaec
170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
172 HGC_RXM_DFX_STATUS15_MEM3_OFF)
173 /* phy registers need init */
174 #define PORT_BASE (0x2000)
175
176 #define PHY_CFG (PORT_BASE + 0x0)
177 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PHY_CFG_ENA_OFF 0
179 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
180 #define PHY_CFG_DC_OPT_OFF 2
181 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
182 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
183 #define PROG_PHY_LINK_RATE_MAX_OFF 0
184 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
185 #define PHY_CTRL (PORT_BASE + 0x14)
186 #define PHY_CTRL_RESET_OFF 0
187 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
188 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
189 #define SL_CFG (PORT_BASE + 0x84)
190 #define PHY_PCN (PORT_BASE + 0x44)
191 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
192 #define SL_CONTROL (PORT_BASE + 0x94)
193 #define SL_CONTROL_NOTIFY_EN_OFF 0
194 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
195 #define SL_CONTROL_CTA_OFF 17
196 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
197 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
198 #define RX_BCAST_CHG_OFF 1
199 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
200 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
201 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
202 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
203 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
204 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
205 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
206 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
207 #define TXID_AUTO (PORT_BASE + 0xb8)
208 #define TXID_AUTO_CT3_OFF 1
209 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
210 #define TXID_AUTO_CTB_OFF 11
211 #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
212 #define TX_HARDRST_OFF 2
213 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
214 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
215 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
216 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
217 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
218 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
219 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
220 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
221 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
222 #define CON_CONTROL (PORT_BASE + 0x118)
223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
225 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
226 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
227 #define CHL_INT0 (PORT_BASE + 0x1b4)
228 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
229 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
230 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
231 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
232 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
233 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
234 #define CHL_INT0_NOT_RDY_OFF 4
235 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
236 #define CHL_INT0_PHY_RDY_OFF 5
237 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
238 #define CHL_INT1 (PORT_BASE + 0x1b8)
239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
243 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
244 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
245 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
246 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
247 #define CHL_INT2 (PORT_BASE + 0x1bc)
248 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
249 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
250 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
251 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
252 #define DMA_TX_DFX0 (PORT_BASE + 0x200)
253 #define DMA_TX_DFX1 (PORT_BASE + 0x204)
254 #define DMA_TX_DFX1_IPTT_OFF 0
255 #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
256 #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
257 #define PORT_DFX0 (PORT_BASE + 0x258)
258 #define LINK_DFX2 (PORT_BASE + 0X264)
259 #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
260 #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
261 #define LINK_DFX2_SEND_HOLD_STS_OFF 10
262 #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
263 #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
264 #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
265 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
266 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
267 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
268 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
269 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
270 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
271 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
272 #define DMA_TX_STATUS_BUSY_OFF 0
273 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
274 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
275 #define DMA_RX_STATUS_BUSY_OFF 0
276 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
277
278 #define AXI_CFG (0x5100)
279 #define AM_CFG_MAX_TRANS (0x5010)
280 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
281
282 #define AXI_MASTER_CFG_BASE (0x5000)
283 #define AM_CTRL_GLOBAL (0x0)
284 #define AM_CURR_TRANS_RETURN (0x150)
285
286 /* HW dma structures */
287 /* Delivery queue header */
288 /* dw0 */
289 #define CMD_HDR_ABORT_FLAG_OFF 0
290 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
291 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
292 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
293 #define CMD_HDR_RESP_REPORT_OFF 5
294 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
295 #define CMD_HDR_TLR_CTRL_OFF 6
296 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
297 #define CMD_HDR_PORT_OFF 18
298 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
299 #define CMD_HDR_PRIORITY_OFF 27
300 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
301 #define CMD_HDR_CMD_OFF 29
302 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
303 /* dw1 */
304 #define CMD_HDR_DIR_OFF 5
305 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
306 #define CMD_HDR_RESET_OFF 7
307 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
308 #define CMD_HDR_VDTL_OFF 10
309 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
310 #define CMD_HDR_FRAME_TYPE_OFF 11
311 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
312 #define CMD_HDR_DEV_ID_OFF 16
313 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
314 /* dw2 */
315 #define CMD_HDR_CFL_OFF 0
316 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
317 #define CMD_HDR_NCQ_TAG_OFF 10
318 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
319 #define CMD_HDR_MRFL_OFF 15
320 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
321 #define CMD_HDR_SG_MOD_OFF 24
322 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
323 #define CMD_HDR_FIRST_BURST_OFF 26
324 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
325 /* dw3 */
326 #define CMD_HDR_IPTT_OFF 0
327 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
328 /* dw6 */
329 #define CMD_HDR_DIF_SGL_LEN_OFF 0
330 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
331 #define CMD_HDR_DATA_SGL_LEN_OFF 16
332 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
333 #define CMD_HDR_ABORT_IPTT_OFF 16
334 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
335
336 /* Completion header */
337 /* dw0 */
338 #define CMPLT_HDR_ERR_PHASE_OFF 2
339 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
340 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
341 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
342 #define CMPLT_HDR_ERX_OFF 12
343 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
344 #define CMPLT_HDR_ABORT_STAT_OFF 13
345 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
346 /* abort_stat */
347 #define STAT_IO_NOT_VALID 0x1
348 #define STAT_IO_NO_DEVICE 0x2
349 #define STAT_IO_COMPLETE 0x3
350 #define STAT_IO_ABORTED 0x4
351 /* dw1 */
352 #define CMPLT_HDR_IPTT_OFF 0
353 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
354 #define CMPLT_HDR_DEV_ID_OFF 16
355 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
356
357 /* ITCT header */
358 /* qw0 */
359 #define ITCT_HDR_DEV_TYPE_OFF 0
360 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
361 #define ITCT_HDR_VALID_OFF 2
362 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
363 #define ITCT_HDR_MCR_OFF 5
364 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
365 #define ITCT_HDR_VLN_OFF 9
366 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
367 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
368 #define ITCT_HDR_SMP_TIMEOUT_8US 1
369 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
370 250) /* 2ms */
371 #define ITCT_HDR_AWT_CONTINUE_OFF 25
372 #define ITCT_HDR_PORT_ID_OFF 28
373 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
374 /* qw2 */
375 #define ITCT_HDR_INLT_OFF 0
376 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
377 #define ITCT_HDR_BITLT_OFF 16
378 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
379 #define ITCT_HDR_MCTLT_OFF 32
380 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
381 #define ITCT_HDR_RTOLT_OFF 48
382 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
383
384 #define HISI_SAS_FATAL_INT_NR 2
385
386 struct hisi_sas_complete_v2_hdr {
387 __le32 dw0;
388 __le32 dw1;
389 __le32 act;
390 __le32 dw3;
391 };
392
393 struct hisi_sas_err_record_v2 {
394 /* dw0 */
395 __le32 trans_tx_fail_type;
396
397 /* dw1 */
398 __le32 trans_rx_fail_type;
399
400 /* dw2 */
401 __le16 dma_tx_err_type;
402 __le16 sipc_rx_err_type;
403
404 /* dw3 */
405 __le32 dma_rx_err_type;
406 };
407
408 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
409 {
410 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
411 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
412 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
413 .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
414 .reg = HGC_DQE_ECC_ADDR,
415 },
416 {
417 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
418 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
419 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
420 .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
421 .reg = HGC_IOST_ECC_ADDR,
422 },
423 {
424 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
425 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
426 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
427 .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
428 .reg = HGC_ITCT_ECC_ADDR,
429 },
430 {
431 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
432 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
433 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
434 .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
435 .reg = HGC_LM_DFX_STATUS2,
436 },
437 {
438 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
439 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
440 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
441 .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
442 .reg = HGC_LM_DFX_STATUS2,
443 },
444 {
445 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
446 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
447 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
448 .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
449 .reg = HGC_CQE_ECC_ADDR,
450 },
451 {
452 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
453 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
454 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
455 .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
456 .reg = HGC_RXM_DFX_STATUS14,
457 },
458 {
459 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
460 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
461 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
462 .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
463 .reg = HGC_RXM_DFX_STATUS14,
464 },
465 {
466 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
467 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
468 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
469 .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
470 .reg = HGC_RXM_DFX_STATUS14,
471 },
472 {
473 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
474 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
475 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
476 .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
477 .reg = HGC_RXM_DFX_STATUS15,
478 },
479 };
480
481 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
482 {
483 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
484 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
485 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
486 .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
487 .reg = HGC_DQE_ECC_ADDR,
488 },
489 {
490 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
491 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
492 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
493 .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
494 .reg = HGC_IOST_ECC_ADDR,
495 },
496 {
497 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
498 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
499 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
500 .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
501 .reg = HGC_ITCT_ECC_ADDR,
502 },
503 {
504 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
505 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
506 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
507 .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
508 .reg = HGC_LM_DFX_STATUS2,
509 },
510 {
511 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
512 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
513 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
514 .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
515 .reg = HGC_LM_DFX_STATUS2,
516 },
517 {
518 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
519 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
520 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
521 .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
522 .reg = HGC_CQE_ECC_ADDR,
523 },
524 {
525 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
526 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
527 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
528 .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
529 .reg = HGC_RXM_DFX_STATUS14,
530 },
531 {
532 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
533 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
534 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
535 .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
536 .reg = HGC_RXM_DFX_STATUS14,
537 },
538 {
539 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
540 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
541 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
542 .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
543 .reg = HGC_RXM_DFX_STATUS14,
544 },
545 {
546 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
547 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
548 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
549 .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
550 .reg = HGC_RXM_DFX_STATUS15,
551 },
552 };
553
554 enum {
555 HISI_SAS_PHY_PHY_UPDOWN,
556 HISI_SAS_PHY_CHNL_INT,
557 HISI_SAS_PHY_INT_NR
558 };
559
560 enum {
561 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
562 TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
563 DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
564 SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
565 DMA_RX_ERR_BASE = 0x60, /* dw3 */
566
567 /* trans tx*/
568 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
569 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
570 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
571 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
572 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
573 RESERVED0, /* 0x5 */
574 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
575 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
576 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
577 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
578 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
579 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
580 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
581 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
582 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
583 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
584 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
585 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
586 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
587 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
588 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
589 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
590 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
591 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
592 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
593 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
594 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
595 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
596 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
597 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
598 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
599 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
600 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
601 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
602 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
603
604 /* trans rx */
605 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
606 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
607 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
608 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
609 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
610 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
611 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
612 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
613 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
614 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
615 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
616 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
617 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
618 RESERVED1, /* 0x2b */
619 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
620 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
621 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
622 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
623 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
624 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
625 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
626 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
627 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
628 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
629 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
630 RESERVED2, /* 0x34 */
631 RESERVED3, /* 0x35 */
632 RESERVED4, /* 0x36 */
633 RESERVED5, /* 0x37 */
634 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
635 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
636 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
637 RESERVED6, /* 0x3b */
638 RESERVED7, /* 0x3c */
639 RESERVED8, /* 0x3d */
640 RESERVED9, /* 0x3e */
641 TRANS_RX_R_ERR, /* 0x3f */
642
643 /* dma tx */
644 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
645 DMA_TX_DIF_APP_ERR, /* 0x41 */
646 DMA_TX_DIF_RPP_ERR, /* 0x42 */
647 DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
648 DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
649 DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
650 DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
651 DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
652 DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
653 DMA_TX_RAM_ECC_ERR, /* 0x49 */
654 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
655 DMA_TX_MAX_ERR_CODE,
656
657 /* sipc rx */
658 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
659 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
660 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
661 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
662 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
663 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
664 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
665 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
666 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
667 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
668 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
669 SIPC_RX_MAX_ERR_CODE,
670
671 /* dma rx */
672 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
673 DMA_RX_DIF_APP_ERR, /* 0x61 */
674 DMA_RX_DIF_RPP_ERR, /* 0x62 */
675 DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
676 DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
677 DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
678 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
679 DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
680 RESERVED10, /* 0x68 */
681 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
682 DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
683 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
684 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
685 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
686 DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
687 DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
688 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
689 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
690 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
691 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
692 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
693 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
694 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
695 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
696 DMA_RX_RAM_ECC_ERR, /* 0x78 */
697 DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
698 DMA_RX_MAX_ERR_CODE,
699 };
700
701 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
702 #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
703
704 #define DIR_NO_DATA 0
705 #define DIR_TO_INI 1
706 #define DIR_TO_DEVICE 2
707 #define DIR_RESERVED 3
708
709 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
710 err_phase == 0x4 || err_phase == 0x8 ||\
711 err_phase == 0x6 || err_phase == 0xa)
712 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
713 err_phase == 0x20 || err_phase == 0x40)
714
715 static void link_timeout_disable_link(struct timer_list *t);
716
717 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
718 {
719 void __iomem *regs = hisi_hba->regs + off;
720
721 return readl(regs);
722 }
723
724 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
725 {
726 void __iomem *regs = hisi_hba->regs + off;
727
728 return readl_relaxed(regs);
729 }
730
731 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
732 {
733 void __iomem *regs = hisi_hba->regs + off;
734
735 writel(val, regs);
736 }
737
738 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
739 u32 off, u32 val)
740 {
741 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
742
743 writel(val, regs);
744 }
745
746 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
747 int phy_no, u32 off)
748 {
749 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
750
751 return readl(regs);
752 }
753
754 /* This function needs to be protected from pre-emption. */
755 static int
756 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
757 struct domain_device *device)
758 {
759 int sata_dev = dev_is_sata(device);
760 void *bitmap = hisi_hba->slot_index_tags;
761 struct hisi_sas_device *sas_dev = device->lldd_dev;
762 int sata_idx = sas_dev->sata_idx;
763 int start, end;
764
765 if (!sata_dev) {
766 /*
767 * STP link SoC bug workaround: index starts from 1.
768 * additionally, we can only allocate odd IPTT(1~4095)
769 * for SAS/SMP device.
770 */
771 start = 1;
772 end = hisi_hba->slot_index_count;
773 } else {
774 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
775 return -EINVAL;
776
777 /*
778 * For SATA device: allocate even IPTT in this interval
779 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
780 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
781 * SoC bug workaround. So we ignore the first 32 even IPTTs.
782 */
783 start = 64 * (sata_idx + 1);
784 end = 64 * (sata_idx + 2);
785 }
786
787 while (1) {
788 start = find_next_zero_bit(bitmap,
789 hisi_hba->slot_index_count, start);
790 if (start >= end)
791 return -SAS_QUEUE_FULL;
792 /*
793 * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
794 */
795 if (sata_dev ^ (start & 1))
796 break;
797 start++;
798 }
799
800 set_bit(start, bitmap);
801 *slot_idx = start;
802 return 0;
803 }
804
805 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
806 {
807 unsigned int index;
808 struct device *dev = hisi_hba->dev;
809 void *bitmap = hisi_hba->sata_dev_bitmap;
810
811 index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
812 if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
813 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
814 return false;
815 }
816
817 set_bit(index, bitmap);
818 *idx = index;
819 return true;
820 }
821
822
823 static struct
824 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
825 {
826 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
827 struct hisi_sas_device *sas_dev = NULL;
828 int i, sata_dev = dev_is_sata(device);
829 int sata_idx = -1;
830 unsigned long flags;
831
832 spin_lock_irqsave(&hisi_hba->lock, flags);
833
834 if (sata_dev)
835 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
836 goto out;
837
838 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
839 /*
840 * SATA device id bit0 should be 0
841 */
842 if (sata_dev && (i & 1))
843 continue;
844 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
845 int queue = i % hisi_hba->queue_count;
846 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
847
848 hisi_hba->devices[i].device_id = i;
849 sas_dev = &hisi_hba->devices[i];
850 sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
851 sas_dev->dev_type = device->dev_type;
852 sas_dev->hisi_hba = hisi_hba;
853 sas_dev->sas_device = device;
854 sas_dev->sata_idx = sata_idx;
855 sas_dev->dq = dq;
856 INIT_LIST_HEAD(&hisi_hba->devices[i].list);
857 break;
858 }
859 }
860
861 out:
862 spin_unlock_irqrestore(&hisi_hba->lock, flags);
863
864 return sas_dev;
865 }
866
867 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
868 {
869 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
870
871 cfg &= ~PHY_CFG_DC_OPT_MSK;
872 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
873 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
874 }
875
876 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
877 {
878 struct sas_identify_frame identify_frame;
879 u32 *identify_buffer;
880
881 memset(&identify_frame, 0, sizeof(identify_frame));
882 identify_frame.dev_type = SAS_END_DEVICE;
883 identify_frame.frame_type = 0;
884 identify_frame._un1 = 1;
885 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
886 identify_frame.target_bits = SAS_PROTOCOL_NONE;
887 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
888 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
889 identify_frame.phy_id = phy_no;
890 identify_buffer = (u32 *)(&identify_frame);
891
892 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
893 __swab32(identify_buffer[0]));
894 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
895 __swab32(identify_buffer[1]));
896 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
897 __swab32(identify_buffer[2]));
898 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
899 __swab32(identify_buffer[3]));
900 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
901 __swab32(identify_buffer[4]));
902 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
903 __swab32(identify_buffer[5]));
904 }
905
906 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
907 struct hisi_sas_device *sas_dev)
908 {
909 struct domain_device *device = sas_dev->sas_device;
910 struct device *dev = hisi_hba->dev;
911 u64 qw0, device_id = sas_dev->device_id;
912 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
913 struct domain_device *parent_dev = device->parent;
914 struct asd_sas_port *sas_port = device->port;
915 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
916
917 memset(itct, 0, sizeof(*itct));
918
919 /* qw0 */
920 qw0 = 0;
921 switch (sas_dev->dev_type) {
922 case SAS_END_DEVICE:
923 case SAS_EDGE_EXPANDER_DEVICE:
924 case SAS_FANOUT_EXPANDER_DEVICE:
925 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
926 break;
927 case SAS_SATA_DEV:
928 case SAS_SATA_PENDING:
929 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
930 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
931 else
932 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
933 break;
934 default:
935 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
936 sas_dev->dev_type);
937 }
938
939 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
940 (device->linkrate << ITCT_HDR_MCR_OFF) |
941 (1 << ITCT_HDR_VLN_OFF) |
942 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
943 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
944 (port->id << ITCT_HDR_PORT_ID_OFF));
945 itct->qw0 = cpu_to_le64(qw0);
946
947 /* qw1 */
948 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
949 itct->sas_addr = __swab64(itct->sas_addr);
950
951 /* qw2 */
952 if (!dev_is_sata(device))
953 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
954 (0x1ULL << ITCT_HDR_BITLT_OFF) |
955 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
956 (0x1ULL << ITCT_HDR_RTOLT_OFF));
957 }
958
959 static void clear_itct_v2_hw(struct hisi_hba *hisi_hba,
960 struct hisi_sas_device *sas_dev)
961 {
962 DECLARE_COMPLETION_ONSTACK(completion);
963 u64 dev_id = sas_dev->device_id;
964 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
965 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
966 int i;
967
968 sas_dev->completion = &completion;
969
970 /* clear the itct interrupt state */
971 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
972 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
973 ENT_INT_SRC3_ITC_INT_MSK);
974
975 for (i = 0; i < 2; i++) {
976 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
977 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
978 wait_for_completion(sas_dev->completion);
979
980 memset(itct, 0, sizeof(struct hisi_sas_itct));
981 }
982 }
983
984 static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
985 {
986 struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
987
988 /* SoC bug workaround */
989 if (dev_is_sata(sas_dev->sas_device))
990 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
991 }
992
993 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
994 {
995 int i, reset_val;
996 u32 val;
997 unsigned long end_time;
998 struct device *dev = hisi_hba->dev;
999
1000 /* The mask needs to be set depending on the number of phys */
1001 if (hisi_hba->n_phy == 9)
1002 reset_val = 0x1fffff;
1003 else
1004 reset_val = 0x7ffff;
1005
1006 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1007
1008 /* Disable all of the PHYs */
1009 for (i = 0; i < hisi_hba->n_phy; i++) {
1010 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1011
1012 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1013 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1014 }
1015 udelay(50);
1016
1017 /* Ensure DMA tx & rx idle */
1018 for (i = 0; i < hisi_hba->n_phy; i++) {
1019 u32 dma_tx_status, dma_rx_status;
1020
1021 end_time = jiffies + msecs_to_jiffies(1000);
1022
1023 while (1) {
1024 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1025 DMA_TX_STATUS);
1026 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1027 DMA_RX_STATUS);
1028
1029 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1030 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1031 break;
1032
1033 msleep(20);
1034 if (time_after(jiffies, end_time))
1035 return -EIO;
1036 }
1037 }
1038
1039 /* Ensure axi bus idle */
1040 end_time = jiffies + msecs_to_jiffies(1000);
1041 while (1) {
1042 u32 axi_status =
1043 hisi_sas_read32(hisi_hba, AXI_CFG);
1044
1045 if (axi_status == 0)
1046 break;
1047
1048 msleep(20);
1049 if (time_after(jiffies, end_time))
1050 return -EIO;
1051 }
1052
1053 if (ACPI_HANDLE(dev)) {
1054 acpi_status s;
1055
1056 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1057 if (ACPI_FAILURE(s)) {
1058 dev_err(dev, "Reset failed\n");
1059 return -EIO;
1060 }
1061 } else if (hisi_hba->ctrl) {
1062 /* reset and disable clock*/
1063 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1064 reset_val);
1065 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1066 reset_val);
1067 msleep(1);
1068 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1069 if (reset_val != (val & reset_val)) {
1070 dev_err(dev, "SAS reset fail.\n");
1071 return -EIO;
1072 }
1073
1074 /* De-reset and enable clock*/
1075 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1076 reset_val);
1077 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1078 reset_val);
1079 msleep(1);
1080 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1081 &val);
1082 if (val & reset_val) {
1083 dev_err(dev, "SAS de-reset fail.\n");
1084 return -EIO;
1085 }
1086 } else
1087 dev_warn(dev, "no reset method\n");
1088
1089 return 0;
1090 }
1091
1092 /* This function needs to be called after resetting SAS controller. */
1093 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1094 {
1095 u32 cfg;
1096 int phy_no;
1097
1098 hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1099 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1100 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1101 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1102 continue;
1103
1104 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1105 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1106 }
1107 }
1108
1109 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1110 {
1111 int phy_no;
1112 u32 dma_tx_dfx1;
1113
1114 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1115 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1116 continue;
1117
1118 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1119 DMA_TX_DFX1);
1120 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1121 u32 cfg = hisi_sas_phy_read32(hisi_hba,
1122 phy_no, CON_CONTROL);
1123
1124 cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1125 hisi_sas_phy_write32(hisi_hba, phy_no,
1126 CON_CONTROL, cfg);
1127 clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1128 }
1129 }
1130 }
1131
1132 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1133 {
1134 struct device *dev = hisi_hba->dev;
1135 int i;
1136
1137 /* Global registers init */
1138
1139 /* Deal with am-max-transmissions quirk */
1140 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1141 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1142 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1143 0x2020);
1144 } /* Else, use defaults -> do nothing */
1145
1146 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1147 (u32)((1ULL << hisi_hba->queue_count) - 1));
1148 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1149 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1150 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1151 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1152 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1153 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1154 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1155 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1156 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1157 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1158 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1159 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1160 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1161 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1162 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1163 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1164 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1165 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1166 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1167 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1168 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1169 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1170 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1171 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1172 for (i = 0; i < hisi_hba->queue_count; i++)
1173 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1174
1175 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1176 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1177
1178 for (i = 0; i < hisi_hba->n_phy; i++) {
1179 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
1180 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
1181 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1182 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1183 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1184 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1185 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1186 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1187 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1188 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1189 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff);
1190 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
1191 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1192 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1193 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1194 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1195 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1196 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1197 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1198 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1199 if (hisi_hba->refclk_frequency_mhz == 66)
1200 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1201 /* else, do nothing -> leave it how you found it */
1202 }
1203
1204 for (i = 0; i < hisi_hba->queue_count; i++) {
1205 /* Delivery queue */
1206 hisi_sas_write32(hisi_hba,
1207 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1208 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1209
1210 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1211 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1212
1213 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1214 HISI_SAS_QUEUE_SLOTS);
1215
1216 /* Completion queue */
1217 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1218 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1219
1220 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1221 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1222
1223 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1224 HISI_SAS_QUEUE_SLOTS);
1225 }
1226
1227 /* itct */
1228 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1229 lower_32_bits(hisi_hba->itct_dma));
1230
1231 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1232 upper_32_bits(hisi_hba->itct_dma));
1233
1234 /* iost */
1235 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1236 lower_32_bits(hisi_hba->iost_dma));
1237
1238 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1239 upper_32_bits(hisi_hba->iost_dma));
1240
1241 /* breakpoint */
1242 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1243 lower_32_bits(hisi_hba->breakpoint_dma));
1244
1245 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1246 upper_32_bits(hisi_hba->breakpoint_dma));
1247
1248 /* SATA broken msg */
1249 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1250 lower_32_bits(hisi_hba->sata_breakpoint_dma));
1251
1252 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1253 upper_32_bits(hisi_hba->sata_breakpoint_dma));
1254
1255 /* SATA initial fis */
1256 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1257 lower_32_bits(hisi_hba->initial_fis_dma));
1258
1259 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1260 upper_32_bits(hisi_hba->initial_fis_dma));
1261 }
1262
1263 static void link_timeout_enable_link(struct timer_list *t)
1264 {
1265 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1266 int i, reg_val;
1267
1268 for (i = 0; i < hisi_hba->n_phy; i++) {
1269 if (hisi_hba->reject_stp_links_msk & BIT(i))
1270 continue;
1271
1272 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1273 if (!(reg_val & BIT(0))) {
1274 hisi_sas_phy_write32(hisi_hba, i,
1275 CON_CONTROL, 0x7);
1276 break;
1277 }
1278 }
1279
1280 hisi_hba->timer.function = link_timeout_disable_link;
1281 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1282 }
1283
1284 static void link_timeout_disable_link(struct timer_list *t)
1285 {
1286 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1287 int i, reg_val;
1288
1289 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1290 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1291 if (hisi_hba->reject_stp_links_msk & BIT(i))
1292 continue;
1293
1294 if (reg_val & BIT(i)) {
1295 hisi_sas_phy_write32(hisi_hba, i,
1296 CON_CONTROL, 0x6);
1297 break;
1298 }
1299 }
1300
1301 hisi_hba->timer.function = link_timeout_enable_link;
1302 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1303 }
1304
1305 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1306 {
1307 hisi_hba->timer.function = link_timeout_disable_link;
1308 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1309 add_timer(&hisi_hba->timer);
1310 }
1311
1312 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1313 {
1314 struct device *dev = hisi_hba->dev;
1315 int rc;
1316
1317 rc = reset_hw_v2_hw(hisi_hba);
1318 if (rc) {
1319 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1320 return rc;
1321 }
1322
1323 msleep(100);
1324 init_reg_v2_hw(hisi_hba);
1325
1326 return 0;
1327 }
1328
1329 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1330 {
1331 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1332
1333 cfg |= PHY_CFG_ENA_MSK;
1334 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1335 }
1336
1337 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1338 {
1339 u32 context;
1340
1341 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1342 if (context & (1 << phy_no))
1343 return true;
1344
1345 return false;
1346 }
1347
1348 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1349 {
1350 u32 dfx_val;
1351
1352 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1353
1354 if (dfx_val & BIT(16))
1355 return false;
1356
1357 return true;
1358 }
1359
1360 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1361 {
1362 int i, max_loop = 1000;
1363 struct device *dev = hisi_hba->dev;
1364 u32 status, axi_status, dfx_val, dfx_tx_val;
1365
1366 for (i = 0; i < max_loop; i++) {
1367 status = hisi_sas_read32_relaxed(hisi_hba,
1368 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1369
1370 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1371 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1372 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1373 phy_no, DMA_TX_FIFO_DFX0);
1374
1375 if ((status == 0x3) && (axi_status == 0x0) &&
1376 (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1377 return true;
1378 udelay(10);
1379 }
1380 dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1381 phy_no, status, axi_status,
1382 dfx_val, dfx_tx_val);
1383 return false;
1384 }
1385
1386 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1387 {
1388 int i, max_loop = 1000;
1389 struct device *dev = hisi_hba->dev;
1390 u32 status, tx_dfx0;
1391
1392 for (i = 0; i < max_loop; i++) {
1393 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1394 status = (status & 0x3fc0) >> 6;
1395
1396 if (status != 0x1)
1397 return true;
1398
1399 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1400 if ((tx_dfx0 & 0x1ff) == 0x2)
1401 return true;
1402 udelay(10);
1403 }
1404 dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1405 phy_no, status, tx_dfx0);
1406 return false;
1407 }
1408
1409 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1410 {
1411 if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1412 return true;
1413
1414 if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1415 return false;
1416
1417 if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1418 return false;
1419
1420 return true;
1421 }
1422
1423
1424 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1425 {
1426 u32 cfg, axi_val, dfx0_val, txid_auto;
1427 struct device *dev = hisi_hba->dev;
1428
1429 /* Close axi bus. */
1430 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1431 AM_CTRL_GLOBAL);
1432 axi_val |= 0x1;
1433 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1434 AM_CTRL_GLOBAL, axi_val);
1435
1436 if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1437 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1438 goto do_disable;
1439
1440 /* Reset host controller. */
1441 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1442 return;
1443 }
1444
1445 dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1446 dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1447 if (dfx0_val != 0x4)
1448 goto do_disable;
1449
1450 if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1451 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1452 phy_no);
1453 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1454 TXID_AUTO);
1455 txid_auto |= TXID_AUTO_CTB_MSK;
1456 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1457 txid_auto);
1458 }
1459
1460 do_disable:
1461 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1462 cfg &= ~PHY_CFG_ENA_MSK;
1463 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1464
1465 /* Open axi bus. */
1466 axi_val &= ~0x1;
1467 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1468 AM_CTRL_GLOBAL, axi_val);
1469 }
1470
1471 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1472 {
1473 config_id_frame_v2_hw(hisi_hba, phy_no);
1474 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1475 enable_phy_v2_hw(hisi_hba, phy_no);
1476 }
1477
1478 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1479 {
1480 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1481 u32 txid_auto;
1482
1483 disable_phy_v2_hw(hisi_hba, phy_no);
1484 if (phy->identify.device_type == SAS_END_DEVICE) {
1485 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1486 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1487 txid_auto | TX_HARDRST_MSK);
1488 }
1489 msleep(100);
1490 start_phy_v2_hw(hisi_hba, phy_no);
1491 }
1492
1493 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1494 {
1495 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1496 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1497 struct sas_phy *sphy = sas_phy->phy;
1498 u32 err4_reg_val, err6_reg_val;
1499
1500 /* loss dword syn, phy reset problem */
1501 err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1502
1503 /* disparity err, invalid dword */
1504 err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1505
1506 sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1507 sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1508 sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1509 sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1510 }
1511
1512 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1513 {
1514 int i;
1515
1516 for (i = 0; i < hisi_hba->n_phy; i++) {
1517 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1518 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1519
1520 if (!sas_phy->phy->enabled)
1521 continue;
1522
1523 start_phy_v2_hw(hisi_hba, i);
1524 }
1525 }
1526
1527 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1528 {
1529 u32 sl_control;
1530
1531 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1532 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1533 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1534 msleep(1);
1535 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1536 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1537 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1538 }
1539
1540 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1541 {
1542 return SAS_LINK_RATE_12_0_GBPS;
1543 }
1544
1545 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1546 struct sas_phy_linkrates *r)
1547 {
1548 u32 prog_phy_link_rate =
1549 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1550 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1551 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1552 int i;
1553 enum sas_linkrate min, max;
1554 u32 rate_mask = 0;
1555
1556 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1557 max = sas_phy->phy->maximum_linkrate;
1558 min = r->minimum_linkrate;
1559 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1560 max = r->maximum_linkrate;
1561 min = sas_phy->phy->minimum_linkrate;
1562 } else
1563 return;
1564
1565 sas_phy->phy->maximum_linkrate = max;
1566 sas_phy->phy->minimum_linkrate = min;
1567
1568 min -= SAS_LINK_RATE_1_5_GBPS;
1569 max -= SAS_LINK_RATE_1_5_GBPS;
1570
1571 for (i = 0; i <= max; i++)
1572 rate_mask |= 1 << (i * 2);
1573
1574 prog_phy_link_rate &= ~0xff;
1575 prog_phy_link_rate |= rate_mask;
1576
1577 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1578 prog_phy_link_rate);
1579
1580 phy_hard_reset_v2_hw(hisi_hba, phy_no);
1581 }
1582
1583 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1584 {
1585 int i, bitmap = 0;
1586 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1587 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1588
1589 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1590 if (phy_state & 1 << i)
1591 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1592 bitmap |= 1 << i;
1593
1594 if (hisi_hba->n_phy == 9) {
1595 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1596
1597 if (phy_state & 1 << 8)
1598 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1599 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1600 bitmap |= 1 << 9;
1601 }
1602
1603 return bitmap;
1604 }
1605
1606 /*
1607 * The callpath to this function and upto writing the write
1608 * queue pointer should be safe from interruption.
1609 */
1610 static int
1611 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1612 {
1613 struct device *dev = hisi_hba->dev;
1614 int queue = dq->id;
1615 u32 r, w;
1616
1617 w = dq->wr_point;
1618 r = hisi_sas_read32_relaxed(hisi_hba,
1619 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1620 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1621 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
1622 queue, r, w);
1623 return -EAGAIN;
1624 }
1625
1626 return 0;
1627 }
1628
1629 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1630 {
1631 struct hisi_hba *hisi_hba = dq->hisi_hba;
1632 int dlvry_queue = dq->slot_prep->dlvry_queue;
1633 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
1634
1635 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1636 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1637 dq->wr_point);
1638 }
1639
1640 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1641 struct hisi_sas_slot *slot,
1642 struct hisi_sas_cmd_hdr *hdr,
1643 struct scatterlist *scatter,
1644 int n_elem)
1645 {
1646 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1647 struct device *dev = hisi_hba->dev;
1648 struct scatterlist *sg;
1649 int i;
1650
1651 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1652 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1653 n_elem);
1654 return -EINVAL;
1655 }
1656
1657 for_each_sg(scatter, sg, n_elem, i) {
1658 struct hisi_sas_sge *entry = &sge_page->sge[i];
1659
1660 entry->addr = cpu_to_le64(sg_dma_address(sg));
1661 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1662 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1663 entry->data_off = 0;
1664 }
1665
1666 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1667
1668 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1669
1670 return 0;
1671 }
1672
1673 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1674 struct hisi_sas_slot *slot)
1675 {
1676 struct sas_task *task = slot->task;
1677 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1678 struct domain_device *device = task->dev;
1679 struct device *dev = hisi_hba->dev;
1680 struct hisi_sas_port *port = slot->port;
1681 struct scatterlist *sg_req, *sg_resp;
1682 struct hisi_sas_device *sas_dev = device->lldd_dev;
1683 dma_addr_t req_dma_addr;
1684 unsigned int req_len, resp_len;
1685 int elem, rc;
1686
1687 /*
1688 * DMA-map SMP request, response buffers
1689 */
1690 /* req */
1691 sg_req = &task->smp_task.smp_req;
1692 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1693 if (!elem)
1694 return -ENOMEM;
1695 req_len = sg_dma_len(sg_req);
1696 req_dma_addr = sg_dma_address(sg_req);
1697
1698 /* resp */
1699 sg_resp = &task->smp_task.smp_resp;
1700 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1701 if (!elem) {
1702 rc = -ENOMEM;
1703 goto err_out_req;
1704 }
1705 resp_len = sg_dma_len(sg_resp);
1706 if ((req_len & 0x3) || (resp_len & 0x3)) {
1707 rc = -EINVAL;
1708 goto err_out_resp;
1709 }
1710
1711 /* create header */
1712 /* dw0 */
1713 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1714 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1715 (2 << CMD_HDR_CMD_OFF)); /* smp */
1716
1717 /* map itct entry */
1718 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1719 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1720 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1721
1722 /* dw2 */
1723 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1724 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1725 CMD_HDR_MRFL_OFF));
1726
1727 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1728
1729 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1730 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1731
1732 return 0;
1733
1734 err_out_resp:
1735 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1736 DMA_FROM_DEVICE);
1737 err_out_req:
1738 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1739 DMA_TO_DEVICE);
1740 return rc;
1741 }
1742
1743 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1744 struct hisi_sas_slot *slot, int is_tmf,
1745 struct hisi_sas_tmf_task *tmf)
1746 {
1747 struct sas_task *task = slot->task;
1748 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1749 struct domain_device *device = task->dev;
1750 struct hisi_sas_device *sas_dev = device->lldd_dev;
1751 struct hisi_sas_port *port = slot->port;
1752 struct sas_ssp_task *ssp_task = &task->ssp_task;
1753 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1754 int has_data = 0, rc, priority = is_tmf;
1755 u8 *buf_cmd;
1756 u32 dw1 = 0, dw2 = 0;
1757
1758 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1759 (2 << CMD_HDR_TLR_CTRL_OFF) |
1760 (port->id << CMD_HDR_PORT_OFF) |
1761 (priority << CMD_HDR_PRIORITY_OFF) |
1762 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1763
1764 dw1 = 1 << CMD_HDR_VDTL_OFF;
1765 if (is_tmf) {
1766 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1767 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1768 } else {
1769 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1770 switch (scsi_cmnd->sc_data_direction) {
1771 case DMA_TO_DEVICE:
1772 has_data = 1;
1773 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1774 break;
1775 case DMA_FROM_DEVICE:
1776 has_data = 1;
1777 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1778 break;
1779 default:
1780 dw1 &= ~CMD_HDR_DIR_MSK;
1781 }
1782 }
1783
1784 /* map itct entry */
1785 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1786 hdr->dw1 = cpu_to_le32(dw1);
1787
1788 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1789 + 3) / 4) << CMD_HDR_CFL_OFF) |
1790 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1791 (2 << CMD_HDR_SG_MOD_OFF);
1792 hdr->dw2 = cpu_to_le32(dw2);
1793
1794 hdr->transfer_tags = cpu_to_le32(slot->idx);
1795
1796 if (has_data) {
1797 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1798 slot->n_elem);
1799 if (rc)
1800 return rc;
1801 }
1802
1803 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1804 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1805 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1806
1807 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1808 sizeof(struct ssp_frame_hdr);
1809
1810 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1811 if (!is_tmf) {
1812 buf_cmd[9] = task->ssp_task.task_attr |
1813 (task->ssp_task.task_prio << 3);
1814 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1815 task->ssp_task.cmd->cmd_len);
1816 } else {
1817 buf_cmd[10] = tmf->tmf;
1818 switch (tmf->tmf) {
1819 case TMF_ABORT_TASK:
1820 case TMF_QUERY_TASK:
1821 buf_cmd[12] =
1822 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1823 buf_cmd[13] =
1824 tmf->tag_of_task_to_be_managed & 0xff;
1825 break;
1826 default:
1827 break;
1828 }
1829 }
1830
1831 return 0;
1832 }
1833
1834 #define TRANS_TX_ERR 0
1835 #define TRANS_RX_ERR 1
1836 #define DMA_TX_ERR 2
1837 #define SIPC_RX_ERR 3
1838 #define DMA_RX_ERR 4
1839
1840 #define DMA_TX_ERR_OFF 0
1841 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1842 #define SIPC_RX_ERR_OFF 16
1843 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1844
1845 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1846 {
1847 static const u8 trans_tx_err_code_prio[] = {
1848 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1849 TRANS_TX_ERR_PHY_NOT_ENABLE,
1850 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1851 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1852 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1853 RESERVED0,
1854 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1855 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1856 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1857 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1858 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1859 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1860 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1861 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1862 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1863 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1864 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1865 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1866 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1867 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1868 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1869 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1870 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1871 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1872 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1873 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1874 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1875 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1876 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1877 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1878 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1879 };
1880 int index, i;
1881
1882 for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1883 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1884 if (err_msk & (1 << index))
1885 return trans_tx_err_code_prio[i];
1886 }
1887 return -1;
1888 }
1889
1890 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1891 {
1892 static const u8 trans_rx_err_code_prio[] = {
1893 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1894 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1895 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1896 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1897 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1898 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1899 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1900 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1901 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1902 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1903 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1904 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1905 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1906 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1907 RESERVED1,
1908 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1909 TRANS_RX_ERR_WITH_DATA_LEN0,
1910 TRANS_RX_ERR_WITH_BAD_HASH,
1911 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1912 TRANS_RX_SSP_FRM_LEN_ERR,
1913 RESERVED2,
1914 RESERVED3,
1915 RESERVED4,
1916 RESERVED5,
1917 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1918 TRANS_RX_SMP_FRM_LEN_ERR,
1919 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1920 RESERVED6,
1921 RESERVED7,
1922 RESERVED8,
1923 RESERVED9,
1924 TRANS_RX_R_ERR,
1925 };
1926 int index, i;
1927
1928 for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1929 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1930 if (err_msk & (1 << index))
1931 return trans_rx_err_code_prio[i];
1932 }
1933 return -1;
1934 }
1935
1936 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1937 {
1938 static const u8 dma_tx_err_code_prio[] = {
1939 DMA_TX_UNEXP_XFER_ERR,
1940 DMA_TX_UNEXP_RETRANS_ERR,
1941 DMA_TX_XFER_LEN_OVERFLOW,
1942 DMA_TX_XFER_OFFSET_ERR,
1943 DMA_TX_RAM_ECC_ERR,
1944 DMA_TX_DIF_LEN_ALIGN_ERR,
1945 DMA_TX_DIF_CRC_ERR,
1946 DMA_TX_DIF_APP_ERR,
1947 DMA_TX_DIF_RPP_ERR,
1948 DMA_TX_DATA_SGL_OVERFLOW,
1949 DMA_TX_DIF_SGL_OVERFLOW,
1950 };
1951 int index, i;
1952
1953 for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1954 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1955 err_msk = err_msk & DMA_TX_ERR_MSK;
1956 if (err_msk & (1 << index))
1957 return dma_tx_err_code_prio[i];
1958 }
1959 return -1;
1960 }
1961
1962 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1963 {
1964 static const u8 sipc_rx_err_code_prio[] = {
1965 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1966 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1967 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1968 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1969 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1970 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1971 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1972 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1973 SIPC_RX_SATA_UNEXP_FIS_ERR,
1974 SIPC_RX_WRSETUP_ESTATUS_ERR,
1975 SIPC_RX_DATA_UNDERFLOW_ERR,
1976 };
1977 int index, i;
1978
1979 for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1980 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1981 err_msk = err_msk & SIPC_RX_ERR_MSK;
1982 if (err_msk & (1 << (index + 0x10)))
1983 return sipc_rx_err_code_prio[i];
1984 }
1985 return -1;
1986 }
1987
1988 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
1989 {
1990 static const u8 dma_rx_err_code_prio[] = {
1991 DMA_RX_UNKNOWN_FRM_ERR,
1992 DMA_RX_DATA_LEN_OVERFLOW,
1993 DMA_RX_DATA_LEN_UNDERFLOW,
1994 DMA_RX_DATA_OFFSET_ERR,
1995 RESERVED10,
1996 DMA_RX_SATA_FRAME_TYPE_ERR,
1997 DMA_RX_RESP_BUF_OVERFLOW,
1998 DMA_RX_UNEXP_RETRANS_RESP_ERR,
1999 DMA_RX_UNEXP_NORM_RESP_ERR,
2000 DMA_RX_UNEXP_RDFRAME_ERR,
2001 DMA_RX_PIO_DATA_LEN_ERR,
2002 DMA_RX_RDSETUP_STATUS_ERR,
2003 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2004 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2005 DMA_RX_RDSETUP_LEN_ODD_ERR,
2006 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2007 DMA_RX_RDSETUP_LEN_OVER_ERR,
2008 DMA_RX_RDSETUP_OFFSET_ERR,
2009 DMA_RX_RDSETUP_ACTIVE_ERR,
2010 DMA_RX_RDSETUP_ESTATUS_ERR,
2011 DMA_RX_RAM_ECC_ERR,
2012 DMA_RX_DIF_CRC_ERR,
2013 DMA_RX_DIF_APP_ERR,
2014 DMA_RX_DIF_RPP_ERR,
2015 DMA_RX_DATA_SGL_OVERFLOW,
2016 DMA_RX_DIF_SGL_OVERFLOW,
2017 };
2018 int index, i;
2019
2020 for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2021 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2022 if (err_msk & (1 << index))
2023 return dma_rx_err_code_prio[i];
2024 }
2025 return -1;
2026 }
2027
2028 /* by default, task resp is complete */
2029 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2030 struct sas_task *task,
2031 struct hisi_sas_slot *slot,
2032 int err_phase)
2033 {
2034 struct task_status_struct *ts = &task->task_status;
2035 struct hisi_sas_err_record_v2 *err_record =
2036 hisi_sas_status_buf_addr_mem(slot);
2037 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2038 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2039 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2040 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2041 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2042 int error = -1;
2043
2044 if (err_phase == 1) {
2045 /* error in TX phase, the priority of error is: DW2 > DW0 */
2046 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2047 if (error == -1)
2048 error = parse_trans_tx_err_code_v2_hw(
2049 trans_tx_fail_type);
2050 } else if (err_phase == 2) {
2051 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2052 error = parse_trans_rx_err_code_v2_hw(
2053 trans_rx_fail_type);
2054 if (error == -1) {
2055 error = parse_dma_rx_err_code_v2_hw(
2056 dma_rx_err_type);
2057 if (error == -1)
2058 error = parse_sipc_rx_err_code_v2_hw(
2059 sipc_rx_err_type);
2060 }
2061 }
2062
2063 switch (task->task_proto) {
2064 case SAS_PROTOCOL_SSP:
2065 {
2066 switch (error) {
2067 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2068 {
2069 ts->stat = SAS_OPEN_REJECT;
2070 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2071 break;
2072 }
2073 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2074 {
2075 ts->stat = SAS_OPEN_REJECT;
2076 ts->open_rej_reason = SAS_OREJ_EPROTO;
2077 break;
2078 }
2079 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2080 {
2081 ts->stat = SAS_OPEN_REJECT;
2082 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2083 break;
2084 }
2085 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2086 {
2087 ts->stat = SAS_OPEN_REJECT;
2088 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2089 break;
2090 }
2091 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2092 {
2093 ts->stat = SAS_OPEN_REJECT;
2094 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2095 break;
2096 }
2097 case DMA_RX_UNEXP_NORM_RESP_ERR:
2098 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2099 case DMA_RX_RESP_BUF_OVERFLOW:
2100 {
2101 ts->stat = SAS_OPEN_REJECT;
2102 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2103 break;
2104 }
2105 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2106 {
2107 /* not sure */
2108 ts->stat = SAS_DEV_NO_RESPONSE;
2109 break;
2110 }
2111 case DMA_RX_DATA_LEN_OVERFLOW:
2112 {
2113 ts->stat = SAS_DATA_OVERRUN;
2114 ts->residual = 0;
2115 break;
2116 }
2117 case DMA_RX_DATA_LEN_UNDERFLOW:
2118 {
2119 ts->residual = trans_tx_fail_type;
2120 ts->stat = SAS_DATA_UNDERRUN;
2121 break;
2122 }
2123 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2124 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2125 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2126 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2127 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2128 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2129 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2130 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2131 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2132 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2133 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2134 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2135 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2136 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2137 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2138 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2139 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2140 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2141 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2142 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2143 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2144 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2145 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2146 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2147 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2148 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2149 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2150 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2151 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2152 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2153 case TRANS_TX_ERR_FRAME_TXED:
2154 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2155 case TRANS_RX_ERR_WITH_DATA_LEN0:
2156 case TRANS_RX_ERR_WITH_BAD_HASH:
2157 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2158 case TRANS_RX_SSP_FRM_LEN_ERR:
2159 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2160 case DMA_TX_DATA_SGL_OVERFLOW:
2161 case DMA_TX_UNEXP_XFER_ERR:
2162 case DMA_TX_UNEXP_RETRANS_ERR:
2163 case DMA_TX_XFER_LEN_OVERFLOW:
2164 case DMA_TX_XFER_OFFSET_ERR:
2165 case SIPC_RX_DATA_UNDERFLOW_ERR:
2166 case DMA_RX_DATA_SGL_OVERFLOW:
2167 case DMA_RX_DATA_OFFSET_ERR:
2168 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2169 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2170 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2171 case DMA_RX_SATA_FRAME_TYPE_ERR:
2172 case DMA_RX_UNKNOWN_FRM_ERR:
2173 {
2174 /* This will request a retry */
2175 ts->stat = SAS_QUEUE_FULL;
2176 slot->abort = 1;
2177 break;
2178 }
2179 default:
2180 break;
2181 }
2182 }
2183 break;
2184 case SAS_PROTOCOL_SMP:
2185 ts->stat = SAM_STAT_CHECK_CONDITION;
2186 break;
2187
2188 case SAS_PROTOCOL_SATA:
2189 case SAS_PROTOCOL_STP:
2190 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2191 {
2192 switch (error) {
2193 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2194 {
2195 ts->stat = SAS_OPEN_REJECT;
2196 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2197 break;
2198 }
2199 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2200 {
2201 ts->resp = SAS_TASK_UNDELIVERED;
2202 ts->stat = SAS_DEV_NO_RESPONSE;
2203 break;
2204 }
2205 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2206 {
2207 ts->stat = SAS_OPEN_REJECT;
2208 ts->open_rej_reason = SAS_OREJ_EPROTO;
2209 break;
2210 }
2211 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2212 {
2213 ts->stat = SAS_OPEN_REJECT;
2214 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2215 break;
2216 }
2217 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2218 {
2219 ts->stat = SAS_OPEN_REJECT;
2220 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2221 break;
2222 }
2223 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2224 {
2225 ts->stat = SAS_OPEN_REJECT;
2226 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2227 break;
2228 }
2229 case DMA_RX_RESP_BUF_OVERFLOW:
2230 case DMA_RX_UNEXP_NORM_RESP_ERR:
2231 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2232 {
2233 ts->stat = SAS_OPEN_REJECT;
2234 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2235 break;
2236 }
2237 case DMA_RX_DATA_LEN_OVERFLOW:
2238 {
2239 ts->stat = SAS_DATA_OVERRUN;
2240 ts->residual = 0;
2241 break;
2242 }
2243 case DMA_RX_DATA_LEN_UNDERFLOW:
2244 {
2245 ts->residual = trans_tx_fail_type;
2246 ts->stat = SAS_DATA_UNDERRUN;
2247 break;
2248 }
2249 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2250 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2251 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2252 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2253 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2254 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2255 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2256 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2257 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2258 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2259 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2260 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2261 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2262 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2263 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2264 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2265 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2266 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2267 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2268 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2269 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2270 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2271 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2272 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2273 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2274 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2275 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2276 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2277 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2278 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2279 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2280 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2281 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2282 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2283 case TRANS_RX_ERR_WITH_DATA_LEN0:
2284 case TRANS_RX_ERR_WITH_BAD_HASH:
2285 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2286 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2287 case DMA_TX_DATA_SGL_OVERFLOW:
2288 case DMA_TX_UNEXP_XFER_ERR:
2289 case DMA_TX_UNEXP_RETRANS_ERR:
2290 case DMA_TX_XFER_LEN_OVERFLOW:
2291 case DMA_TX_XFER_OFFSET_ERR:
2292 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2293 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2294 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2295 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2296 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2297 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2298 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2299 case DMA_RX_DATA_SGL_OVERFLOW:
2300 case DMA_RX_DATA_OFFSET_ERR:
2301 case DMA_RX_SATA_FRAME_TYPE_ERR:
2302 case DMA_RX_UNEXP_RDFRAME_ERR:
2303 case DMA_RX_PIO_DATA_LEN_ERR:
2304 case DMA_RX_RDSETUP_STATUS_ERR:
2305 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2306 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2307 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2308 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2309 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2310 case DMA_RX_RDSETUP_OFFSET_ERR:
2311 case DMA_RX_RDSETUP_ACTIVE_ERR:
2312 case DMA_RX_RDSETUP_ESTATUS_ERR:
2313 case DMA_RX_UNKNOWN_FRM_ERR:
2314 case TRANS_RX_SSP_FRM_LEN_ERR:
2315 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2316 {
2317 slot->abort = 1;
2318 ts->stat = SAS_PHY_DOWN;
2319 break;
2320 }
2321 default:
2322 {
2323 ts->stat = SAS_PROTO_RESPONSE;
2324 break;
2325 }
2326 }
2327 hisi_sas_sata_done(task, slot);
2328 }
2329 break;
2330 default:
2331 break;
2332 }
2333 }
2334
2335 static int
2336 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2337 {
2338 struct sas_task *task = slot->task;
2339 struct hisi_sas_device *sas_dev;
2340 struct device *dev = hisi_hba->dev;
2341 struct task_status_struct *ts;
2342 struct domain_device *device;
2343 enum exec_status sts;
2344 struct hisi_sas_complete_v2_hdr *complete_queue =
2345 hisi_hba->complete_hdr[slot->cmplt_queue];
2346 struct hisi_sas_complete_v2_hdr *complete_hdr =
2347 &complete_queue[slot->cmplt_queue_slot];
2348 unsigned long flags;
2349 int aborted;
2350
2351 if (unlikely(!task || !task->lldd_task || !task->dev))
2352 return -EINVAL;
2353
2354 ts = &task->task_status;
2355 device = task->dev;
2356 sas_dev = device->lldd_dev;
2357
2358 spin_lock_irqsave(&task->task_state_lock, flags);
2359 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
2360 task->task_state_flags &=
2361 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2362 spin_unlock_irqrestore(&task->task_state_lock, flags);
2363
2364 memset(ts, 0, sizeof(*ts));
2365 ts->resp = SAS_TASK_COMPLETE;
2366
2367 if (unlikely(aborted)) {
2368 dev_dbg(dev, "slot_complete: task(%p) aborted\n", task);
2369 ts->stat = SAS_ABORTED_TASK;
2370 spin_lock_irqsave(&hisi_hba->lock, flags);
2371 hisi_sas_slot_task_free(hisi_hba, task, slot);
2372 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2373 return -1;
2374 }
2375
2376 if (unlikely(!sas_dev)) {
2377 dev_dbg(dev, "slot complete: port has no device\n");
2378 ts->stat = SAS_PHY_DOWN;
2379 goto out;
2380 }
2381
2382 /* Use SAS+TMF status codes */
2383 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2384 >> CMPLT_HDR_ABORT_STAT_OFF) {
2385 case STAT_IO_ABORTED:
2386 /* this io has been aborted by abort command */
2387 ts->stat = SAS_ABORTED_TASK;
2388 goto out;
2389 case STAT_IO_COMPLETE:
2390 /* internal abort command complete */
2391 ts->stat = TMF_RESP_FUNC_SUCC;
2392 del_timer(&slot->internal_abort_timer);
2393 goto out;
2394 case STAT_IO_NO_DEVICE:
2395 ts->stat = TMF_RESP_FUNC_COMPLETE;
2396 del_timer(&slot->internal_abort_timer);
2397 goto out;
2398 case STAT_IO_NOT_VALID:
2399 /* abort single io, controller don't find
2400 * the io need to abort
2401 */
2402 ts->stat = TMF_RESP_FUNC_FAILED;
2403 del_timer(&slot->internal_abort_timer);
2404 goto out;
2405 default:
2406 break;
2407 }
2408
2409 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2410 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2411 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2412 >> CMPLT_HDR_ERR_PHASE_OFF;
2413 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2414
2415 /* Analyse error happens on which phase TX or RX */
2416 if (ERR_ON_TX_PHASE(err_phase))
2417 slot_err_v2_hw(hisi_hba, task, slot, 1);
2418 else if (ERR_ON_RX_PHASE(err_phase))
2419 slot_err_v2_hw(hisi_hba, task, slot, 2);
2420
2421 if (ts->stat != SAS_DATA_UNDERRUN)
2422 dev_info(dev, "erroneous completion iptt=%d task=%p "
2423 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
2424 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
2425 slot->idx, task,
2426 complete_hdr->dw0, complete_hdr->dw1,
2427 complete_hdr->act, complete_hdr->dw3,
2428 error_info[0], error_info[1],
2429 error_info[2], error_info[3]);
2430
2431 if (unlikely(slot->abort))
2432 return ts->stat;
2433 goto out;
2434 }
2435
2436 switch (task->task_proto) {
2437 case SAS_PROTOCOL_SSP:
2438 {
2439 struct hisi_sas_status_buffer *status_buffer =
2440 hisi_sas_status_buf_addr_mem(slot);
2441 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2442 &status_buffer->iu[0];
2443
2444 sas_ssp_task_response(dev, task, iu);
2445 break;
2446 }
2447 case SAS_PROTOCOL_SMP:
2448 {
2449 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2450 void *to;
2451
2452 ts->stat = SAM_STAT_GOOD;
2453 to = kmap_atomic(sg_page(sg_resp));
2454
2455 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2456 DMA_FROM_DEVICE);
2457 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2458 DMA_TO_DEVICE);
2459 memcpy(to + sg_resp->offset,
2460 hisi_sas_status_buf_addr_mem(slot) +
2461 sizeof(struct hisi_sas_err_record),
2462 sg_dma_len(sg_resp));
2463 kunmap_atomic(to);
2464 break;
2465 }
2466 case SAS_PROTOCOL_SATA:
2467 case SAS_PROTOCOL_STP:
2468 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2469 {
2470 ts->stat = SAM_STAT_GOOD;
2471 hisi_sas_sata_done(task, slot);
2472 break;
2473 }
2474 default:
2475 ts->stat = SAM_STAT_CHECK_CONDITION;
2476 break;
2477 }
2478
2479 if (!slot->port->port_attached) {
2480 dev_warn(dev, "slot complete: port %d has removed\n",
2481 slot->port->sas_port.id);
2482 ts->stat = SAS_PHY_DOWN;
2483 }
2484
2485 out:
2486 spin_lock_irqsave(&task->task_state_lock, flags);
2487 task->task_state_flags |= SAS_TASK_STATE_DONE;
2488 spin_unlock_irqrestore(&task->task_state_lock, flags);
2489 spin_lock_irqsave(&hisi_hba->lock, flags);
2490 hisi_sas_slot_task_free(hisi_hba, task, slot);
2491 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2492 sts = ts->stat;
2493
2494 if (task->task_done)
2495 task->task_done(task);
2496
2497 return sts;
2498 }
2499
2500 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2501 struct hisi_sas_slot *slot)
2502 {
2503 struct sas_task *task = slot->task;
2504 struct domain_device *device = task->dev;
2505 struct domain_device *parent_dev = device->parent;
2506 struct hisi_sas_device *sas_dev = device->lldd_dev;
2507 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2508 struct asd_sas_port *sas_port = device->port;
2509 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2510 u8 *buf_cmd;
2511 int has_data = 0, rc = 0, hdr_tag = 0;
2512 u32 dw1 = 0, dw2 = 0;
2513
2514 /* create header */
2515 /* dw0 */
2516 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2517 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2518 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2519 else
2520 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2521
2522 /* dw1 */
2523 switch (task->data_dir) {
2524 case DMA_TO_DEVICE:
2525 has_data = 1;
2526 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2527 break;
2528 case DMA_FROM_DEVICE:
2529 has_data = 1;
2530 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2531 break;
2532 default:
2533 dw1 &= ~CMD_HDR_DIR_MSK;
2534 }
2535
2536 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2537 (task->ata_task.fis.control & ATA_SRST))
2538 dw1 |= 1 << CMD_HDR_RESET_OFF;
2539
2540 dw1 |= (hisi_sas_get_ata_protocol(
2541 task->ata_task.fis.command, task->data_dir))
2542 << CMD_HDR_FRAME_TYPE_OFF;
2543 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2544 hdr->dw1 = cpu_to_le32(dw1);
2545
2546 /* dw2 */
2547 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2548 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2549 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2550 }
2551
2552 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2553 2 << CMD_HDR_SG_MOD_OFF;
2554 hdr->dw2 = cpu_to_le32(dw2);
2555
2556 /* dw3 */
2557 hdr->transfer_tags = cpu_to_le32(slot->idx);
2558
2559 if (has_data) {
2560 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2561 slot->n_elem);
2562 if (rc)
2563 return rc;
2564 }
2565
2566 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2567 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2568 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2569
2570 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2571
2572 if (likely(!task->ata_task.device_control_reg_update))
2573 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2574 /* fill in command FIS */
2575 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2576
2577 return 0;
2578 }
2579
2580 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
2581 {
2582 struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
2583 struct hisi_sas_port *port = slot->port;
2584 struct asd_sas_port *asd_sas_port;
2585 struct asd_sas_phy *sas_phy;
2586
2587 if (!port)
2588 return;
2589
2590 asd_sas_port = &port->sas_port;
2591
2592 /* Kick the hardware - send break command */
2593 list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2594 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2595 struct hisi_hba *hisi_hba = phy->hisi_hba;
2596 int phy_no = sas_phy->id;
2597 u32 link_dfx2;
2598
2599 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2600 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2601 (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2602 u32 txid_auto;
2603
2604 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2605 TXID_AUTO);
2606 txid_auto |= TXID_AUTO_CTB_MSK;
2607 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2608 txid_auto);
2609 return;
2610 }
2611 }
2612 }
2613
2614 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2615 struct hisi_sas_slot *slot,
2616 int device_id, int abort_flag, int tag_to_abort)
2617 {
2618 struct sas_task *task = slot->task;
2619 struct domain_device *dev = task->dev;
2620 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2621 struct hisi_sas_port *port = slot->port;
2622 struct timer_list *timer = &slot->internal_abort_timer;
2623
2624 /* setup the quirk timer */
2625 timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
2626 /* Set the timeout to 10ms less than internal abort timeout */
2627 mod_timer(timer, jiffies + msecs_to_jiffies(100));
2628
2629 /* dw0 */
2630 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2631 (port->id << CMD_HDR_PORT_OFF) |
2632 ((dev_is_sata(dev) ? 1:0) <<
2633 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2634 (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2635
2636 /* dw1 */
2637 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2638
2639 /* dw7 */
2640 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2641 hdr->transfer_tags = cpu_to_le32(slot->idx);
2642
2643 return 0;
2644 }
2645
2646 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2647 {
2648 int i, res = IRQ_HANDLED;
2649 u32 port_id, link_rate, hard_phy_linkrate;
2650 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2651 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2652 struct device *dev = hisi_hba->dev;
2653 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2654 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2655
2656 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2657
2658 if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2659 goto end;
2660
2661 if (phy_no == 8) {
2662 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2663
2664 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2665 PORT_STATE_PHY8_PORT_NUM_OFF;
2666 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2667 PORT_STATE_PHY8_CONN_RATE_OFF;
2668 } else {
2669 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2670 port_id = (port_id >> (4 * phy_no)) & 0xf;
2671 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2672 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2673 }
2674
2675 if (port_id == 0xf) {
2676 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2677 res = IRQ_NONE;
2678 goto end;
2679 }
2680
2681 for (i = 0; i < 6; i++) {
2682 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2683 RX_IDAF_DWORD0 + (i * 4));
2684 frame_rcvd[i] = __swab32(idaf);
2685 }
2686
2687 sas_phy->linkrate = link_rate;
2688 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2689 HARD_PHY_LINKRATE);
2690 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2691 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2692
2693 sas_phy->oob_mode = SAS_OOB_MODE;
2694 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2695 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2696 phy->port_id = port_id;
2697 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2698 phy->phy_type |= PORT_TYPE_SAS;
2699 phy->phy_attached = 1;
2700 phy->identify.device_type = id->dev_type;
2701 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
2702 if (phy->identify.device_type == SAS_END_DEVICE)
2703 phy->identify.target_port_protocols =
2704 SAS_PROTOCOL_SSP;
2705 else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2706 phy->identify.target_port_protocols =
2707 SAS_PROTOCOL_SMP;
2708 if (!timer_pending(&hisi_hba->timer))
2709 set_link_timer_quirk(hisi_hba);
2710 }
2711 queue_work(hisi_hba->wq, &phy->phyup_ws);
2712
2713 end:
2714 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2715 CHL_INT0_SL_PHY_ENABLE_MSK);
2716 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2717
2718 return res;
2719 }
2720
2721 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2722 {
2723 u32 port_state;
2724
2725 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2726 if (port_state & 0x1ff)
2727 return true;
2728
2729 return false;
2730 }
2731
2732 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2733 {
2734 u32 phy_state, sl_ctrl, txid_auto;
2735 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2736 struct hisi_sas_port *port = phy->port;
2737 struct device *dev = hisi_hba->dev;
2738
2739 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2740
2741 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2742 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
2743 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2744
2745 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2746 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2747 sl_ctrl & ~SL_CONTROL_CTA_MSK);
2748 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2749 if (!check_any_wideports_v2_hw(hisi_hba) &&
2750 timer_pending(&hisi_hba->timer))
2751 del_timer(&hisi_hba->timer);
2752
2753 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2754 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2755 txid_auto | TXID_AUTO_CT3_MSK);
2756
2757 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2758 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2759
2760 return IRQ_HANDLED;
2761 }
2762
2763 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2764 {
2765 struct hisi_hba *hisi_hba = p;
2766 u32 irq_msk;
2767 int phy_no = 0;
2768 irqreturn_t res = IRQ_NONE;
2769
2770 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2771 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2772 while (irq_msk) {
2773 if (irq_msk & 1) {
2774 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2775 CHL_INT0);
2776
2777 switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2778 CHL_INT0_SL_PHY_ENABLE_MSK)) {
2779
2780 case CHL_INT0_SL_PHY_ENABLE_MSK:
2781 /* phy up */
2782 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2783 IRQ_HANDLED)
2784 res = IRQ_HANDLED;
2785 break;
2786
2787 case CHL_INT0_NOT_RDY_MSK:
2788 /* phy down */
2789 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2790 IRQ_HANDLED)
2791 res = IRQ_HANDLED;
2792 break;
2793
2794 case (CHL_INT0_NOT_RDY_MSK |
2795 CHL_INT0_SL_PHY_ENABLE_MSK):
2796 reg_value = hisi_sas_read32(hisi_hba,
2797 PHY_STATE);
2798 if (reg_value & BIT(phy_no)) {
2799 /* phy up */
2800 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2801 IRQ_HANDLED)
2802 res = IRQ_HANDLED;
2803 } else {
2804 /* phy down */
2805 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2806 IRQ_HANDLED)
2807 res = IRQ_HANDLED;
2808 }
2809 break;
2810
2811 default:
2812 break;
2813 }
2814
2815 }
2816 irq_msk >>= 1;
2817 phy_no++;
2818 }
2819
2820 return res;
2821 }
2822
2823 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2824 {
2825 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2826 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2827 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2828 u32 bcast_status;
2829
2830 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2831 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2832 if (bcast_status & RX_BCAST_CHG_MSK)
2833 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2834 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2835 CHL_INT0_SL_RX_BCST_ACK_MSK);
2836 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2837 }
2838
2839 static const struct hisi_sas_hw_error port_ecc_axi_error[] = {
2840 {
2841 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF),
2842 .msg = "dmac_tx_ecc_bad_err",
2843 },
2844 {
2845 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF),
2846 .msg = "dmac_rx_ecc_bad_err",
2847 },
2848 {
2849 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
2850 .msg = "dma_tx_axi_wr_err",
2851 },
2852 {
2853 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
2854 .msg = "dma_tx_axi_rd_err",
2855 },
2856 {
2857 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
2858 .msg = "dma_rx_axi_wr_err",
2859 },
2860 {
2861 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
2862 .msg = "dma_rx_axi_rd_err",
2863 },
2864 };
2865
2866 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2867 {
2868 struct hisi_hba *hisi_hba = p;
2869 struct device *dev = hisi_hba->dev;
2870 u32 ent_msk, ent_tmp, irq_msk;
2871 int phy_no = 0;
2872
2873 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2874 ent_tmp = ent_msk;
2875 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2876 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2877
2878 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2879 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2880
2881 while (irq_msk) {
2882 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2883 CHL_INT0);
2884 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2885 CHL_INT1);
2886 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2887 CHL_INT2);
2888
2889 if ((irq_msk & (1 << phy_no)) && irq_value1) {
2890 int i;
2891
2892 for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) {
2893 const struct hisi_sas_hw_error *error =
2894 &port_ecc_axi_error[i];
2895
2896 if (!(irq_value1 & error->irq_msk))
2897 continue;
2898
2899 dev_warn(dev, "%s error (phy%d 0x%x) found!\n",
2900 error->msg, phy_no, irq_value1);
2901 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2902 }
2903
2904 hisi_sas_phy_write32(hisi_hba, phy_no,
2905 CHL_INT1, irq_value1);
2906 }
2907
2908 if ((irq_msk & (1 << phy_no)) && irq_value2)
2909 hisi_sas_phy_write32(hisi_hba, phy_no,
2910 CHL_INT2, irq_value2);
2911
2912
2913 if ((irq_msk & (1 << phy_no)) && irq_value0) {
2914 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2915 phy_bcast_v2_hw(phy_no, hisi_hba);
2916
2917 hisi_sas_phy_write32(hisi_hba, phy_no,
2918 CHL_INT0, irq_value0
2919 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2920 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2921 & (~CHL_INT0_NOT_RDY_MSK));
2922 }
2923 irq_msk &= ~(1 << phy_no);
2924 phy_no++;
2925 }
2926
2927 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2928
2929 return IRQ_HANDLED;
2930 }
2931
2932 static void
2933 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2934 {
2935 struct device *dev = hisi_hba->dev;
2936 const struct hisi_sas_hw_error *ecc_error;
2937 u32 val;
2938 int i;
2939
2940 for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2941 ecc_error = &one_bit_ecc_errors[i];
2942 if (irq_value & ecc_error->irq_msk) {
2943 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2944 val &= ecc_error->msk;
2945 val >>= ecc_error->shift;
2946 dev_warn(dev, ecc_error->msg, val);
2947 }
2948 }
2949 }
2950
2951 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2952 u32 irq_value)
2953 {
2954 struct device *dev = hisi_hba->dev;
2955 const struct hisi_sas_hw_error *ecc_error;
2956 u32 val;
2957 int i;
2958
2959 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2960 ecc_error = &multi_bit_ecc_errors[i];
2961 if (irq_value & ecc_error->irq_msk) {
2962 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2963 val &= ecc_error->msk;
2964 val >>= ecc_error->shift;
2965 dev_err(dev, ecc_error->msg, irq_value, val);
2966 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2967 }
2968 }
2969
2970 return;
2971 }
2972
2973 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
2974 {
2975 struct hisi_hba *hisi_hba = p;
2976 u32 irq_value, irq_msk;
2977
2978 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2979 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
2980
2981 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2982 if (irq_value) {
2983 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2984 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2985 }
2986
2987 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2988 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2989
2990 return IRQ_HANDLED;
2991 }
2992
2993 static const struct hisi_sas_hw_error axi_error[] = {
2994 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
2995 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
2996 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
2997 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
2998 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
2999 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
3000 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
3001 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
3002 {},
3003 };
3004
3005 static const struct hisi_sas_hw_error fifo_error[] = {
3006 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
3007 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
3008 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
3009 { .msk = BIT(11), .msg = "CMDP_FIFO" },
3010 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
3011 {},
3012 };
3013
3014 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
3015 {
3016 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
3017 .msg = "write pointer and depth",
3018 },
3019 {
3020 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
3021 .msg = "iptt no match slot",
3022 },
3023 {
3024 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
3025 .msg = "read pointer and depth",
3026 },
3027 {
3028 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
3029 .reg = HGC_AXI_FIFO_ERR_INFO,
3030 .sub = axi_error,
3031 },
3032 {
3033 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
3034 .reg = HGC_AXI_FIFO_ERR_INFO,
3035 .sub = fifo_error,
3036 },
3037 {
3038 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
3039 .msg = "LM add/fetch list",
3040 },
3041 {
3042 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
3043 .msg = "SAS_HGC_ABT fetch LM list",
3044 },
3045 };
3046
3047 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
3048 {
3049 struct hisi_hba *hisi_hba = p;
3050 u32 irq_value, irq_msk, err_value;
3051 struct device *dev = hisi_hba->dev;
3052 const struct hisi_sas_hw_error *axi_error;
3053 int i;
3054
3055 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3056 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3057
3058 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3059
3060 for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3061 axi_error = &fatal_axi_errors[i];
3062 if (!(irq_value & axi_error->irq_msk))
3063 continue;
3064
3065 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3066 1 << axi_error->shift);
3067 if (axi_error->sub) {
3068 const struct hisi_sas_hw_error *sub = axi_error->sub;
3069
3070 err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3071 for (; sub->msk || sub->msg; sub++) {
3072 if (!(err_value & sub->msk))
3073 continue;
3074 dev_err(dev, "%s (0x%x) found!\n",
3075 sub->msg, irq_value);
3076 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3077 }
3078 } else {
3079 dev_err(dev, "%s (0x%x) found!\n",
3080 axi_error->msg, irq_value);
3081 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3082 }
3083 }
3084
3085 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3086 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3087 u32 dev_id = reg_val & ITCT_DEV_MSK;
3088 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3089
3090 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3091 dev_dbg(dev, "clear ITCT ok\n");
3092 complete(sas_dev->completion);
3093 }
3094
3095 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3096 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3097
3098 return IRQ_HANDLED;
3099 }
3100
3101 static void cq_tasklet_v2_hw(unsigned long val)
3102 {
3103 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3104 struct hisi_hba *hisi_hba = cq->hisi_hba;
3105 struct hisi_sas_slot *slot;
3106 struct hisi_sas_itct *itct;
3107 struct hisi_sas_complete_v2_hdr *complete_queue;
3108 u32 rd_point = cq->rd_point, wr_point, dev_id;
3109 int queue = cq->id;
3110 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
3111
3112 if (unlikely(hisi_hba->reject_stp_links_msk))
3113 phys_try_accept_stp_links_v2_hw(hisi_hba);
3114
3115 complete_queue = hisi_hba->complete_hdr[queue];
3116
3117 spin_lock(&dq->lock);
3118 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3119 (0x14 * queue));
3120
3121 while (rd_point != wr_point) {
3122 struct hisi_sas_complete_v2_hdr *complete_hdr;
3123 int iptt;
3124
3125 complete_hdr = &complete_queue[rd_point];
3126
3127 /* Check for NCQ completion */
3128 if (complete_hdr->act) {
3129 u32 act_tmp = complete_hdr->act;
3130 int ncq_tag_count = ffs(act_tmp);
3131
3132 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3133 CMPLT_HDR_DEV_ID_OFF;
3134 itct = &hisi_hba->itct[dev_id];
3135
3136 /* The NCQ tags are held in the itct header */
3137 while (ncq_tag_count) {
3138 __le64 *ncq_tag = &itct->qw4_15[0];
3139
3140 ncq_tag_count -= 1;
3141 iptt = (ncq_tag[ncq_tag_count / 5]
3142 >> (ncq_tag_count % 5) * 12) & 0xfff;
3143
3144 slot = &hisi_hba->slot_info[iptt];
3145 slot->cmplt_queue_slot = rd_point;
3146 slot->cmplt_queue = queue;
3147 slot_complete_v2_hw(hisi_hba, slot);
3148
3149 act_tmp &= ~(1 << ncq_tag_count);
3150 ncq_tag_count = ffs(act_tmp);
3151 }
3152 } else {
3153 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3154 slot = &hisi_hba->slot_info[iptt];
3155 slot->cmplt_queue_slot = rd_point;
3156 slot->cmplt_queue = queue;
3157 slot_complete_v2_hw(hisi_hba, slot);
3158 }
3159
3160 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3161 rd_point = 0;
3162 }
3163
3164 /* update rd_point */
3165 cq->rd_point = rd_point;
3166 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3167 spin_unlock(&dq->lock);
3168 }
3169
3170 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3171 {
3172 struct hisi_sas_cq *cq = p;
3173 struct hisi_hba *hisi_hba = cq->hisi_hba;
3174 int queue = cq->id;
3175
3176 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3177
3178 tasklet_schedule(&cq->tasklet);
3179
3180 return IRQ_HANDLED;
3181 }
3182
3183 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3184 {
3185 struct hisi_sas_phy *phy = p;
3186 struct hisi_hba *hisi_hba = phy->hisi_hba;
3187 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3188 struct device *dev = hisi_hba->dev;
3189 struct hisi_sas_initial_fis *initial_fis;
3190 struct dev_to_host_fis *fis;
3191 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3192 irqreturn_t res = IRQ_HANDLED;
3193 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3194 int phy_no, offset;
3195
3196 phy_no = sas_phy->id;
3197 initial_fis = &hisi_hba->initial_fis[phy_no];
3198 fis = &initial_fis->fis;
3199
3200 offset = 4 * (phy_no / 4);
3201 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3202 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3203 ent_msk | 1 << ((phy_no % 4) * 8));
3204
3205 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3206 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3207 (phy_no % 4)));
3208 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3209 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3210 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3211 res = IRQ_NONE;
3212 goto end;
3213 }
3214
3215 /* check ERR bit of Status Register */
3216 if (fis->status & ATA_ERR) {
3217 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3218 fis->status);
3219 disable_phy_v2_hw(hisi_hba, phy_no);
3220 enable_phy_v2_hw(hisi_hba, phy_no);
3221 res = IRQ_NONE;
3222 goto end;
3223 }
3224
3225 if (unlikely(phy_no == 8)) {
3226 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3227
3228 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3229 PORT_STATE_PHY8_PORT_NUM_OFF;
3230 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3231 PORT_STATE_PHY8_CONN_RATE_OFF;
3232 } else {
3233 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3234 port_id = (port_id >> (4 * phy_no)) & 0xf;
3235 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3236 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3237 }
3238
3239 if (port_id == 0xf) {
3240 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3241 res = IRQ_NONE;
3242 goto end;
3243 }
3244
3245 sas_phy->linkrate = link_rate;
3246 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3247 HARD_PHY_LINKRATE);
3248 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3249 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3250
3251 sas_phy->oob_mode = SATA_OOB_MODE;
3252 /* Make up some unique SAS address */
3253 attached_sas_addr[0] = 0x50;
3254 attached_sas_addr[7] = phy_no;
3255 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3256 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3257 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3258 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3259 phy->port_id = port_id;
3260 phy->phy_type |= PORT_TYPE_SATA;
3261 phy->phy_attached = 1;
3262 phy->identify.device_type = SAS_SATA_DEV;
3263 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3264 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3265 queue_work(hisi_hba->wq, &phy->phyup_ws);
3266
3267 end:
3268 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3269 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3270
3271 return res;
3272 }
3273
3274 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3275 int_phy_updown_v2_hw,
3276 int_chnl_int_v2_hw,
3277 };
3278
3279 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3280 fatal_ecc_int_v2_hw,
3281 fatal_axi_int_v2_hw
3282 };
3283
3284 /**
3285 * There is a limitation in the hip06 chipset that we need
3286 * to map in all mbigen interrupts, even if they are not used.
3287 */
3288 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3289 {
3290 struct platform_device *pdev = hisi_hba->platform_dev;
3291 struct device *dev = &pdev->dev;
3292 int irq, rc, irq_map[128];
3293 int i, phy_no, fatal_no, queue_no, k;
3294
3295 for (i = 0; i < 128; i++)
3296 irq_map[i] = platform_get_irq(pdev, i);
3297
3298 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3299 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3300 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3301 DRV_NAME " phy", hisi_hba);
3302 if (rc) {
3303 dev_err(dev, "irq init: could not request "
3304 "phy interrupt %d, rc=%d\n",
3305 irq, rc);
3306 rc = -ENOENT;
3307 goto free_phy_int_irqs;
3308 }
3309 }
3310
3311 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3312 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3313
3314 irq = irq_map[phy_no + 72];
3315 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3316 DRV_NAME " sata", phy);
3317 if (rc) {
3318 dev_err(dev, "irq init: could not request "
3319 "sata interrupt %d, rc=%d\n",
3320 irq, rc);
3321 rc = -ENOENT;
3322 goto free_sata_int_irqs;
3323 }
3324 }
3325
3326 for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3327 irq = irq_map[fatal_no + 81];
3328 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3329 DRV_NAME " fatal", hisi_hba);
3330 if (rc) {
3331 dev_err(dev,
3332 "irq init: could not request fatal interrupt %d, rc=%d\n",
3333 irq, rc);
3334 rc = -ENOENT;
3335 goto free_fatal_int_irqs;
3336 }
3337 }
3338
3339 for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3340 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3341 struct tasklet_struct *t = &cq->tasklet;
3342
3343 irq = irq_map[queue_no + 96];
3344 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3345 DRV_NAME " cq", cq);
3346 if (rc) {
3347 dev_err(dev,
3348 "irq init: could not request cq interrupt %d, rc=%d\n",
3349 irq, rc);
3350 rc = -ENOENT;
3351 goto free_cq_int_irqs;
3352 }
3353 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3354 }
3355
3356 return 0;
3357
3358 free_cq_int_irqs:
3359 for (k = 0; k < queue_no; k++) {
3360 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3361
3362 free_irq(irq_map[k + 96], cq);
3363 tasklet_kill(&cq->tasklet);
3364 }
3365 free_fatal_int_irqs:
3366 for (k = 0; k < fatal_no; k++)
3367 free_irq(irq_map[k + 81], hisi_hba);
3368 free_sata_int_irqs:
3369 for (k = 0; k < phy_no; k++) {
3370 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3371
3372 free_irq(irq_map[k + 72], phy);
3373 }
3374 free_phy_int_irqs:
3375 for (k = 0; k < i; k++)
3376 free_irq(irq_map[k + 1], hisi_hba);
3377 return rc;
3378 }
3379
3380 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3381 {
3382 int rc;
3383
3384 memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3385
3386 rc = hw_init_v2_hw(hisi_hba);
3387 if (rc)
3388 return rc;
3389
3390 rc = interrupt_init_v2_hw(hisi_hba);
3391 if (rc)
3392 return rc;
3393
3394 return 0;
3395 }
3396
3397 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3398 {
3399 struct platform_device *pdev = hisi_hba->platform_dev;
3400 int i;
3401
3402 for (i = 0; i < hisi_hba->queue_count; i++)
3403 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3404
3405 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3406 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3407 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3408 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3409
3410 for (i = 0; i < hisi_hba->n_phy; i++) {
3411 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3412 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3413 }
3414
3415 for (i = 0; i < 128; i++)
3416 synchronize_irq(platform_get_irq(pdev, i));
3417 }
3418
3419
3420 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3421 {
3422 return hisi_sas_read32(hisi_hba, PHY_STATE);
3423 }
3424
3425 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3426 {
3427 struct device *dev = hisi_hba->dev;
3428 int rc, cnt;
3429
3430 interrupt_disable_v2_hw(hisi_hba);
3431 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3432 hisi_sas_kill_tasklets(hisi_hba);
3433
3434 hisi_sas_stop_phys(hisi_hba);
3435
3436 mdelay(10);
3437
3438 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3439
3440 /* wait until bus idle */
3441 cnt = 0;
3442 while (1) {
3443 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3444 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3445
3446 if (status == 0x3)
3447 break;
3448
3449 udelay(10);
3450 if (cnt++ > 10) {
3451 dev_err(dev, "wait axi bus state to idle timeout!\n");
3452 return -1;
3453 }
3454 }
3455
3456 hisi_sas_init_mem(hisi_hba);
3457
3458 rc = hw_init_v2_hw(hisi_hba);
3459 if (rc)
3460 return rc;
3461
3462 phys_reject_stp_links_v2_hw(hisi_hba);
3463
3464 return 0;
3465 }
3466
3467 static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
3468 u8 reg_index, u8 reg_count, u8 *write_data)
3469 {
3470 struct device *dev = hisi_hba->dev;
3471 int phy_no, count;
3472
3473 if (!hisi_hba->sgpio_regs)
3474 return -EOPNOTSUPP;
3475
3476 switch (reg_type) {
3477 case SAS_GPIO_REG_TX:
3478 count = reg_count * 4;
3479 count = min(count, hisi_hba->n_phy);
3480
3481 for (phy_no = 0; phy_no < count; phy_no++) {
3482 /*
3483 * GPIO_TX[n] register has the highest numbered drive
3484 * of the four in the first byte and the lowest
3485 * numbered drive in the fourth byte.
3486 * See SFF-8485 Rev. 0.7 Table 24.
3487 */
3488 void __iomem *reg_addr = hisi_hba->sgpio_regs +
3489 reg_index * 4 + phy_no;
3490 int data_idx = phy_no + 3 - (phy_no % 4) * 2;
3491
3492 writeb(write_data[data_idx], reg_addr);
3493 }
3494
3495 break;
3496 default:
3497 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3498 reg_type);
3499 return -EINVAL;
3500 }
3501
3502 return 0;
3503 }
3504
3505 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3506 .hw_init = hisi_sas_v2_init,
3507 .setup_itct = setup_itct_v2_hw,
3508 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3509 .alloc_dev = alloc_dev_quirk_v2_hw,
3510 .sl_notify = sl_notify_v2_hw,
3511 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3512 .clear_itct = clear_itct_v2_hw,
3513 .free_device = free_device_v2_hw,
3514 .prep_smp = prep_smp_v2_hw,
3515 .prep_ssp = prep_ssp_v2_hw,
3516 .prep_stp = prep_ata_v2_hw,
3517 .prep_abort = prep_abort_v2_hw,
3518 .get_free_slot = get_free_slot_v2_hw,
3519 .start_delivery = start_delivery_v2_hw,
3520 .slot_complete = slot_complete_v2_hw,
3521 .phys_init = phys_init_v2_hw,
3522 .phy_start = start_phy_v2_hw,
3523 .phy_disable = disable_phy_v2_hw,
3524 .phy_hard_reset = phy_hard_reset_v2_hw,
3525 .get_events = phy_get_events_v2_hw,
3526 .phy_set_linkrate = phy_set_linkrate_v2_hw,
3527 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3528 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3529 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3530 .soft_reset = soft_reset_v2_hw,
3531 .get_phys_state = get_phys_state_v2_hw,
3532 .write_gpio = write_gpio_v2_hw,
3533 };
3534
3535 static int hisi_sas_v2_probe(struct platform_device *pdev)
3536 {
3537 /*
3538 * Check if we should defer the probe before we probe the
3539 * upper layer, as it's hard to defer later on.
3540 */
3541 int ret = platform_get_irq(pdev, 0);
3542
3543 if (ret < 0) {
3544 if (ret != -EPROBE_DEFER)
3545 dev_err(&pdev->dev, "cannot obtain irq\n");
3546 return ret;
3547 }
3548
3549 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3550 }
3551
3552 static int hisi_sas_v2_remove(struct platform_device *pdev)
3553 {
3554 struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3555 struct hisi_hba *hisi_hba = sha->lldd_ha;
3556
3557 if (timer_pending(&hisi_hba->timer))
3558 del_timer(&hisi_hba->timer);
3559
3560 hisi_sas_kill_tasklets(hisi_hba);
3561
3562 return hisi_sas_remove(pdev);
3563 }
3564
3565 static const struct of_device_id sas_v2_of_match[] = {
3566 { .compatible = "hisilicon,hip06-sas-v2",},
3567 { .compatible = "hisilicon,hip07-sas-v2",},
3568 {},
3569 };
3570 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3571
3572 static const struct acpi_device_id sas_v2_acpi_match[] = {
3573 { "HISI0162", 0 },
3574 { }
3575 };
3576
3577 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3578
3579 static struct platform_driver hisi_sas_v2_driver = {
3580 .probe = hisi_sas_v2_probe,
3581 .remove = hisi_sas_v2_remove,
3582 .driver = {
3583 .name = DRV_NAME,
3584 .of_match_table = sas_v2_of_match,
3585 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3586 },
3587 };
3588
3589 module_platform_driver(hisi_sas_v2_driver);
3590
3591 MODULE_LICENSE("GPL");
3592 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3593 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3594 MODULE_ALIAS("platform:" DRV_NAME);
ubuntu-bionic-kernel mirror