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scsi: hisi_sas: Create a scsi_host_template per HW module
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
1 /*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12 #include "hisi_sas.h"
13 #define DRV_NAME "hisi_sas_v2_hw"
14
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
34 #define ITCT_CLR 0x44
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
148 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
149 #define DLVRY_Q_0_DEPTH 0x268
150 #define DLVRY_Q_0_WR_PTR 0x26c
151 #define DLVRY_Q_0_RD_PTR 0x270
152 #define HYPER_STREAM_ID_EN_CFG 0xc80
153 #define OQ0_INT_SRC_MSK 0xc90
154 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
155 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
156 #define COMPL_Q_0_DEPTH 0x4e8
157 #define COMPL_Q_0_WR_PTR 0x4ec
158 #define COMPL_Q_0_RD_PTR 0x4f0
159 #define HGC_RXM_DFX_STATUS14 0xae8
160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
162 HGC_RXM_DFX_STATUS14_MEM0_OFF)
163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM1_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM2_OFF)
169 #define HGC_RXM_DFX_STATUS15 0xaec
170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
172 HGC_RXM_DFX_STATUS15_MEM3_OFF)
173 /* phy registers need init */
174 #define PORT_BASE (0x2000)
175
176 #define PHY_CFG (PORT_BASE + 0x0)
177 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PHY_CFG_ENA_OFF 0
179 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
180 #define PHY_CFG_DC_OPT_OFF 2
181 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
182 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
183 #define PROG_PHY_LINK_RATE_MAX_OFF 0
184 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
185 #define PHY_CTRL (PORT_BASE + 0x14)
186 #define PHY_CTRL_RESET_OFF 0
187 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
188 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
189 #define SL_CFG (PORT_BASE + 0x84)
190 #define PHY_PCN (PORT_BASE + 0x44)
191 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
192 #define SL_CONTROL (PORT_BASE + 0x94)
193 #define SL_CONTROL_NOTIFY_EN_OFF 0
194 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
195 #define SL_CONTROL_CTA_OFF 17
196 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
197 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
198 #define RX_BCAST_CHG_OFF 1
199 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
200 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
201 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
202 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
203 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
204 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
205 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
206 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
207 #define TXID_AUTO (PORT_BASE + 0xb8)
208 #define TXID_AUTO_CT3_OFF 1
209 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
210 #define TXID_AUTO_CTB_OFF 11
211 #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
212 #define TX_HARDRST_OFF 2
213 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
214 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
215 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
216 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
217 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
218 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
219 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
220 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
221 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
222 #define CON_CONTROL (PORT_BASE + 0x118)
223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
225 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
226 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
227 #define CHL_INT0 (PORT_BASE + 0x1b4)
228 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
229 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
230 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
231 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
232 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
233 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
234 #define CHL_INT0_NOT_RDY_OFF 4
235 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
236 #define CHL_INT0_PHY_RDY_OFF 5
237 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
238 #define CHL_INT1 (PORT_BASE + 0x1b8)
239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
243 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
244 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
245 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
246 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
247 #define CHL_INT2 (PORT_BASE + 0x1bc)
248 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
249 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
250 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
251 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
252 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
253 #define DMA_TX_DFX0 (PORT_BASE + 0x200)
254 #define DMA_TX_DFX1 (PORT_BASE + 0x204)
255 #define DMA_TX_DFX1_IPTT_OFF 0
256 #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
257 #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
258 #define PORT_DFX0 (PORT_BASE + 0x258)
259 #define LINK_DFX2 (PORT_BASE + 0X264)
260 #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
261 #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
262 #define LINK_DFX2_SEND_HOLD_STS_OFF 10
263 #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
264 #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
265 #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
266 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
267 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
268 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
269 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
270 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
271 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
272 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
273 #define DMA_TX_STATUS_BUSY_OFF 0
274 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
275 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
276 #define DMA_RX_STATUS_BUSY_OFF 0
277 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
278
279 #define AXI_CFG (0x5100)
280 #define AM_CFG_MAX_TRANS (0x5010)
281 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
282
283 #define AXI_MASTER_CFG_BASE (0x5000)
284 #define AM_CTRL_GLOBAL (0x0)
285 #define AM_CURR_TRANS_RETURN (0x150)
286
287 /* HW dma structures */
288 /* Delivery queue header */
289 /* dw0 */
290 #define CMD_HDR_ABORT_FLAG_OFF 0
291 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
292 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
293 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
294 #define CMD_HDR_RESP_REPORT_OFF 5
295 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
296 #define CMD_HDR_TLR_CTRL_OFF 6
297 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
298 #define CMD_HDR_PORT_OFF 18
299 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
300 #define CMD_HDR_PRIORITY_OFF 27
301 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
302 #define CMD_HDR_CMD_OFF 29
303 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
304 /* dw1 */
305 #define CMD_HDR_DIR_OFF 5
306 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
307 #define CMD_HDR_RESET_OFF 7
308 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
309 #define CMD_HDR_VDTL_OFF 10
310 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
311 #define CMD_HDR_FRAME_TYPE_OFF 11
312 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
313 #define CMD_HDR_DEV_ID_OFF 16
314 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
315 /* dw2 */
316 #define CMD_HDR_CFL_OFF 0
317 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
318 #define CMD_HDR_NCQ_TAG_OFF 10
319 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
320 #define CMD_HDR_MRFL_OFF 15
321 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
322 #define CMD_HDR_SG_MOD_OFF 24
323 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
324 #define CMD_HDR_FIRST_BURST_OFF 26
325 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
326 /* dw3 */
327 #define CMD_HDR_IPTT_OFF 0
328 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
329 /* dw6 */
330 #define CMD_HDR_DIF_SGL_LEN_OFF 0
331 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
332 #define CMD_HDR_DATA_SGL_LEN_OFF 16
333 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
334 #define CMD_HDR_ABORT_IPTT_OFF 16
335 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
336
337 /* Completion header */
338 /* dw0 */
339 #define CMPLT_HDR_ERR_PHASE_OFF 2
340 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
341 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
342 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
343 #define CMPLT_HDR_ERX_OFF 12
344 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
345 #define CMPLT_HDR_ABORT_STAT_OFF 13
346 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
347 /* abort_stat */
348 #define STAT_IO_NOT_VALID 0x1
349 #define STAT_IO_NO_DEVICE 0x2
350 #define STAT_IO_COMPLETE 0x3
351 #define STAT_IO_ABORTED 0x4
352 /* dw1 */
353 #define CMPLT_HDR_IPTT_OFF 0
354 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
355 #define CMPLT_HDR_DEV_ID_OFF 16
356 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
357
358 /* ITCT header */
359 /* qw0 */
360 #define ITCT_HDR_DEV_TYPE_OFF 0
361 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
362 #define ITCT_HDR_VALID_OFF 2
363 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
364 #define ITCT_HDR_MCR_OFF 5
365 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
366 #define ITCT_HDR_VLN_OFF 9
367 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
368 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
369 #define ITCT_HDR_SMP_TIMEOUT_8US 1
370 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
371 250) /* 2ms */
372 #define ITCT_HDR_AWT_CONTINUE_OFF 25
373 #define ITCT_HDR_PORT_ID_OFF 28
374 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
375 /* qw2 */
376 #define ITCT_HDR_INLT_OFF 0
377 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
378 #define ITCT_HDR_BITLT_OFF 16
379 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
380 #define ITCT_HDR_MCTLT_OFF 32
381 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
382 #define ITCT_HDR_RTOLT_OFF 48
383 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
384
385 #define HISI_SAS_FATAL_INT_NR 2
386
387 struct hisi_sas_complete_v2_hdr {
388 __le32 dw0;
389 __le32 dw1;
390 __le32 act;
391 __le32 dw3;
392 };
393
394 struct hisi_sas_err_record_v2 {
395 /* dw0 */
396 __le32 trans_tx_fail_type;
397
398 /* dw1 */
399 __le32 trans_rx_fail_type;
400
401 /* dw2 */
402 __le16 dma_tx_err_type;
403 __le16 sipc_rx_err_type;
404
405 /* dw3 */
406 __le32 dma_rx_err_type;
407 };
408
409 struct signal_attenuation_s {
410 u32 de_emphasis;
411 u32 preshoot;
412 u32 boost;
413 };
414
415 struct sig_atten_lu_s {
416 const struct signal_attenuation_s *att;
417 u32 sas_phy_ctrl;
418 };
419
420 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
421 {
422 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
423 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
424 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
425 .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
426 .reg = HGC_DQE_ECC_ADDR,
427 },
428 {
429 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
430 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
431 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
432 .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
433 .reg = HGC_IOST_ECC_ADDR,
434 },
435 {
436 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
437 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
438 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
439 .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
440 .reg = HGC_ITCT_ECC_ADDR,
441 },
442 {
443 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
444 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
445 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
446 .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
447 .reg = HGC_LM_DFX_STATUS2,
448 },
449 {
450 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
451 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
452 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
453 .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
454 .reg = HGC_LM_DFX_STATUS2,
455 },
456 {
457 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
458 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
459 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
460 .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
461 .reg = HGC_CQE_ECC_ADDR,
462 },
463 {
464 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
465 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
466 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
467 .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
468 .reg = HGC_RXM_DFX_STATUS14,
469 },
470 {
471 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
472 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
473 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
474 .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
475 .reg = HGC_RXM_DFX_STATUS14,
476 },
477 {
478 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
479 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
480 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
481 .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
482 .reg = HGC_RXM_DFX_STATUS14,
483 },
484 {
485 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
486 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
487 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
488 .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
489 .reg = HGC_RXM_DFX_STATUS15,
490 },
491 };
492
493 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
494 {
495 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
496 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
497 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
498 .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
499 .reg = HGC_DQE_ECC_ADDR,
500 },
501 {
502 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
503 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
504 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
505 .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
506 .reg = HGC_IOST_ECC_ADDR,
507 },
508 {
509 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
510 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
511 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
512 .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
513 .reg = HGC_ITCT_ECC_ADDR,
514 },
515 {
516 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
517 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
518 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
519 .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
520 .reg = HGC_LM_DFX_STATUS2,
521 },
522 {
523 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
524 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
525 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
526 .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
527 .reg = HGC_LM_DFX_STATUS2,
528 },
529 {
530 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
531 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
532 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
533 .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
534 .reg = HGC_CQE_ECC_ADDR,
535 },
536 {
537 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
538 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
539 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
540 .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
541 .reg = HGC_RXM_DFX_STATUS14,
542 },
543 {
544 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
545 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
546 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
547 .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
548 .reg = HGC_RXM_DFX_STATUS14,
549 },
550 {
551 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
552 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
553 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
554 .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
555 .reg = HGC_RXM_DFX_STATUS14,
556 },
557 {
558 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
559 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
560 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
561 .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
562 .reg = HGC_RXM_DFX_STATUS15,
563 },
564 };
565
566 enum {
567 HISI_SAS_PHY_PHY_UPDOWN,
568 HISI_SAS_PHY_CHNL_INT,
569 HISI_SAS_PHY_INT_NR
570 };
571
572 enum {
573 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
574 TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
575 DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
576 SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
577 DMA_RX_ERR_BASE = 0x60, /* dw3 */
578
579 /* trans tx*/
580 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
581 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
582 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
583 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
584 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
585 RESERVED0, /* 0x5 */
586 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
587 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
588 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
589 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
590 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
591 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
592 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
593 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
594 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
595 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
596 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
597 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
598 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
599 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
600 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
601 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
602 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
603 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
604 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
605 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
606 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
607 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
608 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
609 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
610 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
611 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
612 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
613 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
614 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
615
616 /* trans rx */
617 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
618 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
619 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
620 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
621 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
622 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
623 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
624 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
625 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
626 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
627 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
628 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
629 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
630 RESERVED1, /* 0x2b */
631 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
632 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
633 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
634 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
635 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
636 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
637 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
638 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
639 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
640 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
641 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
642 RESERVED2, /* 0x34 */
643 RESERVED3, /* 0x35 */
644 RESERVED4, /* 0x36 */
645 RESERVED5, /* 0x37 */
646 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
647 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
648 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
649 RESERVED6, /* 0x3b */
650 RESERVED7, /* 0x3c */
651 RESERVED8, /* 0x3d */
652 RESERVED9, /* 0x3e */
653 TRANS_RX_R_ERR, /* 0x3f */
654
655 /* dma tx */
656 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
657 DMA_TX_DIF_APP_ERR, /* 0x41 */
658 DMA_TX_DIF_RPP_ERR, /* 0x42 */
659 DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
660 DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
661 DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
662 DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
663 DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
664 DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
665 DMA_TX_RAM_ECC_ERR, /* 0x49 */
666 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
667 DMA_TX_MAX_ERR_CODE,
668
669 /* sipc rx */
670 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
671 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
672 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
673 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
674 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
675 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
676 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
677 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
678 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
679 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
680 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
681 SIPC_RX_MAX_ERR_CODE,
682
683 /* dma rx */
684 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
685 DMA_RX_DIF_APP_ERR, /* 0x61 */
686 DMA_RX_DIF_RPP_ERR, /* 0x62 */
687 DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
688 DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
689 DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
690 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
691 DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
692 RESERVED10, /* 0x68 */
693 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
694 DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
695 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
696 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
697 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
698 DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
699 DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
700 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
701 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
702 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
703 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
704 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
705 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
706 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
707 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
708 DMA_RX_RAM_ECC_ERR, /* 0x78 */
709 DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
710 DMA_RX_MAX_ERR_CODE,
711 };
712
713 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
714 #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
715
716 #define DIR_NO_DATA 0
717 #define DIR_TO_INI 1
718 #define DIR_TO_DEVICE 2
719 #define DIR_RESERVED 3
720
721 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
722 err_phase == 0x4 || err_phase == 0x8 ||\
723 err_phase == 0x6 || err_phase == 0xa)
724 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
725 err_phase == 0x20 || err_phase == 0x40)
726
727 static void link_timeout_disable_link(struct timer_list *t);
728
729 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
730 {
731 void __iomem *regs = hisi_hba->regs + off;
732
733 return readl(regs);
734 }
735
736 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
737 {
738 void __iomem *regs = hisi_hba->regs + off;
739
740 return readl_relaxed(regs);
741 }
742
743 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
744 {
745 void __iomem *regs = hisi_hba->regs + off;
746
747 writel(val, regs);
748 }
749
750 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
751 u32 off, u32 val)
752 {
753 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
754
755 writel(val, regs);
756 }
757
758 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
759 int phy_no, u32 off)
760 {
761 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
762
763 return readl(regs);
764 }
765
766 /* This function needs to be protected from pre-emption. */
767 static int
768 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
769 struct domain_device *device)
770 {
771 int sata_dev = dev_is_sata(device);
772 void *bitmap = hisi_hba->slot_index_tags;
773 struct hisi_sas_device *sas_dev = device->lldd_dev;
774 int sata_idx = sas_dev->sata_idx;
775 int start, end;
776
777 if (!sata_dev) {
778 /*
779 * STP link SoC bug workaround: index starts from 1.
780 * additionally, we can only allocate odd IPTT(1~4095)
781 * for SAS/SMP device.
782 */
783 start = 1;
784 end = hisi_hba->slot_index_count;
785 } else {
786 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
787 return -EINVAL;
788
789 /*
790 * For SATA device: allocate even IPTT in this interval
791 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
792 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
793 * SoC bug workaround. So we ignore the first 32 even IPTTs.
794 */
795 start = 64 * (sata_idx + 1);
796 end = 64 * (sata_idx + 2);
797 }
798
799 while (1) {
800 start = find_next_zero_bit(bitmap,
801 hisi_hba->slot_index_count, start);
802 if (start >= end)
803 return -SAS_QUEUE_FULL;
804 /*
805 * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
806 */
807 if (sata_dev ^ (start & 1))
808 break;
809 start++;
810 }
811
812 set_bit(start, bitmap);
813 *slot_idx = start;
814 return 0;
815 }
816
817 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
818 {
819 unsigned int index;
820 struct device *dev = hisi_hba->dev;
821 void *bitmap = hisi_hba->sata_dev_bitmap;
822
823 index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
824 if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
825 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
826 return false;
827 }
828
829 set_bit(index, bitmap);
830 *idx = index;
831 return true;
832 }
833
834
835 static struct
836 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
837 {
838 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
839 struct hisi_sas_device *sas_dev = NULL;
840 int i, sata_dev = dev_is_sata(device);
841 int sata_idx = -1;
842 unsigned long flags;
843
844 spin_lock_irqsave(&hisi_hba->lock, flags);
845
846 if (sata_dev)
847 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
848 goto out;
849
850 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
851 /*
852 * SATA device id bit0 should be 0
853 */
854 if (sata_dev && (i & 1))
855 continue;
856 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
857 int queue = i % hisi_hba->queue_count;
858 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
859
860 hisi_hba->devices[i].device_id = i;
861 sas_dev = &hisi_hba->devices[i];
862 sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
863 sas_dev->dev_type = device->dev_type;
864 sas_dev->hisi_hba = hisi_hba;
865 sas_dev->sas_device = device;
866 sas_dev->sata_idx = sata_idx;
867 sas_dev->dq = dq;
868 INIT_LIST_HEAD(&hisi_hba->devices[i].list);
869 break;
870 }
871 }
872
873 out:
874 spin_unlock_irqrestore(&hisi_hba->lock, flags);
875
876 return sas_dev;
877 }
878
879 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
880 {
881 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
882
883 cfg &= ~PHY_CFG_DC_OPT_MSK;
884 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
885 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
886 }
887
888 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
889 {
890 struct sas_identify_frame identify_frame;
891 u32 *identify_buffer;
892
893 memset(&identify_frame, 0, sizeof(identify_frame));
894 identify_frame.dev_type = SAS_END_DEVICE;
895 identify_frame.frame_type = 0;
896 identify_frame._un1 = 1;
897 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
898 identify_frame.target_bits = SAS_PROTOCOL_NONE;
899 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
900 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
901 identify_frame.phy_id = phy_no;
902 identify_buffer = (u32 *)(&identify_frame);
903
904 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
905 __swab32(identify_buffer[0]));
906 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
907 __swab32(identify_buffer[1]));
908 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
909 __swab32(identify_buffer[2]));
910 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
911 __swab32(identify_buffer[3]));
912 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
913 __swab32(identify_buffer[4]));
914 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
915 __swab32(identify_buffer[5]));
916 }
917
918 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
919 struct hisi_sas_device *sas_dev)
920 {
921 struct domain_device *device = sas_dev->sas_device;
922 struct device *dev = hisi_hba->dev;
923 u64 qw0, device_id = sas_dev->device_id;
924 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
925 struct domain_device *parent_dev = device->parent;
926 struct asd_sas_port *sas_port = device->port;
927 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
928
929 memset(itct, 0, sizeof(*itct));
930
931 /* qw0 */
932 qw0 = 0;
933 switch (sas_dev->dev_type) {
934 case SAS_END_DEVICE:
935 case SAS_EDGE_EXPANDER_DEVICE:
936 case SAS_FANOUT_EXPANDER_DEVICE:
937 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
938 break;
939 case SAS_SATA_DEV:
940 case SAS_SATA_PENDING:
941 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
942 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
943 else
944 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
945 break;
946 default:
947 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
948 sas_dev->dev_type);
949 }
950
951 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
952 (device->linkrate << ITCT_HDR_MCR_OFF) |
953 (1 << ITCT_HDR_VLN_OFF) |
954 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
955 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
956 (port->id << ITCT_HDR_PORT_ID_OFF));
957 itct->qw0 = cpu_to_le64(qw0);
958
959 /* qw1 */
960 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
961 itct->sas_addr = __swab64(itct->sas_addr);
962
963 /* qw2 */
964 if (!dev_is_sata(device))
965 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
966 (0x1ULL << ITCT_HDR_BITLT_OFF) |
967 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
968 (0x1ULL << ITCT_HDR_RTOLT_OFF));
969 }
970
971 static void clear_itct_v2_hw(struct hisi_hba *hisi_hba,
972 struct hisi_sas_device *sas_dev)
973 {
974 DECLARE_COMPLETION_ONSTACK(completion);
975 u64 dev_id = sas_dev->device_id;
976 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
977 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
978 int i;
979
980 sas_dev->completion = &completion;
981
982 /* clear the itct interrupt state */
983 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
984 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
985 ENT_INT_SRC3_ITC_INT_MSK);
986
987 for (i = 0; i < 2; i++) {
988 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
989 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
990 wait_for_completion(sas_dev->completion);
991
992 memset(itct, 0, sizeof(struct hisi_sas_itct));
993 }
994 }
995
996 static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
997 {
998 struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
999
1000 /* SoC bug workaround */
1001 if (dev_is_sata(sas_dev->sas_device))
1002 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
1003 }
1004
1005 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
1006 {
1007 int i, reset_val;
1008 u32 val;
1009 unsigned long end_time;
1010 struct device *dev = hisi_hba->dev;
1011
1012 /* The mask needs to be set depending on the number of phys */
1013 if (hisi_hba->n_phy == 9)
1014 reset_val = 0x1fffff;
1015 else
1016 reset_val = 0x7ffff;
1017
1018 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1019
1020 /* Disable all of the PHYs */
1021 for (i = 0; i < hisi_hba->n_phy; i++) {
1022 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1023
1024 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1025 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1026 }
1027 udelay(50);
1028
1029 /* Ensure DMA tx & rx idle */
1030 for (i = 0; i < hisi_hba->n_phy; i++) {
1031 u32 dma_tx_status, dma_rx_status;
1032
1033 end_time = jiffies + msecs_to_jiffies(1000);
1034
1035 while (1) {
1036 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1037 DMA_TX_STATUS);
1038 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1039 DMA_RX_STATUS);
1040
1041 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1042 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1043 break;
1044
1045 msleep(20);
1046 if (time_after(jiffies, end_time))
1047 return -EIO;
1048 }
1049 }
1050
1051 /* Ensure axi bus idle */
1052 end_time = jiffies + msecs_to_jiffies(1000);
1053 while (1) {
1054 u32 axi_status =
1055 hisi_sas_read32(hisi_hba, AXI_CFG);
1056
1057 if (axi_status == 0)
1058 break;
1059
1060 msleep(20);
1061 if (time_after(jiffies, end_time))
1062 return -EIO;
1063 }
1064
1065 if (ACPI_HANDLE(dev)) {
1066 acpi_status s;
1067
1068 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1069 if (ACPI_FAILURE(s)) {
1070 dev_err(dev, "Reset failed\n");
1071 return -EIO;
1072 }
1073 } else if (hisi_hba->ctrl) {
1074 /* reset and disable clock*/
1075 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1076 reset_val);
1077 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1078 reset_val);
1079 msleep(1);
1080 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1081 if (reset_val != (val & reset_val)) {
1082 dev_err(dev, "SAS reset fail.\n");
1083 return -EIO;
1084 }
1085
1086 /* De-reset and enable clock*/
1087 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1088 reset_val);
1089 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1090 reset_val);
1091 msleep(1);
1092 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1093 &val);
1094 if (val & reset_val) {
1095 dev_err(dev, "SAS de-reset fail.\n");
1096 return -EIO;
1097 }
1098 } else {
1099 dev_err(dev, "no reset method\n");
1100 return -EINVAL;
1101 }
1102
1103 return 0;
1104 }
1105
1106 /* This function needs to be called after resetting SAS controller. */
1107 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1108 {
1109 u32 cfg;
1110 int phy_no;
1111
1112 hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1113 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1114 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1115 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1116 continue;
1117
1118 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1119 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1120 }
1121 }
1122
1123 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1124 {
1125 int phy_no;
1126 u32 dma_tx_dfx1;
1127
1128 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1129 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1130 continue;
1131
1132 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1133 DMA_TX_DFX1);
1134 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1135 u32 cfg = hisi_sas_phy_read32(hisi_hba,
1136 phy_no, CON_CONTROL);
1137
1138 cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1139 hisi_sas_phy_write32(hisi_hba, phy_no,
1140 CON_CONTROL, cfg);
1141 clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1142 }
1143 }
1144 }
1145
1146 static const struct signal_attenuation_s x6000 = {9200, 0, 10476};
1147 static const struct sig_atten_lu_s sig_atten_lu[] = {
1148 { &x6000, 0x3016a68 },
1149 };
1150
1151 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1152 {
1153 struct device *dev = hisi_hba->dev;
1154 u32 sas_phy_ctrl = 0x30b9908;
1155 u32 signal[3];
1156 int i;
1157
1158 /* Global registers init */
1159
1160 /* Deal with am-max-transmissions quirk */
1161 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1162 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1163 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1164 0x2020);
1165 } /* Else, use defaults -> do nothing */
1166
1167 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1168 (u32)((1ULL << hisi_hba->queue_count) - 1));
1169 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1170 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1171 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1172 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1173 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1174 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1175 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1176 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1177 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1178 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1179 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1180 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1181 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1182 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1183 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1184 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1185 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1186 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1187 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1188 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1189 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1190 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1191 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1192 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1193 for (i = 0; i < hisi_hba->queue_count; i++)
1194 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1195
1196 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1197 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1198
1199 /* Get sas_phy_ctrl value to deal with TX FFE issue. */
1200 if (!device_property_read_u32_array(dev, "hisilicon,signal-attenuation",
1201 signal, ARRAY_SIZE(signal))) {
1202 for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) {
1203 const struct sig_atten_lu_s *lookup = &sig_atten_lu[i];
1204 const struct signal_attenuation_s *att = lookup->att;
1205
1206 if ((signal[0] == att->de_emphasis) &&
1207 (signal[1] == att->preshoot) &&
1208 (signal[2] == att->boost)) {
1209 sas_phy_ctrl = lookup->sas_phy_ctrl;
1210 break;
1211 }
1212 }
1213
1214 if (i == ARRAY_SIZE(sig_atten_lu))
1215 dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n");
1216 }
1217
1218 for (i = 0; i < hisi_hba->n_phy; i++) {
1219 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1220 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1221 u32 prog_phy_link_rate = 0x800;
1222
1223 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
1224 SAS_LINK_RATE_1_5_GBPS)) {
1225 prog_phy_link_rate = 0x855;
1226 } else {
1227 enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
1228
1229 prog_phy_link_rate =
1230 hisi_sas_get_prog_phy_linkrate_mask(max) |
1231 0x800;
1232 }
1233 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
1234 prog_phy_link_rate);
1235 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl);
1236 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1237 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1238 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1239 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1240 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1241 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1242 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1243 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1244 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff);
1245 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbfe);
1246 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1247 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1248 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1249 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1250 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1251 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1252 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1253 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1254 if (hisi_hba->refclk_frequency_mhz == 66)
1255 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1256 /* else, do nothing -> leave it how you found it */
1257 }
1258
1259 for (i = 0; i < hisi_hba->queue_count; i++) {
1260 /* Delivery queue */
1261 hisi_sas_write32(hisi_hba,
1262 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1263 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1264
1265 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1266 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1267
1268 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1269 HISI_SAS_QUEUE_SLOTS);
1270
1271 /* Completion queue */
1272 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1273 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1274
1275 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1276 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1277
1278 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1279 HISI_SAS_QUEUE_SLOTS);
1280 }
1281
1282 /* itct */
1283 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1284 lower_32_bits(hisi_hba->itct_dma));
1285
1286 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1287 upper_32_bits(hisi_hba->itct_dma));
1288
1289 /* iost */
1290 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1291 lower_32_bits(hisi_hba->iost_dma));
1292
1293 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1294 upper_32_bits(hisi_hba->iost_dma));
1295
1296 /* breakpoint */
1297 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1298 lower_32_bits(hisi_hba->breakpoint_dma));
1299
1300 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1301 upper_32_bits(hisi_hba->breakpoint_dma));
1302
1303 /* SATA broken msg */
1304 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1305 lower_32_bits(hisi_hba->sata_breakpoint_dma));
1306
1307 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1308 upper_32_bits(hisi_hba->sata_breakpoint_dma));
1309
1310 /* SATA initial fis */
1311 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1312 lower_32_bits(hisi_hba->initial_fis_dma));
1313
1314 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1315 upper_32_bits(hisi_hba->initial_fis_dma));
1316 }
1317
1318 static void link_timeout_enable_link(struct timer_list *t)
1319 {
1320 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1321 int i, reg_val;
1322
1323 for (i = 0; i < hisi_hba->n_phy; i++) {
1324 if (hisi_hba->reject_stp_links_msk & BIT(i))
1325 continue;
1326
1327 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1328 if (!(reg_val & BIT(0))) {
1329 hisi_sas_phy_write32(hisi_hba, i,
1330 CON_CONTROL, 0x7);
1331 break;
1332 }
1333 }
1334
1335 hisi_hba->timer.function = link_timeout_disable_link;
1336 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1337 }
1338
1339 static void link_timeout_disable_link(struct timer_list *t)
1340 {
1341 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1342 int i, reg_val;
1343
1344 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1345 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1346 if (hisi_hba->reject_stp_links_msk & BIT(i))
1347 continue;
1348
1349 if (reg_val & BIT(i)) {
1350 hisi_sas_phy_write32(hisi_hba, i,
1351 CON_CONTROL, 0x6);
1352 break;
1353 }
1354 }
1355
1356 hisi_hba->timer.function = link_timeout_enable_link;
1357 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1358 }
1359
1360 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1361 {
1362 hisi_hba->timer.function = link_timeout_disable_link;
1363 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1364 add_timer(&hisi_hba->timer);
1365 }
1366
1367 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1368 {
1369 struct device *dev = hisi_hba->dev;
1370 int rc;
1371
1372 rc = reset_hw_v2_hw(hisi_hba);
1373 if (rc) {
1374 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1375 return rc;
1376 }
1377
1378 msleep(100);
1379 init_reg_v2_hw(hisi_hba);
1380
1381 return 0;
1382 }
1383
1384 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1385 {
1386 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1387
1388 cfg |= PHY_CFG_ENA_MSK;
1389 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1390 }
1391
1392 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1393 {
1394 u32 context;
1395
1396 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1397 if (context & (1 << phy_no))
1398 return true;
1399
1400 return false;
1401 }
1402
1403 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1404 {
1405 u32 dfx_val;
1406
1407 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1408
1409 if (dfx_val & BIT(16))
1410 return false;
1411
1412 return true;
1413 }
1414
1415 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1416 {
1417 int i, max_loop = 1000;
1418 struct device *dev = hisi_hba->dev;
1419 u32 status, axi_status, dfx_val, dfx_tx_val;
1420
1421 for (i = 0; i < max_loop; i++) {
1422 status = hisi_sas_read32_relaxed(hisi_hba,
1423 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1424
1425 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1426 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1427 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1428 phy_no, DMA_TX_FIFO_DFX0);
1429
1430 if ((status == 0x3) && (axi_status == 0x0) &&
1431 (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1432 return true;
1433 udelay(10);
1434 }
1435 dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1436 phy_no, status, axi_status,
1437 dfx_val, dfx_tx_val);
1438 return false;
1439 }
1440
1441 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1442 {
1443 int i, max_loop = 1000;
1444 struct device *dev = hisi_hba->dev;
1445 u32 status, tx_dfx0;
1446
1447 for (i = 0; i < max_loop; i++) {
1448 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1449 status = (status & 0x3fc0) >> 6;
1450
1451 if (status != 0x1)
1452 return true;
1453
1454 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1455 if ((tx_dfx0 & 0x1ff) == 0x2)
1456 return true;
1457 udelay(10);
1458 }
1459 dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1460 phy_no, status, tx_dfx0);
1461 return false;
1462 }
1463
1464 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1465 {
1466 if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1467 return true;
1468
1469 if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1470 return false;
1471
1472 if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1473 return false;
1474
1475 return true;
1476 }
1477
1478
1479 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1480 {
1481 u32 cfg, axi_val, dfx0_val, txid_auto;
1482 struct device *dev = hisi_hba->dev;
1483
1484 /* Close axi bus. */
1485 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1486 AM_CTRL_GLOBAL);
1487 axi_val |= 0x1;
1488 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1489 AM_CTRL_GLOBAL, axi_val);
1490
1491 if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1492 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1493 goto do_disable;
1494
1495 /* Reset host controller. */
1496 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1497 return;
1498 }
1499
1500 dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1501 dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1502 if (dfx0_val != 0x4)
1503 goto do_disable;
1504
1505 if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1506 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1507 phy_no);
1508 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1509 TXID_AUTO);
1510 txid_auto |= TXID_AUTO_CTB_MSK;
1511 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1512 txid_auto);
1513 }
1514
1515 do_disable:
1516 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1517 cfg &= ~PHY_CFG_ENA_MSK;
1518 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1519
1520 /* Open axi bus. */
1521 axi_val &= ~0x1;
1522 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1523 AM_CTRL_GLOBAL, axi_val);
1524 }
1525
1526 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1527 {
1528 config_id_frame_v2_hw(hisi_hba, phy_no);
1529 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1530 enable_phy_v2_hw(hisi_hba, phy_no);
1531 }
1532
1533 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1534 {
1535 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1536 u32 txid_auto;
1537
1538 disable_phy_v2_hw(hisi_hba, phy_no);
1539 if (phy->identify.device_type == SAS_END_DEVICE) {
1540 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1541 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1542 txid_auto | TX_HARDRST_MSK);
1543 }
1544 msleep(100);
1545 start_phy_v2_hw(hisi_hba, phy_no);
1546 }
1547
1548 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1549 {
1550 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1551 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1552 struct sas_phy *sphy = sas_phy->phy;
1553 u32 err4_reg_val, err6_reg_val;
1554
1555 /* loss dword syn, phy reset problem */
1556 err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1557
1558 /* disparity err, invalid dword */
1559 err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1560
1561 sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1562 sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1563 sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1564 sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1565 }
1566
1567 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1568 {
1569 int i;
1570
1571 for (i = 0; i < hisi_hba->n_phy; i++) {
1572 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1573 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1574
1575 if (!sas_phy->phy->enabled)
1576 continue;
1577
1578 start_phy_v2_hw(hisi_hba, i);
1579 }
1580 }
1581
1582 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1583 {
1584 u32 sl_control;
1585
1586 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1587 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1588 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1589 msleep(1);
1590 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1591 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1592 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1593 }
1594
1595 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1596 {
1597 return SAS_LINK_RATE_12_0_GBPS;
1598 }
1599
1600 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1601 struct sas_phy_linkrates *r)
1602 {
1603 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1604 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1605 enum sas_linkrate min, max;
1606 u32 prog_phy_link_rate = 0x800;
1607
1608 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1609 max = sas_phy->phy->maximum_linkrate;
1610 min = r->minimum_linkrate;
1611 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1612 max = r->maximum_linkrate;
1613 min = sas_phy->phy->minimum_linkrate;
1614 } else
1615 return;
1616
1617 sas_phy->phy->maximum_linkrate = max;
1618 sas_phy->phy->minimum_linkrate = min;
1619 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
1620
1621 disable_phy_v2_hw(hisi_hba, phy_no);
1622 msleep(100);
1623 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1624 prog_phy_link_rate);
1625 start_phy_v2_hw(hisi_hba, phy_no);
1626 }
1627
1628 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1629 {
1630 int i, bitmap = 0;
1631 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1632 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1633
1634 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1635 if (phy_state & 1 << i)
1636 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1637 bitmap |= 1 << i;
1638
1639 if (hisi_hba->n_phy == 9) {
1640 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1641
1642 if (phy_state & 1 << 8)
1643 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1644 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1645 bitmap |= 1 << 9;
1646 }
1647
1648 return bitmap;
1649 }
1650
1651 /*
1652 * The callpath to this function and upto writing the write
1653 * queue pointer should be safe from interruption.
1654 */
1655 static int
1656 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1657 {
1658 struct device *dev = hisi_hba->dev;
1659 int queue = dq->id;
1660 u32 r, w;
1661
1662 w = dq->wr_point;
1663 r = hisi_sas_read32_relaxed(hisi_hba,
1664 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1665 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1666 dev_warn(dev, "full queue=%d r=%d w=%d\n",
1667 queue, r, w);
1668 return -EAGAIN;
1669 }
1670
1671 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
1672
1673 return w;
1674 }
1675
1676 /* DQ lock must be taken here */
1677 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1678 {
1679 struct hisi_hba *hisi_hba = dq->hisi_hba;
1680 struct hisi_sas_slot *s, *s1;
1681 struct list_head *dq_list;
1682 int dlvry_queue = dq->id;
1683 int wp, count = 0;
1684
1685 dq_list = &dq->list;
1686 list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1687 if (!s->ready)
1688 break;
1689 count++;
1690 wp = (s->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1691 list_del(&s->delivery);
1692 }
1693
1694 if (!count)
1695 return;
1696
1697 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1698 }
1699
1700 static void prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1701 struct hisi_sas_slot *slot,
1702 struct hisi_sas_cmd_hdr *hdr,
1703 struct scatterlist *scatter,
1704 int n_elem)
1705 {
1706 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1707 struct scatterlist *sg;
1708 int i;
1709
1710 for_each_sg(scatter, sg, n_elem, i) {
1711 struct hisi_sas_sge *entry = &sge_page->sge[i];
1712
1713 entry->addr = cpu_to_le64(sg_dma_address(sg));
1714 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1715 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1716 entry->data_off = 0;
1717 }
1718
1719 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1720
1721 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1722 }
1723
1724 static void prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1725 struct hisi_sas_slot *slot)
1726 {
1727 struct sas_task *task = slot->task;
1728 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1729 struct domain_device *device = task->dev;
1730 struct hisi_sas_port *port = slot->port;
1731 struct scatterlist *sg_req;
1732 struct hisi_sas_device *sas_dev = device->lldd_dev;
1733 dma_addr_t req_dma_addr;
1734 unsigned int req_len;
1735
1736 /* req */
1737 sg_req = &task->smp_task.smp_req;
1738 req_dma_addr = sg_dma_address(sg_req);
1739 req_len = sg_dma_len(&task->smp_task.smp_req);
1740
1741 /* create header */
1742 /* dw0 */
1743 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1744 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1745 (2 << CMD_HDR_CMD_OFF)); /* smp */
1746
1747 /* map itct entry */
1748 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1749 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1750 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1751
1752 /* dw2 */
1753 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1754 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1755 CMD_HDR_MRFL_OFF));
1756
1757 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1758
1759 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1760 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1761 }
1762
1763 static void prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1764 struct hisi_sas_slot *slot, int is_tmf,
1765 struct hisi_sas_tmf_task *tmf)
1766 {
1767 struct sas_task *task = slot->task;
1768 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1769 struct domain_device *device = task->dev;
1770 struct hisi_sas_device *sas_dev = device->lldd_dev;
1771 struct hisi_sas_port *port = slot->port;
1772 struct sas_ssp_task *ssp_task = &task->ssp_task;
1773 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1774 int has_data = 0, priority = is_tmf;
1775 u8 *buf_cmd;
1776 u32 dw1 = 0, dw2 = 0;
1777
1778 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1779 (2 << CMD_HDR_TLR_CTRL_OFF) |
1780 (port->id << CMD_HDR_PORT_OFF) |
1781 (priority << CMD_HDR_PRIORITY_OFF) |
1782 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1783
1784 dw1 = 1 << CMD_HDR_VDTL_OFF;
1785 if (is_tmf) {
1786 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1787 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1788 } else {
1789 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1790 switch (scsi_cmnd->sc_data_direction) {
1791 case DMA_TO_DEVICE:
1792 has_data = 1;
1793 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1794 break;
1795 case DMA_FROM_DEVICE:
1796 has_data = 1;
1797 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1798 break;
1799 default:
1800 dw1 &= ~CMD_HDR_DIR_MSK;
1801 }
1802 }
1803
1804 /* map itct entry */
1805 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1806 hdr->dw1 = cpu_to_le32(dw1);
1807
1808 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1809 + 3) / 4) << CMD_HDR_CFL_OFF) |
1810 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1811 (2 << CMD_HDR_SG_MOD_OFF);
1812 hdr->dw2 = cpu_to_le32(dw2);
1813
1814 hdr->transfer_tags = cpu_to_le32(slot->idx);
1815
1816 if (has_data)
1817 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1818 slot->n_elem);
1819
1820 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1821 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1822 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1823
1824 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1825 sizeof(struct ssp_frame_hdr);
1826
1827 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1828 if (!is_tmf) {
1829 buf_cmd[9] = task->ssp_task.task_attr |
1830 (task->ssp_task.task_prio << 3);
1831 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1832 task->ssp_task.cmd->cmd_len);
1833 } else {
1834 buf_cmd[10] = tmf->tmf;
1835 switch (tmf->tmf) {
1836 case TMF_ABORT_TASK:
1837 case TMF_QUERY_TASK:
1838 buf_cmd[12] =
1839 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1840 buf_cmd[13] =
1841 tmf->tag_of_task_to_be_managed & 0xff;
1842 break;
1843 default:
1844 break;
1845 }
1846 }
1847 }
1848
1849 #define TRANS_TX_ERR 0
1850 #define TRANS_RX_ERR 1
1851 #define DMA_TX_ERR 2
1852 #define SIPC_RX_ERR 3
1853 #define DMA_RX_ERR 4
1854
1855 #define DMA_TX_ERR_OFF 0
1856 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1857 #define SIPC_RX_ERR_OFF 16
1858 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1859
1860 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1861 {
1862 static const u8 trans_tx_err_code_prio[] = {
1863 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1864 TRANS_TX_ERR_PHY_NOT_ENABLE,
1865 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1866 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1867 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1868 RESERVED0,
1869 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1870 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1871 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1872 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1873 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1874 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1875 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1876 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1877 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1878 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1879 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1880 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1881 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1882 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1883 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1884 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1885 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1886 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1887 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1888 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1889 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1890 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1891 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1892 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1893 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1894 };
1895 int index, i;
1896
1897 for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1898 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1899 if (err_msk & (1 << index))
1900 return trans_tx_err_code_prio[i];
1901 }
1902 return -1;
1903 }
1904
1905 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1906 {
1907 static const u8 trans_rx_err_code_prio[] = {
1908 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1909 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1910 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1911 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1912 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1913 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1914 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1915 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1916 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1917 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1918 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1919 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1920 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1921 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1922 RESERVED1,
1923 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1924 TRANS_RX_ERR_WITH_DATA_LEN0,
1925 TRANS_RX_ERR_WITH_BAD_HASH,
1926 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1927 TRANS_RX_SSP_FRM_LEN_ERR,
1928 RESERVED2,
1929 RESERVED3,
1930 RESERVED4,
1931 RESERVED5,
1932 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1933 TRANS_RX_SMP_FRM_LEN_ERR,
1934 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1935 RESERVED6,
1936 RESERVED7,
1937 RESERVED8,
1938 RESERVED9,
1939 TRANS_RX_R_ERR,
1940 };
1941 int index, i;
1942
1943 for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1944 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1945 if (err_msk & (1 << index))
1946 return trans_rx_err_code_prio[i];
1947 }
1948 return -1;
1949 }
1950
1951 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1952 {
1953 static const u8 dma_tx_err_code_prio[] = {
1954 DMA_TX_UNEXP_XFER_ERR,
1955 DMA_TX_UNEXP_RETRANS_ERR,
1956 DMA_TX_XFER_LEN_OVERFLOW,
1957 DMA_TX_XFER_OFFSET_ERR,
1958 DMA_TX_RAM_ECC_ERR,
1959 DMA_TX_DIF_LEN_ALIGN_ERR,
1960 DMA_TX_DIF_CRC_ERR,
1961 DMA_TX_DIF_APP_ERR,
1962 DMA_TX_DIF_RPP_ERR,
1963 DMA_TX_DATA_SGL_OVERFLOW,
1964 DMA_TX_DIF_SGL_OVERFLOW,
1965 };
1966 int index, i;
1967
1968 for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1969 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1970 err_msk = err_msk & DMA_TX_ERR_MSK;
1971 if (err_msk & (1 << index))
1972 return dma_tx_err_code_prio[i];
1973 }
1974 return -1;
1975 }
1976
1977 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1978 {
1979 static const u8 sipc_rx_err_code_prio[] = {
1980 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1981 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1982 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1983 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1984 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1985 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1986 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1987 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1988 SIPC_RX_SATA_UNEXP_FIS_ERR,
1989 SIPC_RX_WRSETUP_ESTATUS_ERR,
1990 SIPC_RX_DATA_UNDERFLOW_ERR,
1991 };
1992 int index, i;
1993
1994 for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1995 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1996 err_msk = err_msk & SIPC_RX_ERR_MSK;
1997 if (err_msk & (1 << (index + 0x10)))
1998 return sipc_rx_err_code_prio[i];
1999 }
2000 return -1;
2001 }
2002
2003 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
2004 {
2005 static const u8 dma_rx_err_code_prio[] = {
2006 DMA_RX_UNKNOWN_FRM_ERR,
2007 DMA_RX_DATA_LEN_OVERFLOW,
2008 DMA_RX_DATA_LEN_UNDERFLOW,
2009 DMA_RX_DATA_OFFSET_ERR,
2010 RESERVED10,
2011 DMA_RX_SATA_FRAME_TYPE_ERR,
2012 DMA_RX_RESP_BUF_OVERFLOW,
2013 DMA_RX_UNEXP_RETRANS_RESP_ERR,
2014 DMA_RX_UNEXP_NORM_RESP_ERR,
2015 DMA_RX_UNEXP_RDFRAME_ERR,
2016 DMA_RX_PIO_DATA_LEN_ERR,
2017 DMA_RX_RDSETUP_STATUS_ERR,
2018 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2019 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2020 DMA_RX_RDSETUP_LEN_ODD_ERR,
2021 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2022 DMA_RX_RDSETUP_LEN_OVER_ERR,
2023 DMA_RX_RDSETUP_OFFSET_ERR,
2024 DMA_RX_RDSETUP_ACTIVE_ERR,
2025 DMA_RX_RDSETUP_ESTATUS_ERR,
2026 DMA_RX_RAM_ECC_ERR,
2027 DMA_RX_DIF_CRC_ERR,
2028 DMA_RX_DIF_APP_ERR,
2029 DMA_RX_DIF_RPP_ERR,
2030 DMA_RX_DATA_SGL_OVERFLOW,
2031 DMA_RX_DIF_SGL_OVERFLOW,
2032 };
2033 int index, i;
2034
2035 for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2036 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2037 if (err_msk & (1 << index))
2038 return dma_rx_err_code_prio[i];
2039 }
2040 return -1;
2041 }
2042
2043 /* by default, task resp is complete */
2044 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2045 struct sas_task *task,
2046 struct hisi_sas_slot *slot,
2047 int err_phase)
2048 {
2049 struct task_status_struct *ts = &task->task_status;
2050 struct hisi_sas_err_record_v2 *err_record =
2051 hisi_sas_status_buf_addr_mem(slot);
2052 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2053 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2054 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2055 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2056 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2057 int error = -1;
2058
2059 if (err_phase == 1) {
2060 /* error in TX phase, the priority of error is: DW2 > DW0 */
2061 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2062 if (error == -1)
2063 error = parse_trans_tx_err_code_v2_hw(
2064 trans_tx_fail_type);
2065 } else if (err_phase == 2) {
2066 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2067 error = parse_trans_rx_err_code_v2_hw(
2068 trans_rx_fail_type);
2069 if (error == -1) {
2070 error = parse_dma_rx_err_code_v2_hw(
2071 dma_rx_err_type);
2072 if (error == -1)
2073 error = parse_sipc_rx_err_code_v2_hw(
2074 sipc_rx_err_type);
2075 }
2076 }
2077
2078 switch (task->task_proto) {
2079 case SAS_PROTOCOL_SSP:
2080 {
2081 switch (error) {
2082 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2083 {
2084 ts->stat = SAS_OPEN_REJECT;
2085 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2086 break;
2087 }
2088 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2089 {
2090 ts->stat = SAS_OPEN_REJECT;
2091 ts->open_rej_reason = SAS_OREJ_EPROTO;
2092 break;
2093 }
2094 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2095 {
2096 ts->stat = SAS_OPEN_REJECT;
2097 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2098 break;
2099 }
2100 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2101 {
2102 ts->stat = SAS_OPEN_REJECT;
2103 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2104 break;
2105 }
2106 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2107 {
2108 ts->stat = SAS_OPEN_REJECT;
2109 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2110 break;
2111 }
2112 case DMA_RX_UNEXP_NORM_RESP_ERR:
2113 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2114 case DMA_RX_RESP_BUF_OVERFLOW:
2115 {
2116 ts->stat = SAS_OPEN_REJECT;
2117 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2118 break;
2119 }
2120 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2121 {
2122 /* not sure */
2123 ts->stat = SAS_DEV_NO_RESPONSE;
2124 break;
2125 }
2126 case DMA_RX_DATA_LEN_OVERFLOW:
2127 {
2128 ts->stat = SAS_DATA_OVERRUN;
2129 ts->residual = 0;
2130 break;
2131 }
2132 case DMA_RX_DATA_LEN_UNDERFLOW:
2133 {
2134 ts->residual = trans_tx_fail_type;
2135 ts->stat = SAS_DATA_UNDERRUN;
2136 break;
2137 }
2138 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2139 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2140 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2141 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2142 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2143 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2144 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2145 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2146 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2147 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2148 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2149 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2150 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2151 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2152 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2153 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2154 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2155 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2156 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2157 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2158 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2159 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2160 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2161 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2162 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2163 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2164 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2165 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2166 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2167 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2168 case TRANS_TX_ERR_FRAME_TXED:
2169 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2170 case TRANS_RX_ERR_WITH_DATA_LEN0:
2171 case TRANS_RX_ERR_WITH_BAD_HASH:
2172 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2173 case TRANS_RX_SSP_FRM_LEN_ERR:
2174 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2175 case DMA_TX_DATA_SGL_OVERFLOW:
2176 case DMA_TX_UNEXP_XFER_ERR:
2177 case DMA_TX_UNEXP_RETRANS_ERR:
2178 case DMA_TX_XFER_LEN_OVERFLOW:
2179 case DMA_TX_XFER_OFFSET_ERR:
2180 case SIPC_RX_DATA_UNDERFLOW_ERR:
2181 case DMA_RX_DATA_SGL_OVERFLOW:
2182 case DMA_RX_DATA_OFFSET_ERR:
2183 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2184 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2185 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2186 case DMA_RX_SATA_FRAME_TYPE_ERR:
2187 case DMA_RX_UNKNOWN_FRM_ERR:
2188 {
2189 /* This will request a retry */
2190 ts->stat = SAS_QUEUE_FULL;
2191 slot->abort = 1;
2192 break;
2193 }
2194 default:
2195 break;
2196 }
2197 }
2198 break;
2199 case SAS_PROTOCOL_SMP:
2200 ts->stat = SAM_STAT_CHECK_CONDITION;
2201 break;
2202
2203 case SAS_PROTOCOL_SATA:
2204 case SAS_PROTOCOL_STP:
2205 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2206 {
2207 switch (error) {
2208 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2209 {
2210 ts->stat = SAS_OPEN_REJECT;
2211 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2212 break;
2213 }
2214 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2215 {
2216 ts->resp = SAS_TASK_UNDELIVERED;
2217 ts->stat = SAS_DEV_NO_RESPONSE;
2218 break;
2219 }
2220 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2221 {
2222 ts->stat = SAS_OPEN_REJECT;
2223 ts->open_rej_reason = SAS_OREJ_EPROTO;
2224 break;
2225 }
2226 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2227 {
2228 ts->stat = SAS_OPEN_REJECT;
2229 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2230 break;
2231 }
2232 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2233 {
2234 ts->stat = SAS_OPEN_REJECT;
2235 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2236 break;
2237 }
2238 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2239 {
2240 ts->stat = SAS_OPEN_REJECT;
2241 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2242 break;
2243 }
2244 case DMA_RX_RESP_BUF_OVERFLOW:
2245 case DMA_RX_UNEXP_NORM_RESP_ERR:
2246 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2247 {
2248 ts->stat = SAS_OPEN_REJECT;
2249 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2250 break;
2251 }
2252 case DMA_RX_DATA_LEN_OVERFLOW:
2253 {
2254 ts->stat = SAS_DATA_OVERRUN;
2255 ts->residual = 0;
2256 break;
2257 }
2258 case DMA_RX_DATA_LEN_UNDERFLOW:
2259 {
2260 ts->residual = trans_tx_fail_type;
2261 ts->stat = SAS_DATA_UNDERRUN;
2262 break;
2263 }
2264 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2265 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2266 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2267 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2268 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2269 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2270 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2271 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2272 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2273 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2274 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2275 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2276 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2277 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2278 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2279 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2280 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2281 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2282 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2283 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2284 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2285 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2286 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2287 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2288 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2289 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2290 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2291 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2292 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2293 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2294 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2295 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2296 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2297 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2298 case TRANS_RX_ERR_WITH_DATA_LEN0:
2299 case TRANS_RX_ERR_WITH_BAD_HASH:
2300 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2301 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2302 case DMA_TX_DATA_SGL_OVERFLOW:
2303 case DMA_TX_UNEXP_XFER_ERR:
2304 case DMA_TX_UNEXP_RETRANS_ERR:
2305 case DMA_TX_XFER_LEN_OVERFLOW:
2306 case DMA_TX_XFER_OFFSET_ERR:
2307 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2308 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2309 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2310 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2311 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2312 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2313 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2314 case DMA_RX_DATA_SGL_OVERFLOW:
2315 case DMA_RX_DATA_OFFSET_ERR:
2316 case DMA_RX_SATA_FRAME_TYPE_ERR:
2317 case DMA_RX_UNEXP_RDFRAME_ERR:
2318 case DMA_RX_PIO_DATA_LEN_ERR:
2319 case DMA_RX_RDSETUP_STATUS_ERR:
2320 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2321 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2322 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2323 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2324 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2325 case DMA_RX_RDSETUP_OFFSET_ERR:
2326 case DMA_RX_RDSETUP_ACTIVE_ERR:
2327 case DMA_RX_RDSETUP_ESTATUS_ERR:
2328 case DMA_RX_UNKNOWN_FRM_ERR:
2329 case TRANS_RX_SSP_FRM_LEN_ERR:
2330 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2331 {
2332 slot->abort = 1;
2333 ts->stat = SAS_PHY_DOWN;
2334 break;
2335 }
2336 default:
2337 {
2338 ts->stat = SAS_PROTO_RESPONSE;
2339 break;
2340 }
2341 }
2342 hisi_sas_sata_done(task, slot);
2343 }
2344 break;
2345 default:
2346 break;
2347 }
2348 }
2349
2350 static int
2351 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2352 {
2353 struct sas_task *task = slot->task;
2354 struct hisi_sas_device *sas_dev;
2355 struct device *dev = hisi_hba->dev;
2356 struct task_status_struct *ts;
2357 struct domain_device *device;
2358 struct sas_ha_struct *ha;
2359 enum exec_status sts;
2360 struct hisi_sas_complete_v2_hdr *complete_queue =
2361 hisi_hba->complete_hdr[slot->cmplt_queue];
2362 struct hisi_sas_complete_v2_hdr *complete_hdr =
2363 &complete_queue[slot->cmplt_queue_slot];
2364 unsigned long flags;
2365 bool is_internal = slot->is_internal;
2366
2367 if (unlikely(!task || !task->lldd_task || !task->dev))
2368 return -EINVAL;
2369
2370 ts = &task->task_status;
2371 device = task->dev;
2372 ha = device->port->ha;
2373 sas_dev = device->lldd_dev;
2374
2375 spin_lock_irqsave(&task->task_state_lock, flags);
2376 task->task_state_flags &=
2377 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2378 spin_unlock_irqrestore(&task->task_state_lock, flags);
2379
2380 memset(ts, 0, sizeof(*ts));
2381 ts->resp = SAS_TASK_COMPLETE;
2382
2383 if (unlikely(!sas_dev)) {
2384 dev_dbg(dev, "slot complete: port has no device\n");
2385 ts->stat = SAS_PHY_DOWN;
2386 goto out;
2387 }
2388
2389 /* Use SAS+TMF status codes */
2390 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2391 >> CMPLT_HDR_ABORT_STAT_OFF) {
2392 case STAT_IO_ABORTED:
2393 /* this io has been aborted by abort command */
2394 ts->stat = SAS_ABORTED_TASK;
2395 goto out;
2396 case STAT_IO_COMPLETE:
2397 /* internal abort command complete */
2398 ts->stat = TMF_RESP_FUNC_SUCC;
2399 del_timer(&slot->internal_abort_timer);
2400 goto out;
2401 case STAT_IO_NO_DEVICE:
2402 ts->stat = TMF_RESP_FUNC_COMPLETE;
2403 del_timer(&slot->internal_abort_timer);
2404 goto out;
2405 case STAT_IO_NOT_VALID:
2406 /* abort single io, controller don't find
2407 * the io need to abort
2408 */
2409 ts->stat = TMF_RESP_FUNC_FAILED;
2410 del_timer(&slot->internal_abort_timer);
2411 goto out;
2412 default:
2413 break;
2414 }
2415
2416 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2417 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2418 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2419 >> CMPLT_HDR_ERR_PHASE_OFF;
2420 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2421
2422 /* Analyse error happens on which phase TX or RX */
2423 if (ERR_ON_TX_PHASE(err_phase))
2424 slot_err_v2_hw(hisi_hba, task, slot, 1);
2425 else if (ERR_ON_RX_PHASE(err_phase))
2426 slot_err_v2_hw(hisi_hba, task, slot, 2);
2427
2428 if (ts->stat != SAS_DATA_UNDERRUN)
2429 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
2430 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
2431 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
2432 slot->idx, task, sas_dev->device_id,
2433 complete_hdr->dw0, complete_hdr->dw1,
2434 complete_hdr->act, complete_hdr->dw3,
2435 error_info[0], error_info[1],
2436 error_info[2], error_info[3]);
2437
2438 if (unlikely(slot->abort))
2439 return ts->stat;
2440 goto out;
2441 }
2442
2443 switch (task->task_proto) {
2444 case SAS_PROTOCOL_SSP:
2445 {
2446 struct hisi_sas_status_buffer *status_buffer =
2447 hisi_sas_status_buf_addr_mem(slot);
2448 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2449 &status_buffer->iu[0];
2450
2451 sas_ssp_task_response(dev, task, iu);
2452 break;
2453 }
2454 case SAS_PROTOCOL_SMP:
2455 {
2456 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2457 void *to;
2458
2459 ts->stat = SAM_STAT_GOOD;
2460 to = kmap_atomic(sg_page(sg_resp));
2461
2462 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2463 DMA_FROM_DEVICE);
2464 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2465 DMA_TO_DEVICE);
2466 memcpy(to + sg_resp->offset,
2467 hisi_sas_status_buf_addr_mem(slot) +
2468 sizeof(struct hisi_sas_err_record),
2469 sg_dma_len(sg_resp));
2470 kunmap_atomic(to);
2471 break;
2472 }
2473 case SAS_PROTOCOL_SATA:
2474 case SAS_PROTOCOL_STP:
2475 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2476 {
2477 ts->stat = SAM_STAT_GOOD;
2478 hisi_sas_sata_done(task, slot);
2479 break;
2480 }
2481 default:
2482 ts->stat = SAM_STAT_CHECK_CONDITION;
2483 break;
2484 }
2485
2486 if (!slot->port->port_attached) {
2487 dev_warn(dev, "slot complete: port %d has removed\n",
2488 slot->port->sas_port.id);
2489 ts->stat = SAS_PHY_DOWN;
2490 }
2491
2492 out:
2493 hisi_sas_slot_task_free(hisi_hba, task, slot);
2494 sts = ts->stat;
2495 spin_lock_irqsave(&task->task_state_lock, flags);
2496 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2497 spin_unlock_irqrestore(&task->task_state_lock, flags);
2498 dev_info(dev, "slot complete: task(%p) aborted\n", task);
2499 return SAS_ABORTED_TASK;
2500 }
2501 task->task_state_flags |= SAS_TASK_STATE_DONE;
2502 spin_unlock_irqrestore(&task->task_state_lock, flags);
2503
2504 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2505 spin_lock_irqsave(&device->done_lock, flags);
2506 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2507 spin_unlock_irqrestore(&device->done_lock, flags);
2508 dev_info(dev, "slot complete: task(%p) ignored\n ",
2509 task);
2510 return sts;
2511 }
2512 spin_unlock_irqrestore(&device->done_lock, flags);
2513 }
2514
2515 if (task->task_done)
2516 task->task_done(task);
2517
2518 return sts;
2519 }
2520
2521 static void prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2522 struct hisi_sas_slot *slot)
2523 {
2524 struct sas_task *task = slot->task;
2525 struct domain_device *device = task->dev;
2526 struct domain_device *parent_dev = device->parent;
2527 struct hisi_sas_device *sas_dev = device->lldd_dev;
2528 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2529 struct asd_sas_port *sas_port = device->port;
2530 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2531 u8 *buf_cmd;
2532 int has_data = 0, hdr_tag = 0;
2533 u32 dw1 = 0, dw2 = 0;
2534
2535 /* create header */
2536 /* dw0 */
2537 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2538 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2539 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2540 else
2541 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2542
2543 /* dw1 */
2544 switch (task->data_dir) {
2545 case DMA_TO_DEVICE:
2546 has_data = 1;
2547 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2548 break;
2549 case DMA_FROM_DEVICE:
2550 has_data = 1;
2551 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2552 break;
2553 default:
2554 dw1 &= ~CMD_HDR_DIR_MSK;
2555 }
2556
2557 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2558 (task->ata_task.fis.control & ATA_SRST))
2559 dw1 |= 1 << CMD_HDR_RESET_OFF;
2560
2561 dw1 |= (hisi_sas_get_ata_protocol(
2562 &task->ata_task.fis, task->data_dir))
2563 << CMD_HDR_FRAME_TYPE_OFF;
2564 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2565 hdr->dw1 = cpu_to_le32(dw1);
2566
2567 /* dw2 */
2568 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2569 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2570 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2571 }
2572
2573 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2574 2 << CMD_HDR_SG_MOD_OFF;
2575 hdr->dw2 = cpu_to_le32(dw2);
2576
2577 /* dw3 */
2578 hdr->transfer_tags = cpu_to_le32(slot->idx);
2579
2580 if (has_data)
2581 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2582 slot->n_elem);
2583
2584 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2585 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2586 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2587
2588 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2589
2590 if (likely(!task->ata_task.device_control_reg_update))
2591 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2592 /* fill in command FIS */
2593 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2594 }
2595
2596 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
2597 {
2598 struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
2599 struct hisi_sas_port *port = slot->port;
2600 struct asd_sas_port *asd_sas_port;
2601 struct asd_sas_phy *sas_phy;
2602
2603 if (!port)
2604 return;
2605
2606 asd_sas_port = &port->sas_port;
2607
2608 /* Kick the hardware - send break command */
2609 list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2610 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2611 struct hisi_hba *hisi_hba = phy->hisi_hba;
2612 int phy_no = sas_phy->id;
2613 u32 link_dfx2;
2614
2615 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2616 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2617 (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2618 u32 txid_auto;
2619
2620 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2621 TXID_AUTO);
2622 txid_auto |= TXID_AUTO_CTB_MSK;
2623 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2624 txid_auto);
2625 return;
2626 }
2627 }
2628 }
2629
2630 static void prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2631 struct hisi_sas_slot *slot,
2632 int device_id, int abort_flag, int tag_to_abort)
2633 {
2634 struct sas_task *task = slot->task;
2635 struct domain_device *dev = task->dev;
2636 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2637 struct hisi_sas_port *port = slot->port;
2638 struct timer_list *timer = &slot->internal_abort_timer;
2639
2640 /* setup the quirk timer */
2641 timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
2642 /* Set the timeout to 10ms less than internal abort timeout */
2643 mod_timer(timer, jiffies + msecs_to_jiffies(100));
2644
2645 /* dw0 */
2646 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2647 (port->id << CMD_HDR_PORT_OFF) |
2648 (dev_is_sata(dev) <<
2649 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2650 (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2651
2652 /* dw1 */
2653 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2654
2655 /* dw7 */
2656 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2657 hdr->transfer_tags = cpu_to_le32(slot->idx);
2658 }
2659
2660 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2661 {
2662 int i, res = IRQ_HANDLED;
2663 u32 port_id, link_rate;
2664 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2665 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2666 struct device *dev = hisi_hba->dev;
2667 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2668 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2669
2670 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2671
2672 if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2673 goto end;
2674
2675 if (phy_no == 8) {
2676 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2677
2678 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2679 PORT_STATE_PHY8_PORT_NUM_OFF;
2680 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2681 PORT_STATE_PHY8_CONN_RATE_OFF;
2682 } else {
2683 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2684 port_id = (port_id >> (4 * phy_no)) & 0xf;
2685 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2686 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2687 }
2688
2689 if (port_id == 0xf) {
2690 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2691 res = IRQ_NONE;
2692 goto end;
2693 }
2694
2695 for (i = 0; i < 6; i++) {
2696 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2697 RX_IDAF_DWORD0 + (i * 4));
2698 frame_rcvd[i] = __swab32(idaf);
2699 }
2700
2701 sas_phy->linkrate = link_rate;
2702 sas_phy->oob_mode = SAS_OOB_MODE;
2703 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2704 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2705 phy->port_id = port_id;
2706 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2707 phy->phy_type |= PORT_TYPE_SAS;
2708 phy->phy_attached = 1;
2709 phy->identify.device_type = id->dev_type;
2710 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
2711 if (phy->identify.device_type == SAS_END_DEVICE)
2712 phy->identify.target_port_protocols =
2713 SAS_PROTOCOL_SSP;
2714 else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2715 phy->identify.target_port_protocols =
2716 SAS_PROTOCOL_SMP;
2717 if (!timer_pending(&hisi_hba->timer))
2718 set_link_timer_quirk(hisi_hba);
2719 }
2720 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
2721
2722 end:
2723 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2724 CHL_INT0_SL_PHY_ENABLE_MSK);
2725 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2726
2727 return res;
2728 }
2729
2730 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2731 {
2732 u32 port_state;
2733
2734 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2735 if (port_state & 0x1ff)
2736 return true;
2737
2738 return false;
2739 }
2740
2741 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2742 {
2743 u32 phy_state, sl_ctrl, txid_auto;
2744 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2745 struct hisi_sas_port *port = phy->port;
2746 struct device *dev = hisi_hba->dev;
2747
2748 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2749
2750 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2751 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
2752 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2753
2754 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2755 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2756 sl_ctrl & ~SL_CONTROL_CTA_MSK);
2757 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2758 if (!check_any_wideports_v2_hw(hisi_hba) &&
2759 timer_pending(&hisi_hba->timer))
2760 del_timer(&hisi_hba->timer);
2761
2762 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2763 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2764 txid_auto | TXID_AUTO_CT3_MSK);
2765
2766 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2767 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2768
2769 return IRQ_HANDLED;
2770 }
2771
2772 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2773 {
2774 struct hisi_hba *hisi_hba = p;
2775 u32 irq_msk;
2776 int phy_no = 0;
2777 irqreturn_t res = IRQ_NONE;
2778
2779 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2780 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2781 while (irq_msk) {
2782 if (irq_msk & 1) {
2783 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2784 CHL_INT0);
2785
2786 switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2787 CHL_INT0_SL_PHY_ENABLE_MSK)) {
2788
2789 case CHL_INT0_SL_PHY_ENABLE_MSK:
2790 /* phy up */
2791 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2792 IRQ_HANDLED)
2793 res = IRQ_HANDLED;
2794 break;
2795
2796 case CHL_INT0_NOT_RDY_MSK:
2797 /* phy down */
2798 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2799 IRQ_HANDLED)
2800 res = IRQ_HANDLED;
2801 break;
2802
2803 case (CHL_INT0_NOT_RDY_MSK |
2804 CHL_INT0_SL_PHY_ENABLE_MSK):
2805 reg_value = hisi_sas_read32(hisi_hba,
2806 PHY_STATE);
2807 if (reg_value & BIT(phy_no)) {
2808 /* phy up */
2809 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2810 IRQ_HANDLED)
2811 res = IRQ_HANDLED;
2812 } else {
2813 /* phy down */
2814 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2815 IRQ_HANDLED)
2816 res = IRQ_HANDLED;
2817 }
2818 break;
2819
2820 default:
2821 break;
2822 }
2823
2824 }
2825 irq_msk >>= 1;
2826 phy_no++;
2827 }
2828
2829 return res;
2830 }
2831
2832 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2833 {
2834 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2835 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2836 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2837 u32 bcast_status;
2838
2839 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2840 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2841 if (bcast_status & RX_BCAST_CHG_MSK)
2842 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2843 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2844 CHL_INT0_SL_RX_BCST_ACK_MSK);
2845 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2846 }
2847
2848 static const struct hisi_sas_hw_error port_ecc_axi_error[] = {
2849 {
2850 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF),
2851 .msg = "dmac_tx_ecc_bad_err",
2852 },
2853 {
2854 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF),
2855 .msg = "dmac_rx_ecc_bad_err",
2856 },
2857 {
2858 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
2859 .msg = "dma_tx_axi_wr_err",
2860 },
2861 {
2862 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
2863 .msg = "dma_tx_axi_rd_err",
2864 },
2865 {
2866 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
2867 .msg = "dma_rx_axi_wr_err",
2868 },
2869 {
2870 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
2871 .msg = "dma_rx_axi_rd_err",
2872 },
2873 };
2874
2875 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2876 {
2877 struct hisi_hba *hisi_hba = p;
2878 struct device *dev = hisi_hba->dev;
2879 u32 ent_msk, ent_tmp, irq_msk;
2880 int phy_no = 0;
2881
2882 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2883 ent_tmp = ent_msk;
2884 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2885 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2886
2887 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2888 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2889
2890 while (irq_msk) {
2891 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2892 CHL_INT0);
2893 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2894 CHL_INT1);
2895 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2896 CHL_INT2);
2897
2898 if ((irq_msk & (1 << phy_no)) && irq_value1) {
2899 int i;
2900
2901 for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) {
2902 const struct hisi_sas_hw_error *error =
2903 &port_ecc_axi_error[i];
2904
2905 if (!(irq_value1 & error->irq_msk))
2906 continue;
2907
2908 dev_warn(dev, "%s error (phy%d 0x%x) found!\n",
2909 error->msg, phy_no, irq_value1);
2910 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2911 }
2912
2913 hisi_sas_phy_write32(hisi_hba, phy_no,
2914 CHL_INT1, irq_value1);
2915 }
2916
2917 if ((irq_msk & (1 << phy_no)) && irq_value2) {
2918 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2919
2920 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
2921 dev_warn(dev, "phy%d identify timeout\n",
2922 phy_no);
2923 hisi_sas_notify_phy_event(phy,
2924 HISI_PHYE_LINK_RESET);
2925 }
2926
2927 hisi_sas_phy_write32(hisi_hba, phy_no,
2928 CHL_INT2, irq_value2);
2929 }
2930
2931 if ((irq_msk & (1 << phy_no)) && irq_value0) {
2932 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2933 phy_bcast_v2_hw(phy_no, hisi_hba);
2934
2935 hisi_sas_phy_write32(hisi_hba, phy_no,
2936 CHL_INT0, irq_value0
2937 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2938 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2939 & (~CHL_INT0_NOT_RDY_MSK));
2940 }
2941 irq_msk &= ~(1 << phy_no);
2942 phy_no++;
2943 }
2944
2945 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2946
2947 return IRQ_HANDLED;
2948 }
2949
2950 static void
2951 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2952 {
2953 struct device *dev = hisi_hba->dev;
2954 const struct hisi_sas_hw_error *ecc_error;
2955 u32 val;
2956 int i;
2957
2958 for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2959 ecc_error = &one_bit_ecc_errors[i];
2960 if (irq_value & ecc_error->irq_msk) {
2961 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2962 val &= ecc_error->msk;
2963 val >>= ecc_error->shift;
2964 dev_warn(dev, ecc_error->msg, val);
2965 }
2966 }
2967 }
2968
2969 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2970 u32 irq_value)
2971 {
2972 struct device *dev = hisi_hba->dev;
2973 const struct hisi_sas_hw_error *ecc_error;
2974 u32 val;
2975 int i;
2976
2977 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2978 ecc_error = &multi_bit_ecc_errors[i];
2979 if (irq_value & ecc_error->irq_msk) {
2980 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2981 val &= ecc_error->msk;
2982 val >>= ecc_error->shift;
2983 dev_err(dev, ecc_error->msg, irq_value, val);
2984 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2985 }
2986 }
2987
2988 return;
2989 }
2990
2991 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
2992 {
2993 struct hisi_hba *hisi_hba = p;
2994 u32 irq_value, irq_msk;
2995
2996 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2997 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
2998
2999 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
3000 if (irq_value) {
3001 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3002 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3003 }
3004
3005 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
3006 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
3007
3008 return IRQ_HANDLED;
3009 }
3010
3011 static const struct hisi_sas_hw_error axi_error[] = {
3012 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
3013 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
3014 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
3015 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
3016 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
3017 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
3018 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
3019 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
3020 {},
3021 };
3022
3023 static const struct hisi_sas_hw_error fifo_error[] = {
3024 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
3025 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
3026 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
3027 { .msk = BIT(11), .msg = "CMDP_FIFO" },
3028 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
3029 {},
3030 };
3031
3032 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
3033 {
3034 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
3035 .msg = "write pointer and depth",
3036 },
3037 {
3038 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
3039 .msg = "iptt no match slot",
3040 },
3041 {
3042 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
3043 .msg = "read pointer and depth",
3044 },
3045 {
3046 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
3047 .reg = HGC_AXI_FIFO_ERR_INFO,
3048 .sub = axi_error,
3049 },
3050 {
3051 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
3052 .reg = HGC_AXI_FIFO_ERR_INFO,
3053 .sub = fifo_error,
3054 },
3055 {
3056 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
3057 .msg = "LM add/fetch list",
3058 },
3059 {
3060 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
3061 .msg = "SAS_HGC_ABT fetch LM list",
3062 },
3063 };
3064
3065 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
3066 {
3067 struct hisi_hba *hisi_hba = p;
3068 u32 irq_value, irq_msk, err_value;
3069 struct device *dev = hisi_hba->dev;
3070 const struct hisi_sas_hw_error *axi_error;
3071 int i;
3072
3073 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3074 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3075
3076 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3077
3078 for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3079 axi_error = &fatal_axi_errors[i];
3080 if (!(irq_value & axi_error->irq_msk))
3081 continue;
3082
3083 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3084 1 << axi_error->shift);
3085 if (axi_error->sub) {
3086 const struct hisi_sas_hw_error *sub = axi_error->sub;
3087
3088 err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3089 for (; sub->msk || sub->msg; sub++) {
3090 if (!(err_value & sub->msk))
3091 continue;
3092 dev_err(dev, "%s (0x%x) found!\n",
3093 sub->msg, irq_value);
3094 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3095 }
3096 } else {
3097 dev_err(dev, "%s (0x%x) found!\n",
3098 axi_error->msg, irq_value);
3099 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3100 }
3101 }
3102
3103 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3104 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3105 u32 dev_id = reg_val & ITCT_DEV_MSK;
3106 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3107
3108 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3109 dev_dbg(dev, "clear ITCT ok\n");
3110 complete(sas_dev->completion);
3111 }
3112
3113 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3114 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3115
3116 return IRQ_HANDLED;
3117 }
3118
3119 static void cq_tasklet_v2_hw(unsigned long val)
3120 {
3121 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3122 struct hisi_hba *hisi_hba = cq->hisi_hba;
3123 struct hisi_sas_slot *slot;
3124 struct hisi_sas_itct *itct;
3125 struct hisi_sas_complete_v2_hdr *complete_queue;
3126 u32 rd_point = cq->rd_point, wr_point, dev_id;
3127 int queue = cq->id;
3128
3129 if (unlikely(hisi_hba->reject_stp_links_msk))
3130 phys_try_accept_stp_links_v2_hw(hisi_hba);
3131
3132 complete_queue = hisi_hba->complete_hdr[queue];
3133
3134 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3135 (0x14 * queue));
3136
3137 while (rd_point != wr_point) {
3138 struct hisi_sas_complete_v2_hdr *complete_hdr;
3139 int iptt;
3140
3141 complete_hdr = &complete_queue[rd_point];
3142
3143 /* Check for NCQ completion */
3144 if (complete_hdr->act) {
3145 u32 act_tmp = complete_hdr->act;
3146 int ncq_tag_count = ffs(act_tmp);
3147
3148 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3149 CMPLT_HDR_DEV_ID_OFF;
3150 itct = &hisi_hba->itct[dev_id];
3151
3152 /* The NCQ tags are held in the itct header */
3153 while (ncq_tag_count) {
3154 __le64 *ncq_tag = &itct->qw4_15[0];
3155
3156 ncq_tag_count -= 1;
3157 iptt = (ncq_tag[ncq_tag_count / 5]
3158 >> (ncq_tag_count % 5) * 12) & 0xfff;
3159
3160 slot = &hisi_hba->slot_info[iptt];
3161 slot->cmplt_queue_slot = rd_point;
3162 slot->cmplt_queue = queue;
3163 slot_complete_v2_hw(hisi_hba, slot);
3164
3165 act_tmp &= ~(1 << ncq_tag_count);
3166 ncq_tag_count = ffs(act_tmp);
3167 }
3168 } else {
3169 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3170 slot = &hisi_hba->slot_info[iptt];
3171 slot->cmplt_queue_slot = rd_point;
3172 slot->cmplt_queue = queue;
3173 slot_complete_v2_hw(hisi_hba, slot);
3174 }
3175
3176 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3177 rd_point = 0;
3178 }
3179
3180 /* update rd_point */
3181 cq->rd_point = rd_point;
3182 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3183 }
3184
3185 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3186 {
3187 struct hisi_sas_cq *cq = p;
3188 struct hisi_hba *hisi_hba = cq->hisi_hba;
3189 int queue = cq->id;
3190
3191 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3192
3193 tasklet_schedule(&cq->tasklet);
3194
3195 return IRQ_HANDLED;
3196 }
3197
3198 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3199 {
3200 struct hisi_sas_phy *phy = p;
3201 struct hisi_hba *hisi_hba = phy->hisi_hba;
3202 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3203 struct device *dev = hisi_hba->dev;
3204 struct hisi_sas_initial_fis *initial_fis;
3205 struct dev_to_host_fis *fis;
3206 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3207 irqreturn_t res = IRQ_HANDLED;
3208 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3209 int phy_no, offset;
3210
3211 phy_no = sas_phy->id;
3212 initial_fis = &hisi_hba->initial_fis[phy_no];
3213 fis = &initial_fis->fis;
3214
3215 offset = 4 * (phy_no / 4);
3216 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3217 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3218 ent_msk | 1 << ((phy_no % 4) * 8));
3219
3220 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3221 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3222 (phy_no % 4)));
3223 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3224 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3225 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3226 res = IRQ_NONE;
3227 goto end;
3228 }
3229
3230 /* check ERR bit of Status Register */
3231 if (fis->status & ATA_ERR) {
3232 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3233 fis->status);
3234 disable_phy_v2_hw(hisi_hba, phy_no);
3235 enable_phy_v2_hw(hisi_hba, phy_no);
3236 res = IRQ_NONE;
3237 goto end;
3238 }
3239
3240 if (unlikely(phy_no == 8)) {
3241 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3242
3243 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3244 PORT_STATE_PHY8_PORT_NUM_OFF;
3245 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3246 PORT_STATE_PHY8_CONN_RATE_OFF;
3247 } else {
3248 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3249 port_id = (port_id >> (4 * phy_no)) & 0xf;
3250 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3251 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3252 }
3253
3254 if (port_id == 0xf) {
3255 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3256 res = IRQ_NONE;
3257 goto end;
3258 }
3259
3260 sas_phy->linkrate = link_rate;
3261 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3262 HARD_PHY_LINKRATE);
3263 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3264 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3265
3266 sas_phy->oob_mode = SATA_OOB_MODE;
3267 /* Make up some unique SAS address */
3268 attached_sas_addr[0] = 0x50;
3269 attached_sas_addr[7] = phy_no;
3270 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3271 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3272 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3273 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3274 phy->port_id = port_id;
3275 phy->phy_type |= PORT_TYPE_SATA;
3276 phy->phy_attached = 1;
3277 phy->identify.device_type = SAS_SATA_DEV;
3278 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3279 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3280 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
3281
3282 end:
3283 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3284 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3285
3286 return res;
3287 }
3288
3289 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3290 int_phy_updown_v2_hw,
3291 int_chnl_int_v2_hw,
3292 };
3293
3294 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3295 fatal_ecc_int_v2_hw,
3296 fatal_axi_int_v2_hw
3297 };
3298
3299 /**
3300 * There is a limitation in the hip06 chipset that we need
3301 * to map in all mbigen interrupts, even if they are not used.
3302 */
3303 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3304 {
3305 struct platform_device *pdev = hisi_hba->platform_dev;
3306 struct device *dev = &pdev->dev;
3307 int irq, rc, irq_map[128];
3308 int i, phy_no, fatal_no, queue_no, k;
3309
3310 for (i = 0; i < 128; i++)
3311 irq_map[i] = platform_get_irq(pdev, i);
3312
3313 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3314 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3315 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3316 DRV_NAME " phy", hisi_hba);
3317 if (rc) {
3318 dev_err(dev, "irq init: could not request "
3319 "phy interrupt %d, rc=%d\n",
3320 irq, rc);
3321 rc = -ENOENT;
3322 goto free_phy_int_irqs;
3323 }
3324 }
3325
3326 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3327 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3328
3329 irq = irq_map[phy_no + 72];
3330 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3331 DRV_NAME " sata", phy);
3332 if (rc) {
3333 dev_err(dev, "irq init: could not request "
3334 "sata interrupt %d, rc=%d\n",
3335 irq, rc);
3336 rc = -ENOENT;
3337 goto free_sata_int_irqs;
3338 }
3339 }
3340
3341 for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3342 irq = irq_map[fatal_no + 81];
3343 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3344 DRV_NAME " fatal", hisi_hba);
3345 if (rc) {
3346 dev_err(dev,
3347 "irq init: could not request fatal interrupt %d, rc=%d\n",
3348 irq, rc);
3349 rc = -ENOENT;
3350 goto free_fatal_int_irqs;
3351 }
3352 }
3353
3354 for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3355 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3356 struct tasklet_struct *t = &cq->tasklet;
3357
3358 irq = irq_map[queue_no + 96];
3359 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3360 DRV_NAME " cq", cq);
3361 if (rc) {
3362 dev_err(dev,
3363 "irq init: could not request cq interrupt %d, rc=%d\n",
3364 irq, rc);
3365 rc = -ENOENT;
3366 goto free_cq_int_irqs;
3367 }
3368 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3369 }
3370
3371 return 0;
3372
3373 free_cq_int_irqs:
3374 for (k = 0; k < queue_no; k++) {
3375 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3376
3377 free_irq(irq_map[k + 96], cq);
3378 tasklet_kill(&cq->tasklet);
3379 }
3380 free_fatal_int_irqs:
3381 for (k = 0; k < fatal_no; k++)
3382 free_irq(irq_map[k + 81], hisi_hba);
3383 free_sata_int_irqs:
3384 for (k = 0; k < phy_no; k++) {
3385 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3386
3387 free_irq(irq_map[k + 72], phy);
3388 }
3389 free_phy_int_irqs:
3390 for (k = 0; k < i; k++)
3391 free_irq(irq_map[k + 1], hisi_hba);
3392 return rc;
3393 }
3394
3395 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3396 {
3397 int rc;
3398
3399 memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3400
3401 rc = hw_init_v2_hw(hisi_hba);
3402 if (rc)
3403 return rc;
3404
3405 rc = interrupt_init_v2_hw(hisi_hba);
3406 if (rc)
3407 return rc;
3408
3409 return 0;
3410 }
3411
3412 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3413 {
3414 struct platform_device *pdev = hisi_hba->platform_dev;
3415 int i;
3416
3417 for (i = 0; i < hisi_hba->queue_count; i++)
3418 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3419
3420 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3421 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3422 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3423 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3424
3425 for (i = 0; i < hisi_hba->n_phy; i++) {
3426 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3427 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3428 }
3429
3430 for (i = 0; i < 128; i++)
3431 synchronize_irq(platform_get_irq(pdev, i));
3432 }
3433
3434
3435 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3436 {
3437 return hisi_sas_read32(hisi_hba, PHY_STATE);
3438 }
3439
3440 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3441 {
3442 struct device *dev = hisi_hba->dev;
3443 int rc, cnt;
3444
3445 interrupt_disable_v2_hw(hisi_hba);
3446 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3447 hisi_sas_kill_tasklets(hisi_hba);
3448
3449 hisi_sas_stop_phys(hisi_hba);
3450
3451 mdelay(10);
3452
3453 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3454
3455 /* wait until bus idle */
3456 cnt = 0;
3457 while (1) {
3458 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3459 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3460
3461 if (status == 0x3)
3462 break;
3463
3464 udelay(10);
3465 if (cnt++ > 10) {
3466 dev_err(dev, "wait axi bus state to idle timeout!\n");
3467 return -1;
3468 }
3469 }
3470
3471 hisi_sas_init_mem(hisi_hba);
3472
3473 rc = hw_init_v2_hw(hisi_hba);
3474 if (rc)
3475 return rc;
3476
3477 phys_reject_stp_links_v2_hw(hisi_hba);
3478
3479 return 0;
3480 }
3481
3482 static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
3483 u8 reg_index, u8 reg_count, u8 *write_data)
3484 {
3485 struct device *dev = hisi_hba->dev;
3486 int phy_no, count;
3487
3488 if (!hisi_hba->sgpio_regs)
3489 return -EOPNOTSUPP;
3490
3491 switch (reg_type) {
3492 case SAS_GPIO_REG_TX:
3493 count = reg_count * 4;
3494 count = min(count, hisi_hba->n_phy);
3495
3496 for (phy_no = 0; phy_no < count; phy_no++) {
3497 /*
3498 * GPIO_TX[n] register has the highest numbered drive
3499 * of the four in the first byte and the lowest
3500 * numbered drive in the fourth byte.
3501 * See SFF-8485 Rev. 0.7 Table 24.
3502 */
3503 void __iomem *reg_addr = hisi_hba->sgpio_regs +
3504 reg_index * 4 + phy_no;
3505 int data_idx = phy_no + 3 - (phy_no % 4) * 2;
3506
3507 writeb(write_data[data_idx], reg_addr);
3508 }
3509
3510 break;
3511 default:
3512 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3513 reg_type);
3514 return -EINVAL;
3515 }
3516
3517 return 0;
3518 }
3519
3520
3521 static struct scsi_host_template sht_v2_hw = {
3522 .name = DRV_NAME,
3523 .module = THIS_MODULE,
3524 .queuecommand = sas_queuecommand,
3525 .target_alloc = sas_target_alloc,
3526 .slave_configure = hisi_sas_slave_configure,
3527 .scan_finished = hisi_sas_scan_finished,
3528 .scan_start = hisi_sas_scan_start,
3529 .change_queue_depth = sas_change_queue_depth,
3530 .bios_param = sas_bios_param,
3531 .can_queue = 1,
3532 .this_id = -1,
3533 .sg_tablesize = SG_ALL,
3534 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
3535 .use_clustering = ENABLE_CLUSTERING,
3536 .eh_device_reset_handler = sas_eh_device_reset_handler,
3537 .eh_target_reset_handler = sas_eh_target_reset_handler,
3538 .target_destroy = sas_target_destroy,
3539 .ioctl = sas_ioctl,
3540 .shost_attrs = host_attrs,
3541 };
3542
3543 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3544 .hw_init = hisi_sas_v2_init,
3545 .setup_itct = setup_itct_v2_hw,
3546 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3547 .alloc_dev = alloc_dev_quirk_v2_hw,
3548 .sl_notify = sl_notify_v2_hw,
3549 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3550 .clear_itct = clear_itct_v2_hw,
3551 .free_device = free_device_v2_hw,
3552 .prep_smp = prep_smp_v2_hw,
3553 .prep_ssp = prep_ssp_v2_hw,
3554 .prep_stp = prep_ata_v2_hw,
3555 .prep_abort = prep_abort_v2_hw,
3556 .get_free_slot = get_free_slot_v2_hw,
3557 .start_delivery = start_delivery_v2_hw,
3558 .slot_complete = slot_complete_v2_hw,
3559 .phys_init = phys_init_v2_hw,
3560 .phy_start = start_phy_v2_hw,
3561 .phy_disable = disable_phy_v2_hw,
3562 .phy_hard_reset = phy_hard_reset_v2_hw,
3563 .get_events = phy_get_events_v2_hw,
3564 .phy_set_linkrate = phy_set_linkrate_v2_hw,
3565 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3566 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3567 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3568 .soft_reset = soft_reset_v2_hw,
3569 .get_phys_state = get_phys_state_v2_hw,
3570 .write_gpio = write_gpio_v2_hw,
3571 .sht = &sht_v2_hw,
3572 };
3573
3574 static int hisi_sas_v2_probe(struct platform_device *pdev)
3575 {
3576 /*
3577 * Check if we should defer the probe before we probe the
3578 * upper layer, as it's hard to defer later on.
3579 */
3580 int ret = platform_get_irq(pdev, 0);
3581
3582 if (ret < 0) {
3583 if (ret != -EPROBE_DEFER)
3584 dev_err(&pdev->dev, "cannot obtain irq\n");
3585 return ret;
3586 }
3587
3588 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3589 }
3590
3591 static int hisi_sas_v2_remove(struct platform_device *pdev)
3592 {
3593 struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3594 struct hisi_hba *hisi_hba = sha->lldd_ha;
3595
3596 hisi_sas_kill_tasklets(hisi_hba);
3597
3598 return hisi_sas_remove(pdev);
3599 }
3600
3601 static const struct of_device_id sas_v2_of_match[] = {
3602 { .compatible = "hisilicon,hip06-sas-v2",},
3603 { .compatible = "hisilicon,hip07-sas-v2",},
3604 {},
3605 };
3606 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3607
3608 static const struct acpi_device_id sas_v2_acpi_match[] = {
3609 { "HISI0162", 0 },
3610 { }
3611 };
3612
3613 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3614
3615 static struct platform_driver hisi_sas_v2_driver = {
3616 .probe = hisi_sas_v2_probe,
3617 .remove = hisi_sas_v2_remove,
3618 .driver = {
3619 .name = DRV_NAME,
3620 .of_match_table = sas_v2_of_match,
3621 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3622 },
3623 };
3624
3625 module_platform_driver(hisi_sas_v2_driver);
3626
3627 MODULE_LICENSE("GPL");
3628 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3629 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3630 MODULE_ALIAS("platform:" DRV_NAME);
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