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scsi: hisi_sas: make SAS address of SATA disks unique
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
1 /*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12 #include "hisi_sas.h"
13 #define DRV_NAME "hisi_sas_v2_hw"
14
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
34 #define ITCT_CLR 0x44
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define CQE_SEND_CNT 0x248
148 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
149 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
150 #define DLVRY_Q_0_DEPTH 0x268
151 #define DLVRY_Q_0_WR_PTR 0x26c
152 #define DLVRY_Q_0_RD_PTR 0x270
153 #define HYPER_STREAM_ID_EN_CFG 0xc80
154 #define OQ0_INT_SRC_MSK 0xc90
155 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
156 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
157 #define COMPL_Q_0_DEPTH 0x4e8
158 #define COMPL_Q_0_WR_PTR 0x4ec
159 #define COMPL_Q_0_RD_PTR 0x4f0
160 #define HGC_RXM_DFX_STATUS14 0xae8
161 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
162 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
163 HGC_RXM_DFX_STATUS14_MEM0_OFF)
164 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
165 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
166 HGC_RXM_DFX_STATUS14_MEM1_OFF)
167 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
168 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
169 HGC_RXM_DFX_STATUS14_MEM2_OFF)
170 #define HGC_RXM_DFX_STATUS15 0xaec
171 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
172 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
173 HGC_RXM_DFX_STATUS15_MEM3_OFF)
174 /* phy registers need init */
175 #define PORT_BASE (0x2000)
176
177 #define PHY_CFG (PORT_BASE + 0x0)
178 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
179 #define PHY_CFG_ENA_OFF 0
180 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
181 #define PHY_CFG_DC_OPT_OFF 2
182 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
183 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
184 #define PROG_PHY_LINK_RATE_MAX_OFF 0
185 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
186 #define PHY_CTRL (PORT_BASE + 0x14)
187 #define PHY_CTRL_RESET_OFF 0
188 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
189 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
190 #define SL_CFG (PORT_BASE + 0x84)
191 #define PHY_PCN (PORT_BASE + 0x44)
192 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
193 #define SL_CONTROL (PORT_BASE + 0x94)
194 #define SL_CONTROL_NOTIFY_EN_OFF 0
195 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
196 #define SL_CONTROL_CTA_OFF 17
197 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
198 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
199 #define RX_BCAST_CHG_OFF 1
200 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
201 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
202 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
203 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
204 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
205 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
206 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
207 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
208 #define TXID_AUTO (PORT_BASE + 0xb8)
209 #define TXID_AUTO_CT3_OFF 1
210 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
211 #define TXID_AUTO_CTB_OFF 11
212 #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
213 #define TX_HARDRST_OFF 2
214 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
215 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
216 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
217 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
218 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
219 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
220 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
221 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
222 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
223 #define CON_CONTROL (PORT_BASE + 0x118)
224 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
225 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
226 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
227 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
228 #define CHL_INT0 (PORT_BASE + 0x1b4)
229 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
230 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
231 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
232 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
233 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
234 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
235 #define CHL_INT0_NOT_RDY_OFF 4
236 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
237 #define CHL_INT0_PHY_RDY_OFF 5
238 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
239 #define CHL_INT1 (PORT_BASE + 0x1b8)
240 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
241 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
242 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
243 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
244 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
245 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
246 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
247 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
248 #define CHL_INT2 (PORT_BASE + 0x1bc)
249 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
250 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
251 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
252 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
253 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
254 #define DMA_TX_DFX0 (PORT_BASE + 0x200)
255 #define DMA_TX_DFX1 (PORT_BASE + 0x204)
256 #define DMA_TX_DFX1_IPTT_OFF 0
257 #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
258 #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
259 #define PORT_DFX0 (PORT_BASE + 0x258)
260 #define LINK_DFX2 (PORT_BASE + 0X264)
261 #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
262 #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
263 #define LINK_DFX2_SEND_HOLD_STS_OFF 10
264 #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
265 #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
266 #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
267 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
268 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
269 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
270 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
271 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
272 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
273 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
274 #define DMA_TX_STATUS_BUSY_OFF 0
275 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
276 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
277 #define DMA_RX_STATUS_BUSY_OFF 0
278 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
279
280 #define AXI_CFG (0x5100)
281 #define AM_CFG_MAX_TRANS (0x5010)
282 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
283
284 #define AXI_MASTER_CFG_BASE (0x5000)
285 #define AM_CTRL_GLOBAL (0x0)
286 #define AM_CURR_TRANS_RETURN (0x150)
287
288 /* HW dma structures */
289 /* Delivery queue header */
290 /* dw0 */
291 #define CMD_HDR_ABORT_FLAG_OFF 0
292 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
293 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
294 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
295 #define CMD_HDR_RESP_REPORT_OFF 5
296 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
297 #define CMD_HDR_TLR_CTRL_OFF 6
298 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
299 #define CMD_HDR_PHY_ID_OFF 8
300 #define CMD_HDR_PHY_ID_MSK (0x1ff << CMD_HDR_PHY_ID_OFF)
301 #define CMD_HDR_FORCE_PHY_OFF 17
302 #define CMD_HDR_FORCE_PHY_MSK (0x1 << CMD_HDR_FORCE_PHY_OFF)
303 #define CMD_HDR_PORT_OFF 18
304 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
305 #define CMD_HDR_PRIORITY_OFF 27
306 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
307 #define CMD_HDR_CMD_OFF 29
308 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
309 /* dw1 */
310 #define CMD_HDR_DIR_OFF 5
311 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
312 #define CMD_HDR_RESET_OFF 7
313 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
314 #define CMD_HDR_VDTL_OFF 10
315 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
316 #define CMD_HDR_FRAME_TYPE_OFF 11
317 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
318 #define CMD_HDR_DEV_ID_OFF 16
319 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
320 /* dw2 */
321 #define CMD_HDR_CFL_OFF 0
322 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
323 #define CMD_HDR_NCQ_TAG_OFF 10
324 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
325 #define CMD_HDR_MRFL_OFF 15
326 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
327 #define CMD_HDR_SG_MOD_OFF 24
328 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
329 #define CMD_HDR_FIRST_BURST_OFF 26
330 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
331 /* dw3 */
332 #define CMD_HDR_IPTT_OFF 0
333 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
334 /* dw6 */
335 #define CMD_HDR_DIF_SGL_LEN_OFF 0
336 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
337 #define CMD_HDR_DATA_SGL_LEN_OFF 16
338 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
339 #define CMD_HDR_ABORT_IPTT_OFF 16
340 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
341
342 /* Completion header */
343 /* dw0 */
344 #define CMPLT_HDR_ERR_PHASE_OFF 2
345 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
346 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
347 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
348 #define CMPLT_HDR_ERX_OFF 12
349 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
350 #define CMPLT_HDR_ABORT_STAT_OFF 13
351 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
352 /* abort_stat */
353 #define STAT_IO_NOT_VALID 0x1
354 #define STAT_IO_NO_DEVICE 0x2
355 #define STAT_IO_COMPLETE 0x3
356 #define STAT_IO_ABORTED 0x4
357 /* dw1 */
358 #define CMPLT_HDR_IPTT_OFF 0
359 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
360 #define CMPLT_HDR_DEV_ID_OFF 16
361 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
362
363 /* ITCT header */
364 /* qw0 */
365 #define ITCT_HDR_DEV_TYPE_OFF 0
366 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
367 #define ITCT_HDR_VALID_OFF 2
368 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
369 #define ITCT_HDR_MCR_OFF 5
370 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
371 #define ITCT_HDR_VLN_OFF 9
372 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
373 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
374 #define ITCT_HDR_SMP_TIMEOUT_8US 1
375 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
376 250) /* 2ms */
377 #define ITCT_HDR_AWT_CONTINUE_OFF 25
378 #define ITCT_HDR_PORT_ID_OFF 28
379 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
380 /* qw2 */
381 #define ITCT_HDR_INLT_OFF 0
382 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
383 #define ITCT_HDR_BITLT_OFF 16
384 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
385 #define ITCT_HDR_MCTLT_OFF 32
386 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
387 #define ITCT_HDR_RTOLT_OFF 48
388 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
389
390 #define HISI_SAS_FATAL_INT_NR 2
391
392 struct hisi_sas_complete_v2_hdr {
393 __le32 dw0;
394 __le32 dw1;
395 __le32 act;
396 __le32 dw3;
397 };
398
399 struct hisi_sas_err_record_v2 {
400 /* dw0 */
401 __le32 trans_tx_fail_type;
402
403 /* dw1 */
404 __le32 trans_rx_fail_type;
405
406 /* dw2 */
407 __le16 dma_tx_err_type;
408 __le16 sipc_rx_err_type;
409
410 /* dw3 */
411 __le32 dma_rx_err_type;
412 };
413
414 struct signal_attenuation_s {
415 u32 de_emphasis;
416 u32 preshoot;
417 u32 boost;
418 };
419
420 struct sig_atten_lu_s {
421 const struct signal_attenuation_s *att;
422 u32 sas_phy_ctrl;
423 };
424
425 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
426 {
427 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
428 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
429 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
430 .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
431 .reg = HGC_DQE_ECC_ADDR,
432 },
433 {
434 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
435 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
436 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
437 .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
438 .reg = HGC_IOST_ECC_ADDR,
439 },
440 {
441 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
442 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
443 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
444 .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
445 .reg = HGC_ITCT_ECC_ADDR,
446 },
447 {
448 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
449 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
450 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
451 .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
452 .reg = HGC_LM_DFX_STATUS2,
453 },
454 {
455 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
456 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
457 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
458 .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
459 .reg = HGC_LM_DFX_STATUS2,
460 },
461 {
462 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
463 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
464 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
465 .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
466 .reg = HGC_CQE_ECC_ADDR,
467 },
468 {
469 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
470 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
471 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
472 .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
473 .reg = HGC_RXM_DFX_STATUS14,
474 },
475 {
476 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
477 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
478 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
479 .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
480 .reg = HGC_RXM_DFX_STATUS14,
481 },
482 {
483 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
484 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
485 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
486 .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
487 .reg = HGC_RXM_DFX_STATUS14,
488 },
489 {
490 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
491 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
492 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
493 .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
494 .reg = HGC_RXM_DFX_STATUS15,
495 },
496 };
497
498 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
499 {
500 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
501 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
502 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
503 .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
504 .reg = HGC_DQE_ECC_ADDR,
505 },
506 {
507 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
508 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
509 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
510 .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
511 .reg = HGC_IOST_ECC_ADDR,
512 },
513 {
514 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
515 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
516 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
517 .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
518 .reg = HGC_ITCT_ECC_ADDR,
519 },
520 {
521 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
522 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
523 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
524 .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
525 .reg = HGC_LM_DFX_STATUS2,
526 },
527 {
528 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
529 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
530 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
531 .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
532 .reg = HGC_LM_DFX_STATUS2,
533 },
534 {
535 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
536 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
537 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
538 .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
539 .reg = HGC_CQE_ECC_ADDR,
540 },
541 {
542 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
543 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
544 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
545 .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
546 .reg = HGC_RXM_DFX_STATUS14,
547 },
548 {
549 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
550 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
551 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
552 .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
553 .reg = HGC_RXM_DFX_STATUS14,
554 },
555 {
556 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
557 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
558 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
559 .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
560 .reg = HGC_RXM_DFX_STATUS14,
561 },
562 {
563 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
564 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
565 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
566 .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
567 .reg = HGC_RXM_DFX_STATUS15,
568 },
569 };
570
571 enum {
572 HISI_SAS_PHY_PHY_UPDOWN,
573 HISI_SAS_PHY_CHNL_INT,
574 HISI_SAS_PHY_INT_NR
575 };
576
577 enum {
578 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
579 TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
580 DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
581 SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
582 DMA_RX_ERR_BASE = 0x60, /* dw3 */
583
584 /* trans tx*/
585 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
586 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
587 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
588 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
589 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
590 RESERVED0, /* 0x5 */
591 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
592 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
593 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
594 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
595 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
596 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
597 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
598 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
599 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
600 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
601 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
602 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
603 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
604 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
605 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
606 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
607 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
608 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
609 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
610 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
611 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
612 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
613 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
614 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
615 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
616 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
617 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
618 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
619 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
620
621 /* trans rx */
622 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
623 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
624 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
625 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
626 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
627 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
628 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
629 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
630 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
631 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
632 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
633 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
634 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
635 RESERVED1, /* 0x2b */
636 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
637 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
638 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
639 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
640 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
641 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
642 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
643 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
644 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
645 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
646 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
647 RESERVED2, /* 0x34 */
648 RESERVED3, /* 0x35 */
649 RESERVED4, /* 0x36 */
650 RESERVED5, /* 0x37 */
651 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
652 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
653 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
654 RESERVED6, /* 0x3b */
655 RESERVED7, /* 0x3c */
656 RESERVED8, /* 0x3d */
657 RESERVED9, /* 0x3e */
658 TRANS_RX_R_ERR, /* 0x3f */
659
660 /* dma tx */
661 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
662 DMA_TX_DIF_APP_ERR, /* 0x41 */
663 DMA_TX_DIF_RPP_ERR, /* 0x42 */
664 DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
665 DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
666 DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
667 DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
668 DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
669 DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
670 DMA_TX_RAM_ECC_ERR, /* 0x49 */
671 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
672 DMA_TX_MAX_ERR_CODE,
673
674 /* sipc rx */
675 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
676 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
677 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
678 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
679 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
680 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
681 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
682 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
683 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
684 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
685 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
686 SIPC_RX_MAX_ERR_CODE,
687
688 /* dma rx */
689 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
690 DMA_RX_DIF_APP_ERR, /* 0x61 */
691 DMA_RX_DIF_RPP_ERR, /* 0x62 */
692 DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
693 DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
694 DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
695 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
696 DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
697 RESERVED10, /* 0x68 */
698 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
699 DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
700 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
701 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
702 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
703 DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
704 DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
705 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
706 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
707 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
708 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
709 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
710 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
711 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
712 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
713 DMA_RX_RAM_ECC_ERR, /* 0x78 */
714 DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
715 DMA_RX_MAX_ERR_CODE,
716 };
717
718 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
719 #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
720
721 #define DIR_NO_DATA 0
722 #define DIR_TO_INI 1
723 #define DIR_TO_DEVICE 2
724 #define DIR_RESERVED 3
725
726 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
727 err_phase == 0x4 || err_phase == 0x8 ||\
728 err_phase == 0x6 || err_phase == 0xa)
729 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
730 err_phase == 0x20 || err_phase == 0x40)
731
732 static void link_timeout_disable_link(struct timer_list *t);
733
734 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
735 {
736 void __iomem *regs = hisi_hba->regs + off;
737
738 return readl(regs);
739 }
740
741 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
742 {
743 void __iomem *regs = hisi_hba->regs + off;
744
745 return readl_relaxed(regs);
746 }
747
748 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
749 {
750 void __iomem *regs = hisi_hba->regs + off;
751
752 writel(val, regs);
753 }
754
755 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
756 u32 off, u32 val)
757 {
758 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
759
760 writel(val, regs);
761 }
762
763 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
764 int phy_no, u32 off)
765 {
766 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
767
768 return readl(regs);
769 }
770
771 /* This function needs to be protected from pre-emption. */
772 static int
773 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
774 struct domain_device *device)
775 {
776 int sata_dev = dev_is_sata(device);
777 void *bitmap = hisi_hba->slot_index_tags;
778 struct hisi_sas_device *sas_dev = device->lldd_dev;
779 int sata_idx = sas_dev->sata_idx;
780 int start, end;
781
782 if (!sata_dev) {
783 /*
784 * STP link SoC bug workaround: index starts from 1.
785 * additionally, we can only allocate odd IPTT(1~4095)
786 * for SAS/SMP device.
787 */
788 start = 1;
789 end = hisi_hba->slot_index_count;
790 } else {
791 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
792 return -EINVAL;
793
794 /*
795 * For SATA device: allocate even IPTT in this interval
796 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
797 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
798 * SoC bug workaround. So we ignore the first 32 even IPTTs.
799 */
800 start = 64 * (sata_idx + 1);
801 end = 64 * (sata_idx + 2);
802 }
803
804 while (1) {
805 start = find_next_zero_bit(bitmap,
806 hisi_hba->slot_index_count, start);
807 if (start >= end)
808 return -SAS_QUEUE_FULL;
809 /*
810 * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
811 */
812 if (sata_dev ^ (start & 1))
813 break;
814 start++;
815 }
816
817 set_bit(start, bitmap);
818 *slot_idx = start;
819 return 0;
820 }
821
822 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
823 {
824 unsigned int index;
825 struct device *dev = hisi_hba->dev;
826 void *bitmap = hisi_hba->sata_dev_bitmap;
827
828 index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
829 if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
830 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
831 return false;
832 }
833
834 set_bit(index, bitmap);
835 *idx = index;
836 return true;
837 }
838
839
840 static struct
841 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
842 {
843 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
844 struct hisi_sas_device *sas_dev = NULL;
845 int i, sata_dev = dev_is_sata(device);
846 int sata_idx = -1;
847 unsigned long flags;
848
849 spin_lock_irqsave(&hisi_hba->lock, flags);
850
851 if (sata_dev)
852 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
853 goto out;
854
855 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
856 /*
857 * SATA device id bit0 should be 0
858 */
859 if (sata_dev && (i & 1))
860 continue;
861 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
862 int queue = i % hisi_hba->queue_count;
863 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
864
865 hisi_hba->devices[i].device_id = i;
866 sas_dev = &hisi_hba->devices[i];
867 sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
868 sas_dev->dev_type = device->dev_type;
869 sas_dev->hisi_hba = hisi_hba;
870 sas_dev->sas_device = device;
871 sas_dev->sata_idx = sata_idx;
872 sas_dev->dq = dq;
873 INIT_LIST_HEAD(&hisi_hba->devices[i].list);
874 break;
875 }
876 }
877
878 out:
879 spin_unlock_irqrestore(&hisi_hba->lock, flags);
880
881 return sas_dev;
882 }
883
884 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
885 {
886 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
887
888 cfg &= ~PHY_CFG_DC_OPT_MSK;
889 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
890 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
891 }
892
893 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
894 {
895 struct sas_identify_frame identify_frame;
896 u32 *identify_buffer;
897
898 memset(&identify_frame, 0, sizeof(identify_frame));
899 identify_frame.dev_type = SAS_END_DEVICE;
900 identify_frame.frame_type = 0;
901 identify_frame._un1 = 1;
902 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
903 identify_frame.target_bits = SAS_PROTOCOL_NONE;
904 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
905 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
906 identify_frame.phy_id = phy_no;
907 identify_buffer = (u32 *)(&identify_frame);
908
909 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
910 __swab32(identify_buffer[0]));
911 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
912 __swab32(identify_buffer[1]));
913 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
914 __swab32(identify_buffer[2]));
915 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
916 __swab32(identify_buffer[3]));
917 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
918 __swab32(identify_buffer[4]));
919 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
920 __swab32(identify_buffer[5]));
921 }
922
923 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
924 struct hisi_sas_device *sas_dev)
925 {
926 struct domain_device *device = sas_dev->sas_device;
927 struct device *dev = hisi_hba->dev;
928 u64 qw0, device_id = sas_dev->device_id;
929 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
930 struct domain_device *parent_dev = device->parent;
931 struct asd_sas_port *sas_port = device->port;
932 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
933
934 memset(itct, 0, sizeof(*itct));
935
936 /* qw0 */
937 qw0 = 0;
938 switch (sas_dev->dev_type) {
939 case SAS_END_DEVICE:
940 case SAS_EDGE_EXPANDER_DEVICE:
941 case SAS_FANOUT_EXPANDER_DEVICE:
942 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
943 break;
944 case SAS_SATA_DEV:
945 case SAS_SATA_PENDING:
946 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
947 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
948 else
949 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
950 break;
951 default:
952 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
953 sas_dev->dev_type);
954 }
955
956 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
957 (device->linkrate << ITCT_HDR_MCR_OFF) |
958 (1 << ITCT_HDR_VLN_OFF) |
959 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
960 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
961 (port->id << ITCT_HDR_PORT_ID_OFF));
962 itct->qw0 = cpu_to_le64(qw0);
963
964 /* qw1 */
965 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
966 itct->sas_addr = __swab64(itct->sas_addr);
967
968 /* qw2 */
969 if (!dev_is_sata(device))
970 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
971 (0x1ULL << ITCT_HDR_BITLT_OFF) |
972 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
973 (0x1ULL << ITCT_HDR_RTOLT_OFF));
974 }
975
976 static void clear_itct_v2_hw(struct hisi_hba *hisi_hba,
977 struct hisi_sas_device *sas_dev)
978 {
979 DECLARE_COMPLETION_ONSTACK(completion);
980 u64 dev_id = sas_dev->device_id;
981 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
982 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
983 int i;
984
985 sas_dev->completion = &completion;
986
987 /* clear the itct interrupt state */
988 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
989 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
990 ENT_INT_SRC3_ITC_INT_MSK);
991
992 for (i = 0; i < 2; i++) {
993 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
994 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
995 wait_for_completion(sas_dev->completion);
996
997 memset(itct, 0, sizeof(struct hisi_sas_itct));
998 }
999 }
1000
1001 static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
1002 {
1003 struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
1004
1005 /* SoC bug workaround */
1006 if (dev_is_sata(sas_dev->sas_device))
1007 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
1008 }
1009
1010 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
1011 {
1012 int i, reset_val;
1013 u32 val;
1014 unsigned long end_time;
1015 struct device *dev = hisi_hba->dev;
1016
1017 /* The mask needs to be set depending on the number of phys */
1018 if (hisi_hba->n_phy == 9)
1019 reset_val = 0x1fffff;
1020 else
1021 reset_val = 0x7ffff;
1022
1023 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1024
1025 /* Disable all of the PHYs */
1026 for (i = 0; i < hisi_hba->n_phy; i++) {
1027 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1028
1029 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1030 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1031 }
1032 udelay(50);
1033
1034 /* Ensure DMA tx & rx idle */
1035 for (i = 0; i < hisi_hba->n_phy; i++) {
1036 u32 dma_tx_status, dma_rx_status;
1037
1038 end_time = jiffies + msecs_to_jiffies(1000);
1039
1040 while (1) {
1041 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1042 DMA_TX_STATUS);
1043 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1044 DMA_RX_STATUS);
1045
1046 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1047 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1048 break;
1049
1050 msleep(20);
1051 if (time_after(jiffies, end_time))
1052 return -EIO;
1053 }
1054 }
1055
1056 /* Ensure axi bus idle */
1057 end_time = jiffies + msecs_to_jiffies(1000);
1058 while (1) {
1059 u32 axi_status =
1060 hisi_sas_read32(hisi_hba, AXI_CFG);
1061
1062 if (axi_status == 0)
1063 break;
1064
1065 msleep(20);
1066 if (time_after(jiffies, end_time))
1067 return -EIO;
1068 }
1069
1070 if (ACPI_HANDLE(dev)) {
1071 acpi_status s;
1072
1073 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1074 if (ACPI_FAILURE(s)) {
1075 dev_err(dev, "Reset failed\n");
1076 return -EIO;
1077 }
1078 } else if (hisi_hba->ctrl) {
1079 /* reset and disable clock*/
1080 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1081 reset_val);
1082 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1083 reset_val);
1084 msleep(1);
1085 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1086 if (reset_val != (val & reset_val)) {
1087 dev_err(dev, "SAS reset fail.\n");
1088 return -EIO;
1089 }
1090
1091 /* De-reset and enable clock*/
1092 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1093 reset_val);
1094 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1095 reset_val);
1096 msleep(1);
1097 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1098 &val);
1099 if (val & reset_val) {
1100 dev_err(dev, "SAS de-reset fail.\n");
1101 return -EIO;
1102 }
1103 } else {
1104 dev_err(dev, "no reset method\n");
1105 return -EINVAL;
1106 }
1107
1108 return 0;
1109 }
1110
1111 /* This function needs to be called after resetting SAS controller. */
1112 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1113 {
1114 u32 cfg;
1115 int phy_no;
1116
1117 hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1118 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1119 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1120 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1121 continue;
1122
1123 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1124 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1125 }
1126 }
1127
1128 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1129 {
1130 int phy_no;
1131 u32 dma_tx_dfx1;
1132
1133 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1134 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1135 continue;
1136
1137 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1138 DMA_TX_DFX1);
1139 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1140 u32 cfg = hisi_sas_phy_read32(hisi_hba,
1141 phy_no, CON_CONTROL);
1142
1143 cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1144 hisi_sas_phy_write32(hisi_hba, phy_no,
1145 CON_CONTROL, cfg);
1146 clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1147 }
1148 }
1149 }
1150
1151 static const struct signal_attenuation_s x6000 = {9200, 0, 10476};
1152 static const struct sig_atten_lu_s sig_atten_lu[] = {
1153 { &x6000, 0x3016a68 },
1154 };
1155
1156 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1157 {
1158 struct device *dev = hisi_hba->dev;
1159 u32 sas_phy_ctrl = 0x30b9908;
1160 u32 signal[3];
1161 int i;
1162
1163 /* Global registers init */
1164
1165 /* Deal with am-max-transmissions quirk */
1166 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1167 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1168 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1169 0x2020);
1170 } /* Else, use defaults -> do nothing */
1171
1172 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1173 (u32)((1ULL << hisi_hba->queue_count) - 1));
1174 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1175 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1176 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1177 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1178 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1179 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1180 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1181 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1182 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1183 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1184 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1185 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1186 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1187 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1188 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1189 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1190 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1191 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1192 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1193 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1194 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1195 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1196 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1197 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1198 for (i = 0; i < hisi_hba->queue_count; i++)
1199 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1200
1201 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1202 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1203
1204 /* Get sas_phy_ctrl value to deal with TX FFE issue. */
1205 if (!device_property_read_u32_array(dev, "hisilicon,signal-attenuation",
1206 signal, ARRAY_SIZE(signal))) {
1207 for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) {
1208 const struct sig_atten_lu_s *lookup = &sig_atten_lu[i];
1209 const struct signal_attenuation_s *att = lookup->att;
1210
1211 if ((signal[0] == att->de_emphasis) &&
1212 (signal[1] == att->preshoot) &&
1213 (signal[2] == att->boost)) {
1214 sas_phy_ctrl = lookup->sas_phy_ctrl;
1215 break;
1216 }
1217 }
1218
1219 if (i == ARRAY_SIZE(sig_atten_lu))
1220 dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n");
1221 }
1222
1223 for (i = 0; i < hisi_hba->n_phy; i++) {
1224 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1225 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1226 u32 prog_phy_link_rate = 0x800;
1227
1228 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
1229 SAS_LINK_RATE_1_5_GBPS)) {
1230 prog_phy_link_rate = 0x855;
1231 } else {
1232 enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
1233
1234 prog_phy_link_rate =
1235 hisi_sas_get_prog_phy_linkrate_mask(max) |
1236 0x800;
1237 }
1238 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
1239 prog_phy_link_rate);
1240 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl);
1241 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1242 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1243 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1244 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1245 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1246 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1247 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1248 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1249 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff);
1250 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbfe);
1251 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1252 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1253 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1254 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1255 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1256 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1257 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1258 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1259 if (hisi_hba->refclk_frequency_mhz == 66)
1260 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1261 /* else, do nothing -> leave it how you found it */
1262 }
1263
1264 for (i = 0; i < hisi_hba->queue_count; i++) {
1265 /* Delivery queue */
1266 hisi_sas_write32(hisi_hba,
1267 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1268 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1269
1270 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1271 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1272
1273 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1274 HISI_SAS_QUEUE_SLOTS);
1275
1276 /* Completion queue */
1277 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1278 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1279
1280 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1281 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1282
1283 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1284 HISI_SAS_QUEUE_SLOTS);
1285 }
1286
1287 /* itct */
1288 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1289 lower_32_bits(hisi_hba->itct_dma));
1290
1291 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1292 upper_32_bits(hisi_hba->itct_dma));
1293
1294 /* iost */
1295 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1296 lower_32_bits(hisi_hba->iost_dma));
1297
1298 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1299 upper_32_bits(hisi_hba->iost_dma));
1300
1301 /* breakpoint */
1302 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1303 lower_32_bits(hisi_hba->breakpoint_dma));
1304
1305 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1306 upper_32_bits(hisi_hba->breakpoint_dma));
1307
1308 /* SATA broken msg */
1309 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1310 lower_32_bits(hisi_hba->sata_breakpoint_dma));
1311
1312 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1313 upper_32_bits(hisi_hba->sata_breakpoint_dma));
1314
1315 /* SATA initial fis */
1316 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1317 lower_32_bits(hisi_hba->initial_fis_dma));
1318
1319 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1320 upper_32_bits(hisi_hba->initial_fis_dma));
1321 }
1322
1323 static void link_timeout_enable_link(struct timer_list *t)
1324 {
1325 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1326 int i, reg_val;
1327
1328 for (i = 0; i < hisi_hba->n_phy; i++) {
1329 if (hisi_hba->reject_stp_links_msk & BIT(i))
1330 continue;
1331
1332 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1333 if (!(reg_val & BIT(0))) {
1334 hisi_sas_phy_write32(hisi_hba, i,
1335 CON_CONTROL, 0x7);
1336 break;
1337 }
1338 }
1339
1340 hisi_hba->timer.function = link_timeout_disable_link;
1341 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1342 }
1343
1344 static void link_timeout_disable_link(struct timer_list *t)
1345 {
1346 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1347 int i, reg_val;
1348
1349 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1350 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1351 if (hisi_hba->reject_stp_links_msk & BIT(i))
1352 continue;
1353
1354 if (reg_val & BIT(i)) {
1355 hisi_sas_phy_write32(hisi_hba, i,
1356 CON_CONTROL, 0x6);
1357 break;
1358 }
1359 }
1360
1361 hisi_hba->timer.function = link_timeout_enable_link;
1362 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1363 }
1364
1365 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1366 {
1367 hisi_hba->timer.function = link_timeout_disable_link;
1368 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1369 add_timer(&hisi_hba->timer);
1370 }
1371
1372 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1373 {
1374 struct device *dev = hisi_hba->dev;
1375 int rc;
1376
1377 rc = reset_hw_v2_hw(hisi_hba);
1378 if (rc) {
1379 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1380 return rc;
1381 }
1382
1383 msleep(100);
1384 init_reg_v2_hw(hisi_hba);
1385
1386 return 0;
1387 }
1388
1389 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1390 {
1391 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1392
1393 cfg |= PHY_CFG_ENA_MSK;
1394 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1395 }
1396
1397 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1398 {
1399 u32 context;
1400
1401 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1402 if (context & (1 << phy_no))
1403 return true;
1404
1405 return false;
1406 }
1407
1408 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1409 {
1410 u32 dfx_val;
1411
1412 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1413
1414 if (dfx_val & BIT(16))
1415 return false;
1416
1417 return true;
1418 }
1419
1420 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1421 {
1422 int i, max_loop = 1000;
1423 struct device *dev = hisi_hba->dev;
1424 u32 status, axi_status, dfx_val, dfx_tx_val;
1425
1426 for (i = 0; i < max_loop; i++) {
1427 status = hisi_sas_read32_relaxed(hisi_hba,
1428 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1429
1430 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1431 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1432 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1433 phy_no, DMA_TX_FIFO_DFX0);
1434
1435 if ((status == 0x3) && (axi_status == 0x0) &&
1436 (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1437 return true;
1438 udelay(10);
1439 }
1440 dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1441 phy_no, status, axi_status,
1442 dfx_val, dfx_tx_val);
1443 return false;
1444 }
1445
1446 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1447 {
1448 int i, max_loop = 1000;
1449 struct device *dev = hisi_hba->dev;
1450 u32 status, tx_dfx0;
1451
1452 for (i = 0; i < max_loop; i++) {
1453 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1454 status = (status & 0x3fc0) >> 6;
1455
1456 if (status != 0x1)
1457 return true;
1458
1459 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1460 if ((tx_dfx0 & 0x1ff) == 0x2)
1461 return true;
1462 udelay(10);
1463 }
1464 dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1465 phy_no, status, tx_dfx0);
1466 return false;
1467 }
1468
1469 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1470 {
1471 if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1472 return true;
1473
1474 if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1475 return false;
1476
1477 if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1478 return false;
1479
1480 return true;
1481 }
1482
1483
1484 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1485 {
1486 u32 cfg, axi_val, dfx0_val, txid_auto;
1487 struct device *dev = hisi_hba->dev;
1488
1489 /* Close axi bus. */
1490 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1491 AM_CTRL_GLOBAL);
1492 axi_val |= 0x1;
1493 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1494 AM_CTRL_GLOBAL, axi_val);
1495
1496 if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1497 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1498 goto do_disable;
1499
1500 /* Reset host controller. */
1501 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1502 return;
1503 }
1504
1505 dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1506 dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1507 if (dfx0_val != 0x4)
1508 goto do_disable;
1509
1510 if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1511 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1512 phy_no);
1513 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1514 TXID_AUTO);
1515 txid_auto |= TXID_AUTO_CTB_MSK;
1516 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1517 txid_auto);
1518 }
1519
1520 do_disable:
1521 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1522 cfg &= ~PHY_CFG_ENA_MSK;
1523 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1524
1525 /* Open axi bus. */
1526 axi_val &= ~0x1;
1527 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1528 AM_CTRL_GLOBAL, axi_val);
1529 }
1530
1531 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1532 {
1533 config_id_frame_v2_hw(hisi_hba, phy_no);
1534 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1535 enable_phy_v2_hw(hisi_hba, phy_no);
1536 }
1537
1538 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1539 {
1540 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1541 u32 txid_auto;
1542
1543 disable_phy_v2_hw(hisi_hba, phy_no);
1544 if (phy->identify.device_type == SAS_END_DEVICE) {
1545 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1546 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1547 txid_auto | TX_HARDRST_MSK);
1548 }
1549 msleep(100);
1550 start_phy_v2_hw(hisi_hba, phy_no);
1551 }
1552
1553 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1554 {
1555 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1556 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1557 struct sas_phy *sphy = sas_phy->phy;
1558 u32 err4_reg_val, err6_reg_val;
1559
1560 /* loss dword syn, phy reset problem */
1561 err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1562
1563 /* disparity err, invalid dword */
1564 err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1565
1566 sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1567 sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1568 sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1569 sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1570 }
1571
1572 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1573 {
1574 int i;
1575
1576 for (i = 0; i < hisi_hba->n_phy; i++) {
1577 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1578 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1579
1580 if (!sas_phy->phy->enabled)
1581 continue;
1582
1583 start_phy_v2_hw(hisi_hba, i);
1584 }
1585 }
1586
1587 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1588 {
1589 u32 sl_control;
1590
1591 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1592 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1593 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1594 msleep(1);
1595 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1596 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1597 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1598 }
1599
1600 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1601 {
1602 return SAS_LINK_RATE_12_0_GBPS;
1603 }
1604
1605 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1606 struct sas_phy_linkrates *r)
1607 {
1608 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1609 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1610 enum sas_linkrate min, max;
1611 u32 prog_phy_link_rate = 0x800;
1612
1613 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1614 max = sas_phy->phy->maximum_linkrate;
1615 min = r->minimum_linkrate;
1616 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1617 max = r->maximum_linkrate;
1618 min = sas_phy->phy->minimum_linkrate;
1619 } else
1620 return;
1621
1622 sas_phy->phy->maximum_linkrate = max;
1623 sas_phy->phy->minimum_linkrate = min;
1624 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
1625
1626 disable_phy_v2_hw(hisi_hba, phy_no);
1627 msleep(100);
1628 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1629 prog_phy_link_rate);
1630 start_phy_v2_hw(hisi_hba, phy_no);
1631 }
1632
1633 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1634 {
1635 int i, bitmap = 0;
1636 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1637 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1638
1639 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1640 if (phy_state & 1 << i)
1641 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1642 bitmap |= 1 << i;
1643
1644 if (hisi_hba->n_phy == 9) {
1645 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1646
1647 if (phy_state & 1 << 8)
1648 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1649 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1650 bitmap |= 1 << 9;
1651 }
1652
1653 return bitmap;
1654 }
1655
1656 /*
1657 * The callpath to this function and upto writing the write
1658 * queue pointer should be safe from interruption.
1659 */
1660 static int
1661 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1662 {
1663 struct device *dev = hisi_hba->dev;
1664 int queue = dq->id;
1665 u32 r, w;
1666
1667 w = dq->wr_point;
1668 r = hisi_sas_read32_relaxed(hisi_hba,
1669 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1670 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1671 dev_warn(dev, "full queue=%d r=%d w=%d\n",
1672 queue, r, w);
1673 return -EAGAIN;
1674 }
1675
1676 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
1677
1678 return w;
1679 }
1680
1681 /* DQ lock must be taken here */
1682 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1683 {
1684 struct hisi_hba *hisi_hba = dq->hisi_hba;
1685 struct hisi_sas_slot *s, *s1;
1686 struct list_head *dq_list;
1687 int dlvry_queue = dq->id;
1688 int wp, count = 0;
1689
1690 dq_list = &dq->list;
1691 list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1692 if (!s->ready)
1693 break;
1694 count++;
1695 wp = (s->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1696 list_del(&s->delivery);
1697 }
1698
1699 if (!count)
1700 return;
1701
1702 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1703 }
1704
1705 static void prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1706 struct hisi_sas_slot *slot,
1707 struct hisi_sas_cmd_hdr *hdr,
1708 struct scatterlist *scatter,
1709 int n_elem)
1710 {
1711 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1712 struct scatterlist *sg;
1713 int i;
1714
1715 for_each_sg(scatter, sg, n_elem, i) {
1716 struct hisi_sas_sge *entry = &sge_page->sge[i];
1717
1718 entry->addr = cpu_to_le64(sg_dma_address(sg));
1719 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1720 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1721 entry->data_off = 0;
1722 }
1723
1724 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1725
1726 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1727 }
1728
1729 static void prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1730 struct hisi_sas_slot *slot)
1731 {
1732 struct sas_task *task = slot->task;
1733 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1734 struct domain_device *device = task->dev;
1735 struct hisi_sas_port *port = slot->port;
1736 struct scatterlist *sg_req;
1737 struct hisi_sas_device *sas_dev = device->lldd_dev;
1738 dma_addr_t req_dma_addr;
1739 unsigned int req_len;
1740
1741 /* req */
1742 sg_req = &task->smp_task.smp_req;
1743 req_dma_addr = sg_dma_address(sg_req);
1744 req_len = sg_dma_len(&task->smp_task.smp_req);
1745
1746 /* create header */
1747 /* dw0 */
1748 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1749 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1750 (2 << CMD_HDR_CMD_OFF)); /* smp */
1751
1752 /* map itct entry */
1753 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1754 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1755 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1756
1757 /* dw2 */
1758 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1759 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1760 CMD_HDR_MRFL_OFF));
1761
1762 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1763
1764 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1765 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1766 }
1767
1768 static void prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1769 struct hisi_sas_slot *slot)
1770 {
1771 struct sas_task *task = slot->task;
1772 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1773 struct domain_device *device = task->dev;
1774 struct hisi_sas_device *sas_dev = device->lldd_dev;
1775 struct hisi_sas_port *port = slot->port;
1776 struct sas_ssp_task *ssp_task = &task->ssp_task;
1777 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1778 struct hisi_sas_tmf_task *tmf = slot->tmf;
1779 int has_data = 0, priority = !!tmf;
1780 u8 *buf_cmd;
1781 u32 dw1 = 0, dw2 = 0;
1782
1783 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1784 (2 << CMD_HDR_TLR_CTRL_OFF) |
1785 (port->id << CMD_HDR_PORT_OFF) |
1786 (priority << CMD_HDR_PRIORITY_OFF) |
1787 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1788
1789 dw1 = 1 << CMD_HDR_VDTL_OFF;
1790 if (tmf) {
1791 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1792 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1793 } else {
1794 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1795 switch (scsi_cmnd->sc_data_direction) {
1796 case DMA_TO_DEVICE:
1797 has_data = 1;
1798 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1799 break;
1800 case DMA_FROM_DEVICE:
1801 has_data = 1;
1802 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1803 break;
1804 default:
1805 dw1 &= ~CMD_HDR_DIR_MSK;
1806 }
1807 }
1808
1809 /* map itct entry */
1810 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1811 hdr->dw1 = cpu_to_le32(dw1);
1812
1813 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1814 + 3) / 4) << CMD_HDR_CFL_OFF) |
1815 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1816 (2 << CMD_HDR_SG_MOD_OFF);
1817 hdr->dw2 = cpu_to_le32(dw2);
1818
1819 hdr->transfer_tags = cpu_to_le32(slot->idx);
1820
1821 if (has_data)
1822 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1823 slot->n_elem);
1824
1825 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1826 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1827 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1828
1829 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1830 sizeof(struct ssp_frame_hdr);
1831
1832 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1833 if (!tmf) {
1834 buf_cmd[9] = task->ssp_task.task_attr |
1835 (task->ssp_task.task_prio << 3);
1836 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1837 task->ssp_task.cmd->cmd_len);
1838 } else {
1839 buf_cmd[10] = tmf->tmf;
1840 switch (tmf->tmf) {
1841 case TMF_ABORT_TASK:
1842 case TMF_QUERY_TASK:
1843 buf_cmd[12] =
1844 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1845 buf_cmd[13] =
1846 tmf->tag_of_task_to_be_managed & 0xff;
1847 break;
1848 default:
1849 break;
1850 }
1851 }
1852 }
1853
1854 #define TRANS_TX_ERR 0
1855 #define TRANS_RX_ERR 1
1856 #define DMA_TX_ERR 2
1857 #define SIPC_RX_ERR 3
1858 #define DMA_RX_ERR 4
1859
1860 #define DMA_TX_ERR_OFF 0
1861 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1862 #define SIPC_RX_ERR_OFF 16
1863 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1864
1865 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1866 {
1867 static const u8 trans_tx_err_code_prio[] = {
1868 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1869 TRANS_TX_ERR_PHY_NOT_ENABLE,
1870 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1871 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1872 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1873 RESERVED0,
1874 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1875 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1876 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1877 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1878 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1879 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1880 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1881 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1882 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1883 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1884 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1885 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1886 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1887 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1888 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1889 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1890 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1891 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1892 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1893 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1894 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1895 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1896 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1897 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1898 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1899 };
1900 int index, i;
1901
1902 for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1903 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1904 if (err_msk & (1 << index))
1905 return trans_tx_err_code_prio[i];
1906 }
1907 return -1;
1908 }
1909
1910 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1911 {
1912 static const u8 trans_rx_err_code_prio[] = {
1913 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1914 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1915 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1916 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1917 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1918 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1919 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1920 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1921 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1922 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1923 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1924 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1925 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1926 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1927 RESERVED1,
1928 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1929 TRANS_RX_ERR_WITH_DATA_LEN0,
1930 TRANS_RX_ERR_WITH_BAD_HASH,
1931 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1932 TRANS_RX_SSP_FRM_LEN_ERR,
1933 RESERVED2,
1934 RESERVED3,
1935 RESERVED4,
1936 RESERVED5,
1937 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1938 TRANS_RX_SMP_FRM_LEN_ERR,
1939 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1940 RESERVED6,
1941 RESERVED7,
1942 RESERVED8,
1943 RESERVED9,
1944 TRANS_RX_R_ERR,
1945 };
1946 int index, i;
1947
1948 for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1949 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1950 if (err_msk & (1 << index))
1951 return trans_rx_err_code_prio[i];
1952 }
1953 return -1;
1954 }
1955
1956 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1957 {
1958 static const u8 dma_tx_err_code_prio[] = {
1959 DMA_TX_UNEXP_XFER_ERR,
1960 DMA_TX_UNEXP_RETRANS_ERR,
1961 DMA_TX_XFER_LEN_OVERFLOW,
1962 DMA_TX_XFER_OFFSET_ERR,
1963 DMA_TX_RAM_ECC_ERR,
1964 DMA_TX_DIF_LEN_ALIGN_ERR,
1965 DMA_TX_DIF_CRC_ERR,
1966 DMA_TX_DIF_APP_ERR,
1967 DMA_TX_DIF_RPP_ERR,
1968 DMA_TX_DATA_SGL_OVERFLOW,
1969 DMA_TX_DIF_SGL_OVERFLOW,
1970 };
1971 int index, i;
1972
1973 for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1974 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1975 err_msk = err_msk & DMA_TX_ERR_MSK;
1976 if (err_msk & (1 << index))
1977 return dma_tx_err_code_prio[i];
1978 }
1979 return -1;
1980 }
1981
1982 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1983 {
1984 static const u8 sipc_rx_err_code_prio[] = {
1985 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1986 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1987 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1988 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1989 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1990 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1991 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1992 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1993 SIPC_RX_SATA_UNEXP_FIS_ERR,
1994 SIPC_RX_WRSETUP_ESTATUS_ERR,
1995 SIPC_RX_DATA_UNDERFLOW_ERR,
1996 };
1997 int index, i;
1998
1999 for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
2000 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
2001 err_msk = err_msk & SIPC_RX_ERR_MSK;
2002 if (err_msk & (1 << (index + 0x10)))
2003 return sipc_rx_err_code_prio[i];
2004 }
2005 return -1;
2006 }
2007
2008 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
2009 {
2010 static const u8 dma_rx_err_code_prio[] = {
2011 DMA_RX_UNKNOWN_FRM_ERR,
2012 DMA_RX_DATA_LEN_OVERFLOW,
2013 DMA_RX_DATA_LEN_UNDERFLOW,
2014 DMA_RX_DATA_OFFSET_ERR,
2015 RESERVED10,
2016 DMA_RX_SATA_FRAME_TYPE_ERR,
2017 DMA_RX_RESP_BUF_OVERFLOW,
2018 DMA_RX_UNEXP_RETRANS_RESP_ERR,
2019 DMA_RX_UNEXP_NORM_RESP_ERR,
2020 DMA_RX_UNEXP_RDFRAME_ERR,
2021 DMA_RX_PIO_DATA_LEN_ERR,
2022 DMA_RX_RDSETUP_STATUS_ERR,
2023 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2024 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2025 DMA_RX_RDSETUP_LEN_ODD_ERR,
2026 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2027 DMA_RX_RDSETUP_LEN_OVER_ERR,
2028 DMA_RX_RDSETUP_OFFSET_ERR,
2029 DMA_RX_RDSETUP_ACTIVE_ERR,
2030 DMA_RX_RDSETUP_ESTATUS_ERR,
2031 DMA_RX_RAM_ECC_ERR,
2032 DMA_RX_DIF_CRC_ERR,
2033 DMA_RX_DIF_APP_ERR,
2034 DMA_RX_DIF_RPP_ERR,
2035 DMA_RX_DATA_SGL_OVERFLOW,
2036 DMA_RX_DIF_SGL_OVERFLOW,
2037 };
2038 int index, i;
2039
2040 for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2041 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2042 if (err_msk & (1 << index))
2043 return dma_rx_err_code_prio[i];
2044 }
2045 return -1;
2046 }
2047
2048 /* by default, task resp is complete */
2049 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2050 struct sas_task *task,
2051 struct hisi_sas_slot *slot,
2052 int err_phase)
2053 {
2054 struct task_status_struct *ts = &task->task_status;
2055 struct hisi_sas_err_record_v2 *err_record =
2056 hisi_sas_status_buf_addr_mem(slot);
2057 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2058 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2059 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2060 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2061 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2062 int error = -1;
2063
2064 if (err_phase == 1) {
2065 /* error in TX phase, the priority of error is: DW2 > DW0 */
2066 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2067 if (error == -1)
2068 error = parse_trans_tx_err_code_v2_hw(
2069 trans_tx_fail_type);
2070 } else if (err_phase == 2) {
2071 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2072 error = parse_trans_rx_err_code_v2_hw(
2073 trans_rx_fail_type);
2074 if (error == -1) {
2075 error = parse_dma_rx_err_code_v2_hw(
2076 dma_rx_err_type);
2077 if (error == -1)
2078 error = parse_sipc_rx_err_code_v2_hw(
2079 sipc_rx_err_type);
2080 }
2081 }
2082
2083 switch (task->task_proto) {
2084 case SAS_PROTOCOL_SSP:
2085 {
2086 switch (error) {
2087 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2088 {
2089 ts->stat = SAS_OPEN_REJECT;
2090 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2091 break;
2092 }
2093 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2094 {
2095 ts->stat = SAS_OPEN_REJECT;
2096 ts->open_rej_reason = SAS_OREJ_EPROTO;
2097 break;
2098 }
2099 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2100 {
2101 ts->stat = SAS_OPEN_REJECT;
2102 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2103 break;
2104 }
2105 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2106 {
2107 ts->stat = SAS_OPEN_REJECT;
2108 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2109 break;
2110 }
2111 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2112 {
2113 ts->stat = SAS_OPEN_REJECT;
2114 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2115 break;
2116 }
2117 case DMA_RX_UNEXP_NORM_RESP_ERR:
2118 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2119 case DMA_RX_RESP_BUF_OVERFLOW:
2120 {
2121 ts->stat = SAS_OPEN_REJECT;
2122 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2123 break;
2124 }
2125 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2126 {
2127 /* not sure */
2128 ts->stat = SAS_DEV_NO_RESPONSE;
2129 break;
2130 }
2131 case DMA_RX_DATA_LEN_OVERFLOW:
2132 {
2133 ts->stat = SAS_DATA_OVERRUN;
2134 ts->residual = 0;
2135 break;
2136 }
2137 case DMA_RX_DATA_LEN_UNDERFLOW:
2138 {
2139 ts->residual = trans_tx_fail_type;
2140 ts->stat = SAS_DATA_UNDERRUN;
2141 break;
2142 }
2143 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2144 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2145 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2146 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2147 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2148 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2149 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2150 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2151 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2152 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2153 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2154 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2155 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2156 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2157 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2158 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2159 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2160 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2161 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2162 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2163 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2164 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2165 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2166 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2167 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2168 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2169 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2170 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2171 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2172 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2173 case TRANS_TX_ERR_FRAME_TXED:
2174 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2175 case TRANS_RX_ERR_WITH_DATA_LEN0:
2176 case TRANS_RX_ERR_WITH_BAD_HASH:
2177 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2178 case TRANS_RX_SSP_FRM_LEN_ERR:
2179 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2180 case DMA_TX_DATA_SGL_OVERFLOW:
2181 case DMA_TX_UNEXP_XFER_ERR:
2182 case DMA_TX_UNEXP_RETRANS_ERR:
2183 case DMA_TX_XFER_LEN_OVERFLOW:
2184 case DMA_TX_XFER_OFFSET_ERR:
2185 case SIPC_RX_DATA_UNDERFLOW_ERR:
2186 case DMA_RX_DATA_SGL_OVERFLOW:
2187 case DMA_RX_DATA_OFFSET_ERR:
2188 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2189 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2190 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2191 case DMA_RX_SATA_FRAME_TYPE_ERR:
2192 case DMA_RX_UNKNOWN_FRM_ERR:
2193 {
2194 /* This will request a retry */
2195 ts->stat = SAS_QUEUE_FULL;
2196 slot->abort = 1;
2197 break;
2198 }
2199 default:
2200 break;
2201 }
2202 }
2203 break;
2204 case SAS_PROTOCOL_SMP:
2205 ts->stat = SAM_STAT_CHECK_CONDITION;
2206 break;
2207
2208 case SAS_PROTOCOL_SATA:
2209 case SAS_PROTOCOL_STP:
2210 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2211 {
2212 switch (error) {
2213 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2214 {
2215 ts->stat = SAS_OPEN_REJECT;
2216 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2217 break;
2218 }
2219 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2220 {
2221 ts->resp = SAS_TASK_UNDELIVERED;
2222 ts->stat = SAS_DEV_NO_RESPONSE;
2223 break;
2224 }
2225 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2226 {
2227 ts->stat = SAS_OPEN_REJECT;
2228 ts->open_rej_reason = SAS_OREJ_EPROTO;
2229 break;
2230 }
2231 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2232 {
2233 ts->stat = SAS_OPEN_REJECT;
2234 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2235 break;
2236 }
2237 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2238 {
2239 ts->stat = SAS_OPEN_REJECT;
2240 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2241 break;
2242 }
2243 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2244 {
2245 ts->stat = SAS_OPEN_REJECT;
2246 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2247 break;
2248 }
2249 case DMA_RX_RESP_BUF_OVERFLOW:
2250 case DMA_RX_UNEXP_NORM_RESP_ERR:
2251 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2252 {
2253 ts->stat = SAS_OPEN_REJECT;
2254 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2255 break;
2256 }
2257 case DMA_RX_DATA_LEN_OVERFLOW:
2258 {
2259 ts->stat = SAS_DATA_OVERRUN;
2260 ts->residual = 0;
2261 break;
2262 }
2263 case DMA_RX_DATA_LEN_UNDERFLOW:
2264 {
2265 ts->residual = trans_tx_fail_type;
2266 ts->stat = SAS_DATA_UNDERRUN;
2267 break;
2268 }
2269 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2270 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2271 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2272 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2273 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2274 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2275 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2276 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2277 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2278 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2279 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2280 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2281 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2282 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2283 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2284 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2285 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2286 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2287 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2288 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2289 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2290 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2291 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2292 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2293 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2294 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2295 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2296 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2297 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2298 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2299 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2300 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2301 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2302 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2303 case TRANS_RX_ERR_WITH_DATA_LEN0:
2304 case TRANS_RX_ERR_WITH_BAD_HASH:
2305 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2306 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2307 case DMA_TX_DATA_SGL_OVERFLOW:
2308 case DMA_TX_UNEXP_XFER_ERR:
2309 case DMA_TX_UNEXP_RETRANS_ERR:
2310 case DMA_TX_XFER_LEN_OVERFLOW:
2311 case DMA_TX_XFER_OFFSET_ERR:
2312 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2313 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2314 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2315 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2316 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2317 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2318 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2319 case DMA_RX_DATA_SGL_OVERFLOW:
2320 case DMA_RX_DATA_OFFSET_ERR:
2321 case DMA_RX_SATA_FRAME_TYPE_ERR:
2322 case DMA_RX_UNEXP_RDFRAME_ERR:
2323 case DMA_RX_PIO_DATA_LEN_ERR:
2324 case DMA_RX_RDSETUP_STATUS_ERR:
2325 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2326 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2327 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2328 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2329 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2330 case DMA_RX_RDSETUP_OFFSET_ERR:
2331 case DMA_RX_RDSETUP_ACTIVE_ERR:
2332 case DMA_RX_RDSETUP_ESTATUS_ERR:
2333 case DMA_RX_UNKNOWN_FRM_ERR:
2334 case TRANS_RX_SSP_FRM_LEN_ERR:
2335 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2336 {
2337 slot->abort = 1;
2338 ts->stat = SAS_PHY_DOWN;
2339 break;
2340 }
2341 default:
2342 {
2343 ts->stat = SAS_PROTO_RESPONSE;
2344 break;
2345 }
2346 }
2347 hisi_sas_sata_done(task, slot);
2348 }
2349 break;
2350 default:
2351 break;
2352 }
2353 }
2354
2355 static int
2356 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2357 {
2358 struct sas_task *task = slot->task;
2359 struct hisi_sas_device *sas_dev;
2360 struct device *dev = hisi_hba->dev;
2361 struct task_status_struct *ts;
2362 struct domain_device *device;
2363 struct sas_ha_struct *ha;
2364 enum exec_status sts;
2365 struct hisi_sas_complete_v2_hdr *complete_queue =
2366 hisi_hba->complete_hdr[slot->cmplt_queue];
2367 struct hisi_sas_complete_v2_hdr *complete_hdr =
2368 &complete_queue[slot->cmplt_queue_slot];
2369 unsigned long flags;
2370 bool is_internal = slot->is_internal;
2371
2372 if (unlikely(!task || !task->lldd_task || !task->dev))
2373 return -EINVAL;
2374
2375 ts = &task->task_status;
2376 device = task->dev;
2377 ha = device->port->ha;
2378 sas_dev = device->lldd_dev;
2379
2380 spin_lock_irqsave(&task->task_state_lock, flags);
2381 task->task_state_flags &=
2382 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2383 spin_unlock_irqrestore(&task->task_state_lock, flags);
2384
2385 memset(ts, 0, sizeof(*ts));
2386 ts->resp = SAS_TASK_COMPLETE;
2387
2388 if (unlikely(!sas_dev)) {
2389 dev_dbg(dev, "slot complete: port has no device\n");
2390 ts->stat = SAS_PHY_DOWN;
2391 goto out;
2392 }
2393
2394 /* Use SAS+TMF status codes */
2395 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2396 >> CMPLT_HDR_ABORT_STAT_OFF) {
2397 case STAT_IO_ABORTED:
2398 /* this io has been aborted by abort command */
2399 ts->stat = SAS_ABORTED_TASK;
2400 goto out;
2401 case STAT_IO_COMPLETE:
2402 /* internal abort command complete */
2403 ts->stat = TMF_RESP_FUNC_SUCC;
2404 del_timer(&slot->internal_abort_timer);
2405 goto out;
2406 case STAT_IO_NO_DEVICE:
2407 ts->stat = TMF_RESP_FUNC_COMPLETE;
2408 del_timer(&slot->internal_abort_timer);
2409 goto out;
2410 case STAT_IO_NOT_VALID:
2411 /* abort single io, controller don't find
2412 * the io need to abort
2413 */
2414 ts->stat = TMF_RESP_FUNC_FAILED;
2415 del_timer(&slot->internal_abort_timer);
2416 goto out;
2417 default:
2418 break;
2419 }
2420
2421 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2422 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2423 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2424 >> CMPLT_HDR_ERR_PHASE_OFF;
2425 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2426
2427 /* Analyse error happens on which phase TX or RX */
2428 if (ERR_ON_TX_PHASE(err_phase))
2429 slot_err_v2_hw(hisi_hba, task, slot, 1);
2430 else if (ERR_ON_RX_PHASE(err_phase))
2431 slot_err_v2_hw(hisi_hba, task, slot, 2);
2432
2433 if (ts->stat != SAS_DATA_UNDERRUN)
2434 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
2435 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
2436 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
2437 slot->idx, task, sas_dev->device_id,
2438 complete_hdr->dw0, complete_hdr->dw1,
2439 complete_hdr->act, complete_hdr->dw3,
2440 error_info[0], error_info[1],
2441 error_info[2], error_info[3]);
2442
2443 if (unlikely(slot->abort))
2444 return ts->stat;
2445 goto out;
2446 }
2447
2448 switch (task->task_proto) {
2449 case SAS_PROTOCOL_SSP:
2450 {
2451 struct hisi_sas_status_buffer *status_buffer =
2452 hisi_sas_status_buf_addr_mem(slot);
2453 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2454 &status_buffer->iu[0];
2455
2456 sas_ssp_task_response(dev, task, iu);
2457 break;
2458 }
2459 case SAS_PROTOCOL_SMP:
2460 {
2461 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2462 void *to;
2463
2464 ts->stat = SAM_STAT_GOOD;
2465 to = kmap_atomic(sg_page(sg_resp));
2466
2467 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2468 DMA_FROM_DEVICE);
2469 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2470 DMA_TO_DEVICE);
2471 memcpy(to + sg_resp->offset,
2472 hisi_sas_status_buf_addr_mem(slot) +
2473 sizeof(struct hisi_sas_err_record),
2474 sg_dma_len(sg_resp));
2475 kunmap_atomic(to);
2476 break;
2477 }
2478 case SAS_PROTOCOL_SATA:
2479 case SAS_PROTOCOL_STP:
2480 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2481 {
2482 ts->stat = SAM_STAT_GOOD;
2483 hisi_sas_sata_done(task, slot);
2484 break;
2485 }
2486 default:
2487 ts->stat = SAM_STAT_CHECK_CONDITION;
2488 break;
2489 }
2490
2491 if (!slot->port->port_attached) {
2492 dev_warn(dev, "slot complete: port %d has removed\n",
2493 slot->port->sas_port.id);
2494 ts->stat = SAS_PHY_DOWN;
2495 }
2496
2497 out:
2498 hisi_sas_slot_task_free(hisi_hba, task, slot);
2499 sts = ts->stat;
2500 spin_lock_irqsave(&task->task_state_lock, flags);
2501 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2502 spin_unlock_irqrestore(&task->task_state_lock, flags);
2503 dev_info(dev, "slot complete: task(%p) aborted\n", task);
2504 return SAS_ABORTED_TASK;
2505 }
2506 task->task_state_flags |= SAS_TASK_STATE_DONE;
2507 spin_unlock_irqrestore(&task->task_state_lock, flags);
2508
2509 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2510 spin_lock_irqsave(&device->done_lock, flags);
2511 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2512 spin_unlock_irqrestore(&device->done_lock, flags);
2513 dev_info(dev, "slot complete: task(%p) ignored\n ",
2514 task);
2515 return sts;
2516 }
2517 spin_unlock_irqrestore(&device->done_lock, flags);
2518 }
2519
2520 if (task->task_done)
2521 task->task_done(task);
2522
2523 return sts;
2524 }
2525
2526 static void prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2527 struct hisi_sas_slot *slot)
2528 {
2529 struct sas_task *task = slot->task;
2530 struct domain_device *device = task->dev;
2531 struct domain_device *parent_dev = device->parent;
2532 struct hisi_sas_device *sas_dev = device->lldd_dev;
2533 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2534 struct asd_sas_port *sas_port = device->port;
2535 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2536 struct hisi_sas_tmf_task *tmf = slot->tmf;
2537 u8 *buf_cmd;
2538 int has_data = 0, hdr_tag = 0;
2539 u32 dw1 = 0, dw2 = 0;
2540
2541 /* create header */
2542 /* dw0 */
2543 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2544 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2545 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2546 else
2547 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2548
2549 if (tmf && tmf->force_phy) {
2550 hdr->dw0 |= CMD_HDR_FORCE_PHY_MSK;
2551 hdr->dw0 |= cpu_to_le32((1 << tmf->phy_id)
2552 << CMD_HDR_PHY_ID_OFF);
2553 }
2554
2555 /* dw1 */
2556 switch (task->data_dir) {
2557 case DMA_TO_DEVICE:
2558 has_data = 1;
2559 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2560 break;
2561 case DMA_FROM_DEVICE:
2562 has_data = 1;
2563 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2564 break;
2565 default:
2566 dw1 &= ~CMD_HDR_DIR_MSK;
2567 }
2568
2569 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2570 (task->ata_task.fis.control & ATA_SRST))
2571 dw1 |= 1 << CMD_HDR_RESET_OFF;
2572
2573 dw1 |= (hisi_sas_get_ata_protocol(
2574 &task->ata_task.fis, task->data_dir))
2575 << CMD_HDR_FRAME_TYPE_OFF;
2576 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2577 hdr->dw1 = cpu_to_le32(dw1);
2578
2579 /* dw2 */
2580 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2581 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2582 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2583 }
2584
2585 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2586 2 << CMD_HDR_SG_MOD_OFF;
2587 hdr->dw2 = cpu_to_le32(dw2);
2588
2589 /* dw3 */
2590 hdr->transfer_tags = cpu_to_le32(slot->idx);
2591
2592 if (has_data)
2593 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2594 slot->n_elem);
2595
2596 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2597 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2598 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2599
2600 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2601
2602 if (likely(!task->ata_task.device_control_reg_update))
2603 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2604 /* fill in command FIS */
2605 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2606 }
2607
2608 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
2609 {
2610 struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
2611 struct hisi_sas_port *port = slot->port;
2612 struct asd_sas_port *asd_sas_port;
2613 struct asd_sas_phy *sas_phy;
2614
2615 if (!port)
2616 return;
2617
2618 asd_sas_port = &port->sas_port;
2619
2620 /* Kick the hardware - send break command */
2621 list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2622 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2623 struct hisi_hba *hisi_hba = phy->hisi_hba;
2624 int phy_no = sas_phy->id;
2625 u32 link_dfx2;
2626
2627 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2628 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2629 (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2630 u32 txid_auto;
2631
2632 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2633 TXID_AUTO);
2634 txid_auto |= TXID_AUTO_CTB_MSK;
2635 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2636 txid_auto);
2637 return;
2638 }
2639 }
2640 }
2641
2642 static void prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2643 struct hisi_sas_slot *slot,
2644 int device_id, int abort_flag, int tag_to_abort)
2645 {
2646 struct sas_task *task = slot->task;
2647 struct domain_device *dev = task->dev;
2648 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2649 struct hisi_sas_port *port = slot->port;
2650 struct timer_list *timer = &slot->internal_abort_timer;
2651
2652 /* setup the quirk timer */
2653 timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
2654 /* Set the timeout to 10ms less than internal abort timeout */
2655 mod_timer(timer, jiffies + msecs_to_jiffies(100));
2656
2657 /* dw0 */
2658 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2659 (port->id << CMD_HDR_PORT_OFF) |
2660 (dev_is_sata(dev) <<
2661 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2662 (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2663
2664 /* dw1 */
2665 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2666
2667 /* dw7 */
2668 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2669 hdr->transfer_tags = cpu_to_le32(slot->idx);
2670 }
2671
2672 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2673 {
2674 int i, res = IRQ_HANDLED;
2675 u32 port_id, link_rate;
2676 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2677 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2678 struct device *dev = hisi_hba->dev;
2679 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2680 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2681 unsigned long flags;
2682
2683 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2684
2685 if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2686 goto end;
2687
2688 if (phy_no == 8) {
2689 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2690
2691 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2692 PORT_STATE_PHY8_PORT_NUM_OFF;
2693 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2694 PORT_STATE_PHY8_CONN_RATE_OFF;
2695 } else {
2696 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2697 port_id = (port_id >> (4 * phy_no)) & 0xf;
2698 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2699 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2700 }
2701
2702 if (port_id == 0xf) {
2703 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2704 res = IRQ_NONE;
2705 goto end;
2706 }
2707
2708 for (i = 0; i < 6; i++) {
2709 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2710 RX_IDAF_DWORD0 + (i * 4));
2711 frame_rcvd[i] = __swab32(idaf);
2712 }
2713
2714 sas_phy->linkrate = link_rate;
2715 sas_phy->oob_mode = SAS_OOB_MODE;
2716 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2717 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2718 phy->port_id = port_id;
2719 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2720 phy->phy_type |= PORT_TYPE_SAS;
2721 phy->phy_attached = 1;
2722 phy->identify.device_type = id->dev_type;
2723 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
2724 if (phy->identify.device_type == SAS_END_DEVICE)
2725 phy->identify.target_port_protocols =
2726 SAS_PROTOCOL_SSP;
2727 else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2728 phy->identify.target_port_protocols =
2729 SAS_PROTOCOL_SMP;
2730 if (!timer_pending(&hisi_hba->timer))
2731 set_link_timer_quirk(hisi_hba);
2732 }
2733 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
2734 spin_lock_irqsave(&phy->lock, flags);
2735 if (phy->reset_completion) {
2736 phy->in_reset = 0;
2737 complete(phy->reset_completion);
2738 }
2739 spin_unlock_irqrestore(&phy->lock, flags);
2740
2741 end:
2742 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2743 CHL_INT0_SL_PHY_ENABLE_MSK);
2744 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2745
2746 return res;
2747 }
2748
2749 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2750 {
2751 u32 port_state;
2752
2753 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2754 if (port_state & 0x1ff)
2755 return true;
2756
2757 return false;
2758 }
2759
2760 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2761 {
2762 u32 phy_state, sl_ctrl, txid_auto;
2763 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2764 struct hisi_sas_port *port = phy->port;
2765 struct device *dev = hisi_hba->dev;
2766
2767 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2768
2769 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2770 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
2771 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2772
2773 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2774 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2775 sl_ctrl & ~SL_CONTROL_CTA_MSK);
2776 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2777 if (!check_any_wideports_v2_hw(hisi_hba) &&
2778 timer_pending(&hisi_hba->timer))
2779 del_timer(&hisi_hba->timer);
2780
2781 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2782 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2783 txid_auto | TXID_AUTO_CT3_MSK);
2784
2785 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2786 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2787
2788 return IRQ_HANDLED;
2789 }
2790
2791 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2792 {
2793 struct hisi_hba *hisi_hba = p;
2794 u32 irq_msk;
2795 int phy_no = 0;
2796 irqreturn_t res = IRQ_NONE;
2797
2798 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2799 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2800 while (irq_msk) {
2801 if (irq_msk & 1) {
2802 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2803 CHL_INT0);
2804
2805 switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2806 CHL_INT0_SL_PHY_ENABLE_MSK)) {
2807
2808 case CHL_INT0_SL_PHY_ENABLE_MSK:
2809 /* phy up */
2810 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2811 IRQ_HANDLED)
2812 res = IRQ_HANDLED;
2813 break;
2814
2815 case CHL_INT0_NOT_RDY_MSK:
2816 /* phy down */
2817 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2818 IRQ_HANDLED)
2819 res = IRQ_HANDLED;
2820 break;
2821
2822 case (CHL_INT0_NOT_RDY_MSK |
2823 CHL_INT0_SL_PHY_ENABLE_MSK):
2824 reg_value = hisi_sas_read32(hisi_hba,
2825 PHY_STATE);
2826 if (reg_value & BIT(phy_no)) {
2827 /* phy up */
2828 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2829 IRQ_HANDLED)
2830 res = IRQ_HANDLED;
2831 } else {
2832 /* phy down */
2833 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2834 IRQ_HANDLED)
2835 res = IRQ_HANDLED;
2836 }
2837 break;
2838
2839 default:
2840 break;
2841 }
2842
2843 }
2844 irq_msk >>= 1;
2845 phy_no++;
2846 }
2847
2848 return res;
2849 }
2850
2851 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2852 {
2853 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2854 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2855 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2856 u32 bcast_status;
2857
2858 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2859 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2860 if (bcast_status & RX_BCAST_CHG_MSK)
2861 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2862 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2863 CHL_INT0_SL_RX_BCST_ACK_MSK);
2864 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2865 }
2866
2867 static const struct hisi_sas_hw_error port_ecc_axi_error[] = {
2868 {
2869 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF),
2870 .msg = "dmac_tx_ecc_bad_err",
2871 },
2872 {
2873 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF),
2874 .msg = "dmac_rx_ecc_bad_err",
2875 },
2876 {
2877 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
2878 .msg = "dma_tx_axi_wr_err",
2879 },
2880 {
2881 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
2882 .msg = "dma_tx_axi_rd_err",
2883 },
2884 {
2885 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
2886 .msg = "dma_rx_axi_wr_err",
2887 },
2888 {
2889 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
2890 .msg = "dma_rx_axi_rd_err",
2891 },
2892 };
2893
2894 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2895 {
2896 struct hisi_hba *hisi_hba = p;
2897 struct device *dev = hisi_hba->dev;
2898 u32 ent_msk, ent_tmp, irq_msk;
2899 int phy_no = 0;
2900
2901 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2902 ent_tmp = ent_msk;
2903 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2904 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2905
2906 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2907 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2908
2909 while (irq_msk) {
2910 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2911 CHL_INT0);
2912 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2913 CHL_INT1);
2914 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2915 CHL_INT2);
2916
2917 if ((irq_msk & (1 << phy_no)) && irq_value1) {
2918 int i;
2919
2920 for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) {
2921 const struct hisi_sas_hw_error *error =
2922 &port_ecc_axi_error[i];
2923
2924 if (!(irq_value1 & error->irq_msk))
2925 continue;
2926
2927 dev_warn(dev, "%s error (phy%d 0x%x) found!\n",
2928 error->msg, phy_no, irq_value1);
2929 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2930 }
2931
2932 hisi_sas_phy_write32(hisi_hba, phy_no,
2933 CHL_INT1, irq_value1);
2934 }
2935
2936 if ((irq_msk & (1 << phy_no)) && irq_value2) {
2937 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2938
2939 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
2940 dev_warn(dev, "phy%d identify timeout\n",
2941 phy_no);
2942 hisi_sas_notify_phy_event(phy,
2943 HISI_PHYE_LINK_RESET);
2944 }
2945
2946 hisi_sas_phy_write32(hisi_hba, phy_no,
2947 CHL_INT2, irq_value2);
2948 }
2949
2950 if ((irq_msk & (1 << phy_no)) && irq_value0) {
2951 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2952 phy_bcast_v2_hw(phy_no, hisi_hba);
2953
2954 hisi_sas_phy_write32(hisi_hba, phy_no,
2955 CHL_INT0, irq_value0
2956 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2957 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2958 & (~CHL_INT0_NOT_RDY_MSK));
2959 }
2960 irq_msk &= ~(1 << phy_no);
2961 phy_no++;
2962 }
2963
2964 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2965
2966 return IRQ_HANDLED;
2967 }
2968
2969 static void
2970 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2971 {
2972 struct device *dev = hisi_hba->dev;
2973 const struct hisi_sas_hw_error *ecc_error;
2974 u32 val;
2975 int i;
2976
2977 for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2978 ecc_error = &one_bit_ecc_errors[i];
2979 if (irq_value & ecc_error->irq_msk) {
2980 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2981 val &= ecc_error->msk;
2982 val >>= ecc_error->shift;
2983 dev_warn(dev, ecc_error->msg, val);
2984 }
2985 }
2986 }
2987
2988 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2989 u32 irq_value)
2990 {
2991 struct device *dev = hisi_hba->dev;
2992 const struct hisi_sas_hw_error *ecc_error;
2993 u32 val;
2994 int i;
2995
2996 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2997 ecc_error = &multi_bit_ecc_errors[i];
2998 if (irq_value & ecc_error->irq_msk) {
2999 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
3000 val &= ecc_error->msk;
3001 val >>= ecc_error->shift;
3002 dev_err(dev, ecc_error->msg, irq_value, val);
3003 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3004 }
3005 }
3006
3007 return;
3008 }
3009
3010 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
3011 {
3012 struct hisi_hba *hisi_hba = p;
3013 u32 irq_value, irq_msk;
3014
3015 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
3016 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
3017
3018 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
3019 if (irq_value) {
3020 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3021 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3022 }
3023
3024 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
3025 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
3026
3027 return IRQ_HANDLED;
3028 }
3029
3030 static const struct hisi_sas_hw_error axi_error[] = {
3031 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
3032 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
3033 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
3034 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
3035 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
3036 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
3037 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
3038 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
3039 {},
3040 };
3041
3042 static const struct hisi_sas_hw_error fifo_error[] = {
3043 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
3044 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
3045 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
3046 { .msk = BIT(11), .msg = "CMDP_FIFO" },
3047 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
3048 {},
3049 };
3050
3051 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
3052 {
3053 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
3054 .msg = "write pointer and depth",
3055 },
3056 {
3057 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
3058 .msg = "iptt no match slot",
3059 },
3060 {
3061 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
3062 .msg = "read pointer and depth",
3063 },
3064 {
3065 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
3066 .reg = HGC_AXI_FIFO_ERR_INFO,
3067 .sub = axi_error,
3068 },
3069 {
3070 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
3071 .reg = HGC_AXI_FIFO_ERR_INFO,
3072 .sub = fifo_error,
3073 },
3074 {
3075 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
3076 .msg = "LM add/fetch list",
3077 },
3078 {
3079 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
3080 .msg = "SAS_HGC_ABT fetch LM list",
3081 },
3082 };
3083
3084 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
3085 {
3086 struct hisi_hba *hisi_hba = p;
3087 u32 irq_value, irq_msk, err_value;
3088 struct device *dev = hisi_hba->dev;
3089 const struct hisi_sas_hw_error *axi_error;
3090 int i;
3091
3092 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3093 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3094
3095 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3096
3097 for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3098 axi_error = &fatal_axi_errors[i];
3099 if (!(irq_value & axi_error->irq_msk))
3100 continue;
3101
3102 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3103 1 << axi_error->shift);
3104 if (axi_error->sub) {
3105 const struct hisi_sas_hw_error *sub = axi_error->sub;
3106
3107 err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3108 for (; sub->msk || sub->msg; sub++) {
3109 if (!(err_value & sub->msk))
3110 continue;
3111 dev_err(dev, "%s (0x%x) found!\n",
3112 sub->msg, irq_value);
3113 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3114 }
3115 } else {
3116 dev_err(dev, "%s (0x%x) found!\n",
3117 axi_error->msg, irq_value);
3118 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3119 }
3120 }
3121
3122 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3123 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3124 u32 dev_id = reg_val & ITCT_DEV_MSK;
3125 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3126
3127 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3128 dev_dbg(dev, "clear ITCT ok\n");
3129 complete(sas_dev->completion);
3130 }
3131
3132 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3133 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3134
3135 return IRQ_HANDLED;
3136 }
3137
3138 static void cq_tasklet_v2_hw(unsigned long val)
3139 {
3140 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3141 struct hisi_hba *hisi_hba = cq->hisi_hba;
3142 struct hisi_sas_slot *slot;
3143 struct hisi_sas_itct *itct;
3144 struct hisi_sas_complete_v2_hdr *complete_queue;
3145 u32 rd_point = cq->rd_point, wr_point, dev_id;
3146 int queue = cq->id;
3147
3148 if (unlikely(hisi_hba->reject_stp_links_msk))
3149 phys_try_accept_stp_links_v2_hw(hisi_hba);
3150
3151 complete_queue = hisi_hba->complete_hdr[queue];
3152
3153 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3154 (0x14 * queue));
3155
3156 while (rd_point != wr_point) {
3157 struct hisi_sas_complete_v2_hdr *complete_hdr;
3158 int iptt;
3159
3160 complete_hdr = &complete_queue[rd_point];
3161
3162 /* Check for NCQ completion */
3163 if (complete_hdr->act) {
3164 u32 act_tmp = complete_hdr->act;
3165 int ncq_tag_count = ffs(act_tmp);
3166
3167 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3168 CMPLT_HDR_DEV_ID_OFF;
3169 itct = &hisi_hba->itct[dev_id];
3170
3171 /* The NCQ tags are held in the itct header */
3172 while (ncq_tag_count) {
3173 __le64 *ncq_tag = &itct->qw4_15[0];
3174
3175 ncq_tag_count -= 1;
3176 iptt = (ncq_tag[ncq_tag_count / 5]
3177 >> (ncq_tag_count % 5) * 12) & 0xfff;
3178
3179 slot = &hisi_hba->slot_info[iptt];
3180 slot->cmplt_queue_slot = rd_point;
3181 slot->cmplt_queue = queue;
3182 slot_complete_v2_hw(hisi_hba, slot);
3183
3184 act_tmp &= ~(1 << ncq_tag_count);
3185 ncq_tag_count = ffs(act_tmp);
3186 }
3187 } else {
3188 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3189 slot = &hisi_hba->slot_info[iptt];
3190 slot->cmplt_queue_slot = rd_point;
3191 slot->cmplt_queue = queue;
3192 slot_complete_v2_hw(hisi_hba, slot);
3193 }
3194
3195 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3196 rd_point = 0;
3197 }
3198
3199 /* update rd_point */
3200 cq->rd_point = rd_point;
3201 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3202 }
3203
3204 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3205 {
3206 struct hisi_sas_cq *cq = p;
3207 struct hisi_hba *hisi_hba = cq->hisi_hba;
3208 int queue = cq->id;
3209
3210 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3211
3212 tasklet_schedule(&cq->tasklet);
3213
3214 return IRQ_HANDLED;
3215 }
3216
3217 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3218 {
3219 struct hisi_sas_phy *phy = p;
3220 struct hisi_hba *hisi_hba = phy->hisi_hba;
3221 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3222 struct device *dev = hisi_hba->dev;
3223 struct hisi_sas_initial_fis *initial_fis;
3224 struct dev_to_host_fis *fis;
3225 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3226 irqreturn_t res = IRQ_HANDLED;
3227 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3228 unsigned long flags;
3229 int phy_no, offset;
3230
3231 phy_no = sas_phy->id;
3232 initial_fis = &hisi_hba->initial_fis[phy_no];
3233 fis = &initial_fis->fis;
3234
3235 offset = 4 * (phy_no / 4);
3236 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3237 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3238 ent_msk | 1 << ((phy_no % 4) * 8));
3239
3240 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3241 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3242 (phy_no % 4)));
3243 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3244 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3245 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3246 res = IRQ_NONE;
3247 goto end;
3248 }
3249
3250 /* check ERR bit of Status Register */
3251 if (fis->status & ATA_ERR) {
3252 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3253 fis->status);
3254 disable_phy_v2_hw(hisi_hba, phy_no);
3255 enable_phy_v2_hw(hisi_hba, phy_no);
3256 res = IRQ_NONE;
3257 goto end;
3258 }
3259
3260 if (unlikely(phy_no == 8)) {
3261 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3262
3263 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3264 PORT_STATE_PHY8_PORT_NUM_OFF;
3265 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3266 PORT_STATE_PHY8_CONN_RATE_OFF;
3267 } else {
3268 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3269 port_id = (port_id >> (4 * phy_no)) & 0xf;
3270 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3271 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3272 }
3273
3274 if (port_id == 0xf) {
3275 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3276 res = IRQ_NONE;
3277 goto end;
3278 }
3279
3280 sas_phy->linkrate = link_rate;
3281 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3282 HARD_PHY_LINKRATE);
3283 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3284 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3285
3286 sas_phy->oob_mode = SATA_OOB_MODE;
3287 /* Make up some unique SAS address */
3288 attached_sas_addr[0] = 0x50;
3289 attached_sas_addr[6] = hisi_hba->shost->host_no;
3290 attached_sas_addr[7] = phy_no;
3291 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3292 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3293 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3294 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3295 phy->port_id = port_id;
3296 phy->phy_type |= PORT_TYPE_SATA;
3297 phy->phy_attached = 1;
3298 phy->identify.device_type = SAS_SATA_DEV;
3299 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3300 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3301 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
3302
3303 spin_lock_irqsave(&phy->lock, flags);
3304 if (phy->reset_completion) {
3305 phy->in_reset = 0;
3306 complete(phy->reset_completion);
3307 }
3308 spin_unlock_irqrestore(&phy->lock, flags);
3309 end:
3310 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3311 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3312
3313 return res;
3314 }
3315
3316 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3317 int_phy_updown_v2_hw,
3318 int_chnl_int_v2_hw,
3319 };
3320
3321 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3322 fatal_ecc_int_v2_hw,
3323 fatal_axi_int_v2_hw
3324 };
3325
3326 /**
3327 * There is a limitation in the hip06 chipset that we need
3328 * to map in all mbigen interrupts, even if they are not used.
3329 */
3330 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3331 {
3332 struct platform_device *pdev = hisi_hba->platform_dev;
3333 struct device *dev = &pdev->dev;
3334 int irq, rc, irq_map[128];
3335 int i, phy_no, fatal_no, queue_no, k;
3336
3337 for (i = 0; i < 128; i++)
3338 irq_map[i] = platform_get_irq(pdev, i);
3339
3340 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3341 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3342 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3343 DRV_NAME " phy", hisi_hba);
3344 if (rc) {
3345 dev_err(dev, "irq init: could not request "
3346 "phy interrupt %d, rc=%d\n",
3347 irq, rc);
3348 rc = -ENOENT;
3349 goto free_phy_int_irqs;
3350 }
3351 }
3352
3353 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3354 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3355
3356 irq = irq_map[phy_no + 72];
3357 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3358 DRV_NAME " sata", phy);
3359 if (rc) {
3360 dev_err(dev, "irq init: could not request "
3361 "sata interrupt %d, rc=%d\n",
3362 irq, rc);
3363 rc = -ENOENT;
3364 goto free_sata_int_irqs;
3365 }
3366 }
3367
3368 for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3369 irq = irq_map[fatal_no + 81];
3370 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3371 DRV_NAME " fatal", hisi_hba);
3372 if (rc) {
3373 dev_err(dev,
3374 "irq init: could not request fatal interrupt %d, rc=%d\n",
3375 irq, rc);
3376 rc = -ENOENT;
3377 goto free_fatal_int_irqs;
3378 }
3379 }
3380
3381 for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3382 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3383 struct tasklet_struct *t = &cq->tasklet;
3384
3385 irq = irq_map[queue_no + 96];
3386 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3387 DRV_NAME " cq", cq);
3388 if (rc) {
3389 dev_err(dev,
3390 "irq init: could not request cq interrupt %d, rc=%d\n",
3391 irq, rc);
3392 rc = -ENOENT;
3393 goto free_cq_int_irqs;
3394 }
3395 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3396 }
3397
3398 return 0;
3399
3400 free_cq_int_irqs:
3401 for (k = 0; k < queue_no; k++) {
3402 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3403
3404 free_irq(irq_map[k + 96], cq);
3405 tasklet_kill(&cq->tasklet);
3406 }
3407 free_fatal_int_irqs:
3408 for (k = 0; k < fatal_no; k++)
3409 free_irq(irq_map[k + 81], hisi_hba);
3410 free_sata_int_irqs:
3411 for (k = 0; k < phy_no; k++) {
3412 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3413
3414 free_irq(irq_map[k + 72], phy);
3415 }
3416 free_phy_int_irqs:
3417 for (k = 0; k < i; k++)
3418 free_irq(irq_map[k + 1], hisi_hba);
3419 return rc;
3420 }
3421
3422 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3423 {
3424 int rc;
3425
3426 memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3427
3428 rc = hw_init_v2_hw(hisi_hba);
3429 if (rc)
3430 return rc;
3431
3432 rc = interrupt_init_v2_hw(hisi_hba);
3433 if (rc)
3434 return rc;
3435
3436 return 0;
3437 }
3438
3439 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3440 {
3441 struct platform_device *pdev = hisi_hba->platform_dev;
3442 int i;
3443
3444 for (i = 0; i < hisi_hba->queue_count; i++)
3445 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3446
3447 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3448 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3449 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3450 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3451
3452 for (i = 0; i < hisi_hba->n_phy; i++) {
3453 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3454 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3455 }
3456
3457 for (i = 0; i < 128; i++)
3458 synchronize_irq(platform_get_irq(pdev, i));
3459 }
3460
3461
3462 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3463 {
3464 return hisi_sas_read32(hisi_hba, PHY_STATE);
3465 }
3466
3467 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3468 {
3469 struct device *dev = hisi_hba->dev;
3470 int rc, cnt;
3471
3472 interrupt_disable_v2_hw(hisi_hba);
3473 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3474 hisi_sas_kill_tasklets(hisi_hba);
3475
3476 hisi_sas_stop_phys(hisi_hba);
3477
3478 mdelay(10);
3479
3480 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3481
3482 /* wait until bus idle */
3483 cnt = 0;
3484 while (1) {
3485 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3486 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3487
3488 if (status == 0x3)
3489 break;
3490
3491 udelay(10);
3492 if (cnt++ > 10) {
3493 dev_err(dev, "wait axi bus state to idle timeout!\n");
3494 return -1;
3495 }
3496 }
3497
3498 hisi_sas_init_mem(hisi_hba);
3499
3500 rc = hw_init_v2_hw(hisi_hba);
3501 if (rc)
3502 return rc;
3503
3504 phys_reject_stp_links_v2_hw(hisi_hba);
3505
3506 return 0;
3507 }
3508
3509 static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
3510 u8 reg_index, u8 reg_count, u8 *write_data)
3511 {
3512 struct device *dev = hisi_hba->dev;
3513 int phy_no, count;
3514
3515 if (!hisi_hba->sgpio_regs)
3516 return -EOPNOTSUPP;
3517
3518 switch (reg_type) {
3519 case SAS_GPIO_REG_TX:
3520 count = reg_count * 4;
3521 count = min(count, hisi_hba->n_phy);
3522
3523 for (phy_no = 0; phy_no < count; phy_no++) {
3524 /*
3525 * GPIO_TX[n] register has the highest numbered drive
3526 * of the four in the first byte and the lowest
3527 * numbered drive in the fourth byte.
3528 * See SFF-8485 Rev. 0.7 Table 24.
3529 */
3530 void __iomem *reg_addr = hisi_hba->sgpio_regs +
3531 reg_index * 4 + phy_no;
3532 int data_idx = phy_no + 3 - (phy_no % 4) * 2;
3533
3534 writeb(write_data[data_idx], reg_addr);
3535 }
3536
3537 break;
3538 default:
3539 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3540 reg_type);
3541 return -EINVAL;
3542 }
3543
3544 return 0;
3545 }
3546
3547 static void wait_cmds_complete_timeout_v2_hw(struct hisi_hba *hisi_hba,
3548 int delay_ms, int timeout_ms)
3549 {
3550 struct device *dev = hisi_hba->dev;
3551 int entries, entries_old = 0, time;
3552
3553 for (time = 0; time < timeout_ms; time += delay_ms) {
3554 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
3555 if (entries == entries_old)
3556 break;
3557
3558 entries_old = entries;
3559 msleep(delay_ms);
3560 }
3561
3562 dev_dbg(dev, "wait commands complete %dms\n", time);
3563 }
3564
3565 static struct scsi_host_template sht_v2_hw = {
3566 .name = DRV_NAME,
3567 .module = THIS_MODULE,
3568 .queuecommand = sas_queuecommand,
3569 .target_alloc = sas_target_alloc,
3570 .slave_configure = hisi_sas_slave_configure,
3571 .scan_finished = hisi_sas_scan_finished,
3572 .scan_start = hisi_sas_scan_start,
3573 .change_queue_depth = sas_change_queue_depth,
3574 .bios_param = sas_bios_param,
3575 .can_queue = 1,
3576 .this_id = -1,
3577 .sg_tablesize = SG_ALL,
3578 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
3579 .use_clustering = ENABLE_CLUSTERING,
3580 .eh_device_reset_handler = sas_eh_device_reset_handler,
3581 .eh_target_reset_handler = sas_eh_target_reset_handler,
3582 .target_destroy = sas_target_destroy,
3583 .ioctl = sas_ioctl,
3584 .shost_attrs = host_attrs,
3585 };
3586
3587 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3588 .hw_init = hisi_sas_v2_init,
3589 .setup_itct = setup_itct_v2_hw,
3590 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3591 .alloc_dev = alloc_dev_quirk_v2_hw,
3592 .sl_notify = sl_notify_v2_hw,
3593 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3594 .clear_itct = clear_itct_v2_hw,
3595 .free_device = free_device_v2_hw,
3596 .prep_smp = prep_smp_v2_hw,
3597 .prep_ssp = prep_ssp_v2_hw,
3598 .prep_stp = prep_ata_v2_hw,
3599 .prep_abort = prep_abort_v2_hw,
3600 .get_free_slot = get_free_slot_v2_hw,
3601 .start_delivery = start_delivery_v2_hw,
3602 .slot_complete = slot_complete_v2_hw,
3603 .phys_init = phys_init_v2_hw,
3604 .phy_start = start_phy_v2_hw,
3605 .phy_disable = disable_phy_v2_hw,
3606 .phy_hard_reset = phy_hard_reset_v2_hw,
3607 .get_events = phy_get_events_v2_hw,
3608 .phy_set_linkrate = phy_set_linkrate_v2_hw,
3609 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3610 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3611 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3612 .soft_reset = soft_reset_v2_hw,
3613 .get_phys_state = get_phys_state_v2_hw,
3614 .write_gpio = write_gpio_v2_hw,
3615 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v2_hw,
3616 .sht = &sht_v2_hw,
3617 };
3618
3619 static int hisi_sas_v2_probe(struct platform_device *pdev)
3620 {
3621 /*
3622 * Check if we should defer the probe before we probe the
3623 * upper layer, as it's hard to defer later on.
3624 */
3625 int ret = platform_get_irq(pdev, 0);
3626
3627 if (ret < 0) {
3628 if (ret != -EPROBE_DEFER)
3629 dev_err(&pdev->dev, "cannot obtain irq\n");
3630 return ret;
3631 }
3632
3633 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3634 }
3635
3636 static int hisi_sas_v2_remove(struct platform_device *pdev)
3637 {
3638 struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3639 struct hisi_hba *hisi_hba = sha->lldd_ha;
3640
3641 hisi_sas_kill_tasklets(hisi_hba);
3642
3643 return hisi_sas_remove(pdev);
3644 }
3645
3646 static const struct of_device_id sas_v2_of_match[] = {
3647 { .compatible = "hisilicon,hip06-sas-v2",},
3648 { .compatible = "hisilicon,hip07-sas-v2",},
3649 {},
3650 };
3651 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3652
3653 static const struct acpi_device_id sas_v2_acpi_match[] = {
3654 { "HISI0162", 0 },
3655 { }
3656 };
3657
3658 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3659
3660 static struct platform_driver hisi_sas_v2_driver = {
3661 .probe = hisi_sas_v2_probe,
3662 .remove = hisi_sas_v2_remove,
3663 .driver = {
3664 .name = DRV_NAME,
3665 .of_match_table = sas_v2_of_match,
3666 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3667 },
3668 };
3669
3670 module_platform_driver(hisi_sas_v2_driver);
3671
3672 MODULE_LICENSE("GPL");
3673 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3674 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3675 MODULE_ALIAS("platform:" DRV_NAME);
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