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scsi: hisi_sas: relocate clearing ITCT and freeing device
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
1 /*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12 #include "hisi_sas.h"
13 #define DRV_NAME "hisi_sas_v2_hw"
14
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
34 #define ITCT_CLR 0x44
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_LM_DFX_STATUS2 0x128
59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
65 #define HGC_CQE_ECC_ADDR 0x13c
66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
70 #define HGC_IOST_ECC_ADDR 0x140
71 #define HGC_IOST_ECC_1B_ADDR_OFF 0
72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
73 #define HGC_IOST_ECC_MB_ADDR_OFF 16
74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
75 #define HGC_DQE_ECC_ADDR 0x144
76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
80 #define HGC_INVLD_DQE_INFO 0x148
81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
84 #define HGC_ITCT_ECC_ADDR 0x150
85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
87 HGC_ITCT_ECC_1B_ADDR_OFF)
88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
90 HGC_ITCT_ECC_MB_ADDR_OFF)
91 #define HGC_AXI_FIFO_ERR_INFO 0x154
92 #define AXI_ERR_INFO_OFF 0
93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
94 #define FIFO_ERR_INFO_OFF 8
95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
96 #define INT_COAL_EN 0x19c
97 #define OQ_INT_COAL_TIME 0x1a0
98 #define OQ_INT_COAL_CNT 0x1a4
99 #define ENT_INT_COAL_TIME 0x1a8
100 #define ENT_INT_COAL_CNT 0x1ac
101 #define OQ_INT_SRC 0x1b0
102 #define OQ_INT_SRC_MSK 0x1b4
103 #define ENT_INT_SRC1 0x1b8
104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
108 #define ENT_INT_SRC2 0x1bc
109 #define ENT_INT_SRC3 0x1c0
110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
113 #define ENT_INT_SRC3_AXI_OFF 11
114 #define ENT_INT_SRC3_FIFO_OFF 12
115 #define ENT_INT_SRC3_LM_OFF 14
116 #define ENT_INT_SRC3_ITC_INT_OFF 15
117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
118 #define ENT_INT_SRC3_ABT_OFF 16
119 #define ENT_INT_SRC_MSK1 0x1c4
120 #define ENT_INT_SRC_MSK2 0x1c8
121 #define ENT_INT_SRC_MSK3 0x1cc
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
145 #define SAS_ECC_INTR_MSK 0x1ec
146 #define HGC_ERR_STAT_EN 0x238
147 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
148 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
149 #define DLVRY_Q_0_DEPTH 0x268
150 #define DLVRY_Q_0_WR_PTR 0x26c
151 #define DLVRY_Q_0_RD_PTR 0x270
152 #define HYPER_STREAM_ID_EN_CFG 0xc80
153 #define OQ0_INT_SRC_MSK 0xc90
154 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
155 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
156 #define COMPL_Q_0_DEPTH 0x4e8
157 #define COMPL_Q_0_WR_PTR 0x4ec
158 #define COMPL_Q_0_RD_PTR 0x4f0
159 #define HGC_RXM_DFX_STATUS14 0xae8
160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
162 HGC_RXM_DFX_STATUS14_MEM0_OFF)
163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM1_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM2_OFF)
169 #define HGC_RXM_DFX_STATUS15 0xaec
170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
172 HGC_RXM_DFX_STATUS15_MEM3_OFF)
173 /* phy registers need init */
174 #define PORT_BASE (0x2000)
175
176 #define PHY_CFG (PORT_BASE + 0x0)
177 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
178 #define PHY_CFG_ENA_OFF 0
179 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
180 #define PHY_CFG_DC_OPT_OFF 2
181 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
182 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
183 #define PROG_PHY_LINK_RATE_MAX_OFF 0
184 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
185 #define PHY_CTRL (PORT_BASE + 0x14)
186 #define PHY_CTRL_RESET_OFF 0
187 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
188 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
189 #define SL_CFG (PORT_BASE + 0x84)
190 #define PHY_PCN (PORT_BASE + 0x44)
191 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
192 #define SL_CONTROL (PORT_BASE + 0x94)
193 #define SL_CONTROL_NOTIFY_EN_OFF 0
194 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
195 #define SL_CONTROL_CTA_OFF 17
196 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
197 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
198 #define RX_BCAST_CHG_OFF 1
199 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
200 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
201 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
202 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
203 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
204 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
205 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
206 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
207 #define TXID_AUTO (PORT_BASE + 0xb8)
208 #define TXID_AUTO_CT3_OFF 1
209 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
210 #define TXID_AUTO_CTB_OFF 11
211 #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
212 #define TX_HARDRST_OFF 2
213 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
214 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
215 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
216 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
217 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
218 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
219 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
220 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
221 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
222 #define CON_CONTROL (PORT_BASE + 0x118)
223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
225 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
226 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
227 #define CHL_INT0 (PORT_BASE + 0x1b4)
228 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
229 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
230 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
231 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
232 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
233 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
234 #define CHL_INT0_NOT_RDY_OFF 4
235 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
236 #define CHL_INT0_PHY_RDY_OFF 5
237 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
238 #define CHL_INT1 (PORT_BASE + 0x1b8)
239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
243 #define CHL_INT2 (PORT_BASE + 0x1bc)
244 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
245 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
246 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
247 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
248 #define DMA_TX_DFX0 (PORT_BASE + 0x200)
249 #define DMA_TX_DFX1 (PORT_BASE + 0x204)
250 #define DMA_TX_DFX1_IPTT_OFF 0
251 #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
252 #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
253 #define PORT_DFX0 (PORT_BASE + 0x258)
254 #define LINK_DFX2 (PORT_BASE + 0X264)
255 #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
256 #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
257 #define LINK_DFX2_SEND_HOLD_STS_OFF 10
258 #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
259 #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
260 #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
261 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
262 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
263 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
264 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
265 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
266 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
267 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
268 #define DMA_TX_STATUS_BUSY_OFF 0
269 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
270 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
271 #define DMA_RX_STATUS_BUSY_OFF 0
272 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
273
274 #define AXI_CFG (0x5100)
275 #define AM_CFG_MAX_TRANS (0x5010)
276 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
277
278 #define AXI_MASTER_CFG_BASE (0x5000)
279 #define AM_CTRL_GLOBAL (0x0)
280 #define AM_CURR_TRANS_RETURN (0x150)
281
282 /* HW dma structures */
283 /* Delivery queue header */
284 /* dw0 */
285 #define CMD_HDR_ABORT_FLAG_OFF 0
286 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
287 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
288 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
289 #define CMD_HDR_RESP_REPORT_OFF 5
290 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
291 #define CMD_HDR_TLR_CTRL_OFF 6
292 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
293 #define CMD_HDR_PORT_OFF 18
294 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
295 #define CMD_HDR_PRIORITY_OFF 27
296 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
297 #define CMD_HDR_CMD_OFF 29
298 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
299 /* dw1 */
300 #define CMD_HDR_DIR_OFF 5
301 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
302 #define CMD_HDR_RESET_OFF 7
303 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
304 #define CMD_HDR_VDTL_OFF 10
305 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
306 #define CMD_HDR_FRAME_TYPE_OFF 11
307 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
308 #define CMD_HDR_DEV_ID_OFF 16
309 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
310 /* dw2 */
311 #define CMD_HDR_CFL_OFF 0
312 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
313 #define CMD_HDR_NCQ_TAG_OFF 10
314 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
315 #define CMD_HDR_MRFL_OFF 15
316 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
317 #define CMD_HDR_SG_MOD_OFF 24
318 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
319 #define CMD_HDR_FIRST_BURST_OFF 26
320 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
321 /* dw3 */
322 #define CMD_HDR_IPTT_OFF 0
323 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
324 /* dw6 */
325 #define CMD_HDR_DIF_SGL_LEN_OFF 0
326 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
327 #define CMD_HDR_DATA_SGL_LEN_OFF 16
328 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
329 #define CMD_HDR_ABORT_IPTT_OFF 16
330 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
331
332 /* Completion header */
333 /* dw0 */
334 #define CMPLT_HDR_ERR_PHASE_OFF 2
335 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
336 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
337 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
338 #define CMPLT_HDR_ERX_OFF 12
339 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
340 #define CMPLT_HDR_ABORT_STAT_OFF 13
341 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
342 /* abort_stat */
343 #define STAT_IO_NOT_VALID 0x1
344 #define STAT_IO_NO_DEVICE 0x2
345 #define STAT_IO_COMPLETE 0x3
346 #define STAT_IO_ABORTED 0x4
347 /* dw1 */
348 #define CMPLT_HDR_IPTT_OFF 0
349 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
350 #define CMPLT_HDR_DEV_ID_OFF 16
351 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
352
353 /* ITCT header */
354 /* qw0 */
355 #define ITCT_HDR_DEV_TYPE_OFF 0
356 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
357 #define ITCT_HDR_VALID_OFF 2
358 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
359 #define ITCT_HDR_MCR_OFF 5
360 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
361 #define ITCT_HDR_VLN_OFF 9
362 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
363 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
364 #define ITCT_HDR_SMP_TIMEOUT_8US 1
365 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
366 250) /* 2ms */
367 #define ITCT_HDR_AWT_CONTINUE_OFF 25
368 #define ITCT_HDR_PORT_ID_OFF 28
369 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
370 /* qw2 */
371 #define ITCT_HDR_INLT_OFF 0
372 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
373 #define ITCT_HDR_BITLT_OFF 16
374 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
375 #define ITCT_HDR_MCTLT_OFF 32
376 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
377 #define ITCT_HDR_RTOLT_OFF 48
378 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
379
380 #define HISI_SAS_FATAL_INT_NR 2
381
382 struct hisi_sas_complete_v2_hdr {
383 __le32 dw0;
384 __le32 dw1;
385 __le32 act;
386 __le32 dw3;
387 };
388
389 struct hisi_sas_err_record_v2 {
390 /* dw0 */
391 __le32 trans_tx_fail_type;
392
393 /* dw1 */
394 __le32 trans_rx_fail_type;
395
396 /* dw2 */
397 __le16 dma_tx_err_type;
398 __le16 sipc_rx_err_type;
399
400 /* dw3 */
401 __le32 dma_rx_err_type;
402 };
403
404 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
405 {
406 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
407 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
408 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
409 .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
410 .reg = HGC_DQE_ECC_ADDR,
411 },
412 {
413 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
414 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
415 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
416 .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
417 .reg = HGC_IOST_ECC_ADDR,
418 },
419 {
420 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
421 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
422 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
423 .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
424 .reg = HGC_ITCT_ECC_ADDR,
425 },
426 {
427 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
428 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
429 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
430 .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
431 .reg = HGC_LM_DFX_STATUS2,
432 },
433 {
434 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
435 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
436 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
437 .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
438 .reg = HGC_LM_DFX_STATUS2,
439 },
440 {
441 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
442 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
443 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
444 .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
445 .reg = HGC_CQE_ECC_ADDR,
446 },
447 {
448 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
449 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
450 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
451 .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
452 .reg = HGC_RXM_DFX_STATUS14,
453 },
454 {
455 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
456 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
457 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
458 .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
459 .reg = HGC_RXM_DFX_STATUS14,
460 },
461 {
462 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
463 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
464 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
465 .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
466 .reg = HGC_RXM_DFX_STATUS14,
467 },
468 {
469 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
470 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
471 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
472 .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
473 .reg = HGC_RXM_DFX_STATUS15,
474 },
475 };
476
477 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
478 {
479 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
480 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
481 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
482 .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
483 .reg = HGC_DQE_ECC_ADDR,
484 },
485 {
486 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
487 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
488 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
489 .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
490 .reg = HGC_IOST_ECC_ADDR,
491 },
492 {
493 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
494 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
495 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
496 .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
497 .reg = HGC_ITCT_ECC_ADDR,
498 },
499 {
500 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
501 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
502 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
503 .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
504 .reg = HGC_LM_DFX_STATUS2,
505 },
506 {
507 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
508 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
509 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
510 .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
511 .reg = HGC_LM_DFX_STATUS2,
512 },
513 {
514 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
515 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
516 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
517 .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
518 .reg = HGC_CQE_ECC_ADDR,
519 },
520 {
521 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
522 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
523 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
524 .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
525 .reg = HGC_RXM_DFX_STATUS14,
526 },
527 {
528 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
529 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
530 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
531 .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
532 .reg = HGC_RXM_DFX_STATUS14,
533 },
534 {
535 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
536 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
537 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
538 .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
539 .reg = HGC_RXM_DFX_STATUS14,
540 },
541 {
542 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
543 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
544 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
545 .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
546 .reg = HGC_RXM_DFX_STATUS15,
547 },
548 };
549
550 enum {
551 HISI_SAS_PHY_PHY_UPDOWN,
552 HISI_SAS_PHY_CHNL_INT,
553 HISI_SAS_PHY_INT_NR
554 };
555
556 enum {
557 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
558 TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
559 DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
560 SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
561 DMA_RX_ERR_BASE = 0x60, /* dw3 */
562
563 /* trans tx*/
564 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
565 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
566 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
567 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
568 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
569 RESERVED0, /* 0x5 */
570 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
571 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
572 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
573 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
574 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
575 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
576 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
577 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
578 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
579 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
580 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
581 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
582 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
583 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
584 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
585 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
586 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
587 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
588 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
589 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
590 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
591 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
592 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
593 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
594 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
595 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
596 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
597 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
598 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
599
600 /* trans rx */
601 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
602 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
603 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
604 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
605 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
606 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
607 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
608 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
609 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
610 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
611 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
612 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
613 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
614 RESERVED1, /* 0x2b */
615 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
616 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
617 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
618 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
619 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
620 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
621 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
622 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
623 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
624 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
625 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
626 RESERVED2, /* 0x34 */
627 RESERVED3, /* 0x35 */
628 RESERVED4, /* 0x36 */
629 RESERVED5, /* 0x37 */
630 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
631 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
632 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
633 RESERVED6, /* 0x3b */
634 RESERVED7, /* 0x3c */
635 RESERVED8, /* 0x3d */
636 RESERVED9, /* 0x3e */
637 TRANS_RX_R_ERR, /* 0x3f */
638
639 /* dma tx */
640 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
641 DMA_TX_DIF_APP_ERR, /* 0x41 */
642 DMA_TX_DIF_RPP_ERR, /* 0x42 */
643 DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
644 DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
645 DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
646 DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
647 DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
648 DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
649 DMA_TX_RAM_ECC_ERR, /* 0x49 */
650 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
651 DMA_TX_MAX_ERR_CODE,
652
653 /* sipc rx */
654 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
655 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
656 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
657 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
658 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
659 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
660 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
661 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
662 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
663 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
664 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
665 SIPC_RX_MAX_ERR_CODE,
666
667 /* dma rx */
668 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
669 DMA_RX_DIF_APP_ERR, /* 0x61 */
670 DMA_RX_DIF_RPP_ERR, /* 0x62 */
671 DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
672 DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
673 DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
674 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
675 DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
676 RESERVED10, /* 0x68 */
677 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
678 DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
679 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
680 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
681 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
682 DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
683 DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
684 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
685 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
686 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
687 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
688 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
689 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
690 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
691 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
692 DMA_RX_RAM_ECC_ERR, /* 0x78 */
693 DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
694 DMA_RX_MAX_ERR_CODE,
695 };
696
697 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
698 #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
699
700 #define DIR_NO_DATA 0
701 #define DIR_TO_INI 1
702 #define DIR_TO_DEVICE 2
703 #define DIR_RESERVED 3
704
705 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
706 err_phase == 0x4 || err_phase == 0x8 ||\
707 err_phase == 0x6 || err_phase == 0xa)
708 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
709 err_phase == 0x20 || err_phase == 0x40)
710
711 static void link_timeout_disable_link(struct timer_list *t);
712
713 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
714 {
715 void __iomem *regs = hisi_hba->regs + off;
716
717 return readl(regs);
718 }
719
720 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
721 {
722 void __iomem *regs = hisi_hba->regs + off;
723
724 return readl_relaxed(regs);
725 }
726
727 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
728 {
729 void __iomem *regs = hisi_hba->regs + off;
730
731 writel(val, regs);
732 }
733
734 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
735 u32 off, u32 val)
736 {
737 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
738
739 writel(val, regs);
740 }
741
742 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
743 int phy_no, u32 off)
744 {
745 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
746
747 return readl(regs);
748 }
749
750 /* This function needs to be protected from pre-emption. */
751 static int
752 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
753 struct domain_device *device)
754 {
755 int sata_dev = dev_is_sata(device);
756 void *bitmap = hisi_hba->slot_index_tags;
757 struct hisi_sas_device *sas_dev = device->lldd_dev;
758 int sata_idx = sas_dev->sata_idx;
759 int start, end;
760
761 if (!sata_dev) {
762 /*
763 * STP link SoC bug workaround: index starts from 1.
764 * additionally, we can only allocate odd IPTT(1~4095)
765 * for SAS/SMP device.
766 */
767 start = 1;
768 end = hisi_hba->slot_index_count;
769 } else {
770 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
771 return -EINVAL;
772
773 /*
774 * For SATA device: allocate even IPTT in this interval
775 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
776 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
777 * SoC bug workaround. So we ignore the first 32 even IPTTs.
778 */
779 start = 64 * (sata_idx + 1);
780 end = 64 * (sata_idx + 2);
781 }
782
783 while (1) {
784 start = find_next_zero_bit(bitmap,
785 hisi_hba->slot_index_count, start);
786 if (start >= end)
787 return -SAS_QUEUE_FULL;
788 /*
789 * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
790 */
791 if (sata_dev ^ (start & 1))
792 break;
793 start++;
794 }
795
796 set_bit(start, bitmap);
797 *slot_idx = start;
798 return 0;
799 }
800
801 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
802 {
803 unsigned int index;
804 struct device *dev = hisi_hba->dev;
805 void *bitmap = hisi_hba->sata_dev_bitmap;
806
807 index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
808 if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
809 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
810 return false;
811 }
812
813 set_bit(index, bitmap);
814 *idx = index;
815 return true;
816 }
817
818
819 static struct
820 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
821 {
822 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
823 struct hisi_sas_device *sas_dev = NULL;
824 int i, sata_dev = dev_is_sata(device);
825 int sata_idx = -1;
826 unsigned long flags;
827
828 spin_lock_irqsave(&hisi_hba->lock, flags);
829
830 if (sata_dev)
831 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
832 goto out;
833
834 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
835 /*
836 * SATA device id bit0 should be 0
837 */
838 if (sata_dev && (i & 1))
839 continue;
840 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
841 int queue = i % hisi_hba->queue_count;
842 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
843
844 hisi_hba->devices[i].device_id = i;
845 sas_dev = &hisi_hba->devices[i];
846 sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
847 sas_dev->dev_type = device->dev_type;
848 sas_dev->hisi_hba = hisi_hba;
849 sas_dev->sas_device = device;
850 sas_dev->sata_idx = sata_idx;
851 sas_dev->dq = dq;
852 INIT_LIST_HEAD(&hisi_hba->devices[i].list);
853 break;
854 }
855 }
856
857 out:
858 spin_unlock_irqrestore(&hisi_hba->lock, flags);
859
860 return sas_dev;
861 }
862
863 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
864 {
865 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
866
867 cfg &= ~PHY_CFG_DC_OPT_MSK;
868 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
869 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
870 }
871
872 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
873 {
874 struct sas_identify_frame identify_frame;
875 u32 *identify_buffer;
876
877 memset(&identify_frame, 0, sizeof(identify_frame));
878 identify_frame.dev_type = SAS_END_DEVICE;
879 identify_frame.frame_type = 0;
880 identify_frame._un1 = 1;
881 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
882 identify_frame.target_bits = SAS_PROTOCOL_NONE;
883 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
884 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
885 identify_frame.phy_id = phy_no;
886 identify_buffer = (u32 *)(&identify_frame);
887
888 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
889 __swab32(identify_buffer[0]));
890 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
891 __swab32(identify_buffer[1]));
892 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
893 __swab32(identify_buffer[2]));
894 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
895 __swab32(identify_buffer[3]));
896 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
897 __swab32(identify_buffer[4]));
898 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
899 __swab32(identify_buffer[5]));
900 }
901
902 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
903 struct hisi_sas_device *sas_dev)
904 {
905 struct domain_device *device = sas_dev->sas_device;
906 struct device *dev = hisi_hba->dev;
907 u64 qw0, device_id = sas_dev->device_id;
908 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
909 struct domain_device *parent_dev = device->parent;
910 struct asd_sas_port *sas_port = device->port;
911 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
912
913 memset(itct, 0, sizeof(*itct));
914
915 /* qw0 */
916 qw0 = 0;
917 switch (sas_dev->dev_type) {
918 case SAS_END_DEVICE:
919 case SAS_EDGE_EXPANDER_DEVICE:
920 case SAS_FANOUT_EXPANDER_DEVICE:
921 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
922 break;
923 case SAS_SATA_DEV:
924 case SAS_SATA_PENDING:
925 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
926 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
927 else
928 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
929 break;
930 default:
931 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
932 sas_dev->dev_type);
933 }
934
935 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
936 (device->linkrate << ITCT_HDR_MCR_OFF) |
937 (1 << ITCT_HDR_VLN_OFF) |
938 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
939 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
940 (port->id << ITCT_HDR_PORT_ID_OFF));
941 itct->qw0 = cpu_to_le64(qw0);
942
943 /* qw1 */
944 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
945 itct->sas_addr = __swab64(itct->sas_addr);
946
947 /* qw2 */
948 if (!dev_is_sata(device))
949 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
950 (0x1ULL << ITCT_HDR_BITLT_OFF) |
951 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
952 (0x1ULL << ITCT_HDR_RTOLT_OFF));
953 }
954
955 static void clear_itct_v2_hw(struct hisi_hba *hisi_hba,
956 struct hisi_sas_device *sas_dev)
957 {
958 DECLARE_COMPLETION_ONSTACK(completion);
959 u64 dev_id = sas_dev->device_id;
960 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
961 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
962 int i;
963
964 sas_dev->completion = &completion;
965
966 /* clear the itct interrupt state */
967 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
968 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
969 ENT_INT_SRC3_ITC_INT_MSK);
970
971 for (i = 0; i < 2; i++) {
972 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
973 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
974 wait_for_completion(sas_dev->completion);
975
976 memset(itct, 0, sizeof(struct hisi_sas_itct));
977 }
978 }
979
980 static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
981 {
982 struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
983
984 /* SoC bug workaround */
985 if (dev_is_sata(sas_dev->sas_device))
986 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
987 }
988
989 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
990 {
991 int i, reset_val;
992 u32 val;
993 unsigned long end_time;
994 struct device *dev = hisi_hba->dev;
995
996 /* The mask needs to be set depending on the number of phys */
997 if (hisi_hba->n_phy == 9)
998 reset_val = 0x1fffff;
999 else
1000 reset_val = 0x7ffff;
1001
1002 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1003
1004 /* Disable all of the PHYs */
1005 for (i = 0; i < hisi_hba->n_phy; i++) {
1006 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1007
1008 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1009 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1010 }
1011 udelay(50);
1012
1013 /* Ensure DMA tx & rx idle */
1014 for (i = 0; i < hisi_hba->n_phy; i++) {
1015 u32 dma_tx_status, dma_rx_status;
1016
1017 end_time = jiffies + msecs_to_jiffies(1000);
1018
1019 while (1) {
1020 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1021 DMA_TX_STATUS);
1022 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1023 DMA_RX_STATUS);
1024
1025 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1026 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1027 break;
1028
1029 msleep(20);
1030 if (time_after(jiffies, end_time))
1031 return -EIO;
1032 }
1033 }
1034
1035 /* Ensure axi bus idle */
1036 end_time = jiffies + msecs_to_jiffies(1000);
1037 while (1) {
1038 u32 axi_status =
1039 hisi_sas_read32(hisi_hba, AXI_CFG);
1040
1041 if (axi_status == 0)
1042 break;
1043
1044 msleep(20);
1045 if (time_after(jiffies, end_time))
1046 return -EIO;
1047 }
1048
1049 if (ACPI_HANDLE(dev)) {
1050 acpi_status s;
1051
1052 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1053 if (ACPI_FAILURE(s)) {
1054 dev_err(dev, "Reset failed\n");
1055 return -EIO;
1056 }
1057 } else if (hisi_hba->ctrl) {
1058 /* reset and disable clock*/
1059 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1060 reset_val);
1061 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1062 reset_val);
1063 msleep(1);
1064 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1065 if (reset_val != (val & reset_val)) {
1066 dev_err(dev, "SAS reset fail.\n");
1067 return -EIO;
1068 }
1069
1070 /* De-reset and enable clock*/
1071 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1072 reset_val);
1073 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1074 reset_val);
1075 msleep(1);
1076 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1077 &val);
1078 if (val & reset_val) {
1079 dev_err(dev, "SAS de-reset fail.\n");
1080 return -EIO;
1081 }
1082 } else
1083 dev_warn(dev, "no reset method\n");
1084
1085 return 0;
1086 }
1087
1088 /* This function needs to be called after resetting SAS controller. */
1089 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1090 {
1091 u32 cfg;
1092 int phy_no;
1093
1094 hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1095 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1096 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1097 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1098 continue;
1099
1100 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1101 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1102 }
1103 }
1104
1105 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1106 {
1107 int phy_no;
1108 u32 dma_tx_dfx1;
1109
1110 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1111 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1112 continue;
1113
1114 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1115 DMA_TX_DFX1);
1116 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1117 u32 cfg = hisi_sas_phy_read32(hisi_hba,
1118 phy_no, CON_CONTROL);
1119
1120 cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1121 hisi_sas_phy_write32(hisi_hba, phy_no,
1122 CON_CONTROL, cfg);
1123 clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1124 }
1125 }
1126 }
1127
1128 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1129 {
1130 struct device *dev = hisi_hba->dev;
1131 int i;
1132
1133 /* Global registers init */
1134
1135 /* Deal with am-max-transmissions quirk */
1136 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1137 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1138 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1139 0x2020);
1140 } /* Else, use defaults -> do nothing */
1141
1142 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1143 (u32)((1ULL << hisi_hba->queue_count) - 1));
1144 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1145 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1146 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1147 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1148 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1149 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1150 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1151 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1152 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1153 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1154 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1155 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1156 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1157 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1158 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1159 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1160 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1161 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1162 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1163 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1164 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1165 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1166 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1167 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1168 for (i = 0; i < hisi_hba->queue_count; i++)
1169 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1170
1171 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1172 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1173
1174 for (i = 0; i < hisi_hba->n_phy; i++) {
1175 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
1176 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
1177 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1178 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1179 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1180 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1181 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1182 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1183 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1184 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1185 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1186 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
1187 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1188 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1189 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1190 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1191 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1192 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1193 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1194 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1195 if (hisi_hba->refclk_frequency_mhz == 66)
1196 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1197 /* else, do nothing -> leave it how you found it */
1198 }
1199
1200 for (i = 0; i < hisi_hba->queue_count; i++) {
1201 /* Delivery queue */
1202 hisi_sas_write32(hisi_hba,
1203 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1204 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1205
1206 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1207 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1208
1209 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1210 HISI_SAS_QUEUE_SLOTS);
1211
1212 /* Completion queue */
1213 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1214 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1215
1216 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1217 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1218
1219 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1220 HISI_SAS_QUEUE_SLOTS);
1221 }
1222
1223 /* itct */
1224 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1225 lower_32_bits(hisi_hba->itct_dma));
1226
1227 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1228 upper_32_bits(hisi_hba->itct_dma));
1229
1230 /* iost */
1231 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1232 lower_32_bits(hisi_hba->iost_dma));
1233
1234 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1235 upper_32_bits(hisi_hba->iost_dma));
1236
1237 /* breakpoint */
1238 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1239 lower_32_bits(hisi_hba->breakpoint_dma));
1240
1241 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1242 upper_32_bits(hisi_hba->breakpoint_dma));
1243
1244 /* SATA broken msg */
1245 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1246 lower_32_bits(hisi_hba->sata_breakpoint_dma));
1247
1248 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1249 upper_32_bits(hisi_hba->sata_breakpoint_dma));
1250
1251 /* SATA initial fis */
1252 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1253 lower_32_bits(hisi_hba->initial_fis_dma));
1254
1255 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1256 upper_32_bits(hisi_hba->initial_fis_dma));
1257 }
1258
1259 static void link_timeout_enable_link(struct timer_list *t)
1260 {
1261 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1262 int i, reg_val;
1263
1264 for (i = 0; i < hisi_hba->n_phy; i++) {
1265 if (hisi_hba->reject_stp_links_msk & BIT(i))
1266 continue;
1267
1268 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1269 if (!(reg_val & BIT(0))) {
1270 hisi_sas_phy_write32(hisi_hba, i,
1271 CON_CONTROL, 0x7);
1272 break;
1273 }
1274 }
1275
1276 hisi_hba->timer.function = link_timeout_disable_link;
1277 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1278 }
1279
1280 static void link_timeout_disable_link(struct timer_list *t)
1281 {
1282 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1283 int i, reg_val;
1284
1285 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1286 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1287 if (hisi_hba->reject_stp_links_msk & BIT(i))
1288 continue;
1289
1290 if (reg_val & BIT(i)) {
1291 hisi_sas_phy_write32(hisi_hba, i,
1292 CON_CONTROL, 0x6);
1293 break;
1294 }
1295 }
1296
1297 hisi_hba->timer.function = link_timeout_enable_link;
1298 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1299 }
1300
1301 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1302 {
1303 hisi_hba->timer.function = link_timeout_disable_link;
1304 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1305 add_timer(&hisi_hba->timer);
1306 }
1307
1308 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1309 {
1310 struct device *dev = hisi_hba->dev;
1311 int rc;
1312
1313 rc = reset_hw_v2_hw(hisi_hba);
1314 if (rc) {
1315 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1316 return rc;
1317 }
1318
1319 msleep(100);
1320 init_reg_v2_hw(hisi_hba);
1321
1322 return 0;
1323 }
1324
1325 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1326 {
1327 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1328
1329 cfg |= PHY_CFG_ENA_MSK;
1330 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1331 }
1332
1333 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1334 {
1335 u32 context;
1336
1337 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1338 if (context & (1 << phy_no))
1339 return true;
1340
1341 return false;
1342 }
1343
1344 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1345 {
1346 u32 dfx_val;
1347
1348 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1349
1350 if (dfx_val & BIT(16))
1351 return false;
1352
1353 return true;
1354 }
1355
1356 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1357 {
1358 int i, max_loop = 1000;
1359 struct device *dev = hisi_hba->dev;
1360 u32 status, axi_status, dfx_val, dfx_tx_val;
1361
1362 for (i = 0; i < max_loop; i++) {
1363 status = hisi_sas_read32_relaxed(hisi_hba,
1364 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1365
1366 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1367 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1368 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1369 phy_no, DMA_TX_FIFO_DFX0);
1370
1371 if ((status == 0x3) && (axi_status == 0x0) &&
1372 (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1373 return true;
1374 udelay(10);
1375 }
1376 dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1377 phy_no, status, axi_status,
1378 dfx_val, dfx_tx_val);
1379 return false;
1380 }
1381
1382 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1383 {
1384 int i, max_loop = 1000;
1385 struct device *dev = hisi_hba->dev;
1386 u32 status, tx_dfx0;
1387
1388 for (i = 0; i < max_loop; i++) {
1389 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1390 status = (status & 0x3fc0) >> 6;
1391
1392 if (status != 0x1)
1393 return true;
1394
1395 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1396 if ((tx_dfx0 & 0x1ff) == 0x2)
1397 return true;
1398 udelay(10);
1399 }
1400 dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1401 phy_no, status, tx_dfx0);
1402 return false;
1403 }
1404
1405 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1406 {
1407 if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1408 return true;
1409
1410 if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1411 return false;
1412
1413 if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1414 return false;
1415
1416 return true;
1417 }
1418
1419
1420 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1421 {
1422 u32 cfg, axi_val, dfx0_val, txid_auto;
1423 struct device *dev = hisi_hba->dev;
1424
1425 /* Close axi bus. */
1426 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1427 AM_CTRL_GLOBAL);
1428 axi_val |= 0x1;
1429 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1430 AM_CTRL_GLOBAL, axi_val);
1431
1432 if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1433 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1434 goto do_disable;
1435
1436 /* Reset host controller. */
1437 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1438 return;
1439 }
1440
1441 dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1442 dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1443 if (dfx0_val != 0x4)
1444 goto do_disable;
1445
1446 if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1447 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1448 phy_no);
1449 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1450 TXID_AUTO);
1451 txid_auto |= TXID_AUTO_CTB_MSK;
1452 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1453 txid_auto);
1454 }
1455
1456 do_disable:
1457 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1458 cfg &= ~PHY_CFG_ENA_MSK;
1459 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1460
1461 /* Open axi bus. */
1462 axi_val &= ~0x1;
1463 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1464 AM_CTRL_GLOBAL, axi_val);
1465 }
1466
1467 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1468 {
1469 config_id_frame_v2_hw(hisi_hba, phy_no);
1470 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1471 enable_phy_v2_hw(hisi_hba, phy_no);
1472 }
1473
1474 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1475 {
1476 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1477 u32 txid_auto;
1478
1479 disable_phy_v2_hw(hisi_hba, phy_no);
1480 if (phy->identify.device_type == SAS_END_DEVICE) {
1481 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1482 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1483 txid_auto | TX_HARDRST_MSK);
1484 }
1485 msleep(100);
1486 start_phy_v2_hw(hisi_hba, phy_no);
1487 }
1488
1489 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1490 {
1491 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1492 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1493 struct sas_phy *sphy = sas_phy->phy;
1494 u32 err4_reg_val, err6_reg_val;
1495
1496 /* loss dword syn, phy reset problem */
1497 err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1498
1499 /* disparity err, invalid dword */
1500 err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1501
1502 sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1503 sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1504 sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1505 sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1506 }
1507
1508 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1509 {
1510 int i;
1511
1512 for (i = 0; i < hisi_hba->n_phy; i++) {
1513 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1514 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1515
1516 if (!sas_phy->phy->enabled)
1517 continue;
1518
1519 start_phy_v2_hw(hisi_hba, i);
1520 }
1521 }
1522
1523 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1524 {
1525 u32 sl_control;
1526
1527 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1528 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1529 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1530 msleep(1);
1531 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1532 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1533 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1534 }
1535
1536 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1537 {
1538 return SAS_LINK_RATE_12_0_GBPS;
1539 }
1540
1541 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1542 struct sas_phy_linkrates *r)
1543 {
1544 u32 prog_phy_link_rate =
1545 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1546 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1547 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1548 int i;
1549 enum sas_linkrate min, max;
1550 u32 rate_mask = 0;
1551
1552 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1553 max = sas_phy->phy->maximum_linkrate;
1554 min = r->minimum_linkrate;
1555 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1556 max = r->maximum_linkrate;
1557 min = sas_phy->phy->minimum_linkrate;
1558 } else
1559 return;
1560
1561 sas_phy->phy->maximum_linkrate = max;
1562 sas_phy->phy->minimum_linkrate = min;
1563
1564 min -= SAS_LINK_RATE_1_5_GBPS;
1565 max -= SAS_LINK_RATE_1_5_GBPS;
1566
1567 for (i = 0; i <= max; i++)
1568 rate_mask |= 1 << (i * 2);
1569
1570 prog_phy_link_rate &= ~0xff;
1571 prog_phy_link_rate |= rate_mask;
1572
1573 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1574 prog_phy_link_rate);
1575
1576 phy_hard_reset_v2_hw(hisi_hba, phy_no);
1577 }
1578
1579 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1580 {
1581 int i, bitmap = 0;
1582 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1583 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1584
1585 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1586 if (phy_state & 1 << i)
1587 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1588 bitmap |= 1 << i;
1589
1590 if (hisi_hba->n_phy == 9) {
1591 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1592
1593 if (phy_state & 1 << 8)
1594 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1595 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1596 bitmap |= 1 << 9;
1597 }
1598
1599 return bitmap;
1600 }
1601
1602 /*
1603 * The callpath to this function and upto writing the write
1604 * queue pointer should be safe from interruption.
1605 */
1606 static int
1607 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1608 {
1609 struct device *dev = hisi_hba->dev;
1610 int queue = dq->id;
1611 u32 r, w;
1612
1613 w = dq->wr_point;
1614 r = hisi_sas_read32_relaxed(hisi_hba,
1615 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1616 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1617 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
1618 queue, r, w);
1619 return -EAGAIN;
1620 }
1621
1622 return 0;
1623 }
1624
1625 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1626 {
1627 struct hisi_hba *hisi_hba = dq->hisi_hba;
1628 int dlvry_queue = dq->slot_prep->dlvry_queue;
1629 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
1630
1631 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1632 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1633 dq->wr_point);
1634 }
1635
1636 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1637 struct hisi_sas_slot *slot,
1638 struct hisi_sas_cmd_hdr *hdr,
1639 struct scatterlist *scatter,
1640 int n_elem)
1641 {
1642 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1643 struct device *dev = hisi_hba->dev;
1644 struct scatterlist *sg;
1645 int i;
1646
1647 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1648 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1649 n_elem);
1650 return -EINVAL;
1651 }
1652
1653 for_each_sg(scatter, sg, n_elem, i) {
1654 struct hisi_sas_sge *entry = &sge_page->sge[i];
1655
1656 entry->addr = cpu_to_le64(sg_dma_address(sg));
1657 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1658 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1659 entry->data_off = 0;
1660 }
1661
1662 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1663
1664 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1665
1666 return 0;
1667 }
1668
1669 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1670 struct hisi_sas_slot *slot)
1671 {
1672 struct sas_task *task = slot->task;
1673 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1674 struct domain_device *device = task->dev;
1675 struct device *dev = hisi_hba->dev;
1676 struct hisi_sas_port *port = slot->port;
1677 struct scatterlist *sg_req, *sg_resp;
1678 struct hisi_sas_device *sas_dev = device->lldd_dev;
1679 dma_addr_t req_dma_addr;
1680 unsigned int req_len, resp_len;
1681 int elem, rc;
1682
1683 /*
1684 * DMA-map SMP request, response buffers
1685 */
1686 /* req */
1687 sg_req = &task->smp_task.smp_req;
1688 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1689 if (!elem)
1690 return -ENOMEM;
1691 req_len = sg_dma_len(sg_req);
1692 req_dma_addr = sg_dma_address(sg_req);
1693
1694 /* resp */
1695 sg_resp = &task->smp_task.smp_resp;
1696 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1697 if (!elem) {
1698 rc = -ENOMEM;
1699 goto err_out_req;
1700 }
1701 resp_len = sg_dma_len(sg_resp);
1702 if ((req_len & 0x3) || (resp_len & 0x3)) {
1703 rc = -EINVAL;
1704 goto err_out_resp;
1705 }
1706
1707 /* create header */
1708 /* dw0 */
1709 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1710 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1711 (2 << CMD_HDR_CMD_OFF)); /* smp */
1712
1713 /* map itct entry */
1714 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1715 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1716 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1717
1718 /* dw2 */
1719 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1720 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1721 CMD_HDR_MRFL_OFF));
1722
1723 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1724
1725 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1726 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1727
1728 return 0;
1729
1730 err_out_resp:
1731 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1732 DMA_FROM_DEVICE);
1733 err_out_req:
1734 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1735 DMA_TO_DEVICE);
1736 return rc;
1737 }
1738
1739 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1740 struct hisi_sas_slot *slot, int is_tmf,
1741 struct hisi_sas_tmf_task *tmf)
1742 {
1743 struct sas_task *task = slot->task;
1744 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1745 struct domain_device *device = task->dev;
1746 struct hisi_sas_device *sas_dev = device->lldd_dev;
1747 struct hisi_sas_port *port = slot->port;
1748 struct sas_ssp_task *ssp_task = &task->ssp_task;
1749 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1750 int has_data = 0, rc, priority = is_tmf;
1751 u8 *buf_cmd;
1752 u32 dw1 = 0, dw2 = 0;
1753
1754 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1755 (2 << CMD_HDR_TLR_CTRL_OFF) |
1756 (port->id << CMD_HDR_PORT_OFF) |
1757 (priority << CMD_HDR_PRIORITY_OFF) |
1758 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1759
1760 dw1 = 1 << CMD_HDR_VDTL_OFF;
1761 if (is_tmf) {
1762 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1763 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1764 } else {
1765 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1766 switch (scsi_cmnd->sc_data_direction) {
1767 case DMA_TO_DEVICE:
1768 has_data = 1;
1769 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1770 break;
1771 case DMA_FROM_DEVICE:
1772 has_data = 1;
1773 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1774 break;
1775 default:
1776 dw1 &= ~CMD_HDR_DIR_MSK;
1777 }
1778 }
1779
1780 /* map itct entry */
1781 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1782 hdr->dw1 = cpu_to_le32(dw1);
1783
1784 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1785 + 3) / 4) << CMD_HDR_CFL_OFF) |
1786 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1787 (2 << CMD_HDR_SG_MOD_OFF);
1788 hdr->dw2 = cpu_to_le32(dw2);
1789
1790 hdr->transfer_tags = cpu_to_le32(slot->idx);
1791
1792 if (has_data) {
1793 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1794 slot->n_elem);
1795 if (rc)
1796 return rc;
1797 }
1798
1799 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1800 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1801 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1802
1803 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1804 sizeof(struct ssp_frame_hdr);
1805
1806 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1807 if (!is_tmf) {
1808 buf_cmd[9] = task->ssp_task.task_attr |
1809 (task->ssp_task.task_prio << 3);
1810 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1811 task->ssp_task.cmd->cmd_len);
1812 } else {
1813 buf_cmd[10] = tmf->tmf;
1814 switch (tmf->tmf) {
1815 case TMF_ABORT_TASK:
1816 case TMF_QUERY_TASK:
1817 buf_cmd[12] =
1818 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1819 buf_cmd[13] =
1820 tmf->tag_of_task_to_be_managed & 0xff;
1821 break;
1822 default:
1823 break;
1824 }
1825 }
1826
1827 return 0;
1828 }
1829
1830 #define TRANS_TX_ERR 0
1831 #define TRANS_RX_ERR 1
1832 #define DMA_TX_ERR 2
1833 #define SIPC_RX_ERR 3
1834 #define DMA_RX_ERR 4
1835
1836 #define DMA_TX_ERR_OFF 0
1837 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1838 #define SIPC_RX_ERR_OFF 16
1839 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1840
1841 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1842 {
1843 static const u8 trans_tx_err_code_prio[] = {
1844 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1845 TRANS_TX_ERR_PHY_NOT_ENABLE,
1846 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1847 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1848 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1849 RESERVED0,
1850 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1851 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1852 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1853 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1854 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1855 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1856 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1857 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1858 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1859 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1860 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1861 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1862 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1863 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1864 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1865 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1866 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1867 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1868 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1869 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1870 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1871 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1872 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1873 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1874 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1875 };
1876 int index, i;
1877
1878 for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1879 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1880 if (err_msk & (1 << index))
1881 return trans_tx_err_code_prio[i];
1882 }
1883 return -1;
1884 }
1885
1886 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1887 {
1888 static const u8 trans_rx_err_code_prio[] = {
1889 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1890 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1891 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1892 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1893 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1894 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1895 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1896 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1897 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1898 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1899 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1900 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1901 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1902 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1903 RESERVED1,
1904 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1905 TRANS_RX_ERR_WITH_DATA_LEN0,
1906 TRANS_RX_ERR_WITH_BAD_HASH,
1907 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1908 TRANS_RX_SSP_FRM_LEN_ERR,
1909 RESERVED2,
1910 RESERVED3,
1911 RESERVED4,
1912 RESERVED5,
1913 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1914 TRANS_RX_SMP_FRM_LEN_ERR,
1915 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1916 RESERVED6,
1917 RESERVED7,
1918 RESERVED8,
1919 RESERVED9,
1920 TRANS_RX_R_ERR,
1921 };
1922 int index, i;
1923
1924 for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1925 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1926 if (err_msk & (1 << index))
1927 return trans_rx_err_code_prio[i];
1928 }
1929 return -1;
1930 }
1931
1932 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1933 {
1934 static const u8 dma_tx_err_code_prio[] = {
1935 DMA_TX_UNEXP_XFER_ERR,
1936 DMA_TX_UNEXP_RETRANS_ERR,
1937 DMA_TX_XFER_LEN_OVERFLOW,
1938 DMA_TX_XFER_OFFSET_ERR,
1939 DMA_TX_RAM_ECC_ERR,
1940 DMA_TX_DIF_LEN_ALIGN_ERR,
1941 DMA_TX_DIF_CRC_ERR,
1942 DMA_TX_DIF_APP_ERR,
1943 DMA_TX_DIF_RPP_ERR,
1944 DMA_TX_DATA_SGL_OVERFLOW,
1945 DMA_TX_DIF_SGL_OVERFLOW,
1946 };
1947 int index, i;
1948
1949 for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1950 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1951 err_msk = err_msk & DMA_TX_ERR_MSK;
1952 if (err_msk & (1 << index))
1953 return dma_tx_err_code_prio[i];
1954 }
1955 return -1;
1956 }
1957
1958 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1959 {
1960 static const u8 sipc_rx_err_code_prio[] = {
1961 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1962 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1963 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1964 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1965 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1966 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1967 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1968 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1969 SIPC_RX_SATA_UNEXP_FIS_ERR,
1970 SIPC_RX_WRSETUP_ESTATUS_ERR,
1971 SIPC_RX_DATA_UNDERFLOW_ERR,
1972 };
1973 int index, i;
1974
1975 for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1976 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1977 err_msk = err_msk & SIPC_RX_ERR_MSK;
1978 if (err_msk & (1 << (index + 0x10)))
1979 return sipc_rx_err_code_prio[i];
1980 }
1981 return -1;
1982 }
1983
1984 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
1985 {
1986 static const u8 dma_rx_err_code_prio[] = {
1987 DMA_RX_UNKNOWN_FRM_ERR,
1988 DMA_RX_DATA_LEN_OVERFLOW,
1989 DMA_RX_DATA_LEN_UNDERFLOW,
1990 DMA_RX_DATA_OFFSET_ERR,
1991 RESERVED10,
1992 DMA_RX_SATA_FRAME_TYPE_ERR,
1993 DMA_RX_RESP_BUF_OVERFLOW,
1994 DMA_RX_UNEXP_RETRANS_RESP_ERR,
1995 DMA_RX_UNEXP_NORM_RESP_ERR,
1996 DMA_RX_UNEXP_RDFRAME_ERR,
1997 DMA_RX_PIO_DATA_LEN_ERR,
1998 DMA_RX_RDSETUP_STATUS_ERR,
1999 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2000 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2001 DMA_RX_RDSETUP_LEN_ODD_ERR,
2002 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2003 DMA_RX_RDSETUP_LEN_OVER_ERR,
2004 DMA_RX_RDSETUP_OFFSET_ERR,
2005 DMA_RX_RDSETUP_ACTIVE_ERR,
2006 DMA_RX_RDSETUP_ESTATUS_ERR,
2007 DMA_RX_RAM_ECC_ERR,
2008 DMA_RX_DIF_CRC_ERR,
2009 DMA_RX_DIF_APP_ERR,
2010 DMA_RX_DIF_RPP_ERR,
2011 DMA_RX_DATA_SGL_OVERFLOW,
2012 DMA_RX_DIF_SGL_OVERFLOW,
2013 };
2014 int index, i;
2015
2016 for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2017 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2018 if (err_msk & (1 << index))
2019 return dma_rx_err_code_prio[i];
2020 }
2021 return -1;
2022 }
2023
2024 /* by default, task resp is complete */
2025 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2026 struct sas_task *task,
2027 struct hisi_sas_slot *slot,
2028 int err_phase)
2029 {
2030 struct task_status_struct *ts = &task->task_status;
2031 struct hisi_sas_err_record_v2 *err_record =
2032 hisi_sas_status_buf_addr_mem(slot);
2033 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2034 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2035 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2036 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2037 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2038 int error = -1;
2039
2040 if (err_phase == 1) {
2041 /* error in TX phase, the priority of error is: DW2 > DW0 */
2042 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2043 if (error == -1)
2044 error = parse_trans_tx_err_code_v2_hw(
2045 trans_tx_fail_type);
2046 } else if (err_phase == 2) {
2047 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2048 error = parse_trans_rx_err_code_v2_hw(
2049 trans_rx_fail_type);
2050 if (error == -1) {
2051 error = parse_dma_rx_err_code_v2_hw(
2052 dma_rx_err_type);
2053 if (error == -1)
2054 error = parse_sipc_rx_err_code_v2_hw(
2055 sipc_rx_err_type);
2056 }
2057 }
2058
2059 switch (task->task_proto) {
2060 case SAS_PROTOCOL_SSP:
2061 {
2062 switch (error) {
2063 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2064 {
2065 ts->stat = SAS_OPEN_REJECT;
2066 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2067 break;
2068 }
2069 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2070 {
2071 ts->stat = SAS_OPEN_REJECT;
2072 ts->open_rej_reason = SAS_OREJ_EPROTO;
2073 break;
2074 }
2075 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2076 {
2077 ts->stat = SAS_OPEN_REJECT;
2078 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2079 break;
2080 }
2081 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2082 {
2083 ts->stat = SAS_OPEN_REJECT;
2084 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2085 break;
2086 }
2087 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2088 {
2089 ts->stat = SAS_OPEN_REJECT;
2090 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2091 break;
2092 }
2093 case DMA_RX_UNEXP_NORM_RESP_ERR:
2094 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2095 case DMA_RX_RESP_BUF_OVERFLOW:
2096 {
2097 ts->stat = SAS_OPEN_REJECT;
2098 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2099 break;
2100 }
2101 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2102 {
2103 /* not sure */
2104 ts->stat = SAS_DEV_NO_RESPONSE;
2105 break;
2106 }
2107 case DMA_RX_DATA_LEN_OVERFLOW:
2108 {
2109 ts->stat = SAS_DATA_OVERRUN;
2110 ts->residual = 0;
2111 break;
2112 }
2113 case DMA_RX_DATA_LEN_UNDERFLOW:
2114 {
2115 ts->residual = trans_tx_fail_type;
2116 ts->stat = SAS_DATA_UNDERRUN;
2117 break;
2118 }
2119 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2120 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2121 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2122 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2123 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2124 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2125 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2126 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2127 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2128 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2129 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2130 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2131 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2132 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2133 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2134 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2135 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2136 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2137 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2138 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2139 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2140 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2141 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2142 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2143 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2144 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2145 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2146 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2147 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2148 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2149 case TRANS_TX_ERR_FRAME_TXED:
2150 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2151 case TRANS_RX_ERR_WITH_DATA_LEN0:
2152 case TRANS_RX_ERR_WITH_BAD_HASH:
2153 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2154 case TRANS_RX_SSP_FRM_LEN_ERR:
2155 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2156 case DMA_TX_DATA_SGL_OVERFLOW:
2157 case DMA_TX_UNEXP_XFER_ERR:
2158 case DMA_TX_UNEXP_RETRANS_ERR:
2159 case DMA_TX_XFER_LEN_OVERFLOW:
2160 case DMA_TX_XFER_OFFSET_ERR:
2161 case SIPC_RX_DATA_UNDERFLOW_ERR:
2162 case DMA_RX_DATA_SGL_OVERFLOW:
2163 case DMA_RX_DATA_OFFSET_ERR:
2164 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2165 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2166 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2167 case DMA_RX_SATA_FRAME_TYPE_ERR:
2168 case DMA_RX_UNKNOWN_FRM_ERR:
2169 {
2170 /* This will request a retry */
2171 ts->stat = SAS_QUEUE_FULL;
2172 slot->abort = 1;
2173 break;
2174 }
2175 default:
2176 break;
2177 }
2178 }
2179 break;
2180 case SAS_PROTOCOL_SMP:
2181 ts->stat = SAM_STAT_CHECK_CONDITION;
2182 break;
2183
2184 case SAS_PROTOCOL_SATA:
2185 case SAS_PROTOCOL_STP:
2186 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2187 {
2188 switch (error) {
2189 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2190 {
2191 ts->stat = SAS_OPEN_REJECT;
2192 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2193 break;
2194 }
2195 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2196 {
2197 ts->resp = SAS_TASK_UNDELIVERED;
2198 ts->stat = SAS_DEV_NO_RESPONSE;
2199 break;
2200 }
2201 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2202 {
2203 ts->stat = SAS_OPEN_REJECT;
2204 ts->open_rej_reason = SAS_OREJ_EPROTO;
2205 break;
2206 }
2207 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2208 {
2209 ts->stat = SAS_OPEN_REJECT;
2210 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2211 break;
2212 }
2213 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2214 {
2215 ts->stat = SAS_OPEN_REJECT;
2216 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2217 break;
2218 }
2219 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2220 {
2221 ts->stat = SAS_OPEN_REJECT;
2222 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2223 break;
2224 }
2225 case DMA_RX_RESP_BUF_OVERFLOW:
2226 case DMA_RX_UNEXP_NORM_RESP_ERR:
2227 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2228 {
2229 ts->stat = SAS_OPEN_REJECT;
2230 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2231 break;
2232 }
2233 case DMA_RX_DATA_LEN_OVERFLOW:
2234 {
2235 ts->stat = SAS_DATA_OVERRUN;
2236 ts->residual = 0;
2237 break;
2238 }
2239 case DMA_RX_DATA_LEN_UNDERFLOW:
2240 {
2241 ts->residual = trans_tx_fail_type;
2242 ts->stat = SAS_DATA_UNDERRUN;
2243 break;
2244 }
2245 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2246 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2247 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2248 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2249 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2250 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2251 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2252 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2253 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2254 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2255 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2256 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2257 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2258 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2259 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2260 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2261 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2262 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2263 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2264 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2265 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2266 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2267 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2268 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2269 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2270 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2271 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2272 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2273 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2274 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2275 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2276 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2277 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2278 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2279 case TRANS_RX_ERR_WITH_DATA_LEN0:
2280 case TRANS_RX_ERR_WITH_BAD_HASH:
2281 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2282 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2283 case DMA_TX_DATA_SGL_OVERFLOW:
2284 case DMA_TX_UNEXP_XFER_ERR:
2285 case DMA_TX_UNEXP_RETRANS_ERR:
2286 case DMA_TX_XFER_LEN_OVERFLOW:
2287 case DMA_TX_XFER_OFFSET_ERR:
2288 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2289 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2290 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2291 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2292 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2293 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2294 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2295 case DMA_RX_DATA_SGL_OVERFLOW:
2296 case DMA_RX_DATA_OFFSET_ERR:
2297 case DMA_RX_SATA_FRAME_TYPE_ERR:
2298 case DMA_RX_UNEXP_RDFRAME_ERR:
2299 case DMA_RX_PIO_DATA_LEN_ERR:
2300 case DMA_RX_RDSETUP_STATUS_ERR:
2301 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2302 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2303 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2304 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2305 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2306 case DMA_RX_RDSETUP_OFFSET_ERR:
2307 case DMA_RX_RDSETUP_ACTIVE_ERR:
2308 case DMA_RX_RDSETUP_ESTATUS_ERR:
2309 case DMA_RX_UNKNOWN_FRM_ERR:
2310 case TRANS_RX_SSP_FRM_LEN_ERR:
2311 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2312 {
2313 slot->abort = 1;
2314 ts->stat = SAS_PHY_DOWN;
2315 break;
2316 }
2317 default:
2318 {
2319 ts->stat = SAS_PROTO_RESPONSE;
2320 break;
2321 }
2322 }
2323 hisi_sas_sata_done(task, slot);
2324 }
2325 break;
2326 default:
2327 break;
2328 }
2329 }
2330
2331 static int
2332 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2333 {
2334 struct sas_task *task = slot->task;
2335 struct hisi_sas_device *sas_dev;
2336 struct device *dev = hisi_hba->dev;
2337 struct task_status_struct *ts;
2338 struct domain_device *device;
2339 enum exec_status sts;
2340 struct hisi_sas_complete_v2_hdr *complete_queue =
2341 hisi_hba->complete_hdr[slot->cmplt_queue];
2342 struct hisi_sas_complete_v2_hdr *complete_hdr =
2343 &complete_queue[slot->cmplt_queue_slot];
2344 unsigned long flags;
2345 int aborted;
2346
2347 if (unlikely(!task || !task->lldd_task || !task->dev))
2348 return -EINVAL;
2349
2350 ts = &task->task_status;
2351 device = task->dev;
2352 sas_dev = device->lldd_dev;
2353
2354 spin_lock_irqsave(&task->task_state_lock, flags);
2355 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
2356 task->task_state_flags &=
2357 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2358 spin_unlock_irqrestore(&task->task_state_lock, flags);
2359
2360 memset(ts, 0, sizeof(*ts));
2361 ts->resp = SAS_TASK_COMPLETE;
2362
2363 if (unlikely(aborted)) {
2364 ts->stat = SAS_ABORTED_TASK;
2365 spin_lock_irqsave(&hisi_hba->lock, flags);
2366 hisi_sas_slot_task_free(hisi_hba, task, slot);
2367 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2368 return -1;
2369 }
2370
2371 if (unlikely(!sas_dev)) {
2372 dev_dbg(dev, "slot complete: port has no device\n");
2373 ts->stat = SAS_PHY_DOWN;
2374 goto out;
2375 }
2376
2377 /* Use SAS+TMF status codes */
2378 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2379 >> CMPLT_HDR_ABORT_STAT_OFF) {
2380 case STAT_IO_ABORTED:
2381 /* this io has been aborted by abort command */
2382 ts->stat = SAS_ABORTED_TASK;
2383 goto out;
2384 case STAT_IO_COMPLETE:
2385 /* internal abort command complete */
2386 ts->stat = TMF_RESP_FUNC_SUCC;
2387 del_timer(&slot->internal_abort_timer);
2388 goto out;
2389 case STAT_IO_NO_DEVICE:
2390 ts->stat = TMF_RESP_FUNC_COMPLETE;
2391 del_timer(&slot->internal_abort_timer);
2392 goto out;
2393 case STAT_IO_NOT_VALID:
2394 /* abort single io, controller don't find
2395 * the io need to abort
2396 */
2397 ts->stat = TMF_RESP_FUNC_FAILED;
2398 del_timer(&slot->internal_abort_timer);
2399 goto out;
2400 default:
2401 break;
2402 }
2403
2404 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2405 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2406 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2407 >> CMPLT_HDR_ERR_PHASE_OFF;
2408
2409 /* Analyse error happens on which phase TX or RX */
2410 if (ERR_ON_TX_PHASE(err_phase))
2411 slot_err_v2_hw(hisi_hba, task, slot, 1);
2412 else if (ERR_ON_RX_PHASE(err_phase))
2413 slot_err_v2_hw(hisi_hba, task, slot, 2);
2414
2415 if (unlikely(slot->abort))
2416 return ts->stat;
2417 goto out;
2418 }
2419
2420 switch (task->task_proto) {
2421 case SAS_PROTOCOL_SSP:
2422 {
2423 struct hisi_sas_status_buffer *status_buffer =
2424 hisi_sas_status_buf_addr_mem(slot);
2425 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2426 &status_buffer->iu[0];
2427
2428 sas_ssp_task_response(dev, task, iu);
2429 break;
2430 }
2431 case SAS_PROTOCOL_SMP:
2432 {
2433 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2434 void *to;
2435
2436 ts->stat = SAM_STAT_GOOD;
2437 to = kmap_atomic(sg_page(sg_resp));
2438
2439 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2440 DMA_FROM_DEVICE);
2441 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2442 DMA_TO_DEVICE);
2443 memcpy(to + sg_resp->offset,
2444 hisi_sas_status_buf_addr_mem(slot) +
2445 sizeof(struct hisi_sas_err_record),
2446 sg_dma_len(sg_resp));
2447 kunmap_atomic(to);
2448 break;
2449 }
2450 case SAS_PROTOCOL_SATA:
2451 case SAS_PROTOCOL_STP:
2452 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2453 {
2454 ts->stat = SAM_STAT_GOOD;
2455 hisi_sas_sata_done(task, slot);
2456 break;
2457 }
2458 default:
2459 ts->stat = SAM_STAT_CHECK_CONDITION;
2460 break;
2461 }
2462
2463 if (!slot->port->port_attached) {
2464 dev_err(dev, "slot complete: port %d has removed\n",
2465 slot->port->sas_port.id);
2466 ts->stat = SAS_PHY_DOWN;
2467 }
2468
2469 out:
2470 spin_lock_irqsave(&task->task_state_lock, flags);
2471 task->task_state_flags |= SAS_TASK_STATE_DONE;
2472 spin_unlock_irqrestore(&task->task_state_lock, flags);
2473 spin_lock_irqsave(&hisi_hba->lock, flags);
2474 hisi_sas_slot_task_free(hisi_hba, task, slot);
2475 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2476 sts = ts->stat;
2477
2478 if (task->task_done)
2479 task->task_done(task);
2480
2481 return sts;
2482 }
2483
2484 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2485 struct hisi_sas_slot *slot)
2486 {
2487 struct sas_task *task = slot->task;
2488 struct domain_device *device = task->dev;
2489 struct domain_device *parent_dev = device->parent;
2490 struct hisi_sas_device *sas_dev = device->lldd_dev;
2491 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2492 struct asd_sas_port *sas_port = device->port;
2493 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2494 u8 *buf_cmd;
2495 int has_data = 0, rc = 0, hdr_tag = 0;
2496 u32 dw1 = 0, dw2 = 0;
2497
2498 /* create header */
2499 /* dw0 */
2500 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2501 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2502 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2503 else
2504 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2505
2506 /* dw1 */
2507 switch (task->data_dir) {
2508 case DMA_TO_DEVICE:
2509 has_data = 1;
2510 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2511 break;
2512 case DMA_FROM_DEVICE:
2513 has_data = 1;
2514 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2515 break;
2516 default:
2517 dw1 &= ~CMD_HDR_DIR_MSK;
2518 }
2519
2520 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2521 (task->ata_task.fis.control & ATA_SRST))
2522 dw1 |= 1 << CMD_HDR_RESET_OFF;
2523
2524 dw1 |= (hisi_sas_get_ata_protocol(
2525 task->ata_task.fis.command, task->data_dir))
2526 << CMD_HDR_FRAME_TYPE_OFF;
2527 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2528 hdr->dw1 = cpu_to_le32(dw1);
2529
2530 /* dw2 */
2531 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2532 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2533 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2534 }
2535
2536 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2537 2 << CMD_HDR_SG_MOD_OFF;
2538 hdr->dw2 = cpu_to_le32(dw2);
2539
2540 /* dw3 */
2541 hdr->transfer_tags = cpu_to_le32(slot->idx);
2542
2543 if (has_data) {
2544 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2545 slot->n_elem);
2546 if (rc)
2547 return rc;
2548 }
2549
2550 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2551 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2552 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2553
2554 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2555
2556 if (likely(!task->ata_task.device_control_reg_update))
2557 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2558 /* fill in command FIS */
2559 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2560
2561 return 0;
2562 }
2563
2564 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
2565 {
2566 struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
2567 struct hisi_sas_port *port = slot->port;
2568 struct asd_sas_port *asd_sas_port;
2569 struct asd_sas_phy *sas_phy;
2570
2571 if (!port)
2572 return;
2573
2574 asd_sas_port = &port->sas_port;
2575
2576 /* Kick the hardware - send break command */
2577 list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2578 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2579 struct hisi_hba *hisi_hba = phy->hisi_hba;
2580 int phy_no = sas_phy->id;
2581 u32 link_dfx2;
2582
2583 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2584 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2585 (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2586 u32 txid_auto;
2587
2588 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2589 TXID_AUTO);
2590 txid_auto |= TXID_AUTO_CTB_MSK;
2591 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2592 txid_auto);
2593 return;
2594 }
2595 }
2596 }
2597
2598 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2599 struct hisi_sas_slot *slot,
2600 int device_id, int abort_flag, int tag_to_abort)
2601 {
2602 struct sas_task *task = slot->task;
2603 struct domain_device *dev = task->dev;
2604 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2605 struct hisi_sas_port *port = slot->port;
2606 struct timer_list *timer = &slot->internal_abort_timer;
2607
2608 /* setup the quirk timer */
2609 timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
2610 /* Set the timeout to 10ms less than internal abort timeout */
2611 mod_timer(timer, jiffies + msecs_to_jiffies(100));
2612
2613 /* dw0 */
2614 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2615 (port->id << CMD_HDR_PORT_OFF) |
2616 ((dev_is_sata(dev) ? 1:0) <<
2617 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2618 (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2619
2620 /* dw1 */
2621 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2622
2623 /* dw7 */
2624 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2625 hdr->transfer_tags = cpu_to_le32(slot->idx);
2626
2627 return 0;
2628 }
2629
2630 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2631 {
2632 int i, res = IRQ_HANDLED;
2633 u32 port_id, link_rate, hard_phy_linkrate;
2634 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2635 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2636 struct device *dev = hisi_hba->dev;
2637 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2638 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2639
2640 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2641
2642 if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2643 goto end;
2644
2645 if (phy_no == 8) {
2646 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2647
2648 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2649 PORT_STATE_PHY8_PORT_NUM_OFF;
2650 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2651 PORT_STATE_PHY8_CONN_RATE_OFF;
2652 } else {
2653 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2654 port_id = (port_id >> (4 * phy_no)) & 0xf;
2655 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2656 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2657 }
2658
2659 if (port_id == 0xf) {
2660 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2661 res = IRQ_NONE;
2662 goto end;
2663 }
2664
2665 for (i = 0; i < 6; i++) {
2666 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2667 RX_IDAF_DWORD0 + (i * 4));
2668 frame_rcvd[i] = __swab32(idaf);
2669 }
2670
2671 sas_phy->linkrate = link_rate;
2672 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2673 HARD_PHY_LINKRATE);
2674 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2675 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2676
2677 sas_phy->oob_mode = SAS_OOB_MODE;
2678 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2679 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2680 phy->port_id = port_id;
2681 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2682 phy->phy_type |= PORT_TYPE_SAS;
2683 phy->phy_attached = 1;
2684 phy->identify.device_type = id->dev_type;
2685 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
2686 if (phy->identify.device_type == SAS_END_DEVICE)
2687 phy->identify.target_port_protocols =
2688 SAS_PROTOCOL_SSP;
2689 else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2690 phy->identify.target_port_protocols =
2691 SAS_PROTOCOL_SMP;
2692 if (!timer_pending(&hisi_hba->timer))
2693 set_link_timer_quirk(hisi_hba);
2694 }
2695 queue_work(hisi_hba->wq, &phy->phyup_ws);
2696
2697 end:
2698 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2699 CHL_INT0_SL_PHY_ENABLE_MSK);
2700 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2701
2702 return res;
2703 }
2704
2705 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2706 {
2707 u32 port_state;
2708
2709 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2710 if (port_state & 0x1ff)
2711 return true;
2712
2713 return false;
2714 }
2715
2716 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2717 {
2718 u32 phy_state, sl_ctrl, txid_auto;
2719 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2720 struct hisi_sas_port *port = phy->port;
2721
2722 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2723
2724 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2725 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2726
2727 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2728 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2729 sl_ctrl & ~SL_CONTROL_CTA_MSK);
2730 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2731 if (!check_any_wideports_v2_hw(hisi_hba) &&
2732 timer_pending(&hisi_hba->timer))
2733 del_timer(&hisi_hba->timer);
2734
2735 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2736 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2737 txid_auto | TXID_AUTO_CT3_MSK);
2738
2739 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2740 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2741
2742 return IRQ_HANDLED;
2743 }
2744
2745 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2746 {
2747 struct hisi_hba *hisi_hba = p;
2748 u32 irq_msk;
2749 int phy_no = 0;
2750 irqreturn_t res = IRQ_NONE;
2751
2752 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2753 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2754 while (irq_msk) {
2755 if (irq_msk & 1) {
2756 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2757 CHL_INT0);
2758
2759 switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2760 CHL_INT0_SL_PHY_ENABLE_MSK)) {
2761
2762 case CHL_INT0_SL_PHY_ENABLE_MSK:
2763 /* phy up */
2764 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2765 IRQ_HANDLED)
2766 res = IRQ_HANDLED;
2767 break;
2768
2769 case CHL_INT0_NOT_RDY_MSK:
2770 /* phy down */
2771 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2772 IRQ_HANDLED)
2773 res = IRQ_HANDLED;
2774 break;
2775
2776 case (CHL_INT0_NOT_RDY_MSK |
2777 CHL_INT0_SL_PHY_ENABLE_MSK):
2778 reg_value = hisi_sas_read32(hisi_hba,
2779 PHY_STATE);
2780 if (reg_value & BIT(phy_no)) {
2781 /* phy up */
2782 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2783 IRQ_HANDLED)
2784 res = IRQ_HANDLED;
2785 } else {
2786 /* phy down */
2787 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2788 IRQ_HANDLED)
2789 res = IRQ_HANDLED;
2790 }
2791 break;
2792
2793 default:
2794 break;
2795 }
2796
2797 }
2798 irq_msk >>= 1;
2799 phy_no++;
2800 }
2801
2802 return res;
2803 }
2804
2805 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2806 {
2807 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2808 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2809 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2810 u32 bcast_status;
2811
2812 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2813 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2814 if (bcast_status & RX_BCAST_CHG_MSK)
2815 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2816 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2817 CHL_INT0_SL_RX_BCST_ACK_MSK);
2818 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2819 }
2820
2821 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2822 {
2823 struct hisi_hba *hisi_hba = p;
2824 struct device *dev = hisi_hba->dev;
2825 u32 ent_msk, ent_tmp, irq_msk;
2826 int phy_no = 0;
2827
2828 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2829 ent_tmp = ent_msk;
2830 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2831 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2832
2833 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2834 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2835
2836 while (irq_msk) {
2837 if (irq_msk & (1 << phy_no)) {
2838 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2839 CHL_INT0);
2840 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2841 CHL_INT1);
2842 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2843 CHL_INT2);
2844
2845 if (irq_value1) {
2846 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
2847 CHL_INT1_DMAC_TX_ECC_ERR_MSK))
2848 panic("%s: DMAC RX/TX ecc bad error!\
2849 (0x%x)",
2850 dev_name(dev), irq_value1);
2851
2852 hisi_sas_phy_write32(hisi_hba, phy_no,
2853 CHL_INT1, irq_value1);
2854 }
2855
2856 if (irq_value2)
2857 hisi_sas_phy_write32(hisi_hba, phy_no,
2858 CHL_INT2, irq_value2);
2859
2860
2861 if (irq_value0) {
2862 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2863 phy_bcast_v2_hw(phy_no, hisi_hba);
2864
2865 hisi_sas_phy_write32(hisi_hba, phy_no,
2866 CHL_INT0, irq_value0
2867 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2868 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2869 & (~CHL_INT0_NOT_RDY_MSK));
2870 }
2871 }
2872 irq_msk &= ~(1 << phy_no);
2873 phy_no++;
2874 }
2875
2876 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2877
2878 return IRQ_HANDLED;
2879 }
2880
2881 static void
2882 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2883 {
2884 struct device *dev = hisi_hba->dev;
2885 const struct hisi_sas_hw_error *ecc_error;
2886 u32 val;
2887 int i;
2888
2889 for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2890 ecc_error = &one_bit_ecc_errors[i];
2891 if (irq_value & ecc_error->irq_msk) {
2892 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2893 val &= ecc_error->msk;
2894 val >>= ecc_error->shift;
2895 dev_warn(dev, ecc_error->msg, val);
2896 }
2897 }
2898 }
2899
2900 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2901 u32 irq_value)
2902 {
2903 struct device *dev = hisi_hba->dev;
2904 const struct hisi_sas_hw_error *ecc_error;
2905 u32 val;
2906 int i;
2907
2908 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2909 ecc_error = &multi_bit_ecc_errors[i];
2910 if (irq_value & ecc_error->irq_msk) {
2911 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2912 val &= ecc_error->msk;
2913 val >>= ecc_error->shift;
2914 dev_warn(dev, ecc_error->msg, irq_value, val);
2915 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2916 }
2917 }
2918
2919 return;
2920 }
2921
2922 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
2923 {
2924 struct hisi_hba *hisi_hba = p;
2925 u32 irq_value, irq_msk;
2926
2927 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2928 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
2929
2930 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2931 if (irq_value) {
2932 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2933 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2934 }
2935
2936 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2937 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2938
2939 return IRQ_HANDLED;
2940 }
2941
2942 static const struct hisi_sas_hw_error axi_error[] = {
2943 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
2944 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
2945 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
2946 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
2947 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
2948 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
2949 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
2950 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
2951 {},
2952 };
2953
2954 static const struct hisi_sas_hw_error fifo_error[] = {
2955 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
2956 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
2957 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
2958 { .msk = BIT(11), .msg = "CMDP_FIFO" },
2959 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
2960 {},
2961 };
2962
2963 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
2964 {
2965 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
2966 .msg = "write pointer and depth",
2967 },
2968 {
2969 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
2970 .msg = "iptt no match slot",
2971 },
2972 {
2973 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
2974 .msg = "read pointer and depth",
2975 },
2976 {
2977 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
2978 .reg = HGC_AXI_FIFO_ERR_INFO,
2979 .sub = axi_error,
2980 },
2981 {
2982 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
2983 .reg = HGC_AXI_FIFO_ERR_INFO,
2984 .sub = fifo_error,
2985 },
2986 {
2987 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
2988 .msg = "LM add/fetch list",
2989 },
2990 {
2991 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
2992 .msg = "SAS_HGC_ABT fetch LM list",
2993 },
2994 };
2995
2996 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
2997 {
2998 struct hisi_hba *hisi_hba = p;
2999 u32 irq_value, irq_msk, err_value;
3000 struct device *dev = hisi_hba->dev;
3001 const struct hisi_sas_hw_error *axi_error;
3002 int i;
3003
3004 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3005 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3006
3007 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3008
3009 for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3010 axi_error = &fatal_axi_errors[i];
3011 if (!(irq_value & axi_error->irq_msk))
3012 continue;
3013
3014 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3015 1 << axi_error->shift);
3016 if (axi_error->sub) {
3017 const struct hisi_sas_hw_error *sub = axi_error->sub;
3018
3019 err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3020 for (; sub->msk || sub->msg; sub++) {
3021 if (!(err_value & sub->msk))
3022 continue;
3023 dev_warn(dev, "%s (0x%x) found!\n",
3024 sub->msg, irq_value);
3025 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3026 }
3027 } else {
3028 dev_warn(dev, "%s (0x%x) found!\n",
3029 axi_error->msg, irq_value);
3030 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3031 }
3032 }
3033
3034 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3035 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3036 u32 dev_id = reg_val & ITCT_DEV_MSK;
3037 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3038
3039 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3040 dev_dbg(dev, "clear ITCT ok\n");
3041 complete(sas_dev->completion);
3042 }
3043
3044 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3045 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3046
3047 return IRQ_HANDLED;
3048 }
3049
3050 static void cq_tasklet_v2_hw(unsigned long val)
3051 {
3052 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3053 struct hisi_hba *hisi_hba = cq->hisi_hba;
3054 struct hisi_sas_slot *slot;
3055 struct hisi_sas_itct *itct;
3056 struct hisi_sas_complete_v2_hdr *complete_queue;
3057 u32 rd_point = cq->rd_point, wr_point, dev_id;
3058 int queue = cq->id;
3059 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
3060
3061 if (unlikely(hisi_hba->reject_stp_links_msk))
3062 phys_try_accept_stp_links_v2_hw(hisi_hba);
3063
3064 complete_queue = hisi_hba->complete_hdr[queue];
3065
3066 spin_lock(&dq->lock);
3067 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3068 (0x14 * queue));
3069
3070 while (rd_point != wr_point) {
3071 struct hisi_sas_complete_v2_hdr *complete_hdr;
3072 int iptt;
3073
3074 complete_hdr = &complete_queue[rd_point];
3075
3076 /* Check for NCQ completion */
3077 if (complete_hdr->act) {
3078 u32 act_tmp = complete_hdr->act;
3079 int ncq_tag_count = ffs(act_tmp);
3080
3081 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3082 CMPLT_HDR_DEV_ID_OFF;
3083 itct = &hisi_hba->itct[dev_id];
3084
3085 /* The NCQ tags are held in the itct header */
3086 while (ncq_tag_count) {
3087 __le64 *ncq_tag = &itct->qw4_15[0];
3088
3089 ncq_tag_count -= 1;
3090 iptt = (ncq_tag[ncq_tag_count / 5]
3091 >> (ncq_tag_count % 5) * 12) & 0xfff;
3092
3093 slot = &hisi_hba->slot_info[iptt];
3094 slot->cmplt_queue_slot = rd_point;
3095 slot->cmplt_queue = queue;
3096 slot_complete_v2_hw(hisi_hba, slot);
3097
3098 act_tmp &= ~(1 << ncq_tag_count);
3099 ncq_tag_count = ffs(act_tmp);
3100 }
3101 } else {
3102 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3103 slot = &hisi_hba->slot_info[iptt];
3104 slot->cmplt_queue_slot = rd_point;
3105 slot->cmplt_queue = queue;
3106 slot_complete_v2_hw(hisi_hba, slot);
3107 }
3108
3109 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3110 rd_point = 0;
3111 }
3112
3113 /* update rd_point */
3114 cq->rd_point = rd_point;
3115 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3116 spin_unlock(&dq->lock);
3117 }
3118
3119 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3120 {
3121 struct hisi_sas_cq *cq = p;
3122 struct hisi_hba *hisi_hba = cq->hisi_hba;
3123 int queue = cq->id;
3124
3125 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3126
3127 tasklet_schedule(&cq->tasklet);
3128
3129 return IRQ_HANDLED;
3130 }
3131
3132 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3133 {
3134 struct hisi_sas_phy *phy = p;
3135 struct hisi_hba *hisi_hba = phy->hisi_hba;
3136 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3137 struct device *dev = hisi_hba->dev;
3138 struct hisi_sas_initial_fis *initial_fis;
3139 struct dev_to_host_fis *fis;
3140 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3141 irqreturn_t res = IRQ_HANDLED;
3142 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3143 int phy_no, offset;
3144
3145 phy_no = sas_phy->id;
3146 initial_fis = &hisi_hba->initial_fis[phy_no];
3147 fis = &initial_fis->fis;
3148
3149 offset = 4 * (phy_no / 4);
3150 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3151 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3152 ent_msk | 1 << ((phy_no % 4) * 8));
3153
3154 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3155 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3156 (phy_no % 4)));
3157 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3158 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3159 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3160 res = IRQ_NONE;
3161 goto end;
3162 }
3163
3164 /* check ERR bit of Status Register */
3165 if (fis->status & ATA_ERR) {
3166 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3167 fis->status);
3168 disable_phy_v2_hw(hisi_hba, phy_no);
3169 enable_phy_v2_hw(hisi_hba, phy_no);
3170 res = IRQ_NONE;
3171 goto end;
3172 }
3173
3174 if (unlikely(phy_no == 8)) {
3175 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3176
3177 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3178 PORT_STATE_PHY8_PORT_NUM_OFF;
3179 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3180 PORT_STATE_PHY8_CONN_RATE_OFF;
3181 } else {
3182 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3183 port_id = (port_id >> (4 * phy_no)) & 0xf;
3184 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3185 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3186 }
3187
3188 if (port_id == 0xf) {
3189 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3190 res = IRQ_NONE;
3191 goto end;
3192 }
3193
3194 sas_phy->linkrate = link_rate;
3195 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3196 HARD_PHY_LINKRATE);
3197 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3198 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3199
3200 sas_phy->oob_mode = SATA_OOB_MODE;
3201 /* Make up some unique SAS address */
3202 attached_sas_addr[0] = 0x50;
3203 attached_sas_addr[7] = phy_no;
3204 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3205 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3206 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3207 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3208 phy->port_id = port_id;
3209 phy->phy_type |= PORT_TYPE_SATA;
3210 phy->phy_attached = 1;
3211 phy->identify.device_type = SAS_SATA_DEV;
3212 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3213 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3214 queue_work(hisi_hba->wq, &phy->phyup_ws);
3215
3216 end:
3217 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3218 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3219
3220 return res;
3221 }
3222
3223 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3224 int_phy_updown_v2_hw,
3225 int_chnl_int_v2_hw,
3226 };
3227
3228 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3229 fatal_ecc_int_v2_hw,
3230 fatal_axi_int_v2_hw
3231 };
3232
3233 /**
3234 * There is a limitation in the hip06 chipset that we need
3235 * to map in all mbigen interrupts, even if they are not used.
3236 */
3237 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3238 {
3239 struct platform_device *pdev = hisi_hba->platform_dev;
3240 struct device *dev = &pdev->dev;
3241 int irq, rc, irq_map[128];
3242 int i, phy_no, fatal_no, queue_no, k;
3243
3244 for (i = 0; i < 128; i++)
3245 irq_map[i] = platform_get_irq(pdev, i);
3246
3247 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3248 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3249 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3250 DRV_NAME " phy", hisi_hba);
3251 if (rc) {
3252 dev_err(dev, "irq init: could not request "
3253 "phy interrupt %d, rc=%d\n",
3254 irq, rc);
3255 rc = -ENOENT;
3256 goto free_phy_int_irqs;
3257 }
3258 }
3259
3260 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3261 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3262
3263 irq = irq_map[phy_no + 72];
3264 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3265 DRV_NAME " sata", phy);
3266 if (rc) {
3267 dev_err(dev, "irq init: could not request "
3268 "sata interrupt %d, rc=%d\n",
3269 irq, rc);
3270 rc = -ENOENT;
3271 goto free_sata_int_irqs;
3272 }
3273 }
3274
3275 for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3276 irq = irq_map[fatal_no + 81];
3277 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3278 DRV_NAME " fatal", hisi_hba);
3279 if (rc) {
3280 dev_err(dev,
3281 "irq init: could not request fatal interrupt %d, rc=%d\n",
3282 irq, rc);
3283 rc = -ENOENT;
3284 goto free_fatal_int_irqs;
3285 }
3286 }
3287
3288 for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3289 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3290 struct tasklet_struct *t = &cq->tasklet;
3291
3292 irq = irq_map[queue_no + 96];
3293 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3294 DRV_NAME " cq", cq);
3295 if (rc) {
3296 dev_err(dev,
3297 "irq init: could not request cq interrupt %d, rc=%d\n",
3298 irq, rc);
3299 rc = -ENOENT;
3300 goto free_cq_int_irqs;
3301 }
3302 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3303 }
3304
3305 return 0;
3306
3307 free_cq_int_irqs:
3308 for (k = 0; k < queue_no; k++) {
3309 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3310
3311 free_irq(irq_map[k + 96], cq);
3312 tasklet_kill(&cq->tasklet);
3313 }
3314 free_fatal_int_irqs:
3315 for (k = 0; k < fatal_no; k++)
3316 free_irq(irq_map[k + 81], hisi_hba);
3317 free_sata_int_irqs:
3318 for (k = 0; k < phy_no; k++) {
3319 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3320
3321 free_irq(irq_map[k + 72], phy);
3322 }
3323 free_phy_int_irqs:
3324 for (k = 0; k < i; k++)
3325 free_irq(irq_map[k + 1], hisi_hba);
3326 return rc;
3327 }
3328
3329 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3330 {
3331 int rc;
3332
3333 memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3334
3335 rc = hw_init_v2_hw(hisi_hba);
3336 if (rc)
3337 return rc;
3338
3339 rc = interrupt_init_v2_hw(hisi_hba);
3340 if (rc)
3341 return rc;
3342
3343 return 0;
3344 }
3345
3346 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3347 {
3348 struct platform_device *pdev = hisi_hba->platform_dev;
3349 int i;
3350
3351 for (i = 0; i < hisi_hba->queue_count; i++)
3352 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3353
3354 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3355 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3356 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3357 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3358
3359 for (i = 0; i < hisi_hba->n_phy; i++) {
3360 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3361 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3362 }
3363
3364 for (i = 0; i < 128; i++)
3365 synchronize_irq(platform_get_irq(pdev, i));
3366 }
3367
3368
3369 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3370 {
3371 return hisi_sas_read32(hisi_hba, PHY_STATE);
3372 }
3373
3374 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3375 {
3376 struct device *dev = hisi_hba->dev;
3377 int rc, cnt;
3378
3379 interrupt_disable_v2_hw(hisi_hba);
3380 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3381 hisi_sas_kill_tasklets(hisi_hba);
3382
3383 hisi_sas_stop_phys(hisi_hba);
3384
3385 mdelay(10);
3386
3387 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3388
3389 /* wait until bus idle */
3390 cnt = 0;
3391 while (1) {
3392 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3393 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3394
3395 if (status == 0x3)
3396 break;
3397
3398 udelay(10);
3399 if (cnt++ > 10) {
3400 dev_info(dev, "wait axi bus state to idle timeout!\n");
3401 return -1;
3402 }
3403 }
3404
3405 hisi_sas_init_mem(hisi_hba);
3406
3407 rc = hw_init_v2_hw(hisi_hba);
3408 if (rc)
3409 return rc;
3410
3411 phys_reject_stp_links_v2_hw(hisi_hba);
3412
3413 return 0;
3414 }
3415
3416 static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
3417 u8 reg_index, u8 reg_count, u8 *write_data)
3418 {
3419 struct device *dev = hisi_hba->dev;
3420 int phy_no, count;
3421
3422 if (!hisi_hba->sgpio_regs)
3423 return -EOPNOTSUPP;
3424
3425 switch (reg_type) {
3426 case SAS_GPIO_REG_TX:
3427 count = reg_count * 4;
3428 count = min(count, hisi_hba->n_phy);
3429
3430 for (phy_no = 0; phy_no < count; phy_no++) {
3431 /*
3432 * GPIO_TX[n] register has the highest numbered drive
3433 * of the four in the first byte and the lowest
3434 * numbered drive in the fourth byte.
3435 * See SFF-8485 Rev. 0.7 Table 24.
3436 */
3437 void __iomem *reg_addr = hisi_hba->sgpio_regs +
3438 reg_index * 4 + phy_no;
3439 int data_idx = phy_no + 3 - (phy_no % 4) * 2;
3440
3441 writeb(write_data[data_idx], reg_addr);
3442 }
3443
3444 break;
3445 default:
3446 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3447 reg_type);
3448 return -EINVAL;
3449 }
3450
3451 return 0;
3452 }
3453
3454 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3455 .hw_init = hisi_sas_v2_init,
3456 .setup_itct = setup_itct_v2_hw,
3457 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3458 .alloc_dev = alloc_dev_quirk_v2_hw,
3459 .sl_notify = sl_notify_v2_hw,
3460 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3461 .clear_itct = clear_itct_v2_hw,
3462 .free_device = free_device_v2_hw,
3463 .prep_smp = prep_smp_v2_hw,
3464 .prep_ssp = prep_ssp_v2_hw,
3465 .prep_stp = prep_ata_v2_hw,
3466 .prep_abort = prep_abort_v2_hw,
3467 .get_free_slot = get_free_slot_v2_hw,
3468 .start_delivery = start_delivery_v2_hw,
3469 .slot_complete = slot_complete_v2_hw,
3470 .phys_init = phys_init_v2_hw,
3471 .phy_start = start_phy_v2_hw,
3472 .phy_disable = disable_phy_v2_hw,
3473 .phy_hard_reset = phy_hard_reset_v2_hw,
3474 .get_events = phy_get_events_v2_hw,
3475 .phy_set_linkrate = phy_set_linkrate_v2_hw,
3476 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3477 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3478 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3479 .soft_reset = soft_reset_v2_hw,
3480 .get_phys_state = get_phys_state_v2_hw,
3481 .write_gpio = write_gpio_v2_hw,
3482 };
3483
3484 static int hisi_sas_v2_probe(struct platform_device *pdev)
3485 {
3486 /*
3487 * Check if we should defer the probe before we probe the
3488 * upper layer, as it's hard to defer later on.
3489 */
3490 int ret = platform_get_irq(pdev, 0);
3491
3492 if (ret < 0) {
3493 if (ret != -EPROBE_DEFER)
3494 dev_err(&pdev->dev, "cannot obtain irq\n");
3495 return ret;
3496 }
3497
3498 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3499 }
3500
3501 static int hisi_sas_v2_remove(struct platform_device *pdev)
3502 {
3503 struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3504 struct hisi_hba *hisi_hba = sha->lldd_ha;
3505
3506 if (timer_pending(&hisi_hba->timer))
3507 del_timer(&hisi_hba->timer);
3508
3509 hisi_sas_kill_tasklets(hisi_hba);
3510
3511 return hisi_sas_remove(pdev);
3512 }
3513
3514 static const struct of_device_id sas_v2_of_match[] = {
3515 { .compatible = "hisilicon,hip06-sas-v2",},
3516 { .compatible = "hisilicon,hip07-sas-v2",},
3517 {},
3518 };
3519 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3520
3521 static const struct acpi_device_id sas_v2_acpi_match[] = {
3522 { "HISI0162", 0 },
3523 { }
3524 };
3525
3526 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3527
3528 static struct platform_driver hisi_sas_v2_driver = {
3529 .probe = hisi_sas_v2_probe,
3530 .remove = hisi_sas_v2_remove,
3531 .driver = {
3532 .name = DRV_NAME,
3533 .of_match_table = sas_v2_of_match,
3534 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3535 },
3536 };
3537
3538 module_platform_driver(hisi_sas_v2_driver);
3539
3540 MODULE_LICENSE("GPL");
3541 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3542 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3543 MODULE_ALIAS("platform:" DRV_NAME);
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