2 * Copyright (c) 2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
12 #define DRV_NAME "hisi_sas_v3_hw"
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CFG_1US_TIMER_TRSH 0xcc
55 #define CHNL_INT_STATUS 0x148
56 #define INT_COAL_EN 0x19c
57 #define OQ_INT_COAL_TIME 0x1a0
58 #define OQ_INT_COAL_CNT 0x1a4
59 #define ENT_INT_COAL_TIME 0x1a8
60 #define ENT_INT_COAL_CNT 0x1ac
61 #define OQ_INT_SRC 0x1b0
62 #define OQ_INT_SRC_MSK 0x1b4
63 #define ENT_INT_SRC1 0x1b8
64 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
65 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
66 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
67 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
68 #define ENT_INT_SRC2 0x1bc
69 #define ENT_INT_SRC3 0x1c0
70 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
71 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
72 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
73 #define ENT_INT_SRC3_AXI_OFF 11
74 #define ENT_INT_SRC3_FIFO_OFF 12
75 #define ENT_INT_SRC3_LM_OFF 14
76 #define ENT_INT_SRC3_ITC_INT_OFF 15
77 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
78 #define ENT_INT_SRC3_ABT_OFF 16
79 #define ENT_INT_SRC_MSK1 0x1c4
80 #define ENT_INT_SRC_MSK2 0x1c8
81 #define ENT_INT_SRC_MSK3 0x1cc
82 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
83 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
84 #define CHNL_ENT_INT_MSK 0x1d4
85 #define HGC_COM_INT_MSK 0x1d8
86 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
87 #define SAS_ECC_INTR 0x1e8
88 #define SAS_ECC_INTR_MSK 0x1ec
89 #define HGC_ERR_STAT_EN 0x238
90 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
91 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
92 #define DLVRY_Q_0_DEPTH 0x268
93 #define DLVRY_Q_0_WR_PTR 0x26c
94 #define DLVRY_Q_0_RD_PTR 0x270
95 #define HYPER_STREAM_ID_EN_CFG 0xc80
96 #define OQ0_INT_SRC_MSK 0xc90
97 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
98 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
99 #define COMPL_Q_0_DEPTH 0x4e8
100 #define COMPL_Q_0_WR_PTR 0x4ec
101 #define COMPL_Q_0_RD_PTR 0x4f0
102 #define AWQOS_AWCACHE_CFG 0xc84
103 #define ARQOS_ARCACHE_CFG 0xc88
105 /* phy registers requiring init */
106 #define PORT_BASE (0x2000)
107 #define PHY_CFG (PORT_BASE + 0x0)
108 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
109 #define PHY_CFG_ENA_OFF 0
110 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
111 #define PHY_CFG_DC_OPT_OFF 2
112 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
113 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
114 #define PHY_CTRL (PORT_BASE + 0x14)
115 #define PHY_CTRL_RESET_OFF 0
116 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
117 #define SL_CFG (PORT_BASE + 0x84)
118 #define SL_CONTROL (PORT_BASE + 0x94)
119 #define SL_CONTROL_NOTIFY_EN_OFF 0
120 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
121 #define SL_CTA_OFF 17
122 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
123 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
124 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
125 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
126 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
127 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
128 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
129 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
130 #define TXID_AUTO (PORT_BASE + 0xb8)
132 #define CT3_MSK (0x1 << CT3_OFF)
133 #define TX_HARDRST_OFF 2
134 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
135 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
136 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
137 #define STP_LINK_TIMER (PORT_BASE + 0x120)
138 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
139 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
140 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
141 #define CHL_INT0 (PORT_BASE + 0x1b4)
142 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
143 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
144 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
145 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
146 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
147 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
148 #define CHL_INT0_NOT_RDY_OFF 4
149 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
150 #define CHL_INT0_PHY_RDY_OFF 5
151 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
152 #define CHL_INT1 (PORT_BASE + 0x1b8)
153 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
154 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
155 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
156 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
157 #define CHL_INT2 (PORT_BASE + 0x1bc)
158 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
159 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
160 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
161 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
162 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
163 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
164 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
165 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
166 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
167 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
168 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
169 #define DMA_TX_STATUS_BUSY_OFF 0
170 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
171 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
172 #define DMA_RX_STATUS_BUSY_OFF 0
173 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
175 #define MAX_ITCT_HW 4096 /* max the hw can support */
176 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
177 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
178 #error Max ITCT exceeded
181 #define AXI_MASTER_CFG_BASE (0x5000)
182 #define AM_CTRL_GLOBAL (0x0)
183 #define AM_CURR_TRANS_RETURN (0x150)
185 #define AM_CFG_MAX_TRANS (0x5010)
186 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
187 #define AXI_CFG (0x5100)
188 #define AM_ROB_ECC_ERR_ADDR (0x510c)
189 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
190 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
191 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
192 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
194 /* HW dma structures */
195 /* Delivery queue header */
197 #define CMD_HDR_ABORT_FLAG_OFF 0
198 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
199 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
200 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
201 #define CMD_HDR_RESP_REPORT_OFF 5
202 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
203 #define CMD_HDR_TLR_CTRL_OFF 6
204 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
205 #define CMD_HDR_PORT_OFF 18
206 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
207 #define CMD_HDR_PRIORITY_OFF 27
208 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
209 #define CMD_HDR_CMD_OFF 29
210 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
212 #define CMD_HDR_UNCON_CMD_OFF 3
213 #define CMD_HDR_DIR_OFF 5
214 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
215 #define CMD_HDR_RESET_OFF 7
216 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
217 #define CMD_HDR_VDTL_OFF 10
218 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
219 #define CMD_HDR_FRAME_TYPE_OFF 11
220 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
221 #define CMD_HDR_DEV_ID_OFF 16
222 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
224 #define CMD_HDR_CFL_OFF 0
225 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
226 #define CMD_HDR_NCQ_TAG_OFF 10
227 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
228 #define CMD_HDR_MRFL_OFF 15
229 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
230 #define CMD_HDR_SG_MOD_OFF 24
231 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
233 #define CMD_HDR_IPTT_OFF 0
234 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
236 #define CMD_HDR_DIF_SGL_LEN_OFF 0
237 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
238 #define CMD_HDR_DATA_SGL_LEN_OFF 16
239 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
241 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
242 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
243 #define CMD_HDR_ABORT_IPTT_OFF 16
244 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
246 /* Completion header */
248 #define CMPLT_HDR_CMPLT_OFF 0
249 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
250 #define CMPLT_HDR_ERROR_PHASE_OFF 2
251 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
252 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
253 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
254 #define CMPLT_HDR_ERX_OFF 12
255 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
256 #define CMPLT_HDR_ABORT_STAT_OFF 13
257 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
259 #define STAT_IO_NOT_VALID 0x1
260 #define STAT_IO_NO_DEVICE 0x2
261 #define STAT_IO_COMPLETE 0x3
262 #define STAT_IO_ABORTED 0x4
264 #define CMPLT_HDR_IPTT_OFF 0
265 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
266 #define CMPLT_HDR_DEV_ID_OFF 16
267 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
269 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
270 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
274 #define ITCT_HDR_DEV_TYPE_OFF 0
275 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
276 #define ITCT_HDR_VALID_OFF 2
277 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
278 #define ITCT_HDR_MCR_OFF 5
279 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
280 #define ITCT_HDR_VLN_OFF 9
281 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
282 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
283 #define ITCT_HDR_AWT_CONTINUE_OFF 25
284 #define ITCT_HDR_PORT_ID_OFF 28
285 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
287 #define ITCT_HDR_INLT_OFF 0
288 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
289 #define ITCT_HDR_RTOLT_OFF 48
290 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
292 struct hisi_sas_complete_v3_hdr
{
299 struct hisi_sas_err_record_v3
{
301 __le32 trans_tx_fail_type
;
304 __le32 trans_rx_fail_type
;
307 __le16 dma_tx_err_type
;
308 __le16 sipc_rx_err_type
;
311 __le32 dma_rx_err_type
;
314 #define RX_DATA_LEN_UNDERFLOW_OFF 6
315 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
317 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
318 #define HISI_SAS_MSI_COUNT_V3_HW 32
321 HISI_SAS_PHY_PHY_UPDOWN
,
322 HISI_SAS_PHY_CHNL_INT
,
326 #define DIR_NO_DATA 0
328 #define DIR_TO_DEVICE 2
329 #define DIR_RESERVED 3
331 #define CMD_IS_UNCONSTRAINT(cmd) \
332 ((cmd == ATA_CMD_READ_LOG_EXT) || \
333 (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
334 (cmd == ATA_CMD_DEV_RESET))
336 static u32
hisi_sas_read32(struct hisi_hba
*hisi_hba
, u32 off
)
338 void __iomem
*regs
= hisi_hba
->regs
+ off
;
343 static u32
hisi_sas_read32_relaxed(struct hisi_hba
*hisi_hba
, u32 off
)
345 void __iomem
*regs
= hisi_hba
->regs
+ off
;
347 return readl_relaxed(regs
);
350 static void hisi_sas_write32(struct hisi_hba
*hisi_hba
, u32 off
, u32 val
)
352 void __iomem
*regs
= hisi_hba
->regs
+ off
;
357 static void hisi_sas_phy_write32(struct hisi_hba
*hisi_hba
, int phy_no
,
360 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
365 static u32
hisi_sas_phy_read32(struct hisi_hba
*hisi_hba
,
368 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
373 static void init_reg_v3_hw(struct hisi_hba
*hisi_hba
)
377 /* Global registers init */
378 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
,
379 (u32
)((1ULL << hisi_hba
->queue_count
) - 1));
380 hisi_sas_write32(hisi_hba
, HGC_SAS_TXFAIL_RETRY_CTRL
, 0x108);
381 hisi_sas_write32(hisi_hba
, CFG_1US_TIMER_TRSH
, 0xd);
382 hisi_sas_write32(hisi_hba
, INT_COAL_EN
, 0x1);
383 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_TIME
, 0x1);
384 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_CNT
, 0x1);
385 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 0xffff);
386 hisi_sas_write32(hisi_hba
, ENT_INT_SRC1
, 0xffffffff);
387 hisi_sas_write32(hisi_hba
, ENT_INT_SRC2
, 0xffffffff);
388 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
, 0xffffffff);
389 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0xfefefefe);
390 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0xfefefefe);
391 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0xffffffff);
392 hisi_sas_write32(hisi_hba
, CHNL_PHYUPDOWN_INT_MSK
, 0x0);
393 hisi_sas_write32(hisi_hba
, CHNL_ENT_INT_MSK
, 0x0);
394 hisi_sas_write32(hisi_hba
, HGC_COM_INT_MSK
, 0x0);
395 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0x0);
396 hisi_sas_write32(hisi_hba
, AWQOS_AWCACHE_CFG
, 0xf0f0);
397 hisi_sas_write32(hisi_hba
, ARQOS_ARCACHE_CFG
, 0xf0f0);
398 for (i
= 0; i
< hisi_hba
->queue_count
; i
++)
399 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+0x4*i
, 0);
401 hisi_sas_write32(hisi_hba
, HYPER_STREAM_ID_EN_CFG
, 1);
402 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
, 0x30000);
404 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
405 hisi_sas_phy_write32(hisi_hba
, i
, PROG_PHY_LINK_RATE
, 0x801);
406 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT0
, 0xffffffff);
407 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1
, 0xffffffff);
408 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2
, 0xffffffff);
409 hisi_sas_phy_write32(hisi_hba
, i
, RXOP_CHECK_CFG_H
, 0x1000);
410 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xffffffff);
411 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0x8ffffbff);
412 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL_RDY_MSK
, 0x0);
413 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_NOT_RDY_MSK
, 0x0);
414 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_DWS_RESET_MSK
, 0x0);
415 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_PHY_ENA_MSK
, 0x0);
416 hisi_sas_phy_write32(hisi_hba
, i
, SL_RX_BCAST_CHK_MSK
, 0x0);
417 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_OOB_RESTART_MSK
, 0x0);
418 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL
, 0x199b4fa);
419 hisi_sas_phy_write32(hisi_hba
, i
, SAS_SSP_CON_TIMER_CFG
,
421 hisi_sas_phy_write32(hisi_hba
, i
, SAS_STP_CON_TIMER_CFG
,
423 hisi_sas_phy_write32(hisi_hba
, i
, STP_LINK_TIMER
,
426 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
428 hisi_sas_write32(hisi_hba
,
429 DLVRY_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
430 upper_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
432 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
433 lower_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
435 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_DEPTH
+ (i
* 0x14),
436 HISI_SAS_QUEUE_SLOTS
);
438 /* Completion queue */
439 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
440 upper_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
442 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
443 lower_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
445 hisi_sas_write32(hisi_hba
, COMPL_Q_0_DEPTH
+ (i
* 0x14),
446 HISI_SAS_QUEUE_SLOTS
);
450 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_LO
,
451 lower_32_bits(hisi_hba
->itct_dma
));
453 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_HI
,
454 upper_32_bits(hisi_hba
->itct_dma
));
457 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_LO
,
458 lower_32_bits(hisi_hba
->iost_dma
));
460 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_HI
,
461 upper_32_bits(hisi_hba
->iost_dma
));
464 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_LO
,
465 lower_32_bits(hisi_hba
->breakpoint_dma
));
467 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_HI
,
468 upper_32_bits(hisi_hba
->breakpoint_dma
));
470 /* SATA broken msg */
471 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_LO
,
472 lower_32_bits(hisi_hba
->sata_breakpoint_dma
));
474 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_HI
,
475 upper_32_bits(hisi_hba
->sata_breakpoint_dma
));
477 /* SATA initial fis */
478 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_LO
,
479 lower_32_bits(hisi_hba
->initial_fis_dma
));
481 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_HI
,
482 upper_32_bits(hisi_hba
->initial_fis_dma
));
485 static void config_phy_opt_mode_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
487 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
489 cfg
&= ~PHY_CFG_DC_OPT_MSK
;
490 cfg
|= 1 << PHY_CFG_DC_OPT_OFF
;
491 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
494 static void config_id_frame_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
496 struct sas_identify_frame identify_frame
;
497 u32
*identify_buffer
;
499 memset(&identify_frame
, 0, sizeof(identify_frame
));
500 identify_frame
.dev_type
= SAS_END_DEVICE
;
501 identify_frame
.frame_type
= 0;
502 identify_frame
._un1
= 1;
503 identify_frame
.initiator_bits
= SAS_PROTOCOL_ALL
;
504 identify_frame
.target_bits
= SAS_PROTOCOL_NONE
;
505 memcpy(&identify_frame
._un4_11
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
506 memcpy(&identify_frame
.sas_addr
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
507 identify_frame
.phy_id
= phy_no
;
508 identify_buffer
= (u32
*)(&identify_frame
);
510 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD0
,
511 __swab32(identify_buffer
[0]));
512 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD1
,
513 __swab32(identify_buffer
[1]));
514 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD2
,
515 __swab32(identify_buffer
[2]));
516 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD3
,
517 __swab32(identify_buffer
[3]));
518 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD4
,
519 __swab32(identify_buffer
[4]));
520 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD5
,
521 __swab32(identify_buffer
[5]));
524 static void setup_itct_v3_hw(struct hisi_hba
*hisi_hba
,
525 struct hisi_sas_device
*sas_dev
)
527 struct domain_device
*device
= sas_dev
->sas_device
;
528 struct device
*dev
= hisi_hba
->dev
;
529 u64 qw0
, device_id
= sas_dev
->device_id
;
530 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[device_id
];
531 struct domain_device
*parent_dev
= device
->parent
;
532 struct asd_sas_port
*sas_port
= device
->port
;
533 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
535 memset(itct
, 0, sizeof(*itct
));
539 switch (sas_dev
->dev_type
) {
541 case SAS_EDGE_EXPANDER_DEVICE
:
542 case SAS_FANOUT_EXPANDER_DEVICE
:
543 qw0
= HISI_SAS_DEV_TYPE_SSP
<< ITCT_HDR_DEV_TYPE_OFF
;
546 case SAS_SATA_PENDING
:
547 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
548 qw0
= HISI_SAS_DEV_TYPE_STP
<< ITCT_HDR_DEV_TYPE_OFF
;
550 qw0
= HISI_SAS_DEV_TYPE_SATA
<< ITCT_HDR_DEV_TYPE_OFF
;
553 dev_warn(dev
, "setup itct: unsupported dev type (%d)\n",
557 qw0
|= ((1 << ITCT_HDR_VALID_OFF
) |
558 (device
->linkrate
<< ITCT_HDR_MCR_OFF
) |
559 (1 << ITCT_HDR_VLN_OFF
) |
560 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF
) |
561 (1 << ITCT_HDR_AWT_CONTINUE_OFF
) |
562 (port
->id
<< ITCT_HDR_PORT_ID_OFF
));
563 itct
->qw0
= cpu_to_le64(qw0
);
566 memcpy(&itct
->sas_addr
, device
->sas_addr
, SAS_ADDR_SIZE
);
567 itct
->sas_addr
= __swab64(itct
->sas_addr
);
570 if (!dev_is_sata(device
))
571 itct
->qw2
= cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF
) |
572 (0x1ULL
<< ITCT_HDR_RTOLT_OFF
));
575 static void free_device_v3_hw(struct hisi_hba
*hisi_hba
,
576 struct hisi_sas_device
*sas_dev
)
578 u64 dev_id
= sas_dev
->device_id
;
579 struct device
*dev
= hisi_hba
->dev
;
580 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[dev_id
];
581 u32 reg_val
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
583 /* clear the itct interrupt state */
584 if (ENT_INT_SRC3_ITC_INT_MSK
& reg_val
)
585 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
586 ENT_INT_SRC3_ITC_INT_MSK
);
588 /* clear the itct table*/
589 reg_val
= hisi_sas_read32(hisi_hba
, ITCT_CLR
);
590 reg_val
|= ITCT_CLR_EN_MSK
| (dev_id
& ITCT_DEV_MSK
);
591 hisi_sas_write32(hisi_hba
, ITCT_CLR
, reg_val
);
594 reg_val
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
595 if (ENT_INT_SRC3_ITC_INT_MSK
& reg_val
) {
596 dev_dbg(dev
, "got clear ITCT done interrupt\n");
598 /* invalid the itct state*/
599 memset(itct
, 0, sizeof(struct hisi_sas_itct
));
600 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
601 ENT_INT_SRC3_ITC_INT_MSK
);
604 hisi_sas_write32(hisi_hba
, ITCT_CLR
, 0);
605 dev_dbg(dev
, "clear ITCT ok\n");
609 static void dereg_device_v3_hw(struct hisi_hba
*hisi_hba
,
610 struct domain_device
*device
)
612 struct hisi_sas_slot
*slot
, *slot2
;
613 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
614 u32 cfg_abt_set_query_iptt
;
616 cfg_abt_set_query_iptt
= hisi_sas_read32(hisi_hba
,
617 CFG_ABT_SET_QUERY_IPTT
);
618 list_for_each_entry_safe(slot
, slot2
, &sas_dev
->list
, entry
) {
619 cfg_abt_set_query_iptt
&= ~CFG_SET_ABORTED_IPTT_MSK
;
620 cfg_abt_set_query_iptt
|= (1 << CFG_SET_ABORTED_EN_OFF
) |
621 (slot
->idx
<< CFG_SET_ABORTED_IPTT_OFF
);
622 hisi_sas_write32(hisi_hba
, CFG_ABT_SET_QUERY_IPTT
,
623 cfg_abt_set_query_iptt
);
625 cfg_abt_set_query_iptt
&= ~(1 << CFG_SET_ABORTED_EN_OFF
);
626 hisi_sas_write32(hisi_hba
, CFG_ABT_SET_QUERY_IPTT
,
627 cfg_abt_set_query_iptt
);
628 hisi_sas_write32(hisi_hba
, CFG_ABT_SET_IPTT_DONE
,
629 1 << CFG_ABT_SET_IPTT_DONE_OFF
);
632 static int reset_hw_v3_hw(struct hisi_hba
*hisi_hba
)
634 struct device
*dev
= hisi_hba
->dev
;
638 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0);
640 /* Disable all of the PHYs */
641 hisi_sas_stop_phys(hisi_hba
);
644 /* Ensure axi bus idle */
645 ret
= readl_poll_timeout(hisi_hba
->regs
+ AXI_CFG
, val
, !val
,
648 dev_err(dev
, "axi bus is not idle, ret = %d!\n", ret
);
652 if (ACPI_HANDLE(dev
)) {
655 s
= acpi_evaluate_object(ACPI_HANDLE(dev
), "_RST", NULL
, NULL
);
656 if (ACPI_FAILURE(s
)) {
657 dev_err(dev
, "Reset failed\n");
661 dev_err(dev
, "no reset method!\n");
666 static int hw_init_v3_hw(struct hisi_hba
*hisi_hba
)
668 struct device
*dev
= hisi_hba
->dev
;
671 rc
= reset_hw_v3_hw(hisi_hba
);
673 dev_err(dev
, "hisi_sas_reset_hw failed, rc=%d", rc
);
678 init_reg_v3_hw(hisi_hba
);
683 static void enable_phy_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
685 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
687 cfg
|= PHY_CFG_ENA_MSK
;
688 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
691 static void disable_phy_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
693 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
695 cfg
&= ~PHY_CFG_ENA_MSK
;
696 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
699 static void start_phy_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
701 config_id_frame_v3_hw(hisi_hba
, phy_no
);
702 config_phy_opt_mode_v3_hw(hisi_hba
, phy_no
);
703 enable_phy_v3_hw(hisi_hba
, phy_no
);
706 static void phy_hard_reset_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
708 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
711 disable_phy_v3_hw(hisi_hba
, phy_no
);
712 if (phy
->identify
.device_type
== SAS_END_DEVICE
) {
713 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
714 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
715 txid_auto
| TX_HARDRST_MSK
);
718 start_phy_v3_hw(hisi_hba
, phy_no
);
721 enum sas_linkrate
phy_get_max_linkrate_v3_hw(void)
723 return SAS_LINK_RATE_12_0_GBPS
;
726 static void phys_init_v3_hw(struct hisi_hba
*hisi_hba
)
730 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
731 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[i
];
732 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
734 if (!sas_phy
->phy
->enabled
)
737 start_phy_v3_hw(hisi_hba
, i
);
741 static void sl_notify_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
745 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
746 sl_control
|= SL_CONTROL_NOTIFY_EN_MSK
;
747 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
749 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
750 sl_control
&= ~SL_CONTROL_NOTIFY_EN_MSK
;
751 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
754 static int get_wideport_bitmap_v3_hw(struct hisi_hba
*hisi_hba
, int port_id
)
757 u32 phy_port_num_ma
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
759 for (i
= 0; i
< hisi_hba
->n_phy
; i
++)
760 if (((phy_port_num_ma
>> (i
* 4)) & 0xf) == port_id
)
767 * The callpath to this function and upto writing the write
768 * queue pointer should be safe from interruption.
771 get_free_slot_v3_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_dq
*dq
)
773 struct device
*dev
= hisi_hba
->dev
;
778 r
= hisi_sas_read32_relaxed(hisi_hba
,
779 DLVRY_Q_0_RD_PTR
+ (queue
* 0x14));
780 if (r
== (w
+1) % HISI_SAS_QUEUE_SLOTS
) {
781 dev_warn(dev
, "full queue=%d r=%d w=%d\n\n",
789 static void start_delivery_v3_hw(struct hisi_sas_dq
*dq
)
791 struct hisi_hba
*hisi_hba
= dq
->hisi_hba
;
792 int dlvry_queue
= dq
->slot_prep
->dlvry_queue
;
793 int dlvry_queue_slot
= dq
->slot_prep
->dlvry_queue_slot
;
795 dq
->wr_point
= ++dlvry_queue_slot
% HISI_SAS_QUEUE_SLOTS
;
796 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_WR_PTR
+ (dlvry_queue
* 0x14),
800 static int prep_prd_sge_v3_hw(struct hisi_hba
*hisi_hba
,
801 struct hisi_sas_slot
*slot
,
802 struct hisi_sas_cmd_hdr
*hdr
,
803 struct scatterlist
*scatter
,
806 struct hisi_sas_sge_page
*sge_page
= hisi_sas_sge_addr_mem(slot
);
807 struct device
*dev
= hisi_hba
->dev
;
808 struct scatterlist
*sg
;
811 if (n_elem
> HISI_SAS_SGE_PAGE_CNT
) {
812 dev_err(dev
, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
817 for_each_sg(scatter
, sg
, n_elem
, i
) {
818 struct hisi_sas_sge
*entry
= &sge_page
->sge
[i
];
820 entry
->addr
= cpu_to_le64(sg_dma_address(sg
));
821 entry
->page_ctrl_0
= entry
->page_ctrl_1
= 0;
822 entry
->data_len
= cpu_to_le32(sg_dma_len(sg
));
826 hdr
->prd_table_addr
= cpu_to_le64(hisi_sas_sge_addr_dma(slot
));
828 hdr
->sg_len
= cpu_to_le32(n_elem
<< CMD_HDR_DATA_SGL_LEN_OFF
);
833 static int prep_ssp_v3_hw(struct hisi_hba
*hisi_hba
,
834 struct hisi_sas_slot
*slot
, int is_tmf
,
835 struct hisi_sas_tmf_task
*tmf
)
837 struct sas_task
*task
= slot
->task
;
838 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
839 struct domain_device
*device
= task
->dev
;
840 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
841 struct hisi_sas_port
*port
= slot
->port
;
842 struct sas_ssp_task
*ssp_task
= &task
->ssp_task
;
843 struct scsi_cmnd
*scsi_cmnd
= ssp_task
->cmd
;
844 int has_data
= 0, rc
, priority
= is_tmf
;
846 u32 dw1
= 0, dw2
= 0;
848 hdr
->dw0
= cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF
) |
849 (2 << CMD_HDR_TLR_CTRL_OFF
) |
850 (port
->id
<< CMD_HDR_PORT_OFF
) |
851 (priority
<< CMD_HDR_PRIORITY_OFF
) |
852 (1 << CMD_HDR_CMD_OFF
)); /* ssp */
854 dw1
= 1 << CMD_HDR_VDTL_OFF
;
856 dw1
|= 2 << CMD_HDR_FRAME_TYPE_OFF
;
857 dw1
|= DIR_NO_DATA
<< CMD_HDR_DIR_OFF
;
859 dw1
|= 1 << CMD_HDR_FRAME_TYPE_OFF
;
860 switch (scsi_cmnd
->sc_data_direction
) {
863 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
865 case DMA_FROM_DEVICE
:
867 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
870 dw1
&= ~CMD_HDR_DIR_MSK
;
875 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
876 hdr
->dw1
= cpu_to_le32(dw1
);
878 dw2
= (((sizeof(struct ssp_command_iu
) + sizeof(struct ssp_frame_hdr
)
879 + 3) / 4) << CMD_HDR_CFL_OFF
) |
880 ((HISI_SAS_MAX_SSP_RESP_SZ
/ 4) << CMD_HDR_MRFL_OFF
) |
881 (2 << CMD_HDR_SG_MOD_OFF
);
882 hdr
->dw2
= cpu_to_le32(dw2
);
883 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
886 rc
= prep_prd_sge_v3_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
892 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
893 hdr
->cmd_table_addr
= cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot
));
894 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
896 buf_cmd
= hisi_sas_cmd_hdr_addr_mem(slot
) +
897 sizeof(struct ssp_frame_hdr
);
899 memcpy(buf_cmd
, &task
->ssp_task
.LUN
, 8);
901 buf_cmd
[9] = ssp_task
->task_attr
| (ssp_task
->task_prio
<< 3);
902 memcpy(buf_cmd
+ 12, scsi_cmnd
->cmnd
, scsi_cmnd
->cmd_len
);
904 buf_cmd
[10] = tmf
->tmf
;
909 (tmf
->tag_of_task_to_be_managed
>> 8) & 0xff;
911 tmf
->tag_of_task_to_be_managed
& 0xff;
921 static int prep_smp_v3_hw(struct hisi_hba
*hisi_hba
,
922 struct hisi_sas_slot
*slot
)
924 struct sas_task
*task
= slot
->task
;
925 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
926 struct domain_device
*device
= task
->dev
;
927 struct device
*dev
= hisi_hba
->dev
;
928 struct hisi_sas_port
*port
= slot
->port
;
929 struct scatterlist
*sg_req
, *sg_resp
;
930 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
931 dma_addr_t req_dma_addr
;
932 unsigned int req_len
, resp_len
;
936 * DMA-map SMP request, response buffers
939 sg_req
= &task
->smp_task
.smp_req
;
940 elem
= dma_map_sg(dev
, sg_req
, 1, DMA_TO_DEVICE
);
943 req_len
= sg_dma_len(sg_req
);
944 req_dma_addr
= sg_dma_address(sg_req
);
947 sg_resp
= &task
->smp_task
.smp_resp
;
948 elem
= dma_map_sg(dev
, sg_resp
, 1, DMA_FROM_DEVICE
);
953 resp_len
= sg_dma_len(sg_resp
);
954 if ((req_len
& 0x3) || (resp_len
& 0x3)) {
961 hdr
->dw0
= cpu_to_le32((port
->id
<< CMD_HDR_PORT_OFF
) |
962 (1 << CMD_HDR_PRIORITY_OFF
) | /* high pri */
963 (2 << CMD_HDR_CMD_OFF
)); /* smp */
966 hdr
->dw1
= cpu_to_le32((sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
) |
967 (1 << CMD_HDR_FRAME_TYPE_OFF
) |
968 (DIR_NO_DATA
<< CMD_HDR_DIR_OFF
));
971 hdr
->dw2
= cpu_to_le32((((req_len
- 4) / 4) << CMD_HDR_CFL_OFF
) |
972 (HISI_SAS_MAX_SMP_RESP_SZ
/ 4 <<
975 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
<< CMD_HDR_IPTT_OFF
);
977 hdr
->cmd_table_addr
= cpu_to_le64(req_dma_addr
);
978 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
983 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_resp
, 1,
986 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_req
, 1,
991 static int get_ncq_tag_v3_hw(struct sas_task
*task
, u32
*tag
)
993 struct ata_queued_cmd
*qc
= task
->uldd_task
;
996 if (qc
->tf
.command
== ATA_CMD_FPDMA_WRITE
||
997 qc
->tf
.command
== ATA_CMD_FPDMA_READ
) {
1005 static int prep_ata_v3_hw(struct hisi_hba
*hisi_hba
,
1006 struct hisi_sas_slot
*slot
)
1008 struct sas_task
*task
= slot
->task
;
1009 struct domain_device
*device
= task
->dev
;
1010 struct domain_device
*parent_dev
= device
->parent
;
1011 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
1012 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1013 struct asd_sas_port
*sas_port
= device
->port
;
1014 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
1016 int has_data
= 0, rc
= 0, hdr_tag
= 0;
1017 u32 dw1
= 0, dw2
= 0;
1019 hdr
->dw0
= cpu_to_le32(port
->id
<< CMD_HDR_PORT_OFF
);
1020 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
1021 hdr
->dw0
|= cpu_to_le32(3 << CMD_HDR_CMD_OFF
);
1023 hdr
->dw0
|= cpu_to_le32(4 << CMD_HDR_CMD_OFF
);
1025 switch (task
->data_dir
) {
1028 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
1030 case DMA_FROM_DEVICE
:
1032 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
1035 dw1
&= ~CMD_HDR_DIR_MSK
;
1038 if ((task
->ata_task
.fis
.command
== ATA_CMD_DEV_RESET
) &&
1039 (task
->ata_task
.fis
.control
& ATA_SRST
))
1040 dw1
|= 1 << CMD_HDR_RESET_OFF
;
1042 dw1
|= (hisi_sas_get_ata_protocol(
1043 task
->ata_task
.fis
.command
, task
->data_dir
))
1044 << CMD_HDR_FRAME_TYPE_OFF
;
1045 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
1047 if (CMD_IS_UNCONSTRAINT(task
->ata_task
.fis
.command
))
1048 dw1
|= 1 << CMD_HDR_UNCON_CMD_OFF
;
1050 hdr
->dw1
= cpu_to_le32(dw1
);
1053 if (task
->ata_task
.use_ncq
&& get_ncq_tag_v3_hw(task
, &hdr_tag
)) {
1054 task
->ata_task
.fis
.sector_count
|= (u8
) (hdr_tag
<< 3);
1055 dw2
|= hdr_tag
<< CMD_HDR_NCQ_TAG_OFF
;
1058 dw2
|= (HISI_SAS_MAX_STP_RESP_SZ
/ 4) << CMD_HDR_CFL_OFF
|
1059 2 << CMD_HDR_SG_MOD_OFF
;
1060 hdr
->dw2
= cpu_to_le32(dw2
);
1063 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
1066 rc
= prep_prd_sge_v3_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
1072 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
1073 hdr
->cmd_table_addr
= cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot
));
1074 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
1076 buf_cmd
= hisi_sas_cmd_hdr_addr_mem(slot
);
1078 if (likely(!task
->ata_task
.device_control_reg_update
))
1079 task
->ata_task
.fis
.flags
|= 0x80; /* C=1: update ATA cmd reg */
1080 /* fill in command FIS */
1081 memcpy(buf_cmd
, &task
->ata_task
.fis
, sizeof(struct host_to_dev_fis
));
1086 static int prep_abort_v3_hw(struct hisi_hba
*hisi_hba
,
1087 struct hisi_sas_slot
*slot
,
1088 int device_id
, int abort_flag
, int tag_to_abort
)
1090 struct sas_task
*task
= slot
->task
;
1091 struct domain_device
*dev
= task
->dev
;
1092 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1093 struct hisi_sas_port
*port
= slot
->port
;
1096 hdr
->dw0
= cpu_to_le32((5 << CMD_HDR_CMD_OFF
) | /*abort*/
1097 (port
->id
<< CMD_HDR_PORT_OFF
) |
1098 ((dev_is_sata(dev
) ? 1:0)
1099 << CMD_HDR_ABORT_DEVICE_TYPE_OFF
) |
1101 << CMD_HDR_ABORT_FLAG_OFF
));
1104 hdr
->dw1
= cpu_to_le32(device_id
1105 << CMD_HDR_DEV_ID_OFF
);
1108 hdr
->dw7
= cpu_to_le32(tag_to_abort
<< CMD_HDR_ABORT_IPTT_OFF
);
1109 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
1114 static int phy_up_v3_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
1117 u32 context
, port_id
, link_rate
, hard_phy_linkrate
;
1118 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1119 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1120 struct device
*dev
= hisi_hba
->dev
;
1122 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 1);
1124 port_id
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
1125 port_id
= (port_id
>> (4 * phy_no
)) & 0xf;
1126 link_rate
= hisi_sas_read32(hisi_hba
, PHY_CONN_RATE
);
1127 link_rate
= (link_rate
>> (phy_no
* 4)) & 0xf;
1129 if (port_id
== 0xf) {
1130 dev_err(dev
, "phyup: phy%d invalid portid\n", phy_no
);
1134 sas_phy
->linkrate
= link_rate
;
1135 hard_phy_linkrate
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1137 phy
->maximum_linkrate
= hard_phy_linkrate
& 0xf;
1138 phy
->minimum_linkrate
= (hard_phy_linkrate
>> 4) & 0xf;
1139 phy
->phy_type
&= ~(PORT_TYPE_SAS
| PORT_TYPE_SATA
);
1141 /* Check for SATA dev */
1142 context
= hisi_sas_read32(hisi_hba
, PHY_CONTEXT
);
1143 if (context
& (1 << phy_no
)) {
1144 struct hisi_sas_initial_fis
*initial_fis
;
1145 struct dev_to_host_fis
*fis
;
1146 u8 attached_sas_addr
[SAS_ADDR_SIZE
] = {0};
1148 dev_info(dev
, "phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
1149 initial_fis
= &hisi_hba
->initial_fis
[phy_no
];
1150 fis
= &initial_fis
->fis
;
1151 sas_phy
->oob_mode
= SATA_OOB_MODE
;
1152 attached_sas_addr
[0] = 0x50;
1153 attached_sas_addr
[7] = phy_no
;
1154 memcpy(sas_phy
->attached_sas_addr
,
1157 memcpy(sas_phy
->frame_rcvd
, fis
,
1158 sizeof(struct dev_to_host_fis
));
1159 phy
->phy_type
|= PORT_TYPE_SATA
;
1160 phy
->identify
.device_type
= SAS_SATA_DEV
;
1161 phy
->frame_rcvd_size
= sizeof(struct dev_to_host_fis
);
1162 phy
->identify
.target_port_protocols
= SAS_PROTOCOL_SATA
;
1164 u32
*frame_rcvd
= (u32
*)sas_phy
->frame_rcvd
;
1165 struct sas_identify_frame
*id
=
1166 (struct sas_identify_frame
*)frame_rcvd
;
1168 dev_info(dev
, "phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
1169 for (i
= 0; i
< 6; i
++) {
1170 u32 idaf
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1171 RX_IDAF_DWORD0
+ (i
* 4));
1172 frame_rcvd
[i
] = __swab32(idaf
);
1174 sas_phy
->oob_mode
= SAS_OOB_MODE
;
1175 memcpy(sas_phy
->attached_sas_addr
,
1178 phy
->phy_type
|= PORT_TYPE_SAS
;
1179 phy
->identify
.device_type
= id
->dev_type
;
1180 phy
->frame_rcvd_size
= sizeof(struct sas_identify_frame
);
1181 if (phy
->identify
.device_type
== SAS_END_DEVICE
)
1182 phy
->identify
.target_port_protocols
=
1184 else if (phy
->identify
.device_type
!= SAS_PHY_UNUSED
)
1185 phy
->identify
.target_port_protocols
=
1189 phy
->port_id
= port_id
;
1190 phy
->phy_attached
= 1;
1191 queue_work(hisi_hba
->wq
, &phy
->phyup_ws
);
1194 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
1195 CHL_INT0_SL_PHY_ENABLE_MSK
);
1196 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 0);
1201 static int phy_down_v3_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
1204 u32 phy_state
, sl_ctrl
, txid_auto
;
1205 struct device
*dev
= hisi_hba
->dev
;
1207 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 1);
1209 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1210 dev_info(dev
, "phydown: phy%d phy_state=0x%x\n", phy_no
, phy_state
);
1211 hisi_sas_phy_down(hisi_hba
, phy_no
, (phy_state
& 1 << phy_no
) ? 1 : 0);
1213 sl_ctrl
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
1214 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
,
1215 sl_ctrl
&(~SL_CTA_MSK
));
1217 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
1218 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
1219 txid_auto
| CT3_MSK
);
1221 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
, CHL_INT0_NOT_RDY_MSK
);
1222 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 0);
1227 static void phy_bcast_v3_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
1229 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1230 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1231 struct sas_ha_struct
*sas_ha
= &hisi_hba
->sha
;
1233 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 1);
1234 sas_ha
->notify_port_event(sas_phy
, PORTE_BROADCAST_RCVD
);
1235 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
1236 CHL_INT0_SL_RX_BCST_ACK_MSK
);
1237 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 0);
1240 static irqreturn_t
int_phy_up_down_bcast_v3_hw(int irq_no
, void *p
)
1242 struct hisi_hba
*hisi_hba
= p
;
1245 irqreturn_t res
= IRQ_NONE
;
1247 irq_msk
= hisi_sas_read32(hisi_hba
, CHNL_INT_STATUS
)
1251 u32 irq_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1253 u32 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1254 int rdy
= phy_state
& (1 << phy_no
);
1257 if (irq_value
& CHL_INT0_SL_PHY_ENABLE_MSK
)
1259 if (phy_up_v3_hw(phy_no
, hisi_hba
)
1262 if (irq_value
& CHL_INT0_SL_RX_BCST_ACK_MSK
)
1264 phy_bcast_v3_hw(phy_no
, hisi_hba
);
1266 if (irq_value
& CHL_INT0_NOT_RDY_MSK
)
1268 if (phy_down_v3_hw(phy_no
, hisi_hba
)
1280 static irqreturn_t
int_chnl_int_v3_hw(int irq_no
, void *p
)
1282 struct hisi_hba
*hisi_hba
= p
;
1283 struct device
*dev
= hisi_hba
->dev
;
1284 u32 ent_msk
, ent_tmp
, irq_msk
;
1287 ent_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
1289 ent_msk
|= ENT_INT_SRC_MSK3_ENT95_MSK_MSK
;
1290 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_msk
);
1292 irq_msk
= hisi_sas_read32(hisi_hba
, CHNL_INT_STATUS
)
1296 u32 irq_value0
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1298 u32 irq_value1
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1300 u32 irq_value2
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1303 if ((irq_msk
& (4 << (phy_no
* 4))) &&
1305 if (irq_value1
& (CHL_INT1_DMAC_RX_ECC_ERR_MSK
|
1306 CHL_INT1_DMAC_TX_ECC_ERR_MSK
))
1307 panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
1308 dev_name(dev
), irq_value1
);
1310 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1311 CHL_INT1
, irq_value1
);
1314 if (irq_msk
& (8 << (phy_no
* 4)) && irq_value2
)
1315 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1316 CHL_INT2
, irq_value2
);
1319 if (irq_msk
& (2 << (phy_no
* 4)) && irq_value0
) {
1320 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1321 CHL_INT0
, irq_value0
1322 & (~CHL_INT0_SL_RX_BCST_ACK_MSK
)
1323 & (~CHL_INT0_SL_PHY_ENABLE_MSK
)
1324 & (~CHL_INT0_NOT_RDY_MSK
));
1326 irq_msk
&= ~(0xe << (phy_no
* 4));
1330 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_tmp
);
1336 slot_err_v3_hw(struct hisi_hba
*hisi_hba
, struct sas_task
*task
,
1337 struct hisi_sas_slot
*slot
)
1339 struct task_status_struct
*ts
= &task
->task_status
;
1340 struct hisi_sas_complete_v3_hdr
*complete_queue
=
1341 hisi_hba
->complete_hdr
[slot
->cmplt_queue
];
1342 struct hisi_sas_complete_v3_hdr
*complete_hdr
=
1343 &complete_queue
[slot
->cmplt_queue_slot
];
1344 struct hisi_sas_err_record_v3
*record
=
1345 hisi_sas_status_buf_addr_mem(slot
);
1346 u32 dma_rx_err_type
= record
->dma_rx_err_type
;
1347 u32 trans_tx_fail_type
= record
->trans_tx_fail_type
;
1349 switch (task
->task_proto
) {
1350 case SAS_PROTOCOL_SSP
:
1351 if (dma_rx_err_type
& RX_DATA_LEN_UNDERFLOW_MSK
) {
1352 ts
->residual
= trans_tx_fail_type
;
1353 ts
->stat
= SAS_DATA_UNDERRUN
;
1354 } else if (complete_hdr
->dw3
& CMPLT_HDR_IO_IN_TARGET_MSK
) {
1355 ts
->stat
= SAS_QUEUE_FULL
;
1358 ts
->stat
= SAS_OPEN_REJECT
;
1359 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
1362 case SAS_PROTOCOL_SATA
:
1363 case SAS_PROTOCOL_STP
:
1364 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
1365 if (dma_rx_err_type
& RX_DATA_LEN_UNDERFLOW_MSK
) {
1366 ts
->residual
= trans_tx_fail_type
;
1367 ts
->stat
= SAS_DATA_UNDERRUN
;
1368 } else if (complete_hdr
->dw3
& CMPLT_HDR_IO_IN_TARGET_MSK
) {
1369 ts
->stat
= SAS_PHY_DOWN
;
1372 ts
->stat
= SAS_OPEN_REJECT
;
1373 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
1375 hisi_sas_sata_done(task
, slot
);
1377 case SAS_PROTOCOL_SMP
:
1378 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
1386 slot_complete_v3_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_slot
*slot
)
1388 struct sas_task
*task
= slot
->task
;
1389 struct hisi_sas_device
*sas_dev
;
1390 struct device
*dev
= hisi_hba
->dev
;
1391 struct task_status_struct
*ts
;
1392 struct domain_device
*device
;
1393 enum exec_status sts
;
1394 struct hisi_sas_complete_v3_hdr
*complete_queue
=
1395 hisi_hba
->complete_hdr
[slot
->cmplt_queue
];
1396 struct hisi_sas_complete_v3_hdr
*complete_hdr
=
1397 &complete_queue
[slot
->cmplt_queue_slot
];
1399 unsigned long flags
;
1401 if (unlikely(!task
|| !task
->lldd_task
|| !task
->dev
))
1404 ts
= &task
->task_status
;
1406 sas_dev
= device
->lldd_dev
;
1408 spin_lock_irqsave(&task
->task_state_lock
, flags
);
1409 aborted
= task
->task_state_flags
& SAS_TASK_STATE_ABORTED
;
1410 task
->task_state_flags
&=
1411 ~(SAS_TASK_STATE_PENDING
| SAS_TASK_AT_INITIATOR
);
1412 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
1414 memset(ts
, 0, sizeof(*ts
));
1415 ts
->resp
= SAS_TASK_COMPLETE
;
1416 if (unlikely(aborted
)) {
1417 ts
->stat
= SAS_ABORTED_TASK
;
1418 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
1422 if (unlikely(!sas_dev
)) {
1423 dev_dbg(dev
, "slot complete: port has not device\n");
1424 ts
->stat
= SAS_PHY_DOWN
;
1429 * Use SAS+TMF status codes
1431 switch ((complete_hdr
->dw0
& CMPLT_HDR_ABORT_STAT_MSK
)
1432 >> CMPLT_HDR_ABORT_STAT_OFF
) {
1433 case STAT_IO_ABORTED
:
1434 /* this IO has been aborted by abort command */
1435 ts
->stat
= SAS_ABORTED_TASK
;
1437 case STAT_IO_COMPLETE
:
1438 /* internal abort command complete */
1439 ts
->stat
= TMF_RESP_FUNC_SUCC
;
1441 case STAT_IO_NO_DEVICE
:
1442 ts
->stat
= TMF_RESP_FUNC_COMPLETE
;
1444 case STAT_IO_NOT_VALID
:
1446 * abort single IO, the controller can't find the IO
1448 ts
->stat
= TMF_RESP_FUNC_FAILED
;
1454 /* check for erroneous completion */
1455 if ((complete_hdr
->dw0
& CMPLT_HDR_CMPLT_MSK
) == 0x3) {
1456 slot_err_v3_hw(hisi_hba
, task
, slot
);
1457 if (unlikely(slot
->abort
))
1462 switch (task
->task_proto
) {
1463 case SAS_PROTOCOL_SSP
: {
1464 struct ssp_response_iu
*iu
=
1465 hisi_sas_status_buf_addr_mem(slot
) +
1466 sizeof(struct hisi_sas_err_record
);
1468 sas_ssp_task_response(dev
, task
, iu
);
1471 case SAS_PROTOCOL_SMP
: {
1472 struct scatterlist
*sg_resp
= &task
->smp_task
.smp_resp
;
1475 ts
->stat
= SAM_STAT_GOOD
;
1476 to
= kmap_atomic(sg_page(sg_resp
));
1478 dma_unmap_sg(dev
, &task
->smp_task
.smp_resp
, 1,
1480 dma_unmap_sg(dev
, &task
->smp_task
.smp_req
, 1,
1482 memcpy(to
+ sg_resp
->offset
,
1483 hisi_sas_status_buf_addr_mem(slot
) +
1484 sizeof(struct hisi_sas_err_record
),
1485 sg_dma_len(sg_resp
));
1489 case SAS_PROTOCOL_SATA
:
1490 case SAS_PROTOCOL_STP
:
1491 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
1492 ts
->stat
= SAM_STAT_GOOD
;
1493 hisi_sas_sata_done(task
, slot
);
1496 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
1500 if (!slot
->port
->port_attached
) {
1501 dev_err(dev
, "slot complete: port %d has removed\n",
1502 slot
->port
->sas_port
.id
);
1503 ts
->stat
= SAS_PHY_DOWN
;
1507 spin_lock_irqsave(&task
->task_state_lock
, flags
);
1508 task
->task_state_flags
|= SAS_TASK_STATE_DONE
;
1509 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
1510 spin_lock_irqsave(&hisi_hba
->lock
, flags
);
1511 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
1512 spin_unlock_irqrestore(&hisi_hba
->lock
, flags
);
1515 if (task
->task_done
)
1516 task
->task_done(task
);
1521 static void cq_tasklet_v3_hw(unsigned long val
)
1523 struct hisi_sas_cq
*cq
= (struct hisi_sas_cq
*)val
;
1524 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
1525 struct hisi_sas_slot
*slot
;
1526 struct hisi_sas_itct
*itct
;
1527 struct hisi_sas_complete_v3_hdr
*complete_queue
;
1528 u32 rd_point
= cq
->rd_point
, wr_point
, dev_id
;
1530 struct hisi_sas_dq
*dq
= &hisi_hba
->dq
[queue
];
1532 complete_queue
= hisi_hba
->complete_hdr
[queue
];
1534 spin_lock(&dq
->lock
);
1535 wr_point
= hisi_sas_read32(hisi_hba
, COMPL_Q_0_WR_PTR
+
1538 while (rd_point
!= wr_point
) {
1539 struct hisi_sas_complete_v3_hdr
*complete_hdr
;
1542 complete_hdr
= &complete_queue
[rd_point
];
1544 /* Check for NCQ completion */
1545 if (complete_hdr
->act
) {
1546 u32 act_tmp
= complete_hdr
->act
;
1547 int ncq_tag_count
= ffs(act_tmp
);
1549 dev_id
= (complete_hdr
->dw1
& CMPLT_HDR_DEV_ID_MSK
) >>
1550 CMPLT_HDR_DEV_ID_OFF
;
1551 itct
= &hisi_hba
->itct
[dev_id
];
1553 /* The NCQ tags are held in the itct header */
1554 while (ncq_tag_count
) {
1555 __le64
*ncq_tag
= &itct
->qw4_15
[0];
1558 iptt
= (ncq_tag
[ncq_tag_count
/ 5]
1559 >> (ncq_tag_count
% 5) * 12) & 0xfff;
1561 slot
= &hisi_hba
->slot_info
[iptt
];
1562 slot
->cmplt_queue_slot
= rd_point
;
1563 slot
->cmplt_queue
= queue
;
1564 slot_complete_v3_hw(hisi_hba
, slot
);
1566 act_tmp
&= ~(1 << ncq_tag_count
);
1567 ncq_tag_count
= ffs(act_tmp
);
1570 iptt
= (complete_hdr
->dw1
) & CMPLT_HDR_IPTT_MSK
;
1571 slot
= &hisi_hba
->slot_info
[iptt
];
1572 slot
->cmplt_queue_slot
= rd_point
;
1573 slot
->cmplt_queue
= queue
;
1574 slot_complete_v3_hw(hisi_hba
, slot
);
1577 if (++rd_point
>= HISI_SAS_QUEUE_SLOTS
)
1581 /* update rd_point */
1582 cq
->rd_point
= rd_point
;
1583 hisi_sas_write32(hisi_hba
, COMPL_Q_0_RD_PTR
+ (0x14 * queue
), rd_point
);
1584 spin_unlock(&dq
->lock
);
1587 static irqreturn_t
cq_interrupt_v3_hw(int irq_no
, void *p
)
1589 struct hisi_sas_cq
*cq
= p
;
1590 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
1593 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 1 << queue
);
1595 tasklet_schedule(&cq
->tasklet
);
1600 static int interrupt_init_v3_hw(struct hisi_hba
*hisi_hba
)
1602 struct device
*dev
= hisi_hba
->dev
;
1603 struct pci_dev
*pdev
= hisi_hba
->pci_dev
;
1606 int max_msi
= HISI_SAS_MSI_COUNT_V3_HW
;
1608 vectors
= pci_alloc_irq_vectors(hisi_hba
->pci_dev
, 1,
1609 max_msi
, PCI_IRQ_MSI
);
1610 if (vectors
< max_msi
) {
1611 dev_err(dev
, "could not allocate all msi (%d)\n", vectors
);
1615 rc
= devm_request_irq(dev
, pci_irq_vector(pdev
, 1),
1616 int_phy_up_down_bcast_v3_hw
, 0,
1617 DRV_NAME
" phy", hisi_hba
);
1619 dev_err(dev
, "could not request phy interrupt, rc=%d\n", rc
);
1621 goto free_irq_vectors
;
1624 rc
= devm_request_irq(dev
, pci_irq_vector(pdev
, 2),
1625 int_chnl_int_v3_hw
, 0,
1626 DRV_NAME
" channel", hisi_hba
);
1628 dev_err(dev
, "could not request chnl interrupt, rc=%d\n", rc
);
1633 /* Init tasklets for cq only */
1634 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
1635 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[i
];
1636 struct tasklet_struct
*t
= &cq
->tasklet
;
1638 rc
= devm_request_irq(dev
, pci_irq_vector(pdev
, i
+16),
1639 cq_interrupt_v3_hw
, 0,
1640 DRV_NAME
" cq", cq
);
1643 "could not request cq%d interrupt, rc=%d\n",
1649 tasklet_init(t
, cq_tasklet_v3_hw
, (unsigned long)cq
);
1655 for (k
= 0; k
< i
; k
++) {
1656 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[k
];
1658 free_irq(pci_irq_vector(pdev
, k
+16), cq
);
1660 free_irq(pci_irq_vector(pdev
, 2), hisi_hba
);
1662 free_irq(pci_irq_vector(pdev
, 1), hisi_hba
);
1664 pci_free_irq_vectors(pdev
);
1668 static int hisi_sas_v3_init(struct hisi_hba
*hisi_hba
)
1672 rc
= hw_init_v3_hw(hisi_hba
);
1676 rc
= interrupt_init_v3_hw(hisi_hba
);
1683 static void interrupt_disable_v3_hw(struct hisi_hba
*hisi_hba
)
1685 struct pci_dev
*pdev
= hisi_hba
->pci_dev
;
1688 synchronize_irq(pci_irq_vector(pdev
, 1));
1689 synchronize_irq(pci_irq_vector(pdev
, 2));
1690 synchronize_irq(pci_irq_vector(pdev
, 11));
1691 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
1692 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+ 0x4 * i
, 0x1);
1693 synchronize_irq(pci_irq_vector(pdev
, i
+ 16));
1696 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0xffffffff);
1697 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0xffffffff);
1698 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0xffffffff);
1699 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0xffffffff);
1701 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1702 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xffffffff);
1703 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0xffffffff);
1704 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_NOT_RDY_MSK
, 0x1);
1705 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_PHY_ENA_MSK
, 0x1);
1706 hisi_sas_phy_write32(hisi_hba
, i
, SL_RX_BCAST_CHK_MSK
, 0x1);
1710 static u32
get_phys_state_v3_hw(struct hisi_hba
*hisi_hba
)
1712 return hisi_sas_read32(hisi_hba
, PHY_STATE
);
1715 static int soft_reset_v3_hw(struct hisi_hba
*hisi_hba
)
1717 struct device
*dev
= hisi_hba
->dev
;
1721 interrupt_disable_v3_hw(hisi_hba
);
1722 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0x0);
1724 hisi_sas_stop_phys(hisi_hba
);
1728 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
+ AM_CTRL_GLOBAL
, 0x1);
1730 /* wait until bus idle */
1731 rc
= readl_poll_timeout(hisi_hba
->regs
+ AXI_MASTER_CFG_BASE
+
1732 AM_CURR_TRANS_RETURN
, status
, status
== 0x3, 10, 100);
1734 dev_err(dev
, "axi bus is not idle, rc = %d\n", rc
);
1738 hisi_sas_init_mem(hisi_hba
);
1740 return hw_init_v3_hw(hisi_hba
);
1743 static const struct hisi_sas_hw hisi_sas_v3_hw
= {
1744 .hw_init
= hisi_sas_v3_init
,
1745 .setup_itct
= setup_itct_v3_hw
,
1746 .max_command_entries
= HISI_SAS_COMMAND_ENTRIES_V3_HW
,
1747 .get_wideport_bitmap
= get_wideport_bitmap_v3_hw
,
1748 .complete_hdr_size
= sizeof(struct hisi_sas_complete_v3_hdr
),
1749 .free_device
= free_device_v3_hw
,
1750 .sl_notify
= sl_notify_v3_hw
,
1751 .prep_ssp
= prep_ssp_v3_hw
,
1752 .prep_smp
= prep_smp_v3_hw
,
1753 .prep_stp
= prep_ata_v3_hw
,
1754 .prep_abort
= prep_abort_v3_hw
,
1755 .get_free_slot
= get_free_slot_v3_hw
,
1756 .start_delivery
= start_delivery_v3_hw
,
1757 .slot_complete
= slot_complete_v3_hw
,
1758 .phys_init
= phys_init_v3_hw
,
1759 .phy_enable
= enable_phy_v3_hw
,
1760 .phy_disable
= disable_phy_v3_hw
,
1761 .phy_hard_reset
= phy_hard_reset_v3_hw
,
1762 .phy_get_max_linkrate
= phy_get_max_linkrate_v3_hw
,
1763 .dereg_device
= dereg_device_v3_hw
,
1764 .soft_reset
= soft_reset_v3_hw
,
1765 .get_phys_state
= get_phys_state_v3_hw
,
1768 static struct Scsi_Host
*
1769 hisi_sas_shost_alloc_pci(struct pci_dev
*pdev
)
1771 struct Scsi_Host
*shost
;
1772 struct hisi_hba
*hisi_hba
;
1773 struct device
*dev
= &pdev
->dev
;
1775 shost
= scsi_host_alloc(hisi_sas_sht
, sizeof(*hisi_hba
));
1778 hisi_hba
= shost_priv(shost
);
1780 hisi_hba
->hw
= &hisi_sas_v3_hw
;
1781 hisi_hba
->pci_dev
= pdev
;
1782 hisi_hba
->dev
= dev
;
1783 hisi_hba
->shost
= shost
;
1784 SHOST_TO_SAS_HA(shost
) = &hisi_hba
->sha
;
1786 init_timer(&hisi_hba
->timer
);
1788 if (hisi_sas_get_fw_info(hisi_hba
) < 0)
1791 if (hisi_sas_alloc(hisi_hba
, shost
)) {
1792 hisi_sas_free(hisi_hba
);
1798 dev_err(dev
, "shost alloc failed\n");
1803 hisi_sas_v3_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1805 struct Scsi_Host
*shost
;
1806 struct hisi_hba
*hisi_hba
;
1807 struct device
*dev
= &pdev
->dev
;
1808 struct asd_sas_phy
**arr_phy
;
1809 struct asd_sas_port
**arr_port
;
1810 struct sas_ha_struct
*sha
;
1811 int rc
, phy_nr
, port_nr
, i
;
1813 rc
= pci_enable_device(pdev
);
1817 pci_set_master(pdev
);
1819 rc
= pci_request_regions(pdev
, DRV_NAME
);
1821 goto err_out_disable_device
;
1823 if ((pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) != 0) ||
1824 (pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64)) != 0)) {
1825 if ((pci_set_dma_mask(pdev
, DMA_BIT_MASK(32)) != 0) ||
1826 (pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)) != 0)) {
1827 dev_err(dev
, "No usable DMA addressing method\n");
1829 goto err_out_regions
;
1833 shost
= hisi_sas_shost_alloc_pci(pdev
);
1836 goto err_out_regions
;
1839 sha
= SHOST_TO_SAS_HA(shost
);
1840 hisi_hba
= shost_priv(shost
);
1841 dev_set_drvdata(dev
, sha
);
1843 hisi_hba
->regs
= pcim_iomap(pdev
, 5, 0);
1844 if (!hisi_hba
->regs
) {
1845 dev_err(dev
, "cannot map register.\n");
1850 phy_nr
= port_nr
= hisi_hba
->n_phy
;
1852 arr_phy
= devm_kcalloc(dev
, phy_nr
, sizeof(void *), GFP_KERNEL
);
1853 arr_port
= devm_kcalloc(dev
, port_nr
, sizeof(void *), GFP_KERNEL
);
1854 if (!arr_phy
|| !arr_port
) {
1859 sha
->sas_phy
= arr_phy
;
1860 sha
->sas_port
= arr_port
;
1861 sha
->core
.shost
= shost
;
1862 sha
->lldd_ha
= hisi_hba
;
1864 shost
->transportt
= hisi_sas_stt
;
1865 shost
->max_id
= HISI_SAS_MAX_DEVICES
;
1866 shost
->max_lun
= ~0;
1867 shost
->max_channel
= 1;
1868 shost
->max_cmd_len
= 16;
1869 shost
->sg_tablesize
= min_t(u16
, SG_ALL
, HISI_SAS_SGE_PAGE_CNT
);
1870 shost
->can_queue
= hisi_hba
->hw
->max_command_entries
;
1871 shost
->cmd_per_lun
= hisi_hba
->hw
->max_command_entries
;
1873 sha
->sas_ha_name
= DRV_NAME
;
1875 sha
->lldd_module
= THIS_MODULE
;
1876 sha
->sas_addr
= &hisi_hba
->sas_addr
[0];
1877 sha
->num_phys
= hisi_hba
->n_phy
;
1878 sha
->core
.shost
= hisi_hba
->shost
;
1880 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1881 sha
->sas_phy
[i
] = &hisi_hba
->phy
[i
].sas_phy
;
1882 sha
->sas_port
[i
] = &hisi_hba
->port
[i
].sas_port
;
1885 hisi_sas_init_add(hisi_hba
);
1887 rc
= scsi_add_host(shost
, dev
);
1891 rc
= sas_register_ha(sha
);
1893 goto err_out_register_ha
;
1895 rc
= hisi_hba
->hw
->hw_init(hisi_hba
);
1897 goto err_out_register_ha
;
1899 scsi_scan_host(shost
);
1903 err_out_register_ha
:
1904 scsi_remove_host(shost
);
1908 pci_release_regions(pdev
);
1909 err_out_disable_device
:
1910 pci_disable_device(pdev
);
1916 hisi_sas_v3_destroy_irqs(struct pci_dev
*pdev
, struct hisi_hba
*hisi_hba
)
1920 free_irq(pci_irq_vector(pdev
, 1), hisi_hba
);
1921 free_irq(pci_irq_vector(pdev
, 2), hisi_hba
);
1922 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
1923 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[i
];
1925 free_irq(pci_irq_vector(pdev
, i
+16), cq
);
1926 tasklet_kill(&cq
->tasklet
);
1928 pci_free_irq_vectors(pdev
);
1931 static void hisi_sas_v3_remove(struct pci_dev
*pdev
)
1933 struct device
*dev
= &pdev
->dev
;
1934 struct sas_ha_struct
*sha
= dev_get_drvdata(dev
);
1935 struct hisi_hba
*hisi_hba
= sha
->lldd_ha
;
1937 sas_unregister_ha(sha
);
1938 sas_remove_host(sha
->core
.shost
);
1940 hisi_sas_free(hisi_hba
);
1941 hisi_sas_v3_destroy_irqs(pdev
, hisi_hba
);
1942 pci_release_regions(pdev
);
1943 pci_disable_device(pdev
);
1947 /* instances of the controller */
1951 static const struct pci_device_id sas_v3_pci_table
[] = {
1952 { PCI_VDEVICE(HUAWEI
, 0xa230), hip08
},
1956 static struct pci_driver sas_v3_pci_driver
= {
1958 .id_table
= sas_v3_pci_table
,
1959 .probe
= hisi_sas_v3_probe
,
1960 .remove
= hisi_sas_v3_remove
,
1963 module_pci_driver(sas_v3_pci_driver
);
1965 MODULE_VERSION(DRV_VERSION
);
1966 MODULE_LICENSE("GPL");
1967 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
1968 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
1969 MODULE_ALIAS("platform:" DRV_NAME
);