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scsi: hisi_sas: do link reset for some CHL_INT2 ints
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v3_hw.c
1 /*
2 * Copyright (c) 2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 #include "hisi_sas.h"
12 #define DRV_NAME "hisi_sas_v3_hw"
13
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
26 #define ITCT_CLR 0x44
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CFG_1US_TIMER_TRSH 0xcc
55 #define CHNL_INT_STATUS 0x148
56 #define HGC_AXI_FIFO_ERR_INFO 0x154
57 #define AXI_ERR_INFO_OFF 0
58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
59 #define FIFO_ERR_INFO_OFF 8
60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
61 #define INT_COAL_EN 0x19c
62 #define OQ_INT_COAL_TIME 0x1a0
63 #define OQ_INT_COAL_CNT 0x1a4
64 #define ENT_INT_COAL_TIME 0x1a8
65 #define ENT_INT_COAL_CNT 0x1ac
66 #define OQ_INT_SRC 0x1b0
67 #define OQ_INT_SRC_MSK 0x1b4
68 #define ENT_INT_SRC1 0x1b8
69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
73 #define ENT_INT_SRC2 0x1bc
74 #define ENT_INT_SRC3 0x1c0
75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
78 #define ENT_INT_SRC3_AXI_OFF 11
79 #define ENT_INT_SRC3_FIFO_OFF 12
80 #define ENT_INT_SRC3_LM_OFF 14
81 #define ENT_INT_SRC3_ITC_INT_OFF 15
82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
83 #define ENT_INT_SRC3_ABT_OFF 16
84 #define ENT_INT_SRC_MSK1 0x1c4
85 #define ENT_INT_SRC_MSK2 0x1c8
86 #define ENT_INT_SRC_MSK3 0x1cc
87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
89 #define CHNL_ENT_INT_MSK 0x1d4
90 #define HGC_COM_INT_MSK 0x1d8
91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
92 #define SAS_ECC_INTR 0x1e8
93 #define SAS_ECC_INTR_MSK 0x1ec
94 #define HGC_ERR_STAT_EN 0x238
95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
97 #define DLVRY_Q_0_DEPTH 0x268
98 #define DLVRY_Q_0_WR_PTR 0x26c
99 #define DLVRY_Q_0_RD_PTR 0x270
100 #define HYPER_STREAM_ID_EN_CFG 0xc80
101 #define OQ0_INT_SRC_MSK 0xc90
102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
104 #define COMPL_Q_0_DEPTH 0x4e8
105 #define COMPL_Q_0_WR_PTR 0x4ec
106 #define COMPL_Q_0_RD_PTR 0x4f0
107 #define AWQOS_AWCACHE_CFG 0xc84
108 #define ARQOS_ARCACHE_CFG 0xc88
109
110 /* phy registers requiring init */
111 #define PORT_BASE (0x2000)
112 #define PHY_CFG (PORT_BASE + 0x0)
113 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
114 #define PHY_CFG_ENA_OFF 0
115 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
116 #define PHY_CFG_DC_OPT_OFF 2
117 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
118 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
119 #define PHY_CTRL (PORT_BASE + 0x14)
120 #define PHY_CTRL_RESET_OFF 0
121 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
122 #define SL_CFG (PORT_BASE + 0x84)
123 #define SL_CONTROL (PORT_BASE + 0x94)
124 #define SL_CONTROL_NOTIFY_EN_OFF 0
125 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
126 #define SL_CTA_OFF 17
127 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
128 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
129 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
130 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
131 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
132 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
133 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
134 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
135 #define TXID_AUTO (PORT_BASE + 0xb8)
136 #define CT3_OFF 1
137 #define CT3_MSK (0x1 << CT3_OFF)
138 #define TX_HARDRST_OFF 2
139 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
140 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
141 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
142 #define STP_LINK_TIMER (PORT_BASE + 0x120)
143 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
144 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
145 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
146 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
147 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
148 #define CHL_INT0 (PORT_BASE + 0x1b4)
149 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
150 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
151 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
152 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
153 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
154 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
155 #define CHL_INT0_NOT_RDY_OFF 4
156 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
157 #define CHL_INT0_PHY_RDY_OFF 5
158 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
159 #define CHL_INT1 (PORT_BASE + 0x1b8)
160 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
161 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
162 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
163 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
164 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
165 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
166 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
167 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
168 #define CHL_INT2 (PORT_BASE + 0x1bc)
169 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
170 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
171 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
172 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
173 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
174 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
175 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
176 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
177 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
178 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
179 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
180 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
181 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
182 #define DMA_TX_STATUS_BUSY_OFF 0
183 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
184 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
185 #define DMA_RX_STATUS_BUSY_OFF 0
186 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
187 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
188 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
189 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
190 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
191
192 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
193 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
194 #error Max ITCT exceeded
195 #endif
196
197 #define AXI_MASTER_CFG_BASE (0x5000)
198 #define AM_CTRL_GLOBAL (0x0)
199 #define AM_CURR_TRANS_RETURN (0x150)
200
201 #define AM_CFG_MAX_TRANS (0x5010)
202 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
203 #define AXI_CFG (0x5100)
204 #define AM_ROB_ECC_ERR_ADDR (0x510c)
205 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
206 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
207 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
208 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
209
210 /* RAS registers need init */
211 #define RAS_BASE (0x6000)
212 #define SAS_RAS_INTR0 (RAS_BASE)
213 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
214 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
215 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
216
217 /* HW dma structures */
218 /* Delivery queue header */
219 /* dw0 */
220 #define CMD_HDR_ABORT_FLAG_OFF 0
221 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
222 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
223 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
224 #define CMD_HDR_RESP_REPORT_OFF 5
225 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
226 #define CMD_HDR_TLR_CTRL_OFF 6
227 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
228 #define CMD_HDR_PORT_OFF 18
229 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
230 #define CMD_HDR_PRIORITY_OFF 27
231 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
232 #define CMD_HDR_CMD_OFF 29
233 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
234 /* dw1 */
235 #define CMD_HDR_UNCON_CMD_OFF 3
236 #define CMD_HDR_DIR_OFF 5
237 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
238 #define CMD_HDR_RESET_OFF 7
239 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
240 #define CMD_HDR_VDTL_OFF 10
241 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
242 #define CMD_HDR_FRAME_TYPE_OFF 11
243 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
244 #define CMD_HDR_DEV_ID_OFF 16
245 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
246 /* dw2 */
247 #define CMD_HDR_CFL_OFF 0
248 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
249 #define CMD_HDR_NCQ_TAG_OFF 10
250 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
251 #define CMD_HDR_MRFL_OFF 15
252 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
253 #define CMD_HDR_SG_MOD_OFF 24
254 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
255 /* dw3 */
256 #define CMD_HDR_IPTT_OFF 0
257 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
258 /* dw6 */
259 #define CMD_HDR_DIF_SGL_LEN_OFF 0
260 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
261 #define CMD_HDR_DATA_SGL_LEN_OFF 16
262 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
263 /* dw7 */
264 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
265 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
266 #define CMD_HDR_ABORT_IPTT_OFF 16
267 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
268
269 /* Completion header */
270 /* dw0 */
271 #define CMPLT_HDR_CMPLT_OFF 0
272 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
273 #define CMPLT_HDR_ERROR_PHASE_OFF 2
274 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
275 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
276 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
277 #define CMPLT_HDR_ERX_OFF 12
278 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
279 #define CMPLT_HDR_ABORT_STAT_OFF 13
280 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
281 /* abort_stat */
282 #define STAT_IO_NOT_VALID 0x1
283 #define STAT_IO_NO_DEVICE 0x2
284 #define STAT_IO_COMPLETE 0x3
285 #define STAT_IO_ABORTED 0x4
286 /* dw1 */
287 #define CMPLT_HDR_IPTT_OFF 0
288 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
289 #define CMPLT_HDR_DEV_ID_OFF 16
290 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
291 /* dw3 */
292 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
293 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
294
295 /* ITCT header */
296 /* qw0 */
297 #define ITCT_HDR_DEV_TYPE_OFF 0
298 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
299 #define ITCT_HDR_VALID_OFF 2
300 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
301 #define ITCT_HDR_MCR_OFF 5
302 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
303 #define ITCT_HDR_VLN_OFF 9
304 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
305 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
306 #define ITCT_HDR_AWT_CONTINUE_OFF 25
307 #define ITCT_HDR_PORT_ID_OFF 28
308 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
309 /* qw2 */
310 #define ITCT_HDR_INLT_OFF 0
311 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
312 #define ITCT_HDR_RTOLT_OFF 48
313 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
314
315 struct hisi_sas_complete_v3_hdr {
316 __le32 dw0;
317 __le32 dw1;
318 __le32 act;
319 __le32 dw3;
320 };
321
322 struct hisi_sas_err_record_v3 {
323 /* dw0 */
324 __le32 trans_tx_fail_type;
325
326 /* dw1 */
327 __le32 trans_rx_fail_type;
328
329 /* dw2 */
330 __le16 dma_tx_err_type;
331 __le16 sipc_rx_err_type;
332
333 /* dw3 */
334 __le32 dma_rx_err_type;
335 };
336
337 #define RX_DATA_LEN_UNDERFLOW_OFF 6
338 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
339
340 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
341 #define HISI_SAS_MSI_COUNT_V3_HW 32
342
343 enum {
344 HISI_SAS_PHY_PHY_UPDOWN,
345 HISI_SAS_PHY_CHNL_INT,
346 HISI_SAS_PHY_INT_NR
347 };
348
349 #define DIR_NO_DATA 0
350 #define DIR_TO_INI 1
351 #define DIR_TO_DEVICE 2
352 #define DIR_RESERVED 3
353
354 #define CMD_IS_UNCONSTRAINT(cmd) \
355 ((cmd == ATA_CMD_READ_LOG_EXT) || \
356 (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
357 (cmd == ATA_CMD_DEV_RESET))
358
359 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
360 {
361 void __iomem *regs = hisi_hba->regs + off;
362
363 return readl(regs);
364 }
365
366 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
367 {
368 void __iomem *regs = hisi_hba->regs + off;
369
370 return readl_relaxed(regs);
371 }
372
373 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
374 {
375 void __iomem *regs = hisi_hba->regs + off;
376
377 writel(val, regs);
378 }
379
380 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
381 u32 off, u32 val)
382 {
383 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
384
385 writel(val, regs);
386 }
387
388 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
389 int phy_no, u32 off)
390 {
391 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
392
393 return readl(regs);
394 }
395
396 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
397 {
398 int i;
399
400 /* Global registers init */
401 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
402 (u32)((1ULL << hisi_hba->queue_count) - 1));
403 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
404 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
405 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
406 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
407 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
408 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
409 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
410 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
411 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
412 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
413 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
414 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
415 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff);
416 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
417 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
418 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
419 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
420 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
421 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
422 for (i = 0; i < hisi_hba->queue_count; i++)
423 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
424
425 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
426 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE, 0x30000);
427
428 for (i = 0; i < hisi_hba->n_phy; i++) {
429 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x801);
430 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
431 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
432 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
433 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
434 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff87ffff);
435 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
436 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
437 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
438 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
439 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
440 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
441 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
442 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199b4fa);
443 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG,
444 0xa03e8);
445 hisi_sas_phy_write32(hisi_hba, i, SAS_STP_CON_TIMER_CFG,
446 0xa03e8);
447 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER,
448 0x7f7a120);
449 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER,
450 0x2a0a80);
451 }
452 for (i = 0; i < hisi_hba->queue_count; i++) {
453 /* Delivery queue */
454 hisi_sas_write32(hisi_hba,
455 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
456 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
457
458 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
459 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
460
461 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
462 HISI_SAS_QUEUE_SLOTS);
463
464 /* Completion queue */
465 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
466 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
467
468 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
469 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
470
471 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
472 HISI_SAS_QUEUE_SLOTS);
473 }
474
475 /* itct */
476 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
477 lower_32_bits(hisi_hba->itct_dma));
478
479 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
480 upper_32_bits(hisi_hba->itct_dma));
481
482 /* iost */
483 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
484 lower_32_bits(hisi_hba->iost_dma));
485
486 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
487 upper_32_bits(hisi_hba->iost_dma));
488
489 /* breakpoint */
490 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
491 lower_32_bits(hisi_hba->breakpoint_dma));
492
493 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
494 upper_32_bits(hisi_hba->breakpoint_dma));
495
496 /* SATA broken msg */
497 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
498 lower_32_bits(hisi_hba->sata_breakpoint_dma));
499
500 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
501 upper_32_bits(hisi_hba->sata_breakpoint_dma));
502
503 /* SATA initial fis */
504 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
505 lower_32_bits(hisi_hba->initial_fis_dma));
506
507 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
508 upper_32_bits(hisi_hba->initial_fis_dma));
509
510 /* RAS registers init */
511 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
512 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
513 }
514
515 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
516 {
517 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
518
519 cfg &= ~PHY_CFG_DC_OPT_MSK;
520 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
521 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
522 }
523
524 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
525 {
526 struct sas_identify_frame identify_frame;
527 u32 *identify_buffer;
528
529 memset(&identify_frame, 0, sizeof(identify_frame));
530 identify_frame.dev_type = SAS_END_DEVICE;
531 identify_frame.frame_type = 0;
532 identify_frame._un1 = 1;
533 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
534 identify_frame.target_bits = SAS_PROTOCOL_NONE;
535 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
536 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
537 identify_frame.phy_id = phy_no;
538 identify_buffer = (u32 *)(&identify_frame);
539
540 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
541 __swab32(identify_buffer[0]));
542 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
543 __swab32(identify_buffer[1]));
544 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
545 __swab32(identify_buffer[2]));
546 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
547 __swab32(identify_buffer[3]));
548 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
549 __swab32(identify_buffer[4]));
550 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
551 __swab32(identify_buffer[5]));
552 }
553
554 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
555 struct hisi_sas_device *sas_dev)
556 {
557 struct domain_device *device = sas_dev->sas_device;
558 struct device *dev = hisi_hba->dev;
559 u64 qw0, device_id = sas_dev->device_id;
560 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
561 struct domain_device *parent_dev = device->parent;
562 struct asd_sas_port *sas_port = device->port;
563 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
564
565 memset(itct, 0, sizeof(*itct));
566
567 /* qw0 */
568 qw0 = 0;
569 switch (sas_dev->dev_type) {
570 case SAS_END_DEVICE:
571 case SAS_EDGE_EXPANDER_DEVICE:
572 case SAS_FANOUT_EXPANDER_DEVICE:
573 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
574 break;
575 case SAS_SATA_DEV:
576 case SAS_SATA_PENDING:
577 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
578 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
579 else
580 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
581 break;
582 default:
583 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
584 sas_dev->dev_type);
585 }
586
587 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
588 (device->linkrate << ITCT_HDR_MCR_OFF) |
589 (1 << ITCT_HDR_VLN_OFF) |
590 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
591 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
592 (port->id << ITCT_HDR_PORT_ID_OFF));
593 itct->qw0 = cpu_to_le64(qw0);
594
595 /* qw1 */
596 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
597 itct->sas_addr = __swab64(itct->sas_addr);
598
599 /* qw2 */
600 if (!dev_is_sata(device))
601 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
602 (0x1ULL << ITCT_HDR_RTOLT_OFF));
603 }
604
605 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba,
606 struct hisi_sas_device *sas_dev)
607 {
608 DECLARE_COMPLETION_ONSTACK(completion);
609 u64 dev_id = sas_dev->device_id;
610 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
611 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
612
613 sas_dev->completion = &completion;
614
615 /* clear the itct interrupt state */
616 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
617 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
618 ENT_INT_SRC3_ITC_INT_MSK);
619
620 /* clear the itct table*/
621 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
622 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
623
624 wait_for_completion(sas_dev->completion);
625 memset(itct, 0, sizeof(struct hisi_sas_itct));
626 }
627
628 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
629 struct domain_device *device)
630 {
631 struct hisi_sas_slot *slot, *slot2;
632 struct hisi_sas_device *sas_dev = device->lldd_dev;
633 u32 cfg_abt_set_query_iptt;
634
635 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
636 CFG_ABT_SET_QUERY_IPTT);
637 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
638 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
639 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
640 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
641 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
642 cfg_abt_set_query_iptt);
643 }
644 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
645 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
646 cfg_abt_set_query_iptt);
647 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
648 1 << CFG_ABT_SET_IPTT_DONE_OFF);
649 }
650
651 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
652 {
653 struct device *dev = hisi_hba->dev;
654 int ret;
655 u32 val;
656
657 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
658
659 /* Disable all of the PHYs */
660 hisi_sas_stop_phys(hisi_hba);
661 udelay(50);
662
663 /* Ensure axi bus idle */
664 ret = readl_poll_timeout(hisi_hba->regs + AXI_CFG, val, !val,
665 20000, 1000000);
666 if (ret) {
667 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
668 return -EIO;
669 }
670
671 if (ACPI_HANDLE(dev)) {
672 acpi_status s;
673
674 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
675 if (ACPI_FAILURE(s)) {
676 dev_err(dev, "Reset failed\n");
677 return -EIO;
678 }
679 } else
680 dev_err(dev, "no reset method!\n");
681
682 return 0;
683 }
684
685 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
686 {
687 struct device *dev = hisi_hba->dev;
688 int rc;
689
690 rc = reset_hw_v3_hw(hisi_hba);
691 if (rc) {
692 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
693 return rc;
694 }
695
696 msleep(100);
697 init_reg_v3_hw(hisi_hba);
698
699 return 0;
700 }
701
702 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
703 {
704 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
705
706 cfg |= PHY_CFG_ENA_MSK;
707 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
708 }
709
710 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
711 {
712 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
713
714 cfg &= ~PHY_CFG_ENA_MSK;
715 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
716 }
717
718 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
719 {
720 config_id_frame_v3_hw(hisi_hba, phy_no);
721 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
722 enable_phy_v3_hw(hisi_hba, phy_no);
723 }
724
725 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
726 {
727 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
728 u32 txid_auto;
729
730 disable_phy_v3_hw(hisi_hba, phy_no);
731 if (phy->identify.device_type == SAS_END_DEVICE) {
732 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
733 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
734 txid_auto | TX_HARDRST_MSK);
735 }
736 msleep(100);
737 start_phy_v3_hw(hisi_hba, phy_no);
738 }
739
740 enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
741 {
742 return SAS_LINK_RATE_12_0_GBPS;
743 }
744
745 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
746 {
747 int i;
748
749 for (i = 0; i < hisi_hba->n_phy; i++) {
750 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
751 struct asd_sas_phy *sas_phy = &phy->sas_phy;
752
753 if (!sas_phy->phy->enabled)
754 continue;
755
756 start_phy_v3_hw(hisi_hba, i);
757 }
758 }
759
760 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
761 {
762 u32 sl_control;
763
764 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
765 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
766 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
767 msleep(1);
768 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
769 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
770 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
771 }
772
773 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
774 {
775 int i, bitmap = 0;
776 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
777 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
778
779 for (i = 0; i < hisi_hba->n_phy; i++)
780 if (phy_state & BIT(i))
781 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
782 bitmap |= BIT(i);
783
784 return bitmap;
785 }
786
787 /**
788 * The callpath to this function and upto writing the write
789 * queue pointer should be safe from interruption.
790 */
791 static int
792 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
793 {
794 struct device *dev = hisi_hba->dev;
795 int queue = dq->id;
796 u32 r, w;
797
798 w = dq->wr_point;
799 r = hisi_sas_read32_relaxed(hisi_hba,
800 DLVRY_Q_0_RD_PTR + (queue * 0x14));
801 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
802 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
803 queue, r, w);
804 return -EAGAIN;
805 }
806
807 return 0;
808 }
809
810 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
811 {
812 struct hisi_hba *hisi_hba = dq->hisi_hba;
813 int dlvry_queue = dq->slot_prep->dlvry_queue;
814 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
815
816 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
817 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
818 dq->wr_point);
819 }
820
821 static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
822 struct hisi_sas_slot *slot,
823 struct hisi_sas_cmd_hdr *hdr,
824 struct scatterlist *scatter,
825 int n_elem)
826 {
827 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
828 struct device *dev = hisi_hba->dev;
829 struct scatterlist *sg;
830 int i;
831
832 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
833 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
834 n_elem);
835 return -EINVAL;
836 }
837
838 for_each_sg(scatter, sg, n_elem, i) {
839 struct hisi_sas_sge *entry = &sge_page->sge[i];
840
841 entry->addr = cpu_to_le64(sg_dma_address(sg));
842 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
843 entry->data_len = cpu_to_le32(sg_dma_len(sg));
844 entry->data_off = 0;
845 }
846
847 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
848
849 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
850
851 return 0;
852 }
853
854 static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
855 struct hisi_sas_slot *slot, int is_tmf,
856 struct hisi_sas_tmf_task *tmf)
857 {
858 struct sas_task *task = slot->task;
859 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
860 struct domain_device *device = task->dev;
861 struct hisi_sas_device *sas_dev = device->lldd_dev;
862 struct hisi_sas_port *port = slot->port;
863 struct sas_ssp_task *ssp_task = &task->ssp_task;
864 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
865 int has_data = 0, rc, priority = is_tmf;
866 u8 *buf_cmd;
867 u32 dw1 = 0, dw2 = 0;
868
869 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
870 (2 << CMD_HDR_TLR_CTRL_OFF) |
871 (port->id << CMD_HDR_PORT_OFF) |
872 (priority << CMD_HDR_PRIORITY_OFF) |
873 (1 << CMD_HDR_CMD_OFF)); /* ssp */
874
875 dw1 = 1 << CMD_HDR_VDTL_OFF;
876 if (is_tmf) {
877 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
878 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
879 } else {
880 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
881 switch (scsi_cmnd->sc_data_direction) {
882 case DMA_TO_DEVICE:
883 has_data = 1;
884 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
885 break;
886 case DMA_FROM_DEVICE:
887 has_data = 1;
888 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
889 break;
890 default:
891 dw1 &= ~CMD_HDR_DIR_MSK;
892 }
893 }
894
895 /* map itct entry */
896 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
897 hdr->dw1 = cpu_to_le32(dw1);
898
899 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
900 + 3) / 4) << CMD_HDR_CFL_OFF) |
901 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
902 (2 << CMD_HDR_SG_MOD_OFF);
903 hdr->dw2 = cpu_to_le32(dw2);
904 hdr->transfer_tags = cpu_to_le32(slot->idx);
905
906 if (has_data) {
907 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
908 slot->n_elem);
909 if (rc)
910 return rc;
911 }
912
913 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
914 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
915 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
916
917 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
918 sizeof(struct ssp_frame_hdr);
919
920 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
921 if (!is_tmf) {
922 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
923 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
924 } else {
925 buf_cmd[10] = tmf->tmf;
926 switch (tmf->tmf) {
927 case TMF_ABORT_TASK:
928 case TMF_QUERY_TASK:
929 buf_cmd[12] =
930 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
931 buf_cmd[13] =
932 tmf->tag_of_task_to_be_managed & 0xff;
933 break;
934 default:
935 break;
936 }
937 }
938
939 return 0;
940 }
941
942 static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
943 struct hisi_sas_slot *slot)
944 {
945 struct sas_task *task = slot->task;
946 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
947 struct domain_device *device = task->dev;
948 struct device *dev = hisi_hba->dev;
949 struct hisi_sas_port *port = slot->port;
950 struct scatterlist *sg_req, *sg_resp;
951 struct hisi_sas_device *sas_dev = device->lldd_dev;
952 dma_addr_t req_dma_addr;
953 unsigned int req_len, resp_len;
954 int elem, rc;
955
956 /*
957 * DMA-map SMP request, response buffers
958 */
959 /* req */
960 sg_req = &task->smp_task.smp_req;
961 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
962 if (!elem)
963 return -ENOMEM;
964 req_len = sg_dma_len(sg_req);
965 req_dma_addr = sg_dma_address(sg_req);
966
967 /* resp */
968 sg_resp = &task->smp_task.smp_resp;
969 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
970 if (!elem) {
971 rc = -ENOMEM;
972 goto err_out_req;
973 }
974 resp_len = sg_dma_len(sg_resp);
975 if ((req_len & 0x3) || (resp_len & 0x3)) {
976 rc = -EINVAL;
977 goto err_out_resp;
978 }
979
980 /* create header */
981 /* dw0 */
982 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
983 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
984 (2 << CMD_HDR_CMD_OFF)); /* smp */
985
986 /* map itct entry */
987 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
988 (1 << CMD_HDR_FRAME_TYPE_OFF) |
989 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
990
991 /* dw2 */
992 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
993 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
994 CMD_HDR_MRFL_OFF));
995
996 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
997
998 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
999 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1000
1001 return 0;
1002
1003 err_out_resp:
1004 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1005 DMA_FROM_DEVICE);
1006 err_out_req:
1007 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1008 DMA_TO_DEVICE);
1009 return rc;
1010 }
1011
1012 static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1013 struct hisi_sas_slot *slot)
1014 {
1015 struct sas_task *task = slot->task;
1016 struct domain_device *device = task->dev;
1017 struct domain_device *parent_dev = device->parent;
1018 struct hisi_sas_device *sas_dev = device->lldd_dev;
1019 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1020 struct asd_sas_port *sas_port = device->port;
1021 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1022 u8 *buf_cmd;
1023 int has_data = 0, rc = 0, hdr_tag = 0;
1024 u32 dw1 = 0, dw2 = 0;
1025
1026 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1027 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1028 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1029 else
1030 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1031
1032 switch (task->data_dir) {
1033 case DMA_TO_DEVICE:
1034 has_data = 1;
1035 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1036 break;
1037 case DMA_FROM_DEVICE:
1038 has_data = 1;
1039 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1040 break;
1041 default:
1042 dw1 &= ~CMD_HDR_DIR_MSK;
1043 }
1044
1045 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1046 (task->ata_task.fis.control & ATA_SRST))
1047 dw1 |= 1 << CMD_HDR_RESET_OFF;
1048
1049 dw1 |= (hisi_sas_get_ata_protocol(
1050 task->ata_task.fis.command, task->data_dir))
1051 << CMD_HDR_FRAME_TYPE_OFF;
1052 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1053
1054 if (CMD_IS_UNCONSTRAINT(task->ata_task.fis.command))
1055 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1056
1057 hdr->dw1 = cpu_to_le32(dw1);
1058
1059 /* dw2 */
1060 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
1061 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1062 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1063 }
1064
1065 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1066 2 << CMD_HDR_SG_MOD_OFF;
1067 hdr->dw2 = cpu_to_le32(dw2);
1068
1069 /* dw3 */
1070 hdr->transfer_tags = cpu_to_le32(slot->idx);
1071
1072 if (has_data) {
1073 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1074 slot->n_elem);
1075 if (rc)
1076 return rc;
1077 }
1078
1079 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1080 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1081 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1082
1083 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1084
1085 if (likely(!task->ata_task.device_control_reg_update))
1086 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1087 /* fill in command FIS */
1088 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1089
1090 return 0;
1091 }
1092
1093 static int prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1094 struct hisi_sas_slot *slot,
1095 int device_id, int abort_flag, int tag_to_abort)
1096 {
1097 struct sas_task *task = slot->task;
1098 struct domain_device *dev = task->dev;
1099 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1100 struct hisi_sas_port *port = slot->port;
1101
1102 /* dw0 */
1103 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1104 (port->id << CMD_HDR_PORT_OFF) |
1105 ((dev_is_sata(dev) ? 1:0)
1106 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1107 (abort_flag
1108 << CMD_HDR_ABORT_FLAG_OFF));
1109
1110 /* dw1 */
1111 hdr->dw1 = cpu_to_le32(device_id
1112 << CMD_HDR_DEV_ID_OFF);
1113
1114 /* dw7 */
1115 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1116 hdr->transfer_tags = cpu_to_le32(slot->idx);
1117
1118 return 0;
1119 }
1120
1121 static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1122 {
1123 int i, res = 0;
1124 u32 context, port_id, link_rate, hard_phy_linkrate;
1125 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1126 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1127 struct device *dev = hisi_hba->dev;
1128
1129 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1130
1131 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1132 port_id = (port_id >> (4 * phy_no)) & 0xf;
1133 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1134 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1135
1136 if (port_id == 0xf) {
1137 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1138 res = IRQ_NONE;
1139 goto end;
1140 }
1141 sas_phy->linkrate = link_rate;
1142 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1143 HARD_PHY_LINKRATE);
1144 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1145 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1146 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1147
1148 /* Check for SATA dev */
1149 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1150 if (context & (1 << phy_no)) {
1151 struct hisi_sas_initial_fis *initial_fis;
1152 struct dev_to_host_fis *fis;
1153 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1154
1155 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1156 initial_fis = &hisi_hba->initial_fis[phy_no];
1157 fis = &initial_fis->fis;
1158 sas_phy->oob_mode = SATA_OOB_MODE;
1159 attached_sas_addr[0] = 0x50;
1160 attached_sas_addr[7] = phy_no;
1161 memcpy(sas_phy->attached_sas_addr,
1162 attached_sas_addr,
1163 SAS_ADDR_SIZE);
1164 memcpy(sas_phy->frame_rcvd, fis,
1165 sizeof(struct dev_to_host_fis));
1166 phy->phy_type |= PORT_TYPE_SATA;
1167 phy->identify.device_type = SAS_SATA_DEV;
1168 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1169 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1170 } else {
1171 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1172 struct sas_identify_frame *id =
1173 (struct sas_identify_frame *)frame_rcvd;
1174
1175 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1176 for (i = 0; i < 6; i++) {
1177 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1178 RX_IDAF_DWORD0 + (i * 4));
1179 frame_rcvd[i] = __swab32(idaf);
1180 }
1181 sas_phy->oob_mode = SAS_OOB_MODE;
1182 memcpy(sas_phy->attached_sas_addr,
1183 &id->sas_addr,
1184 SAS_ADDR_SIZE);
1185 phy->phy_type |= PORT_TYPE_SAS;
1186 phy->identify.device_type = id->dev_type;
1187 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1188 if (phy->identify.device_type == SAS_END_DEVICE)
1189 phy->identify.target_port_protocols =
1190 SAS_PROTOCOL_SSP;
1191 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1192 phy->identify.target_port_protocols =
1193 SAS_PROTOCOL_SMP;
1194 }
1195
1196 phy->port_id = port_id;
1197 phy->phy_attached = 1;
1198 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1199
1200 end:
1201 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1202 CHL_INT0_SL_PHY_ENABLE_MSK);
1203 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1204
1205 return res;
1206 }
1207
1208 static int phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1209 {
1210 u32 phy_state, sl_ctrl, txid_auto;
1211 struct device *dev = hisi_hba->dev;
1212
1213 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1214
1215 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1216 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1217 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1218
1219 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1220 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1221 sl_ctrl&(~SL_CTA_MSK));
1222
1223 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1224 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1225 txid_auto | CT3_MSK);
1226
1227 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1228 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1229
1230 return 0;
1231 }
1232
1233 static void phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1234 {
1235 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1236 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1237 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1238
1239 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1240 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1241 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1242 CHL_INT0_SL_RX_BCST_ACK_MSK);
1243 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1244 }
1245
1246 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1247 {
1248 struct hisi_hba *hisi_hba = p;
1249 u32 irq_msk;
1250 int phy_no = 0;
1251 irqreturn_t res = IRQ_NONE;
1252
1253 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1254 & 0x11111111;
1255 while (irq_msk) {
1256 if (irq_msk & 1) {
1257 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1258 CHL_INT0);
1259 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1260 int rdy = phy_state & (1 << phy_no);
1261
1262 if (rdy) {
1263 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1264 /* phy up */
1265 if (phy_up_v3_hw(phy_no, hisi_hba)
1266 == IRQ_HANDLED)
1267 res = IRQ_HANDLED;
1268 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1269 /* phy bcast */
1270 phy_bcast_v3_hw(phy_no, hisi_hba);
1271 } else {
1272 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1273 /* phy down */
1274 if (phy_down_v3_hw(phy_no, hisi_hba)
1275 == IRQ_HANDLED)
1276 res = IRQ_HANDLED;
1277 }
1278 }
1279 irq_msk >>= 4;
1280 phy_no++;
1281 }
1282
1283 return res;
1284 }
1285
1286 static const struct hisi_sas_hw_error port_axi_error[] = {
1287 {
1288 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1289 .msg = "dma_tx_axi_wr_err",
1290 },
1291 {
1292 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1293 .msg = "dma_tx_axi_rd_err",
1294 },
1295 {
1296 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1297 .msg = "dma_rx_axi_wr_err",
1298 },
1299 {
1300 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1301 .msg = "dma_rx_axi_rd_err",
1302 },
1303 };
1304
1305 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1306 {
1307 struct hisi_hba *hisi_hba = p;
1308 struct device *dev = hisi_hba->dev;
1309 u32 ent_msk, ent_tmp, irq_msk;
1310 int phy_no = 0;
1311
1312 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1313 ent_tmp = ent_msk;
1314 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1315 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1316
1317 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1318 & 0xeeeeeeee;
1319
1320 while (irq_msk) {
1321 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1322 CHL_INT0);
1323 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1324 CHL_INT1);
1325 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1326 CHL_INT2);
1327
1328 if ((irq_msk & (4 << (phy_no * 4))) &&
1329 irq_value1) {
1330 int i;
1331
1332 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1333 const struct hisi_sas_hw_error *error =
1334 &port_axi_error[i];
1335
1336 if (!(irq_value1 & error->irq_msk))
1337 continue;
1338
1339 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1340 error->msg, phy_no, irq_value1);
1341 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1342 }
1343
1344 hisi_sas_phy_write32(hisi_hba, phy_no,
1345 CHL_INT1, irq_value1);
1346 }
1347
1348 if (irq_msk & (8 << (phy_no * 4)) && irq_value2) {
1349 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1350
1351 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1352 dev_warn(dev, "phy%d identify timeout\n",
1353 phy_no);
1354 hisi_sas_notify_phy_event(phy,
1355 HISI_PHYE_LINK_RESET);
1356
1357 }
1358
1359 if (irq_value2 & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1360 u32 reg_value = hisi_sas_phy_read32(hisi_hba,
1361 phy_no, STP_LINK_TIMEOUT_STATE);
1362
1363 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1364 phy_no, reg_value);
1365 if (reg_value & BIT(4))
1366 hisi_sas_notify_phy_event(phy,
1367 HISI_PHYE_LINK_RESET);
1368 }
1369
1370 hisi_sas_phy_write32(hisi_hba, phy_no,
1371 CHL_INT2, irq_value2);
1372 }
1373
1374
1375 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1376 hisi_sas_phy_write32(hisi_hba, phy_no,
1377 CHL_INT0, irq_value0
1378 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1379 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1380 & (~CHL_INT0_NOT_RDY_MSK));
1381 }
1382 irq_msk &= ~(0xe << (phy_no * 4));
1383 phy_no++;
1384 }
1385
1386 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1387
1388 return IRQ_HANDLED;
1389 }
1390
1391 static const struct hisi_sas_hw_error axi_error[] = {
1392 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1393 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1394 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1395 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1396 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1397 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1398 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1399 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1400 {},
1401 };
1402
1403 static const struct hisi_sas_hw_error fifo_error[] = {
1404 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
1405 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
1406 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1407 { .msk = BIT(11), .msg = "CMDP_FIFO" },
1408 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1409 {},
1410 };
1411
1412 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1413 {
1414 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1415 .msg = "write pointer and depth",
1416 },
1417 {
1418 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
1419 .msg = "iptt no match slot",
1420 },
1421 {
1422 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
1423 .msg = "read pointer and depth",
1424 },
1425 {
1426 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
1427 .reg = HGC_AXI_FIFO_ERR_INFO,
1428 .sub = axi_error,
1429 },
1430 {
1431 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
1432 .reg = HGC_AXI_FIFO_ERR_INFO,
1433 .sub = fifo_error,
1434 },
1435 {
1436 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
1437 .msg = "LM add/fetch list",
1438 },
1439 {
1440 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
1441 .msg = "SAS_HGC_ABT fetch LM list",
1442 },
1443 };
1444
1445 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
1446 {
1447 u32 irq_value, irq_msk;
1448 struct hisi_hba *hisi_hba = p;
1449 struct device *dev = hisi_hba->dev;
1450 int i;
1451
1452 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1453 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
1454
1455 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
1456
1457 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
1458 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
1459
1460 if (!(irq_value & error->irq_msk))
1461 continue;
1462
1463 if (error->sub) {
1464 const struct hisi_sas_hw_error *sub = error->sub;
1465 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
1466
1467 for (; sub->msk || sub->msg; sub++) {
1468 if (!(err_value & sub->msk))
1469 continue;
1470
1471 dev_err(dev, "%s error (0x%x) found!\n",
1472 sub->msg, irq_value);
1473 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1474 }
1475 } else {
1476 dev_err(dev, "%s error (0x%x) found!\n",
1477 error->msg, irq_value);
1478 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1479 }
1480 }
1481
1482 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
1483 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
1484 u32 dev_id = reg_val & ITCT_DEV_MSK;
1485 struct hisi_sas_device *sas_dev =
1486 &hisi_hba->devices[dev_id];
1487
1488 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
1489 dev_dbg(dev, "clear ITCT ok\n");
1490 complete(sas_dev->completion);
1491 }
1492
1493 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
1494 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
1495
1496 return IRQ_HANDLED;
1497 }
1498
1499 static void
1500 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1501 struct hisi_sas_slot *slot)
1502 {
1503 struct task_status_struct *ts = &task->task_status;
1504 struct hisi_sas_complete_v3_hdr *complete_queue =
1505 hisi_hba->complete_hdr[slot->cmplt_queue];
1506 struct hisi_sas_complete_v3_hdr *complete_hdr =
1507 &complete_queue[slot->cmplt_queue_slot];
1508 struct hisi_sas_err_record_v3 *record =
1509 hisi_sas_status_buf_addr_mem(slot);
1510 u32 dma_rx_err_type = record->dma_rx_err_type;
1511 u32 trans_tx_fail_type = record->trans_tx_fail_type;
1512
1513 switch (task->task_proto) {
1514 case SAS_PROTOCOL_SSP:
1515 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1516 ts->residual = trans_tx_fail_type;
1517 ts->stat = SAS_DATA_UNDERRUN;
1518 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1519 ts->stat = SAS_QUEUE_FULL;
1520 slot->abort = 1;
1521 } else {
1522 ts->stat = SAS_OPEN_REJECT;
1523 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1524 }
1525 break;
1526 case SAS_PROTOCOL_SATA:
1527 case SAS_PROTOCOL_STP:
1528 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1529 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1530 ts->residual = trans_tx_fail_type;
1531 ts->stat = SAS_DATA_UNDERRUN;
1532 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1533 ts->stat = SAS_PHY_DOWN;
1534 slot->abort = 1;
1535 } else {
1536 ts->stat = SAS_OPEN_REJECT;
1537 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1538 }
1539 hisi_sas_sata_done(task, slot);
1540 break;
1541 case SAS_PROTOCOL_SMP:
1542 ts->stat = SAM_STAT_CHECK_CONDITION;
1543 break;
1544 default:
1545 break;
1546 }
1547 }
1548
1549 static int
1550 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1551 {
1552 struct sas_task *task = slot->task;
1553 struct hisi_sas_device *sas_dev;
1554 struct device *dev = hisi_hba->dev;
1555 struct task_status_struct *ts;
1556 struct domain_device *device;
1557 enum exec_status sts;
1558 struct hisi_sas_complete_v3_hdr *complete_queue =
1559 hisi_hba->complete_hdr[slot->cmplt_queue];
1560 struct hisi_sas_complete_v3_hdr *complete_hdr =
1561 &complete_queue[slot->cmplt_queue_slot];
1562 int aborted;
1563 unsigned long flags;
1564
1565 if (unlikely(!task || !task->lldd_task || !task->dev))
1566 return -EINVAL;
1567
1568 ts = &task->task_status;
1569 device = task->dev;
1570 sas_dev = device->lldd_dev;
1571
1572 spin_lock_irqsave(&task->task_state_lock, flags);
1573 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1574 task->task_state_flags &=
1575 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1576 spin_unlock_irqrestore(&task->task_state_lock, flags);
1577
1578 memset(ts, 0, sizeof(*ts));
1579 ts->resp = SAS_TASK_COMPLETE;
1580 if (unlikely(aborted)) {
1581 dev_dbg(dev, "slot complete: task(%p) aborted\n", task);
1582 ts->stat = SAS_ABORTED_TASK;
1583 spin_lock_irqsave(&hisi_hba->lock, flags);
1584 hisi_sas_slot_task_free(hisi_hba, task, slot);
1585 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1586 return -1;
1587 }
1588
1589 if (unlikely(!sas_dev)) {
1590 dev_dbg(dev, "slot complete: port has not device\n");
1591 ts->stat = SAS_PHY_DOWN;
1592 goto out;
1593 }
1594
1595 /*
1596 * Use SAS+TMF status codes
1597 */
1598 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1599 >> CMPLT_HDR_ABORT_STAT_OFF) {
1600 case STAT_IO_ABORTED:
1601 /* this IO has been aborted by abort command */
1602 ts->stat = SAS_ABORTED_TASK;
1603 goto out;
1604 case STAT_IO_COMPLETE:
1605 /* internal abort command complete */
1606 ts->stat = TMF_RESP_FUNC_SUCC;
1607 goto out;
1608 case STAT_IO_NO_DEVICE:
1609 ts->stat = TMF_RESP_FUNC_COMPLETE;
1610 goto out;
1611 case STAT_IO_NOT_VALID:
1612 /*
1613 * abort single IO, the controller can't find the IO
1614 */
1615 ts->stat = TMF_RESP_FUNC_FAILED;
1616 goto out;
1617 default:
1618 break;
1619 }
1620
1621 /* check for erroneous completion */
1622 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1623 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
1624
1625 slot_err_v3_hw(hisi_hba, task, slot);
1626 if (ts->stat != SAS_DATA_UNDERRUN)
1627 dev_info(dev, "erroneous completion iptt=%d task=%p "
1628 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
1629 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
1630 slot->idx, task,
1631 complete_hdr->dw0, complete_hdr->dw1,
1632 complete_hdr->act, complete_hdr->dw3,
1633 error_info[0], error_info[1],
1634 error_info[2], error_info[3]);
1635 if (unlikely(slot->abort))
1636 return ts->stat;
1637 goto out;
1638 }
1639
1640 switch (task->task_proto) {
1641 case SAS_PROTOCOL_SSP: {
1642 struct ssp_response_iu *iu =
1643 hisi_sas_status_buf_addr_mem(slot) +
1644 sizeof(struct hisi_sas_err_record);
1645
1646 sas_ssp_task_response(dev, task, iu);
1647 break;
1648 }
1649 case SAS_PROTOCOL_SMP: {
1650 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1651 void *to;
1652
1653 ts->stat = SAM_STAT_GOOD;
1654 to = kmap_atomic(sg_page(sg_resp));
1655
1656 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1657 DMA_FROM_DEVICE);
1658 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1659 DMA_TO_DEVICE);
1660 memcpy(to + sg_resp->offset,
1661 hisi_sas_status_buf_addr_mem(slot) +
1662 sizeof(struct hisi_sas_err_record),
1663 sg_dma_len(sg_resp));
1664 kunmap_atomic(to);
1665 break;
1666 }
1667 case SAS_PROTOCOL_SATA:
1668 case SAS_PROTOCOL_STP:
1669 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1670 ts->stat = SAM_STAT_GOOD;
1671 hisi_sas_sata_done(task, slot);
1672 break;
1673 default:
1674 ts->stat = SAM_STAT_CHECK_CONDITION;
1675 break;
1676 }
1677
1678 if (!slot->port->port_attached) {
1679 dev_warn(dev, "slot complete: port %d has removed\n",
1680 slot->port->sas_port.id);
1681 ts->stat = SAS_PHY_DOWN;
1682 }
1683
1684 out:
1685 spin_lock_irqsave(&task->task_state_lock, flags);
1686 task->task_state_flags |= SAS_TASK_STATE_DONE;
1687 spin_unlock_irqrestore(&task->task_state_lock, flags);
1688 spin_lock_irqsave(&hisi_hba->lock, flags);
1689 hisi_sas_slot_task_free(hisi_hba, task, slot);
1690 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1691 sts = ts->stat;
1692
1693 if (task->task_done)
1694 task->task_done(task);
1695
1696 return sts;
1697 }
1698
1699 static void cq_tasklet_v3_hw(unsigned long val)
1700 {
1701 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1702 struct hisi_hba *hisi_hba = cq->hisi_hba;
1703 struct hisi_sas_slot *slot;
1704 struct hisi_sas_complete_v3_hdr *complete_queue;
1705 u32 rd_point = cq->rd_point, wr_point;
1706 int queue = cq->id;
1707 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
1708
1709 complete_queue = hisi_hba->complete_hdr[queue];
1710
1711 spin_lock(&dq->lock);
1712 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1713 (0x14 * queue));
1714
1715 while (rd_point != wr_point) {
1716 struct hisi_sas_complete_v3_hdr *complete_hdr;
1717 int iptt;
1718
1719 complete_hdr = &complete_queue[rd_point];
1720
1721 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1722 slot = &hisi_hba->slot_info[iptt];
1723 slot->cmplt_queue_slot = rd_point;
1724 slot->cmplt_queue = queue;
1725 slot_complete_v3_hw(hisi_hba, slot);
1726
1727 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1728 rd_point = 0;
1729 }
1730
1731 /* update rd_point */
1732 cq->rd_point = rd_point;
1733 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1734 spin_unlock(&dq->lock);
1735 }
1736
1737 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1738 {
1739 struct hisi_sas_cq *cq = p;
1740 struct hisi_hba *hisi_hba = cq->hisi_hba;
1741 int queue = cq->id;
1742
1743 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1744
1745 tasklet_schedule(&cq->tasklet);
1746
1747 return IRQ_HANDLED;
1748 }
1749
1750 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1751 {
1752 struct device *dev = hisi_hba->dev;
1753 struct pci_dev *pdev = hisi_hba->pci_dev;
1754 int vectors, rc;
1755 int i, k;
1756 int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1757
1758 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1759 max_msi, PCI_IRQ_MSI);
1760 if (vectors < max_msi) {
1761 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1762 return -ENOENT;
1763 }
1764
1765 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1766 int_phy_up_down_bcast_v3_hw, 0,
1767 DRV_NAME " phy", hisi_hba);
1768 if (rc) {
1769 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1770 rc = -ENOENT;
1771 goto free_irq_vectors;
1772 }
1773
1774 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1775 int_chnl_int_v3_hw, 0,
1776 DRV_NAME " channel", hisi_hba);
1777 if (rc) {
1778 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1779 rc = -ENOENT;
1780 goto free_phy_irq;
1781 }
1782
1783 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
1784 fatal_axi_int_v3_hw, 0,
1785 DRV_NAME " fatal", hisi_hba);
1786 if (rc) {
1787 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
1788 rc = -ENOENT;
1789 goto free_chnl_interrupt;
1790 }
1791
1792 /* Init tasklets for cq only */
1793 for (i = 0; i < hisi_hba->queue_count; i++) {
1794 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1795 struct tasklet_struct *t = &cq->tasklet;
1796
1797 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1798 cq_interrupt_v3_hw, 0,
1799 DRV_NAME " cq", cq);
1800 if (rc) {
1801 dev_err(dev,
1802 "could not request cq%d interrupt, rc=%d\n",
1803 i, rc);
1804 rc = -ENOENT;
1805 goto free_cq_irqs;
1806 }
1807
1808 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1809 }
1810
1811 return 0;
1812
1813 free_cq_irqs:
1814 for (k = 0; k < i; k++) {
1815 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1816
1817 free_irq(pci_irq_vector(pdev, k+16), cq);
1818 }
1819 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
1820 free_chnl_interrupt:
1821 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1822 free_phy_irq:
1823 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1824 free_irq_vectors:
1825 pci_free_irq_vectors(pdev);
1826 return rc;
1827 }
1828
1829 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1830 {
1831 int rc;
1832
1833 rc = hw_init_v3_hw(hisi_hba);
1834 if (rc)
1835 return rc;
1836
1837 rc = interrupt_init_v3_hw(hisi_hba);
1838 if (rc)
1839 return rc;
1840
1841 return 0;
1842 }
1843
1844 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
1845 struct sas_phy_linkrates *r)
1846 {
1847 u32 prog_phy_link_rate =
1848 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1849 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1850 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1851 int i;
1852 enum sas_linkrate min, max;
1853 u32 rate_mask = 0;
1854
1855 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1856 max = sas_phy->phy->maximum_linkrate;
1857 min = r->minimum_linkrate;
1858 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1859 max = r->maximum_linkrate;
1860 min = sas_phy->phy->minimum_linkrate;
1861 } else
1862 return;
1863
1864 sas_phy->phy->maximum_linkrate = max;
1865 sas_phy->phy->minimum_linkrate = min;
1866
1867 min -= SAS_LINK_RATE_1_5_GBPS;
1868 max -= SAS_LINK_RATE_1_5_GBPS;
1869
1870 for (i = 0; i <= max; i++)
1871 rate_mask |= 1 << (i * 2);
1872
1873 prog_phy_link_rate &= ~0xff;
1874 prog_phy_link_rate |= rate_mask;
1875
1876 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1877 prog_phy_link_rate);
1878
1879 phy_hard_reset_v3_hw(hisi_hba, phy_no);
1880 }
1881
1882 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
1883 {
1884 struct pci_dev *pdev = hisi_hba->pci_dev;
1885 int i;
1886
1887 synchronize_irq(pci_irq_vector(pdev, 1));
1888 synchronize_irq(pci_irq_vector(pdev, 2));
1889 synchronize_irq(pci_irq_vector(pdev, 11));
1890 for (i = 0; i < hisi_hba->queue_count; i++) {
1891 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
1892 synchronize_irq(pci_irq_vector(pdev, i + 16));
1893 }
1894
1895 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
1896 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
1897 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
1898 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1899
1900 for (i = 0; i < hisi_hba->n_phy; i++) {
1901 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1902 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
1903 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
1904 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
1905 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
1906 }
1907 }
1908
1909 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
1910 {
1911 return hisi_sas_read32(hisi_hba, PHY_STATE);
1912 }
1913
1914 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1915 {
1916 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1917 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1918 struct sas_phy *sphy = sas_phy->phy;
1919 u32 reg_value;
1920
1921 /* loss dword sync */
1922 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1923 sphy->loss_of_dword_sync_count += reg_value;
1924
1925 /* phy reset problem */
1926 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1927 sphy->phy_reset_problem_count += reg_value;
1928
1929 /* invalid dword */
1930 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1931 sphy->invalid_dword_count += reg_value;
1932
1933 /* disparity err */
1934 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1935 sphy->running_disparity_error_count += reg_value;
1936
1937 }
1938
1939 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
1940 {
1941 struct device *dev = hisi_hba->dev;
1942 int rc;
1943 u32 status;
1944
1945 interrupt_disable_v3_hw(hisi_hba);
1946 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
1947 hisi_sas_kill_tasklets(hisi_hba);
1948
1949 hisi_sas_stop_phys(hisi_hba);
1950
1951 mdelay(10);
1952
1953 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
1954
1955 /* wait until bus idle */
1956 rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
1957 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
1958 if (rc) {
1959 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
1960 return rc;
1961 }
1962
1963 hisi_sas_init_mem(hisi_hba);
1964
1965 return hw_init_v3_hw(hisi_hba);
1966 }
1967
1968 static const struct hisi_sas_hw hisi_sas_v3_hw = {
1969 .hw_init = hisi_sas_v3_init,
1970 .setup_itct = setup_itct_v3_hw,
1971 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
1972 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
1973 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
1974 .clear_itct = clear_itct_v3_hw,
1975 .sl_notify = sl_notify_v3_hw,
1976 .prep_ssp = prep_ssp_v3_hw,
1977 .prep_smp = prep_smp_v3_hw,
1978 .prep_stp = prep_ata_v3_hw,
1979 .prep_abort = prep_abort_v3_hw,
1980 .get_free_slot = get_free_slot_v3_hw,
1981 .start_delivery = start_delivery_v3_hw,
1982 .slot_complete = slot_complete_v3_hw,
1983 .phys_init = phys_init_v3_hw,
1984 .phy_start = start_phy_v3_hw,
1985 .phy_disable = disable_phy_v3_hw,
1986 .phy_hard_reset = phy_hard_reset_v3_hw,
1987 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
1988 .phy_set_linkrate = phy_set_linkrate_v3_hw,
1989 .dereg_device = dereg_device_v3_hw,
1990 .soft_reset = soft_reset_v3_hw,
1991 .get_phys_state = get_phys_state_v3_hw,
1992 .get_events = phy_get_events_v3_hw,
1993 };
1994
1995 static struct Scsi_Host *
1996 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
1997 {
1998 struct Scsi_Host *shost;
1999 struct hisi_hba *hisi_hba;
2000 struct device *dev = &pdev->dev;
2001
2002 shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
2003 if (!shost) {
2004 dev_err(dev, "shost alloc failed\n");
2005 return NULL;
2006 }
2007 hisi_hba = shost_priv(shost);
2008
2009 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
2010 hisi_hba->hw = &hisi_sas_v3_hw;
2011 hisi_hba->pci_dev = pdev;
2012 hisi_hba->dev = dev;
2013 hisi_hba->shost = shost;
2014 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
2015
2016 timer_setup(&hisi_hba->timer, NULL, 0);
2017
2018 if (hisi_sas_get_fw_info(hisi_hba) < 0)
2019 goto err_out;
2020
2021 if (hisi_sas_alloc(hisi_hba, shost)) {
2022 hisi_sas_free(hisi_hba);
2023 goto err_out;
2024 }
2025
2026 return shost;
2027 err_out:
2028 scsi_host_put(shost);
2029 dev_err(dev, "shost alloc failed\n");
2030 return NULL;
2031 }
2032
2033 static int
2034 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2035 {
2036 struct Scsi_Host *shost;
2037 struct hisi_hba *hisi_hba;
2038 struct device *dev = &pdev->dev;
2039 struct asd_sas_phy **arr_phy;
2040 struct asd_sas_port **arr_port;
2041 struct sas_ha_struct *sha;
2042 int rc, phy_nr, port_nr, i;
2043
2044 rc = pci_enable_device(pdev);
2045 if (rc)
2046 goto err_out;
2047
2048 pci_set_master(pdev);
2049
2050 rc = pci_request_regions(pdev, DRV_NAME);
2051 if (rc)
2052 goto err_out_disable_device;
2053
2054 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
2055 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
2056 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2057 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2058 dev_err(dev, "No usable DMA addressing method\n");
2059 rc = -EIO;
2060 goto err_out_regions;
2061 }
2062 }
2063
2064 shost = hisi_sas_shost_alloc_pci(pdev);
2065 if (!shost) {
2066 rc = -ENOMEM;
2067 goto err_out_regions;
2068 }
2069
2070 sha = SHOST_TO_SAS_HA(shost);
2071 hisi_hba = shost_priv(shost);
2072 dev_set_drvdata(dev, sha);
2073
2074 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
2075 if (!hisi_hba->regs) {
2076 dev_err(dev, "cannot map register.\n");
2077 rc = -ENOMEM;
2078 goto err_out_ha;
2079 }
2080
2081 phy_nr = port_nr = hisi_hba->n_phy;
2082
2083 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
2084 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
2085 if (!arr_phy || !arr_port) {
2086 rc = -ENOMEM;
2087 goto err_out_ha;
2088 }
2089
2090 sha->sas_phy = arr_phy;
2091 sha->sas_port = arr_port;
2092 sha->core.shost = shost;
2093 sha->lldd_ha = hisi_hba;
2094
2095 shost->transportt = hisi_sas_stt;
2096 shost->max_id = HISI_SAS_MAX_DEVICES;
2097 shost->max_lun = ~0;
2098 shost->max_channel = 1;
2099 shost->max_cmd_len = 16;
2100 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
2101 shost->can_queue = hisi_hba->hw->max_command_entries;
2102 shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
2103
2104 sha->sas_ha_name = DRV_NAME;
2105 sha->dev = dev;
2106 sha->lldd_module = THIS_MODULE;
2107 sha->sas_addr = &hisi_hba->sas_addr[0];
2108 sha->num_phys = hisi_hba->n_phy;
2109 sha->core.shost = hisi_hba->shost;
2110
2111 for (i = 0; i < hisi_hba->n_phy; i++) {
2112 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
2113 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
2114 }
2115
2116 hisi_sas_init_add(hisi_hba);
2117
2118 rc = scsi_add_host(shost, dev);
2119 if (rc)
2120 goto err_out_ha;
2121
2122 rc = sas_register_ha(sha);
2123 if (rc)
2124 goto err_out_register_ha;
2125
2126 rc = hisi_hba->hw->hw_init(hisi_hba);
2127 if (rc)
2128 goto err_out_register_ha;
2129
2130 scsi_scan_host(shost);
2131
2132 return 0;
2133
2134 err_out_register_ha:
2135 scsi_remove_host(shost);
2136 err_out_ha:
2137 scsi_host_put(shost);
2138 err_out_regions:
2139 pci_release_regions(pdev);
2140 err_out_disable_device:
2141 pci_disable_device(pdev);
2142 err_out:
2143 return rc;
2144 }
2145
2146 static void
2147 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
2148 {
2149 int i;
2150
2151 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2152 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2153 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2154 for (i = 0; i < hisi_hba->queue_count; i++) {
2155 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2156
2157 free_irq(pci_irq_vector(pdev, i+16), cq);
2158 }
2159 pci_free_irq_vectors(pdev);
2160 }
2161
2162 static void hisi_sas_v3_remove(struct pci_dev *pdev)
2163 {
2164 struct device *dev = &pdev->dev;
2165 struct sas_ha_struct *sha = dev_get_drvdata(dev);
2166 struct hisi_hba *hisi_hba = sha->lldd_ha;
2167 struct Scsi_Host *shost = sha->core.shost;
2168
2169 sas_unregister_ha(sha);
2170 sas_remove_host(sha->core.shost);
2171
2172 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
2173 hisi_sas_kill_tasklets(hisi_hba);
2174 pci_release_regions(pdev);
2175 pci_disable_device(pdev);
2176 hisi_sas_free(hisi_hba);
2177 scsi_host_put(shost);
2178 }
2179
2180 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = {
2181 { .irq_msk = BIT(19), .msg = "HILINK_INT" },
2182 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" },
2183 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" },
2184 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" },
2185 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" },
2186 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" },
2187 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" },
2188 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" },
2189 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" },
2190 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" },
2191 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" },
2192 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" },
2193 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" },
2194 };
2195
2196 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = {
2197 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" },
2198 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" },
2199 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" },
2200 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" },
2201 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" },
2202 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" },
2203 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" },
2204 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" },
2205 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" },
2206 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" },
2207 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" },
2208 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" },
2209 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" },
2210 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" },
2211 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" },
2212 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" },
2213 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" },
2214 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" },
2215 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" },
2216 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" },
2217 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" },
2218 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" },
2219 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" },
2220 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" },
2221 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" },
2222 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" },
2223 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" },
2224 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" },
2225 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" },
2226 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" },
2227 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" },
2228 };
2229
2230 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba)
2231 {
2232 struct device *dev = hisi_hba->dev;
2233 const struct hisi_sas_hw_error *ras_error;
2234 bool need_reset = false;
2235 u32 irq_value;
2236 int i;
2237
2238 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0);
2239 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) {
2240 ras_error = &sas_ras_intr0_nfe[i];
2241 if (ras_error->irq_msk & irq_value) {
2242 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n",
2243 ras_error->msg, irq_value);
2244 need_reset = true;
2245 }
2246 }
2247 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value);
2248
2249 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1);
2250 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) {
2251 ras_error = &sas_ras_intr1_nfe[i];
2252 if (ras_error->irq_msk & irq_value) {
2253 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n",
2254 ras_error->msg, irq_value);
2255 need_reset = true;
2256 }
2257 }
2258 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value);
2259
2260 return need_reset;
2261 }
2262
2263 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev,
2264 pci_channel_state_t state)
2265 {
2266 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2267 struct hisi_hba *hisi_hba = sha->lldd_ha;
2268 struct device *dev = hisi_hba->dev;
2269
2270 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state);
2271 if (state == pci_channel_io_perm_failure)
2272 return PCI_ERS_RESULT_DISCONNECT;
2273
2274 if (process_non_fatal_error_v3_hw(hisi_hba))
2275 return PCI_ERS_RESULT_NEED_RESET;
2276
2277 return PCI_ERS_RESULT_CAN_RECOVER;
2278 }
2279
2280 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev)
2281 {
2282 return PCI_ERS_RESULT_RECOVERED;
2283 }
2284
2285 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev)
2286 {
2287 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2288 struct hisi_hba *hisi_hba = sha->lldd_ha;
2289 struct device *dev = hisi_hba->dev;
2290 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r);
2291
2292 dev_info(dev, "PCI error: slot reset callback!!\n");
2293 queue_work(hisi_hba->wq, &r.work);
2294 wait_for_completion(r.completion);
2295 if (r.done)
2296 return PCI_ERS_RESULT_RECOVERED;
2297
2298 return PCI_ERS_RESULT_DISCONNECT;
2299 }
2300
2301 enum {
2302 /* instances of the controller */
2303 hip08,
2304 };
2305
2306 static const struct pci_device_id sas_v3_pci_table[] = {
2307 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
2308 {}
2309 };
2310
2311 static const struct pci_error_handlers hisi_sas_err_handler = {
2312 .error_detected = hisi_sas_error_detected_v3_hw,
2313 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw,
2314 .slot_reset = hisi_sas_slot_reset_v3_hw,
2315 };
2316
2317 static struct pci_driver sas_v3_pci_driver = {
2318 .name = DRV_NAME,
2319 .id_table = sas_v3_pci_table,
2320 .probe = hisi_sas_v3_probe,
2321 .remove = hisi_sas_v3_remove,
2322 .err_handler = &hisi_sas_err_handler,
2323 };
2324
2325 module_pci_driver(sas_v3_pci_driver);
2326
2327 MODULE_LICENSE("GPL");
2328 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2329 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2330 MODULE_ALIAS("platform:" DRV_NAME);
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