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[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v3_hw.c
1 /*
2 * Copyright (c) 2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 #include "hisi_sas.h"
12 #define DRV_NAME "hisi_sas_v3_hw"
13
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
26 #define ITCT_CLR 0x44
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CHNL_INT_STATUS 0x148
55 #define HGC_AXI_FIFO_ERR_INFO 0x154
56 #define AXI_ERR_INFO_OFF 0
57 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
58 #define FIFO_ERR_INFO_OFF 8
59 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
60 #define INT_COAL_EN 0x19c
61 #define OQ_INT_COAL_TIME 0x1a0
62 #define OQ_INT_COAL_CNT 0x1a4
63 #define ENT_INT_COAL_TIME 0x1a8
64 #define ENT_INT_COAL_CNT 0x1ac
65 #define OQ_INT_SRC 0x1b0
66 #define OQ_INT_SRC_MSK 0x1b4
67 #define ENT_INT_SRC1 0x1b8
68 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
69 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
70 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
71 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
72 #define ENT_INT_SRC2 0x1bc
73 #define ENT_INT_SRC3 0x1c0
74 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
75 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
76 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
77 #define ENT_INT_SRC3_AXI_OFF 11
78 #define ENT_INT_SRC3_FIFO_OFF 12
79 #define ENT_INT_SRC3_LM_OFF 14
80 #define ENT_INT_SRC3_ITC_INT_OFF 15
81 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
82 #define ENT_INT_SRC3_ABT_OFF 16
83 #define ENT_INT_SRC_MSK1 0x1c4
84 #define ENT_INT_SRC_MSK2 0x1c8
85 #define ENT_INT_SRC_MSK3 0x1cc
86 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
87 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
88 #define CHNL_ENT_INT_MSK 0x1d4
89 #define HGC_COM_INT_MSK 0x1d8
90 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
91 #define SAS_ECC_INTR 0x1e8
92 #define SAS_ECC_INTR_MSK 0x1ec
93 #define HGC_ERR_STAT_EN 0x238
94 #define CQE_SEND_CNT 0x248
95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
97 #define DLVRY_Q_0_DEPTH 0x268
98 #define DLVRY_Q_0_WR_PTR 0x26c
99 #define DLVRY_Q_0_RD_PTR 0x270
100 #define HYPER_STREAM_ID_EN_CFG 0xc80
101 #define OQ0_INT_SRC_MSK 0xc90
102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
104 #define COMPL_Q_0_DEPTH 0x4e8
105 #define COMPL_Q_0_WR_PTR 0x4ec
106 #define COMPL_Q_0_RD_PTR 0x4f0
107 #define AWQOS_AWCACHE_CFG 0xc84
108 #define ARQOS_ARCACHE_CFG 0xc88
109 #define HILINK_ERR_DFX 0xe04
110 #define SAS_GPIO_CFG_0 0x1000
111 #define SAS_GPIO_CFG_1 0x1004
112 #define SAS_GPIO_TX_0_1 0x1040
113 #define SAS_CFG_DRIVE_VLD 0x1070
114
115 /* phy registers requiring init */
116 #define PORT_BASE (0x2000)
117 #define PHY_CFG (PORT_BASE + 0x0)
118 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
119 #define PHY_CFG_ENA_OFF 0
120 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
121 #define PHY_CFG_DC_OPT_OFF 2
122 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
123 #define PHY_CFG_PHY_RST_OFF 3
124 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF)
125 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
126 #define PHY_CTRL (PORT_BASE + 0x14)
127 #define PHY_CTRL_RESET_OFF 0
128 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
129 #define SL_CFG (PORT_BASE + 0x84)
130 #define SL_CONTROL (PORT_BASE + 0x94)
131 #define SL_CONTROL_NOTIFY_EN_OFF 0
132 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
133 #define SL_CTA_OFF 17
134 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
135 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
136 #define RX_BCAST_CHG_OFF 1
137 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
138 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
139 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
140 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
141 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
142 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
143 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
144 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
145 #define TXID_AUTO (PORT_BASE + 0xb8)
146 #define CT3_OFF 1
147 #define CT3_MSK (0x1 << CT3_OFF)
148 #define TX_HARDRST_OFF 2
149 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
150 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
151 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
152 #define STP_LINK_TIMER (PORT_BASE + 0x120)
153 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
154 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
155 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
156 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
157 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
158 #define CHL_INT0 (PORT_BASE + 0x1b4)
159 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
160 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
161 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
162 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
163 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
164 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
165 #define CHL_INT0_NOT_RDY_OFF 4
166 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
167 #define CHL_INT0_PHY_RDY_OFF 5
168 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
169 #define CHL_INT1 (PORT_BASE + 0x1b8)
170 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
171 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
172 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
173 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
174 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
175 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
176 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
177 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
178 #define CHL_INT2 (PORT_BASE + 0x1bc)
179 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
180 #define CHL_INT2_RX_INVLD_DW_OFF 30
181 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
182 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
183 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
184 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
185 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
186 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
187 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
188 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
189 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
190 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
191 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
192 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
193 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
194 #define DMA_TX_STATUS_BUSY_OFF 0
195 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
196 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
197 #define DMA_RX_STATUS_BUSY_OFF 0
198 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
199
200 #define COARSETUNE_TIME (PORT_BASE + 0x304)
201 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
202 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
203 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
204 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
205
206 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
207 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
208 #error Max ITCT exceeded
209 #endif
210
211 #define AXI_MASTER_CFG_BASE (0x5000)
212 #define AM_CTRL_GLOBAL (0x0)
213 #define AM_CTRL_SHUTDOWN_REQ_OFF 0
214 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
215 #define AM_CURR_TRANS_RETURN (0x150)
216
217 #define AM_CFG_MAX_TRANS (0x5010)
218 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
219 #define AXI_CFG (0x5100)
220 #define AM_ROB_ECC_ERR_ADDR (0x510c)
221 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
222 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
223 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
224 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
225
226 /* RAS registers need init */
227 #define RAS_BASE (0x6000)
228 #define SAS_RAS_INTR0 (RAS_BASE)
229 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
230 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
231 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
232 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c)
233 #define SAS_RAS_INTR2 (RAS_BASE + 0x20)
234 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24)
235
236 /* HW dma structures */
237 /* Delivery queue header */
238 /* dw0 */
239 #define CMD_HDR_ABORT_FLAG_OFF 0
240 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
241 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
242 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
243 #define CMD_HDR_RESP_REPORT_OFF 5
244 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
245 #define CMD_HDR_TLR_CTRL_OFF 6
246 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
247 #define CMD_HDR_PORT_OFF 18
248 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
249 #define CMD_HDR_PRIORITY_OFF 27
250 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
251 #define CMD_HDR_CMD_OFF 29
252 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
253 /* dw1 */
254 #define CMD_HDR_UNCON_CMD_OFF 3
255 #define CMD_HDR_DIR_OFF 5
256 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
257 #define CMD_HDR_RESET_OFF 7
258 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
259 #define CMD_HDR_VDTL_OFF 10
260 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
261 #define CMD_HDR_FRAME_TYPE_OFF 11
262 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
263 #define CMD_HDR_DEV_ID_OFF 16
264 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
265 /* dw2 */
266 #define CMD_HDR_CFL_OFF 0
267 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
268 #define CMD_HDR_NCQ_TAG_OFF 10
269 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
270 #define CMD_HDR_MRFL_OFF 15
271 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
272 #define CMD_HDR_SG_MOD_OFF 24
273 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
274 /* dw3 */
275 #define CMD_HDR_IPTT_OFF 0
276 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
277 /* dw6 */
278 #define CMD_HDR_DIF_SGL_LEN_OFF 0
279 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
280 #define CMD_HDR_DATA_SGL_LEN_OFF 16
281 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
282 /* dw7 */
283 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
284 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
285 #define CMD_HDR_ABORT_IPTT_OFF 16
286 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
287
288 /* Completion header */
289 /* dw0 */
290 #define CMPLT_HDR_CMPLT_OFF 0
291 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
292 #define CMPLT_HDR_ERROR_PHASE_OFF 2
293 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
294 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
295 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
296 #define CMPLT_HDR_ERX_OFF 12
297 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
298 #define CMPLT_HDR_ABORT_STAT_OFF 13
299 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
300 /* abort_stat */
301 #define STAT_IO_NOT_VALID 0x1
302 #define STAT_IO_NO_DEVICE 0x2
303 #define STAT_IO_COMPLETE 0x3
304 #define STAT_IO_ABORTED 0x4
305 /* dw1 */
306 #define CMPLT_HDR_IPTT_OFF 0
307 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
308 #define CMPLT_HDR_DEV_ID_OFF 16
309 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
310 /* dw3 */
311 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
312 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
313
314 /* ITCT header */
315 /* qw0 */
316 #define ITCT_HDR_DEV_TYPE_OFF 0
317 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
318 #define ITCT_HDR_VALID_OFF 2
319 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
320 #define ITCT_HDR_MCR_OFF 5
321 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
322 #define ITCT_HDR_VLN_OFF 9
323 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
324 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
325 #define ITCT_HDR_AWT_CONTINUE_OFF 25
326 #define ITCT_HDR_PORT_ID_OFF 28
327 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
328 /* qw2 */
329 #define ITCT_HDR_INLT_OFF 0
330 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
331 #define ITCT_HDR_RTOLT_OFF 48
332 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
333
334 struct hisi_sas_complete_v3_hdr {
335 __le32 dw0;
336 __le32 dw1;
337 __le32 act;
338 __le32 dw3;
339 };
340
341 struct hisi_sas_err_record_v3 {
342 /* dw0 */
343 __le32 trans_tx_fail_type;
344
345 /* dw1 */
346 __le32 trans_rx_fail_type;
347
348 /* dw2 */
349 __le16 dma_tx_err_type;
350 __le16 sipc_rx_err_type;
351
352 /* dw3 */
353 __le32 dma_rx_err_type;
354 };
355
356 #define RX_DATA_LEN_UNDERFLOW_OFF 6
357 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
358
359 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
360 #define HISI_SAS_MSI_COUNT_V3_HW 32
361
362 #define DIR_NO_DATA 0
363 #define DIR_TO_INI 1
364 #define DIR_TO_DEVICE 2
365 #define DIR_RESERVED 3
366
367 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
368 ((fis.command == ATA_CMD_READ_LOG_EXT) || \
369 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
370 ((fis.command == ATA_CMD_DEV_RESET) && \
371 ((fis.control & ATA_SRST) != 0)))
372
373 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
374 {
375 void __iomem *regs = hisi_hba->regs + off;
376
377 return readl(regs);
378 }
379
380 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
381 {
382 void __iomem *regs = hisi_hba->regs + off;
383
384 return readl_relaxed(regs);
385 }
386
387 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
388 {
389 void __iomem *regs = hisi_hba->regs + off;
390
391 writel(val, regs);
392 }
393
394 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
395 u32 off, u32 val)
396 {
397 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
398
399 writel(val, regs);
400 }
401
402 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
403 int phy_no, u32 off)
404 {
405 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
406
407 return readl(regs);
408 }
409
410 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \
411 timeout_us) \
412 ({ \
413 void __iomem *regs = hisi_hba->regs + off; \
414 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \
415 })
416
417 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \
418 timeout_us) \
419 ({ \
420 void __iomem *regs = hisi_hba->regs + off; \
421 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
422 })
423
424 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
425 {
426 struct pci_dev *pdev = hisi_hba->pci_dev;
427 int i;
428
429 /* Global registers init */
430 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
431 (u32)((1ULL << hisi_hba->queue_count) - 1));
432 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
433 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
434 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
435 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
436 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
437 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
438 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
439 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
440 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
441 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
442 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
443 if (pdev->revision >= 0x21)
444 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7fff);
445 else
446 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff);
447 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
448 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
449 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
450 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
451 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
452 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
453 for (i = 0; i < hisi_hba->queue_count; i++)
454 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
455
456 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
457
458 for (i = 0; i < hisi_hba->n_phy; i++) {
459 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
460 struct asd_sas_phy *sas_phy = &phy->sas_phy;
461 u32 prog_phy_link_rate = 0x800;
462
463 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
464 SAS_LINK_RATE_1_5_GBPS)) {
465 prog_phy_link_rate = 0x855;
466 } else {
467 enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
468
469 prog_phy_link_rate =
470 hisi_sas_get_prog_phy_linkrate_mask(max) |
471 0x800;
472 }
473 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
474 prog_phy_link_rate);
475 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
476 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
477 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
478 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
479 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
480 if (pdev->revision >= 0x21)
481 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
482 0xffffffff);
483 else
484 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
485 0xff87ffff);
486 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
487 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
488 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
489 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
490 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
491 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
492 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
493 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
494 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
495
496 /* used for 12G negotiate */
497 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
498 }
499
500 for (i = 0; i < hisi_hba->queue_count; i++) {
501 /* Delivery queue */
502 hisi_sas_write32(hisi_hba,
503 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
504 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
505
506 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
507 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
508
509 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
510 HISI_SAS_QUEUE_SLOTS);
511
512 /* Completion queue */
513 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
514 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
515
516 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
517 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
518
519 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
520 HISI_SAS_QUEUE_SLOTS);
521 }
522
523 /* itct */
524 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
525 lower_32_bits(hisi_hba->itct_dma));
526
527 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
528 upper_32_bits(hisi_hba->itct_dma));
529
530 /* iost */
531 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
532 lower_32_bits(hisi_hba->iost_dma));
533
534 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
535 upper_32_bits(hisi_hba->iost_dma));
536
537 /* breakpoint */
538 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
539 lower_32_bits(hisi_hba->breakpoint_dma));
540
541 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
542 upper_32_bits(hisi_hba->breakpoint_dma));
543
544 /* SATA broken msg */
545 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
546 lower_32_bits(hisi_hba->sata_breakpoint_dma));
547
548 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
549 upper_32_bits(hisi_hba->sata_breakpoint_dma));
550
551 /* SATA initial fis */
552 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
553 lower_32_bits(hisi_hba->initial_fis_dma));
554
555 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
556 upper_32_bits(hisi_hba->initial_fis_dma));
557
558 /* RAS registers init */
559 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
560 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
561 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
562 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
563
564 /* LED registers init */
565 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
566 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
567 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
568 /* Configure blink generator rate A to 1Hz and B to 4Hz */
569 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
570 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
571 }
572
573 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
574 {
575 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
576
577 cfg &= ~PHY_CFG_DC_OPT_MSK;
578 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
579 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
580 }
581
582 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
583 {
584 struct sas_identify_frame identify_frame;
585 u32 *identify_buffer;
586
587 memset(&identify_frame, 0, sizeof(identify_frame));
588 identify_frame.dev_type = SAS_END_DEVICE;
589 identify_frame.frame_type = 0;
590 identify_frame._un1 = 1;
591 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
592 identify_frame.target_bits = SAS_PROTOCOL_NONE;
593 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
594 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
595 identify_frame.phy_id = phy_no;
596 identify_buffer = (u32 *)(&identify_frame);
597
598 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
599 __swab32(identify_buffer[0]));
600 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
601 __swab32(identify_buffer[1]));
602 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
603 __swab32(identify_buffer[2]));
604 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
605 __swab32(identify_buffer[3]));
606 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
607 __swab32(identify_buffer[4]));
608 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
609 __swab32(identify_buffer[5]));
610 }
611
612 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
613 struct hisi_sas_device *sas_dev)
614 {
615 struct domain_device *device = sas_dev->sas_device;
616 struct device *dev = hisi_hba->dev;
617 u64 qw0, device_id = sas_dev->device_id;
618 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
619 struct domain_device *parent_dev = device->parent;
620 struct asd_sas_port *sas_port = device->port;
621 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
622
623 memset(itct, 0, sizeof(*itct));
624
625 /* qw0 */
626 qw0 = 0;
627 switch (sas_dev->dev_type) {
628 case SAS_END_DEVICE:
629 case SAS_EDGE_EXPANDER_DEVICE:
630 case SAS_FANOUT_EXPANDER_DEVICE:
631 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
632 break;
633 case SAS_SATA_DEV:
634 case SAS_SATA_PENDING:
635 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
636 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
637 else
638 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
639 break;
640 default:
641 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
642 sas_dev->dev_type);
643 }
644
645 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
646 (device->linkrate << ITCT_HDR_MCR_OFF) |
647 (1 << ITCT_HDR_VLN_OFF) |
648 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
649 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
650 (port->id << ITCT_HDR_PORT_ID_OFF));
651 itct->qw0 = cpu_to_le64(qw0);
652
653 /* qw1 */
654 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
655 itct->sas_addr = __swab64(itct->sas_addr);
656
657 /* qw2 */
658 if (!dev_is_sata(device))
659 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
660 (0x1ULL << ITCT_HDR_RTOLT_OFF));
661 }
662
663 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba,
664 struct hisi_sas_device *sas_dev)
665 {
666 DECLARE_COMPLETION_ONSTACK(completion);
667 u64 dev_id = sas_dev->device_id;
668 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
669 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
670
671 sas_dev->completion = &completion;
672
673 /* clear the itct interrupt state */
674 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
675 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
676 ENT_INT_SRC3_ITC_INT_MSK);
677
678 /* clear the itct table*/
679 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
680 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
681
682 wait_for_completion(sas_dev->completion);
683 memset(itct, 0, sizeof(struct hisi_sas_itct));
684 }
685
686 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
687 struct domain_device *device)
688 {
689 struct hisi_sas_slot *slot, *slot2;
690 struct hisi_sas_device *sas_dev = device->lldd_dev;
691 u32 cfg_abt_set_query_iptt;
692
693 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
694 CFG_ABT_SET_QUERY_IPTT);
695 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
696 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
697 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
698 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
699 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
700 cfg_abt_set_query_iptt);
701 }
702 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
703 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
704 cfg_abt_set_query_iptt);
705 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
706 1 << CFG_ABT_SET_IPTT_DONE_OFF);
707 }
708
709 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
710 {
711 struct device *dev = hisi_hba->dev;
712 int ret;
713 u32 val;
714
715 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
716
717 /* Disable all of the PHYs */
718 hisi_sas_stop_phys(hisi_hba);
719 udelay(50);
720
721 /* Ensure axi bus idle */
722 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
723 20000, 1000000);
724 if (ret) {
725 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
726 return -EIO;
727 }
728
729 if (ACPI_HANDLE(dev)) {
730 acpi_status s;
731
732 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
733 if (ACPI_FAILURE(s)) {
734 dev_err(dev, "Reset failed\n");
735 return -EIO;
736 }
737 } else {
738 dev_err(dev, "no reset method!\n");
739 return -EINVAL;
740 }
741
742 return 0;
743 }
744
745 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
746 {
747 struct device *dev = hisi_hba->dev;
748 int rc;
749
750 rc = reset_hw_v3_hw(hisi_hba);
751 if (rc) {
752 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
753 return rc;
754 }
755
756 msleep(100);
757 init_reg_v3_hw(hisi_hba);
758
759 return 0;
760 }
761
762 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
763 {
764 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
765
766 cfg |= PHY_CFG_ENA_MSK;
767 cfg &= ~PHY_CFG_PHY_RST_MSK;
768 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
769 }
770
771 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
772 {
773 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
774 u32 state;
775
776 cfg &= ~PHY_CFG_ENA_MSK;
777 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
778
779 mdelay(50);
780
781 state = hisi_sas_read32(hisi_hba, PHY_STATE);
782 if (state & BIT(phy_no)) {
783 cfg |= PHY_CFG_PHY_RST_MSK;
784 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
785 }
786 }
787
788 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
789 {
790 config_id_frame_v3_hw(hisi_hba, phy_no);
791 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
792 enable_phy_v3_hw(hisi_hba, phy_no);
793 }
794
795 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
796 {
797 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
798 u32 txid_auto;
799
800 disable_phy_v3_hw(hisi_hba, phy_no);
801 if (phy->identify.device_type == SAS_END_DEVICE) {
802 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
803 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
804 txid_auto | TX_HARDRST_MSK);
805 }
806 msleep(100);
807 start_phy_v3_hw(hisi_hba, phy_no);
808 }
809
810 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
811 {
812 return SAS_LINK_RATE_12_0_GBPS;
813 }
814
815 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
816 {
817 int i;
818
819 for (i = 0; i < hisi_hba->n_phy; i++) {
820 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
821 struct asd_sas_phy *sas_phy = &phy->sas_phy;
822
823 if (!sas_phy->phy->enabled)
824 continue;
825
826 start_phy_v3_hw(hisi_hba, i);
827 }
828 }
829
830 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
831 {
832 u32 sl_control;
833
834 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
835 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
836 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
837 msleep(1);
838 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
839 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
840 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
841 }
842
843 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
844 {
845 int i, bitmap = 0;
846 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
847 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
848
849 for (i = 0; i < hisi_hba->n_phy; i++)
850 if (phy_state & BIT(i))
851 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
852 bitmap |= BIT(i);
853
854 return bitmap;
855 }
856
857 /**
858 * The callpath to this function and upto writing the write
859 * queue pointer should be safe from interruption.
860 */
861 static int
862 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
863 {
864 struct device *dev = hisi_hba->dev;
865 int queue = dq->id;
866 u32 r, w;
867
868 w = dq->wr_point;
869 r = hisi_sas_read32_relaxed(hisi_hba,
870 DLVRY_Q_0_RD_PTR + (queue * 0x14));
871 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
872 dev_warn(dev, "full queue=%d r=%d w=%d\n",
873 queue, r, w);
874 return -EAGAIN;
875 }
876
877 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
878
879 return w;
880 }
881
882 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
883 {
884 struct hisi_hba *hisi_hba = dq->hisi_hba;
885 struct hisi_sas_slot *s, *s1;
886 struct list_head *dq_list;
887 int dlvry_queue = dq->id;
888 int wp, count = 0;
889
890 dq_list = &dq->list;
891 list_for_each_entry_safe(s, s1, &dq->list, delivery) {
892 if (!s->ready)
893 break;
894 count++;
895 wp = (s->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
896 list_del(&s->delivery);
897 }
898
899 if (!count)
900 return;
901
902 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
903 }
904
905 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
906 struct hisi_sas_slot *slot,
907 struct hisi_sas_cmd_hdr *hdr,
908 struct scatterlist *scatter,
909 int n_elem)
910 {
911 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
912 struct scatterlist *sg;
913 int i;
914
915 for_each_sg(scatter, sg, n_elem, i) {
916 struct hisi_sas_sge *entry = &sge_page->sge[i];
917
918 entry->addr = cpu_to_le64(sg_dma_address(sg));
919 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
920 entry->data_len = cpu_to_le32(sg_dma_len(sg));
921 entry->data_off = 0;
922 }
923
924 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
925
926 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
927 }
928
929 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
930 struct hisi_sas_slot *slot)
931 {
932 struct sas_task *task = slot->task;
933 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
934 struct domain_device *device = task->dev;
935 struct hisi_sas_device *sas_dev = device->lldd_dev;
936 struct hisi_sas_port *port = slot->port;
937 struct sas_ssp_task *ssp_task = &task->ssp_task;
938 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
939 struct hisi_sas_tmf_task *tmf = slot->tmf;
940 int has_data = 0, priority = !!tmf;
941 u8 *buf_cmd;
942 u32 dw1 = 0, dw2 = 0;
943
944 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
945 (2 << CMD_HDR_TLR_CTRL_OFF) |
946 (port->id << CMD_HDR_PORT_OFF) |
947 (priority << CMD_HDR_PRIORITY_OFF) |
948 (1 << CMD_HDR_CMD_OFF)); /* ssp */
949
950 dw1 = 1 << CMD_HDR_VDTL_OFF;
951 if (tmf) {
952 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
953 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
954 } else {
955 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
956 switch (scsi_cmnd->sc_data_direction) {
957 case DMA_TO_DEVICE:
958 has_data = 1;
959 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
960 break;
961 case DMA_FROM_DEVICE:
962 has_data = 1;
963 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
964 break;
965 default:
966 dw1 &= ~CMD_HDR_DIR_MSK;
967 }
968 }
969
970 /* map itct entry */
971 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
972 hdr->dw1 = cpu_to_le32(dw1);
973
974 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
975 + 3) / 4) << CMD_HDR_CFL_OFF) |
976 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
977 (2 << CMD_HDR_SG_MOD_OFF);
978 hdr->dw2 = cpu_to_le32(dw2);
979 hdr->transfer_tags = cpu_to_le32(slot->idx);
980
981 if (has_data)
982 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
983 slot->n_elem);
984
985 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
986 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
987 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
988
989 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
990 sizeof(struct ssp_frame_hdr);
991
992 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
993 if (!tmf) {
994 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
995 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
996 } else {
997 buf_cmd[10] = tmf->tmf;
998 switch (tmf->tmf) {
999 case TMF_ABORT_TASK:
1000 case TMF_QUERY_TASK:
1001 buf_cmd[12] =
1002 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1003 buf_cmd[13] =
1004 tmf->tag_of_task_to_be_managed & 0xff;
1005 break;
1006 default:
1007 break;
1008 }
1009 }
1010 }
1011
1012 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1013 struct hisi_sas_slot *slot)
1014 {
1015 struct sas_task *task = slot->task;
1016 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1017 struct domain_device *device = task->dev;
1018 struct hisi_sas_port *port = slot->port;
1019 struct scatterlist *sg_req;
1020 struct hisi_sas_device *sas_dev = device->lldd_dev;
1021 dma_addr_t req_dma_addr;
1022 unsigned int req_len;
1023
1024 /* req */
1025 sg_req = &task->smp_task.smp_req;
1026 req_len = sg_dma_len(sg_req);
1027 req_dma_addr = sg_dma_address(sg_req);
1028
1029 /* create header */
1030 /* dw0 */
1031 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1032 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1033 (2 << CMD_HDR_CMD_OFF)); /* smp */
1034
1035 /* map itct entry */
1036 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1037 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1038 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1039
1040 /* dw2 */
1041 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1042 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1043 CMD_HDR_MRFL_OFF));
1044
1045 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1046
1047 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1048 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1049
1050 }
1051
1052 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1053 struct hisi_sas_slot *slot)
1054 {
1055 struct sas_task *task = slot->task;
1056 struct domain_device *device = task->dev;
1057 struct domain_device *parent_dev = device->parent;
1058 struct hisi_sas_device *sas_dev = device->lldd_dev;
1059 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1060 struct asd_sas_port *sas_port = device->port;
1061 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1062 u8 *buf_cmd;
1063 int has_data = 0, hdr_tag = 0;
1064 u32 dw1 = 0, dw2 = 0;
1065
1066 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1067 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1068 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1069 else
1070 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1071
1072 switch (task->data_dir) {
1073 case DMA_TO_DEVICE:
1074 has_data = 1;
1075 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1076 break;
1077 case DMA_FROM_DEVICE:
1078 has_data = 1;
1079 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1080 break;
1081 default:
1082 dw1 &= ~CMD_HDR_DIR_MSK;
1083 }
1084
1085 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1086 (task->ata_task.fis.control & ATA_SRST))
1087 dw1 |= 1 << CMD_HDR_RESET_OFF;
1088
1089 dw1 |= (hisi_sas_get_ata_protocol(
1090 &task->ata_task.fis, task->data_dir))
1091 << CMD_HDR_FRAME_TYPE_OFF;
1092 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1093
1094 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1095 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1096
1097 hdr->dw1 = cpu_to_le32(dw1);
1098
1099 /* dw2 */
1100 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
1101 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1102 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1103 }
1104
1105 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1106 2 << CMD_HDR_SG_MOD_OFF;
1107 hdr->dw2 = cpu_to_le32(dw2);
1108
1109 /* dw3 */
1110 hdr->transfer_tags = cpu_to_le32(slot->idx);
1111
1112 if (has_data)
1113 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1114 slot->n_elem);
1115
1116 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1117 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1118 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1119
1120 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1121
1122 if (likely(!task->ata_task.device_control_reg_update))
1123 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1124 /* fill in command FIS */
1125 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1126 }
1127
1128 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1129 struct hisi_sas_slot *slot,
1130 int device_id, int abort_flag, int tag_to_abort)
1131 {
1132 struct sas_task *task = slot->task;
1133 struct domain_device *dev = task->dev;
1134 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1135 struct hisi_sas_port *port = slot->port;
1136
1137 /* dw0 */
1138 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1139 (port->id << CMD_HDR_PORT_OFF) |
1140 (dev_is_sata(dev)
1141 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1142 (abort_flag
1143 << CMD_HDR_ABORT_FLAG_OFF));
1144
1145 /* dw1 */
1146 hdr->dw1 = cpu_to_le32(device_id
1147 << CMD_HDR_DEV_ID_OFF);
1148
1149 /* dw7 */
1150 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1151 hdr->transfer_tags = cpu_to_le32(slot->idx);
1152
1153 }
1154
1155 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1156 {
1157 int i, res;
1158 u32 context, port_id, link_rate;
1159 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1160 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1161 struct device *dev = hisi_hba->dev;
1162 unsigned long flags;
1163
1164 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1165
1166 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1167 port_id = (port_id >> (4 * phy_no)) & 0xf;
1168 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1169 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1170
1171 if (port_id == 0xf) {
1172 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1173 res = IRQ_NONE;
1174 goto end;
1175 }
1176 sas_phy->linkrate = link_rate;
1177 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1178
1179 /* Check for SATA dev */
1180 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1181 if (context & (1 << phy_no)) {
1182 struct hisi_sas_initial_fis *initial_fis;
1183 struct dev_to_host_fis *fis;
1184 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1185
1186 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1187 initial_fis = &hisi_hba->initial_fis[phy_no];
1188 fis = &initial_fis->fis;
1189 sas_phy->oob_mode = SATA_OOB_MODE;
1190 attached_sas_addr[0] = 0x50;
1191 attached_sas_addr[7] = phy_no;
1192 memcpy(sas_phy->attached_sas_addr,
1193 attached_sas_addr,
1194 SAS_ADDR_SIZE);
1195 memcpy(sas_phy->frame_rcvd, fis,
1196 sizeof(struct dev_to_host_fis));
1197 phy->phy_type |= PORT_TYPE_SATA;
1198 phy->identify.device_type = SAS_SATA_DEV;
1199 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1200 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1201 } else {
1202 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1203 struct sas_identify_frame *id =
1204 (struct sas_identify_frame *)frame_rcvd;
1205
1206 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1207 for (i = 0; i < 6; i++) {
1208 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1209 RX_IDAF_DWORD0 + (i * 4));
1210 frame_rcvd[i] = __swab32(idaf);
1211 }
1212 sas_phy->oob_mode = SAS_OOB_MODE;
1213 memcpy(sas_phy->attached_sas_addr,
1214 &id->sas_addr,
1215 SAS_ADDR_SIZE);
1216 phy->phy_type |= PORT_TYPE_SAS;
1217 phy->identify.device_type = id->dev_type;
1218 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1219 if (phy->identify.device_type == SAS_END_DEVICE)
1220 phy->identify.target_port_protocols =
1221 SAS_PROTOCOL_SSP;
1222 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1223 phy->identify.target_port_protocols =
1224 SAS_PROTOCOL_SMP;
1225 }
1226
1227 phy->port_id = port_id;
1228 phy->phy_attached = 1;
1229 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1230 res = IRQ_HANDLED;
1231 spin_lock_irqsave(&phy->lock, flags);
1232 if (phy->reset_completion) {
1233 phy->in_reset = 0;
1234 complete(phy->reset_completion);
1235 }
1236 spin_unlock_irqrestore(&phy->lock, flags);
1237 end:
1238 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1239 CHL_INT0_SL_PHY_ENABLE_MSK);
1240 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1241
1242 return res;
1243 }
1244
1245 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1246 {
1247 u32 phy_state, sl_ctrl, txid_auto;
1248 struct device *dev = hisi_hba->dev;
1249
1250 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1251
1252 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1253 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1254 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1255
1256 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1257 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1258 sl_ctrl&(~SL_CTA_MSK));
1259
1260 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1261 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1262 txid_auto | CT3_MSK);
1263
1264 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1265 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1266
1267 return IRQ_HANDLED;
1268 }
1269
1270 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1271 {
1272 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1273 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1274 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1275 u32 bcast_status;
1276
1277 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1278 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1279 if ((bcast_status & RX_BCAST_CHG_MSK) &&
1280 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
1281 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1282 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1283 CHL_INT0_SL_RX_BCST_ACK_MSK);
1284 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1285
1286 return IRQ_HANDLED;
1287 }
1288
1289 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1290 {
1291 struct hisi_hba *hisi_hba = p;
1292 u32 irq_msk;
1293 int phy_no = 0;
1294 irqreturn_t res = IRQ_NONE;
1295
1296 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1297 & 0x11111111;
1298 while (irq_msk) {
1299 if (irq_msk & 1) {
1300 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1301 CHL_INT0);
1302 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1303 int rdy = phy_state & (1 << phy_no);
1304
1305 if (rdy) {
1306 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1307 /* phy up */
1308 if (phy_up_v3_hw(phy_no, hisi_hba)
1309 == IRQ_HANDLED)
1310 res = IRQ_HANDLED;
1311 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1312 /* phy bcast */
1313 if (phy_bcast_v3_hw(phy_no, hisi_hba)
1314 == IRQ_HANDLED)
1315 res = IRQ_HANDLED;
1316 } else {
1317 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1318 /* phy down */
1319 if (phy_down_v3_hw(phy_no, hisi_hba)
1320 == IRQ_HANDLED)
1321 res = IRQ_HANDLED;
1322 }
1323 }
1324 irq_msk >>= 4;
1325 phy_no++;
1326 }
1327
1328 return res;
1329 }
1330
1331 static const struct hisi_sas_hw_error port_axi_error[] = {
1332 {
1333 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1334 .msg = "dma_tx_axi_wr_err",
1335 },
1336 {
1337 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1338 .msg = "dma_tx_axi_rd_err",
1339 },
1340 {
1341 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1342 .msg = "dma_rx_axi_wr_err",
1343 },
1344 {
1345 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1346 .msg = "dma_rx_axi_rd_err",
1347 },
1348 };
1349
1350 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1351 {
1352 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1353 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1354 struct device *dev = hisi_hba->dev;
1355 int i;
1356
1357 irq_value &= ~irq_msk;
1358 if (!irq_value)
1359 return;
1360
1361 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1362 const struct hisi_sas_hw_error *error = &port_axi_error[i];
1363
1364 if (!(irq_value & error->irq_msk))
1365 continue;
1366
1367 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1368 error->msg, phy_no, irq_value);
1369 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1370 }
1371
1372 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
1373 }
1374
1375 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1376 {
1377 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1378 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1379 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1380 struct pci_dev *pci_dev = hisi_hba->pci_dev;
1381 struct device *dev = hisi_hba->dev;
1382
1383 irq_value &= ~irq_msk;
1384 if (!irq_value)
1385 return;
1386
1387 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1388 dev_warn(dev, "phy%d identify timeout\n", phy_no);
1389 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1390 }
1391
1392 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1393 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1394 STP_LINK_TIMEOUT_STATE);
1395
1396 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1397 phy_no, reg_value);
1398 if (reg_value & BIT(4))
1399 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1400 }
1401
1402 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1403 (pci_dev->revision == 0x20)) {
1404 u32 reg_value;
1405 int rc;
1406
1407 rc = hisi_sas_read32_poll_timeout_atomic(
1408 HILINK_ERR_DFX, reg_value,
1409 !((reg_value >> 8) & BIT(phy_no)),
1410 1000, 10000);
1411 if (rc)
1412 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1413 }
1414
1415 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
1416 }
1417
1418 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1419 {
1420 struct hisi_hba *hisi_hba = p;
1421 u32 irq_msk;
1422 int phy_no = 0;
1423
1424 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1425 & 0xeeeeeeee;
1426
1427 while (irq_msk) {
1428 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1429 CHL_INT0);
1430
1431 if (irq_msk & (4 << (phy_no * 4)))
1432 handle_chl_int1_v3_hw(hisi_hba, phy_no);
1433
1434 if (irq_msk & (8 << (phy_no * 4)))
1435 handle_chl_int2_v3_hw(hisi_hba, phy_no);
1436
1437 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1438 hisi_sas_phy_write32(hisi_hba, phy_no,
1439 CHL_INT0, irq_value0
1440 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1441 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1442 & (~CHL_INT0_NOT_RDY_MSK));
1443 }
1444 irq_msk &= ~(0xe << (phy_no * 4));
1445 phy_no++;
1446 }
1447
1448 return IRQ_HANDLED;
1449 }
1450
1451 static const struct hisi_sas_hw_error axi_error[] = {
1452 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1453 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1454 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1455 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1456 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1457 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1458 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1459 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1460 {},
1461 };
1462
1463 static const struct hisi_sas_hw_error fifo_error[] = {
1464 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
1465 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
1466 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1467 { .msk = BIT(11), .msg = "CMDP_FIFO" },
1468 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1469 {},
1470 };
1471
1472 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1473 {
1474 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1475 .msg = "write pointer and depth",
1476 },
1477 {
1478 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
1479 .msg = "iptt no match slot",
1480 },
1481 {
1482 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
1483 .msg = "read pointer and depth",
1484 },
1485 {
1486 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
1487 .reg = HGC_AXI_FIFO_ERR_INFO,
1488 .sub = axi_error,
1489 },
1490 {
1491 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
1492 .reg = HGC_AXI_FIFO_ERR_INFO,
1493 .sub = fifo_error,
1494 },
1495 {
1496 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
1497 .msg = "LM add/fetch list",
1498 },
1499 {
1500 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
1501 .msg = "SAS_HGC_ABT fetch LM list",
1502 },
1503 };
1504
1505 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
1506 {
1507 u32 irq_value, irq_msk;
1508 struct hisi_hba *hisi_hba = p;
1509 struct device *dev = hisi_hba->dev;
1510 int i;
1511
1512 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1513 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
1514
1515 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
1516 irq_value &= ~irq_msk;
1517
1518 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
1519 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
1520
1521 if (!(irq_value & error->irq_msk))
1522 continue;
1523
1524 if (error->sub) {
1525 const struct hisi_sas_hw_error *sub = error->sub;
1526 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
1527
1528 for (; sub->msk || sub->msg; sub++) {
1529 if (!(err_value & sub->msk))
1530 continue;
1531
1532 dev_err(dev, "%s error (0x%x) found!\n",
1533 sub->msg, irq_value);
1534 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1535 }
1536 } else {
1537 dev_err(dev, "%s error (0x%x) found!\n",
1538 error->msg, irq_value);
1539 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1540 }
1541 }
1542
1543 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
1544 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
1545 u32 dev_id = reg_val & ITCT_DEV_MSK;
1546 struct hisi_sas_device *sas_dev =
1547 &hisi_hba->devices[dev_id];
1548
1549 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
1550 dev_dbg(dev, "clear ITCT ok\n");
1551 complete(sas_dev->completion);
1552 }
1553
1554 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
1555 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
1556
1557 return IRQ_HANDLED;
1558 }
1559
1560 static void
1561 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1562 struct hisi_sas_slot *slot)
1563 {
1564 struct task_status_struct *ts = &task->task_status;
1565 struct hisi_sas_complete_v3_hdr *complete_queue =
1566 hisi_hba->complete_hdr[slot->cmplt_queue];
1567 struct hisi_sas_complete_v3_hdr *complete_hdr =
1568 &complete_queue[slot->cmplt_queue_slot];
1569 struct hisi_sas_err_record_v3 *record =
1570 hisi_sas_status_buf_addr_mem(slot);
1571 u32 dma_rx_err_type = record->dma_rx_err_type;
1572 u32 trans_tx_fail_type = record->trans_tx_fail_type;
1573
1574 switch (task->task_proto) {
1575 case SAS_PROTOCOL_SSP:
1576 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1577 ts->residual = trans_tx_fail_type;
1578 ts->stat = SAS_DATA_UNDERRUN;
1579 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1580 ts->stat = SAS_QUEUE_FULL;
1581 slot->abort = 1;
1582 } else {
1583 ts->stat = SAS_OPEN_REJECT;
1584 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1585 }
1586 break;
1587 case SAS_PROTOCOL_SATA:
1588 case SAS_PROTOCOL_STP:
1589 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1590 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1591 ts->residual = trans_tx_fail_type;
1592 ts->stat = SAS_DATA_UNDERRUN;
1593 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1594 ts->stat = SAS_PHY_DOWN;
1595 slot->abort = 1;
1596 } else {
1597 ts->stat = SAS_OPEN_REJECT;
1598 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1599 }
1600 hisi_sas_sata_done(task, slot);
1601 break;
1602 case SAS_PROTOCOL_SMP:
1603 ts->stat = SAM_STAT_CHECK_CONDITION;
1604 break;
1605 default:
1606 break;
1607 }
1608 }
1609
1610 static int
1611 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1612 {
1613 struct sas_task *task = slot->task;
1614 struct hisi_sas_device *sas_dev;
1615 struct device *dev = hisi_hba->dev;
1616 struct task_status_struct *ts;
1617 struct domain_device *device;
1618 struct sas_ha_struct *ha;
1619 enum exec_status sts;
1620 struct hisi_sas_complete_v3_hdr *complete_queue =
1621 hisi_hba->complete_hdr[slot->cmplt_queue];
1622 struct hisi_sas_complete_v3_hdr *complete_hdr =
1623 &complete_queue[slot->cmplt_queue_slot];
1624 unsigned long flags;
1625 bool is_internal = slot->is_internal;
1626
1627 if (unlikely(!task || !task->lldd_task || !task->dev))
1628 return -EINVAL;
1629
1630 ts = &task->task_status;
1631 device = task->dev;
1632 ha = device->port->ha;
1633 sas_dev = device->lldd_dev;
1634
1635 spin_lock_irqsave(&task->task_state_lock, flags);
1636 task->task_state_flags &=
1637 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1638 spin_unlock_irqrestore(&task->task_state_lock, flags);
1639
1640 memset(ts, 0, sizeof(*ts));
1641 ts->resp = SAS_TASK_COMPLETE;
1642
1643 if (unlikely(!sas_dev)) {
1644 dev_dbg(dev, "slot complete: port has not device\n");
1645 ts->stat = SAS_PHY_DOWN;
1646 goto out;
1647 }
1648
1649 /*
1650 * Use SAS+TMF status codes
1651 */
1652 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1653 >> CMPLT_HDR_ABORT_STAT_OFF) {
1654 case STAT_IO_ABORTED:
1655 /* this IO has been aborted by abort command */
1656 ts->stat = SAS_ABORTED_TASK;
1657 goto out;
1658 case STAT_IO_COMPLETE:
1659 /* internal abort command complete */
1660 ts->stat = TMF_RESP_FUNC_SUCC;
1661 goto out;
1662 case STAT_IO_NO_DEVICE:
1663 ts->stat = TMF_RESP_FUNC_COMPLETE;
1664 goto out;
1665 case STAT_IO_NOT_VALID:
1666 /*
1667 * abort single IO, the controller can't find the IO
1668 */
1669 ts->stat = TMF_RESP_FUNC_FAILED;
1670 goto out;
1671 default:
1672 break;
1673 }
1674
1675 /* check for erroneous completion */
1676 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1677 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
1678
1679 slot_err_v3_hw(hisi_hba, task, slot);
1680 if (ts->stat != SAS_DATA_UNDERRUN)
1681 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
1682 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
1683 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
1684 slot->idx, task, sas_dev->device_id,
1685 complete_hdr->dw0, complete_hdr->dw1,
1686 complete_hdr->act, complete_hdr->dw3,
1687 error_info[0], error_info[1],
1688 error_info[2], error_info[3]);
1689 if (unlikely(slot->abort))
1690 return ts->stat;
1691 goto out;
1692 }
1693
1694 switch (task->task_proto) {
1695 case SAS_PROTOCOL_SSP: {
1696 struct ssp_response_iu *iu =
1697 hisi_sas_status_buf_addr_mem(slot) +
1698 sizeof(struct hisi_sas_err_record);
1699
1700 sas_ssp_task_response(dev, task, iu);
1701 break;
1702 }
1703 case SAS_PROTOCOL_SMP: {
1704 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1705 void *to;
1706
1707 ts->stat = SAM_STAT_GOOD;
1708 to = kmap_atomic(sg_page(sg_resp));
1709
1710 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1711 DMA_FROM_DEVICE);
1712 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1713 DMA_TO_DEVICE);
1714 memcpy(to + sg_resp->offset,
1715 hisi_sas_status_buf_addr_mem(slot) +
1716 sizeof(struct hisi_sas_err_record),
1717 sg_dma_len(sg_resp));
1718 kunmap_atomic(to);
1719 break;
1720 }
1721 case SAS_PROTOCOL_SATA:
1722 case SAS_PROTOCOL_STP:
1723 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1724 ts->stat = SAM_STAT_GOOD;
1725 hisi_sas_sata_done(task, slot);
1726 break;
1727 default:
1728 ts->stat = SAM_STAT_CHECK_CONDITION;
1729 break;
1730 }
1731
1732 if (!slot->port->port_attached) {
1733 dev_warn(dev, "slot complete: port %d has removed\n",
1734 slot->port->sas_port.id);
1735 ts->stat = SAS_PHY_DOWN;
1736 }
1737
1738 out:
1739 hisi_sas_slot_task_free(hisi_hba, task, slot);
1740 sts = ts->stat;
1741 spin_lock_irqsave(&task->task_state_lock, flags);
1742 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
1743 spin_unlock_irqrestore(&task->task_state_lock, flags);
1744 dev_info(dev, "slot complete: task(%p) aborted\n", task);
1745 return SAS_ABORTED_TASK;
1746 }
1747 task->task_state_flags |= SAS_TASK_STATE_DONE;
1748 spin_unlock_irqrestore(&task->task_state_lock, flags);
1749
1750 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
1751 spin_lock_irqsave(&device->done_lock, flags);
1752 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
1753 spin_unlock_irqrestore(&device->done_lock, flags);
1754 dev_info(dev, "slot complete: task(%p) ignored\n ",
1755 task);
1756 return sts;
1757 }
1758 spin_unlock_irqrestore(&device->done_lock, flags);
1759 }
1760
1761 if (task->task_done)
1762 task->task_done(task);
1763
1764 return sts;
1765 }
1766
1767 static void cq_tasklet_v3_hw(unsigned long val)
1768 {
1769 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1770 struct hisi_hba *hisi_hba = cq->hisi_hba;
1771 struct hisi_sas_slot *slot;
1772 struct hisi_sas_complete_v3_hdr *complete_queue;
1773 u32 rd_point = cq->rd_point, wr_point;
1774 int queue = cq->id;
1775
1776 complete_queue = hisi_hba->complete_hdr[queue];
1777
1778 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1779 (0x14 * queue));
1780
1781 while (rd_point != wr_point) {
1782 struct hisi_sas_complete_v3_hdr *complete_hdr;
1783 struct device *dev = hisi_hba->dev;
1784 int iptt;
1785
1786 complete_hdr = &complete_queue[rd_point];
1787
1788 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1789 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
1790 slot = &hisi_hba->slot_info[iptt];
1791 slot->cmplt_queue_slot = rd_point;
1792 slot->cmplt_queue = queue;
1793 slot_complete_v3_hw(hisi_hba, slot);
1794 } else
1795 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
1796
1797 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1798 rd_point = 0;
1799 }
1800
1801 /* update rd_point */
1802 cq->rd_point = rd_point;
1803 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1804 }
1805
1806 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1807 {
1808 struct hisi_sas_cq *cq = p;
1809 struct hisi_hba *hisi_hba = cq->hisi_hba;
1810 int queue = cq->id;
1811
1812 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1813
1814 tasklet_schedule(&cq->tasklet);
1815
1816 return IRQ_HANDLED;
1817 }
1818
1819 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1820 {
1821 struct device *dev = hisi_hba->dev;
1822 struct pci_dev *pdev = hisi_hba->pci_dev;
1823 int vectors, rc;
1824 int i, k;
1825 int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1826
1827 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1828 max_msi, PCI_IRQ_MSI);
1829 if (vectors < max_msi) {
1830 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1831 return -ENOENT;
1832 }
1833
1834 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1835 int_phy_up_down_bcast_v3_hw, 0,
1836 DRV_NAME " phy", hisi_hba);
1837 if (rc) {
1838 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1839 rc = -ENOENT;
1840 goto free_irq_vectors;
1841 }
1842
1843 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1844 int_chnl_int_v3_hw, 0,
1845 DRV_NAME " channel", hisi_hba);
1846 if (rc) {
1847 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1848 rc = -ENOENT;
1849 goto free_phy_irq;
1850 }
1851
1852 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
1853 fatal_axi_int_v3_hw, 0,
1854 DRV_NAME " fatal", hisi_hba);
1855 if (rc) {
1856 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
1857 rc = -ENOENT;
1858 goto free_chnl_interrupt;
1859 }
1860
1861 /* Init tasklets for cq only */
1862 for (i = 0; i < hisi_hba->queue_count; i++) {
1863 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1864 struct tasklet_struct *t = &cq->tasklet;
1865
1866 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1867 cq_interrupt_v3_hw, 0,
1868 DRV_NAME " cq", cq);
1869 if (rc) {
1870 dev_err(dev,
1871 "could not request cq%d interrupt, rc=%d\n",
1872 i, rc);
1873 rc = -ENOENT;
1874 goto free_cq_irqs;
1875 }
1876
1877 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1878 }
1879
1880 return 0;
1881
1882 free_cq_irqs:
1883 for (k = 0; k < i; k++) {
1884 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1885
1886 free_irq(pci_irq_vector(pdev, k+16), cq);
1887 }
1888 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
1889 free_chnl_interrupt:
1890 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1891 free_phy_irq:
1892 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1893 free_irq_vectors:
1894 pci_free_irq_vectors(pdev);
1895 return rc;
1896 }
1897
1898 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1899 {
1900 int rc;
1901
1902 rc = hw_init_v3_hw(hisi_hba);
1903 if (rc)
1904 return rc;
1905
1906 rc = interrupt_init_v3_hw(hisi_hba);
1907 if (rc)
1908 return rc;
1909
1910 return 0;
1911 }
1912
1913 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
1914 struct sas_phy_linkrates *r)
1915 {
1916 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1917 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1918 enum sas_linkrate min, max;
1919 u32 prog_phy_link_rate = 0x800;
1920
1921 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1922 max = sas_phy->phy->maximum_linkrate;
1923 min = r->minimum_linkrate;
1924 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1925 max = r->maximum_linkrate;
1926 min = sas_phy->phy->minimum_linkrate;
1927 } else
1928 return;
1929
1930 sas_phy->phy->maximum_linkrate = max;
1931 sas_phy->phy->minimum_linkrate = min;
1932 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
1933
1934 disable_phy_v3_hw(hisi_hba, phy_no);
1935 msleep(100);
1936 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1937 prog_phy_link_rate);
1938 start_phy_v3_hw(hisi_hba, phy_no);
1939 }
1940
1941 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
1942 {
1943 struct pci_dev *pdev = hisi_hba->pci_dev;
1944 int i;
1945
1946 synchronize_irq(pci_irq_vector(pdev, 1));
1947 synchronize_irq(pci_irq_vector(pdev, 2));
1948 synchronize_irq(pci_irq_vector(pdev, 11));
1949 for (i = 0; i < hisi_hba->queue_count; i++) {
1950 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
1951 synchronize_irq(pci_irq_vector(pdev, i + 16));
1952 }
1953
1954 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
1955 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
1956 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
1957 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1958
1959 for (i = 0; i < hisi_hba->n_phy; i++) {
1960 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1961 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
1962 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
1963 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
1964 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
1965 }
1966 }
1967
1968 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
1969 {
1970 return hisi_sas_read32(hisi_hba, PHY_STATE);
1971 }
1972
1973 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1974 {
1975 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1976 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1977 struct sas_phy *sphy = sas_phy->phy;
1978 u32 reg_value;
1979
1980 /* loss dword sync */
1981 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1982 sphy->loss_of_dword_sync_count += reg_value;
1983
1984 /* phy reset problem */
1985 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1986 sphy->phy_reset_problem_count += reg_value;
1987
1988 /* invalid dword */
1989 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1990 sphy->invalid_dword_count += reg_value;
1991
1992 /* disparity err */
1993 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1994 sphy->running_disparity_error_count += reg_value;
1995
1996 }
1997
1998 static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
1999 {
2000 struct device *dev = hisi_hba->dev;
2001 u32 status, reg_val;
2002 int rc;
2003
2004 interrupt_disable_v3_hw(hisi_hba);
2005 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2006 hisi_sas_kill_tasklets(hisi_hba);
2007
2008 hisi_sas_stop_phys(hisi_hba);
2009
2010 mdelay(10);
2011
2012 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2013 AM_CTRL_GLOBAL);
2014 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2015 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2016 AM_CTRL_GLOBAL, reg_val);
2017
2018 /* wait until bus idle */
2019 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2020 AM_CURR_TRANS_RETURN, status,
2021 status == 0x3, 10, 100);
2022 if (rc) {
2023 dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
2024 return rc;
2025 }
2026
2027 return 0;
2028 }
2029
2030 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
2031 {
2032 struct device *dev = hisi_hba->dev;
2033 int rc;
2034
2035 rc = disable_host_v3_hw(hisi_hba);
2036 if (rc) {
2037 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
2038 return rc;
2039 }
2040
2041 hisi_sas_init_mem(hisi_hba);
2042
2043 return hw_init_v3_hw(hisi_hba);
2044 }
2045
2046 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2047 u8 reg_index, u8 reg_count, u8 *write_data)
2048 {
2049 struct device *dev = hisi_hba->dev;
2050 u32 *data = (u32 *)write_data;
2051 int i;
2052
2053 switch (reg_type) {
2054 case SAS_GPIO_REG_TX:
2055 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2056 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2057 reg_index, reg_index + reg_count - 1);
2058 return -EINVAL;
2059 }
2060
2061 for (i = 0; i < reg_count; i++)
2062 hisi_sas_write32(hisi_hba,
2063 SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2064 data[i]);
2065 break;
2066 default:
2067 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2068 reg_type);
2069 return -EINVAL;
2070 }
2071
2072 return 0;
2073 }
2074
2075 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2076 int delay_ms, int timeout_ms)
2077 {
2078 struct device *dev = hisi_hba->dev;
2079 int entries, entries_old = 0, time;
2080
2081 for (time = 0; time < timeout_ms; time += delay_ms) {
2082 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2083 if (entries == entries_old)
2084 break;
2085
2086 entries_old = entries;
2087 msleep(delay_ms);
2088 }
2089
2090 dev_dbg(dev, "wait commands complete %dms\n", time);
2091 }
2092
2093 static struct scsi_host_template sht_v3_hw = {
2094 .name = DRV_NAME,
2095 .module = THIS_MODULE,
2096 .queuecommand = sas_queuecommand,
2097 .target_alloc = sas_target_alloc,
2098 .slave_configure = hisi_sas_slave_configure,
2099 .scan_finished = hisi_sas_scan_finished,
2100 .scan_start = hisi_sas_scan_start,
2101 .change_queue_depth = sas_change_queue_depth,
2102 .bios_param = sas_bios_param,
2103 .can_queue = 1,
2104 .this_id = -1,
2105 .sg_tablesize = SG_ALL,
2106 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
2107 .use_clustering = ENABLE_CLUSTERING,
2108 .eh_device_reset_handler = sas_eh_device_reset_handler,
2109 .eh_target_reset_handler = sas_eh_target_reset_handler,
2110 .target_destroy = sas_target_destroy,
2111 .ioctl = sas_ioctl,
2112 .shost_attrs = host_attrs,
2113 };
2114
2115 static const struct hisi_sas_hw hisi_sas_v3_hw = {
2116 .hw_init = hisi_sas_v3_init,
2117 .setup_itct = setup_itct_v3_hw,
2118 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
2119 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
2120 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
2121 .clear_itct = clear_itct_v3_hw,
2122 .sl_notify = sl_notify_v3_hw,
2123 .prep_ssp = prep_ssp_v3_hw,
2124 .prep_smp = prep_smp_v3_hw,
2125 .prep_stp = prep_ata_v3_hw,
2126 .prep_abort = prep_abort_v3_hw,
2127 .get_free_slot = get_free_slot_v3_hw,
2128 .start_delivery = start_delivery_v3_hw,
2129 .slot_complete = slot_complete_v3_hw,
2130 .phys_init = phys_init_v3_hw,
2131 .phy_start = start_phy_v3_hw,
2132 .phy_disable = disable_phy_v3_hw,
2133 .phy_hard_reset = phy_hard_reset_v3_hw,
2134 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
2135 .phy_set_linkrate = phy_set_linkrate_v3_hw,
2136 .dereg_device = dereg_device_v3_hw,
2137 .soft_reset = soft_reset_v3_hw,
2138 .get_phys_state = get_phys_state_v3_hw,
2139 .get_events = phy_get_events_v3_hw,
2140 .write_gpio = write_gpio_v3_hw,
2141 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
2142 };
2143
2144 static struct Scsi_Host *
2145 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
2146 {
2147 struct Scsi_Host *shost;
2148 struct hisi_hba *hisi_hba;
2149 struct device *dev = &pdev->dev;
2150
2151 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
2152 if (!shost) {
2153 dev_err(dev, "shost alloc failed\n");
2154 return NULL;
2155 }
2156 hisi_hba = shost_priv(shost);
2157
2158 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
2159 hisi_hba->hw = &hisi_sas_v3_hw;
2160 hisi_hba->pci_dev = pdev;
2161 hisi_hba->dev = dev;
2162 hisi_hba->shost = shost;
2163 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
2164
2165 timer_setup(&hisi_hba->timer, NULL, 0);
2166
2167 if (hisi_sas_get_fw_info(hisi_hba) < 0)
2168 goto err_out;
2169
2170 if (hisi_sas_alloc(hisi_hba, shost)) {
2171 hisi_sas_free(hisi_hba);
2172 goto err_out;
2173 }
2174
2175 return shost;
2176 err_out:
2177 scsi_host_put(shost);
2178 dev_err(dev, "shost alloc failed\n");
2179 return NULL;
2180 }
2181
2182 static int
2183 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2184 {
2185 struct Scsi_Host *shost;
2186 struct hisi_hba *hisi_hba;
2187 struct device *dev = &pdev->dev;
2188 struct asd_sas_phy **arr_phy;
2189 struct asd_sas_port **arr_port;
2190 struct sas_ha_struct *sha;
2191 int rc, phy_nr, port_nr, i;
2192
2193 rc = pci_enable_device(pdev);
2194 if (rc)
2195 goto err_out;
2196
2197 pci_set_master(pdev);
2198
2199 rc = pci_request_regions(pdev, DRV_NAME);
2200 if (rc)
2201 goto err_out_disable_device;
2202
2203 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
2204 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
2205 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2206 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2207 dev_err(dev, "No usable DMA addressing method\n");
2208 rc = -EIO;
2209 goto err_out_regions;
2210 }
2211 }
2212
2213 shost = hisi_sas_shost_alloc_pci(pdev);
2214 if (!shost) {
2215 rc = -ENOMEM;
2216 goto err_out_regions;
2217 }
2218
2219 sha = SHOST_TO_SAS_HA(shost);
2220 hisi_hba = shost_priv(shost);
2221 dev_set_drvdata(dev, sha);
2222
2223 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
2224 if (!hisi_hba->regs) {
2225 dev_err(dev, "cannot map register.\n");
2226 rc = -ENOMEM;
2227 goto err_out_ha;
2228 }
2229
2230 phy_nr = port_nr = hisi_hba->n_phy;
2231
2232 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
2233 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
2234 if (!arr_phy || !arr_port) {
2235 rc = -ENOMEM;
2236 goto err_out_ha;
2237 }
2238
2239 sha->sas_phy = arr_phy;
2240 sha->sas_port = arr_port;
2241 sha->core.shost = shost;
2242 sha->lldd_ha = hisi_hba;
2243
2244 shost->transportt = hisi_sas_stt;
2245 shost->max_id = HISI_SAS_MAX_DEVICES;
2246 shost->max_lun = ~0;
2247 shost->max_channel = 1;
2248 shost->max_cmd_len = 16;
2249 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
2250 shost->can_queue = hisi_hba->hw->max_command_entries;
2251 shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
2252
2253 sha->sas_ha_name = DRV_NAME;
2254 sha->dev = dev;
2255 sha->lldd_module = THIS_MODULE;
2256 sha->sas_addr = &hisi_hba->sas_addr[0];
2257 sha->num_phys = hisi_hba->n_phy;
2258 sha->core.shost = hisi_hba->shost;
2259
2260 for (i = 0; i < hisi_hba->n_phy; i++) {
2261 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
2262 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
2263 }
2264
2265 hisi_sas_init_add(hisi_hba);
2266
2267 rc = scsi_add_host(shost, dev);
2268 if (rc)
2269 goto err_out_ha;
2270
2271 rc = sas_register_ha(sha);
2272 if (rc)
2273 goto err_out_register_ha;
2274
2275 rc = hisi_hba->hw->hw_init(hisi_hba);
2276 if (rc)
2277 goto err_out_register_ha;
2278
2279 scsi_scan_host(shost);
2280
2281 return 0;
2282
2283 err_out_register_ha:
2284 scsi_remove_host(shost);
2285 err_out_ha:
2286 scsi_host_put(shost);
2287 err_out_regions:
2288 pci_release_regions(pdev);
2289 err_out_disable_device:
2290 pci_disable_device(pdev);
2291 err_out:
2292 return rc;
2293 }
2294
2295 static void
2296 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
2297 {
2298 int i;
2299
2300 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2301 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2302 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2303 for (i = 0; i < hisi_hba->queue_count; i++) {
2304 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2305
2306 free_irq(pci_irq_vector(pdev, i+16), cq);
2307 }
2308 pci_free_irq_vectors(pdev);
2309 }
2310
2311 static void hisi_sas_v3_remove(struct pci_dev *pdev)
2312 {
2313 struct device *dev = &pdev->dev;
2314 struct sas_ha_struct *sha = dev_get_drvdata(dev);
2315 struct hisi_hba *hisi_hba = sha->lldd_ha;
2316 struct Scsi_Host *shost = sha->core.shost;
2317
2318 if (timer_pending(&hisi_hba->timer))
2319 del_timer(&hisi_hba->timer);
2320
2321 sas_unregister_ha(sha);
2322 sas_remove_host(sha->core.shost);
2323
2324 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
2325 hisi_sas_kill_tasklets(hisi_hba);
2326 pci_release_regions(pdev);
2327 pci_disable_device(pdev);
2328 hisi_sas_free(hisi_hba);
2329 scsi_host_put(shost);
2330 }
2331
2332 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = {
2333 { .irq_msk = BIT(19), .msg = "HILINK_INT" },
2334 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" },
2335 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" },
2336 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" },
2337 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" },
2338 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" },
2339 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" },
2340 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" },
2341 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" },
2342 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" },
2343 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" },
2344 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" },
2345 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" },
2346 };
2347
2348 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = {
2349 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" },
2350 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" },
2351 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" },
2352 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" },
2353 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" },
2354 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" },
2355 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" },
2356 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" },
2357 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" },
2358 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" },
2359 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" },
2360 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" },
2361 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" },
2362 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" },
2363 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" },
2364 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" },
2365 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" },
2366 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" },
2367 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" },
2368 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" },
2369 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" },
2370 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" },
2371 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" },
2372 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" },
2373 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" },
2374 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" },
2375 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" },
2376 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" },
2377 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" },
2378 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" },
2379 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" },
2380 };
2381
2382 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = {
2383 { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" },
2384 { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" },
2385 { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" },
2386 { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" },
2387 { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" },
2388 { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" },
2389 { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" },
2390 { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" },
2391 { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" },
2392 { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" },
2393 { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" },
2394 { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" },
2395 { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" },
2396 { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" },
2397 { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" },
2398 { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" },
2399 { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" },
2400 { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" },
2401 { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" },
2402 { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" },
2403 };
2404
2405 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba)
2406 {
2407 struct device *dev = hisi_hba->dev;
2408 const struct hisi_sas_hw_error *ras_error;
2409 bool need_reset = false;
2410 u32 irq_value;
2411 int i;
2412
2413 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0);
2414 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) {
2415 ras_error = &sas_ras_intr0_nfe[i];
2416 if (ras_error->irq_msk & irq_value) {
2417 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n",
2418 ras_error->msg, irq_value);
2419 need_reset = true;
2420 }
2421 }
2422 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value);
2423
2424 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1);
2425 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) {
2426 ras_error = &sas_ras_intr1_nfe[i];
2427 if (ras_error->irq_msk & irq_value) {
2428 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n",
2429 ras_error->msg, irq_value);
2430 need_reset = true;
2431 }
2432 }
2433 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value);
2434
2435 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2);
2436 for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) {
2437 ras_error = &sas_ras_intr2_nfe[i];
2438 if (ras_error->irq_msk & irq_value) {
2439 dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n",
2440 ras_error->msg, irq_value);
2441 need_reset = true;
2442 }
2443 }
2444 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value);
2445
2446 return need_reset;
2447 }
2448
2449 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev,
2450 pci_channel_state_t state)
2451 {
2452 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2453 struct hisi_hba *hisi_hba = sha->lldd_ha;
2454 struct device *dev = hisi_hba->dev;
2455
2456 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state);
2457 if (state == pci_channel_io_perm_failure)
2458 return PCI_ERS_RESULT_DISCONNECT;
2459
2460 if (process_non_fatal_error_v3_hw(hisi_hba))
2461 return PCI_ERS_RESULT_NEED_RESET;
2462
2463 return PCI_ERS_RESULT_CAN_RECOVER;
2464 }
2465
2466 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev)
2467 {
2468 return PCI_ERS_RESULT_RECOVERED;
2469 }
2470
2471 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev)
2472 {
2473 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2474 struct hisi_hba *hisi_hba = sha->lldd_ha;
2475 struct device *dev = hisi_hba->dev;
2476 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r);
2477
2478 dev_info(dev, "PCI error: slot reset callback!!\n");
2479 queue_work(hisi_hba->wq, &r.work);
2480 wait_for_completion(r.completion);
2481 if (r.done)
2482 return PCI_ERS_RESULT_RECOVERED;
2483
2484 return PCI_ERS_RESULT_DISCONNECT;
2485 }
2486
2487 enum {
2488 /* instances of the controller */
2489 hip08,
2490 };
2491
2492 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state)
2493 {
2494 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2495 struct hisi_hba *hisi_hba = sha->lldd_ha;
2496 struct device *dev = hisi_hba->dev;
2497 struct Scsi_Host *shost = hisi_hba->shost;
2498 u32 device_state;
2499 int rc;
2500
2501 if (!pdev->pm_cap) {
2502 dev_err(dev, "PCI PM not supported\n");
2503 return -ENODEV;
2504 }
2505
2506 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
2507 return -1;
2508
2509 scsi_block_requests(shost);
2510 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2511 flush_workqueue(hisi_hba->wq);
2512
2513 rc = disable_host_v3_hw(hisi_hba);
2514 if (rc) {
2515 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
2516 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2517 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2518 scsi_unblock_requests(shost);
2519 return rc;
2520 }
2521
2522 hisi_sas_init_mem(hisi_hba);
2523
2524 device_state = pci_choose_state(pdev, state);
2525 dev_warn(dev, "entering operating state [D%d]\n",
2526 device_state);
2527 pci_save_state(pdev);
2528 pci_disable_device(pdev);
2529 pci_set_power_state(pdev, device_state);
2530
2531 hisi_sas_release_tasks(hisi_hba);
2532
2533 sas_suspend_ha(sha);
2534 return 0;
2535 }
2536
2537 static int hisi_sas_v3_resume(struct pci_dev *pdev)
2538 {
2539 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2540 struct hisi_hba *hisi_hba = sha->lldd_ha;
2541 struct Scsi_Host *shost = hisi_hba->shost;
2542 struct device *dev = hisi_hba->dev;
2543 unsigned int rc;
2544 u32 device_state = pdev->current_state;
2545
2546 dev_warn(dev, "resuming from operating state [D%d]\n",
2547 device_state);
2548 pci_set_power_state(pdev, PCI_D0);
2549 pci_enable_wake(pdev, PCI_D0, 0);
2550 pci_restore_state(pdev);
2551 rc = pci_enable_device(pdev);
2552 if (rc)
2553 dev_err(dev, "enable device failed during resume (%d)\n", rc);
2554
2555 pci_set_master(pdev);
2556 scsi_unblock_requests(shost);
2557 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2558
2559 sas_prep_resume_ha(sha);
2560 init_reg_v3_hw(hisi_hba);
2561 hisi_hba->hw->phys_init(hisi_hba);
2562 sas_resume_ha(sha);
2563 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2564
2565 return 0;
2566 }
2567
2568 static const struct pci_device_id sas_v3_pci_table[] = {
2569 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
2570 {}
2571 };
2572 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
2573
2574 static const struct pci_error_handlers hisi_sas_err_handler = {
2575 .error_detected = hisi_sas_error_detected_v3_hw,
2576 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw,
2577 .slot_reset = hisi_sas_slot_reset_v3_hw,
2578 };
2579
2580 static struct pci_driver sas_v3_pci_driver = {
2581 .name = DRV_NAME,
2582 .id_table = sas_v3_pci_table,
2583 .probe = hisi_sas_v3_probe,
2584 .remove = hisi_sas_v3_remove,
2585 .suspend = hisi_sas_v3_suspend,
2586 .resume = hisi_sas_v3_resume,
2587 .err_handler = &hisi_sas_err_handler,
2588 };
2589
2590 module_pci_driver(sas_v3_pci_driver);
2591
2592 MODULE_LICENSE("GPL");
2593 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2594 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2595 MODULE_ALIAS("pci:" DRV_NAME);
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