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scsi: hisi_sas: add some print to enhance debugging
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v3_hw.c
1 /*
2 * Copyright (c) 2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 #include "hisi_sas.h"
12 #define DRV_NAME "hisi_sas_v3_hw"
13
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
26 #define ITCT_CLR 0x44
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CFG_1US_TIMER_TRSH 0xcc
55 #define CHNL_INT_STATUS 0x148
56 #define HGC_AXI_FIFO_ERR_INFO 0x154
57 #define AXI_ERR_INFO_OFF 0
58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
59 #define FIFO_ERR_INFO_OFF 8
60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
61 #define INT_COAL_EN 0x19c
62 #define OQ_INT_COAL_TIME 0x1a0
63 #define OQ_INT_COAL_CNT 0x1a4
64 #define ENT_INT_COAL_TIME 0x1a8
65 #define ENT_INT_COAL_CNT 0x1ac
66 #define OQ_INT_SRC 0x1b0
67 #define OQ_INT_SRC_MSK 0x1b4
68 #define ENT_INT_SRC1 0x1b8
69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
73 #define ENT_INT_SRC2 0x1bc
74 #define ENT_INT_SRC3 0x1c0
75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
78 #define ENT_INT_SRC3_AXI_OFF 11
79 #define ENT_INT_SRC3_FIFO_OFF 12
80 #define ENT_INT_SRC3_LM_OFF 14
81 #define ENT_INT_SRC3_ITC_INT_OFF 15
82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
83 #define ENT_INT_SRC3_ABT_OFF 16
84 #define ENT_INT_SRC_MSK1 0x1c4
85 #define ENT_INT_SRC_MSK2 0x1c8
86 #define ENT_INT_SRC_MSK3 0x1cc
87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
89 #define CHNL_ENT_INT_MSK 0x1d4
90 #define HGC_COM_INT_MSK 0x1d8
91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
92 #define SAS_ECC_INTR 0x1e8
93 #define SAS_ECC_INTR_MSK 0x1ec
94 #define HGC_ERR_STAT_EN 0x238
95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
97 #define DLVRY_Q_0_DEPTH 0x268
98 #define DLVRY_Q_0_WR_PTR 0x26c
99 #define DLVRY_Q_0_RD_PTR 0x270
100 #define HYPER_STREAM_ID_EN_CFG 0xc80
101 #define OQ0_INT_SRC_MSK 0xc90
102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
104 #define COMPL_Q_0_DEPTH 0x4e8
105 #define COMPL_Q_0_WR_PTR 0x4ec
106 #define COMPL_Q_0_RD_PTR 0x4f0
107 #define AWQOS_AWCACHE_CFG 0xc84
108 #define ARQOS_ARCACHE_CFG 0xc88
109
110 /* phy registers requiring init */
111 #define PORT_BASE (0x2000)
112 #define PHY_CFG (PORT_BASE + 0x0)
113 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
114 #define PHY_CFG_ENA_OFF 0
115 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
116 #define PHY_CFG_DC_OPT_OFF 2
117 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
118 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
119 #define PHY_CTRL (PORT_BASE + 0x14)
120 #define PHY_CTRL_RESET_OFF 0
121 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
122 #define SL_CFG (PORT_BASE + 0x84)
123 #define SL_CONTROL (PORT_BASE + 0x94)
124 #define SL_CONTROL_NOTIFY_EN_OFF 0
125 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
126 #define SL_CTA_OFF 17
127 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
128 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
129 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
130 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
131 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
132 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
133 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
134 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
135 #define TXID_AUTO (PORT_BASE + 0xb8)
136 #define CT3_OFF 1
137 #define CT3_MSK (0x1 << CT3_OFF)
138 #define TX_HARDRST_OFF 2
139 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
140 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
141 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
142 #define STP_LINK_TIMER (PORT_BASE + 0x120)
143 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
144 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
145 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
146 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
147 #define CHL_INT0 (PORT_BASE + 0x1b4)
148 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
149 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
150 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
151 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
152 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
153 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
154 #define CHL_INT0_NOT_RDY_OFF 4
155 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
156 #define CHL_INT0_PHY_RDY_OFF 5
157 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
158 #define CHL_INT1 (PORT_BASE + 0x1b8)
159 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
160 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
161 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
162 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
163 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
164 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
165 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
166 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
167 #define CHL_INT2 (PORT_BASE + 0x1bc)
168 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
169 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
170 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
171 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
172 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
173 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
174 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
175 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
176 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
177 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
178 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
179 #define DMA_TX_STATUS_BUSY_OFF 0
180 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
181 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
182 #define DMA_RX_STATUS_BUSY_OFF 0
183 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
184 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
185 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
186 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
187 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
188
189 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
190 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
191 #error Max ITCT exceeded
192 #endif
193
194 #define AXI_MASTER_CFG_BASE (0x5000)
195 #define AM_CTRL_GLOBAL (0x0)
196 #define AM_CURR_TRANS_RETURN (0x150)
197
198 #define AM_CFG_MAX_TRANS (0x5010)
199 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
200 #define AXI_CFG (0x5100)
201 #define AM_ROB_ECC_ERR_ADDR (0x510c)
202 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
203 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
204 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
205 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
206
207 /* RAS registers need init */
208 #define RAS_BASE (0x6000)
209 #define SAS_RAS_INTR0 (RAS_BASE)
210 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
211 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
212 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
213
214 /* HW dma structures */
215 /* Delivery queue header */
216 /* dw0 */
217 #define CMD_HDR_ABORT_FLAG_OFF 0
218 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
219 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
220 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
221 #define CMD_HDR_RESP_REPORT_OFF 5
222 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
223 #define CMD_HDR_TLR_CTRL_OFF 6
224 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
225 #define CMD_HDR_PORT_OFF 18
226 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
227 #define CMD_HDR_PRIORITY_OFF 27
228 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
229 #define CMD_HDR_CMD_OFF 29
230 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
231 /* dw1 */
232 #define CMD_HDR_UNCON_CMD_OFF 3
233 #define CMD_HDR_DIR_OFF 5
234 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
235 #define CMD_HDR_RESET_OFF 7
236 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
237 #define CMD_HDR_VDTL_OFF 10
238 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
239 #define CMD_HDR_FRAME_TYPE_OFF 11
240 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
241 #define CMD_HDR_DEV_ID_OFF 16
242 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
243 /* dw2 */
244 #define CMD_HDR_CFL_OFF 0
245 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
246 #define CMD_HDR_NCQ_TAG_OFF 10
247 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
248 #define CMD_HDR_MRFL_OFF 15
249 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
250 #define CMD_HDR_SG_MOD_OFF 24
251 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
252 /* dw3 */
253 #define CMD_HDR_IPTT_OFF 0
254 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
255 /* dw6 */
256 #define CMD_HDR_DIF_SGL_LEN_OFF 0
257 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
258 #define CMD_HDR_DATA_SGL_LEN_OFF 16
259 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
260 /* dw7 */
261 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
262 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
263 #define CMD_HDR_ABORT_IPTT_OFF 16
264 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
265
266 /* Completion header */
267 /* dw0 */
268 #define CMPLT_HDR_CMPLT_OFF 0
269 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
270 #define CMPLT_HDR_ERROR_PHASE_OFF 2
271 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
272 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
273 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
274 #define CMPLT_HDR_ERX_OFF 12
275 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
276 #define CMPLT_HDR_ABORT_STAT_OFF 13
277 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
278 /* abort_stat */
279 #define STAT_IO_NOT_VALID 0x1
280 #define STAT_IO_NO_DEVICE 0x2
281 #define STAT_IO_COMPLETE 0x3
282 #define STAT_IO_ABORTED 0x4
283 /* dw1 */
284 #define CMPLT_HDR_IPTT_OFF 0
285 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
286 #define CMPLT_HDR_DEV_ID_OFF 16
287 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
288 /* dw3 */
289 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
290 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
291
292 /* ITCT header */
293 /* qw0 */
294 #define ITCT_HDR_DEV_TYPE_OFF 0
295 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
296 #define ITCT_HDR_VALID_OFF 2
297 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
298 #define ITCT_HDR_MCR_OFF 5
299 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
300 #define ITCT_HDR_VLN_OFF 9
301 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
302 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
303 #define ITCT_HDR_AWT_CONTINUE_OFF 25
304 #define ITCT_HDR_PORT_ID_OFF 28
305 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
306 /* qw2 */
307 #define ITCT_HDR_INLT_OFF 0
308 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
309 #define ITCT_HDR_RTOLT_OFF 48
310 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
311
312 struct hisi_sas_complete_v3_hdr {
313 __le32 dw0;
314 __le32 dw1;
315 __le32 act;
316 __le32 dw3;
317 };
318
319 struct hisi_sas_err_record_v3 {
320 /* dw0 */
321 __le32 trans_tx_fail_type;
322
323 /* dw1 */
324 __le32 trans_rx_fail_type;
325
326 /* dw2 */
327 __le16 dma_tx_err_type;
328 __le16 sipc_rx_err_type;
329
330 /* dw3 */
331 __le32 dma_rx_err_type;
332 };
333
334 #define RX_DATA_LEN_UNDERFLOW_OFF 6
335 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
336
337 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
338 #define HISI_SAS_MSI_COUNT_V3_HW 32
339
340 enum {
341 HISI_SAS_PHY_PHY_UPDOWN,
342 HISI_SAS_PHY_CHNL_INT,
343 HISI_SAS_PHY_INT_NR
344 };
345
346 #define DIR_NO_DATA 0
347 #define DIR_TO_INI 1
348 #define DIR_TO_DEVICE 2
349 #define DIR_RESERVED 3
350
351 #define CMD_IS_UNCONSTRAINT(cmd) \
352 ((cmd == ATA_CMD_READ_LOG_EXT) || \
353 (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
354 (cmd == ATA_CMD_DEV_RESET))
355
356 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
357 {
358 void __iomem *regs = hisi_hba->regs + off;
359
360 return readl(regs);
361 }
362
363 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
364 {
365 void __iomem *regs = hisi_hba->regs + off;
366
367 return readl_relaxed(regs);
368 }
369
370 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
371 {
372 void __iomem *regs = hisi_hba->regs + off;
373
374 writel(val, regs);
375 }
376
377 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
378 u32 off, u32 val)
379 {
380 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
381
382 writel(val, regs);
383 }
384
385 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
386 int phy_no, u32 off)
387 {
388 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
389
390 return readl(regs);
391 }
392
393 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
394 {
395 int i;
396
397 /* Global registers init */
398 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
399 (u32)((1ULL << hisi_hba->queue_count) - 1));
400 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
401 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
402 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
403 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
404 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
405 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
406 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
407 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
408 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
409 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
410 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
411 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
412 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff);
413 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
414 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
415 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
416 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
417 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
418 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
419 for (i = 0; i < hisi_hba->queue_count; i++)
420 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
421
422 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
423 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE, 0x30000);
424
425 for (i = 0; i < hisi_hba->n_phy; i++) {
426 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x801);
427 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
428 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
429 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
430 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
431 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff87ffff);
432 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
433 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
434 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
435 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
436 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
437 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
438 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
439 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199b4fa);
440 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG,
441 0xa03e8);
442 hisi_sas_phy_write32(hisi_hba, i, SAS_STP_CON_TIMER_CFG,
443 0xa03e8);
444 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER,
445 0x7f7a120);
446 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER,
447 0x2a0a80);
448 }
449 for (i = 0; i < hisi_hba->queue_count; i++) {
450 /* Delivery queue */
451 hisi_sas_write32(hisi_hba,
452 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
453 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
454
455 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
456 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
457
458 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
459 HISI_SAS_QUEUE_SLOTS);
460
461 /* Completion queue */
462 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
463 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
464
465 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
466 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
467
468 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
469 HISI_SAS_QUEUE_SLOTS);
470 }
471
472 /* itct */
473 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
474 lower_32_bits(hisi_hba->itct_dma));
475
476 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
477 upper_32_bits(hisi_hba->itct_dma));
478
479 /* iost */
480 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
481 lower_32_bits(hisi_hba->iost_dma));
482
483 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
484 upper_32_bits(hisi_hba->iost_dma));
485
486 /* breakpoint */
487 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
488 lower_32_bits(hisi_hba->breakpoint_dma));
489
490 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
491 upper_32_bits(hisi_hba->breakpoint_dma));
492
493 /* SATA broken msg */
494 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
495 lower_32_bits(hisi_hba->sata_breakpoint_dma));
496
497 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
498 upper_32_bits(hisi_hba->sata_breakpoint_dma));
499
500 /* SATA initial fis */
501 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
502 lower_32_bits(hisi_hba->initial_fis_dma));
503
504 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
505 upper_32_bits(hisi_hba->initial_fis_dma));
506
507 /* RAS registers init */
508 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
509 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
510 }
511
512 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
513 {
514 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
515
516 cfg &= ~PHY_CFG_DC_OPT_MSK;
517 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
518 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
519 }
520
521 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
522 {
523 struct sas_identify_frame identify_frame;
524 u32 *identify_buffer;
525
526 memset(&identify_frame, 0, sizeof(identify_frame));
527 identify_frame.dev_type = SAS_END_DEVICE;
528 identify_frame.frame_type = 0;
529 identify_frame._un1 = 1;
530 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
531 identify_frame.target_bits = SAS_PROTOCOL_NONE;
532 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
533 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
534 identify_frame.phy_id = phy_no;
535 identify_buffer = (u32 *)(&identify_frame);
536
537 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
538 __swab32(identify_buffer[0]));
539 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
540 __swab32(identify_buffer[1]));
541 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
542 __swab32(identify_buffer[2]));
543 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
544 __swab32(identify_buffer[3]));
545 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
546 __swab32(identify_buffer[4]));
547 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
548 __swab32(identify_buffer[5]));
549 }
550
551 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
552 struct hisi_sas_device *sas_dev)
553 {
554 struct domain_device *device = sas_dev->sas_device;
555 struct device *dev = hisi_hba->dev;
556 u64 qw0, device_id = sas_dev->device_id;
557 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
558 struct domain_device *parent_dev = device->parent;
559 struct asd_sas_port *sas_port = device->port;
560 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
561
562 memset(itct, 0, sizeof(*itct));
563
564 /* qw0 */
565 qw0 = 0;
566 switch (sas_dev->dev_type) {
567 case SAS_END_DEVICE:
568 case SAS_EDGE_EXPANDER_DEVICE:
569 case SAS_FANOUT_EXPANDER_DEVICE:
570 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
571 break;
572 case SAS_SATA_DEV:
573 case SAS_SATA_PENDING:
574 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
575 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
576 else
577 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
578 break;
579 default:
580 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
581 sas_dev->dev_type);
582 }
583
584 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
585 (device->linkrate << ITCT_HDR_MCR_OFF) |
586 (1 << ITCT_HDR_VLN_OFF) |
587 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
588 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
589 (port->id << ITCT_HDR_PORT_ID_OFF));
590 itct->qw0 = cpu_to_le64(qw0);
591
592 /* qw1 */
593 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
594 itct->sas_addr = __swab64(itct->sas_addr);
595
596 /* qw2 */
597 if (!dev_is_sata(device))
598 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
599 (0x1ULL << ITCT_HDR_RTOLT_OFF));
600 }
601
602 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba,
603 struct hisi_sas_device *sas_dev)
604 {
605 DECLARE_COMPLETION_ONSTACK(completion);
606 u64 dev_id = sas_dev->device_id;
607 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
608 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
609
610 sas_dev->completion = &completion;
611
612 /* clear the itct interrupt state */
613 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
614 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
615 ENT_INT_SRC3_ITC_INT_MSK);
616
617 /* clear the itct table*/
618 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
619 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
620
621 wait_for_completion(sas_dev->completion);
622 memset(itct, 0, sizeof(struct hisi_sas_itct));
623 }
624
625 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
626 struct domain_device *device)
627 {
628 struct hisi_sas_slot *slot, *slot2;
629 struct hisi_sas_device *sas_dev = device->lldd_dev;
630 u32 cfg_abt_set_query_iptt;
631
632 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
633 CFG_ABT_SET_QUERY_IPTT);
634 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
635 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
636 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
637 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
638 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
639 cfg_abt_set_query_iptt);
640 }
641 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
642 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
643 cfg_abt_set_query_iptt);
644 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
645 1 << CFG_ABT_SET_IPTT_DONE_OFF);
646 }
647
648 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
649 {
650 struct device *dev = hisi_hba->dev;
651 int ret;
652 u32 val;
653
654 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
655
656 /* Disable all of the PHYs */
657 hisi_sas_stop_phys(hisi_hba);
658 udelay(50);
659
660 /* Ensure axi bus idle */
661 ret = readl_poll_timeout(hisi_hba->regs + AXI_CFG, val, !val,
662 20000, 1000000);
663 if (ret) {
664 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
665 return -EIO;
666 }
667
668 if (ACPI_HANDLE(dev)) {
669 acpi_status s;
670
671 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
672 if (ACPI_FAILURE(s)) {
673 dev_err(dev, "Reset failed\n");
674 return -EIO;
675 }
676 } else
677 dev_err(dev, "no reset method!\n");
678
679 return 0;
680 }
681
682 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
683 {
684 struct device *dev = hisi_hba->dev;
685 int rc;
686
687 rc = reset_hw_v3_hw(hisi_hba);
688 if (rc) {
689 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
690 return rc;
691 }
692
693 msleep(100);
694 init_reg_v3_hw(hisi_hba);
695
696 return 0;
697 }
698
699 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
700 {
701 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
702
703 cfg |= PHY_CFG_ENA_MSK;
704 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
705 }
706
707 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
708 {
709 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
710
711 cfg &= ~PHY_CFG_ENA_MSK;
712 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
713 }
714
715 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
716 {
717 config_id_frame_v3_hw(hisi_hba, phy_no);
718 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
719 enable_phy_v3_hw(hisi_hba, phy_no);
720 }
721
722 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
723 {
724 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
725 u32 txid_auto;
726
727 disable_phy_v3_hw(hisi_hba, phy_no);
728 if (phy->identify.device_type == SAS_END_DEVICE) {
729 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
730 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
731 txid_auto | TX_HARDRST_MSK);
732 }
733 msleep(100);
734 start_phy_v3_hw(hisi_hba, phy_no);
735 }
736
737 enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
738 {
739 return SAS_LINK_RATE_12_0_GBPS;
740 }
741
742 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
743 {
744 int i;
745
746 for (i = 0; i < hisi_hba->n_phy; i++) {
747 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
748 struct asd_sas_phy *sas_phy = &phy->sas_phy;
749
750 if (!sas_phy->phy->enabled)
751 continue;
752
753 start_phy_v3_hw(hisi_hba, i);
754 }
755 }
756
757 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
758 {
759 u32 sl_control;
760
761 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
762 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
763 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
764 msleep(1);
765 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
766 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
767 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
768 }
769
770 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
771 {
772 int i, bitmap = 0;
773 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
774 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
775
776 for (i = 0; i < hisi_hba->n_phy; i++)
777 if (phy_state & BIT(i))
778 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
779 bitmap |= BIT(i);
780
781 return bitmap;
782 }
783
784 /**
785 * The callpath to this function and upto writing the write
786 * queue pointer should be safe from interruption.
787 */
788 static int
789 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
790 {
791 struct device *dev = hisi_hba->dev;
792 int queue = dq->id;
793 u32 r, w;
794
795 w = dq->wr_point;
796 r = hisi_sas_read32_relaxed(hisi_hba,
797 DLVRY_Q_0_RD_PTR + (queue * 0x14));
798 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
799 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
800 queue, r, w);
801 return -EAGAIN;
802 }
803
804 return 0;
805 }
806
807 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
808 {
809 struct hisi_hba *hisi_hba = dq->hisi_hba;
810 int dlvry_queue = dq->slot_prep->dlvry_queue;
811 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
812
813 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
814 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
815 dq->wr_point);
816 }
817
818 static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
819 struct hisi_sas_slot *slot,
820 struct hisi_sas_cmd_hdr *hdr,
821 struct scatterlist *scatter,
822 int n_elem)
823 {
824 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
825 struct device *dev = hisi_hba->dev;
826 struct scatterlist *sg;
827 int i;
828
829 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
830 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
831 n_elem);
832 return -EINVAL;
833 }
834
835 for_each_sg(scatter, sg, n_elem, i) {
836 struct hisi_sas_sge *entry = &sge_page->sge[i];
837
838 entry->addr = cpu_to_le64(sg_dma_address(sg));
839 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
840 entry->data_len = cpu_to_le32(sg_dma_len(sg));
841 entry->data_off = 0;
842 }
843
844 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
845
846 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
847
848 return 0;
849 }
850
851 static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
852 struct hisi_sas_slot *slot, int is_tmf,
853 struct hisi_sas_tmf_task *tmf)
854 {
855 struct sas_task *task = slot->task;
856 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
857 struct domain_device *device = task->dev;
858 struct hisi_sas_device *sas_dev = device->lldd_dev;
859 struct hisi_sas_port *port = slot->port;
860 struct sas_ssp_task *ssp_task = &task->ssp_task;
861 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
862 int has_data = 0, rc, priority = is_tmf;
863 u8 *buf_cmd;
864 u32 dw1 = 0, dw2 = 0;
865
866 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
867 (2 << CMD_HDR_TLR_CTRL_OFF) |
868 (port->id << CMD_HDR_PORT_OFF) |
869 (priority << CMD_HDR_PRIORITY_OFF) |
870 (1 << CMD_HDR_CMD_OFF)); /* ssp */
871
872 dw1 = 1 << CMD_HDR_VDTL_OFF;
873 if (is_tmf) {
874 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
875 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
876 } else {
877 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
878 switch (scsi_cmnd->sc_data_direction) {
879 case DMA_TO_DEVICE:
880 has_data = 1;
881 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
882 break;
883 case DMA_FROM_DEVICE:
884 has_data = 1;
885 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
886 break;
887 default:
888 dw1 &= ~CMD_HDR_DIR_MSK;
889 }
890 }
891
892 /* map itct entry */
893 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
894 hdr->dw1 = cpu_to_le32(dw1);
895
896 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
897 + 3) / 4) << CMD_HDR_CFL_OFF) |
898 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
899 (2 << CMD_HDR_SG_MOD_OFF);
900 hdr->dw2 = cpu_to_le32(dw2);
901 hdr->transfer_tags = cpu_to_le32(slot->idx);
902
903 if (has_data) {
904 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
905 slot->n_elem);
906 if (rc)
907 return rc;
908 }
909
910 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
911 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
912 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
913
914 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
915 sizeof(struct ssp_frame_hdr);
916
917 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
918 if (!is_tmf) {
919 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
920 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
921 } else {
922 buf_cmd[10] = tmf->tmf;
923 switch (tmf->tmf) {
924 case TMF_ABORT_TASK:
925 case TMF_QUERY_TASK:
926 buf_cmd[12] =
927 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
928 buf_cmd[13] =
929 tmf->tag_of_task_to_be_managed & 0xff;
930 break;
931 default:
932 break;
933 }
934 }
935
936 return 0;
937 }
938
939 static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
940 struct hisi_sas_slot *slot)
941 {
942 struct sas_task *task = slot->task;
943 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
944 struct domain_device *device = task->dev;
945 struct device *dev = hisi_hba->dev;
946 struct hisi_sas_port *port = slot->port;
947 struct scatterlist *sg_req, *sg_resp;
948 struct hisi_sas_device *sas_dev = device->lldd_dev;
949 dma_addr_t req_dma_addr;
950 unsigned int req_len, resp_len;
951 int elem, rc;
952
953 /*
954 * DMA-map SMP request, response buffers
955 */
956 /* req */
957 sg_req = &task->smp_task.smp_req;
958 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
959 if (!elem)
960 return -ENOMEM;
961 req_len = sg_dma_len(sg_req);
962 req_dma_addr = sg_dma_address(sg_req);
963
964 /* resp */
965 sg_resp = &task->smp_task.smp_resp;
966 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
967 if (!elem) {
968 rc = -ENOMEM;
969 goto err_out_req;
970 }
971 resp_len = sg_dma_len(sg_resp);
972 if ((req_len & 0x3) || (resp_len & 0x3)) {
973 rc = -EINVAL;
974 goto err_out_resp;
975 }
976
977 /* create header */
978 /* dw0 */
979 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
980 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
981 (2 << CMD_HDR_CMD_OFF)); /* smp */
982
983 /* map itct entry */
984 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
985 (1 << CMD_HDR_FRAME_TYPE_OFF) |
986 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
987
988 /* dw2 */
989 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
990 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
991 CMD_HDR_MRFL_OFF));
992
993 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
994
995 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
996 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
997
998 return 0;
999
1000 err_out_resp:
1001 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1002 DMA_FROM_DEVICE);
1003 err_out_req:
1004 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1005 DMA_TO_DEVICE);
1006 return rc;
1007 }
1008
1009 static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1010 struct hisi_sas_slot *slot)
1011 {
1012 struct sas_task *task = slot->task;
1013 struct domain_device *device = task->dev;
1014 struct domain_device *parent_dev = device->parent;
1015 struct hisi_sas_device *sas_dev = device->lldd_dev;
1016 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1017 struct asd_sas_port *sas_port = device->port;
1018 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1019 u8 *buf_cmd;
1020 int has_data = 0, rc = 0, hdr_tag = 0;
1021 u32 dw1 = 0, dw2 = 0;
1022
1023 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1024 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1025 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1026 else
1027 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1028
1029 switch (task->data_dir) {
1030 case DMA_TO_DEVICE:
1031 has_data = 1;
1032 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1033 break;
1034 case DMA_FROM_DEVICE:
1035 has_data = 1;
1036 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1037 break;
1038 default:
1039 dw1 &= ~CMD_HDR_DIR_MSK;
1040 }
1041
1042 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1043 (task->ata_task.fis.control & ATA_SRST))
1044 dw1 |= 1 << CMD_HDR_RESET_OFF;
1045
1046 dw1 |= (hisi_sas_get_ata_protocol(
1047 task->ata_task.fis.command, task->data_dir))
1048 << CMD_HDR_FRAME_TYPE_OFF;
1049 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1050
1051 if (CMD_IS_UNCONSTRAINT(task->ata_task.fis.command))
1052 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1053
1054 hdr->dw1 = cpu_to_le32(dw1);
1055
1056 /* dw2 */
1057 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
1058 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1059 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1060 }
1061
1062 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1063 2 << CMD_HDR_SG_MOD_OFF;
1064 hdr->dw2 = cpu_to_le32(dw2);
1065
1066 /* dw3 */
1067 hdr->transfer_tags = cpu_to_le32(slot->idx);
1068
1069 if (has_data) {
1070 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1071 slot->n_elem);
1072 if (rc)
1073 return rc;
1074 }
1075
1076 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1077 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1078 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1079
1080 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1081
1082 if (likely(!task->ata_task.device_control_reg_update))
1083 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1084 /* fill in command FIS */
1085 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1086
1087 return 0;
1088 }
1089
1090 static int prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1091 struct hisi_sas_slot *slot,
1092 int device_id, int abort_flag, int tag_to_abort)
1093 {
1094 struct sas_task *task = slot->task;
1095 struct domain_device *dev = task->dev;
1096 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1097 struct hisi_sas_port *port = slot->port;
1098
1099 /* dw0 */
1100 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1101 (port->id << CMD_HDR_PORT_OFF) |
1102 ((dev_is_sata(dev) ? 1:0)
1103 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1104 (abort_flag
1105 << CMD_HDR_ABORT_FLAG_OFF));
1106
1107 /* dw1 */
1108 hdr->dw1 = cpu_to_le32(device_id
1109 << CMD_HDR_DEV_ID_OFF);
1110
1111 /* dw7 */
1112 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1113 hdr->transfer_tags = cpu_to_le32(slot->idx);
1114
1115 return 0;
1116 }
1117
1118 static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1119 {
1120 int i, res = 0;
1121 u32 context, port_id, link_rate, hard_phy_linkrate;
1122 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1123 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1124 struct device *dev = hisi_hba->dev;
1125
1126 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1127
1128 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1129 port_id = (port_id >> (4 * phy_no)) & 0xf;
1130 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1131 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1132
1133 if (port_id == 0xf) {
1134 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1135 res = IRQ_NONE;
1136 goto end;
1137 }
1138 sas_phy->linkrate = link_rate;
1139 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1140 HARD_PHY_LINKRATE);
1141 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1142 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1143 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1144
1145 /* Check for SATA dev */
1146 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1147 if (context & (1 << phy_no)) {
1148 struct hisi_sas_initial_fis *initial_fis;
1149 struct dev_to_host_fis *fis;
1150 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1151
1152 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1153 initial_fis = &hisi_hba->initial_fis[phy_no];
1154 fis = &initial_fis->fis;
1155 sas_phy->oob_mode = SATA_OOB_MODE;
1156 attached_sas_addr[0] = 0x50;
1157 attached_sas_addr[7] = phy_no;
1158 memcpy(sas_phy->attached_sas_addr,
1159 attached_sas_addr,
1160 SAS_ADDR_SIZE);
1161 memcpy(sas_phy->frame_rcvd, fis,
1162 sizeof(struct dev_to_host_fis));
1163 phy->phy_type |= PORT_TYPE_SATA;
1164 phy->identify.device_type = SAS_SATA_DEV;
1165 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1166 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1167 } else {
1168 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1169 struct sas_identify_frame *id =
1170 (struct sas_identify_frame *)frame_rcvd;
1171
1172 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1173 for (i = 0; i < 6; i++) {
1174 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1175 RX_IDAF_DWORD0 + (i * 4));
1176 frame_rcvd[i] = __swab32(idaf);
1177 }
1178 sas_phy->oob_mode = SAS_OOB_MODE;
1179 memcpy(sas_phy->attached_sas_addr,
1180 &id->sas_addr,
1181 SAS_ADDR_SIZE);
1182 phy->phy_type |= PORT_TYPE_SAS;
1183 phy->identify.device_type = id->dev_type;
1184 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1185 if (phy->identify.device_type == SAS_END_DEVICE)
1186 phy->identify.target_port_protocols =
1187 SAS_PROTOCOL_SSP;
1188 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1189 phy->identify.target_port_protocols =
1190 SAS_PROTOCOL_SMP;
1191 }
1192
1193 phy->port_id = port_id;
1194 phy->phy_attached = 1;
1195 queue_work(hisi_hba->wq, &phy->phyup_ws);
1196
1197 end:
1198 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1199 CHL_INT0_SL_PHY_ENABLE_MSK);
1200 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1201
1202 return res;
1203 }
1204
1205 static int phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1206 {
1207 u32 phy_state, sl_ctrl, txid_auto;
1208 struct device *dev = hisi_hba->dev;
1209
1210 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1211
1212 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1213 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1214 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1215
1216 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1217 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1218 sl_ctrl&(~SL_CTA_MSK));
1219
1220 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1221 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1222 txid_auto | CT3_MSK);
1223
1224 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1225 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1226
1227 return 0;
1228 }
1229
1230 static void phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1231 {
1232 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1233 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1234 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1235
1236 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1237 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1238 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1239 CHL_INT0_SL_RX_BCST_ACK_MSK);
1240 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1241 }
1242
1243 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1244 {
1245 struct hisi_hba *hisi_hba = p;
1246 u32 irq_msk;
1247 int phy_no = 0;
1248 irqreturn_t res = IRQ_NONE;
1249
1250 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1251 & 0x11111111;
1252 while (irq_msk) {
1253 if (irq_msk & 1) {
1254 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1255 CHL_INT0);
1256 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1257 int rdy = phy_state & (1 << phy_no);
1258
1259 if (rdy) {
1260 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1261 /* phy up */
1262 if (phy_up_v3_hw(phy_no, hisi_hba)
1263 == IRQ_HANDLED)
1264 res = IRQ_HANDLED;
1265 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1266 /* phy bcast */
1267 phy_bcast_v3_hw(phy_no, hisi_hba);
1268 } else {
1269 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1270 /* phy down */
1271 if (phy_down_v3_hw(phy_no, hisi_hba)
1272 == IRQ_HANDLED)
1273 res = IRQ_HANDLED;
1274 }
1275 }
1276 irq_msk >>= 4;
1277 phy_no++;
1278 }
1279
1280 return res;
1281 }
1282
1283 static const struct hisi_sas_hw_error port_axi_error[] = {
1284 {
1285 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1286 .msg = "dma_tx_axi_wr_err",
1287 },
1288 {
1289 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1290 .msg = "dma_tx_axi_rd_err",
1291 },
1292 {
1293 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1294 .msg = "dma_rx_axi_wr_err",
1295 },
1296 {
1297 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1298 .msg = "dma_rx_axi_rd_err",
1299 },
1300 };
1301
1302 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1303 {
1304 struct hisi_hba *hisi_hba = p;
1305 struct device *dev = hisi_hba->dev;
1306 u32 ent_msk, ent_tmp, irq_msk;
1307 int phy_no = 0;
1308
1309 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1310 ent_tmp = ent_msk;
1311 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1312 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1313
1314 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1315 & 0xeeeeeeee;
1316
1317 while (irq_msk) {
1318 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1319 CHL_INT0);
1320 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1321 CHL_INT1);
1322 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1323 CHL_INT2);
1324
1325 if ((irq_msk & (4 << (phy_no * 4))) &&
1326 irq_value1) {
1327 int i;
1328
1329 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1330 const struct hisi_sas_hw_error *error =
1331 &port_axi_error[i];
1332
1333 if (!(irq_value1 & error->irq_msk))
1334 continue;
1335
1336 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1337 error->msg, phy_no, irq_value1);
1338 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1339 }
1340
1341 hisi_sas_phy_write32(hisi_hba, phy_no,
1342 CHL_INT1, irq_value1);
1343 }
1344
1345 if (irq_msk & (8 << (phy_no * 4)) && irq_value2)
1346 hisi_sas_phy_write32(hisi_hba, phy_no,
1347 CHL_INT2, irq_value2);
1348
1349
1350 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1351 hisi_sas_phy_write32(hisi_hba, phy_no,
1352 CHL_INT0, irq_value0
1353 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1354 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1355 & (~CHL_INT0_NOT_RDY_MSK));
1356 }
1357 irq_msk &= ~(0xe << (phy_no * 4));
1358 phy_no++;
1359 }
1360
1361 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1362
1363 return IRQ_HANDLED;
1364 }
1365
1366 static const struct hisi_sas_hw_error axi_error[] = {
1367 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1368 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1369 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1370 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1371 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1372 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1373 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1374 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1375 {},
1376 };
1377
1378 static const struct hisi_sas_hw_error fifo_error[] = {
1379 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
1380 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
1381 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1382 { .msk = BIT(11), .msg = "CMDP_FIFO" },
1383 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1384 {},
1385 };
1386
1387 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1388 {
1389 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1390 .msg = "write pointer and depth",
1391 },
1392 {
1393 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
1394 .msg = "iptt no match slot",
1395 },
1396 {
1397 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
1398 .msg = "read pointer and depth",
1399 },
1400 {
1401 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
1402 .reg = HGC_AXI_FIFO_ERR_INFO,
1403 .sub = axi_error,
1404 },
1405 {
1406 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
1407 .reg = HGC_AXI_FIFO_ERR_INFO,
1408 .sub = fifo_error,
1409 },
1410 {
1411 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
1412 .msg = "LM add/fetch list",
1413 },
1414 {
1415 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
1416 .msg = "SAS_HGC_ABT fetch LM list",
1417 },
1418 };
1419
1420 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
1421 {
1422 u32 irq_value, irq_msk;
1423 struct hisi_hba *hisi_hba = p;
1424 struct device *dev = hisi_hba->dev;
1425 int i;
1426
1427 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1428 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
1429
1430 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
1431
1432 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
1433 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
1434
1435 if (!(irq_value & error->irq_msk))
1436 continue;
1437
1438 if (error->sub) {
1439 const struct hisi_sas_hw_error *sub = error->sub;
1440 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
1441
1442 for (; sub->msk || sub->msg; sub++) {
1443 if (!(err_value & sub->msk))
1444 continue;
1445
1446 dev_err(dev, "%s error (0x%x) found!\n",
1447 sub->msg, irq_value);
1448 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1449 }
1450 } else {
1451 dev_err(dev, "%s error (0x%x) found!\n",
1452 error->msg, irq_value);
1453 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1454 }
1455 }
1456
1457 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
1458 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
1459 u32 dev_id = reg_val & ITCT_DEV_MSK;
1460 struct hisi_sas_device *sas_dev =
1461 &hisi_hba->devices[dev_id];
1462
1463 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
1464 dev_dbg(dev, "clear ITCT ok\n");
1465 complete(sas_dev->completion);
1466 }
1467
1468 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
1469 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
1470
1471 return IRQ_HANDLED;
1472 }
1473
1474 static void
1475 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1476 struct hisi_sas_slot *slot)
1477 {
1478 struct task_status_struct *ts = &task->task_status;
1479 struct hisi_sas_complete_v3_hdr *complete_queue =
1480 hisi_hba->complete_hdr[slot->cmplt_queue];
1481 struct hisi_sas_complete_v3_hdr *complete_hdr =
1482 &complete_queue[slot->cmplt_queue_slot];
1483 struct hisi_sas_err_record_v3 *record =
1484 hisi_sas_status_buf_addr_mem(slot);
1485 u32 dma_rx_err_type = record->dma_rx_err_type;
1486 u32 trans_tx_fail_type = record->trans_tx_fail_type;
1487
1488 switch (task->task_proto) {
1489 case SAS_PROTOCOL_SSP:
1490 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1491 ts->residual = trans_tx_fail_type;
1492 ts->stat = SAS_DATA_UNDERRUN;
1493 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1494 ts->stat = SAS_QUEUE_FULL;
1495 slot->abort = 1;
1496 } else {
1497 ts->stat = SAS_OPEN_REJECT;
1498 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1499 }
1500 break;
1501 case SAS_PROTOCOL_SATA:
1502 case SAS_PROTOCOL_STP:
1503 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1504 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1505 ts->residual = trans_tx_fail_type;
1506 ts->stat = SAS_DATA_UNDERRUN;
1507 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1508 ts->stat = SAS_PHY_DOWN;
1509 slot->abort = 1;
1510 } else {
1511 ts->stat = SAS_OPEN_REJECT;
1512 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1513 }
1514 hisi_sas_sata_done(task, slot);
1515 break;
1516 case SAS_PROTOCOL_SMP:
1517 ts->stat = SAM_STAT_CHECK_CONDITION;
1518 break;
1519 default:
1520 break;
1521 }
1522 }
1523
1524 static int
1525 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1526 {
1527 struct sas_task *task = slot->task;
1528 struct hisi_sas_device *sas_dev;
1529 struct device *dev = hisi_hba->dev;
1530 struct task_status_struct *ts;
1531 struct domain_device *device;
1532 enum exec_status sts;
1533 struct hisi_sas_complete_v3_hdr *complete_queue =
1534 hisi_hba->complete_hdr[slot->cmplt_queue];
1535 struct hisi_sas_complete_v3_hdr *complete_hdr =
1536 &complete_queue[slot->cmplt_queue_slot];
1537 int aborted;
1538 unsigned long flags;
1539
1540 if (unlikely(!task || !task->lldd_task || !task->dev))
1541 return -EINVAL;
1542
1543 ts = &task->task_status;
1544 device = task->dev;
1545 sas_dev = device->lldd_dev;
1546
1547 spin_lock_irqsave(&task->task_state_lock, flags);
1548 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1549 task->task_state_flags &=
1550 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1551 spin_unlock_irqrestore(&task->task_state_lock, flags);
1552
1553 memset(ts, 0, sizeof(*ts));
1554 ts->resp = SAS_TASK_COMPLETE;
1555 if (unlikely(aborted)) {
1556 dev_dbg(dev, "slot complete: task(%p) aborted\n", task);
1557 ts->stat = SAS_ABORTED_TASK;
1558 spin_lock_irqsave(&hisi_hba->lock, flags);
1559 hisi_sas_slot_task_free(hisi_hba, task, slot);
1560 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1561 return -1;
1562 }
1563
1564 if (unlikely(!sas_dev)) {
1565 dev_dbg(dev, "slot complete: port has not device\n");
1566 ts->stat = SAS_PHY_DOWN;
1567 goto out;
1568 }
1569
1570 /*
1571 * Use SAS+TMF status codes
1572 */
1573 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1574 >> CMPLT_HDR_ABORT_STAT_OFF) {
1575 case STAT_IO_ABORTED:
1576 /* this IO has been aborted by abort command */
1577 ts->stat = SAS_ABORTED_TASK;
1578 goto out;
1579 case STAT_IO_COMPLETE:
1580 /* internal abort command complete */
1581 ts->stat = TMF_RESP_FUNC_SUCC;
1582 goto out;
1583 case STAT_IO_NO_DEVICE:
1584 ts->stat = TMF_RESP_FUNC_COMPLETE;
1585 goto out;
1586 case STAT_IO_NOT_VALID:
1587 /*
1588 * abort single IO, the controller can't find the IO
1589 */
1590 ts->stat = TMF_RESP_FUNC_FAILED;
1591 goto out;
1592 default:
1593 break;
1594 }
1595
1596 /* check for erroneous completion */
1597 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1598 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
1599
1600 slot_err_v3_hw(hisi_hba, task, slot);
1601 if (ts->stat != SAS_DATA_UNDERRUN)
1602 dev_info(dev, "erroneous completion iptt=%d task=%p "
1603 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
1604 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
1605 slot->idx, task,
1606 complete_hdr->dw0, complete_hdr->dw1,
1607 complete_hdr->act, complete_hdr->dw3,
1608 error_info[0], error_info[1],
1609 error_info[2], error_info[3]);
1610 if (unlikely(slot->abort))
1611 return ts->stat;
1612 goto out;
1613 }
1614
1615 switch (task->task_proto) {
1616 case SAS_PROTOCOL_SSP: {
1617 struct ssp_response_iu *iu =
1618 hisi_sas_status_buf_addr_mem(slot) +
1619 sizeof(struct hisi_sas_err_record);
1620
1621 sas_ssp_task_response(dev, task, iu);
1622 break;
1623 }
1624 case SAS_PROTOCOL_SMP: {
1625 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1626 void *to;
1627
1628 ts->stat = SAM_STAT_GOOD;
1629 to = kmap_atomic(sg_page(sg_resp));
1630
1631 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1632 DMA_FROM_DEVICE);
1633 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1634 DMA_TO_DEVICE);
1635 memcpy(to + sg_resp->offset,
1636 hisi_sas_status_buf_addr_mem(slot) +
1637 sizeof(struct hisi_sas_err_record),
1638 sg_dma_len(sg_resp));
1639 kunmap_atomic(to);
1640 break;
1641 }
1642 case SAS_PROTOCOL_SATA:
1643 case SAS_PROTOCOL_STP:
1644 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1645 ts->stat = SAM_STAT_GOOD;
1646 hisi_sas_sata_done(task, slot);
1647 break;
1648 default:
1649 ts->stat = SAM_STAT_CHECK_CONDITION;
1650 break;
1651 }
1652
1653 if (!slot->port->port_attached) {
1654 dev_warn(dev, "slot complete: port %d has removed\n",
1655 slot->port->sas_port.id);
1656 ts->stat = SAS_PHY_DOWN;
1657 }
1658
1659 out:
1660 spin_lock_irqsave(&task->task_state_lock, flags);
1661 task->task_state_flags |= SAS_TASK_STATE_DONE;
1662 spin_unlock_irqrestore(&task->task_state_lock, flags);
1663 spin_lock_irqsave(&hisi_hba->lock, flags);
1664 hisi_sas_slot_task_free(hisi_hba, task, slot);
1665 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1666 sts = ts->stat;
1667
1668 if (task->task_done)
1669 task->task_done(task);
1670
1671 return sts;
1672 }
1673
1674 static void cq_tasklet_v3_hw(unsigned long val)
1675 {
1676 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1677 struct hisi_hba *hisi_hba = cq->hisi_hba;
1678 struct hisi_sas_slot *slot;
1679 struct hisi_sas_complete_v3_hdr *complete_queue;
1680 u32 rd_point = cq->rd_point, wr_point;
1681 int queue = cq->id;
1682 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
1683
1684 complete_queue = hisi_hba->complete_hdr[queue];
1685
1686 spin_lock(&dq->lock);
1687 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1688 (0x14 * queue));
1689
1690 while (rd_point != wr_point) {
1691 struct hisi_sas_complete_v3_hdr *complete_hdr;
1692 int iptt;
1693
1694 complete_hdr = &complete_queue[rd_point];
1695
1696 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1697 slot = &hisi_hba->slot_info[iptt];
1698 slot->cmplt_queue_slot = rd_point;
1699 slot->cmplt_queue = queue;
1700 slot_complete_v3_hw(hisi_hba, slot);
1701
1702 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1703 rd_point = 0;
1704 }
1705
1706 /* update rd_point */
1707 cq->rd_point = rd_point;
1708 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1709 spin_unlock(&dq->lock);
1710 }
1711
1712 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1713 {
1714 struct hisi_sas_cq *cq = p;
1715 struct hisi_hba *hisi_hba = cq->hisi_hba;
1716 int queue = cq->id;
1717
1718 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1719
1720 tasklet_schedule(&cq->tasklet);
1721
1722 return IRQ_HANDLED;
1723 }
1724
1725 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1726 {
1727 struct device *dev = hisi_hba->dev;
1728 struct pci_dev *pdev = hisi_hba->pci_dev;
1729 int vectors, rc;
1730 int i, k;
1731 int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1732
1733 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1734 max_msi, PCI_IRQ_MSI);
1735 if (vectors < max_msi) {
1736 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1737 return -ENOENT;
1738 }
1739
1740 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1741 int_phy_up_down_bcast_v3_hw, 0,
1742 DRV_NAME " phy", hisi_hba);
1743 if (rc) {
1744 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1745 rc = -ENOENT;
1746 goto free_irq_vectors;
1747 }
1748
1749 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1750 int_chnl_int_v3_hw, 0,
1751 DRV_NAME " channel", hisi_hba);
1752 if (rc) {
1753 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1754 rc = -ENOENT;
1755 goto free_phy_irq;
1756 }
1757
1758 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
1759 fatal_axi_int_v3_hw, 0,
1760 DRV_NAME " fatal", hisi_hba);
1761 if (rc) {
1762 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
1763 rc = -ENOENT;
1764 goto free_chnl_interrupt;
1765 }
1766
1767 /* Init tasklets for cq only */
1768 for (i = 0; i < hisi_hba->queue_count; i++) {
1769 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1770 struct tasklet_struct *t = &cq->tasklet;
1771
1772 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1773 cq_interrupt_v3_hw, 0,
1774 DRV_NAME " cq", cq);
1775 if (rc) {
1776 dev_err(dev,
1777 "could not request cq%d interrupt, rc=%d\n",
1778 i, rc);
1779 rc = -ENOENT;
1780 goto free_cq_irqs;
1781 }
1782
1783 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1784 }
1785
1786 return 0;
1787
1788 free_cq_irqs:
1789 for (k = 0; k < i; k++) {
1790 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1791
1792 free_irq(pci_irq_vector(pdev, k+16), cq);
1793 }
1794 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
1795 free_chnl_interrupt:
1796 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1797 free_phy_irq:
1798 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1799 free_irq_vectors:
1800 pci_free_irq_vectors(pdev);
1801 return rc;
1802 }
1803
1804 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1805 {
1806 int rc;
1807
1808 rc = hw_init_v3_hw(hisi_hba);
1809 if (rc)
1810 return rc;
1811
1812 rc = interrupt_init_v3_hw(hisi_hba);
1813 if (rc)
1814 return rc;
1815
1816 return 0;
1817 }
1818
1819 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
1820 struct sas_phy_linkrates *r)
1821 {
1822 u32 prog_phy_link_rate =
1823 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1824 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1825 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1826 int i;
1827 enum sas_linkrate min, max;
1828 u32 rate_mask = 0;
1829
1830 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1831 max = sas_phy->phy->maximum_linkrate;
1832 min = r->minimum_linkrate;
1833 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1834 max = r->maximum_linkrate;
1835 min = sas_phy->phy->minimum_linkrate;
1836 } else
1837 return;
1838
1839 sas_phy->phy->maximum_linkrate = max;
1840 sas_phy->phy->minimum_linkrate = min;
1841
1842 min -= SAS_LINK_RATE_1_5_GBPS;
1843 max -= SAS_LINK_RATE_1_5_GBPS;
1844
1845 for (i = 0; i <= max; i++)
1846 rate_mask |= 1 << (i * 2);
1847
1848 prog_phy_link_rate &= ~0xff;
1849 prog_phy_link_rate |= rate_mask;
1850
1851 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1852 prog_phy_link_rate);
1853
1854 phy_hard_reset_v3_hw(hisi_hba, phy_no);
1855 }
1856
1857 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
1858 {
1859 struct pci_dev *pdev = hisi_hba->pci_dev;
1860 int i;
1861
1862 synchronize_irq(pci_irq_vector(pdev, 1));
1863 synchronize_irq(pci_irq_vector(pdev, 2));
1864 synchronize_irq(pci_irq_vector(pdev, 11));
1865 for (i = 0; i < hisi_hba->queue_count; i++) {
1866 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
1867 synchronize_irq(pci_irq_vector(pdev, i + 16));
1868 }
1869
1870 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
1871 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
1872 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
1873 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1874
1875 for (i = 0; i < hisi_hba->n_phy; i++) {
1876 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1877 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
1878 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
1879 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
1880 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
1881 }
1882 }
1883
1884 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
1885 {
1886 return hisi_sas_read32(hisi_hba, PHY_STATE);
1887 }
1888
1889 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1890 {
1891 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1892 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1893 struct sas_phy *sphy = sas_phy->phy;
1894 u32 reg_value;
1895
1896 /* loss dword sync */
1897 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1898 sphy->loss_of_dword_sync_count += reg_value;
1899
1900 /* phy reset problem */
1901 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1902 sphy->phy_reset_problem_count += reg_value;
1903
1904 /* invalid dword */
1905 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1906 sphy->invalid_dword_count += reg_value;
1907
1908 /* disparity err */
1909 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1910 sphy->running_disparity_error_count += reg_value;
1911
1912 }
1913
1914 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
1915 {
1916 struct device *dev = hisi_hba->dev;
1917 int rc;
1918 u32 status;
1919
1920 interrupt_disable_v3_hw(hisi_hba);
1921 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
1922 hisi_sas_kill_tasklets(hisi_hba);
1923
1924 hisi_sas_stop_phys(hisi_hba);
1925
1926 mdelay(10);
1927
1928 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
1929
1930 /* wait until bus idle */
1931 rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
1932 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
1933 if (rc) {
1934 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
1935 return rc;
1936 }
1937
1938 hisi_sas_init_mem(hisi_hba);
1939
1940 return hw_init_v3_hw(hisi_hba);
1941 }
1942
1943 static const struct hisi_sas_hw hisi_sas_v3_hw = {
1944 .hw_init = hisi_sas_v3_init,
1945 .setup_itct = setup_itct_v3_hw,
1946 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
1947 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
1948 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
1949 .clear_itct = clear_itct_v3_hw,
1950 .sl_notify = sl_notify_v3_hw,
1951 .prep_ssp = prep_ssp_v3_hw,
1952 .prep_smp = prep_smp_v3_hw,
1953 .prep_stp = prep_ata_v3_hw,
1954 .prep_abort = prep_abort_v3_hw,
1955 .get_free_slot = get_free_slot_v3_hw,
1956 .start_delivery = start_delivery_v3_hw,
1957 .slot_complete = slot_complete_v3_hw,
1958 .phys_init = phys_init_v3_hw,
1959 .phy_start = start_phy_v3_hw,
1960 .phy_disable = disable_phy_v3_hw,
1961 .phy_hard_reset = phy_hard_reset_v3_hw,
1962 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
1963 .phy_set_linkrate = phy_set_linkrate_v3_hw,
1964 .dereg_device = dereg_device_v3_hw,
1965 .soft_reset = soft_reset_v3_hw,
1966 .get_phys_state = get_phys_state_v3_hw,
1967 .get_events = phy_get_events_v3_hw,
1968 };
1969
1970 static struct Scsi_Host *
1971 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
1972 {
1973 struct Scsi_Host *shost;
1974 struct hisi_hba *hisi_hba;
1975 struct device *dev = &pdev->dev;
1976
1977 shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
1978 if (!shost) {
1979 dev_err(dev, "shost alloc failed\n");
1980 return NULL;
1981 }
1982 hisi_hba = shost_priv(shost);
1983
1984 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
1985 hisi_hba->hw = &hisi_sas_v3_hw;
1986 hisi_hba->pci_dev = pdev;
1987 hisi_hba->dev = dev;
1988 hisi_hba->shost = shost;
1989 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
1990
1991 timer_setup(&hisi_hba->timer, NULL, 0);
1992
1993 if (hisi_sas_get_fw_info(hisi_hba) < 0)
1994 goto err_out;
1995
1996 if (hisi_sas_alloc(hisi_hba, shost)) {
1997 hisi_sas_free(hisi_hba);
1998 goto err_out;
1999 }
2000
2001 return shost;
2002 err_out:
2003 scsi_host_put(shost);
2004 dev_err(dev, "shost alloc failed\n");
2005 return NULL;
2006 }
2007
2008 static int
2009 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2010 {
2011 struct Scsi_Host *shost;
2012 struct hisi_hba *hisi_hba;
2013 struct device *dev = &pdev->dev;
2014 struct asd_sas_phy **arr_phy;
2015 struct asd_sas_port **arr_port;
2016 struct sas_ha_struct *sha;
2017 int rc, phy_nr, port_nr, i;
2018
2019 rc = pci_enable_device(pdev);
2020 if (rc)
2021 goto err_out;
2022
2023 pci_set_master(pdev);
2024
2025 rc = pci_request_regions(pdev, DRV_NAME);
2026 if (rc)
2027 goto err_out_disable_device;
2028
2029 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
2030 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
2031 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2032 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2033 dev_err(dev, "No usable DMA addressing method\n");
2034 rc = -EIO;
2035 goto err_out_regions;
2036 }
2037 }
2038
2039 shost = hisi_sas_shost_alloc_pci(pdev);
2040 if (!shost) {
2041 rc = -ENOMEM;
2042 goto err_out_regions;
2043 }
2044
2045 sha = SHOST_TO_SAS_HA(shost);
2046 hisi_hba = shost_priv(shost);
2047 dev_set_drvdata(dev, sha);
2048
2049 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
2050 if (!hisi_hba->regs) {
2051 dev_err(dev, "cannot map register.\n");
2052 rc = -ENOMEM;
2053 goto err_out_ha;
2054 }
2055
2056 phy_nr = port_nr = hisi_hba->n_phy;
2057
2058 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
2059 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
2060 if (!arr_phy || !arr_port) {
2061 rc = -ENOMEM;
2062 goto err_out_ha;
2063 }
2064
2065 sha->sas_phy = arr_phy;
2066 sha->sas_port = arr_port;
2067 sha->core.shost = shost;
2068 sha->lldd_ha = hisi_hba;
2069
2070 shost->transportt = hisi_sas_stt;
2071 shost->max_id = HISI_SAS_MAX_DEVICES;
2072 shost->max_lun = ~0;
2073 shost->max_channel = 1;
2074 shost->max_cmd_len = 16;
2075 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
2076 shost->can_queue = hisi_hba->hw->max_command_entries;
2077 shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
2078
2079 sha->sas_ha_name = DRV_NAME;
2080 sha->dev = dev;
2081 sha->lldd_module = THIS_MODULE;
2082 sha->sas_addr = &hisi_hba->sas_addr[0];
2083 sha->num_phys = hisi_hba->n_phy;
2084 sha->core.shost = hisi_hba->shost;
2085
2086 for (i = 0; i < hisi_hba->n_phy; i++) {
2087 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
2088 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
2089 }
2090
2091 hisi_sas_init_add(hisi_hba);
2092
2093 rc = scsi_add_host(shost, dev);
2094 if (rc)
2095 goto err_out_ha;
2096
2097 rc = sas_register_ha(sha);
2098 if (rc)
2099 goto err_out_register_ha;
2100
2101 rc = hisi_hba->hw->hw_init(hisi_hba);
2102 if (rc)
2103 goto err_out_register_ha;
2104
2105 scsi_scan_host(shost);
2106
2107 return 0;
2108
2109 err_out_register_ha:
2110 scsi_remove_host(shost);
2111 err_out_ha:
2112 scsi_host_put(shost);
2113 err_out_regions:
2114 pci_release_regions(pdev);
2115 err_out_disable_device:
2116 pci_disable_device(pdev);
2117 err_out:
2118 return rc;
2119 }
2120
2121 static void
2122 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
2123 {
2124 int i;
2125
2126 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2127 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2128 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2129 for (i = 0; i < hisi_hba->queue_count; i++) {
2130 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2131
2132 free_irq(pci_irq_vector(pdev, i+16), cq);
2133 }
2134 pci_free_irq_vectors(pdev);
2135 }
2136
2137 static void hisi_sas_v3_remove(struct pci_dev *pdev)
2138 {
2139 struct device *dev = &pdev->dev;
2140 struct sas_ha_struct *sha = dev_get_drvdata(dev);
2141 struct hisi_hba *hisi_hba = sha->lldd_ha;
2142 struct Scsi_Host *shost = sha->core.shost;
2143
2144 sas_unregister_ha(sha);
2145 sas_remove_host(sha->core.shost);
2146
2147 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
2148 hisi_sas_kill_tasklets(hisi_hba);
2149 pci_release_regions(pdev);
2150 pci_disable_device(pdev);
2151 hisi_sas_free(hisi_hba);
2152 scsi_host_put(shost);
2153 }
2154
2155 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = {
2156 { .irq_msk = BIT(19), .msg = "HILINK_INT" },
2157 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" },
2158 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" },
2159 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" },
2160 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" },
2161 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" },
2162 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" },
2163 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" },
2164 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" },
2165 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" },
2166 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" },
2167 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" },
2168 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" },
2169 };
2170
2171 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = {
2172 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" },
2173 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" },
2174 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" },
2175 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" },
2176 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" },
2177 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" },
2178 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" },
2179 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" },
2180 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" },
2181 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" },
2182 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" },
2183 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" },
2184 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" },
2185 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" },
2186 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" },
2187 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" },
2188 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" },
2189 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" },
2190 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" },
2191 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" },
2192 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" },
2193 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" },
2194 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" },
2195 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" },
2196 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" },
2197 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" },
2198 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" },
2199 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" },
2200 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" },
2201 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" },
2202 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" },
2203 };
2204
2205 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba)
2206 {
2207 struct device *dev = hisi_hba->dev;
2208 const struct hisi_sas_hw_error *ras_error;
2209 bool need_reset = false;
2210 u32 irq_value;
2211 int i;
2212
2213 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0);
2214 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) {
2215 ras_error = &sas_ras_intr0_nfe[i];
2216 if (ras_error->irq_msk & irq_value) {
2217 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n",
2218 ras_error->msg, irq_value);
2219 need_reset = true;
2220 }
2221 }
2222 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value);
2223
2224 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1);
2225 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) {
2226 ras_error = &sas_ras_intr1_nfe[i];
2227 if (ras_error->irq_msk & irq_value) {
2228 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n",
2229 ras_error->msg, irq_value);
2230 need_reset = true;
2231 }
2232 }
2233 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value);
2234
2235 return need_reset;
2236 }
2237
2238 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev,
2239 pci_channel_state_t state)
2240 {
2241 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2242 struct hisi_hba *hisi_hba = sha->lldd_ha;
2243 struct device *dev = hisi_hba->dev;
2244
2245 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state);
2246 if (state == pci_channel_io_perm_failure)
2247 return PCI_ERS_RESULT_DISCONNECT;
2248
2249 if (process_non_fatal_error_v3_hw(hisi_hba))
2250 return PCI_ERS_RESULT_NEED_RESET;
2251
2252 return PCI_ERS_RESULT_CAN_RECOVER;
2253 }
2254
2255 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev)
2256 {
2257 return PCI_ERS_RESULT_RECOVERED;
2258 }
2259
2260 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev)
2261 {
2262 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2263 struct hisi_hba *hisi_hba = sha->lldd_ha;
2264 struct device *dev = hisi_hba->dev;
2265 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r);
2266
2267 dev_info(dev, "PCI error: slot reset callback!!\n");
2268 queue_work(hisi_hba->wq, &r.work);
2269 wait_for_completion(r.completion);
2270 if (r.done)
2271 return PCI_ERS_RESULT_RECOVERED;
2272
2273 return PCI_ERS_RESULT_DISCONNECT;
2274 }
2275
2276 enum {
2277 /* instances of the controller */
2278 hip08,
2279 };
2280
2281 static const struct pci_device_id sas_v3_pci_table[] = {
2282 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
2283 {}
2284 };
2285
2286 static const struct pci_error_handlers hisi_sas_err_handler = {
2287 .error_detected = hisi_sas_error_detected_v3_hw,
2288 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw,
2289 .slot_reset = hisi_sas_slot_reset_v3_hw,
2290 };
2291
2292 static struct pci_driver sas_v3_pci_driver = {
2293 .name = DRV_NAME,
2294 .id_table = sas_v3_pci_table,
2295 .probe = hisi_sas_v3_probe,
2296 .remove = hisi_sas_v3_remove,
2297 .err_handler = &hisi_sas_err_handler,
2298 };
2299
2300 module_pci_driver(sas_v3_pci_driver);
2301
2302 MODULE_LICENSE("GPL");
2303 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2304 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2305 MODULE_ALIAS("platform:" DRV_NAME);
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