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scsi: hisi_sas: Fix the failure of recovering PHY from STP link timeout
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v3_hw.c
1 /*
2 * Copyright (c) 2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 #include "hisi_sas.h"
12 #define DRV_NAME "hisi_sas_v3_hw"
13
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
26 #define ITCT_CLR 0x44
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CHNL_INT_STATUS 0x148
55 #define HGC_AXI_FIFO_ERR_INFO 0x154
56 #define AXI_ERR_INFO_OFF 0
57 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
58 #define FIFO_ERR_INFO_OFF 8
59 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
60 #define INT_COAL_EN 0x19c
61 #define OQ_INT_COAL_TIME 0x1a0
62 #define OQ_INT_COAL_CNT 0x1a4
63 #define ENT_INT_COAL_TIME 0x1a8
64 #define ENT_INT_COAL_CNT 0x1ac
65 #define OQ_INT_SRC 0x1b0
66 #define OQ_INT_SRC_MSK 0x1b4
67 #define ENT_INT_SRC1 0x1b8
68 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
69 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
70 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
71 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
72 #define ENT_INT_SRC2 0x1bc
73 #define ENT_INT_SRC3 0x1c0
74 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
75 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
76 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
77 #define ENT_INT_SRC3_AXI_OFF 11
78 #define ENT_INT_SRC3_FIFO_OFF 12
79 #define ENT_INT_SRC3_LM_OFF 14
80 #define ENT_INT_SRC3_ITC_INT_OFF 15
81 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
82 #define ENT_INT_SRC3_ABT_OFF 16
83 #define ENT_INT_SRC_MSK1 0x1c4
84 #define ENT_INT_SRC_MSK2 0x1c8
85 #define ENT_INT_SRC_MSK3 0x1cc
86 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
87 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
88 #define CHNL_ENT_INT_MSK 0x1d4
89 #define HGC_COM_INT_MSK 0x1d8
90 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
91 #define SAS_ECC_INTR 0x1e8
92 #define SAS_ECC_INTR_MSK 0x1ec
93 #define HGC_ERR_STAT_EN 0x238
94 #define CQE_SEND_CNT 0x248
95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
97 #define DLVRY_Q_0_DEPTH 0x268
98 #define DLVRY_Q_0_WR_PTR 0x26c
99 #define DLVRY_Q_0_RD_PTR 0x270
100 #define HYPER_STREAM_ID_EN_CFG 0xc80
101 #define OQ0_INT_SRC_MSK 0xc90
102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
104 #define COMPL_Q_0_DEPTH 0x4e8
105 #define COMPL_Q_0_WR_PTR 0x4ec
106 #define COMPL_Q_0_RD_PTR 0x4f0
107 #define AWQOS_AWCACHE_CFG 0xc84
108 #define ARQOS_ARCACHE_CFG 0xc88
109 #define HILINK_ERR_DFX 0xe04
110 #define SAS_GPIO_CFG_0 0x1000
111 #define SAS_GPIO_CFG_1 0x1004
112 #define SAS_GPIO_TX_0_1 0x1040
113 #define SAS_CFG_DRIVE_VLD 0x1070
114
115 /* phy registers requiring init */
116 #define PORT_BASE (0x2000)
117 #define PHY_CFG (PORT_BASE + 0x0)
118 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
119 #define PHY_CFG_ENA_OFF 0
120 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
121 #define PHY_CFG_DC_OPT_OFF 2
122 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
123 #define PHY_CFG_PHY_RST_OFF 3
124 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF)
125 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
126 #define PHY_CTRL (PORT_BASE + 0x14)
127 #define PHY_CTRL_RESET_OFF 0
128 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
129 #define SL_CFG (PORT_BASE + 0x84)
130 #define SL_CONTROL (PORT_BASE + 0x94)
131 #define SL_CONTROL_NOTIFY_EN_OFF 0
132 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
133 #define SL_CTA_OFF 17
134 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
135 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
136 #define RX_BCAST_CHG_OFF 1
137 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
138 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
139 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
140 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
141 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
142 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
143 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
144 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
145 #define TXID_AUTO (PORT_BASE + 0xb8)
146 #define CT3_OFF 1
147 #define CT3_MSK (0x1 << CT3_OFF)
148 #define TX_HARDRST_OFF 2
149 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
150 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
151 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
152 #define STP_LINK_TIMER (PORT_BASE + 0x120)
153 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
154 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
155 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
156 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
157 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
158 #define CHL_INT0 (PORT_BASE + 0x1b4)
159 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
160 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
161 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
162 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
163 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
164 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
165 #define CHL_INT0_NOT_RDY_OFF 4
166 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
167 #define CHL_INT0_PHY_RDY_OFF 5
168 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
169 #define CHL_INT1 (PORT_BASE + 0x1b8)
170 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
171 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
172 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
173 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
174 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
175 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
176 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
177 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
178 #define CHL_INT2 (PORT_BASE + 0x1bc)
179 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
180 #define CHL_INT2_RX_INVLD_DW_OFF 30
181 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
182 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
183 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
184 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
185 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
186 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
187 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
188 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
189 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
190 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
191 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
192 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
193 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
194 #define DMA_TX_STATUS_BUSY_OFF 0
195 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
196 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
197 #define DMA_RX_STATUS_BUSY_OFF 0
198 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
199
200 #define COARSETUNE_TIME (PORT_BASE + 0x304)
201 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
202 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
203 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
204 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
205
206 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
207 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
208 #error Max ITCT exceeded
209 #endif
210
211 #define AXI_MASTER_CFG_BASE (0x5000)
212 #define AM_CTRL_GLOBAL (0x0)
213 #define AM_CURR_TRANS_RETURN (0x150)
214
215 #define AM_CFG_MAX_TRANS (0x5010)
216 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
217 #define AXI_CFG (0x5100)
218 #define AM_ROB_ECC_ERR_ADDR (0x510c)
219 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
220 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
221 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
222 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
223
224 /* RAS registers need init */
225 #define RAS_BASE (0x6000)
226 #define SAS_RAS_INTR0 (RAS_BASE)
227 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
228 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
229 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
230 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c)
231 #define SAS_RAS_INTR2 (RAS_BASE + 0x20)
232 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24)
233
234 /* HW dma structures */
235 /* Delivery queue header */
236 /* dw0 */
237 #define CMD_HDR_ABORT_FLAG_OFF 0
238 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
239 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
240 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
241 #define CMD_HDR_RESP_REPORT_OFF 5
242 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
243 #define CMD_HDR_TLR_CTRL_OFF 6
244 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
245 #define CMD_HDR_PORT_OFF 18
246 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
247 #define CMD_HDR_PRIORITY_OFF 27
248 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
249 #define CMD_HDR_CMD_OFF 29
250 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
251 /* dw1 */
252 #define CMD_HDR_UNCON_CMD_OFF 3
253 #define CMD_HDR_DIR_OFF 5
254 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
255 #define CMD_HDR_RESET_OFF 7
256 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
257 #define CMD_HDR_VDTL_OFF 10
258 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
259 #define CMD_HDR_FRAME_TYPE_OFF 11
260 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
261 #define CMD_HDR_DEV_ID_OFF 16
262 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
263 /* dw2 */
264 #define CMD_HDR_CFL_OFF 0
265 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
266 #define CMD_HDR_NCQ_TAG_OFF 10
267 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
268 #define CMD_HDR_MRFL_OFF 15
269 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
270 #define CMD_HDR_SG_MOD_OFF 24
271 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
272 /* dw3 */
273 #define CMD_HDR_IPTT_OFF 0
274 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
275 /* dw6 */
276 #define CMD_HDR_DIF_SGL_LEN_OFF 0
277 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
278 #define CMD_HDR_DATA_SGL_LEN_OFF 16
279 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
280 /* dw7 */
281 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
282 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
283 #define CMD_HDR_ABORT_IPTT_OFF 16
284 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
285
286 /* Completion header */
287 /* dw0 */
288 #define CMPLT_HDR_CMPLT_OFF 0
289 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
290 #define CMPLT_HDR_ERROR_PHASE_OFF 2
291 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
292 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
293 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
294 #define CMPLT_HDR_ERX_OFF 12
295 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
296 #define CMPLT_HDR_ABORT_STAT_OFF 13
297 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
298 /* abort_stat */
299 #define STAT_IO_NOT_VALID 0x1
300 #define STAT_IO_NO_DEVICE 0x2
301 #define STAT_IO_COMPLETE 0x3
302 #define STAT_IO_ABORTED 0x4
303 /* dw1 */
304 #define CMPLT_HDR_IPTT_OFF 0
305 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
306 #define CMPLT_HDR_DEV_ID_OFF 16
307 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
308 /* dw3 */
309 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
310 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
311
312 /* ITCT header */
313 /* qw0 */
314 #define ITCT_HDR_DEV_TYPE_OFF 0
315 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
316 #define ITCT_HDR_VALID_OFF 2
317 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
318 #define ITCT_HDR_MCR_OFF 5
319 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
320 #define ITCT_HDR_VLN_OFF 9
321 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
322 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
323 #define ITCT_HDR_AWT_CONTINUE_OFF 25
324 #define ITCT_HDR_PORT_ID_OFF 28
325 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
326 /* qw2 */
327 #define ITCT_HDR_INLT_OFF 0
328 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
329 #define ITCT_HDR_RTOLT_OFF 48
330 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
331
332 struct hisi_sas_complete_v3_hdr {
333 __le32 dw0;
334 __le32 dw1;
335 __le32 act;
336 __le32 dw3;
337 };
338
339 struct hisi_sas_err_record_v3 {
340 /* dw0 */
341 __le32 trans_tx_fail_type;
342
343 /* dw1 */
344 __le32 trans_rx_fail_type;
345
346 /* dw2 */
347 __le16 dma_tx_err_type;
348 __le16 sipc_rx_err_type;
349
350 /* dw3 */
351 __le32 dma_rx_err_type;
352 };
353
354 #define RX_DATA_LEN_UNDERFLOW_OFF 6
355 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
356
357 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
358 #define HISI_SAS_MSI_COUNT_V3_HW 32
359
360 #define DIR_NO_DATA 0
361 #define DIR_TO_INI 1
362 #define DIR_TO_DEVICE 2
363 #define DIR_RESERVED 3
364
365 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
366 ((fis.command == ATA_CMD_READ_LOG_EXT) || \
367 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
368 ((fis.command == ATA_CMD_DEV_RESET) && \
369 ((fis.control & ATA_SRST) != 0)))
370
371 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
372 {
373 void __iomem *regs = hisi_hba->regs + off;
374
375 return readl(regs);
376 }
377
378 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
379 {
380 void __iomem *regs = hisi_hba->regs + off;
381
382 return readl_relaxed(regs);
383 }
384
385 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
386 {
387 void __iomem *regs = hisi_hba->regs + off;
388
389 writel(val, regs);
390 }
391
392 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
393 u32 off, u32 val)
394 {
395 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
396
397 writel(val, regs);
398 }
399
400 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
401 int phy_no, u32 off)
402 {
403 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
404
405 return readl(regs);
406 }
407
408 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \
409 timeout_us) \
410 ({ \
411 void __iomem *regs = hisi_hba->regs + off; \
412 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \
413 })
414
415 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \
416 timeout_us) \
417 ({ \
418 void __iomem *regs = hisi_hba->regs + off; \
419 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
420 })
421
422 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
423 {
424 struct pci_dev *pdev = hisi_hba->pci_dev;
425 int i;
426
427 /* Global registers init */
428 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
429 (u32)((1ULL << hisi_hba->queue_count) - 1));
430 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
431 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
432 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
433 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
434 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
435 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
436 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
437 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
438 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
439 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
440 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
441 if (pdev->revision >= 0x21)
442 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7fff);
443 else
444 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff);
445 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
446 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
447 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
448 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
449 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
450 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
451 for (i = 0; i < hisi_hba->queue_count; i++)
452 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
453
454 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
455
456 for (i = 0; i < hisi_hba->n_phy; i++) {
457 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
458 struct asd_sas_phy *sas_phy = &phy->sas_phy;
459 u32 prog_phy_link_rate = 0x800;
460
461 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
462 SAS_LINK_RATE_1_5_GBPS)) {
463 prog_phy_link_rate = 0x855;
464 } else {
465 enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
466
467 prog_phy_link_rate =
468 hisi_sas_get_prog_phy_linkrate_mask(max) |
469 0x800;
470 }
471 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
472 prog_phy_link_rate);
473 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
474 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
475 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
476 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
477 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
478 if (pdev->revision >= 0x21)
479 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
480 0xffffffff);
481 else
482 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
483 0xff87ffff);
484 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
485 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
486 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
487 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
488 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
489 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
490 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
491 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
492 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
493
494 /* used for 12G negotiate */
495 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
496 }
497
498 for (i = 0; i < hisi_hba->queue_count; i++) {
499 /* Delivery queue */
500 hisi_sas_write32(hisi_hba,
501 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
502 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
503
504 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
505 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
506
507 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
508 HISI_SAS_QUEUE_SLOTS);
509
510 /* Completion queue */
511 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
512 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
513
514 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
515 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
516
517 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
518 HISI_SAS_QUEUE_SLOTS);
519 }
520
521 /* itct */
522 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
523 lower_32_bits(hisi_hba->itct_dma));
524
525 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
526 upper_32_bits(hisi_hba->itct_dma));
527
528 /* iost */
529 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
530 lower_32_bits(hisi_hba->iost_dma));
531
532 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
533 upper_32_bits(hisi_hba->iost_dma));
534
535 /* breakpoint */
536 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
537 lower_32_bits(hisi_hba->breakpoint_dma));
538
539 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
540 upper_32_bits(hisi_hba->breakpoint_dma));
541
542 /* SATA broken msg */
543 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
544 lower_32_bits(hisi_hba->sata_breakpoint_dma));
545
546 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
547 upper_32_bits(hisi_hba->sata_breakpoint_dma));
548
549 /* SATA initial fis */
550 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
551 lower_32_bits(hisi_hba->initial_fis_dma));
552
553 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
554 upper_32_bits(hisi_hba->initial_fis_dma));
555
556 /* RAS registers init */
557 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
558 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
559 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
560 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
561
562 /* LED registers init */
563 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
564 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
565 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
566 /* Configure blink generator rate A to 1Hz and B to 4Hz */
567 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
568 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
569 }
570
571 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
572 {
573 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
574
575 cfg &= ~PHY_CFG_DC_OPT_MSK;
576 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
577 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
578 }
579
580 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
581 {
582 struct sas_identify_frame identify_frame;
583 u32 *identify_buffer;
584
585 memset(&identify_frame, 0, sizeof(identify_frame));
586 identify_frame.dev_type = SAS_END_DEVICE;
587 identify_frame.frame_type = 0;
588 identify_frame._un1 = 1;
589 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
590 identify_frame.target_bits = SAS_PROTOCOL_NONE;
591 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
592 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
593 identify_frame.phy_id = phy_no;
594 identify_buffer = (u32 *)(&identify_frame);
595
596 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
597 __swab32(identify_buffer[0]));
598 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
599 __swab32(identify_buffer[1]));
600 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
601 __swab32(identify_buffer[2]));
602 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
603 __swab32(identify_buffer[3]));
604 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
605 __swab32(identify_buffer[4]));
606 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
607 __swab32(identify_buffer[5]));
608 }
609
610 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
611 struct hisi_sas_device *sas_dev)
612 {
613 struct domain_device *device = sas_dev->sas_device;
614 struct device *dev = hisi_hba->dev;
615 u64 qw0, device_id = sas_dev->device_id;
616 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
617 struct domain_device *parent_dev = device->parent;
618 struct asd_sas_port *sas_port = device->port;
619 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
620
621 memset(itct, 0, sizeof(*itct));
622
623 /* qw0 */
624 qw0 = 0;
625 switch (sas_dev->dev_type) {
626 case SAS_END_DEVICE:
627 case SAS_EDGE_EXPANDER_DEVICE:
628 case SAS_FANOUT_EXPANDER_DEVICE:
629 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
630 break;
631 case SAS_SATA_DEV:
632 case SAS_SATA_PENDING:
633 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
634 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
635 else
636 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
637 break;
638 default:
639 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
640 sas_dev->dev_type);
641 }
642
643 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
644 (device->linkrate << ITCT_HDR_MCR_OFF) |
645 (1 << ITCT_HDR_VLN_OFF) |
646 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
647 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
648 (port->id << ITCT_HDR_PORT_ID_OFF));
649 itct->qw0 = cpu_to_le64(qw0);
650
651 /* qw1 */
652 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
653 itct->sas_addr = __swab64(itct->sas_addr);
654
655 /* qw2 */
656 if (!dev_is_sata(device))
657 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
658 (0x1ULL << ITCT_HDR_RTOLT_OFF));
659 }
660
661 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba,
662 struct hisi_sas_device *sas_dev)
663 {
664 DECLARE_COMPLETION_ONSTACK(completion);
665 u64 dev_id = sas_dev->device_id;
666 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
667 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
668
669 sas_dev->completion = &completion;
670
671 /* clear the itct interrupt state */
672 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
673 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
674 ENT_INT_SRC3_ITC_INT_MSK);
675
676 /* clear the itct table*/
677 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
678 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
679
680 wait_for_completion(sas_dev->completion);
681 memset(itct, 0, sizeof(struct hisi_sas_itct));
682 }
683
684 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
685 struct domain_device *device)
686 {
687 struct hisi_sas_slot *slot, *slot2;
688 struct hisi_sas_device *sas_dev = device->lldd_dev;
689 u32 cfg_abt_set_query_iptt;
690
691 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
692 CFG_ABT_SET_QUERY_IPTT);
693 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
694 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
695 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
696 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
697 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
698 cfg_abt_set_query_iptt);
699 }
700 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
701 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
702 cfg_abt_set_query_iptt);
703 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
704 1 << CFG_ABT_SET_IPTT_DONE_OFF);
705 }
706
707 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
708 {
709 struct device *dev = hisi_hba->dev;
710 int ret;
711 u32 val;
712
713 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
714
715 /* Disable all of the PHYs */
716 hisi_sas_stop_phys(hisi_hba);
717 udelay(50);
718
719 /* Ensure axi bus idle */
720 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
721 20000, 1000000);
722 if (ret) {
723 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
724 return -EIO;
725 }
726
727 if (ACPI_HANDLE(dev)) {
728 acpi_status s;
729
730 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
731 if (ACPI_FAILURE(s)) {
732 dev_err(dev, "Reset failed\n");
733 return -EIO;
734 }
735 } else {
736 dev_err(dev, "no reset method!\n");
737 return -EINVAL;
738 }
739
740 return 0;
741 }
742
743 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
744 {
745 struct device *dev = hisi_hba->dev;
746 int rc;
747
748 rc = reset_hw_v3_hw(hisi_hba);
749 if (rc) {
750 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
751 return rc;
752 }
753
754 msleep(100);
755 init_reg_v3_hw(hisi_hba);
756
757 return 0;
758 }
759
760 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
761 {
762 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
763
764 cfg |= PHY_CFG_ENA_MSK;
765 cfg &= ~PHY_CFG_PHY_RST_MSK;
766 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
767 }
768
769 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
770 {
771 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
772 u32 state;
773
774 cfg &= ~PHY_CFG_ENA_MSK;
775 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
776
777 mdelay(50);
778
779 state = hisi_sas_read32(hisi_hba, PHY_STATE);
780 if (state & BIT(phy_no)) {
781 cfg |= PHY_CFG_PHY_RST_MSK;
782 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
783 }
784 }
785
786 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
787 {
788 config_id_frame_v3_hw(hisi_hba, phy_no);
789 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
790 enable_phy_v3_hw(hisi_hba, phy_no);
791 }
792
793 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
794 {
795 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
796 u32 txid_auto;
797
798 disable_phy_v3_hw(hisi_hba, phy_no);
799 if (phy->identify.device_type == SAS_END_DEVICE) {
800 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
801 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
802 txid_auto | TX_HARDRST_MSK);
803 }
804 msleep(100);
805 start_phy_v3_hw(hisi_hba, phy_no);
806 }
807
808 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
809 {
810 return SAS_LINK_RATE_12_0_GBPS;
811 }
812
813 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
814 {
815 int i;
816
817 for (i = 0; i < hisi_hba->n_phy; i++) {
818 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
819 struct asd_sas_phy *sas_phy = &phy->sas_phy;
820
821 if (!sas_phy->phy->enabled)
822 continue;
823
824 start_phy_v3_hw(hisi_hba, i);
825 }
826 }
827
828 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
829 {
830 u32 sl_control;
831
832 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
833 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
834 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
835 msleep(1);
836 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
837 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
838 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
839 }
840
841 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
842 {
843 int i, bitmap = 0;
844 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
845 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
846
847 for (i = 0; i < hisi_hba->n_phy; i++)
848 if (phy_state & BIT(i))
849 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
850 bitmap |= BIT(i);
851
852 return bitmap;
853 }
854
855 /**
856 * The callpath to this function and upto writing the write
857 * queue pointer should be safe from interruption.
858 */
859 static int
860 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
861 {
862 struct device *dev = hisi_hba->dev;
863 int queue = dq->id;
864 u32 r, w;
865
866 w = dq->wr_point;
867 r = hisi_sas_read32_relaxed(hisi_hba,
868 DLVRY_Q_0_RD_PTR + (queue * 0x14));
869 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
870 dev_warn(dev, "full queue=%d r=%d w=%d\n",
871 queue, r, w);
872 return -EAGAIN;
873 }
874
875 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
876
877 return w;
878 }
879
880 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
881 {
882 struct hisi_hba *hisi_hba = dq->hisi_hba;
883 struct hisi_sas_slot *s, *s1;
884 struct list_head *dq_list;
885 int dlvry_queue = dq->id;
886 int wp, count = 0;
887
888 dq_list = &dq->list;
889 list_for_each_entry_safe(s, s1, &dq->list, delivery) {
890 if (!s->ready)
891 break;
892 count++;
893 wp = (s->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
894 list_del(&s->delivery);
895 }
896
897 if (!count)
898 return;
899
900 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
901 }
902
903 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
904 struct hisi_sas_slot *slot,
905 struct hisi_sas_cmd_hdr *hdr,
906 struct scatterlist *scatter,
907 int n_elem)
908 {
909 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
910 struct scatterlist *sg;
911 int i;
912
913 for_each_sg(scatter, sg, n_elem, i) {
914 struct hisi_sas_sge *entry = &sge_page->sge[i];
915
916 entry->addr = cpu_to_le64(sg_dma_address(sg));
917 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
918 entry->data_len = cpu_to_le32(sg_dma_len(sg));
919 entry->data_off = 0;
920 }
921
922 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
923
924 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
925 }
926
927 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
928 struct hisi_sas_slot *slot)
929 {
930 struct sas_task *task = slot->task;
931 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
932 struct domain_device *device = task->dev;
933 struct hisi_sas_device *sas_dev = device->lldd_dev;
934 struct hisi_sas_port *port = slot->port;
935 struct sas_ssp_task *ssp_task = &task->ssp_task;
936 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
937 struct hisi_sas_tmf_task *tmf = slot->tmf;
938 int has_data = 0, priority = !!tmf;
939 u8 *buf_cmd;
940 u32 dw1 = 0, dw2 = 0;
941
942 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
943 (2 << CMD_HDR_TLR_CTRL_OFF) |
944 (port->id << CMD_HDR_PORT_OFF) |
945 (priority << CMD_HDR_PRIORITY_OFF) |
946 (1 << CMD_HDR_CMD_OFF)); /* ssp */
947
948 dw1 = 1 << CMD_HDR_VDTL_OFF;
949 if (tmf) {
950 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
951 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
952 } else {
953 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
954 switch (scsi_cmnd->sc_data_direction) {
955 case DMA_TO_DEVICE:
956 has_data = 1;
957 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
958 break;
959 case DMA_FROM_DEVICE:
960 has_data = 1;
961 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
962 break;
963 default:
964 dw1 &= ~CMD_HDR_DIR_MSK;
965 }
966 }
967
968 /* map itct entry */
969 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
970 hdr->dw1 = cpu_to_le32(dw1);
971
972 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
973 + 3) / 4) << CMD_HDR_CFL_OFF) |
974 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
975 (2 << CMD_HDR_SG_MOD_OFF);
976 hdr->dw2 = cpu_to_le32(dw2);
977 hdr->transfer_tags = cpu_to_le32(slot->idx);
978
979 if (has_data)
980 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
981 slot->n_elem);
982
983 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
984 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
985 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
986
987 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
988 sizeof(struct ssp_frame_hdr);
989
990 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
991 if (!tmf) {
992 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
993 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
994 } else {
995 buf_cmd[10] = tmf->tmf;
996 switch (tmf->tmf) {
997 case TMF_ABORT_TASK:
998 case TMF_QUERY_TASK:
999 buf_cmd[12] =
1000 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1001 buf_cmd[13] =
1002 tmf->tag_of_task_to_be_managed & 0xff;
1003 break;
1004 default:
1005 break;
1006 }
1007 }
1008 }
1009
1010 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1011 struct hisi_sas_slot *slot)
1012 {
1013 struct sas_task *task = slot->task;
1014 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1015 struct domain_device *device = task->dev;
1016 struct hisi_sas_port *port = slot->port;
1017 struct scatterlist *sg_req;
1018 struct hisi_sas_device *sas_dev = device->lldd_dev;
1019 dma_addr_t req_dma_addr;
1020 unsigned int req_len;
1021
1022 /* req */
1023 sg_req = &task->smp_task.smp_req;
1024 req_len = sg_dma_len(sg_req);
1025 req_dma_addr = sg_dma_address(sg_req);
1026
1027 /* create header */
1028 /* dw0 */
1029 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1030 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1031 (2 << CMD_HDR_CMD_OFF)); /* smp */
1032
1033 /* map itct entry */
1034 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1035 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1036 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1037
1038 /* dw2 */
1039 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1040 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1041 CMD_HDR_MRFL_OFF));
1042
1043 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1044
1045 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1046 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1047
1048 }
1049
1050 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1051 struct hisi_sas_slot *slot)
1052 {
1053 struct sas_task *task = slot->task;
1054 struct domain_device *device = task->dev;
1055 struct domain_device *parent_dev = device->parent;
1056 struct hisi_sas_device *sas_dev = device->lldd_dev;
1057 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1058 struct asd_sas_port *sas_port = device->port;
1059 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1060 u8 *buf_cmd;
1061 int has_data = 0, hdr_tag = 0;
1062 u32 dw1 = 0, dw2 = 0;
1063
1064 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1065 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1066 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1067 else
1068 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1069
1070 switch (task->data_dir) {
1071 case DMA_TO_DEVICE:
1072 has_data = 1;
1073 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1074 break;
1075 case DMA_FROM_DEVICE:
1076 has_data = 1;
1077 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1078 break;
1079 default:
1080 dw1 &= ~CMD_HDR_DIR_MSK;
1081 }
1082
1083 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1084 (task->ata_task.fis.control & ATA_SRST))
1085 dw1 |= 1 << CMD_HDR_RESET_OFF;
1086
1087 dw1 |= (hisi_sas_get_ata_protocol(
1088 &task->ata_task.fis, task->data_dir))
1089 << CMD_HDR_FRAME_TYPE_OFF;
1090 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1091
1092 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1093 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1094
1095 hdr->dw1 = cpu_to_le32(dw1);
1096
1097 /* dw2 */
1098 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
1099 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1100 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1101 }
1102
1103 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1104 2 << CMD_HDR_SG_MOD_OFF;
1105 hdr->dw2 = cpu_to_le32(dw2);
1106
1107 /* dw3 */
1108 hdr->transfer_tags = cpu_to_le32(slot->idx);
1109
1110 if (has_data)
1111 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1112 slot->n_elem);
1113
1114 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1115 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1116 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1117
1118 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1119
1120 if (likely(!task->ata_task.device_control_reg_update))
1121 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1122 /* fill in command FIS */
1123 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1124 }
1125
1126 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1127 struct hisi_sas_slot *slot,
1128 int device_id, int abort_flag, int tag_to_abort)
1129 {
1130 struct sas_task *task = slot->task;
1131 struct domain_device *dev = task->dev;
1132 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1133 struct hisi_sas_port *port = slot->port;
1134
1135 /* dw0 */
1136 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1137 (port->id << CMD_HDR_PORT_OFF) |
1138 (dev_is_sata(dev)
1139 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1140 (abort_flag
1141 << CMD_HDR_ABORT_FLAG_OFF));
1142
1143 /* dw1 */
1144 hdr->dw1 = cpu_to_le32(device_id
1145 << CMD_HDR_DEV_ID_OFF);
1146
1147 /* dw7 */
1148 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1149 hdr->transfer_tags = cpu_to_le32(slot->idx);
1150
1151 }
1152
1153 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1154 {
1155 int i, res;
1156 u32 context, port_id, link_rate;
1157 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1158 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1159 struct device *dev = hisi_hba->dev;
1160 unsigned long flags;
1161
1162 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1163
1164 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1165 port_id = (port_id >> (4 * phy_no)) & 0xf;
1166 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1167 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1168
1169 if (port_id == 0xf) {
1170 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1171 res = IRQ_NONE;
1172 goto end;
1173 }
1174 sas_phy->linkrate = link_rate;
1175 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1176
1177 /* Check for SATA dev */
1178 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1179 if (context & (1 << phy_no)) {
1180 struct hisi_sas_initial_fis *initial_fis;
1181 struct dev_to_host_fis *fis;
1182 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1183
1184 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1185 initial_fis = &hisi_hba->initial_fis[phy_no];
1186 fis = &initial_fis->fis;
1187 sas_phy->oob_mode = SATA_OOB_MODE;
1188 attached_sas_addr[0] = 0x50;
1189 attached_sas_addr[7] = phy_no;
1190 memcpy(sas_phy->attached_sas_addr,
1191 attached_sas_addr,
1192 SAS_ADDR_SIZE);
1193 memcpy(sas_phy->frame_rcvd, fis,
1194 sizeof(struct dev_to_host_fis));
1195 phy->phy_type |= PORT_TYPE_SATA;
1196 phy->identify.device_type = SAS_SATA_DEV;
1197 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1198 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1199 } else {
1200 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1201 struct sas_identify_frame *id =
1202 (struct sas_identify_frame *)frame_rcvd;
1203
1204 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1205 for (i = 0; i < 6; i++) {
1206 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1207 RX_IDAF_DWORD0 + (i * 4));
1208 frame_rcvd[i] = __swab32(idaf);
1209 }
1210 sas_phy->oob_mode = SAS_OOB_MODE;
1211 memcpy(sas_phy->attached_sas_addr,
1212 &id->sas_addr,
1213 SAS_ADDR_SIZE);
1214 phy->phy_type |= PORT_TYPE_SAS;
1215 phy->identify.device_type = id->dev_type;
1216 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1217 if (phy->identify.device_type == SAS_END_DEVICE)
1218 phy->identify.target_port_protocols =
1219 SAS_PROTOCOL_SSP;
1220 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1221 phy->identify.target_port_protocols =
1222 SAS_PROTOCOL_SMP;
1223 }
1224
1225 phy->port_id = port_id;
1226 phy->phy_attached = 1;
1227 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1228 res = IRQ_HANDLED;
1229 spin_lock_irqsave(&phy->lock, flags);
1230 if (phy->reset_completion) {
1231 phy->in_reset = 0;
1232 complete(phy->reset_completion);
1233 }
1234 spin_unlock_irqrestore(&phy->lock, flags);
1235 end:
1236 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1237 CHL_INT0_SL_PHY_ENABLE_MSK);
1238 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1239
1240 return res;
1241 }
1242
1243 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1244 {
1245 u32 phy_state, sl_ctrl, txid_auto;
1246 struct device *dev = hisi_hba->dev;
1247
1248 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1249
1250 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1251 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1252 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1253
1254 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1255 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1256 sl_ctrl&(~SL_CTA_MSK));
1257
1258 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1259 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1260 txid_auto | CT3_MSK);
1261
1262 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1263 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1264
1265 return IRQ_HANDLED;
1266 }
1267
1268 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1269 {
1270 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1271 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1272 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1273 u32 bcast_status;
1274
1275 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1276 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1277 if ((bcast_status & RX_BCAST_CHG_MSK) &&
1278 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
1279 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1280 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1281 CHL_INT0_SL_RX_BCST_ACK_MSK);
1282 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1283
1284 return IRQ_HANDLED;
1285 }
1286
1287 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1288 {
1289 struct hisi_hba *hisi_hba = p;
1290 u32 irq_msk;
1291 int phy_no = 0;
1292 irqreturn_t res = IRQ_NONE;
1293
1294 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1295 & 0x11111111;
1296 while (irq_msk) {
1297 if (irq_msk & 1) {
1298 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1299 CHL_INT0);
1300 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1301 int rdy = phy_state & (1 << phy_no);
1302
1303 if (rdy) {
1304 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1305 /* phy up */
1306 if (phy_up_v3_hw(phy_no, hisi_hba)
1307 == IRQ_HANDLED)
1308 res = IRQ_HANDLED;
1309 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1310 /* phy bcast */
1311 if (phy_bcast_v3_hw(phy_no, hisi_hba)
1312 == IRQ_HANDLED)
1313 res = IRQ_HANDLED;
1314 } else {
1315 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1316 /* phy down */
1317 if (phy_down_v3_hw(phy_no, hisi_hba)
1318 == IRQ_HANDLED)
1319 res = IRQ_HANDLED;
1320 }
1321 }
1322 irq_msk >>= 4;
1323 phy_no++;
1324 }
1325
1326 return res;
1327 }
1328
1329 static const struct hisi_sas_hw_error port_axi_error[] = {
1330 {
1331 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1332 .msg = "dma_tx_axi_wr_err",
1333 },
1334 {
1335 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1336 .msg = "dma_tx_axi_rd_err",
1337 },
1338 {
1339 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1340 .msg = "dma_rx_axi_wr_err",
1341 },
1342 {
1343 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1344 .msg = "dma_rx_axi_rd_err",
1345 },
1346 };
1347
1348 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1349 {
1350 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1351 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1352 struct device *dev = hisi_hba->dev;
1353 int i;
1354
1355 irq_value &= ~irq_msk;
1356 if (!irq_value)
1357 return;
1358
1359 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1360 const struct hisi_sas_hw_error *error = &port_axi_error[i];
1361
1362 if (!(irq_value & error->irq_msk))
1363 continue;
1364
1365 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1366 error->msg, phy_no, irq_value);
1367 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1368 }
1369
1370 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
1371 }
1372
1373 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1374 {
1375 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1376 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1377 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1378 struct pci_dev *pci_dev = hisi_hba->pci_dev;
1379 struct device *dev = hisi_hba->dev;
1380
1381 irq_value &= ~irq_msk;
1382 if (!irq_value)
1383 return;
1384
1385 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1386 dev_warn(dev, "phy%d identify timeout\n", phy_no);
1387 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1388 }
1389
1390 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1391 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1392 STP_LINK_TIMEOUT_STATE);
1393
1394 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1395 phy_no, reg_value);
1396 if (reg_value & BIT(4))
1397 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1398 }
1399
1400 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1401 (pci_dev->revision == 0x20)) {
1402 u32 reg_value;
1403 int rc;
1404
1405 rc = hisi_sas_read32_poll_timeout_atomic(
1406 HILINK_ERR_DFX, reg_value,
1407 !((reg_value >> 8) & BIT(phy_no)),
1408 1000, 10000);
1409 if (rc)
1410 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1411 }
1412
1413 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
1414 }
1415
1416 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1417 {
1418 struct hisi_hba *hisi_hba = p;
1419 u32 irq_msk;
1420 int phy_no = 0;
1421
1422 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1423 & 0xeeeeeeee;
1424
1425 while (irq_msk) {
1426 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1427 CHL_INT0);
1428
1429 if (irq_msk & (4 << (phy_no * 4)))
1430 handle_chl_int1_v3_hw(hisi_hba, phy_no);
1431
1432 if (irq_msk & (8 << (phy_no * 4)))
1433 handle_chl_int2_v3_hw(hisi_hba, phy_no);
1434
1435 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1436 hisi_sas_phy_write32(hisi_hba, phy_no,
1437 CHL_INT0, irq_value0
1438 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1439 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1440 & (~CHL_INT0_NOT_RDY_MSK));
1441 }
1442 irq_msk &= ~(0xe << (phy_no * 4));
1443 phy_no++;
1444 }
1445
1446 return IRQ_HANDLED;
1447 }
1448
1449 static const struct hisi_sas_hw_error axi_error[] = {
1450 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1451 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1452 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1453 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1454 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1455 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1456 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1457 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1458 {},
1459 };
1460
1461 static const struct hisi_sas_hw_error fifo_error[] = {
1462 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
1463 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
1464 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1465 { .msk = BIT(11), .msg = "CMDP_FIFO" },
1466 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1467 {},
1468 };
1469
1470 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1471 {
1472 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1473 .msg = "write pointer and depth",
1474 },
1475 {
1476 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
1477 .msg = "iptt no match slot",
1478 },
1479 {
1480 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
1481 .msg = "read pointer and depth",
1482 },
1483 {
1484 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
1485 .reg = HGC_AXI_FIFO_ERR_INFO,
1486 .sub = axi_error,
1487 },
1488 {
1489 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
1490 .reg = HGC_AXI_FIFO_ERR_INFO,
1491 .sub = fifo_error,
1492 },
1493 {
1494 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
1495 .msg = "LM add/fetch list",
1496 },
1497 {
1498 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
1499 .msg = "SAS_HGC_ABT fetch LM list",
1500 },
1501 };
1502
1503 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
1504 {
1505 u32 irq_value, irq_msk;
1506 struct hisi_hba *hisi_hba = p;
1507 struct device *dev = hisi_hba->dev;
1508 int i;
1509
1510 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1511 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
1512
1513 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
1514 irq_value &= ~irq_msk;
1515
1516 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
1517 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
1518
1519 if (!(irq_value & error->irq_msk))
1520 continue;
1521
1522 if (error->sub) {
1523 const struct hisi_sas_hw_error *sub = error->sub;
1524 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
1525
1526 for (; sub->msk || sub->msg; sub++) {
1527 if (!(err_value & sub->msk))
1528 continue;
1529
1530 dev_err(dev, "%s error (0x%x) found!\n",
1531 sub->msg, irq_value);
1532 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1533 }
1534 } else {
1535 dev_err(dev, "%s error (0x%x) found!\n",
1536 error->msg, irq_value);
1537 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1538 }
1539 }
1540
1541 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
1542 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
1543 u32 dev_id = reg_val & ITCT_DEV_MSK;
1544 struct hisi_sas_device *sas_dev =
1545 &hisi_hba->devices[dev_id];
1546
1547 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
1548 dev_dbg(dev, "clear ITCT ok\n");
1549 complete(sas_dev->completion);
1550 }
1551
1552 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
1553 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
1554
1555 return IRQ_HANDLED;
1556 }
1557
1558 static void
1559 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1560 struct hisi_sas_slot *slot)
1561 {
1562 struct task_status_struct *ts = &task->task_status;
1563 struct hisi_sas_complete_v3_hdr *complete_queue =
1564 hisi_hba->complete_hdr[slot->cmplt_queue];
1565 struct hisi_sas_complete_v3_hdr *complete_hdr =
1566 &complete_queue[slot->cmplt_queue_slot];
1567 struct hisi_sas_err_record_v3 *record =
1568 hisi_sas_status_buf_addr_mem(slot);
1569 u32 dma_rx_err_type = record->dma_rx_err_type;
1570 u32 trans_tx_fail_type = record->trans_tx_fail_type;
1571
1572 switch (task->task_proto) {
1573 case SAS_PROTOCOL_SSP:
1574 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1575 ts->residual = trans_tx_fail_type;
1576 ts->stat = SAS_DATA_UNDERRUN;
1577 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1578 ts->stat = SAS_QUEUE_FULL;
1579 slot->abort = 1;
1580 } else {
1581 ts->stat = SAS_OPEN_REJECT;
1582 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1583 }
1584 break;
1585 case SAS_PROTOCOL_SATA:
1586 case SAS_PROTOCOL_STP:
1587 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1588 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1589 ts->residual = trans_tx_fail_type;
1590 ts->stat = SAS_DATA_UNDERRUN;
1591 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1592 ts->stat = SAS_PHY_DOWN;
1593 slot->abort = 1;
1594 } else {
1595 ts->stat = SAS_OPEN_REJECT;
1596 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1597 }
1598 hisi_sas_sata_done(task, slot);
1599 break;
1600 case SAS_PROTOCOL_SMP:
1601 ts->stat = SAM_STAT_CHECK_CONDITION;
1602 break;
1603 default:
1604 break;
1605 }
1606 }
1607
1608 static int
1609 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1610 {
1611 struct sas_task *task = slot->task;
1612 struct hisi_sas_device *sas_dev;
1613 struct device *dev = hisi_hba->dev;
1614 struct task_status_struct *ts;
1615 struct domain_device *device;
1616 struct sas_ha_struct *ha;
1617 enum exec_status sts;
1618 struct hisi_sas_complete_v3_hdr *complete_queue =
1619 hisi_hba->complete_hdr[slot->cmplt_queue];
1620 struct hisi_sas_complete_v3_hdr *complete_hdr =
1621 &complete_queue[slot->cmplt_queue_slot];
1622 unsigned long flags;
1623 bool is_internal = slot->is_internal;
1624
1625 if (unlikely(!task || !task->lldd_task || !task->dev))
1626 return -EINVAL;
1627
1628 ts = &task->task_status;
1629 device = task->dev;
1630 ha = device->port->ha;
1631 sas_dev = device->lldd_dev;
1632
1633 spin_lock_irqsave(&task->task_state_lock, flags);
1634 task->task_state_flags &=
1635 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1636 spin_unlock_irqrestore(&task->task_state_lock, flags);
1637
1638 memset(ts, 0, sizeof(*ts));
1639 ts->resp = SAS_TASK_COMPLETE;
1640
1641 if (unlikely(!sas_dev)) {
1642 dev_dbg(dev, "slot complete: port has not device\n");
1643 ts->stat = SAS_PHY_DOWN;
1644 goto out;
1645 }
1646
1647 /*
1648 * Use SAS+TMF status codes
1649 */
1650 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1651 >> CMPLT_HDR_ABORT_STAT_OFF) {
1652 case STAT_IO_ABORTED:
1653 /* this IO has been aborted by abort command */
1654 ts->stat = SAS_ABORTED_TASK;
1655 goto out;
1656 case STAT_IO_COMPLETE:
1657 /* internal abort command complete */
1658 ts->stat = TMF_RESP_FUNC_SUCC;
1659 goto out;
1660 case STAT_IO_NO_DEVICE:
1661 ts->stat = TMF_RESP_FUNC_COMPLETE;
1662 goto out;
1663 case STAT_IO_NOT_VALID:
1664 /*
1665 * abort single IO, the controller can't find the IO
1666 */
1667 ts->stat = TMF_RESP_FUNC_FAILED;
1668 goto out;
1669 default:
1670 break;
1671 }
1672
1673 /* check for erroneous completion */
1674 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1675 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
1676
1677 slot_err_v3_hw(hisi_hba, task, slot);
1678 if (ts->stat != SAS_DATA_UNDERRUN)
1679 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
1680 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
1681 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
1682 slot->idx, task, sas_dev->device_id,
1683 complete_hdr->dw0, complete_hdr->dw1,
1684 complete_hdr->act, complete_hdr->dw3,
1685 error_info[0], error_info[1],
1686 error_info[2], error_info[3]);
1687 if (unlikely(slot->abort))
1688 return ts->stat;
1689 goto out;
1690 }
1691
1692 switch (task->task_proto) {
1693 case SAS_PROTOCOL_SSP: {
1694 struct ssp_response_iu *iu =
1695 hisi_sas_status_buf_addr_mem(slot) +
1696 sizeof(struct hisi_sas_err_record);
1697
1698 sas_ssp_task_response(dev, task, iu);
1699 break;
1700 }
1701 case SAS_PROTOCOL_SMP: {
1702 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1703 void *to;
1704
1705 ts->stat = SAM_STAT_GOOD;
1706 to = kmap_atomic(sg_page(sg_resp));
1707
1708 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1709 DMA_FROM_DEVICE);
1710 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1711 DMA_TO_DEVICE);
1712 memcpy(to + sg_resp->offset,
1713 hisi_sas_status_buf_addr_mem(slot) +
1714 sizeof(struct hisi_sas_err_record),
1715 sg_dma_len(sg_resp));
1716 kunmap_atomic(to);
1717 break;
1718 }
1719 case SAS_PROTOCOL_SATA:
1720 case SAS_PROTOCOL_STP:
1721 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1722 ts->stat = SAM_STAT_GOOD;
1723 hisi_sas_sata_done(task, slot);
1724 break;
1725 default:
1726 ts->stat = SAM_STAT_CHECK_CONDITION;
1727 break;
1728 }
1729
1730 if (!slot->port->port_attached) {
1731 dev_warn(dev, "slot complete: port %d has removed\n",
1732 slot->port->sas_port.id);
1733 ts->stat = SAS_PHY_DOWN;
1734 }
1735
1736 out:
1737 hisi_sas_slot_task_free(hisi_hba, task, slot);
1738 sts = ts->stat;
1739 spin_lock_irqsave(&task->task_state_lock, flags);
1740 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
1741 spin_unlock_irqrestore(&task->task_state_lock, flags);
1742 dev_info(dev, "slot complete: task(%p) aborted\n", task);
1743 return SAS_ABORTED_TASK;
1744 }
1745 task->task_state_flags |= SAS_TASK_STATE_DONE;
1746 spin_unlock_irqrestore(&task->task_state_lock, flags);
1747
1748 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
1749 spin_lock_irqsave(&device->done_lock, flags);
1750 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
1751 spin_unlock_irqrestore(&device->done_lock, flags);
1752 dev_info(dev, "slot complete: task(%p) ignored\n ",
1753 task);
1754 return sts;
1755 }
1756 spin_unlock_irqrestore(&device->done_lock, flags);
1757 }
1758
1759 if (task->task_done)
1760 task->task_done(task);
1761
1762 return sts;
1763 }
1764
1765 static void cq_tasklet_v3_hw(unsigned long val)
1766 {
1767 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1768 struct hisi_hba *hisi_hba = cq->hisi_hba;
1769 struct hisi_sas_slot *slot;
1770 struct hisi_sas_complete_v3_hdr *complete_queue;
1771 u32 rd_point = cq->rd_point, wr_point;
1772 int queue = cq->id;
1773
1774 complete_queue = hisi_hba->complete_hdr[queue];
1775
1776 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1777 (0x14 * queue));
1778
1779 while (rd_point != wr_point) {
1780 struct hisi_sas_complete_v3_hdr *complete_hdr;
1781 struct device *dev = hisi_hba->dev;
1782 int iptt;
1783
1784 complete_hdr = &complete_queue[rd_point];
1785
1786 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1787 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
1788 slot = &hisi_hba->slot_info[iptt];
1789 slot->cmplt_queue_slot = rd_point;
1790 slot->cmplt_queue = queue;
1791 slot_complete_v3_hw(hisi_hba, slot);
1792 } else
1793 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
1794
1795 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1796 rd_point = 0;
1797 }
1798
1799 /* update rd_point */
1800 cq->rd_point = rd_point;
1801 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1802 }
1803
1804 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1805 {
1806 struct hisi_sas_cq *cq = p;
1807 struct hisi_hba *hisi_hba = cq->hisi_hba;
1808 int queue = cq->id;
1809
1810 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1811
1812 tasklet_schedule(&cq->tasklet);
1813
1814 return IRQ_HANDLED;
1815 }
1816
1817 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1818 {
1819 struct device *dev = hisi_hba->dev;
1820 struct pci_dev *pdev = hisi_hba->pci_dev;
1821 int vectors, rc;
1822 int i, k;
1823 int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1824
1825 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1826 max_msi, PCI_IRQ_MSI);
1827 if (vectors < max_msi) {
1828 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1829 return -ENOENT;
1830 }
1831
1832 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1833 int_phy_up_down_bcast_v3_hw, 0,
1834 DRV_NAME " phy", hisi_hba);
1835 if (rc) {
1836 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1837 rc = -ENOENT;
1838 goto free_irq_vectors;
1839 }
1840
1841 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1842 int_chnl_int_v3_hw, 0,
1843 DRV_NAME " channel", hisi_hba);
1844 if (rc) {
1845 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1846 rc = -ENOENT;
1847 goto free_phy_irq;
1848 }
1849
1850 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
1851 fatal_axi_int_v3_hw, 0,
1852 DRV_NAME " fatal", hisi_hba);
1853 if (rc) {
1854 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
1855 rc = -ENOENT;
1856 goto free_chnl_interrupt;
1857 }
1858
1859 /* Init tasklets for cq only */
1860 for (i = 0; i < hisi_hba->queue_count; i++) {
1861 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1862 struct tasklet_struct *t = &cq->tasklet;
1863
1864 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1865 cq_interrupt_v3_hw, 0,
1866 DRV_NAME " cq", cq);
1867 if (rc) {
1868 dev_err(dev,
1869 "could not request cq%d interrupt, rc=%d\n",
1870 i, rc);
1871 rc = -ENOENT;
1872 goto free_cq_irqs;
1873 }
1874
1875 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1876 }
1877
1878 return 0;
1879
1880 free_cq_irqs:
1881 for (k = 0; k < i; k++) {
1882 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1883
1884 free_irq(pci_irq_vector(pdev, k+16), cq);
1885 }
1886 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
1887 free_chnl_interrupt:
1888 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1889 free_phy_irq:
1890 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1891 free_irq_vectors:
1892 pci_free_irq_vectors(pdev);
1893 return rc;
1894 }
1895
1896 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1897 {
1898 int rc;
1899
1900 rc = hw_init_v3_hw(hisi_hba);
1901 if (rc)
1902 return rc;
1903
1904 rc = interrupt_init_v3_hw(hisi_hba);
1905 if (rc)
1906 return rc;
1907
1908 return 0;
1909 }
1910
1911 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
1912 struct sas_phy_linkrates *r)
1913 {
1914 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1915 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1916 enum sas_linkrate min, max;
1917 u32 prog_phy_link_rate = 0x800;
1918
1919 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1920 max = sas_phy->phy->maximum_linkrate;
1921 min = r->minimum_linkrate;
1922 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1923 max = r->maximum_linkrate;
1924 min = sas_phy->phy->minimum_linkrate;
1925 } else
1926 return;
1927
1928 sas_phy->phy->maximum_linkrate = max;
1929 sas_phy->phy->minimum_linkrate = min;
1930 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
1931
1932 disable_phy_v3_hw(hisi_hba, phy_no);
1933 msleep(100);
1934 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1935 prog_phy_link_rate);
1936 start_phy_v3_hw(hisi_hba, phy_no);
1937 }
1938
1939 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
1940 {
1941 struct pci_dev *pdev = hisi_hba->pci_dev;
1942 int i;
1943
1944 synchronize_irq(pci_irq_vector(pdev, 1));
1945 synchronize_irq(pci_irq_vector(pdev, 2));
1946 synchronize_irq(pci_irq_vector(pdev, 11));
1947 for (i = 0; i < hisi_hba->queue_count; i++) {
1948 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
1949 synchronize_irq(pci_irq_vector(pdev, i + 16));
1950 }
1951
1952 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
1953 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
1954 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
1955 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1956
1957 for (i = 0; i < hisi_hba->n_phy; i++) {
1958 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1959 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
1960 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
1961 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
1962 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
1963 }
1964 }
1965
1966 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
1967 {
1968 return hisi_sas_read32(hisi_hba, PHY_STATE);
1969 }
1970
1971 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1972 {
1973 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1974 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1975 struct sas_phy *sphy = sas_phy->phy;
1976 u32 reg_value;
1977
1978 /* loss dword sync */
1979 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1980 sphy->loss_of_dword_sync_count += reg_value;
1981
1982 /* phy reset problem */
1983 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1984 sphy->phy_reset_problem_count += reg_value;
1985
1986 /* invalid dword */
1987 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1988 sphy->invalid_dword_count += reg_value;
1989
1990 /* disparity err */
1991 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1992 sphy->running_disparity_error_count += reg_value;
1993
1994 }
1995
1996 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
1997 {
1998 struct device *dev = hisi_hba->dev;
1999 int rc;
2000 u32 status;
2001
2002 interrupt_disable_v3_hw(hisi_hba);
2003 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2004 hisi_sas_kill_tasklets(hisi_hba);
2005
2006 hisi_sas_stop_phys(hisi_hba);
2007
2008 mdelay(10);
2009
2010 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
2011
2012 /* wait until bus idle */
2013 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2014 AM_CURR_TRANS_RETURN, status,
2015 status == 0x3, 10, 100);
2016 if (rc) {
2017 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
2018 return rc;
2019 }
2020
2021 hisi_sas_init_mem(hisi_hba);
2022
2023 return hw_init_v3_hw(hisi_hba);
2024 }
2025
2026 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2027 u8 reg_index, u8 reg_count, u8 *write_data)
2028 {
2029 struct device *dev = hisi_hba->dev;
2030 u32 *data = (u32 *)write_data;
2031 int i;
2032
2033 switch (reg_type) {
2034 case SAS_GPIO_REG_TX:
2035 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2036 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2037 reg_index, reg_index + reg_count - 1);
2038 return -EINVAL;
2039 }
2040
2041 for (i = 0; i < reg_count; i++)
2042 hisi_sas_write32(hisi_hba,
2043 SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2044 data[i]);
2045 break;
2046 default:
2047 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2048 reg_type);
2049 return -EINVAL;
2050 }
2051
2052 return 0;
2053 }
2054
2055 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2056 int delay_ms, int timeout_ms)
2057 {
2058 struct device *dev = hisi_hba->dev;
2059 int entries, entries_old = 0, time;
2060
2061 for (time = 0; time < timeout_ms; time += delay_ms) {
2062 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2063 if (entries == entries_old)
2064 break;
2065
2066 entries_old = entries;
2067 msleep(delay_ms);
2068 }
2069
2070 dev_dbg(dev, "wait commands complete %dms\n", time);
2071 }
2072
2073 static struct scsi_host_template sht_v3_hw = {
2074 .name = DRV_NAME,
2075 .module = THIS_MODULE,
2076 .queuecommand = sas_queuecommand,
2077 .target_alloc = sas_target_alloc,
2078 .slave_configure = hisi_sas_slave_configure,
2079 .scan_finished = hisi_sas_scan_finished,
2080 .scan_start = hisi_sas_scan_start,
2081 .change_queue_depth = sas_change_queue_depth,
2082 .bios_param = sas_bios_param,
2083 .can_queue = 1,
2084 .this_id = -1,
2085 .sg_tablesize = SG_ALL,
2086 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
2087 .use_clustering = ENABLE_CLUSTERING,
2088 .eh_device_reset_handler = sas_eh_device_reset_handler,
2089 .eh_target_reset_handler = sas_eh_target_reset_handler,
2090 .target_destroy = sas_target_destroy,
2091 .ioctl = sas_ioctl,
2092 .shost_attrs = host_attrs,
2093 };
2094
2095 static const struct hisi_sas_hw hisi_sas_v3_hw = {
2096 .hw_init = hisi_sas_v3_init,
2097 .setup_itct = setup_itct_v3_hw,
2098 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
2099 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
2100 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
2101 .clear_itct = clear_itct_v3_hw,
2102 .sl_notify = sl_notify_v3_hw,
2103 .prep_ssp = prep_ssp_v3_hw,
2104 .prep_smp = prep_smp_v3_hw,
2105 .prep_stp = prep_ata_v3_hw,
2106 .prep_abort = prep_abort_v3_hw,
2107 .get_free_slot = get_free_slot_v3_hw,
2108 .start_delivery = start_delivery_v3_hw,
2109 .slot_complete = slot_complete_v3_hw,
2110 .phys_init = phys_init_v3_hw,
2111 .phy_start = start_phy_v3_hw,
2112 .phy_disable = disable_phy_v3_hw,
2113 .phy_hard_reset = phy_hard_reset_v3_hw,
2114 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
2115 .phy_set_linkrate = phy_set_linkrate_v3_hw,
2116 .dereg_device = dereg_device_v3_hw,
2117 .soft_reset = soft_reset_v3_hw,
2118 .get_phys_state = get_phys_state_v3_hw,
2119 .get_events = phy_get_events_v3_hw,
2120 .write_gpio = write_gpio_v3_hw,
2121 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
2122 };
2123
2124 static struct Scsi_Host *
2125 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
2126 {
2127 struct Scsi_Host *shost;
2128 struct hisi_hba *hisi_hba;
2129 struct device *dev = &pdev->dev;
2130
2131 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
2132 if (!shost) {
2133 dev_err(dev, "shost alloc failed\n");
2134 return NULL;
2135 }
2136 hisi_hba = shost_priv(shost);
2137
2138 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
2139 hisi_hba->hw = &hisi_sas_v3_hw;
2140 hisi_hba->pci_dev = pdev;
2141 hisi_hba->dev = dev;
2142 hisi_hba->shost = shost;
2143 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
2144
2145 timer_setup(&hisi_hba->timer, NULL, 0);
2146
2147 if (hisi_sas_get_fw_info(hisi_hba) < 0)
2148 goto err_out;
2149
2150 if (hisi_sas_alloc(hisi_hba, shost)) {
2151 hisi_sas_free(hisi_hba);
2152 goto err_out;
2153 }
2154
2155 return shost;
2156 err_out:
2157 scsi_host_put(shost);
2158 dev_err(dev, "shost alloc failed\n");
2159 return NULL;
2160 }
2161
2162 static int
2163 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2164 {
2165 struct Scsi_Host *shost;
2166 struct hisi_hba *hisi_hba;
2167 struct device *dev = &pdev->dev;
2168 struct asd_sas_phy **arr_phy;
2169 struct asd_sas_port **arr_port;
2170 struct sas_ha_struct *sha;
2171 int rc, phy_nr, port_nr, i;
2172
2173 rc = pci_enable_device(pdev);
2174 if (rc)
2175 goto err_out;
2176
2177 pci_set_master(pdev);
2178
2179 rc = pci_request_regions(pdev, DRV_NAME);
2180 if (rc)
2181 goto err_out_disable_device;
2182
2183 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
2184 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
2185 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2186 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2187 dev_err(dev, "No usable DMA addressing method\n");
2188 rc = -EIO;
2189 goto err_out_regions;
2190 }
2191 }
2192
2193 shost = hisi_sas_shost_alloc_pci(pdev);
2194 if (!shost) {
2195 rc = -ENOMEM;
2196 goto err_out_regions;
2197 }
2198
2199 sha = SHOST_TO_SAS_HA(shost);
2200 hisi_hba = shost_priv(shost);
2201 dev_set_drvdata(dev, sha);
2202
2203 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
2204 if (!hisi_hba->regs) {
2205 dev_err(dev, "cannot map register.\n");
2206 rc = -ENOMEM;
2207 goto err_out_ha;
2208 }
2209
2210 phy_nr = port_nr = hisi_hba->n_phy;
2211
2212 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
2213 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
2214 if (!arr_phy || !arr_port) {
2215 rc = -ENOMEM;
2216 goto err_out_ha;
2217 }
2218
2219 sha->sas_phy = arr_phy;
2220 sha->sas_port = arr_port;
2221 sha->core.shost = shost;
2222 sha->lldd_ha = hisi_hba;
2223
2224 shost->transportt = hisi_sas_stt;
2225 shost->max_id = HISI_SAS_MAX_DEVICES;
2226 shost->max_lun = ~0;
2227 shost->max_channel = 1;
2228 shost->max_cmd_len = 16;
2229 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
2230 shost->can_queue = hisi_hba->hw->max_command_entries;
2231 shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
2232
2233 sha->sas_ha_name = DRV_NAME;
2234 sha->dev = dev;
2235 sha->lldd_module = THIS_MODULE;
2236 sha->sas_addr = &hisi_hba->sas_addr[0];
2237 sha->num_phys = hisi_hba->n_phy;
2238 sha->core.shost = hisi_hba->shost;
2239
2240 for (i = 0; i < hisi_hba->n_phy; i++) {
2241 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
2242 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
2243 }
2244
2245 hisi_sas_init_add(hisi_hba);
2246
2247 rc = scsi_add_host(shost, dev);
2248 if (rc)
2249 goto err_out_ha;
2250
2251 rc = sas_register_ha(sha);
2252 if (rc)
2253 goto err_out_register_ha;
2254
2255 rc = hisi_hba->hw->hw_init(hisi_hba);
2256 if (rc)
2257 goto err_out_register_ha;
2258
2259 scsi_scan_host(shost);
2260
2261 return 0;
2262
2263 err_out_register_ha:
2264 scsi_remove_host(shost);
2265 err_out_ha:
2266 scsi_host_put(shost);
2267 err_out_regions:
2268 pci_release_regions(pdev);
2269 err_out_disable_device:
2270 pci_disable_device(pdev);
2271 err_out:
2272 return rc;
2273 }
2274
2275 static void
2276 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
2277 {
2278 int i;
2279
2280 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2281 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2282 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2283 for (i = 0; i < hisi_hba->queue_count; i++) {
2284 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2285
2286 free_irq(pci_irq_vector(pdev, i+16), cq);
2287 }
2288 pci_free_irq_vectors(pdev);
2289 }
2290
2291 static void hisi_sas_v3_remove(struct pci_dev *pdev)
2292 {
2293 struct device *dev = &pdev->dev;
2294 struct sas_ha_struct *sha = dev_get_drvdata(dev);
2295 struct hisi_hba *hisi_hba = sha->lldd_ha;
2296 struct Scsi_Host *shost = sha->core.shost;
2297
2298 if (timer_pending(&hisi_hba->timer))
2299 del_timer(&hisi_hba->timer);
2300
2301 sas_unregister_ha(sha);
2302 sas_remove_host(sha->core.shost);
2303
2304 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
2305 hisi_sas_kill_tasklets(hisi_hba);
2306 pci_release_regions(pdev);
2307 pci_disable_device(pdev);
2308 hisi_sas_free(hisi_hba);
2309 scsi_host_put(shost);
2310 }
2311
2312 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = {
2313 { .irq_msk = BIT(19), .msg = "HILINK_INT" },
2314 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" },
2315 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" },
2316 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" },
2317 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" },
2318 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" },
2319 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" },
2320 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" },
2321 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" },
2322 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" },
2323 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" },
2324 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" },
2325 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" },
2326 };
2327
2328 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = {
2329 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" },
2330 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" },
2331 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" },
2332 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" },
2333 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" },
2334 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" },
2335 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" },
2336 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" },
2337 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" },
2338 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" },
2339 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" },
2340 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" },
2341 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" },
2342 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" },
2343 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" },
2344 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" },
2345 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" },
2346 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" },
2347 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" },
2348 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" },
2349 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" },
2350 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" },
2351 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" },
2352 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" },
2353 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" },
2354 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" },
2355 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" },
2356 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" },
2357 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" },
2358 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" },
2359 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" },
2360 };
2361
2362 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = {
2363 { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" },
2364 { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" },
2365 { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" },
2366 { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" },
2367 { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" },
2368 { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" },
2369 { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" },
2370 { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" },
2371 { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" },
2372 { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" },
2373 { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" },
2374 { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" },
2375 { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" },
2376 { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" },
2377 { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" },
2378 { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" },
2379 { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" },
2380 { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" },
2381 { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" },
2382 { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" },
2383 };
2384
2385 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba)
2386 {
2387 struct device *dev = hisi_hba->dev;
2388 const struct hisi_sas_hw_error *ras_error;
2389 bool need_reset = false;
2390 u32 irq_value;
2391 int i;
2392
2393 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0);
2394 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) {
2395 ras_error = &sas_ras_intr0_nfe[i];
2396 if (ras_error->irq_msk & irq_value) {
2397 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n",
2398 ras_error->msg, irq_value);
2399 need_reset = true;
2400 }
2401 }
2402 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value);
2403
2404 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1);
2405 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) {
2406 ras_error = &sas_ras_intr1_nfe[i];
2407 if (ras_error->irq_msk & irq_value) {
2408 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n",
2409 ras_error->msg, irq_value);
2410 need_reset = true;
2411 }
2412 }
2413 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value);
2414
2415 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2);
2416 for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) {
2417 ras_error = &sas_ras_intr2_nfe[i];
2418 if (ras_error->irq_msk & irq_value) {
2419 dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n",
2420 ras_error->msg, irq_value);
2421 need_reset = true;
2422 }
2423 }
2424 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value);
2425
2426 return need_reset;
2427 }
2428
2429 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev,
2430 pci_channel_state_t state)
2431 {
2432 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2433 struct hisi_hba *hisi_hba = sha->lldd_ha;
2434 struct device *dev = hisi_hba->dev;
2435
2436 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state);
2437 if (state == pci_channel_io_perm_failure)
2438 return PCI_ERS_RESULT_DISCONNECT;
2439
2440 if (process_non_fatal_error_v3_hw(hisi_hba))
2441 return PCI_ERS_RESULT_NEED_RESET;
2442
2443 return PCI_ERS_RESULT_CAN_RECOVER;
2444 }
2445
2446 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev)
2447 {
2448 return PCI_ERS_RESULT_RECOVERED;
2449 }
2450
2451 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev)
2452 {
2453 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2454 struct hisi_hba *hisi_hba = sha->lldd_ha;
2455 struct device *dev = hisi_hba->dev;
2456 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r);
2457
2458 dev_info(dev, "PCI error: slot reset callback!!\n");
2459 queue_work(hisi_hba->wq, &r.work);
2460 wait_for_completion(r.completion);
2461 if (r.done)
2462 return PCI_ERS_RESULT_RECOVERED;
2463
2464 return PCI_ERS_RESULT_DISCONNECT;
2465 }
2466
2467 enum {
2468 /* instances of the controller */
2469 hip08,
2470 };
2471
2472 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state)
2473 {
2474 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2475 struct hisi_hba *hisi_hba = sha->lldd_ha;
2476 struct device *dev = hisi_hba->dev;
2477 struct Scsi_Host *shost = hisi_hba->shost;
2478 u32 device_state, status;
2479 int rc;
2480 u32 reg_val;
2481
2482 if (!pdev->pm_cap) {
2483 dev_err(dev, "PCI PM not supported\n");
2484 return -ENODEV;
2485 }
2486
2487 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
2488 return -1;
2489
2490 scsi_block_requests(shost);
2491 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2492 flush_workqueue(hisi_hba->wq);
2493 /* disable DQ/PHY/bus */
2494 interrupt_disable_v3_hw(hisi_hba);
2495 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2496 hisi_sas_kill_tasklets(hisi_hba);
2497
2498 hisi_sas_stop_phys(hisi_hba);
2499
2500 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2501 AM_CTRL_GLOBAL);
2502 reg_val |= 0x1;
2503 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2504 AM_CTRL_GLOBAL, reg_val);
2505
2506 /* wait until bus idle */
2507 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2508 AM_CURR_TRANS_RETURN, status,
2509 status == 0x3, 10, 100);
2510 if (rc) {
2511 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
2512 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2513 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2514 scsi_unblock_requests(shost);
2515 return rc;
2516 }
2517
2518 hisi_sas_init_mem(hisi_hba);
2519
2520 device_state = pci_choose_state(pdev, state);
2521 dev_warn(dev, "entering operating state [D%d]\n",
2522 device_state);
2523 pci_save_state(pdev);
2524 pci_disable_device(pdev);
2525 pci_set_power_state(pdev, device_state);
2526
2527 hisi_sas_release_tasks(hisi_hba);
2528
2529 sas_suspend_ha(sha);
2530 return 0;
2531 }
2532
2533 static int hisi_sas_v3_resume(struct pci_dev *pdev)
2534 {
2535 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2536 struct hisi_hba *hisi_hba = sha->lldd_ha;
2537 struct Scsi_Host *shost = hisi_hba->shost;
2538 struct device *dev = hisi_hba->dev;
2539 unsigned int rc;
2540 u32 device_state = pdev->current_state;
2541
2542 dev_warn(dev, "resuming from operating state [D%d]\n",
2543 device_state);
2544 pci_set_power_state(pdev, PCI_D0);
2545 pci_enable_wake(pdev, PCI_D0, 0);
2546 pci_restore_state(pdev);
2547 rc = pci_enable_device(pdev);
2548 if (rc)
2549 dev_err(dev, "enable device failed during resume (%d)\n", rc);
2550
2551 pci_set_master(pdev);
2552 scsi_unblock_requests(shost);
2553 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2554
2555 sas_prep_resume_ha(sha);
2556 init_reg_v3_hw(hisi_hba);
2557 hisi_hba->hw->phys_init(hisi_hba);
2558 sas_resume_ha(sha);
2559 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2560
2561 return 0;
2562 }
2563
2564 static const struct pci_device_id sas_v3_pci_table[] = {
2565 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
2566 {}
2567 };
2568 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
2569
2570 static const struct pci_error_handlers hisi_sas_err_handler = {
2571 .error_detected = hisi_sas_error_detected_v3_hw,
2572 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw,
2573 .slot_reset = hisi_sas_slot_reset_v3_hw,
2574 };
2575
2576 static struct pci_driver sas_v3_pci_driver = {
2577 .name = DRV_NAME,
2578 .id_table = sas_v3_pci_table,
2579 .probe = hisi_sas_v3_probe,
2580 .remove = hisi_sas_v3_remove,
2581 .suspend = hisi_sas_v3_suspend,
2582 .resume = hisi_sas_v3_resume,
2583 .err_handler = &hisi_sas_err_handler,
2584 };
2585
2586 module_pci_driver(sas_v3_pci_driver);
2587
2588 MODULE_LICENSE("GPL");
2589 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2590 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2591 MODULE_ALIAS("pci:" DRV_NAME);
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