2 * Copyright (c) 2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
12 #define DRV_NAME "hisi_sas_v3_hw"
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
26 #define AXI_AHB_CLK_CFG 0x3c
28 #define ITCT_CLR_EN_OFF 16
29 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
30 #define ITCT_DEV_OFF 0
31 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
32 #define AXI_USER1 0x48
33 #define AXI_USER2 0x4c
34 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
35 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
36 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
37 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
38 #define CFG_MAX_TAG 0x68
39 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
40 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
41 #define HGC_GET_ITV_TIME 0x90
42 #define DEVICE_MSG_WORK_MODE 0x94
43 #define OPENA_WT_CONTI_TIME 0x9c
44 #define I_T_NEXUS_LOSS_TIME 0xa0
45 #define MAX_CON_TIME_LIMIT_TIME 0xa4
46 #define BUS_INACTIVE_LIMIT_TIME 0xa8
47 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
48 #define CFG_AGING_TIME 0xbc
49 #define HGC_DFX_CFG2 0xc0
50 #define CFG_ABT_SET_QUERY_IPTT 0xd4
51 #define CFG_SET_ABORTED_IPTT_OFF 0
52 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
53 #define CFG_SET_ABORTED_EN_OFF 12
54 #define CFG_ABT_SET_IPTT_DONE 0xd8
55 #define CFG_ABT_SET_IPTT_DONE_OFF 0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define CHNL_INT_STATUS 0x148
59 #define INT_COAL_EN 0x19c
60 #define OQ_INT_COAL_TIME 0x1a0
61 #define OQ_INT_COAL_CNT 0x1a4
62 #define ENT_INT_COAL_TIME 0x1a8
63 #define ENT_INT_COAL_CNT 0x1ac
64 #define OQ_INT_SRC 0x1b0
65 #define OQ_INT_SRC_MSK 0x1b4
66 #define ENT_INT_SRC1 0x1b8
67 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
68 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
69 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
70 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
71 #define ENT_INT_SRC2 0x1bc
72 #define ENT_INT_SRC3 0x1c0
73 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
74 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
75 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
76 #define ENT_INT_SRC3_AXI_OFF 11
77 #define ENT_INT_SRC3_FIFO_OFF 12
78 #define ENT_INT_SRC3_LM_OFF 14
79 #define ENT_INT_SRC3_ITC_INT_OFF 15
80 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
81 #define ENT_INT_SRC3_ABT_OFF 16
82 #define ENT_INT_SRC_MSK1 0x1c4
83 #define ENT_INT_SRC_MSK2 0x1c8
84 #define ENT_INT_SRC_MSK3 0x1cc
85 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
86 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
87 #define CHNL_ENT_INT_MSK 0x1d4
88 #define HGC_COM_INT_MSK 0x1d8
89 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
90 #define SAS_ECC_INTR 0x1e8
91 #define SAS_ECC_INTR_MSK 0x1ec
92 #define HGC_ERR_STAT_EN 0x238
93 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
94 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
95 #define DLVRY_Q_0_DEPTH 0x268
96 #define DLVRY_Q_0_WR_PTR 0x26c
97 #define DLVRY_Q_0_RD_PTR 0x270
98 #define HYPER_STREAM_ID_EN_CFG 0xc80
99 #define OQ0_INT_SRC_MSK 0xc90
100 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
101 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
102 #define COMPL_Q_0_DEPTH 0x4e8
103 #define COMPL_Q_0_WR_PTR 0x4ec
104 #define COMPL_Q_0_RD_PTR 0x4f0
105 #define AWQOS_AWCACHE_CFG 0xc84
106 #define ARQOS_ARCACHE_CFG 0xc88
108 /* phy registers requiring init */
109 #define PORT_BASE (0x2000)
110 #define PHY_CFG (PORT_BASE + 0x0)
111 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
112 #define PHY_CFG_ENA_OFF 0
113 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
114 #define PHY_CFG_DC_OPT_OFF 2
115 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
116 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
117 #define PHY_CTRL (PORT_BASE + 0x14)
118 #define PHY_CTRL_RESET_OFF 0
119 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
120 #define SL_CFG (PORT_BASE + 0x84)
121 #define SL_CONTROL (PORT_BASE + 0x94)
122 #define SL_CONTROL_NOTIFY_EN_OFF 0
123 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
124 #define SL_CTA_OFF 17
125 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
126 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
127 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
128 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
129 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
130 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
131 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
132 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
133 #define TXID_AUTO (PORT_BASE + 0xb8)
135 #define CT3_MSK (0x1 << CT3_OFF)
136 #define TX_HARDRST_OFF 2
137 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
138 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
139 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
140 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
141 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
142 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
143 #define CHL_INT0 (PORT_BASE + 0x1b4)
144 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
145 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
146 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
147 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
148 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
149 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
150 #define CHL_INT0_NOT_RDY_OFF 4
151 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
152 #define CHL_INT0_PHY_RDY_OFF 5
153 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
154 #define CHL_INT1 (PORT_BASE + 0x1b8)
155 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
156 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
157 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
158 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
159 #define CHL_INT2 (PORT_BASE + 0x1bc)
160 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
161 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
162 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
163 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
164 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
165 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
166 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
167 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
168 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
169 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
171 /* HW dma structures */
172 /* Delivery queue header */
174 #define CMD_HDR_ABORT_FLAG_OFF 0
175 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
176 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
177 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
178 #define CMD_HDR_RESP_REPORT_OFF 5
179 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
180 #define CMD_HDR_TLR_CTRL_OFF 6
181 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
182 #define CMD_HDR_PORT_OFF 18
183 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
184 #define CMD_HDR_PRIORITY_OFF 27
185 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
186 #define CMD_HDR_CMD_OFF 29
187 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
189 #define CMD_HDR_UNCON_CMD_OFF 3
190 #define CMD_HDR_DIR_OFF 5
191 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
192 #define CMD_HDR_RESET_OFF 7
193 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
194 #define CMD_HDR_VDTL_OFF 10
195 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
196 #define CMD_HDR_FRAME_TYPE_OFF 11
197 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
198 #define CMD_HDR_DEV_ID_OFF 16
199 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
201 #define CMD_HDR_CFL_OFF 0
202 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
203 #define CMD_HDR_NCQ_TAG_OFF 10
204 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
205 #define CMD_HDR_MRFL_OFF 15
206 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
207 #define CMD_HDR_SG_MOD_OFF 24
208 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
210 #define CMD_HDR_IPTT_OFF 0
211 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
213 #define CMD_HDR_DIF_SGL_LEN_OFF 0
214 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
215 #define CMD_HDR_DATA_SGL_LEN_OFF 16
216 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
218 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
219 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
220 #define CMD_HDR_ABORT_IPTT_OFF 16
221 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
223 /* Completion header */
225 #define CMPLT_HDR_CMPLT_OFF 0
226 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
227 #define CMPLT_HDR_ERROR_PHASE_OFF 2
228 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
229 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
230 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
231 #define CMPLT_HDR_ERX_OFF 12
232 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
233 #define CMPLT_HDR_ABORT_STAT_OFF 13
234 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
236 #define STAT_IO_NOT_VALID 0x1
237 #define STAT_IO_NO_DEVICE 0x2
238 #define STAT_IO_COMPLETE 0x3
239 #define STAT_IO_ABORTED 0x4
241 #define CMPLT_HDR_IPTT_OFF 0
242 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
243 #define CMPLT_HDR_DEV_ID_OFF 16
244 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
246 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
247 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
251 #define ITCT_HDR_DEV_TYPE_OFF 0
252 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
253 #define ITCT_HDR_VALID_OFF 2
254 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
255 #define ITCT_HDR_MCR_OFF 5
256 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
257 #define ITCT_HDR_VLN_OFF 9
258 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
259 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
260 #define ITCT_HDR_AWT_CONTINUE_OFF 25
261 #define ITCT_HDR_PORT_ID_OFF 28
262 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
264 #define ITCT_HDR_INLT_OFF 0
265 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
266 #define ITCT_HDR_RTOLT_OFF 48
267 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
269 struct hisi_sas_complete_v3_hdr
{
276 struct hisi_sas_err_record_v3
{
278 __le32 trans_tx_fail_type
;
281 __le32 trans_rx_fail_type
;
284 __le16 dma_tx_err_type
;
285 __le16 sipc_rx_err_type
;
288 __le32 dma_rx_err_type
;
291 #define RX_DATA_LEN_UNDERFLOW_OFF 6
292 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
294 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
295 #define HISI_SAS_MSI_COUNT_V3_HW 32
298 HISI_SAS_PHY_PHY_UPDOWN
,
299 HISI_SAS_PHY_CHNL_INT
,
303 #define DIR_NO_DATA 0
305 #define DIR_TO_DEVICE 2
306 #define DIR_RESERVED 3
308 #define CMD_IS_UNCONSTRAINT(cmd) \
309 ((cmd == ATA_CMD_READ_LOG_EXT) || \
310 (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
311 (cmd == ATA_CMD_DEV_RESET))
313 static u32
hisi_sas_read32(struct hisi_hba
*hisi_hba
, u32 off
)
315 void __iomem
*regs
= hisi_hba
->regs
+ off
;
320 static u32
hisi_sas_read32_relaxed(struct hisi_hba
*hisi_hba
, u32 off
)
322 void __iomem
*regs
= hisi_hba
->regs
+ off
;
324 return readl_relaxed(regs
);
327 static void hisi_sas_write32(struct hisi_hba
*hisi_hba
, u32 off
, u32 val
)
329 void __iomem
*regs
= hisi_hba
->regs
+ off
;
334 static void hisi_sas_phy_write32(struct hisi_hba
*hisi_hba
, int phy_no
,
337 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
342 static u32
hisi_sas_phy_read32(struct hisi_hba
*hisi_hba
,
345 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
350 static void init_reg_v3_hw(struct hisi_hba
*hisi_hba
)
354 /* Global registers init */
355 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
,
356 (u32
)((1ULL << hisi_hba
->queue_count
) - 1));
357 hisi_sas_write32(hisi_hba
, AXI_USER1
, 0x0);
358 hisi_sas_write32(hisi_hba
, AXI_USER2
, 0x40000060);
359 hisi_sas_write32(hisi_hba
, HGC_SAS_TXFAIL_RETRY_CTRL
, 0x108);
360 hisi_sas_write32(hisi_hba
, CFG_1US_TIMER_TRSH
, 0xd);
361 hisi_sas_write32(hisi_hba
, INT_COAL_EN
, 0x1);
362 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_TIME
, 0x1);
363 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_CNT
, 0x1);
364 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 0xffff);
365 hisi_sas_write32(hisi_hba
, ENT_INT_SRC1
, 0xffffffff);
366 hisi_sas_write32(hisi_hba
, ENT_INT_SRC2
, 0xffffffff);
367 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
, 0xffffffff);
368 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0xfefefefe);
369 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0xfefefefe);
370 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0xffffffff);
371 hisi_sas_write32(hisi_hba
, CHNL_PHYUPDOWN_INT_MSK
, 0x0);
372 hisi_sas_write32(hisi_hba
, CHNL_ENT_INT_MSK
, 0x0);
373 hisi_sas_write32(hisi_hba
, HGC_COM_INT_MSK
, 0x0);
374 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0xfff00c30);
375 hisi_sas_write32(hisi_hba
, AWQOS_AWCACHE_CFG
, 0xf0f0);
376 hisi_sas_write32(hisi_hba
, ARQOS_ARCACHE_CFG
, 0xf0f0);
377 for (i
= 0; i
< hisi_hba
->queue_count
; i
++)
378 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+0x4*i
, 0);
380 hisi_sas_write32(hisi_hba
, AXI_AHB_CLK_CFG
, 1);
381 hisi_sas_write32(hisi_hba
, HYPER_STREAM_ID_EN_CFG
, 1);
382 hisi_sas_write32(hisi_hba
, CFG_MAX_TAG
, 0xfff07fff);
384 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
385 hisi_sas_phy_write32(hisi_hba
, i
, PROG_PHY_LINK_RATE
, 0x801);
386 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT0
, 0xffffffff);
387 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1
, 0xffffffff);
388 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2
, 0xffffffff);
389 hisi_sas_phy_write32(hisi_hba
, i
, RXOP_CHECK_CFG_H
, 0x1000);
390 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xffffffff);
391 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0x8ffffbff);
392 hisi_sas_phy_write32(hisi_hba
, i
, SL_CFG
, 0x83f801fc);
393 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL_RDY_MSK
, 0x0);
394 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_NOT_RDY_MSK
, 0x0);
395 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_DWS_RESET_MSK
, 0x0);
396 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_PHY_ENA_MSK
, 0x0);
397 hisi_sas_phy_write32(hisi_hba
, i
, SL_RX_BCAST_CHK_MSK
, 0x0);
398 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_OOB_RESTART_MSK
, 0x0);
399 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL
, 0x199b4fa);
400 hisi_sas_phy_write32(hisi_hba
, i
, SAS_SSP_CON_TIMER_CFG
,
402 hisi_sas_phy_write32(hisi_hba
, i
, SAS_STP_CON_TIMER_CFG
,
405 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
407 hisi_sas_write32(hisi_hba
,
408 DLVRY_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
409 upper_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
411 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
412 lower_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
414 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_DEPTH
+ (i
* 0x14),
415 HISI_SAS_QUEUE_SLOTS
);
417 /* Completion queue */
418 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
419 upper_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
421 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
422 lower_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
424 hisi_sas_write32(hisi_hba
, COMPL_Q_0_DEPTH
+ (i
* 0x14),
425 HISI_SAS_QUEUE_SLOTS
);
429 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_LO
,
430 lower_32_bits(hisi_hba
->itct_dma
));
432 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_HI
,
433 upper_32_bits(hisi_hba
->itct_dma
));
436 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_LO
,
437 lower_32_bits(hisi_hba
->iost_dma
));
439 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_HI
,
440 upper_32_bits(hisi_hba
->iost_dma
));
443 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_LO
,
444 lower_32_bits(hisi_hba
->breakpoint_dma
));
446 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_HI
,
447 upper_32_bits(hisi_hba
->breakpoint_dma
));
449 /* SATA broken msg */
450 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_LO
,
451 lower_32_bits(hisi_hba
->sata_breakpoint_dma
));
453 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_HI
,
454 upper_32_bits(hisi_hba
->sata_breakpoint_dma
));
456 /* SATA initial fis */
457 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_LO
,
458 lower_32_bits(hisi_hba
->initial_fis_dma
));
460 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_HI
,
461 upper_32_bits(hisi_hba
->initial_fis_dma
));
464 static void config_phy_opt_mode_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
466 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
468 cfg
&= ~PHY_CFG_DC_OPT_MSK
;
469 cfg
|= 1 << PHY_CFG_DC_OPT_OFF
;
470 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
473 static void config_id_frame_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
475 struct sas_identify_frame identify_frame
;
476 u32
*identify_buffer
;
478 memset(&identify_frame
, 0, sizeof(identify_frame
));
479 identify_frame
.dev_type
= SAS_END_DEVICE
;
480 identify_frame
.frame_type
= 0;
481 identify_frame
._un1
= 1;
482 identify_frame
.initiator_bits
= SAS_PROTOCOL_ALL
;
483 identify_frame
.target_bits
= SAS_PROTOCOL_NONE
;
484 memcpy(&identify_frame
._un4_11
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
485 memcpy(&identify_frame
.sas_addr
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
486 identify_frame
.phy_id
= phy_no
;
487 identify_buffer
= (u32
*)(&identify_frame
);
489 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD0
,
490 __swab32(identify_buffer
[0]));
491 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD1
,
492 __swab32(identify_buffer
[1]));
493 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD2
,
494 __swab32(identify_buffer
[2]));
495 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD3
,
496 __swab32(identify_buffer
[3]));
497 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD4
,
498 __swab32(identify_buffer
[4]));
499 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD5
,
500 __swab32(identify_buffer
[5]));
503 static void setup_itct_v3_hw(struct hisi_hba
*hisi_hba
,
504 struct hisi_sas_device
*sas_dev
)
506 struct domain_device
*device
= sas_dev
->sas_device
;
507 struct device
*dev
= hisi_hba
->dev
;
508 u64 qw0
, device_id
= sas_dev
->device_id
;
509 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[device_id
];
510 struct domain_device
*parent_dev
= device
->parent
;
511 struct asd_sas_port
*sas_port
= device
->port
;
512 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
514 memset(itct
, 0, sizeof(*itct
));
518 switch (sas_dev
->dev_type
) {
520 case SAS_EDGE_EXPANDER_DEVICE
:
521 case SAS_FANOUT_EXPANDER_DEVICE
:
522 qw0
= HISI_SAS_DEV_TYPE_SSP
<< ITCT_HDR_DEV_TYPE_OFF
;
525 case SAS_SATA_PENDING
:
526 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
527 qw0
= HISI_SAS_DEV_TYPE_STP
<< ITCT_HDR_DEV_TYPE_OFF
;
529 qw0
= HISI_SAS_DEV_TYPE_SATA
<< ITCT_HDR_DEV_TYPE_OFF
;
532 dev_warn(dev
, "setup itct: unsupported dev type (%d)\n",
536 qw0
|= ((1 << ITCT_HDR_VALID_OFF
) |
537 (device
->linkrate
<< ITCT_HDR_MCR_OFF
) |
538 (1 << ITCT_HDR_VLN_OFF
) |
539 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF
) |
540 (1 << ITCT_HDR_AWT_CONTINUE_OFF
) |
541 (port
->id
<< ITCT_HDR_PORT_ID_OFF
));
542 itct
->qw0
= cpu_to_le64(qw0
);
545 memcpy(&itct
->sas_addr
, device
->sas_addr
, SAS_ADDR_SIZE
);
546 itct
->sas_addr
= __swab64(itct
->sas_addr
);
549 if (!dev_is_sata(device
))
550 itct
->qw2
= cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF
) |
551 (0x1ULL
<< ITCT_HDR_RTOLT_OFF
));
554 static void free_device_v3_hw(struct hisi_hba
*hisi_hba
,
555 struct hisi_sas_device
*sas_dev
)
557 u64 dev_id
= sas_dev
->device_id
;
558 struct device
*dev
= hisi_hba
->dev
;
559 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[dev_id
];
560 u32 reg_val
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
562 /* clear the itct interrupt state */
563 if (ENT_INT_SRC3_ITC_INT_MSK
& reg_val
)
564 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
565 ENT_INT_SRC3_ITC_INT_MSK
);
567 /* clear the itct table*/
568 reg_val
= hisi_sas_read32(hisi_hba
, ITCT_CLR
);
569 reg_val
|= ITCT_CLR_EN_MSK
| (dev_id
& ITCT_DEV_MSK
);
570 hisi_sas_write32(hisi_hba
, ITCT_CLR
, reg_val
);
573 reg_val
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
574 if (ENT_INT_SRC3_ITC_INT_MSK
& reg_val
) {
575 dev_dbg(dev
, "got clear ITCT done interrupt\n");
577 /* invalid the itct state*/
578 memset(itct
, 0, sizeof(struct hisi_sas_itct
));
579 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
580 ENT_INT_SRC3_ITC_INT_MSK
);
581 hisi_hba
->devices
[dev_id
].dev_type
= SAS_PHY_UNUSED
;
582 hisi_hba
->devices
[dev_id
].dev_status
= HISI_SAS_DEV_NORMAL
;
585 hisi_sas_write32(hisi_hba
, ITCT_CLR
, 0);
586 dev_dbg(dev
, "clear ITCT ok\n");
590 static void dereg_device_v3_hw(struct hisi_hba
*hisi_hba
,
591 struct domain_device
*device
)
593 struct hisi_sas_slot
*slot
, *slot2
;
594 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
595 u32 cfg_abt_set_query_iptt
;
597 cfg_abt_set_query_iptt
= hisi_sas_read32(hisi_hba
,
598 CFG_ABT_SET_QUERY_IPTT
);
599 list_for_each_entry_safe(slot
, slot2
, &sas_dev
->list
, entry
) {
600 cfg_abt_set_query_iptt
&= ~CFG_SET_ABORTED_IPTT_MSK
;
601 cfg_abt_set_query_iptt
|= (1 << CFG_SET_ABORTED_EN_OFF
) |
602 (slot
->idx
<< CFG_SET_ABORTED_IPTT_OFF
);
603 hisi_sas_write32(hisi_hba
, CFG_ABT_SET_QUERY_IPTT
,
604 cfg_abt_set_query_iptt
);
606 cfg_abt_set_query_iptt
&= ~(1 << CFG_SET_ABORTED_EN_OFF
);
607 hisi_sas_write32(hisi_hba
, CFG_ABT_SET_QUERY_IPTT
,
608 cfg_abt_set_query_iptt
);
609 hisi_sas_write32(hisi_hba
, CFG_ABT_SET_IPTT_DONE
,
610 1 << CFG_ABT_SET_IPTT_DONE_OFF
);
613 static int hw_init_v3_hw(struct hisi_hba
*hisi_hba
)
615 init_reg_v3_hw(hisi_hba
);
620 static void enable_phy_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
622 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
624 cfg
|= PHY_CFG_ENA_MSK
;
625 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
628 static void disable_phy_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
630 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
632 cfg
&= ~PHY_CFG_ENA_MSK
;
633 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
636 static void start_phy_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
638 config_id_frame_v3_hw(hisi_hba
, phy_no
);
639 config_phy_opt_mode_v3_hw(hisi_hba
, phy_no
);
640 enable_phy_v3_hw(hisi_hba
, phy_no
);
643 static void stop_phy_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
645 disable_phy_v3_hw(hisi_hba
, phy_no
);
648 static void start_phys_v3_hw(struct hisi_hba
*hisi_hba
)
652 for (i
= 0; i
< hisi_hba
->n_phy
; i
++)
653 start_phy_v3_hw(hisi_hba
, i
);
656 static void phy_hard_reset_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
658 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
661 stop_phy_v3_hw(hisi_hba
, phy_no
);
662 if (phy
->identify
.device_type
== SAS_END_DEVICE
) {
663 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
664 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
665 txid_auto
| TX_HARDRST_MSK
);
668 start_phy_v3_hw(hisi_hba
, phy_no
);
671 enum sas_linkrate
phy_get_max_linkrate_v3_hw(void)
673 return SAS_LINK_RATE_12_0_GBPS
;
676 static void phys_init_v3_hw(struct hisi_hba
*hisi_hba
)
678 start_phys_v3_hw(hisi_hba
);
681 static void sl_notify_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
685 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
686 sl_control
|= SL_CONTROL_NOTIFY_EN_MSK
;
687 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
689 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
690 sl_control
&= ~SL_CONTROL_NOTIFY_EN_MSK
;
691 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
694 static int get_wideport_bitmap_v3_hw(struct hisi_hba
*hisi_hba
, int port_id
)
697 u32 phy_port_num_ma
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
699 for (i
= 0; i
< hisi_hba
->n_phy
; i
++)
700 if (((phy_port_num_ma
>> (i
* 4)) & 0xf) == port_id
)
707 * The callpath to this function and upto writing the write
708 * queue pointer should be safe from interruption.
711 get_free_slot_v3_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_dq
*dq
)
713 struct device
*dev
= hisi_hba
->dev
;
718 r
= hisi_sas_read32_relaxed(hisi_hba
,
719 DLVRY_Q_0_RD_PTR
+ (queue
* 0x14));
720 if (r
== (w
+1) % HISI_SAS_QUEUE_SLOTS
) {
721 dev_warn(dev
, "full queue=%d r=%d w=%d\n\n",
729 static void start_delivery_v3_hw(struct hisi_sas_dq
*dq
)
731 struct hisi_hba
*hisi_hba
= dq
->hisi_hba
;
732 int dlvry_queue
= dq
->slot_prep
->dlvry_queue
;
733 int dlvry_queue_slot
= dq
->slot_prep
->dlvry_queue_slot
;
735 dq
->wr_point
= ++dlvry_queue_slot
% HISI_SAS_QUEUE_SLOTS
;
736 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_WR_PTR
+ (dlvry_queue
* 0x14),
740 static int prep_prd_sge_v3_hw(struct hisi_hba
*hisi_hba
,
741 struct hisi_sas_slot
*slot
,
742 struct hisi_sas_cmd_hdr
*hdr
,
743 struct scatterlist
*scatter
,
746 struct hisi_sas_sge_page
*sge_page
= hisi_sas_sge_addr_mem(slot
);
747 struct device
*dev
= hisi_hba
->dev
;
748 struct scatterlist
*sg
;
751 if (n_elem
> HISI_SAS_SGE_PAGE_CNT
) {
752 dev_err(dev
, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
757 for_each_sg(scatter
, sg
, n_elem
, i
) {
758 struct hisi_sas_sge
*entry
= &sge_page
->sge
[i
];
760 entry
->addr
= cpu_to_le64(sg_dma_address(sg
));
761 entry
->page_ctrl_0
= entry
->page_ctrl_1
= 0;
762 entry
->data_len
= cpu_to_le32(sg_dma_len(sg
));
766 hdr
->prd_table_addr
= cpu_to_le64(hisi_sas_sge_addr_dma(slot
));
768 hdr
->sg_len
= cpu_to_le32(n_elem
<< CMD_HDR_DATA_SGL_LEN_OFF
);
773 static int prep_ssp_v3_hw(struct hisi_hba
*hisi_hba
,
774 struct hisi_sas_slot
*slot
, int is_tmf
,
775 struct hisi_sas_tmf_task
*tmf
)
777 struct sas_task
*task
= slot
->task
;
778 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
779 struct domain_device
*device
= task
->dev
;
780 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
781 struct hisi_sas_port
*port
= slot
->port
;
782 struct sas_ssp_task
*ssp_task
= &task
->ssp_task
;
783 struct scsi_cmnd
*scsi_cmnd
= ssp_task
->cmd
;
784 int has_data
= 0, rc
, priority
= is_tmf
;
786 u32 dw1
= 0, dw2
= 0;
788 hdr
->dw0
= cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF
) |
789 (2 << CMD_HDR_TLR_CTRL_OFF
) |
790 (port
->id
<< CMD_HDR_PORT_OFF
) |
791 (priority
<< CMD_HDR_PRIORITY_OFF
) |
792 (1 << CMD_HDR_CMD_OFF
)); /* ssp */
794 dw1
= 1 << CMD_HDR_VDTL_OFF
;
796 dw1
|= 2 << CMD_HDR_FRAME_TYPE_OFF
;
797 dw1
|= DIR_NO_DATA
<< CMD_HDR_DIR_OFF
;
799 dw1
|= 1 << CMD_HDR_FRAME_TYPE_OFF
;
800 switch (scsi_cmnd
->sc_data_direction
) {
803 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
805 case DMA_FROM_DEVICE
:
807 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
810 dw1
&= ~CMD_HDR_DIR_MSK
;
815 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
816 hdr
->dw1
= cpu_to_le32(dw1
);
818 dw2
= (((sizeof(struct ssp_command_iu
) + sizeof(struct ssp_frame_hdr
)
819 + 3) / 4) << CMD_HDR_CFL_OFF
) |
820 ((HISI_SAS_MAX_SSP_RESP_SZ
/ 4) << CMD_HDR_MRFL_OFF
) |
821 (2 << CMD_HDR_SG_MOD_OFF
);
822 hdr
->dw2
= cpu_to_le32(dw2
);
823 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
826 rc
= prep_prd_sge_v3_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
832 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
833 hdr
->cmd_table_addr
= cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot
));
834 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
836 buf_cmd
= hisi_sas_cmd_hdr_addr_mem(slot
) +
837 sizeof(struct ssp_frame_hdr
);
839 memcpy(buf_cmd
, &task
->ssp_task
.LUN
, 8);
841 buf_cmd
[9] = ssp_task
->task_attr
| (ssp_task
->task_prio
<< 3);
842 memcpy(buf_cmd
+ 12, scsi_cmnd
->cmnd
, scsi_cmnd
->cmd_len
);
844 buf_cmd
[10] = tmf
->tmf
;
849 (tmf
->tag_of_task_to_be_managed
>> 8) & 0xff;
851 tmf
->tag_of_task_to_be_managed
& 0xff;
861 static int prep_smp_v3_hw(struct hisi_hba
*hisi_hba
,
862 struct hisi_sas_slot
*slot
)
864 struct sas_task
*task
= slot
->task
;
865 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
866 struct domain_device
*device
= task
->dev
;
867 struct device
*dev
= hisi_hba
->dev
;
868 struct hisi_sas_port
*port
= slot
->port
;
869 struct scatterlist
*sg_req
, *sg_resp
;
870 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
871 dma_addr_t req_dma_addr
;
872 unsigned int req_len
, resp_len
;
876 * DMA-map SMP request, response buffers
879 sg_req
= &task
->smp_task
.smp_req
;
880 elem
= dma_map_sg(dev
, sg_req
, 1, DMA_TO_DEVICE
);
883 req_len
= sg_dma_len(sg_req
);
884 req_dma_addr
= sg_dma_address(sg_req
);
887 sg_resp
= &task
->smp_task
.smp_resp
;
888 elem
= dma_map_sg(dev
, sg_resp
, 1, DMA_FROM_DEVICE
);
893 resp_len
= sg_dma_len(sg_resp
);
894 if ((req_len
& 0x3) || (resp_len
& 0x3)) {
901 hdr
->dw0
= cpu_to_le32((port
->id
<< CMD_HDR_PORT_OFF
) |
902 (1 << CMD_HDR_PRIORITY_OFF
) | /* high pri */
903 (2 << CMD_HDR_CMD_OFF
)); /* smp */
906 hdr
->dw1
= cpu_to_le32((sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
) |
907 (1 << CMD_HDR_FRAME_TYPE_OFF
) |
908 (DIR_NO_DATA
<< CMD_HDR_DIR_OFF
));
911 hdr
->dw2
= cpu_to_le32((((req_len
- 4) / 4) << CMD_HDR_CFL_OFF
) |
912 (HISI_SAS_MAX_SMP_RESP_SZ
/ 4 <<
915 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
<< CMD_HDR_IPTT_OFF
);
917 hdr
->cmd_table_addr
= cpu_to_le64(req_dma_addr
);
918 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
923 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_resp
, 1,
926 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_req
, 1,
931 static int get_ncq_tag_v3_hw(struct sas_task
*task
, u32
*tag
)
933 struct ata_queued_cmd
*qc
= task
->uldd_task
;
936 if (qc
->tf
.command
== ATA_CMD_FPDMA_WRITE
||
937 qc
->tf
.command
== ATA_CMD_FPDMA_READ
) {
945 static int prep_ata_v3_hw(struct hisi_hba
*hisi_hba
,
946 struct hisi_sas_slot
*slot
)
948 struct sas_task
*task
= slot
->task
;
949 struct domain_device
*device
= task
->dev
;
950 struct domain_device
*parent_dev
= device
->parent
;
951 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
952 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
953 struct asd_sas_port
*sas_port
= device
->port
;
954 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
956 int has_data
= 0, rc
= 0, hdr_tag
= 0;
957 u32 dw1
= 0, dw2
= 0;
959 hdr
->dw0
= cpu_to_le32(port
->id
<< CMD_HDR_PORT_OFF
);
960 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
961 hdr
->dw0
|= cpu_to_le32(3 << CMD_HDR_CMD_OFF
);
963 hdr
->dw0
|= cpu_to_le32(4 << CMD_HDR_CMD_OFF
);
965 switch (task
->data_dir
) {
968 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
970 case DMA_FROM_DEVICE
:
972 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
975 dw1
&= ~CMD_HDR_DIR_MSK
;
978 if ((task
->ata_task
.fis
.command
== ATA_CMD_DEV_RESET
) &&
979 (task
->ata_task
.fis
.control
& ATA_SRST
))
980 dw1
|= 1 << CMD_HDR_RESET_OFF
;
982 dw1
|= (hisi_sas_get_ata_protocol(
983 task
->ata_task
.fis
.command
, task
->data_dir
))
984 << CMD_HDR_FRAME_TYPE_OFF
;
985 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
987 if (CMD_IS_UNCONSTRAINT(task
->ata_task
.fis
.command
))
988 dw1
|= 1 << CMD_HDR_UNCON_CMD_OFF
;
990 hdr
->dw1
= cpu_to_le32(dw1
);
993 if (task
->ata_task
.use_ncq
&& get_ncq_tag_v3_hw(task
, &hdr_tag
)) {
994 task
->ata_task
.fis
.sector_count
|= (u8
) (hdr_tag
<< 3);
995 dw2
|= hdr_tag
<< CMD_HDR_NCQ_TAG_OFF
;
998 dw2
|= (HISI_SAS_MAX_STP_RESP_SZ
/ 4) << CMD_HDR_CFL_OFF
|
999 2 << CMD_HDR_SG_MOD_OFF
;
1000 hdr
->dw2
= cpu_to_le32(dw2
);
1003 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
1006 rc
= prep_prd_sge_v3_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
1012 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
1013 hdr
->cmd_table_addr
= cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot
));
1014 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
1016 buf_cmd
= hisi_sas_cmd_hdr_addr_mem(slot
);
1018 if (likely(!task
->ata_task
.device_control_reg_update
))
1019 task
->ata_task
.fis
.flags
|= 0x80; /* C=1: update ATA cmd reg */
1020 /* fill in command FIS */
1021 memcpy(buf_cmd
, &task
->ata_task
.fis
, sizeof(struct host_to_dev_fis
));
1026 static int prep_abort_v3_hw(struct hisi_hba
*hisi_hba
,
1027 struct hisi_sas_slot
*slot
,
1028 int device_id
, int abort_flag
, int tag_to_abort
)
1030 struct sas_task
*task
= slot
->task
;
1031 struct domain_device
*dev
= task
->dev
;
1032 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1033 struct hisi_sas_port
*port
= slot
->port
;
1036 hdr
->dw0
= cpu_to_le32((5 << CMD_HDR_CMD_OFF
) | /*abort*/
1037 (port
->id
<< CMD_HDR_PORT_OFF
) |
1038 ((dev_is_sata(dev
) ? 1:0)
1039 << CMD_HDR_ABORT_DEVICE_TYPE_OFF
) |
1041 << CMD_HDR_ABORT_FLAG_OFF
));
1044 hdr
->dw1
= cpu_to_le32(device_id
1045 << CMD_HDR_DEV_ID_OFF
);
1048 hdr
->dw7
= cpu_to_le32(tag_to_abort
<< CMD_HDR_ABORT_IPTT_OFF
);
1049 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
1054 static int phy_up_v3_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
1057 u32 context
, port_id
, link_rate
, hard_phy_linkrate
;
1058 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1059 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1060 struct device
*dev
= hisi_hba
->dev
;
1062 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 1);
1064 port_id
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
1065 port_id
= (port_id
>> (4 * phy_no
)) & 0xf;
1066 link_rate
= hisi_sas_read32(hisi_hba
, PHY_CONN_RATE
);
1067 link_rate
= (link_rate
>> (phy_no
* 4)) & 0xf;
1069 if (port_id
== 0xf) {
1070 dev_err(dev
, "phyup: phy%d invalid portid\n", phy_no
);
1074 sas_phy
->linkrate
= link_rate
;
1075 hard_phy_linkrate
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1077 phy
->maximum_linkrate
= hard_phy_linkrate
& 0xf;
1078 phy
->minimum_linkrate
= (hard_phy_linkrate
>> 4) & 0xf;
1079 phy
->phy_type
&= ~(PORT_TYPE_SAS
| PORT_TYPE_SATA
);
1081 /* Check for SATA dev */
1082 context
= hisi_sas_read32(hisi_hba
, PHY_CONTEXT
);
1083 if (context
& (1 << phy_no
)) {
1084 struct hisi_sas_initial_fis
*initial_fis
;
1085 struct dev_to_host_fis
*fis
;
1086 u8 attached_sas_addr
[SAS_ADDR_SIZE
] = {0};
1088 dev_info(dev
, "phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
1089 initial_fis
= &hisi_hba
->initial_fis
[phy_no
];
1090 fis
= &initial_fis
->fis
;
1091 sas_phy
->oob_mode
= SATA_OOB_MODE
;
1092 attached_sas_addr
[0] = 0x50;
1093 attached_sas_addr
[7] = phy_no
;
1094 memcpy(sas_phy
->attached_sas_addr
,
1097 memcpy(sas_phy
->frame_rcvd
, fis
,
1098 sizeof(struct dev_to_host_fis
));
1099 phy
->phy_type
|= PORT_TYPE_SATA
;
1100 phy
->identify
.device_type
= SAS_SATA_DEV
;
1101 phy
->frame_rcvd_size
= sizeof(struct dev_to_host_fis
);
1102 phy
->identify
.target_port_protocols
= SAS_PROTOCOL_SATA
;
1104 u32
*frame_rcvd
= (u32
*)sas_phy
->frame_rcvd
;
1105 struct sas_identify_frame
*id
=
1106 (struct sas_identify_frame
*)frame_rcvd
;
1108 dev_info(dev
, "phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
1109 for (i
= 0; i
< 6; i
++) {
1110 u32 idaf
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1111 RX_IDAF_DWORD0
+ (i
* 4));
1112 frame_rcvd
[i
] = __swab32(idaf
);
1114 sas_phy
->oob_mode
= SAS_OOB_MODE
;
1115 memcpy(sas_phy
->attached_sas_addr
,
1118 phy
->phy_type
|= PORT_TYPE_SAS
;
1119 phy
->identify
.device_type
= id
->dev_type
;
1120 phy
->frame_rcvd_size
= sizeof(struct sas_identify_frame
);
1121 if (phy
->identify
.device_type
== SAS_END_DEVICE
)
1122 phy
->identify
.target_port_protocols
=
1124 else if (phy
->identify
.device_type
!= SAS_PHY_UNUSED
)
1125 phy
->identify
.target_port_protocols
=
1129 phy
->port_id
= port_id
;
1130 phy
->phy_attached
= 1;
1131 queue_work(hisi_hba
->wq
, &phy
->phyup_ws
);
1134 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
1135 CHL_INT0_SL_PHY_ENABLE_MSK
);
1136 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 0);
1141 static int phy_down_v3_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
1144 u32 phy_state
, sl_ctrl
, txid_auto
;
1145 struct device
*dev
= hisi_hba
->dev
;
1147 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 1);
1149 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1150 dev_info(dev
, "phydown: phy%d phy_state=0x%x\n", phy_no
, phy_state
);
1151 hisi_sas_phy_down(hisi_hba
, phy_no
, (phy_state
& 1 << phy_no
) ? 1 : 0);
1153 sl_ctrl
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
1154 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
,
1155 sl_ctrl
&(~SL_CTA_MSK
));
1157 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
1158 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
1159 txid_auto
| CT3_MSK
);
1161 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
, CHL_INT0_NOT_RDY_MSK
);
1162 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 0);
1167 static void phy_bcast_v3_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
1169 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1170 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1171 struct sas_ha_struct
*sas_ha
= &hisi_hba
->sha
;
1173 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 1);
1174 sas_ha
->notify_port_event(sas_phy
, PORTE_BROADCAST_RCVD
);
1175 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
1176 CHL_INT0_SL_RX_BCST_ACK_MSK
);
1177 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 0);
1180 static irqreturn_t
int_phy_up_down_bcast_v3_hw(int irq_no
, void *p
)
1182 struct hisi_hba
*hisi_hba
= p
;
1185 irqreturn_t res
= IRQ_NONE
;
1187 irq_msk
= hisi_sas_read32(hisi_hba
, CHNL_INT_STATUS
)
1191 u32 irq_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1193 u32 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1194 int rdy
= phy_state
& (1 << phy_no
);
1197 if (irq_value
& CHL_INT0_SL_PHY_ENABLE_MSK
)
1199 if (phy_up_v3_hw(phy_no
, hisi_hba
)
1202 if (irq_value
& CHL_INT0_SL_RX_BCST_ACK_MSK
)
1204 phy_bcast_v3_hw(phy_no
, hisi_hba
);
1206 if (irq_value
& CHL_INT0_NOT_RDY_MSK
)
1208 if (phy_down_v3_hw(phy_no
, hisi_hba
)
1220 static irqreturn_t
int_chnl_int_v3_hw(int irq_no
, void *p
)
1222 struct hisi_hba
*hisi_hba
= p
;
1223 struct device
*dev
= hisi_hba
->dev
;
1224 u32 ent_msk
, ent_tmp
, irq_msk
;
1227 ent_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
1229 ent_msk
|= ENT_INT_SRC_MSK3_ENT95_MSK_MSK
;
1230 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_msk
);
1232 irq_msk
= hisi_sas_read32(hisi_hba
, CHNL_INT_STATUS
)
1236 u32 irq_value0
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1238 u32 irq_value1
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1240 u32 irq_value2
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1243 if ((irq_msk
& (4 << (phy_no
* 4))) &&
1245 if (irq_value1
& (CHL_INT1_DMAC_RX_ECC_ERR_MSK
|
1246 CHL_INT1_DMAC_TX_ECC_ERR_MSK
))
1247 panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
1248 dev_name(dev
), irq_value1
);
1250 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1251 CHL_INT1
, irq_value1
);
1254 if (irq_msk
& (8 << (phy_no
* 4)) && irq_value2
)
1255 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1256 CHL_INT2
, irq_value2
);
1259 if (irq_msk
& (2 << (phy_no
* 4)) && irq_value0
) {
1260 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1261 CHL_INT0
, irq_value0
1262 & (~CHL_INT0_HOTPLUG_TOUT_MSK
)
1263 & (~CHL_INT0_SL_PHY_ENABLE_MSK
)
1264 & (~CHL_INT0_NOT_RDY_MSK
));
1266 irq_msk
&= ~(0xe << (phy_no
* 4));
1270 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_tmp
);
1276 slot_err_v3_hw(struct hisi_hba
*hisi_hba
, struct sas_task
*task
,
1277 struct hisi_sas_slot
*slot
)
1279 struct task_status_struct
*ts
= &task
->task_status
;
1280 struct hisi_sas_complete_v3_hdr
*complete_queue
=
1281 hisi_hba
->complete_hdr
[slot
->cmplt_queue
];
1282 struct hisi_sas_complete_v3_hdr
*complete_hdr
=
1283 &complete_queue
[slot
->cmplt_queue_slot
];
1284 struct hisi_sas_err_record_v3
*record
=
1285 hisi_sas_status_buf_addr_mem(slot
);
1286 u32 dma_rx_err_type
= record
->dma_rx_err_type
;
1287 u32 trans_tx_fail_type
= record
->trans_tx_fail_type
;
1289 switch (task
->task_proto
) {
1290 case SAS_PROTOCOL_SSP
:
1291 if (dma_rx_err_type
& RX_DATA_LEN_UNDERFLOW_MSK
) {
1292 ts
->residual
= trans_tx_fail_type
;
1293 ts
->stat
= SAS_DATA_UNDERRUN
;
1294 } else if (complete_hdr
->dw3
& CMPLT_HDR_IO_IN_TARGET_MSK
) {
1295 ts
->stat
= SAS_QUEUE_FULL
;
1298 ts
->stat
= SAS_OPEN_REJECT
;
1299 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
1302 case SAS_PROTOCOL_SATA
:
1303 case SAS_PROTOCOL_STP
:
1304 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
1305 if (dma_rx_err_type
& RX_DATA_LEN_UNDERFLOW_MSK
) {
1306 ts
->residual
= trans_tx_fail_type
;
1307 ts
->stat
= SAS_DATA_UNDERRUN
;
1308 } else if (complete_hdr
->dw3
& CMPLT_HDR_IO_IN_TARGET_MSK
) {
1309 ts
->stat
= SAS_PHY_DOWN
;
1312 ts
->stat
= SAS_OPEN_REJECT
;
1313 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
1315 hisi_sas_sata_done(task
, slot
);
1317 case SAS_PROTOCOL_SMP
:
1318 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
1326 slot_complete_v3_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_slot
*slot
)
1328 struct sas_task
*task
= slot
->task
;
1329 struct hisi_sas_device
*sas_dev
;
1330 struct device
*dev
= hisi_hba
->dev
;
1331 struct task_status_struct
*ts
;
1332 struct domain_device
*device
;
1333 enum exec_status sts
;
1334 struct hisi_sas_complete_v3_hdr
*complete_queue
=
1335 hisi_hba
->complete_hdr
[slot
->cmplt_queue
];
1336 struct hisi_sas_complete_v3_hdr
*complete_hdr
=
1337 &complete_queue
[slot
->cmplt_queue_slot
];
1339 unsigned long flags
;
1341 if (unlikely(!task
|| !task
->lldd_task
|| !task
->dev
))
1344 ts
= &task
->task_status
;
1346 sas_dev
= device
->lldd_dev
;
1348 spin_lock_irqsave(&task
->task_state_lock
, flags
);
1349 aborted
= task
->task_state_flags
& SAS_TASK_STATE_ABORTED
;
1350 task
->task_state_flags
&=
1351 ~(SAS_TASK_STATE_PENDING
| SAS_TASK_AT_INITIATOR
);
1352 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
1354 memset(ts
, 0, sizeof(*ts
));
1355 ts
->resp
= SAS_TASK_COMPLETE
;
1356 if (unlikely(aborted
)) {
1357 ts
->stat
= SAS_ABORTED_TASK
;
1358 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
1362 if (unlikely(!sas_dev
)) {
1363 dev_dbg(dev
, "slot complete: port has not device\n");
1364 ts
->stat
= SAS_PHY_DOWN
;
1369 * Use SAS+TMF status codes
1371 switch ((complete_hdr
->dw0
& CMPLT_HDR_ABORT_STAT_MSK
)
1372 >> CMPLT_HDR_ABORT_STAT_OFF
) {
1373 case STAT_IO_ABORTED
:
1374 /* this IO has been aborted by abort command */
1375 ts
->stat
= SAS_ABORTED_TASK
;
1377 case STAT_IO_COMPLETE
:
1378 /* internal abort command complete */
1379 ts
->stat
= TMF_RESP_FUNC_SUCC
;
1381 case STAT_IO_NO_DEVICE
:
1382 ts
->stat
= TMF_RESP_FUNC_COMPLETE
;
1384 case STAT_IO_NOT_VALID
:
1386 * abort single IO, the controller can't find the IO
1388 ts
->stat
= TMF_RESP_FUNC_FAILED
;
1394 /* check for erroneous completion */
1395 if ((complete_hdr
->dw0
& CMPLT_HDR_CMPLT_MSK
) == 0x3) {
1396 slot_err_v3_hw(hisi_hba
, task
, slot
);
1397 if (unlikely(slot
->abort
))
1402 switch (task
->task_proto
) {
1403 case SAS_PROTOCOL_SSP
: {
1404 struct ssp_response_iu
*iu
=
1405 hisi_sas_status_buf_addr_mem(slot
) +
1406 sizeof(struct hisi_sas_err_record
);
1408 sas_ssp_task_response(dev
, task
, iu
);
1411 case SAS_PROTOCOL_SMP
: {
1412 struct scatterlist
*sg_resp
= &task
->smp_task
.smp_resp
;
1415 ts
->stat
= SAM_STAT_GOOD
;
1416 to
= kmap_atomic(sg_page(sg_resp
));
1418 dma_unmap_sg(dev
, &task
->smp_task
.smp_resp
, 1,
1420 dma_unmap_sg(dev
, &task
->smp_task
.smp_req
, 1,
1422 memcpy(to
+ sg_resp
->offset
,
1423 hisi_sas_status_buf_addr_mem(slot
) +
1424 sizeof(struct hisi_sas_err_record
),
1425 sg_dma_len(sg_resp
));
1429 case SAS_PROTOCOL_SATA
:
1430 case SAS_PROTOCOL_STP
:
1431 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
1432 ts
->stat
= SAM_STAT_GOOD
;
1433 hisi_sas_sata_done(task
, slot
);
1436 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
1440 if (!slot
->port
->port_attached
) {
1441 dev_err(dev
, "slot complete: port %d has removed\n",
1442 slot
->port
->sas_port
.id
);
1443 ts
->stat
= SAS_PHY_DOWN
;
1447 spin_lock_irqsave(&task
->task_state_lock
, flags
);
1448 task
->task_state_flags
|= SAS_TASK_STATE_DONE
;
1449 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
1450 spin_lock_irqsave(&hisi_hba
->lock
, flags
);
1451 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
1452 spin_unlock_irqrestore(&hisi_hba
->lock
, flags
);
1455 if (task
->task_done
)
1456 task
->task_done(task
);
1461 static void cq_tasklet_v3_hw(unsigned long val
)
1463 struct hisi_sas_cq
*cq
= (struct hisi_sas_cq
*)val
;
1464 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
1465 struct hisi_sas_slot
*slot
;
1466 struct hisi_sas_itct
*itct
;
1467 struct hisi_sas_complete_v3_hdr
*complete_queue
;
1468 u32 rd_point
= cq
->rd_point
, wr_point
, dev_id
;
1470 struct hisi_sas_dq
*dq
= &hisi_hba
->dq
[queue
];
1472 complete_queue
= hisi_hba
->complete_hdr
[queue
];
1474 spin_lock(&dq
->lock
);
1475 wr_point
= hisi_sas_read32(hisi_hba
, COMPL_Q_0_WR_PTR
+
1478 while (rd_point
!= wr_point
) {
1479 struct hisi_sas_complete_v3_hdr
*complete_hdr
;
1482 complete_hdr
= &complete_queue
[rd_point
];
1484 /* Check for NCQ completion */
1485 if (complete_hdr
->act
) {
1486 u32 act_tmp
= complete_hdr
->act
;
1487 int ncq_tag_count
= ffs(act_tmp
);
1489 dev_id
= (complete_hdr
->dw1
& CMPLT_HDR_DEV_ID_MSK
) >>
1490 CMPLT_HDR_DEV_ID_OFF
;
1491 itct
= &hisi_hba
->itct
[dev_id
];
1493 /* The NCQ tags are held in the itct header */
1494 while (ncq_tag_count
) {
1495 __le64
*ncq_tag
= &itct
->qw4_15
[0];
1498 iptt
= (ncq_tag
[ncq_tag_count
/ 5]
1499 >> (ncq_tag_count
% 5) * 12) & 0xfff;
1501 slot
= &hisi_hba
->slot_info
[iptt
];
1502 slot
->cmplt_queue_slot
= rd_point
;
1503 slot
->cmplt_queue
= queue
;
1504 slot_complete_v3_hw(hisi_hba
, slot
);
1506 act_tmp
&= ~(1 << ncq_tag_count
);
1507 ncq_tag_count
= ffs(act_tmp
);
1510 iptt
= (complete_hdr
->dw1
) & CMPLT_HDR_IPTT_MSK
;
1511 slot
= &hisi_hba
->slot_info
[iptt
];
1512 slot
->cmplt_queue_slot
= rd_point
;
1513 slot
->cmplt_queue
= queue
;
1514 slot_complete_v3_hw(hisi_hba
, slot
);
1517 if (++rd_point
>= HISI_SAS_QUEUE_SLOTS
)
1521 /* update rd_point */
1522 cq
->rd_point
= rd_point
;
1523 hisi_sas_write32(hisi_hba
, COMPL_Q_0_RD_PTR
+ (0x14 * queue
), rd_point
);
1524 spin_unlock(&dq
->lock
);
1527 static irqreturn_t
cq_interrupt_v3_hw(int irq_no
, void *p
)
1529 struct hisi_sas_cq
*cq
= p
;
1530 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
1533 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 1 << queue
);
1535 tasklet_schedule(&cq
->tasklet
);
1540 static int interrupt_init_v3_hw(struct hisi_hba
*hisi_hba
)
1542 struct device
*dev
= hisi_hba
->dev
;
1543 struct pci_dev
*pdev
= hisi_hba
->pci_dev
;
1546 int max_msi
= HISI_SAS_MSI_COUNT_V3_HW
;
1548 vectors
= pci_alloc_irq_vectors(hisi_hba
->pci_dev
, 1,
1549 max_msi
, PCI_IRQ_MSI
);
1550 if (vectors
< max_msi
) {
1551 dev_err(dev
, "could not allocate all msi (%d)\n", vectors
);
1555 rc
= devm_request_irq(dev
, pci_irq_vector(pdev
, 1),
1556 int_phy_up_down_bcast_v3_hw
, 0,
1557 DRV_NAME
" phy", hisi_hba
);
1559 dev_err(dev
, "could not request phy interrupt, rc=%d\n", rc
);
1561 goto free_irq_vectors
;
1564 rc
= devm_request_irq(dev
, pci_irq_vector(pdev
, 2),
1565 int_chnl_int_v3_hw
, 0,
1566 DRV_NAME
" channel", hisi_hba
);
1568 dev_err(dev
, "could not request chnl interrupt, rc=%d\n", rc
);
1573 /* Init tasklets for cq only */
1574 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
1575 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[i
];
1576 struct tasklet_struct
*t
= &cq
->tasklet
;
1578 rc
= devm_request_irq(dev
, pci_irq_vector(pdev
, i
+16),
1579 cq_interrupt_v3_hw
, 0,
1580 DRV_NAME
" cq", cq
);
1583 "could not request cq%d interrupt, rc=%d\n",
1589 tasklet_init(t
, cq_tasklet_v3_hw
, (unsigned long)cq
);
1595 for (k
= 0; k
< i
; k
++) {
1596 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[k
];
1598 free_irq(pci_irq_vector(pdev
, k
+16), cq
);
1600 free_irq(pci_irq_vector(pdev
, 2), hisi_hba
);
1602 free_irq(pci_irq_vector(pdev
, 1), hisi_hba
);
1604 pci_free_irq_vectors(pdev
);
1608 static int hisi_sas_v3_init(struct hisi_hba
*hisi_hba
)
1612 rc
= hw_init_v3_hw(hisi_hba
);
1616 rc
= interrupt_init_v3_hw(hisi_hba
);
1623 static const struct hisi_sas_hw hisi_sas_v3_hw
= {
1624 .hw_init
= hisi_sas_v3_init
,
1625 .setup_itct
= setup_itct_v3_hw
,
1626 .max_command_entries
= HISI_SAS_COMMAND_ENTRIES_V3_HW
,
1627 .get_wideport_bitmap
= get_wideport_bitmap_v3_hw
,
1628 .complete_hdr_size
= sizeof(struct hisi_sas_complete_v3_hdr
),
1629 .free_device
= free_device_v3_hw
,
1630 .sl_notify
= sl_notify_v3_hw
,
1631 .prep_ssp
= prep_ssp_v3_hw
,
1632 .prep_smp
= prep_smp_v3_hw
,
1633 .prep_stp
= prep_ata_v3_hw
,
1634 .prep_abort
= prep_abort_v3_hw
,
1635 .get_free_slot
= get_free_slot_v3_hw
,
1636 .start_delivery
= start_delivery_v3_hw
,
1637 .slot_complete
= slot_complete_v3_hw
,
1638 .phys_init
= phys_init_v3_hw
,
1639 .phy_enable
= enable_phy_v3_hw
,
1640 .phy_disable
= disable_phy_v3_hw
,
1641 .phy_hard_reset
= phy_hard_reset_v3_hw
,
1642 .phy_get_max_linkrate
= phy_get_max_linkrate_v3_hw
,
1643 .dereg_device
= dereg_device_v3_hw
,
1646 static struct Scsi_Host
*
1647 hisi_sas_shost_alloc_pci(struct pci_dev
*pdev
)
1649 struct Scsi_Host
*shost
;
1650 struct hisi_hba
*hisi_hba
;
1651 struct device
*dev
= &pdev
->dev
;
1653 shost
= scsi_host_alloc(hisi_sas_sht
, sizeof(*hisi_hba
));
1656 hisi_hba
= shost_priv(shost
);
1658 hisi_hba
->hw
= &hisi_sas_v3_hw
;
1659 hisi_hba
->pci_dev
= pdev
;
1660 hisi_hba
->dev
= dev
;
1661 hisi_hba
->shost
= shost
;
1662 SHOST_TO_SAS_HA(shost
) = &hisi_hba
->sha
;
1664 init_timer(&hisi_hba
->timer
);
1666 if (hisi_sas_get_fw_info(hisi_hba
) < 0)
1669 if (hisi_sas_alloc(hisi_hba
, shost
)) {
1670 hisi_sas_free(hisi_hba
);
1676 dev_err(dev
, "shost alloc failed\n");
1681 hisi_sas_v3_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1683 struct Scsi_Host
*shost
;
1684 struct hisi_hba
*hisi_hba
;
1685 struct device
*dev
= &pdev
->dev
;
1686 struct asd_sas_phy
**arr_phy
;
1687 struct asd_sas_port
**arr_port
;
1688 struct sas_ha_struct
*sha
;
1689 int rc
, phy_nr
, port_nr
, i
;
1691 rc
= pci_enable_device(pdev
);
1695 pci_set_master(pdev
);
1697 rc
= pci_request_regions(pdev
, DRV_NAME
);
1699 goto err_out_disable_device
;
1701 if ((pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) != 0) ||
1702 (pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64)) != 0)) {
1703 if ((pci_set_dma_mask(pdev
, DMA_BIT_MASK(32)) != 0) ||
1704 (pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)) != 0)) {
1705 dev_err(dev
, "No usable DMA addressing method\n");
1707 goto err_out_regions
;
1711 shost
= hisi_sas_shost_alloc_pci(pdev
);
1714 goto err_out_regions
;
1717 sha
= SHOST_TO_SAS_HA(shost
);
1718 hisi_hba
= shost_priv(shost
);
1719 dev_set_drvdata(dev
, sha
);
1721 hisi_hba
->regs
= pcim_iomap(pdev
, 5, 0);
1722 if (!hisi_hba
->regs
) {
1723 dev_err(dev
, "cannot map register.\n");
1728 phy_nr
= port_nr
= hisi_hba
->n_phy
;
1730 arr_phy
= devm_kcalloc(dev
, phy_nr
, sizeof(void *), GFP_KERNEL
);
1731 arr_port
= devm_kcalloc(dev
, port_nr
, sizeof(void *), GFP_KERNEL
);
1732 if (!arr_phy
|| !arr_port
) {
1737 sha
->sas_phy
= arr_phy
;
1738 sha
->sas_port
= arr_port
;
1739 sha
->core
.shost
= shost
;
1740 sha
->lldd_ha
= hisi_hba
;
1742 shost
->transportt
= hisi_sas_stt
;
1743 shost
->max_id
= HISI_SAS_MAX_DEVICES
;
1744 shost
->max_lun
= ~0;
1745 shost
->max_channel
= 1;
1746 shost
->max_cmd_len
= 16;
1747 shost
->sg_tablesize
= min_t(u16
, SG_ALL
, HISI_SAS_SGE_PAGE_CNT
);
1748 shost
->can_queue
= hisi_hba
->hw
->max_command_entries
;
1749 shost
->cmd_per_lun
= hisi_hba
->hw
->max_command_entries
;
1751 sha
->sas_ha_name
= DRV_NAME
;
1753 sha
->lldd_module
= THIS_MODULE
;
1754 sha
->sas_addr
= &hisi_hba
->sas_addr
[0];
1755 sha
->num_phys
= hisi_hba
->n_phy
;
1756 sha
->core
.shost
= hisi_hba
->shost
;
1758 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1759 sha
->sas_phy
[i
] = &hisi_hba
->phy
[i
].sas_phy
;
1760 sha
->sas_port
[i
] = &hisi_hba
->port
[i
].sas_port
;
1763 hisi_sas_init_add(hisi_hba
);
1765 rc
= scsi_add_host(shost
, dev
);
1769 rc
= sas_register_ha(sha
);
1771 goto err_out_register_ha
;
1773 rc
= hisi_hba
->hw
->hw_init(hisi_hba
);
1775 goto err_out_register_ha
;
1777 scsi_scan_host(shost
);
1781 err_out_register_ha
:
1782 scsi_remove_host(shost
);
1786 pci_release_regions(pdev
);
1787 err_out_disable_device
:
1788 pci_disable_device(pdev
);
1794 hisi_sas_v3_destroy_irqs(struct pci_dev
*pdev
, struct hisi_hba
*hisi_hba
)
1798 free_irq(pci_irq_vector(pdev
, 1), hisi_hba
);
1799 free_irq(pci_irq_vector(pdev
, 2), hisi_hba
);
1800 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
1801 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[i
];
1803 free_irq(pci_irq_vector(pdev
, i
+16), cq
);
1805 pci_free_irq_vectors(pdev
);
1808 static void hisi_sas_v3_remove(struct pci_dev
*pdev
)
1810 struct device
*dev
= &pdev
->dev
;
1811 struct sas_ha_struct
*sha
= dev_get_drvdata(dev
);
1812 struct hisi_hba
*hisi_hba
= sha
->lldd_ha
;
1814 sas_unregister_ha(sha
);
1815 sas_remove_host(sha
->core
.shost
);
1817 hisi_sas_free(hisi_hba
);
1818 hisi_sas_v3_destroy_irqs(pdev
, hisi_hba
);
1819 pci_release_regions(pdev
);
1820 pci_disable_device(pdev
);
1824 /* instances of the controller */
1828 static const struct pci_device_id sas_v3_pci_table
[] = {
1829 { PCI_VDEVICE(HUAWEI
, 0xa230), hip08
},
1833 static struct pci_driver sas_v3_pci_driver
= {
1835 .id_table
= sas_v3_pci_table
,
1836 .probe
= hisi_sas_v3_probe
,
1837 .remove
= hisi_sas_v3_remove
,
1840 module_pci_driver(sas_v3_pci_driver
);
1842 MODULE_VERSION(DRV_VERSION
);
1843 MODULE_LICENSE("GPL");
1844 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
1845 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
1846 MODULE_ALIAS("platform:" DRV_NAME
);