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scsi: hisi_sas: remove phy_down_v3_hw() res variable
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v3_hw.c
1 /*
2 * Copyright (c) 2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 #include "hisi_sas.h"
12 #define DRV_NAME "hisi_sas_v3_hw"
13
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
26 #define ITCT_CLR 0x44
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CFG_1US_TIMER_TRSH 0xcc
55 #define CHNL_INT_STATUS 0x148
56 #define INT_COAL_EN 0x19c
57 #define OQ_INT_COAL_TIME 0x1a0
58 #define OQ_INT_COAL_CNT 0x1a4
59 #define ENT_INT_COAL_TIME 0x1a8
60 #define ENT_INT_COAL_CNT 0x1ac
61 #define OQ_INT_SRC 0x1b0
62 #define OQ_INT_SRC_MSK 0x1b4
63 #define ENT_INT_SRC1 0x1b8
64 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
65 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
66 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
67 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
68 #define ENT_INT_SRC2 0x1bc
69 #define ENT_INT_SRC3 0x1c0
70 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
71 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
72 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
73 #define ENT_INT_SRC3_AXI_OFF 11
74 #define ENT_INT_SRC3_FIFO_OFF 12
75 #define ENT_INT_SRC3_LM_OFF 14
76 #define ENT_INT_SRC3_ITC_INT_OFF 15
77 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
78 #define ENT_INT_SRC3_ABT_OFF 16
79 #define ENT_INT_SRC_MSK1 0x1c4
80 #define ENT_INT_SRC_MSK2 0x1c8
81 #define ENT_INT_SRC_MSK3 0x1cc
82 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
83 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
84 #define CHNL_ENT_INT_MSK 0x1d4
85 #define HGC_COM_INT_MSK 0x1d8
86 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
87 #define SAS_ECC_INTR 0x1e8
88 #define SAS_ECC_INTR_MSK 0x1ec
89 #define HGC_ERR_STAT_EN 0x238
90 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
91 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
92 #define DLVRY_Q_0_DEPTH 0x268
93 #define DLVRY_Q_0_WR_PTR 0x26c
94 #define DLVRY_Q_0_RD_PTR 0x270
95 #define HYPER_STREAM_ID_EN_CFG 0xc80
96 #define OQ0_INT_SRC_MSK 0xc90
97 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
98 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
99 #define COMPL_Q_0_DEPTH 0x4e8
100 #define COMPL_Q_0_WR_PTR 0x4ec
101 #define COMPL_Q_0_RD_PTR 0x4f0
102 #define AWQOS_AWCACHE_CFG 0xc84
103 #define ARQOS_ARCACHE_CFG 0xc88
104
105 /* phy registers requiring init */
106 #define PORT_BASE (0x2000)
107 #define PHY_CFG (PORT_BASE + 0x0)
108 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
109 #define PHY_CFG_ENA_OFF 0
110 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
111 #define PHY_CFG_DC_OPT_OFF 2
112 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
113 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
114 #define PHY_CTRL (PORT_BASE + 0x14)
115 #define PHY_CTRL_RESET_OFF 0
116 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
117 #define SL_CFG (PORT_BASE + 0x84)
118 #define SL_CONTROL (PORT_BASE + 0x94)
119 #define SL_CONTROL_NOTIFY_EN_OFF 0
120 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
121 #define SL_CTA_OFF 17
122 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
123 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
124 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
125 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
126 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
127 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
128 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
129 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
130 #define TXID_AUTO (PORT_BASE + 0xb8)
131 #define CT3_OFF 1
132 #define CT3_MSK (0x1 << CT3_OFF)
133 #define TX_HARDRST_OFF 2
134 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
135 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
136 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
137 #define STP_LINK_TIMER (PORT_BASE + 0x120)
138 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
139 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
140 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
141 #define CHL_INT0 (PORT_BASE + 0x1b4)
142 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
143 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
144 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
145 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
146 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
147 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
148 #define CHL_INT0_NOT_RDY_OFF 4
149 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
150 #define CHL_INT0_PHY_RDY_OFF 5
151 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
152 #define CHL_INT1 (PORT_BASE + 0x1b8)
153 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
154 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
155 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
156 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
157 #define CHL_INT2 (PORT_BASE + 0x1bc)
158 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
159 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
160 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
161 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
162 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
163 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
164 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
165 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
166 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
167 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
168 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
169 #define DMA_TX_STATUS_BUSY_OFF 0
170 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
171 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
172 #define DMA_RX_STATUS_BUSY_OFF 0
173 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
174
175 #define MAX_ITCT_HW 4096 /* max the hw can support */
176 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
177 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
178 #error Max ITCT exceeded
179 #endif
180
181 #define AXI_MASTER_CFG_BASE (0x5000)
182 #define AM_CTRL_GLOBAL (0x0)
183 #define AM_CURR_TRANS_RETURN (0x150)
184
185 #define AM_CFG_MAX_TRANS (0x5010)
186 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
187 #define AXI_CFG (0x5100)
188 #define AM_ROB_ECC_ERR_ADDR (0x510c)
189 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
190 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
191 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
192 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
193
194 /* HW dma structures */
195 /* Delivery queue header */
196 /* dw0 */
197 #define CMD_HDR_ABORT_FLAG_OFF 0
198 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
199 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
200 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
201 #define CMD_HDR_RESP_REPORT_OFF 5
202 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
203 #define CMD_HDR_TLR_CTRL_OFF 6
204 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
205 #define CMD_HDR_PORT_OFF 18
206 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
207 #define CMD_HDR_PRIORITY_OFF 27
208 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
209 #define CMD_HDR_CMD_OFF 29
210 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
211 /* dw1 */
212 #define CMD_HDR_UNCON_CMD_OFF 3
213 #define CMD_HDR_DIR_OFF 5
214 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
215 #define CMD_HDR_RESET_OFF 7
216 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
217 #define CMD_HDR_VDTL_OFF 10
218 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
219 #define CMD_HDR_FRAME_TYPE_OFF 11
220 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
221 #define CMD_HDR_DEV_ID_OFF 16
222 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
223 /* dw2 */
224 #define CMD_HDR_CFL_OFF 0
225 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
226 #define CMD_HDR_NCQ_TAG_OFF 10
227 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
228 #define CMD_HDR_MRFL_OFF 15
229 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
230 #define CMD_HDR_SG_MOD_OFF 24
231 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
232 /* dw3 */
233 #define CMD_HDR_IPTT_OFF 0
234 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
235 /* dw6 */
236 #define CMD_HDR_DIF_SGL_LEN_OFF 0
237 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
238 #define CMD_HDR_DATA_SGL_LEN_OFF 16
239 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
240 /* dw7 */
241 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
242 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
243 #define CMD_HDR_ABORT_IPTT_OFF 16
244 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
245
246 /* Completion header */
247 /* dw0 */
248 #define CMPLT_HDR_CMPLT_OFF 0
249 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
250 #define CMPLT_HDR_ERROR_PHASE_OFF 2
251 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
252 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
253 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
254 #define CMPLT_HDR_ERX_OFF 12
255 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
256 #define CMPLT_HDR_ABORT_STAT_OFF 13
257 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
258 /* abort_stat */
259 #define STAT_IO_NOT_VALID 0x1
260 #define STAT_IO_NO_DEVICE 0x2
261 #define STAT_IO_COMPLETE 0x3
262 #define STAT_IO_ABORTED 0x4
263 /* dw1 */
264 #define CMPLT_HDR_IPTT_OFF 0
265 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
266 #define CMPLT_HDR_DEV_ID_OFF 16
267 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
268 /* dw3 */
269 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
270 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
271
272 /* ITCT header */
273 /* qw0 */
274 #define ITCT_HDR_DEV_TYPE_OFF 0
275 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
276 #define ITCT_HDR_VALID_OFF 2
277 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
278 #define ITCT_HDR_MCR_OFF 5
279 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
280 #define ITCT_HDR_VLN_OFF 9
281 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
282 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
283 #define ITCT_HDR_AWT_CONTINUE_OFF 25
284 #define ITCT_HDR_PORT_ID_OFF 28
285 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
286 /* qw2 */
287 #define ITCT_HDR_INLT_OFF 0
288 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
289 #define ITCT_HDR_RTOLT_OFF 48
290 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
291
292 struct hisi_sas_complete_v3_hdr {
293 __le32 dw0;
294 __le32 dw1;
295 __le32 act;
296 __le32 dw3;
297 };
298
299 struct hisi_sas_err_record_v3 {
300 /* dw0 */
301 __le32 trans_tx_fail_type;
302
303 /* dw1 */
304 __le32 trans_rx_fail_type;
305
306 /* dw2 */
307 __le16 dma_tx_err_type;
308 __le16 sipc_rx_err_type;
309
310 /* dw3 */
311 __le32 dma_rx_err_type;
312 };
313
314 #define RX_DATA_LEN_UNDERFLOW_OFF 6
315 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
316
317 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
318 #define HISI_SAS_MSI_COUNT_V3_HW 32
319
320 enum {
321 HISI_SAS_PHY_PHY_UPDOWN,
322 HISI_SAS_PHY_CHNL_INT,
323 HISI_SAS_PHY_INT_NR
324 };
325
326 #define DIR_NO_DATA 0
327 #define DIR_TO_INI 1
328 #define DIR_TO_DEVICE 2
329 #define DIR_RESERVED 3
330
331 #define CMD_IS_UNCONSTRAINT(cmd) \
332 ((cmd == ATA_CMD_READ_LOG_EXT) || \
333 (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
334 (cmd == ATA_CMD_DEV_RESET))
335
336 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
337 {
338 void __iomem *regs = hisi_hba->regs + off;
339
340 return readl(regs);
341 }
342
343 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
344 {
345 void __iomem *regs = hisi_hba->regs + off;
346
347 return readl_relaxed(regs);
348 }
349
350 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
351 {
352 void __iomem *regs = hisi_hba->regs + off;
353
354 writel(val, regs);
355 }
356
357 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
358 u32 off, u32 val)
359 {
360 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
361
362 writel(val, regs);
363 }
364
365 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
366 int phy_no, u32 off)
367 {
368 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
369
370 return readl(regs);
371 }
372
373 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
374 {
375 int i;
376
377 /* Global registers init */
378 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
379 (u32)((1ULL << hisi_hba->queue_count) - 1));
380 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
381 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
382 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
383 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
384 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
385 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
386 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
387 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
388 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
389 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
390 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
391 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
392 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
393 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
394 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
395 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
396 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
397 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
398 for (i = 0; i < hisi_hba->queue_count; i++)
399 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
400
401 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
402 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE, 0x30000);
403
404 for (i = 0; i < hisi_hba->n_phy; i++) {
405 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x801);
406 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
407 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
408 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
409 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
410 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
411 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
412 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
413 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
414 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
415 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
416 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
417 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
418 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199b4fa);
419 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG,
420 0xa03e8);
421 hisi_sas_phy_write32(hisi_hba, i, SAS_STP_CON_TIMER_CFG,
422 0xa03e8);
423 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER,
424 0x7f7a120);
425 }
426 for (i = 0; i < hisi_hba->queue_count; i++) {
427 /* Delivery queue */
428 hisi_sas_write32(hisi_hba,
429 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
430 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
431
432 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
433 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
434
435 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
436 HISI_SAS_QUEUE_SLOTS);
437
438 /* Completion queue */
439 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
440 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
441
442 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
443 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
444
445 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
446 HISI_SAS_QUEUE_SLOTS);
447 }
448
449 /* itct */
450 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
451 lower_32_bits(hisi_hba->itct_dma));
452
453 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
454 upper_32_bits(hisi_hba->itct_dma));
455
456 /* iost */
457 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
458 lower_32_bits(hisi_hba->iost_dma));
459
460 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
461 upper_32_bits(hisi_hba->iost_dma));
462
463 /* breakpoint */
464 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
465 lower_32_bits(hisi_hba->breakpoint_dma));
466
467 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
468 upper_32_bits(hisi_hba->breakpoint_dma));
469
470 /* SATA broken msg */
471 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
472 lower_32_bits(hisi_hba->sata_breakpoint_dma));
473
474 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
475 upper_32_bits(hisi_hba->sata_breakpoint_dma));
476
477 /* SATA initial fis */
478 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
479 lower_32_bits(hisi_hba->initial_fis_dma));
480
481 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
482 upper_32_bits(hisi_hba->initial_fis_dma));
483 }
484
485 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
486 {
487 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
488
489 cfg &= ~PHY_CFG_DC_OPT_MSK;
490 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
491 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
492 }
493
494 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
495 {
496 struct sas_identify_frame identify_frame;
497 u32 *identify_buffer;
498
499 memset(&identify_frame, 0, sizeof(identify_frame));
500 identify_frame.dev_type = SAS_END_DEVICE;
501 identify_frame.frame_type = 0;
502 identify_frame._un1 = 1;
503 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
504 identify_frame.target_bits = SAS_PROTOCOL_NONE;
505 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
506 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
507 identify_frame.phy_id = phy_no;
508 identify_buffer = (u32 *)(&identify_frame);
509
510 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
511 __swab32(identify_buffer[0]));
512 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
513 __swab32(identify_buffer[1]));
514 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
515 __swab32(identify_buffer[2]));
516 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
517 __swab32(identify_buffer[3]));
518 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
519 __swab32(identify_buffer[4]));
520 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
521 __swab32(identify_buffer[5]));
522 }
523
524 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
525 struct hisi_sas_device *sas_dev)
526 {
527 struct domain_device *device = sas_dev->sas_device;
528 struct device *dev = hisi_hba->dev;
529 u64 qw0, device_id = sas_dev->device_id;
530 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
531 struct domain_device *parent_dev = device->parent;
532 struct asd_sas_port *sas_port = device->port;
533 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
534
535 memset(itct, 0, sizeof(*itct));
536
537 /* qw0 */
538 qw0 = 0;
539 switch (sas_dev->dev_type) {
540 case SAS_END_DEVICE:
541 case SAS_EDGE_EXPANDER_DEVICE:
542 case SAS_FANOUT_EXPANDER_DEVICE:
543 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
544 break;
545 case SAS_SATA_DEV:
546 case SAS_SATA_PENDING:
547 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
548 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
549 else
550 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
551 break;
552 default:
553 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
554 sas_dev->dev_type);
555 }
556
557 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
558 (device->linkrate << ITCT_HDR_MCR_OFF) |
559 (1 << ITCT_HDR_VLN_OFF) |
560 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
561 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
562 (port->id << ITCT_HDR_PORT_ID_OFF));
563 itct->qw0 = cpu_to_le64(qw0);
564
565 /* qw1 */
566 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
567 itct->sas_addr = __swab64(itct->sas_addr);
568
569 /* qw2 */
570 if (!dev_is_sata(device))
571 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
572 (0x1ULL << ITCT_HDR_RTOLT_OFF));
573 }
574
575 static void free_device_v3_hw(struct hisi_hba *hisi_hba,
576 struct hisi_sas_device *sas_dev)
577 {
578 u64 dev_id = sas_dev->device_id;
579 struct device *dev = hisi_hba->dev;
580 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
581 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
582
583 /* clear the itct interrupt state */
584 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
585 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
586 ENT_INT_SRC3_ITC_INT_MSK);
587
588 /* clear the itct table*/
589 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
590 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
591 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
592
593 udelay(10);
594 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
595 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
596 dev_dbg(dev, "got clear ITCT done interrupt\n");
597
598 /* invalid the itct state*/
599 memset(itct, 0, sizeof(struct hisi_sas_itct));
600 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
601 ENT_INT_SRC3_ITC_INT_MSK);
602
603 /* clear the itct */
604 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
605 dev_dbg(dev, "clear ITCT ok\n");
606 }
607 }
608
609 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
610 struct domain_device *device)
611 {
612 struct hisi_sas_slot *slot, *slot2;
613 struct hisi_sas_device *sas_dev = device->lldd_dev;
614 u32 cfg_abt_set_query_iptt;
615
616 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
617 CFG_ABT_SET_QUERY_IPTT);
618 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
619 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
620 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
621 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
622 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
623 cfg_abt_set_query_iptt);
624 }
625 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
626 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
627 cfg_abt_set_query_iptt);
628 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
629 1 << CFG_ABT_SET_IPTT_DONE_OFF);
630 }
631
632 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
633 {
634 struct device *dev = hisi_hba->dev;
635 int ret;
636 u32 val;
637
638 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
639
640 /* Disable all of the PHYs */
641 hisi_sas_stop_phys(hisi_hba);
642 udelay(50);
643
644 /* Ensure axi bus idle */
645 ret = readl_poll_timeout(hisi_hba->regs + AXI_CFG, val, !val,
646 20000, 1000000);
647 if (ret) {
648 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
649 return -EIO;
650 }
651
652 if (ACPI_HANDLE(dev)) {
653 acpi_status s;
654
655 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
656 if (ACPI_FAILURE(s)) {
657 dev_err(dev, "Reset failed\n");
658 return -EIO;
659 }
660 } else
661 dev_err(dev, "no reset method!\n");
662
663 return 0;
664 }
665
666 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
667 {
668 struct device *dev = hisi_hba->dev;
669 int rc;
670
671 rc = reset_hw_v3_hw(hisi_hba);
672 if (rc) {
673 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
674 return rc;
675 }
676
677 msleep(100);
678 init_reg_v3_hw(hisi_hba);
679
680 return 0;
681 }
682
683 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
684 {
685 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
686
687 cfg |= PHY_CFG_ENA_MSK;
688 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
689 }
690
691 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
692 {
693 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
694
695 cfg &= ~PHY_CFG_ENA_MSK;
696 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
697 }
698
699 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
700 {
701 config_id_frame_v3_hw(hisi_hba, phy_no);
702 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
703 enable_phy_v3_hw(hisi_hba, phy_no);
704 }
705
706 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
707 {
708 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
709 u32 txid_auto;
710
711 disable_phy_v3_hw(hisi_hba, phy_no);
712 if (phy->identify.device_type == SAS_END_DEVICE) {
713 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
714 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
715 txid_auto | TX_HARDRST_MSK);
716 }
717 msleep(100);
718 start_phy_v3_hw(hisi_hba, phy_no);
719 }
720
721 enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
722 {
723 return SAS_LINK_RATE_12_0_GBPS;
724 }
725
726 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
727 {
728 int i;
729
730 for (i = 0; i < hisi_hba->n_phy; i++) {
731 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
732 struct asd_sas_phy *sas_phy = &phy->sas_phy;
733
734 if (!sas_phy->phy->enabled)
735 continue;
736
737 start_phy_v3_hw(hisi_hba, i);
738 }
739 }
740
741 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
742 {
743 u32 sl_control;
744
745 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
746 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
747 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
748 msleep(1);
749 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
750 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
751 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
752 }
753
754 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
755 {
756 int i, bitmap = 0;
757 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
758
759 for (i = 0; i < hisi_hba->n_phy; i++)
760 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
761 bitmap |= 1 << i;
762
763 return bitmap;
764 }
765
766 /**
767 * The callpath to this function and upto writing the write
768 * queue pointer should be safe from interruption.
769 */
770 static int
771 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
772 {
773 struct device *dev = hisi_hba->dev;
774 int queue = dq->id;
775 u32 r, w;
776
777 w = dq->wr_point;
778 r = hisi_sas_read32_relaxed(hisi_hba,
779 DLVRY_Q_0_RD_PTR + (queue * 0x14));
780 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
781 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
782 queue, r, w);
783 return -EAGAIN;
784 }
785
786 return 0;
787 }
788
789 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
790 {
791 struct hisi_hba *hisi_hba = dq->hisi_hba;
792 int dlvry_queue = dq->slot_prep->dlvry_queue;
793 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
794
795 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
796 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
797 dq->wr_point);
798 }
799
800 static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
801 struct hisi_sas_slot *slot,
802 struct hisi_sas_cmd_hdr *hdr,
803 struct scatterlist *scatter,
804 int n_elem)
805 {
806 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
807 struct device *dev = hisi_hba->dev;
808 struct scatterlist *sg;
809 int i;
810
811 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
812 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
813 n_elem);
814 return -EINVAL;
815 }
816
817 for_each_sg(scatter, sg, n_elem, i) {
818 struct hisi_sas_sge *entry = &sge_page->sge[i];
819
820 entry->addr = cpu_to_le64(sg_dma_address(sg));
821 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
822 entry->data_len = cpu_to_le32(sg_dma_len(sg));
823 entry->data_off = 0;
824 }
825
826 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
827
828 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
829
830 return 0;
831 }
832
833 static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
834 struct hisi_sas_slot *slot, int is_tmf,
835 struct hisi_sas_tmf_task *tmf)
836 {
837 struct sas_task *task = slot->task;
838 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
839 struct domain_device *device = task->dev;
840 struct hisi_sas_device *sas_dev = device->lldd_dev;
841 struct hisi_sas_port *port = slot->port;
842 struct sas_ssp_task *ssp_task = &task->ssp_task;
843 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
844 int has_data = 0, rc, priority = is_tmf;
845 u8 *buf_cmd;
846 u32 dw1 = 0, dw2 = 0;
847
848 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
849 (2 << CMD_HDR_TLR_CTRL_OFF) |
850 (port->id << CMD_HDR_PORT_OFF) |
851 (priority << CMD_HDR_PRIORITY_OFF) |
852 (1 << CMD_HDR_CMD_OFF)); /* ssp */
853
854 dw1 = 1 << CMD_HDR_VDTL_OFF;
855 if (is_tmf) {
856 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
857 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
858 } else {
859 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
860 switch (scsi_cmnd->sc_data_direction) {
861 case DMA_TO_DEVICE:
862 has_data = 1;
863 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
864 break;
865 case DMA_FROM_DEVICE:
866 has_data = 1;
867 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
868 break;
869 default:
870 dw1 &= ~CMD_HDR_DIR_MSK;
871 }
872 }
873
874 /* map itct entry */
875 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
876 hdr->dw1 = cpu_to_le32(dw1);
877
878 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
879 + 3) / 4) << CMD_HDR_CFL_OFF) |
880 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
881 (2 << CMD_HDR_SG_MOD_OFF);
882 hdr->dw2 = cpu_to_le32(dw2);
883 hdr->transfer_tags = cpu_to_le32(slot->idx);
884
885 if (has_data) {
886 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
887 slot->n_elem);
888 if (rc)
889 return rc;
890 }
891
892 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
893 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
894 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
895
896 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
897 sizeof(struct ssp_frame_hdr);
898
899 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
900 if (!is_tmf) {
901 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
902 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
903 } else {
904 buf_cmd[10] = tmf->tmf;
905 switch (tmf->tmf) {
906 case TMF_ABORT_TASK:
907 case TMF_QUERY_TASK:
908 buf_cmd[12] =
909 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
910 buf_cmd[13] =
911 tmf->tag_of_task_to_be_managed & 0xff;
912 break;
913 default:
914 break;
915 }
916 }
917
918 return 0;
919 }
920
921 static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
922 struct hisi_sas_slot *slot)
923 {
924 struct sas_task *task = slot->task;
925 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
926 struct domain_device *device = task->dev;
927 struct device *dev = hisi_hba->dev;
928 struct hisi_sas_port *port = slot->port;
929 struct scatterlist *sg_req, *sg_resp;
930 struct hisi_sas_device *sas_dev = device->lldd_dev;
931 dma_addr_t req_dma_addr;
932 unsigned int req_len, resp_len;
933 int elem, rc;
934
935 /*
936 * DMA-map SMP request, response buffers
937 */
938 /* req */
939 sg_req = &task->smp_task.smp_req;
940 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
941 if (!elem)
942 return -ENOMEM;
943 req_len = sg_dma_len(sg_req);
944 req_dma_addr = sg_dma_address(sg_req);
945
946 /* resp */
947 sg_resp = &task->smp_task.smp_resp;
948 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
949 if (!elem) {
950 rc = -ENOMEM;
951 goto err_out_req;
952 }
953 resp_len = sg_dma_len(sg_resp);
954 if ((req_len & 0x3) || (resp_len & 0x3)) {
955 rc = -EINVAL;
956 goto err_out_resp;
957 }
958
959 /* create header */
960 /* dw0 */
961 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
962 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
963 (2 << CMD_HDR_CMD_OFF)); /* smp */
964
965 /* map itct entry */
966 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
967 (1 << CMD_HDR_FRAME_TYPE_OFF) |
968 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
969
970 /* dw2 */
971 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
972 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
973 CMD_HDR_MRFL_OFF));
974
975 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
976
977 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
978 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
979
980 return 0;
981
982 err_out_resp:
983 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
984 DMA_FROM_DEVICE);
985 err_out_req:
986 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
987 DMA_TO_DEVICE);
988 return rc;
989 }
990
991 static int get_ncq_tag_v3_hw(struct sas_task *task, u32 *tag)
992 {
993 struct ata_queued_cmd *qc = task->uldd_task;
994
995 if (qc) {
996 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
997 qc->tf.command == ATA_CMD_FPDMA_READ) {
998 *tag = qc->tag;
999 return 1;
1000 }
1001 }
1002 return 0;
1003 }
1004
1005 static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1006 struct hisi_sas_slot *slot)
1007 {
1008 struct sas_task *task = slot->task;
1009 struct domain_device *device = task->dev;
1010 struct domain_device *parent_dev = device->parent;
1011 struct hisi_sas_device *sas_dev = device->lldd_dev;
1012 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1013 struct asd_sas_port *sas_port = device->port;
1014 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1015 u8 *buf_cmd;
1016 int has_data = 0, rc = 0, hdr_tag = 0;
1017 u32 dw1 = 0, dw2 = 0;
1018
1019 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1020 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1021 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1022 else
1023 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1024
1025 switch (task->data_dir) {
1026 case DMA_TO_DEVICE:
1027 has_data = 1;
1028 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1029 break;
1030 case DMA_FROM_DEVICE:
1031 has_data = 1;
1032 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1033 break;
1034 default:
1035 dw1 &= ~CMD_HDR_DIR_MSK;
1036 }
1037
1038 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1039 (task->ata_task.fis.control & ATA_SRST))
1040 dw1 |= 1 << CMD_HDR_RESET_OFF;
1041
1042 dw1 |= (hisi_sas_get_ata_protocol(
1043 task->ata_task.fis.command, task->data_dir))
1044 << CMD_HDR_FRAME_TYPE_OFF;
1045 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1046
1047 if (CMD_IS_UNCONSTRAINT(task->ata_task.fis.command))
1048 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1049
1050 hdr->dw1 = cpu_to_le32(dw1);
1051
1052 /* dw2 */
1053 if (task->ata_task.use_ncq && get_ncq_tag_v3_hw(task, &hdr_tag)) {
1054 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1055 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1056 }
1057
1058 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1059 2 << CMD_HDR_SG_MOD_OFF;
1060 hdr->dw2 = cpu_to_le32(dw2);
1061
1062 /* dw3 */
1063 hdr->transfer_tags = cpu_to_le32(slot->idx);
1064
1065 if (has_data) {
1066 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1067 slot->n_elem);
1068 if (rc)
1069 return rc;
1070 }
1071
1072 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1073 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1074 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1075
1076 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1077
1078 if (likely(!task->ata_task.device_control_reg_update))
1079 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1080 /* fill in command FIS */
1081 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1082
1083 return 0;
1084 }
1085
1086 static int prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1087 struct hisi_sas_slot *slot,
1088 int device_id, int abort_flag, int tag_to_abort)
1089 {
1090 struct sas_task *task = slot->task;
1091 struct domain_device *dev = task->dev;
1092 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1093 struct hisi_sas_port *port = slot->port;
1094
1095 /* dw0 */
1096 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1097 (port->id << CMD_HDR_PORT_OFF) |
1098 ((dev_is_sata(dev) ? 1:0)
1099 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1100 (abort_flag
1101 << CMD_HDR_ABORT_FLAG_OFF));
1102
1103 /* dw1 */
1104 hdr->dw1 = cpu_to_le32(device_id
1105 << CMD_HDR_DEV_ID_OFF);
1106
1107 /* dw7 */
1108 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1109 hdr->transfer_tags = cpu_to_le32(slot->idx);
1110
1111 return 0;
1112 }
1113
1114 static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1115 {
1116 int i, res = 0;
1117 u32 context, port_id, link_rate, hard_phy_linkrate;
1118 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1119 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1120 struct device *dev = hisi_hba->dev;
1121
1122 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1123
1124 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1125 port_id = (port_id >> (4 * phy_no)) & 0xf;
1126 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1127 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1128
1129 if (port_id == 0xf) {
1130 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1131 res = IRQ_NONE;
1132 goto end;
1133 }
1134 sas_phy->linkrate = link_rate;
1135 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1136 HARD_PHY_LINKRATE);
1137 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1138 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1139 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1140
1141 /* Check for SATA dev */
1142 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1143 if (context & (1 << phy_no)) {
1144 struct hisi_sas_initial_fis *initial_fis;
1145 struct dev_to_host_fis *fis;
1146 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1147
1148 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1149 initial_fis = &hisi_hba->initial_fis[phy_no];
1150 fis = &initial_fis->fis;
1151 sas_phy->oob_mode = SATA_OOB_MODE;
1152 attached_sas_addr[0] = 0x50;
1153 attached_sas_addr[7] = phy_no;
1154 memcpy(sas_phy->attached_sas_addr,
1155 attached_sas_addr,
1156 SAS_ADDR_SIZE);
1157 memcpy(sas_phy->frame_rcvd, fis,
1158 sizeof(struct dev_to_host_fis));
1159 phy->phy_type |= PORT_TYPE_SATA;
1160 phy->identify.device_type = SAS_SATA_DEV;
1161 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1162 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1163 } else {
1164 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1165 struct sas_identify_frame *id =
1166 (struct sas_identify_frame *)frame_rcvd;
1167
1168 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1169 for (i = 0; i < 6; i++) {
1170 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1171 RX_IDAF_DWORD0 + (i * 4));
1172 frame_rcvd[i] = __swab32(idaf);
1173 }
1174 sas_phy->oob_mode = SAS_OOB_MODE;
1175 memcpy(sas_phy->attached_sas_addr,
1176 &id->sas_addr,
1177 SAS_ADDR_SIZE);
1178 phy->phy_type |= PORT_TYPE_SAS;
1179 phy->identify.device_type = id->dev_type;
1180 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1181 if (phy->identify.device_type == SAS_END_DEVICE)
1182 phy->identify.target_port_protocols =
1183 SAS_PROTOCOL_SSP;
1184 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1185 phy->identify.target_port_protocols =
1186 SAS_PROTOCOL_SMP;
1187 }
1188
1189 phy->port_id = port_id;
1190 phy->phy_attached = 1;
1191 queue_work(hisi_hba->wq, &phy->phyup_ws);
1192
1193 end:
1194 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1195 CHL_INT0_SL_PHY_ENABLE_MSK);
1196 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1197
1198 return res;
1199 }
1200
1201 static int phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1202 {
1203 u32 phy_state, sl_ctrl, txid_auto;
1204 struct device *dev = hisi_hba->dev;
1205
1206 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1207
1208 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1209 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1210 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1211
1212 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1213 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1214 sl_ctrl&(~SL_CTA_MSK));
1215
1216 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1217 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1218 txid_auto | CT3_MSK);
1219
1220 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1221 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1222
1223 return 0;
1224 }
1225
1226 static void phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1227 {
1228 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1229 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1230 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1231
1232 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1233 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1234 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1235 CHL_INT0_SL_RX_BCST_ACK_MSK);
1236 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1237 }
1238
1239 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1240 {
1241 struct hisi_hba *hisi_hba = p;
1242 u32 irq_msk;
1243 int phy_no = 0;
1244 irqreturn_t res = IRQ_NONE;
1245
1246 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1247 & 0x11111111;
1248 while (irq_msk) {
1249 if (irq_msk & 1) {
1250 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1251 CHL_INT0);
1252 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1253 int rdy = phy_state & (1 << phy_no);
1254
1255 if (rdy) {
1256 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1257 /* phy up */
1258 if (phy_up_v3_hw(phy_no, hisi_hba)
1259 == IRQ_HANDLED)
1260 res = IRQ_HANDLED;
1261 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1262 /* phy bcast */
1263 phy_bcast_v3_hw(phy_no, hisi_hba);
1264 } else {
1265 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1266 /* phy down */
1267 if (phy_down_v3_hw(phy_no, hisi_hba)
1268 == IRQ_HANDLED)
1269 res = IRQ_HANDLED;
1270 }
1271 }
1272 irq_msk >>= 4;
1273 phy_no++;
1274 }
1275
1276 return res;
1277 }
1278
1279 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1280 {
1281 struct hisi_hba *hisi_hba = p;
1282 struct device *dev = hisi_hba->dev;
1283 u32 ent_msk, ent_tmp, irq_msk;
1284 int phy_no = 0;
1285
1286 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1287 ent_tmp = ent_msk;
1288 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1289 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1290
1291 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1292 & 0xeeeeeeee;
1293
1294 while (irq_msk) {
1295 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1296 CHL_INT0);
1297 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1298 CHL_INT1);
1299 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1300 CHL_INT2);
1301
1302 if ((irq_msk & (4 << (phy_no * 4))) &&
1303 irq_value1) {
1304 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
1305 CHL_INT1_DMAC_TX_ECC_ERR_MSK))
1306 panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
1307 dev_name(dev), irq_value1);
1308
1309 hisi_sas_phy_write32(hisi_hba, phy_no,
1310 CHL_INT1, irq_value1);
1311 }
1312
1313 if (irq_msk & (8 << (phy_no * 4)) && irq_value2)
1314 hisi_sas_phy_write32(hisi_hba, phy_no,
1315 CHL_INT2, irq_value2);
1316
1317
1318 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1319 hisi_sas_phy_write32(hisi_hba, phy_no,
1320 CHL_INT0, irq_value0
1321 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1322 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1323 & (~CHL_INT0_NOT_RDY_MSK));
1324 }
1325 irq_msk &= ~(0xe << (phy_no * 4));
1326 phy_no++;
1327 }
1328
1329 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1330
1331 return IRQ_HANDLED;
1332 }
1333
1334 static void
1335 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1336 struct hisi_sas_slot *slot)
1337 {
1338 struct task_status_struct *ts = &task->task_status;
1339 struct hisi_sas_complete_v3_hdr *complete_queue =
1340 hisi_hba->complete_hdr[slot->cmplt_queue];
1341 struct hisi_sas_complete_v3_hdr *complete_hdr =
1342 &complete_queue[slot->cmplt_queue_slot];
1343 struct hisi_sas_err_record_v3 *record =
1344 hisi_sas_status_buf_addr_mem(slot);
1345 u32 dma_rx_err_type = record->dma_rx_err_type;
1346 u32 trans_tx_fail_type = record->trans_tx_fail_type;
1347
1348 switch (task->task_proto) {
1349 case SAS_PROTOCOL_SSP:
1350 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1351 ts->residual = trans_tx_fail_type;
1352 ts->stat = SAS_DATA_UNDERRUN;
1353 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1354 ts->stat = SAS_QUEUE_FULL;
1355 slot->abort = 1;
1356 } else {
1357 ts->stat = SAS_OPEN_REJECT;
1358 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1359 }
1360 break;
1361 case SAS_PROTOCOL_SATA:
1362 case SAS_PROTOCOL_STP:
1363 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1364 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1365 ts->residual = trans_tx_fail_type;
1366 ts->stat = SAS_DATA_UNDERRUN;
1367 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1368 ts->stat = SAS_PHY_DOWN;
1369 slot->abort = 1;
1370 } else {
1371 ts->stat = SAS_OPEN_REJECT;
1372 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1373 }
1374 hisi_sas_sata_done(task, slot);
1375 break;
1376 case SAS_PROTOCOL_SMP:
1377 ts->stat = SAM_STAT_CHECK_CONDITION;
1378 break;
1379 default:
1380 break;
1381 }
1382 }
1383
1384 static int
1385 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1386 {
1387 struct sas_task *task = slot->task;
1388 struct hisi_sas_device *sas_dev;
1389 struct device *dev = hisi_hba->dev;
1390 struct task_status_struct *ts;
1391 struct domain_device *device;
1392 enum exec_status sts;
1393 struct hisi_sas_complete_v3_hdr *complete_queue =
1394 hisi_hba->complete_hdr[slot->cmplt_queue];
1395 struct hisi_sas_complete_v3_hdr *complete_hdr =
1396 &complete_queue[slot->cmplt_queue_slot];
1397 int aborted;
1398 unsigned long flags;
1399
1400 if (unlikely(!task || !task->lldd_task || !task->dev))
1401 return -EINVAL;
1402
1403 ts = &task->task_status;
1404 device = task->dev;
1405 sas_dev = device->lldd_dev;
1406
1407 spin_lock_irqsave(&task->task_state_lock, flags);
1408 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1409 task->task_state_flags &=
1410 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1411 spin_unlock_irqrestore(&task->task_state_lock, flags);
1412
1413 memset(ts, 0, sizeof(*ts));
1414 ts->resp = SAS_TASK_COMPLETE;
1415 if (unlikely(aborted)) {
1416 ts->stat = SAS_ABORTED_TASK;
1417 hisi_sas_slot_task_free(hisi_hba, task, slot);
1418 return -1;
1419 }
1420
1421 if (unlikely(!sas_dev)) {
1422 dev_dbg(dev, "slot complete: port has not device\n");
1423 ts->stat = SAS_PHY_DOWN;
1424 goto out;
1425 }
1426
1427 /*
1428 * Use SAS+TMF status codes
1429 */
1430 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1431 >> CMPLT_HDR_ABORT_STAT_OFF) {
1432 case STAT_IO_ABORTED:
1433 /* this IO has been aborted by abort command */
1434 ts->stat = SAS_ABORTED_TASK;
1435 goto out;
1436 case STAT_IO_COMPLETE:
1437 /* internal abort command complete */
1438 ts->stat = TMF_RESP_FUNC_SUCC;
1439 goto out;
1440 case STAT_IO_NO_DEVICE:
1441 ts->stat = TMF_RESP_FUNC_COMPLETE;
1442 goto out;
1443 case STAT_IO_NOT_VALID:
1444 /*
1445 * abort single IO, the controller can't find the IO
1446 */
1447 ts->stat = TMF_RESP_FUNC_FAILED;
1448 goto out;
1449 default:
1450 break;
1451 }
1452
1453 /* check for erroneous completion */
1454 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1455 slot_err_v3_hw(hisi_hba, task, slot);
1456 if (unlikely(slot->abort))
1457 return ts->stat;
1458 goto out;
1459 }
1460
1461 switch (task->task_proto) {
1462 case SAS_PROTOCOL_SSP: {
1463 struct ssp_response_iu *iu =
1464 hisi_sas_status_buf_addr_mem(slot) +
1465 sizeof(struct hisi_sas_err_record);
1466
1467 sas_ssp_task_response(dev, task, iu);
1468 break;
1469 }
1470 case SAS_PROTOCOL_SMP: {
1471 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1472 void *to;
1473
1474 ts->stat = SAM_STAT_GOOD;
1475 to = kmap_atomic(sg_page(sg_resp));
1476
1477 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1478 DMA_FROM_DEVICE);
1479 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1480 DMA_TO_DEVICE);
1481 memcpy(to + sg_resp->offset,
1482 hisi_sas_status_buf_addr_mem(slot) +
1483 sizeof(struct hisi_sas_err_record),
1484 sg_dma_len(sg_resp));
1485 kunmap_atomic(to);
1486 break;
1487 }
1488 case SAS_PROTOCOL_SATA:
1489 case SAS_PROTOCOL_STP:
1490 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1491 ts->stat = SAM_STAT_GOOD;
1492 hisi_sas_sata_done(task, slot);
1493 break;
1494 default:
1495 ts->stat = SAM_STAT_CHECK_CONDITION;
1496 break;
1497 }
1498
1499 if (!slot->port->port_attached) {
1500 dev_err(dev, "slot complete: port %d has removed\n",
1501 slot->port->sas_port.id);
1502 ts->stat = SAS_PHY_DOWN;
1503 }
1504
1505 out:
1506 spin_lock_irqsave(&task->task_state_lock, flags);
1507 task->task_state_flags |= SAS_TASK_STATE_DONE;
1508 spin_unlock_irqrestore(&task->task_state_lock, flags);
1509 spin_lock_irqsave(&hisi_hba->lock, flags);
1510 hisi_sas_slot_task_free(hisi_hba, task, slot);
1511 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1512 sts = ts->stat;
1513
1514 if (task->task_done)
1515 task->task_done(task);
1516
1517 return sts;
1518 }
1519
1520 static void cq_tasklet_v3_hw(unsigned long val)
1521 {
1522 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1523 struct hisi_hba *hisi_hba = cq->hisi_hba;
1524 struct hisi_sas_slot *slot;
1525 struct hisi_sas_itct *itct;
1526 struct hisi_sas_complete_v3_hdr *complete_queue;
1527 u32 rd_point = cq->rd_point, wr_point, dev_id;
1528 int queue = cq->id;
1529 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
1530
1531 complete_queue = hisi_hba->complete_hdr[queue];
1532
1533 spin_lock(&dq->lock);
1534 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1535 (0x14 * queue));
1536
1537 while (rd_point != wr_point) {
1538 struct hisi_sas_complete_v3_hdr *complete_hdr;
1539 int iptt;
1540
1541 complete_hdr = &complete_queue[rd_point];
1542
1543 /* Check for NCQ completion */
1544 if (complete_hdr->act) {
1545 u32 act_tmp = complete_hdr->act;
1546 int ncq_tag_count = ffs(act_tmp);
1547
1548 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
1549 CMPLT_HDR_DEV_ID_OFF;
1550 itct = &hisi_hba->itct[dev_id];
1551
1552 /* The NCQ tags are held in the itct header */
1553 while (ncq_tag_count) {
1554 __le64 *ncq_tag = &itct->qw4_15[0];
1555
1556 ncq_tag_count -= 1;
1557 iptt = (ncq_tag[ncq_tag_count / 5]
1558 >> (ncq_tag_count % 5) * 12) & 0xfff;
1559
1560 slot = &hisi_hba->slot_info[iptt];
1561 slot->cmplt_queue_slot = rd_point;
1562 slot->cmplt_queue = queue;
1563 slot_complete_v3_hw(hisi_hba, slot);
1564
1565 act_tmp &= ~(1 << ncq_tag_count);
1566 ncq_tag_count = ffs(act_tmp);
1567 }
1568 } else {
1569 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1570 slot = &hisi_hba->slot_info[iptt];
1571 slot->cmplt_queue_slot = rd_point;
1572 slot->cmplt_queue = queue;
1573 slot_complete_v3_hw(hisi_hba, slot);
1574 }
1575
1576 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1577 rd_point = 0;
1578 }
1579
1580 /* update rd_point */
1581 cq->rd_point = rd_point;
1582 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1583 spin_unlock(&dq->lock);
1584 }
1585
1586 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1587 {
1588 struct hisi_sas_cq *cq = p;
1589 struct hisi_hba *hisi_hba = cq->hisi_hba;
1590 int queue = cq->id;
1591
1592 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1593
1594 tasklet_schedule(&cq->tasklet);
1595
1596 return IRQ_HANDLED;
1597 }
1598
1599 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1600 {
1601 struct device *dev = hisi_hba->dev;
1602 struct pci_dev *pdev = hisi_hba->pci_dev;
1603 int vectors, rc;
1604 int i, k;
1605 int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1606
1607 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1608 max_msi, PCI_IRQ_MSI);
1609 if (vectors < max_msi) {
1610 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1611 return -ENOENT;
1612 }
1613
1614 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1615 int_phy_up_down_bcast_v3_hw, 0,
1616 DRV_NAME " phy", hisi_hba);
1617 if (rc) {
1618 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1619 rc = -ENOENT;
1620 goto free_irq_vectors;
1621 }
1622
1623 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1624 int_chnl_int_v3_hw, 0,
1625 DRV_NAME " channel", hisi_hba);
1626 if (rc) {
1627 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1628 rc = -ENOENT;
1629 goto free_phy_irq;
1630 }
1631
1632 /* Init tasklets for cq only */
1633 for (i = 0; i < hisi_hba->queue_count; i++) {
1634 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1635 struct tasklet_struct *t = &cq->tasklet;
1636
1637 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1638 cq_interrupt_v3_hw, 0,
1639 DRV_NAME " cq", cq);
1640 if (rc) {
1641 dev_err(dev,
1642 "could not request cq%d interrupt, rc=%d\n",
1643 i, rc);
1644 rc = -ENOENT;
1645 goto free_cq_irqs;
1646 }
1647
1648 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1649 }
1650
1651 return 0;
1652
1653 free_cq_irqs:
1654 for (k = 0; k < i; k++) {
1655 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1656
1657 free_irq(pci_irq_vector(pdev, k+16), cq);
1658 }
1659 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1660 free_phy_irq:
1661 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1662 free_irq_vectors:
1663 pci_free_irq_vectors(pdev);
1664 return rc;
1665 }
1666
1667 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1668 {
1669 int rc;
1670
1671 rc = hw_init_v3_hw(hisi_hba);
1672 if (rc)
1673 return rc;
1674
1675 rc = interrupt_init_v3_hw(hisi_hba);
1676 if (rc)
1677 return rc;
1678
1679 return 0;
1680 }
1681
1682 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
1683 struct sas_phy_linkrates *r)
1684 {
1685 u32 prog_phy_link_rate =
1686 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1687 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1688 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1689 int i;
1690 enum sas_linkrate min, max;
1691 u32 rate_mask = 0;
1692
1693 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1694 max = sas_phy->phy->maximum_linkrate;
1695 min = r->minimum_linkrate;
1696 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1697 max = r->maximum_linkrate;
1698 min = sas_phy->phy->minimum_linkrate;
1699 } else
1700 return;
1701
1702 sas_phy->phy->maximum_linkrate = max;
1703 sas_phy->phy->minimum_linkrate = min;
1704
1705 min -= SAS_LINK_RATE_1_5_GBPS;
1706 max -= SAS_LINK_RATE_1_5_GBPS;
1707
1708 for (i = 0; i <= max; i++)
1709 rate_mask |= 1 << (i * 2);
1710
1711 prog_phy_link_rate &= ~0xff;
1712 prog_phy_link_rate |= rate_mask;
1713
1714 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1715 prog_phy_link_rate);
1716
1717 phy_hard_reset_v3_hw(hisi_hba, phy_no);
1718 }
1719
1720 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
1721 {
1722 struct pci_dev *pdev = hisi_hba->pci_dev;
1723 int i;
1724
1725 synchronize_irq(pci_irq_vector(pdev, 1));
1726 synchronize_irq(pci_irq_vector(pdev, 2));
1727 synchronize_irq(pci_irq_vector(pdev, 11));
1728 for (i = 0; i < hisi_hba->queue_count; i++) {
1729 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
1730 synchronize_irq(pci_irq_vector(pdev, i + 16));
1731 }
1732
1733 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
1734 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
1735 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
1736 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1737
1738 for (i = 0; i < hisi_hba->n_phy; i++) {
1739 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1740 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
1741 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
1742 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
1743 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
1744 }
1745 }
1746
1747 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
1748 {
1749 return hisi_sas_read32(hisi_hba, PHY_STATE);
1750 }
1751
1752 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
1753 {
1754 struct device *dev = hisi_hba->dev;
1755 int rc;
1756 u32 status;
1757
1758 interrupt_disable_v3_hw(hisi_hba);
1759 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
1760
1761 hisi_sas_stop_phys(hisi_hba);
1762
1763 mdelay(10);
1764
1765 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
1766
1767 /* wait until bus idle */
1768 rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
1769 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
1770 if (rc) {
1771 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
1772 return rc;
1773 }
1774
1775 hisi_sas_init_mem(hisi_hba);
1776
1777 return hw_init_v3_hw(hisi_hba);
1778 }
1779
1780 static const struct hisi_sas_hw hisi_sas_v3_hw = {
1781 .hw_init = hisi_sas_v3_init,
1782 .setup_itct = setup_itct_v3_hw,
1783 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
1784 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
1785 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
1786 .free_device = free_device_v3_hw,
1787 .sl_notify = sl_notify_v3_hw,
1788 .prep_ssp = prep_ssp_v3_hw,
1789 .prep_smp = prep_smp_v3_hw,
1790 .prep_stp = prep_ata_v3_hw,
1791 .prep_abort = prep_abort_v3_hw,
1792 .get_free_slot = get_free_slot_v3_hw,
1793 .start_delivery = start_delivery_v3_hw,
1794 .slot_complete = slot_complete_v3_hw,
1795 .phys_init = phys_init_v3_hw,
1796 .phy_enable = enable_phy_v3_hw,
1797 .phy_disable = disable_phy_v3_hw,
1798 .phy_hard_reset = phy_hard_reset_v3_hw,
1799 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
1800 .phy_set_linkrate = phy_set_linkrate_v3_hw,
1801 .dereg_device = dereg_device_v3_hw,
1802 .soft_reset = soft_reset_v3_hw,
1803 .get_phys_state = get_phys_state_v3_hw,
1804 };
1805
1806 static struct Scsi_Host *
1807 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
1808 {
1809 struct Scsi_Host *shost;
1810 struct hisi_hba *hisi_hba;
1811 struct device *dev = &pdev->dev;
1812
1813 shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
1814 if (!shost)
1815 goto err_out;
1816 hisi_hba = shost_priv(shost);
1817
1818 hisi_hba->hw = &hisi_sas_v3_hw;
1819 hisi_hba->pci_dev = pdev;
1820 hisi_hba->dev = dev;
1821 hisi_hba->shost = shost;
1822 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
1823
1824 init_timer(&hisi_hba->timer);
1825
1826 if (hisi_sas_get_fw_info(hisi_hba) < 0)
1827 goto err_out;
1828
1829 if (hisi_sas_alloc(hisi_hba, shost)) {
1830 hisi_sas_free(hisi_hba);
1831 goto err_out;
1832 }
1833
1834 return shost;
1835 err_out:
1836 dev_err(dev, "shost alloc failed\n");
1837 return NULL;
1838 }
1839
1840 static int
1841 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1842 {
1843 struct Scsi_Host *shost;
1844 struct hisi_hba *hisi_hba;
1845 struct device *dev = &pdev->dev;
1846 struct asd_sas_phy **arr_phy;
1847 struct asd_sas_port **arr_port;
1848 struct sas_ha_struct *sha;
1849 int rc, phy_nr, port_nr, i;
1850
1851 rc = pci_enable_device(pdev);
1852 if (rc)
1853 goto err_out;
1854
1855 pci_set_master(pdev);
1856
1857 rc = pci_request_regions(pdev, DRV_NAME);
1858 if (rc)
1859 goto err_out_disable_device;
1860
1861 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
1862 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
1863 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
1864 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
1865 dev_err(dev, "No usable DMA addressing method\n");
1866 rc = -EIO;
1867 goto err_out_regions;
1868 }
1869 }
1870
1871 shost = hisi_sas_shost_alloc_pci(pdev);
1872 if (!shost) {
1873 rc = -ENOMEM;
1874 goto err_out_regions;
1875 }
1876
1877 sha = SHOST_TO_SAS_HA(shost);
1878 hisi_hba = shost_priv(shost);
1879 dev_set_drvdata(dev, sha);
1880
1881 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
1882 if (!hisi_hba->regs) {
1883 dev_err(dev, "cannot map register.\n");
1884 rc = -ENOMEM;
1885 goto err_out_ha;
1886 }
1887
1888 phy_nr = port_nr = hisi_hba->n_phy;
1889
1890 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
1891 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
1892 if (!arr_phy || !arr_port) {
1893 rc = -ENOMEM;
1894 goto err_out_ha;
1895 }
1896
1897 sha->sas_phy = arr_phy;
1898 sha->sas_port = arr_port;
1899 sha->core.shost = shost;
1900 sha->lldd_ha = hisi_hba;
1901
1902 shost->transportt = hisi_sas_stt;
1903 shost->max_id = HISI_SAS_MAX_DEVICES;
1904 shost->max_lun = ~0;
1905 shost->max_channel = 1;
1906 shost->max_cmd_len = 16;
1907 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
1908 shost->can_queue = hisi_hba->hw->max_command_entries;
1909 shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
1910
1911 sha->sas_ha_name = DRV_NAME;
1912 sha->dev = dev;
1913 sha->lldd_module = THIS_MODULE;
1914 sha->sas_addr = &hisi_hba->sas_addr[0];
1915 sha->num_phys = hisi_hba->n_phy;
1916 sha->core.shost = hisi_hba->shost;
1917
1918 for (i = 0; i < hisi_hba->n_phy; i++) {
1919 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
1920 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
1921 }
1922
1923 hisi_sas_init_add(hisi_hba);
1924
1925 rc = scsi_add_host(shost, dev);
1926 if (rc)
1927 goto err_out_ha;
1928
1929 rc = sas_register_ha(sha);
1930 if (rc)
1931 goto err_out_register_ha;
1932
1933 rc = hisi_hba->hw->hw_init(hisi_hba);
1934 if (rc)
1935 goto err_out_register_ha;
1936
1937 scsi_scan_host(shost);
1938
1939 return 0;
1940
1941 err_out_register_ha:
1942 scsi_remove_host(shost);
1943 err_out_ha:
1944 kfree(shost);
1945 err_out_regions:
1946 pci_release_regions(pdev);
1947 err_out_disable_device:
1948 pci_disable_device(pdev);
1949 err_out:
1950 return rc;
1951 }
1952
1953 static void
1954 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
1955 {
1956 int i;
1957
1958 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1959 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1960 for (i = 0; i < hisi_hba->queue_count; i++) {
1961 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1962
1963 free_irq(pci_irq_vector(pdev, i+16), cq);
1964 tasklet_kill(&cq->tasklet);
1965 }
1966 pci_free_irq_vectors(pdev);
1967 }
1968
1969 static void hisi_sas_v3_remove(struct pci_dev *pdev)
1970 {
1971 struct device *dev = &pdev->dev;
1972 struct sas_ha_struct *sha = dev_get_drvdata(dev);
1973 struct hisi_hba *hisi_hba = sha->lldd_ha;
1974
1975 sas_unregister_ha(sha);
1976 sas_remove_host(sha->core.shost);
1977
1978 hisi_sas_free(hisi_hba);
1979 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
1980 pci_release_regions(pdev);
1981 pci_disable_device(pdev);
1982 }
1983
1984 enum {
1985 /* instances of the controller */
1986 hip08,
1987 };
1988
1989 static const struct pci_device_id sas_v3_pci_table[] = {
1990 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
1991 {}
1992 };
1993
1994 static struct pci_driver sas_v3_pci_driver = {
1995 .name = DRV_NAME,
1996 .id_table = sas_v3_pci_table,
1997 .probe = hisi_sas_v3_probe,
1998 .remove = hisi_sas_v3_remove,
1999 };
2000
2001 module_pci_driver(sas_v3_pci_driver);
2002
2003 MODULE_VERSION(DRV_VERSION);
2004 MODULE_LICENSE("GPL");
2005 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2006 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2007 MODULE_ALIAS("platform:" DRV_NAME);
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