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scsi: hisi_sas: fix the issue of setting linkrate register
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v3_hw.c
1 /*
2 * Copyright (c) 2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 #include "hisi_sas.h"
12 #define DRV_NAME "hisi_sas_v3_hw"
13
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
26 #define ITCT_CLR 0x44
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CFG_1US_TIMER_TRSH 0xcc
55 #define CHNL_INT_STATUS 0x148
56 #define HGC_AXI_FIFO_ERR_INFO 0x154
57 #define AXI_ERR_INFO_OFF 0
58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
59 #define FIFO_ERR_INFO_OFF 8
60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
61 #define INT_COAL_EN 0x19c
62 #define OQ_INT_COAL_TIME 0x1a0
63 #define OQ_INT_COAL_CNT 0x1a4
64 #define ENT_INT_COAL_TIME 0x1a8
65 #define ENT_INT_COAL_CNT 0x1ac
66 #define OQ_INT_SRC 0x1b0
67 #define OQ_INT_SRC_MSK 0x1b4
68 #define ENT_INT_SRC1 0x1b8
69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
73 #define ENT_INT_SRC2 0x1bc
74 #define ENT_INT_SRC3 0x1c0
75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
78 #define ENT_INT_SRC3_AXI_OFF 11
79 #define ENT_INT_SRC3_FIFO_OFF 12
80 #define ENT_INT_SRC3_LM_OFF 14
81 #define ENT_INT_SRC3_ITC_INT_OFF 15
82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
83 #define ENT_INT_SRC3_ABT_OFF 16
84 #define ENT_INT_SRC_MSK1 0x1c4
85 #define ENT_INT_SRC_MSK2 0x1c8
86 #define ENT_INT_SRC_MSK3 0x1cc
87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
89 #define CHNL_ENT_INT_MSK 0x1d4
90 #define HGC_COM_INT_MSK 0x1d8
91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
92 #define SAS_ECC_INTR 0x1e8
93 #define SAS_ECC_INTR_MSK 0x1ec
94 #define HGC_ERR_STAT_EN 0x238
95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
97 #define DLVRY_Q_0_DEPTH 0x268
98 #define DLVRY_Q_0_WR_PTR 0x26c
99 #define DLVRY_Q_0_RD_PTR 0x270
100 #define HYPER_STREAM_ID_EN_CFG 0xc80
101 #define OQ0_INT_SRC_MSK 0xc90
102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
104 #define COMPL_Q_0_DEPTH 0x4e8
105 #define COMPL_Q_0_WR_PTR 0x4ec
106 #define COMPL_Q_0_RD_PTR 0x4f0
107 #define AWQOS_AWCACHE_CFG 0xc84
108 #define ARQOS_ARCACHE_CFG 0xc88
109
110 /* phy registers requiring init */
111 #define PORT_BASE (0x2000)
112 #define PHY_CFG (PORT_BASE + 0x0)
113 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
114 #define PHY_CFG_ENA_OFF 0
115 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
116 #define PHY_CFG_DC_OPT_OFF 2
117 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
118 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
119 #define PHY_CTRL (PORT_BASE + 0x14)
120 #define PHY_CTRL_RESET_OFF 0
121 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
122 #define SL_CFG (PORT_BASE + 0x84)
123 #define SL_CONTROL (PORT_BASE + 0x94)
124 #define SL_CONTROL_NOTIFY_EN_OFF 0
125 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
126 #define SL_CTA_OFF 17
127 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
128 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
129 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
130 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
131 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
132 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
133 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
134 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
135 #define TXID_AUTO (PORT_BASE + 0xb8)
136 #define CT3_OFF 1
137 #define CT3_MSK (0x1 << CT3_OFF)
138 #define TX_HARDRST_OFF 2
139 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
140 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
141 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
142 #define STP_LINK_TIMER (PORT_BASE + 0x120)
143 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
144 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
145 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
146 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
147 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
148 #define CHL_INT0 (PORT_BASE + 0x1b4)
149 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
150 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
151 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
152 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
153 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
154 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
155 #define CHL_INT0_NOT_RDY_OFF 4
156 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
157 #define CHL_INT0_PHY_RDY_OFF 5
158 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
159 #define CHL_INT1 (PORT_BASE + 0x1b8)
160 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
161 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
162 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
163 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
164 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
165 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
166 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
167 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
168 #define CHL_INT2 (PORT_BASE + 0x1bc)
169 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
170 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
171 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
172 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
173 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
174 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
175 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
176 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
177 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
178 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
179 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
180 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
181 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
182 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
183 #define DMA_TX_STATUS_BUSY_OFF 0
184 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
185 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
186 #define DMA_RX_STATUS_BUSY_OFF 0
187 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
188
189 #define COARSETUNE_TIME (PORT_BASE + 0x304)
190 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
191 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
192 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
193 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
194
195 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
196 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
197 #error Max ITCT exceeded
198 #endif
199
200 #define AXI_MASTER_CFG_BASE (0x5000)
201 #define AM_CTRL_GLOBAL (0x0)
202 #define AM_CURR_TRANS_RETURN (0x150)
203
204 #define AM_CFG_MAX_TRANS (0x5010)
205 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
206 #define AXI_CFG (0x5100)
207 #define AM_ROB_ECC_ERR_ADDR (0x510c)
208 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
209 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
210 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
211 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
212
213 /* RAS registers need init */
214 #define RAS_BASE (0x6000)
215 #define SAS_RAS_INTR0 (RAS_BASE)
216 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
217 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
218 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
219
220 /* HW dma structures */
221 /* Delivery queue header */
222 /* dw0 */
223 #define CMD_HDR_ABORT_FLAG_OFF 0
224 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
225 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
226 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
227 #define CMD_HDR_RESP_REPORT_OFF 5
228 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
229 #define CMD_HDR_TLR_CTRL_OFF 6
230 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
231 #define CMD_HDR_PORT_OFF 18
232 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
233 #define CMD_HDR_PRIORITY_OFF 27
234 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
235 #define CMD_HDR_CMD_OFF 29
236 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
237 /* dw1 */
238 #define CMD_HDR_UNCON_CMD_OFF 3
239 #define CMD_HDR_DIR_OFF 5
240 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
241 #define CMD_HDR_RESET_OFF 7
242 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
243 #define CMD_HDR_VDTL_OFF 10
244 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
245 #define CMD_HDR_FRAME_TYPE_OFF 11
246 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
247 #define CMD_HDR_DEV_ID_OFF 16
248 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
249 /* dw2 */
250 #define CMD_HDR_CFL_OFF 0
251 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
252 #define CMD_HDR_NCQ_TAG_OFF 10
253 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
254 #define CMD_HDR_MRFL_OFF 15
255 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
256 #define CMD_HDR_SG_MOD_OFF 24
257 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
258 /* dw3 */
259 #define CMD_HDR_IPTT_OFF 0
260 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
261 /* dw6 */
262 #define CMD_HDR_DIF_SGL_LEN_OFF 0
263 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
264 #define CMD_HDR_DATA_SGL_LEN_OFF 16
265 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
266 /* dw7 */
267 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
268 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
269 #define CMD_HDR_ABORT_IPTT_OFF 16
270 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
271
272 /* Completion header */
273 /* dw0 */
274 #define CMPLT_HDR_CMPLT_OFF 0
275 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
276 #define CMPLT_HDR_ERROR_PHASE_OFF 2
277 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
278 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
279 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
280 #define CMPLT_HDR_ERX_OFF 12
281 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
282 #define CMPLT_HDR_ABORT_STAT_OFF 13
283 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
284 /* abort_stat */
285 #define STAT_IO_NOT_VALID 0x1
286 #define STAT_IO_NO_DEVICE 0x2
287 #define STAT_IO_COMPLETE 0x3
288 #define STAT_IO_ABORTED 0x4
289 /* dw1 */
290 #define CMPLT_HDR_IPTT_OFF 0
291 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
292 #define CMPLT_HDR_DEV_ID_OFF 16
293 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
294 /* dw3 */
295 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
296 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
297
298 /* ITCT header */
299 /* qw0 */
300 #define ITCT_HDR_DEV_TYPE_OFF 0
301 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
302 #define ITCT_HDR_VALID_OFF 2
303 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
304 #define ITCT_HDR_MCR_OFF 5
305 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
306 #define ITCT_HDR_VLN_OFF 9
307 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
308 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
309 #define ITCT_HDR_AWT_CONTINUE_OFF 25
310 #define ITCT_HDR_PORT_ID_OFF 28
311 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
312 /* qw2 */
313 #define ITCT_HDR_INLT_OFF 0
314 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
315 #define ITCT_HDR_RTOLT_OFF 48
316 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
317
318 struct hisi_sas_complete_v3_hdr {
319 __le32 dw0;
320 __le32 dw1;
321 __le32 act;
322 __le32 dw3;
323 };
324
325 struct hisi_sas_err_record_v3 {
326 /* dw0 */
327 __le32 trans_tx_fail_type;
328
329 /* dw1 */
330 __le32 trans_rx_fail_type;
331
332 /* dw2 */
333 __le16 dma_tx_err_type;
334 __le16 sipc_rx_err_type;
335
336 /* dw3 */
337 __le32 dma_rx_err_type;
338 };
339
340 #define RX_DATA_LEN_UNDERFLOW_OFF 6
341 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
342
343 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
344 #define HISI_SAS_MSI_COUNT_V3_HW 32
345
346 #define DIR_NO_DATA 0
347 #define DIR_TO_INI 1
348 #define DIR_TO_DEVICE 2
349 #define DIR_RESERVED 3
350
351 #define CMD_IS_UNCONSTRAINT(cmd) \
352 ((cmd == ATA_CMD_READ_LOG_EXT) || \
353 (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
354 (cmd == ATA_CMD_DEV_RESET))
355
356 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
357 {
358 void __iomem *regs = hisi_hba->regs + off;
359
360 return readl(regs);
361 }
362
363 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
364 {
365 void __iomem *regs = hisi_hba->regs + off;
366
367 return readl_relaxed(regs);
368 }
369
370 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
371 {
372 void __iomem *regs = hisi_hba->regs + off;
373
374 writel(val, regs);
375 }
376
377 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
378 u32 off, u32 val)
379 {
380 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
381
382 writel(val, regs);
383 }
384
385 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
386 int phy_no, u32 off)
387 {
388 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
389
390 return readl(regs);
391 }
392
393 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
394 {
395 int i;
396
397 /* Global registers init */
398 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
399 (u32)((1ULL << hisi_hba->queue_count) - 1));
400 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
401 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
402 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
403 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
404 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
405 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
406 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
407 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
408 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
409 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
410 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
411 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
412 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff);
413 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
414 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
415 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
416 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
417 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
418 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
419 for (i = 0; i < hisi_hba->queue_count; i++)
420 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
421
422 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
423
424 for (i = 0; i < hisi_hba->n_phy; i++) {
425 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
426 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
427 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
428 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
429 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
430 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
431 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff87ffff);
432 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
433 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
434 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
435 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
436 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
437 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
438 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
439 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
440
441 /* used for 12G negotiate */
442 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
443 }
444
445 for (i = 0; i < hisi_hba->queue_count; i++) {
446 /* Delivery queue */
447 hisi_sas_write32(hisi_hba,
448 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
449 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
450
451 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
452 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
453
454 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
455 HISI_SAS_QUEUE_SLOTS);
456
457 /* Completion queue */
458 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
459 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
460
461 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
462 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
463
464 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
465 HISI_SAS_QUEUE_SLOTS);
466 }
467
468 /* itct */
469 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
470 lower_32_bits(hisi_hba->itct_dma));
471
472 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
473 upper_32_bits(hisi_hba->itct_dma));
474
475 /* iost */
476 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
477 lower_32_bits(hisi_hba->iost_dma));
478
479 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
480 upper_32_bits(hisi_hba->iost_dma));
481
482 /* breakpoint */
483 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
484 lower_32_bits(hisi_hba->breakpoint_dma));
485
486 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
487 upper_32_bits(hisi_hba->breakpoint_dma));
488
489 /* SATA broken msg */
490 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
491 lower_32_bits(hisi_hba->sata_breakpoint_dma));
492
493 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
494 upper_32_bits(hisi_hba->sata_breakpoint_dma));
495
496 /* SATA initial fis */
497 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
498 lower_32_bits(hisi_hba->initial_fis_dma));
499
500 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
501 upper_32_bits(hisi_hba->initial_fis_dma));
502
503 /* RAS registers init */
504 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
505 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
506 }
507
508 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
509 {
510 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
511
512 cfg &= ~PHY_CFG_DC_OPT_MSK;
513 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
514 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
515 }
516
517 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
518 {
519 struct sas_identify_frame identify_frame;
520 u32 *identify_buffer;
521
522 memset(&identify_frame, 0, sizeof(identify_frame));
523 identify_frame.dev_type = SAS_END_DEVICE;
524 identify_frame.frame_type = 0;
525 identify_frame._un1 = 1;
526 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
527 identify_frame.target_bits = SAS_PROTOCOL_NONE;
528 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
529 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
530 identify_frame.phy_id = phy_no;
531 identify_buffer = (u32 *)(&identify_frame);
532
533 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
534 __swab32(identify_buffer[0]));
535 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
536 __swab32(identify_buffer[1]));
537 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
538 __swab32(identify_buffer[2]));
539 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
540 __swab32(identify_buffer[3]));
541 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
542 __swab32(identify_buffer[4]));
543 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
544 __swab32(identify_buffer[5]));
545 }
546
547 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
548 struct hisi_sas_device *sas_dev)
549 {
550 struct domain_device *device = sas_dev->sas_device;
551 struct device *dev = hisi_hba->dev;
552 u64 qw0, device_id = sas_dev->device_id;
553 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
554 struct domain_device *parent_dev = device->parent;
555 struct asd_sas_port *sas_port = device->port;
556 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
557
558 memset(itct, 0, sizeof(*itct));
559
560 /* qw0 */
561 qw0 = 0;
562 switch (sas_dev->dev_type) {
563 case SAS_END_DEVICE:
564 case SAS_EDGE_EXPANDER_DEVICE:
565 case SAS_FANOUT_EXPANDER_DEVICE:
566 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
567 break;
568 case SAS_SATA_DEV:
569 case SAS_SATA_PENDING:
570 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
571 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
572 else
573 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
574 break;
575 default:
576 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
577 sas_dev->dev_type);
578 }
579
580 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
581 (device->linkrate << ITCT_HDR_MCR_OFF) |
582 (1 << ITCT_HDR_VLN_OFF) |
583 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
584 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
585 (port->id << ITCT_HDR_PORT_ID_OFF));
586 itct->qw0 = cpu_to_le64(qw0);
587
588 /* qw1 */
589 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
590 itct->sas_addr = __swab64(itct->sas_addr);
591
592 /* qw2 */
593 if (!dev_is_sata(device))
594 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
595 (0x1ULL << ITCT_HDR_RTOLT_OFF));
596 }
597
598 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba,
599 struct hisi_sas_device *sas_dev)
600 {
601 DECLARE_COMPLETION_ONSTACK(completion);
602 u64 dev_id = sas_dev->device_id;
603 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
604 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
605
606 sas_dev->completion = &completion;
607
608 /* clear the itct interrupt state */
609 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
610 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
611 ENT_INT_SRC3_ITC_INT_MSK);
612
613 /* clear the itct table*/
614 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
615 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
616
617 wait_for_completion(sas_dev->completion);
618 memset(itct, 0, sizeof(struct hisi_sas_itct));
619 }
620
621 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
622 struct domain_device *device)
623 {
624 struct hisi_sas_slot *slot, *slot2;
625 struct hisi_sas_device *sas_dev = device->lldd_dev;
626 u32 cfg_abt_set_query_iptt;
627
628 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
629 CFG_ABT_SET_QUERY_IPTT);
630 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
631 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
632 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
633 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
634 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
635 cfg_abt_set_query_iptt);
636 }
637 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
638 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
639 cfg_abt_set_query_iptt);
640 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
641 1 << CFG_ABT_SET_IPTT_DONE_OFF);
642 }
643
644 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
645 {
646 struct device *dev = hisi_hba->dev;
647 int ret;
648 u32 val;
649
650 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
651
652 /* Disable all of the PHYs */
653 hisi_sas_stop_phys(hisi_hba);
654 udelay(50);
655
656 /* Ensure axi bus idle */
657 ret = readl_poll_timeout(hisi_hba->regs + AXI_CFG, val, !val,
658 20000, 1000000);
659 if (ret) {
660 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
661 return -EIO;
662 }
663
664 if (ACPI_HANDLE(dev)) {
665 acpi_status s;
666
667 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
668 if (ACPI_FAILURE(s)) {
669 dev_err(dev, "Reset failed\n");
670 return -EIO;
671 }
672 } else
673 dev_err(dev, "no reset method!\n");
674
675 return 0;
676 }
677
678 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
679 {
680 struct device *dev = hisi_hba->dev;
681 int rc;
682
683 rc = reset_hw_v3_hw(hisi_hba);
684 if (rc) {
685 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
686 return rc;
687 }
688
689 msleep(100);
690 init_reg_v3_hw(hisi_hba);
691
692 return 0;
693 }
694
695 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
696 {
697 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
698
699 cfg |= PHY_CFG_ENA_MSK;
700 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
701 }
702
703 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
704 {
705 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
706
707 cfg &= ~PHY_CFG_ENA_MSK;
708 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
709 }
710
711 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
712 {
713 config_id_frame_v3_hw(hisi_hba, phy_no);
714 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
715 enable_phy_v3_hw(hisi_hba, phy_no);
716 }
717
718 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
719 {
720 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
721 u32 txid_auto;
722
723 disable_phy_v3_hw(hisi_hba, phy_no);
724 if (phy->identify.device_type == SAS_END_DEVICE) {
725 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
726 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
727 txid_auto | TX_HARDRST_MSK);
728 }
729 msleep(100);
730 start_phy_v3_hw(hisi_hba, phy_no);
731 }
732
733 enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
734 {
735 return SAS_LINK_RATE_12_0_GBPS;
736 }
737
738 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
739 {
740 int i;
741
742 for (i = 0; i < hisi_hba->n_phy; i++) {
743 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
744 struct asd_sas_phy *sas_phy = &phy->sas_phy;
745
746 if (!sas_phy->phy->enabled)
747 continue;
748
749 start_phy_v3_hw(hisi_hba, i);
750 }
751 }
752
753 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
754 {
755 u32 sl_control;
756
757 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
758 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
759 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
760 msleep(1);
761 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
762 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
763 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
764 }
765
766 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
767 {
768 int i, bitmap = 0;
769 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
770 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
771
772 for (i = 0; i < hisi_hba->n_phy; i++)
773 if (phy_state & BIT(i))
774 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
775 bitmap |= BIT(i);
776
777 return bitmap;
778 }
779
780 /**
781 * The callpath to this function and upto writing the write
782 * queue pointer should be safe from interruption.
783 */
784 static int
785 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
786 {
787 struct device *dev = hisi_hba->dev;
788 int queue = dq->id;
789 u32 r, w;
790
791 w = dq->wr_point;
792 r = hisi_sas_read32_relaxed(hisi_hba,
793 DLVRY_Q_0_RD_PTR + (queue * 0x14));
794 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
795 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
796 queue, r, w);
797 return -EAGAIN;
798 }
799
800 return 0;
801 }
802
803 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
804 {
805 struct hisi_hba *hisi_hba = dq->hisi_hba;
806 int dlvry_queue = dq->slot_prep->dlvry_queue;
807 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
808
809 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
810 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
811 dq->wr_point);
812 }
813
814 static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
815 struct hisi_sas_slot *slot,
816 struct hisi_sas_cmd_hdr *hdr,
817 struct scatterlist *scatter,
818 int n_elem)
819 {
820 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
821 struct device *dev = hisi_hba->dev;
822 struct scatterlist *sg;
823 int i;
824
825 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
826 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
827 n_elem);
828 return -EINVAL;
829 }
830
831 for_each_sg(scatter, sg, n_elem, i) {
832 struct hisi_sas_sge *entry = &sge_page->sge[i];
833
834 entry->addr = cpu_to_le64(sg_dma_address(sg));
835 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
836 entry->data_len = cpu_to_le32(sg_dma_len(sg));
837 entry->data_off = 0;
838 }
839
840 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
841
842 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
843
844 return 0;
845 }
846
847 static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
848 struct hisi_sas_slot *slot, int is_tmf,
849 struct hisi_sas_tmf_task *tmf)
850 {
851 struct sas_task *task = slot->task;
852 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
853 struct domain_device *device = task->dev;
854 struct hisi_sas_device *sas_dev = device->lldd_dev;
855 struct hisi_sas_port *port = slot->port;
856 struct sas_ssp_task *ssp_task = &task->ssp_task;
857 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
858 int has_data = 0, rc, priority = is_tmf;
859 u8 *buf_cmd;
860 u32 dw1 = 0, dw2 = 0;
861
862 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
863 (2 << CMD_HDR_TLR_CTRL_OFF) |
864 (port->id << CMD_HDR_PORT_OFF) |
865 (priority << CMD_HDR_PRIORITY_OFF) |
866 (1 << CMD_HDR_CMD_OFF)); /* ssp */
867
868 dw1 = 1 << CMD_HDR_VDTL_OFF;
869 if (is_tmf) {
870 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
871 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
872 } else {
873 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
874 switch (scsi_cmnd->sc_data_direction) {
875 case DMA_TO_DEVICE:
876 has_data = 1;
877 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
878 break;
879 case DMA_FROM_DEVICE:
880 has_data = 1;
881 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
882 break;
883 default:
884 dw1 &= ~CMD_HDR_DIR_MSK;
885 }
886 }
887
888 /* map itct entry */
889 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
890 hdr->dw1 = cpu_to_le32(dw1);
891
892 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
893 + 3) / 4) << CMD_HDR_CFL_OFF) |
894 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
895 (2 << CMD_HDR_SG_MOD_OFF);
896 hdr->dw2 = cpu_to_le32(dw2);
897 hdr->transfer_tags = cpu_to_le32(slot->idx);
898
899 if (has_data) {
900 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
901 slot->n_elem);
902 if (rc)
903 return rc;
904 }
905
906 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
907 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
908 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
909
910 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
911 sizeof(struct ssp_frame_hdr);
912
913 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
914 if (!is_tmf) {
915 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
916 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
917 } else {
918 buf_cmd[10] = tmf->tmf;
919 switch (tmf->tmf) {
920 case TMF_ABORT_TASK:
921 case TMF_QUERY_TASK:
922 buf_cmd[12] =
923 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
924 buf_cmd[13] =
925 tmf->tag_of_task_to_be_managed & 0xff;
926 break;
927 default:
928 break;
929 }
930 }
931
932 return 0;
933 }
934
935 static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
936 struct hisi_sas_slot *slot)
937 {
938 struct sas_task *task = slot->task;
939 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
940 struct domain_device *device = task->dev;
941 struct device *dev = hisi_hba->dev;
942 struct hisi_sas_port *port = slot->port;
943 struct scatterlist *sg_req, *sg_resp;
944 struct hisi_sas_device *sas_dev = device->lldd_dev;
945 dma_addr_t req_dma_addr;
946 unsigned int req_len, resp_len;
947 int elem, rc;
948
949 /*
950 * DMA-map SMP request, response buffers
951 */
952 /* req */
953 sg_req = &task->smp_task.smp_req;
954 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
955 if (!elem)
956 return -ENOMEM;
957 req_len = sg_dma_len(sg_req);
958 req_dma_addr = sg_dma_address(sg_req);
959
960 /* resp */
961 sg_resp = &task->smp_task.smp_resp;
962 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
963 if (!elem) {
964 rc = -ENOMEM;
965 goto err_out_req;
966 }
967 resp_len = sg_dma_len(sg_resp);
968 if ((req_len & 0x3) || (resp_len & 0x3)) {
969 rc = -EINVAL;
970 goto err_out_resp;
971 }
972
973 /* create header */
974 /* dw0 */
975 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
976 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
977 (2 << CMD_HDR_CMD_OFF)); /* smp */
978
979 /* map itct entry */
980 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
981 (1 << CMD_HDR_FRAME_TYPE_OFF) |
982 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
983
984 /* dw2 */
985 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
986 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
987 CMD_HDR_MRFL_OFF));
988
989 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
990
991 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
992 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
993
994 return 0;
995
996 err_out_resp:
997 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
998 DMA_FROM_DEVICE);
999 err_out_req:
1000 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1001 DMA_TO_DEVICE);
1002 return rc;
1003 }
1004
1005 static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1006 struct hisi_sas_slot *slot)
1007 {
1008 struct sas_task *task = slot->task;
1009 struct domain_device *device = task->dev;
1010 struct domain_device *parent_dev = device->parent;
1011 struct hisi_sas_device *sas_dev = device->lldd_dev;
1012 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1013 struct asd_sas_port *sas_port = device->port;
1014 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1015 u8 *buf_cmd;
1016 int has_data = 0, rc = 0, hdr_tag = 0;
1017 u32 dw1 = 0, dw2 = 0;
1018
1019 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1020 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1021 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1022 else
1023 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1024
1025 switch (task->data_dir) {
1026 case DMA_TO_DEVICE:
1027 has_data = 1;
1028 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1029 break;
1030 case DMA_FROM_DEVICE:
1031 has_data = 1;
1032 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1033 break;
1034 default:
1035 dw1 &= ~CMD_HDR_DIR_MSK;
1036 }
1037
1038 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1039 (task->ata_task.fis.control & ATA_SRST))
1040 dw1 |= 1 << CMD_HDR_RESET_OFF;
1041
1042 dw1 |= (hisi_sas_get_ata_protocol(
1043 &task->ata_task.fis, task->data_dir))
1044 << CMD_HDR_FRAME_TYPE_OFF;
1045 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1046
1047 if (CMD_IS_UNCONSTRAINT(task->ata_task.fis.command))
1048 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1049
1050 hdr->dw1 = cpu_to_le32(dw1);
1051
1052 /* dw2 */
1053 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
1054 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1055 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1056 }
1057
1058 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1059 2 << CMD_HDR_SG_MOD_OFF;
1060 hdr->dw2 = cpu_to_le32(dw2);
1061
1062 /* dw3 */
1063 hdr->transfer_tags = cpu_to_le32(slot->idx);
1064
1065 if (has_data) {
1066 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1067 slot->n_elem);
1068 if (rc)
1069 return rc;
1070 }
1071
1072 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1073 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1074 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1075
1076 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1077
1078 if (likely(!task->ata_task.device_control_reg_update))
1079 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1080 /* fill in command FIS */
1081 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1082
1083 return 0;
1084 }
1085
1086 static int prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1087 struct hisi_sas_slot *slot,
1088 int device_id, int abort_flag, int tag_to_abort)
1089 {
1090 struct sas_task *task = slot->task;
1091 struct domain_device *dev = task->dev;
1092 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1093 struct hisi_sas_port *port = slot->port;
1094
1095 /* dw0 */
1096 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1097 (port->id << CMD_HDR_PORT_OFF) |
1098 ((dev_is_sata(dev) ? 1:0)
1099 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1100 (abort_flag
1101 << CMD_HDR_ABORT_FLAG_OFF));
1102
1103 /* dw1 */
1104 hdr->dw1 = cpu_to_le32(device_id
1105 << CMD_HDR_DEV_ID_OFF);
1106
1107 /* dw7 */
1108 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1109 hdr->transfer_tags = cpu_to_le32(slot->idx);
1110
1111 return 0;
1112 }
1113
1114 static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1115 {
1116 int i, res = 0;
1117 u32 context, port_id, link_rate;
1118 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1119 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1120 struct device *dev = hisi_hba->dev;
1121
1122 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1123
1124 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1125 port_id = (port_id >> (4 * phy_no)) & 0xf;
1126 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1127 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1128
1129 if (port_id == 0xf) {
1130 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1131 res = IRQ_NONE;
1132 goto end;
1133 }
1134 sas_phy->linkrate = link_rate;
1135 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1136
1137 /* Check for SATA dev */
1138 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1139 if (context & (1 << phy_no)) {
1140 struct hisi_sas_initial_fis *initial_fis;
1141 struct dev_to_host_fis *fis;
1142 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1143
1144 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1145 initial_fis = &hisi_hba->initial_fis[phy_no];
1146 fis = &initial_fis->fis;
1147 sas_phy->oob_mode = SATA_OOB_MODE;
1148 attached_sas_addr[0] = 0x50;
1149 attached_sas_addr[7] = phy_no;
1150 memcpy(sas_phy->attached_sas_addr,
1151 attached_sas_addr,
1152 SAS_ADDR_SIZE);
1153 memcpy(sas_phy->frame_rcvd, fis,
1154 sizeof(struct dev_to_host_fis));
1155 phy->phy_type |= PORT_TYPE_SATA;
1156 phy->identify.device_type = SAS_SATA_DEV;
1157 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1158 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1159 } else {
1160 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1161 struct sas_identify_frame *id =
1162 (struct sas_identify_frame *)frame_rcvd;
1163
1164 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1165 for (i = 0; i < 6; i++) {
1166 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1167 RX_IDAF_DWORD0 + (i * 4));
1168 frame_rcvd[i] = __swab32(idaf);
1169 }
1170 sas_phy->oob_mode = SAS_OOB_MODE;
1171 memcpy(sas_phy->attached_sas_addr,
1172 &id->sas_addr,
1173 SAS_ADDR_SIZE);
1174 phy->phy_type |= PORT_TYPE_SAS;
1175 phy->identify.device_type = id->dev_type;
1176 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1177 if (phy->identify.device_type == SAS_END_DEVICE)
1178 phy->identify.target_port_protocols =
1179 SAS_PROTOCOL_SSP;
1180 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1181 phy->identify.target_port_protocols =
1182 SAS_PROTOCOL_SMP;
1183 }
1184
1185 phy->port_id = port_id;
1186 phy->phy_attached = 1;
1187 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1188
1189 end:
1190 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1191 CHL_INT0_SL_PHY_ENABLE_MSK);
1192 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1193
1194 return res;
1195 }
1196
1197 static int phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1198 {
1199 u32 phy_state, sl_ctrl, txid_auto;
1200 struct device *dev = hisi_hba->dev;
1201
1202 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1203
1204 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1205 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1206 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1207
1208 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1209 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1210 sl_ctrl&(~SL_CTA_MSK));
1211
1212 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1213 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1214 txid_auto | CT3_MSK);
1215
1216 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1217 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1218
1219 return 0;
1220 }
1221
1222 static void phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1223 {
1224 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1225 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1226 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1227
1228 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1229 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1230 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1231 CHL_INT0_SL_RX_BCST_ACK_MSK);
1232 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1233 }
1234
1235 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1236 {
1237 struct hisi_hba *hisi_hba = p;
1238 u32 irq_msk;
1239 int phy_no = 0;
1240 irqreturn_t res = IRQ_NONE;
1241
1242 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1243 & 0x11111111;
1244 while (irq_msk) {
1245 if (irq_msk & 1) {
1246 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1247 CHL_INT0);
1248 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1249 int rdy = phy_state & (1 << phy_no);
1250
1251 if (rdy) {
1252 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1253 /* phy up */
1254 if (phy_up_v3_hw(phy_no, hisi_hba)
1255 == IRQ_HANDLED)
1256 res = IRQ_HANDLED;
1257 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1258 /* phy bcast */
1259 phy_bcast_v3_hw(phy_no, hisi_hba);
1260 } else {
1261 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1262 /* phy down */
1263 if (phy_down_v3_hw(phy_no, hisi_hba)
1264 == IRQ_HANDLED)
1265 res = IRQ_HANDLED;
1266 }
1267 }
1268 irq_msk >>= 4;
1269 phy_no++;
1270 }
1271
1272 return res;
1273 }
1274
1275 static const struct hisi_sas_hw_error port_axi_error[] = {
1276 {
1277 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1278 .msg = "dma_tx_axi_wr_err",
1279 },
1280 {
1281 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1282 .msg = "dma_tx_axi_rd_err",
1283 },
1284 {
1285 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1286 .msg = "dma_rx_axi_wr_err",
1287 },
1288 {
1289 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1290 .msg = "dma_rx_axi_rd_err",
1291 },
1292 };
1293
1294 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1295 {
1296 struct hisi_hba *hisi_hba = p;
1297 struct device *dev = hisi_hba->dev;
1298 u32 ent_msk, ent_tmp, irq_msk;
1299 int phy_no = 0;
1300
1301 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1302 ent_tmp = ent_msk;
1303 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1304 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1305
1306 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1307 & 0xeeeeeeee;
1308
1309 while (irq_msk) {
1310 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1311 CHL_INT0);
1312 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1313 CHL_INT1);
1314 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1315 CHL_INT2);
1316
1317 if ((irq_msk & (4 << (phy_no * 4))) &&
1318 irq_value1) {
1319 int i;
1320
1321 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1322 const struct hisi_sas_hw_error *error =
1323 &port_axi_error[i];
1324
1325 if (!(irq_value1 & error->irq_msk))
1326 continue;
1327
1328 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1329 error->msg, phy_no, irq_value1);
1330 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1331 }
1332
1333 hisi_sas_phy_write32(hisi_hba, phy_no,
1334 CHL_INT1, irq_value1);
1335 }
1336
1337 if (irq_msk & (8 << (phy_no * 4)) && irq_value2) {
1338 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1339
1340 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1341 dev_warn(dev, "phy%d identify timeout\n",
1342 phy_no);
1343 hisi_sas_notify_phy_event(phy,
1344 HISI_PHYE_LINK_RESET);
1345
1346 }
1347
1348 if (irq_value2 & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1349 u32 reg_value = hisi_sas_phy_read32(hisi_hba,
1350 phy_no, STP_LINK_TIMEOUT_STATE);
1351
1352 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1353 phy_no, reg_value);
1354 if (reg_value & BIT(4))
1355 hisi_sas_notify_phy_event(phy,
1356 HISI_PHYE_LINK_RESET);
1357 }
1358
1359 hisi_sas_phy_write32(hisi_hba, phy_no,
1360 CHL_INT2, irq_value2);
1361 }
1362
1363
1364 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1365 hisi_sas_phy_write32(hisi_hba, phy_no,
1366 CHL_INT0, irq_value0
1367 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1368 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1369 & (~CHL_INT0_NOT_RDY_MSK));
1370 }
1371 irq_msk &= ~(0xe << (phy_no * 4));
1372 phy_no++;
1373 }
1374
1375 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1376
1377 return IRQ_HANDLED;
1378 }
1379
1380 static const struct hisi_sas_hw_error axi_error[] = {
1381 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1382 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1383 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1384 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1385 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1386 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1387 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1388 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1389 {},
1390 };
1391
1392 static const struct hisi_sas_hw_error fifo_error[] = {
1393 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
1394 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
1395 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1396 { .msk = BIT(11), .msg = "CMDP_FIFO" },
1397 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1398 {},
1399 };
1400
1401 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1402 {
1403 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1404 .msg = "write pointer and depth",
1405 },
1406 {
1407 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
1408 .msg = "iptt no match slot",
1409 },
1410 {
1411 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
1412 .msg = "read pointer and depth",
1413 },
1414 {
1415 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
1416 .reg = HGC_AXI_FIFO_ERR_INFO,
1417 .sub = axi_error,
1418 },
1419 {
1420 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
1421 .reg = HGC_AXI_FIFO_ERR_INFO,
1422 .sub = fifo_error,
1423 },
1424 {
1425 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
1426 .msg = "LM add/fetch list",
1427 },
1428 {
1429 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
1430 .msg = "SAS_HGC_ABT fetch LM list",
1431 },
1432 };
1433
1434 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
1435 {
1436 u32 irq_value, irq_msk;
1437 struct hisi_hba *hisi_hba = p;
1438 struct device *dev = hisi_hba->dev;
1439 int i;
1440
1441 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1442 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
1443
1444 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
1445
1446 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
1447 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
1448
1449 if (!(irq_value & error->irq_msk))
1450 continue;
1451
1452 if (error->sub) {
1453 const struct hisi_sas_hw_error *sub = error->sub;
1454 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
1455
1456 for (; sub->msk || sub->msg; sub++) {
1457 if (!(err_value & sub->msk))
1458 continue;
1459
1460 dev_err(dev, "%s error (0x%x) found!\n",
1461 sub->msg, irq_value);
1462 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1463 }
1464 } else {
1465 dev_err(dev, "%s error (0x%x) found!\n",
1466 error->msg, irq_value);
1467 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1468 }
1469 }
1470
1471 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
1472 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
1473 u32 dev_id = reg_val & ITCT_DEV_MSK;
1474 struct hisi_sas_device *sas_dev =
1475 &hisi_hba->devices[dev_id];
1476
1477 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
1478 dev_dbg(dev, "clear ITCT ok\n");
1479 complete(sas_dev->completion);
1480 }
1481
1482 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
1483 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
1484
1485 return IRQ_HANDLED;
1486 }
1487
1488 static void
1489 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1490 struct hisi_sas_slot *slot)
1491 {
1492 struct task_status_struct *ts = &task->task_status;
1493 struct hisi_sas_complete_v3_hdr *complete_queue =
1494 hisi_hba->complete_hdr[slot->cmplt_queue];
1495 struct hisi_sas_complete_v3_hdr *complete_hdr =
1496 &complete_queue[slot->cmplt_queue_slot];
1497 struct hisi_sas_err_record_v3 *record =
1498 hisi_sas_status_buf_addr_mem(slot);
1499 u32 dma_rx_err_type = record->dma_rx_err_type;
1500 u32 trans_tx_fail_type = record->trans_tx_fail_type;
1501
1502 switch (task->task_proto) {
1503 case SAS_PROTOCOL_SSP:
1504 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1505 ts->residual = trans_tx_fail_type;
1506 ts->stat = SAS_DATA_UNDERRUN;
1507 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1508 ts->stat = SAS_QUEUE_FULL;
1509 slot->abort = 1;
1510 } else {
1511 ts->stat = SAS_OPEN_REJECT;
1512 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1513 }
1514 break;
1515 case SAS_PROTOCOL_SATA:
1516 case SAS_PROTOCOL_STP:
1517 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1518 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1519 ts->residual = trans_tx_fail_type;
1520 ts->stat = SAS_DATA_UNDERRUN;
1521 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1522 ts->stat = SAS_PHY_DOWN;
1523 slot->abort = 1;
1524 } else {
1525 ts->stat = SAS_OPEN_REJECT;
1526 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1527 }
1528 hisi_sas_sata_done(task, slot);
1529 break;
1530 case SAS_PROTOCOL_SMP:
1531 ts->stat = SAM_STAT_CHECK_CONDITION;
1532 break;
1533 default:
1534 break;
1535 }
1536 }
1537
1538 static int
1539 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1540 {
1541 struct sas_task *task = slot->task;
1542 struct hisi_sas_device *sas_dev;
1543 struct device *dev = hisi_hba->dev;
1544 struct task_status_struct *ts;
1545 struct domain_device *device;
1546 enum exec_status sts;
1547 struct hisi_sas_complete_v3_hdr *complete_queue =
1548 hisi_hba->complete_hdr[slot->cmplt_queue];
1549 struct hisi_sas_complete_v3_hdr *complete_hdr =
1550 &complete_queue[slot->cmplt_queue_slot];
1551 int aborted;
1552 unsigned long flags;
1553
1554 if (unlikely(!task || !task->lldd_task || !task->dev))
1555 return -EINVAL;
1556
1557 ts = &task->task_status;
1558 device = task->dev;
1559 sas_dev = device->lldd_dev;
1560
1561 spin_lock_irqsave(&task->task_state_lock, flags);
1562 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1563 task->task_state_flags &=
1564 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1565 spin_unlock_irqrestore(&task->task_state_lock, flags);
1566
1567 memset(ts, 0, sizeof(*ts));
1568 ts->resp = SAS_TASK_COMPLETE;
1569 if (unlikely(aborted)) {
1570 dev_dbg(dev, "slot complete: task(%p) aborted\n", task);
1571 ts->stat = SAS_ABORTED_TASK;
1572 spin_lock_irqsave(&hisi_hba->lock, flags);
1573 hisi_sas_slot_task_free(hisi_hba, task, slot);
1574 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1575 return -1;
1576 }
1577
1578 if (unlikely(!sas_dev)) {
1579 dev_dbg(dev, "slot complete: port has not device\n");
1580 ts->stat = SAS_PHY_DOWN;
1581 goto out;
1582 }
1583
1584 /*
1585 * Use SAS+TMF status codes
1586 */
1587 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1588 >> CMPLT_HDR_ABORT_STAT_OFF) {
1589 case STAT_IO_ABORTED:
1590 /* this IO has been aborted by abort command */
1591 ts->stat = SAS_ABORTED_TASK;
1592 goto out;
1593 case STAT_IO_COMPLETE:
1594 /* internal abort command complete */
1595 ts->stat = TMF_RESP_FUNC_SUCC;
1596 goto out;
1597 case STAT_IO_NO_DEVICE:
1598 ts->stat = TMF_RESP_FUNC_COMPLETE;
1599 goto out;
1600 case STAT_IO_NOT_VALID:
1601 /*
1602 * abort single IO, the controller can't find the IO
1603 */
1604 ts->stat = TMF_RESP_FUNC_FAILED;
1605 goto out;
1606 default:
1607 break;
1608 }
1609
1610 /* check for erroneous completion */
1611 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1612 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
1613
1614 slot_err_v3_hw(hisi_hba, task, slot);
1615 if (ts->stat != SAS_DATA_UNDERRUN)
1616 dev_info(dev, "erroneous completion iptt=%d task=%p "
1617 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
1618 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
1619 slot->idx, task,
1620 complete_hdr->dw0, complete_hdr->dw1,
1621 complete_hdr->act, complete_hdr->dw3,
1622 error_info[0], error_info[1],
1623 error_info[2], error_info[3]);
1624 if (unlikely(slot->abort))
1625 return ts->stat;
1626 goto out;
1627 }
1628
1629 switch (task->task_proto) {
1630 case SAS_PROTOCOL_SSP: {
1631 struct ssp_response_iu *iu =
1632 hisi_sas_status_buf_addr_mem(slot) +
1633 sizeof(struct hisi_sas_err_record);
1634
1635 sas_ssp_task_response(dev, task, iu);
1636 break;
1637 }
1638 case SAS_PROTOCOL_SMP: {
1639 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1640 void *to;
1641
1642 ts->stat = SAM_STAT_GOOD;
1643 to = kmap_atomic(sg_page(sg_resp));
1644
1645 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1646 DMA_FROM_DEVICE);
1647 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1648 DMA_TO_DEVICE);
1649 memcpy(to + sg_resp->offset,
1650 hisi_sas_status_buf_addr_mem(slot) +
1651 sizeof(struct hisi_sas_err_record),
1652 sg_dma_len(sg_resp));
1653 kunmap_atomic(to);
1654 break;
1655 }
1656 case SAS_PROTOCOL_SATA:
1657 case SAS_PROTOCOL_STP:
1658 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1659 ts->stat = SAM_STAT_GOOD;
1660 hisi_sas_sata_done(task, slot);
1661 break;
1662 default:
1663 ts->stat = SAM_STAT_CHECK_CONDITION;
1664 break;
1665 }
1666
1667 if (!slot->port->port_attached) {
1668 dev_warn(dev, "slot complete: port %d has removed\n",
1669 slot->port->sas_port.id);
1670 ts->stat = SAS_PHY_DOWN;
1671 }
1672
1673 out:
1674 spin_lock_irqsave(&task->task_state_lock, flags);
1675 task->task_state_flags |= SAS_TASK_STATE_DONE;
1676 spin_unlock_irqrestore(&task->task_state_lock, flags);
1677 spin_lock_irqsave(&hisi_hba->lock, flags);
1678 hisi_sas_slot_task_free(hisi_hba, task, slot);
1679 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1680 sts = ts->stat;
1681
1682 if (task->task_done)
1683 task->task_done(task);
1684
1685 return sts;
1686 }
1687
1688 static void cq_tasklet_v3_hw(unsigned long val)
1689 {
1690 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1691 struct hisi_hba *hisi_hba = cq->hisi_hba;
1692 struct hisi_sas_slot *slot;
1693 struct hisi_sas_complete_v3_hdr *complete_queue;
1694 u32 rd_point = cq->rd_point, wr_point;
1695 int queue = cq->id;
1696 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
1697
1698 complete_queue = hisi_hba->complete_hdr[queue];
1699
1700 spin_lock(&dq->lock);
1701 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1702 (0x14 * queue));
1703
1704 while (rd_point != wr_point) {
1705 struct hisi_sas_complete_v3_hdr *complete_hdr;
1706 int iptt;
1707
1708 complete_hdr = &complete_queue[rd_point];
1709
1710 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1711 slot = &hisi_hba->slot_info[iptt];
1712 slot->cmplt_queue_slot = rd_point;
1713 slot->cmplt_queue = queue;
1714 slot_complete_v3_hw(hisi_hba, slot);
1715
1716 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1717 rd_point = 0;
1718 }
1719
1720 /* update rd_point */
1721 cq->rd_point = rd_point;
1722 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1723 spin_unlock(&dq->lock);
1724 }
1725
1726 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1727 {
1728 struct hisi_sas_cq *cq = p;
1729 struct hisi_hba *hisi_hba = cq->hisi_hba;
1730 int queue = cq->id;
1731
1732 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1733
1734 tasklet_schedule(&cq->tasklet);
1735
1736 return IRQ_HANDLED;
1737 }
1738
1739 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1740 {
1741 struct device *dev = hisi_hba->dev;
1742 struct pci_dev *pdev = hisi_hba->pci_dev;
1743 int vectors, rc;
1744 int i, k;
1745 int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1746
1747 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1748 max_msi, PCI_IRQ_MSI);
1749 if (vectors < max_msi) {
1750 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1751 return -ENOENT;
1752 }
1753
1754 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1755 int_phy_up_down_bcast_v3_hw, 0,
1756 DRV_NAME " phy", hisi_hba);
1757 if (rc) {
1758 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1759 rc = -ENOENT;
1760 goto free_irq_vectors;
1761 }
1762
1763 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1764 int_chnl_int_v3_hw, 0,
1765 DRV_NAME " channel", hisi_hba);
1766 if (rc) {
1767 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1768 rc = -ENOENT;
1769 goto free_phy_irq;
1770 }
1771
1772 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
1773 fatal_axi_int_v3_hw, 0,
1774 DRV_NAME " fatal", hisi_hba);
1775 if (rc) {
1776 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
1777 rc = -ENOENT;
1778 goto free_chnl_interrupt;
1779 }
1780
1781 /* Init tasklets for cq only */
1782 for (i = 0; i < hisi_hba->queue_count; i++) {
1783 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1784 struct tasklet_struct *t = &cq->tasklet;
1785
1786 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1787 cq_interrupt_v3_hw, 0,
1788 DRV_NAME " cq", cq);
1789 if (rc) {
1790 dev_err(dev,
1791 "could not request cq%d interrupt, rc=%d\n",
1792 i, rc);
1793 rc = -ENOENT;
1794 goto free_cq_irqs;
1795 }
1796
1797 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1798 }
1799
1800 return 0;
1801
1802 free_cq_irqs:
1803 for (k = 0; k < i; k++) {
1804 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1805
1806 free_irq(pci_irq_vector(pdev, k+16), cq);
1807 }
1808 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
1809 free_chnl_interrupt:
1810 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1811 free_phy_irq:
1812 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1813 free_irq_vectors:
1814 pci_free_irq_vectors(pdev);
1815 return rc;
1816 }
1817
1818 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1819 {
1820 int rc;
1821
1822 rc = hw_init_v3_hw(hisi_hba);
1823 if (rc)
1824 return rc;
1825
1826 rc = interrupt_init_v3_hw(hisi_hba);
1827 if (rc)
1828 return rc;
1829
1830 return 0;
1831 }
1832
1833 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
1834 struct sas_phy_linkrates *r)
1835 {
1836 u32 prog_phy_link_rate =
1837 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1838 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1839 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1840 int i;
1841 enum sas_linkrate min, max;
1842 u32 rate_mask = 0;
1843
1844 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1845 max = sas_phy->phy->maximum_linkrate;
1846 min = r->minimum_linkrate;
1847 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1848 max = r->maximum_linkrate;
1849 min = sas_phy->phy->minimum_linkrate;
1850 } else
1851 return;
1852
1853 sas_phy->phy->maximum_linkrate = max;
1854 sas_phy->phy->minimum_linkrate = min;
1855
1856 max -= SAS_LINK_RATE_1_5_GBPS;
1857
1858 for (i = 0; i <= max; i++)
1859 rate_mask |= 1 << (i * 2);
1860
1861 prog_phy_link_rate &= ~0xff;
1862 prog_phy_link_rate |= rate_mask;
1863
1864 disable_phy_v3_hw(hisi_hba, phy_no);
1865 msleep(100);
1866 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1867 prog_phy_link_rate);
1868 start_phy_v3_hw(hisi_hba, phy_no);
1869 }
1870
1871 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
1872 {
1873 struct pci_dev *pdev = hisi_hba->pci_dev;
1874 int i;
1875
1876 synchronize_irq(pci_irq_vector(pdev, 1));
1877 synchronize_irq(pci_irq_vector(pdev, 2));
1878 synchronize_irq(pci_irq_vector(pdev, 11));
1879 for (i = 0; i < hisi_hba->queue_count; i++) {
1880 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
1881 synchronize_irq(pci_irq_vector(pdev, i + 16));
1882 }
1883
1884 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
1885 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
1886 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
1887 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1888
1889 for (i = 0; i < hisi_hba->n_phy; i++) {
1890 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1891 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
1892 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
1893 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
1894 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
1895 }
1896 }
1897
1898 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
1899 {
1900 return hisi_sas_read32(hisi_hba, PHY_STATE);
1901 }
1902
1903 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1904 {
1905 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1906 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1907 struct sas_phy *sphy = sas_phy->phy;
1908 u32 reg_value;
1909
1910 /* loss dword sync */
1911 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1912 sphy->loss_of_dword_sync_count += reg_value;
1913
1914 /* phy reset problem */
1915 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1916 sphy->phy_reset_problem_count += reg_value;
1917
1918 /* invalid dword */
1919 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1920 sphy->invalid_dword_count += reg_value;
1921
1922 /* disparity err */
1923 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1924 sphy->running_disparity_error_count += reg_value;
1925
1926 }
1927
1928 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
1929 {
1930 struct device *dev = hisi_hba->dev;
1931 int rc;
1932 u32 status;
1933
1934 interrupt_disable_v3_hw(hisi_hba);
1935 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
1936 hisi_sas_kill_tasklets(hisi_hba);
1937
1938 hisi_sas_stop_phys(hisi_hba);
1939
1940 mdelay(10);
1941
1942 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
1943
1944 /* wait until bus idle */
1945 rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
1946 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
1947 if (rc) {
1948 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
1949 return rc;
1950 }
1951
1952 hisi_sas_init_mem(hisi_hba);
1953
1954 return hw_init_v3_hw(hisi_hba);
1955 }
1956
1957 static const struct hisi_sas_hw hisi_sas_v3_hw = {
1958 .hw_init = hisi_sas_v3_init,
1959 .setup_itct = setup_itct_v3_hw,
1960 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
1961 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
1962 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
1963 .clear_itct = clear_itct_v3_hw,
1964 .sl_notify = sl_notify_v3_hw,
1965 .prep_ssp = prep_ssp_v3_hw,
1966 .prep_smp = prep_smp_v3_hw,
1967 .prep_stp = prep_ata_v3_hw,
1968 .prep_abort = prep_abort_v3_hw,
1969 .get_free_slot = get_free_slot_v3_hw,
1970 .start_delivery = start_delivery_v3_hw,
1971 .slot_complete = slot_complete_v3_hw,
1972 .phys_init = phys_init_v3_hw,
1973 .phy_start = start_phy_v3_hw,
1974 .phy_disable = disable_phy_v3_hw,
1975 .phy_hard_reset = phy_hard_reset_v3_hw,
1976 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
1977 .phy_set_linkrate = phy_set_linkrate_v3_hw,
1978 .dereg_device = dereg_device_v3_hw,
1979 .soft_reset = soft_reset_v3_hw,
1980 .get_phys_state = get_phys_state_v3_hw,
1981 .get_events = phy_get_events_v3_hw,
1982 };
1983
1984 static struct Scsi_Host *
1985 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
1986 {
1987 struct Scsi_Host *shost;
1988 struct hisi_hba *hisi_hba;
1989 struct device *dev = &pdev->dev;
1990
1991 shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
1992 if (!shost) {
1993 dev_err(dev, "shost alloc failed\n");
1994 return NULL;
1995 }
1996 hisi_hba = shost_priv(shost);
1997
1998 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
1999 hisi_hba->hw = &hisi_sas_v3_hw;
2000 hisi_hba->pci_dev = pdev;
2001 hisi_hba->dev = dev;
2002 hisi_hba->shost = shost;
2003 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
2004
2005 timer_setup(&hisi_hba->timer, NULL, 0);
2006
2007 if (hisi_sas_get_fw_info(hisi_hba) < 0)
2008 goto err_out;
2009
2010 if (hisi_sas_alloc(hisi_hba, shost)) {
2011 hisi_sas_free(hisi_hba);
2012 goto err_out;
2013 }
2014
2015 return shost;
2016 err_out:
2017 scsi_host_put(shost);
2018 dev_err(dev, "shost alloc failed\n");
2019 return NULL;
2020 }
2021
2022 static int
2023 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2024 {
2025 struct Scsi_Host *shost;
2026 struct hisi_hba *hisi_hba;
2027 struct device *dev = &pdev->dev;
2028 struct asd_sas_phy **arr_phy;
2029 struct asd_sas_port **arr_port;
2030 struct sas_ha_struct *sha;
2031 int rc, phy_nr, port_nr, i;
2032
2033 rc = pci_enable_device(pdev);
2034 if (rc)
2035 goto err_out;
2036
2037 pci_set_master(pdev);
2038
2039 rc = pci_request_regions(pdev, DRV_NAME);
2040 if (rc)
2041 goto err_out_disable_device;
2042
2043 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
2044 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
2045 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2046 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2047 dev_err(dev, "No usable DMA addressing method\n");
2048 rc = -EIO;
2049 goto err_out_regions;
2050 }
2051 }
2052
2053 shost = hisi_sas_shost_alloc_pci(pdev);
2054 if (!shost) {
2055 rc = -ENOMEM;
2056 goto err_out_regions;
2057 }
2058
2059 sha = SHOST_TO_SAS_HA(shost);
2060 hisi_hba = shost_priv(shost);
2061 dev_set_drvdata(dev, sha);
2062
2063 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
2064 if (!hisi_hba->regs) {
2065 dev_err(dev, "cannot map register.\n");
2066 rc = -ENOMEM;
2067 goto err_out_ha;
2068 }
2069
2070 phy_nr = port_nr = hisi_hba->n_phy;
2071
2072 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
2073 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
2074 if (!arr_phy || !arr_port) {
2075 rc = -ENOMEM;
2076 goto err_out_ha;
2077 }
2078
2079 sha->sas_phy = arr_phy;
2080 sha->sas_port = arr_port;
2081 sha->core.shost = shost;
2082 sha->lldd_ha = hisi_hba;
2083
2084 shost->transportt = hisi_sas_stt;
2085 shost->max_id = HISI_SAS_MAX_DEVICES;
2086 shost->max_lun = ~0;
2087 shost->max_channel = 1;
2088 shost->max_cmd_len = 16;
2089 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
2090 shost->can_queue = hisi_hba->hw->max_command_entries;
2091 shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
2092
2093 sha->sas_ha_name = DRV_NAME;
2094 sha->dev = dev;
2095 sha->lldd_module = THIS_MODULE;
2096 sha->sas_addr = &hisi_hba->sas_addr[0];
2097 sha->num_phys = hisi_hba->n_phy;
2098 sha->core.shost = hisi_hba->shost;
2099
2100 for (i = 0; i < hisi_hba->n_phy; i++) {
2101 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
2102 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
2103 }
2104
2105 hisi_sas_init_add(hisi_hba);
2106
2107 rc = scsi_add_host(shost, dev);
2108 if (rc)
2109 goto err_out_ha;
2110
2111 rc = sas_register_ha(sha);
2112 if (rc)
2113 goto err_out_register_ha;
2114
2115 rc = hisi_hba->hw->hw_init(hisi_hba);
2116 if (rc)
2117 goto err_out_register_ha;
2118
2119 scsi_scan_host(shost);
2120
2121 return 0;
2122
2123 err_out_register_ha:
2124 scsi_remove_host(shost);
2125 err_out_ha:
2126 scsi_host_put(shost);
2127 err_out_regions:
2128 pci_release_regions(pdev);
2129 err_out_disable_device:
2130 pci_disable_device(pdev);
2131 err_out:
2132 return rc;
2133 }
2134
2135 static void
2136 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
2137 {
2138 int i;
2139
2140 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2141 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2142 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2143 for (i = 0; i < hisi_hba->queue_count; i++) {
2144 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2145
2146 free_irq(pci_irq_vector(pdev, i+16), cq);
2147 }
2148 pci_free_irq_vectors(pdev);
2149 }
2150
2151 static void hisi_sas_v3_remove(struct pci_dev *pdev)
2152 {
2153 struct device *dev = &pdev->dev;
2154 struct sas_ha_struct *sha = dev_get_drvdata(dev);
2155 struct hisi_hba *hisi_hba = sha->lldd_ha;
2156 struct Scsi_Host *shost = sha->core.shost;
2157
2158 sas_unregister_ha(sha);
2159 sas_remove_host(sha->core.shost);
2160
2161 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
2162 hisi_sas_kill_tasklets(hisi_hba);
2163 pci_release_regions(pdev);
2164 pci_disable_device(pdev);
2165 hisi_sas_free(hisi_hba);
2166 scsi_host_put(shost);
2167 }
2168
2169 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = {
2170 { .irq_msk = BIT(19), .msg = "HILINK_INT" },
2171 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" },
2172 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" },
2173 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" },
2174 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" },
2175 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" },
2176 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" },
2177 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" },
2178 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" },
2179 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" },
2180 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" },
2181 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" },
2182 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" },
2183 };
2184
2185 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = {
2186 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" },
2187 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" },
2188 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" },
2189 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" },
2190 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" },
2191 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" },
2192 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" },
2193 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" },
2194 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" },
2195 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" },
2196 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" },
2197 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" },
2198 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" },
2199 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" },
2200 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" },
2201 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" },
2202 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" },
2203 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" },
2204 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" },
2205 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" },
2206 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" },
2207 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" },
2208 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" },
2209 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" },
2210 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" },
2211 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" },
2212 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" },
2213 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" },
2214 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" },
2215 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" },
2216 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" },
2217 };
2218
2219 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba)
2220 {
2221 struct device *dev = hisi_hba->dev;
2222 const struct hisi_sas_hw_error *ras_error;
2223 bool need_reset = false;
2224 u32 irq_value;
2225 int i;
2226
2227 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0);
2228 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) {
2229 ras_error = &sas_ras_intr0_nfe[i];
2230 if (ras_error->irq_msk & irq_value) {
2231 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n",
2232 ras_error->msg, irq_value);
2233 need_reset = true;
2234 }
2235 }
2236 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value);
2237
2238 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1);
2239 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) {
2240 ras_error = &sas_ras_intr1_nfe[i];
2241 if (ras_error->irq_msk & irq_value) {
2242 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n",
2243 ras_error->msg, irq_value);
2244 need_reset = true;
2245 }
2246 }
2247 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value);
2248
2249 return need_reset;
2250 }
2251
2252 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev,
2253 pci_channel_state_t state)
2254 {
2255 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2256 struct hisi_hba *hisi_hba = sha->lldd_ha;
2257 struct device *dev = hisi_hba->dev;
2258
2259 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state);
2260 if (state == pci_channel_io_perm_failure)
2261 return PCI_ERS_RESULT_DISCONNECT;
2262
2263 if (process_non_fatal_error_v3_hw(hisi_hba))
2264 return PCI_ERS_RESULT_NEED_RESET;
2265
2266 return PCI_ERS_RESULT_CAN_RECOVER;
2267 }
2268
2269 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev)
2270 {
2271 return PCI_ERS_RESULT_RECOVERED;
2272 }
2273
2274 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev)
2275 {
2276 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2277 struct hisi_hba *hisi_hba = sha->lldd_ha;
2278 struct device *dev = hisi_hba->dev;
2279 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r);
2280
2281 dev_info(dev, "PCI error: slot reset callback!!\n");
2282 queue_work(hisi_hba->wq, &r.work);
2283 wait_for_completion(r.completion);
2284 if (r.done)
2285 return PCI_ERS_RESULT_RECOVERED;
2286
2287 return PCI_ERS_RESULT_DISCONNECT;
2288 }
2289
2290 enum {
2291 /* instances of the controller */
2292 hip08,
2293 };
2294
2295 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state)
2296 {
2297 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2298 struct hisi_hba *hisi_hba = sha->lldd_ha;
2299 struct device *dev = hisi_hba->dev;
2300 struct Scsi_Host *shost = hisi_hba->shost;
2301 u32 device_state, status;
2302 int rc;
2303 u32 reg_val;
2304 unsigned long flags;
2305
2306 if (!pdev->pm_cap) {
2307 dev_err(dev, "PCI PM not supported\n");
2308 return -ENODEV;
2309 }
2310
2311 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2312 scsi_block_requests(shost);
2313 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2314 flush_workqueue(hisi_hba->wq);
2315 /* disable DQ/PHY/bus */
2316 interrupt_disable_v3_hw(hisi_hba);
2317 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2318 hisi_sas_kill_tasklets(hisi_hba);
2319
2320 hisi_sas_stop_phys(hisi_hba);
2321
2322 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2323 AM_CTRL_GLOBAL);
2324 reg_val |= 0x1;
2325 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2326 AM_CTRL_GLOBAL, reg_val);
2327
2328 /* wait until bus idle */
2329 rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
2330 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
2331 if (rc) {
2332 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
2333 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2334 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2335 scsi_unblock_requests(shost);
2336 return rc;
2337 }
2338
2339 hisi_sas_init_mem(hisi_hba);
2340
2341 device_state = pci_choose_state(pdev, state);
2342 dev_warn(dev, "entering operating state [D%d]\n",
2343 device_state);
2344 pci_save_state(pdev);
2345 pci_disable_device(pdev);
2346 pci_set_power_state(pdev, device_state);
2347
2348 spin_lock_irqsave(&hisi_hba->lock, flags);
2349 hisi_sas_release_tasks(hisi_hba);
2350 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2351
2352 sas_suspend_ha(sha);
2353 return 0;
2354 }
2355
2356 static int hisi_sas_v3_resume(struct pci_dev *pdev)
2357 {
2358 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2359 struct hisi_hba *hisi_hba = sha->lldd_ha;
2360 struct Scsi_Host *shost = hisi_hba->shost;
2361 struct device *dev = hisi_hba->dev;
2362 unsigned int rc;
2363 u32 device_state = pdev->current_state;
2364
2365 dev_warn(dev, "resuming from operating state [D%d]\n",
2366 device_state);
2367 pci_set_power_state(pdev, PCI_D0);
2368 pci_enable_wake(pdev, PCI_D0, 0);
2369 pci_restore_state(pdev);
2370 rc = pci_enable_device(pdev);
2371 if (rc)
2372 dev_err(dev, "enable device failed during resume (%d)\n", rc);
2373
2374 pci_set_master(pdev);
2375 scsi_unblock_requests(shost);
2376 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2377
2378 sas_prep_resume_ha(sha);
2379 init_reg_v3_hw(hisi_hba);
2380 hisi_hba->hw->phys_init(hisi_hba);
2381 sas_resume_ha(sha);
2382 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2383
2384 return 0;
2385 }
2386
2387 static const struct pci_device_id sas_v3_pci_table[] = {
2388 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
2389 {}
2390 };
2391 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
2392
2393 static const struct pci_error_handlers hisi_sas_err_handler = {
2394 .error_detected = hisi_sas_error_detected_v3_hw,
2395 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw,
2396 .slot_reset = hisi_sas_slot_reset_v3_hw,
2397 };
2398
2399 static struct pci_driver sas_v3_pci_driver = {
2400 .name = DRV_NAME,
2401 .id_table = sas_v3_pci_table,
2402 .probe = hisi_sas_v3_probe,
2403 .remove = hisi_sas_v3_remove,
2404 .suspend = hisi_sas_v3_suspend,
2405 .resume = hisi_sas_v3_resume,
2406 .err_handler = &hisi_sas_err_handler,
2407 };
2408
2409 module_pci_driver(sas_v3_pci_driver);
2410
2411 MODULE_LICENSE("GPL");
2412 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2413 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2414 MODULE_ALIAS("pci:" DRV_NAME);
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