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scsi: hisi_sas: add readl poll timeout helper wrappers
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v3_hw.c
1 /*
2 * Copyright (c) 2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 #include "hisi_sas.h"
12 #define DRV_NAME "hisi_sas_v3_hw"
13
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
26 #define ITCT_CLR 0x44
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CFG_1US_TIMER_TRSH 0xcc
55 #define CHNL_INT_STATUS 0x148
56 #define HGC_AXI_FIFO_ERR_INFO 0x154
57 #define AXI_ERR_INFO_OFF 0
58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
59 #define FIFO_ERR_INFO_OFF 8
60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
61 #define INT_COAL_EN 0x19c
62 #define OQ_INT_COAL_TIME 0x1a0
63 #define OQ_INT_COAL_CNT 0x1a4
64 #define ENT_INT_COAL_TIME 0x1a8
65 #define ENT_INT_COAL_CNT 0x1ac
66 #define OQ_INT_SRC 0x1b0
67 #define OQ_INT_SRC_MSK 0x1b4
68 #define ENT_INT_SRC1 0x1b8
69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
73 #define ENT_INT_SRC2 0x1bc
74 #define ENT_INT_SRC3 0x1c0
75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
78 #define ENT_INT_SRC3_AXI_OFF 11
79 #define ENT_INT_SRC3_FIFO_OFF 12
80 #define ENT_INT_SRC3_LM_OFF 14
81 #define ENT_INT_SRC3_ITC_INT_OFF 15
82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
83 #define ENT_INT_SRC3_ABT_OFF 16
84 #define ENT_INT_SRC_MSK1 0x1c4
85 #define ENT_INT_SRC_MSK2 0x1c8
86 #define ENT_INT_SRC_MSK3 0x1cc
87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
89 #define CHNL_ENT_INT_MSK 0x1d4
90 #define HGC_COM_INT_MSK 0x1d8
91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
92 #define SAS_ECC_INTR 0x1e8
93 #define SAS_ECC_INTR_MSK 0x1ec
94 #define HGC_ERR_STAT_EN 0x238
95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
97 #define DLVRY_Q_0_DEPTH 0x268
98 #define DLVRY_Q_0_WR_PTR 0x26c
99 #define DLVRY_Q_0_RD_PTR 0x270
100 #define HYPER_STREAM_ID_EN_CFG 0xc80
101 #define OQ0_INT_SRC_MSK 0xc90
102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
104 #define COMPL_Q_0_DEPTH 0x4e8
105 #define COMPL_Q_0_WR_PTR 0x4ec
106 #define COMPL_Q_0_RD_PTR 0x4f0
107 #define AWQOS_AWCACHE_CFG 0xc84
108 #define ARQOS_ARCACHE_CFG 0xc88
109
110 /* phy registers requiring init */
111 #define PORT_BASE (0x2000)
112 #define PHY_CFG (PORT_BASE + 0x0)
113 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
114 #define PHY_CFG_ENA_OFF 0
115 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
116 #define PHY_CFG_DC_OPT_OFF 2
117 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
118 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
119 #define PHY_CTRL (PORT_BASE + 0x14)
120 #define PHY_CTRL_RESET_OFF 0
121 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
122 #define SL_CFG (PORT_BASE + 0x84)
123 #define SL_CONTROL (PORT_BASE + 0x94)
124 #define SL_CONTROL_NOTIFY_EN_OFF 0
125 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
126 #define SL_CTA_OFF 17
127 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
128 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
129 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
130 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
131 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
132 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
133 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
134 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
135 #define TXID_AUTO (PORT_BASE + 0xb8)
136 #define CT3_OFF 1
137 #define CT3_MSK (0x1 << CT3_OFF)
138 #define TX_HARDRST_OFF 2
139 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
140 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
141 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
142 #define STP_LINK_TIMER (PORT_BASE + 0x120)
143 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
144 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
145 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
146 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
147 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
148 #define CHL_INT0 (PORT_BASE + 0x1b4)
149 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
150 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
151 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
152 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
153 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
154 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
155 #define CHL_INT0_NOT_RDY_OFF 4
156 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
157 #define CHL_INT0_PHY_RDY_OFF 5
158 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
159 #define CHL_INT1 (PORT_BASE + 0x1b8)
160 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
161 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
162 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
163 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
164 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
165 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
166 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
167 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
168 #define CHL_INT2 (PORT_BASE + 0x1bc)
169 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
170 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
171 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
172 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
173 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
174 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
175 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
176 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
177 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
178 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
179 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
180 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
181 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
182 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
183 #define DMA_TX_STATUS_BUSY_OFF 0
184 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
185 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
186 #define DMA_RX_STATUS_BUSY_OFF 0
187 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
188
189 #define COARSETUNE_TIME (PORT_BASE + 0x304)
190 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
191 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
192 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
193 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
194
195 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
196 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
197 #error Max ITCT exceeded
198 #endif
199
200 #define AXI_MASTER_CFG_BASE (0x5000)
201 #define AM_CTRL_GLOBAL (0x0)
202 #define AM_CURR_TRANS_RETURN (0x150)
203
204 #define AM_CFG_MAX_TRANS (0x5010)
205 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
206 #define AXI_CFG (0x5100)
207 #define AM_ROB_ECC_ERR_ADDR (0x510c)
208 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
209 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
210 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
211 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
212
213 /* RAS registers need init */
214 #define RAS_BASE (0x6000)
215 #define SAS_RAS_INTR0 (RAS_BASE)
216 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
217 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
218 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
219 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c)
220 #define SAS_RAS_INTR2 (RAS_BASE + 0x20)
221 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24)
222
223 /* HW dma structures */
224 /* Delivery queue header */
225 /* dw0 */
226 #define CMD_HDR_ABORT_FLAG_OFF 0
227 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
228 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
229 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
230 #define CMD_HDR_RESP_REPORT_OFF 5
231 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
232 #define CMD_HDR_TLR_CTRL_OFF 6
233 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
234 #define CMD_HDR_PORT_OFF 18
235 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
236 #define CMD_HDR_PRIORITY_OFF 27
237 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
238 #define CMD_HDR_CMD_OFF 29
239 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
240 /* dw1 */
241 #define CMD_HDR_UNCON_CMD_OFF 3
242 #define CMD_HDR_DIR_OFF 5
243 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
244 #define CMD_HDR_RESET_OFF 7
245 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
246 #define CMD_HDR_VDTL_OFF 10
247 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
248 #define CMD_HDR_FRAME_TYPE_OFF 11
249 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
250 #define CMD_HDR_DEV_ID_OFF 16
251 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
252 /* dw2 */
253 #define CMD_HDR_CFL_OFF 0
254 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
255 #define CMD_HDR_NCQ_TAG_OFF 10
256 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
257 #define CMD_HDR_MRFL_OFF 15
258 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
259 #define CMD_HDR_SG_MOD_OFF 24
260 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
261 /* dw3 */
262 #define CMD_HDR_IPTT_OFF 0
263 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
264 /* dw6 */
265 #define CMD_HDR_DIF_SGL_LEN_OFF 0
266 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
267 #define CMD_HDR_DATA_SGL_LEN_OFF 16
268 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
269 /* dw7 */
270 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
271 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
272 #define CMD_HDR_ABORT_IPTT_OFF 16
273 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
274
275 /* Completion header */
276 /* dw0 */
277 #define CMPLT_HDR_CMPLT_OFF 0
278 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
279 #define CMPLT_HDR_ERROR_PHASE_OFF 2
280 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
281 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
282 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
283 #define CMPLT_HDR_ERX_OFF 12
284 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
285 #define CMPLT_HDR_ABORT_STAT_OFF 13
286 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
287 /* abort_stat */
288 #define STAT_IO_NOT_VALID 0x1
289 #define STAT_IO_NO_DEVICE 0x2
290 #define STAT_IO_COMPLETE 0x3
291 #define STAT_IO_ABORTED 0x4
292 /* dw1 */
293 #define CMPLT_HDR_IPTT_OFF 0
294 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
295 #define CMPLT_HDR_DEV_ID_OFF 16
296 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
297 /* dw3 */
298 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
299 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
300
301 /* ITCT header */
302 /* qw0 */
303 #define ITCT_HDR_DEV_TYPE_OFF 0
304 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
305 #define ITCT_HDR_VALID_OFF 2
306 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
307 #define ITCT_HDR_MCR_OFF 5
308 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
309 #define ITCT_HDR_VLN_OFF 9
310 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
311 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
312 #define ITCT_HDR_AWT_CONTINUE_OFF 25
313 #define ITCT_HDR_PORT_ID_OFF 28
314 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
315 /* qw2 */
316 #define ITCT_HDR_INLT_OFF 0
317 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
318 #define ITCT_HDR_RTOLT_OFF 48
319 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
320
321 struct hisi_sas_complete_v3_hdr {
322 __le32 dw0;
323 __le32 dw1;
324 __le32 act;
325 __le32 dw3;
326 };
327
328 struct hisi_sas_err_record_v3 {
329 /* dw0 */
330 __le32 trans_tx_fail_type;
331
332 /* dw1 */
333 __le32 trans_rx_fail_type;
334
335 /* dw2 */
336 __le16 dma_tx_err_type;
337 __le16 sipc_rx_err_type;
338
339 /* dw3 */
340 __le32 dma_rx_err_type;
341 };
342
343 #define RX_DATA_LEN_UNDERFLOW_OFF 6
344 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
345
346 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
347 #define HISI_SAS_MSI_COUNT_V3_HW 32
348
349 #define DIR_NO_DATA 0
350 #define DIR_TO_INI 1
351 #define DIR_TO_DEVICE 2
352 #define DIR_RESERVED 3
353
354 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
355 ((fis.command == ATA_CMD_READ_LOG_EXT) || \
356 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
357 ((fis.command == ATA_CMD_DEV_RESET) && \
358 ((fis.control & ATA_SRST) != 0)))
359
360 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
361 {
362 void __iomem *regs = hisi_hba->regs + off;
363
364 return readl(regs);
365 }
366
367 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
368 {
369 void __iomem *regs = hisi_hba->regs + off;
370
371 return readl_relaxed(regs);
372 }
373
374 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
375 {
376 void __iomem *regs = hisi_hba->regs + off;
377
378 writel(val, regs);
379 }
380
381 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
382 u32 off, u32 val)
383 {
384 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
385
386 writel(val, regs);
387 }
388
389 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
390 int phy_no, u32 off)
391 {
392 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
393
394 return readl(regs);
395 }
396
397 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \
398 timeout_us) \
399 ({ \
400 void __iomem *regs = hisi_hba->regs + off; \
401 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \
402 })
403
404 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \
405 timeout_us) \
406 ({ \
407 void __iomem *regs = hisi_hba->regs + off; \
408 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
409 })
410
411 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
412 {
413 struct pci_dev *pdev = hisi_hba->pci_dev;
414 int i;
415
416 /* Global registers init */
417 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
418 (u32)((1ULL << hisi_hba->queue_count) - 1));
419 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
420 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
421 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
422 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
423 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
424 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
425 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
426 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
427 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
428 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
429 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
430 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
431 if (pdev->revision >= 0x21)
432 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7fff);
433 else
434 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff);
435 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
436 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
437 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
438 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
439 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
440 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
441 for (i = 0; i < hisi_hba->queue_count; i++)
442 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
443
444 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
445
446 for (i = 0; i < hisi_hba->n_phy; i++) {
447 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
448 struct asd_sas_phy *sas_phy = &phy->sas_phy;
449 u32 prog_phy_link_rate = 0x800;
450
451 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
452 SAS_LINK_RATE_1_5_GBPS)) {
453 prog_phy_link_rate = 0x855;
454 } else {
455 enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
456
457 prog_phy_link_rate =
458 hisi_sas_get_prog_phy_linkrate_mask(max) |
459 0x800;
460 }
461 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
462 prog_phy_link_rate);
463 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
464 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
465 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
466 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
467 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
468 if (pdev->revision >= 0x21)
469 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
470 0xffffffff);
471 else
472 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
473 0xff87ffff);
474 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
475 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
476 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
477 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
478 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
479 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
480 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
481 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
482
483 /* used for 12G negotiate */
484 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
485 }
486
487 for (i = 0; i < hisi_hba->queue_count; i++) {
488 /* Delivery queue */
489 hisi_sas_write32(hisi_hba,
490 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
491 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
492
493 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
494 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
495
496 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
497 HISI_SAS_QUEUE_SLOTS);
498
499 /* Completion queue */
500 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
501 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
502
503 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
504 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
505
506 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
507 HISI_SAS_QUEUE_SLOTS);
508 }
509
510 /* itct */
511 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
512 lower_32_bits(hisi_hba->itct_dma));
513
514 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
515 upper_32_bits(hisi_hba->itct_dma));
516
517 /* iost */
518 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
519 lower_32_bits(hisi_hba->iost_dma));
520
521 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
522 upper_32_bits(hisi_hba->iost_dma));
523
524 /* breakpoint */
525 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
526 lower_32_bits(hisi_hba->breakpoint_dma));
527
528 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
529 upper_32_bits(hisi_hba->breakpoint_dma));
530
531 /* SATA broken msg */
532 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
533 lower_32_bits(hisi_hba->sata_breakpoint_dma));
534
535 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
536 upper_32_bits(hisi_hba->sata_breakpoint_dma));
537
538 /* SATA initial fis */
539 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
540 lower_32_bits(hisi_hba->initial_fis_dma));
541
542 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
543 upper_32_bits(hisi_hba->initial_fis_dma));
544
545 /* RAS registers init */
546 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
547 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
548 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
549 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
550 }
551
552 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
553 {
554 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
555
556 cfg &= ~PHY_CFG_DC_OPT_MSK;
557 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
558 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
559 }
560
561 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
562 {
563 struct sas_identify_frame identify_frame;
564 u32 *identify_buffer;
565
566 memset(&identify_frame, 0, sizeof(identify_frame));
567 identify_frame.dev_type = SAS_END_DEVICE;
568 identify_frame.frame_type = 0;
569 identify_frame._un1 = 1;
570 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
571 identify_frame.target_bits = SAS_PROTOCOL_NONE;
572 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
573 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
574 identify_frame.phy_id = phy_no;
575 identify_buffer = (u32 *)(&identify_frame);
576
577 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
578 __swab32(identify_buffer[0]));
579 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
580 __swab32(identify_buffer[1]));
581 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
582 __swab32(identify_buffer[2]));
583 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
584 __swab32(identify_buffer[3]));
585 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
586 __swab32(identify_buffer[4]));
587 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
588 __swab32(identify_buffer[5]));
589 }
590
591 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
592 struct hisi_sas_device *sas_dev)
593 {
594 struct domain_device *device = sas_dev->sas_device;
595 struct device *dev = hisi_hba->dev;
596 u64 qw0, device_id = sas_dev->device_id;
597 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
598 struct domain_device *parent_dev = device->parent;
599 struct asd_sas_port *sas_port = device->port;
600 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
601
602 memset(itct, 0, sizeof(*itct));
603
604 /* qw0 */
605 qw0 = 0;
606 switch (sas_dev->dev_type) {
607 case SAS_END_DEVICE:
608 case SAS_EDGE_EXPANDER_DEVICE:
609 case SAS_FANOUT_EXPANDER_DEVICE:
610 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
611 break;
612 case SAS_SATA_DEV:
613 case SAS_SATA_PENDING:
614 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
615 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
616 else
617 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
618 break;
619 default:
620 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
621 sas_dev->dev_type);
622 }
623
624 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
625 (device->linkrate << ITCT_HDR_MCR_OFF) |
626 (1 << ITCT_HDR_VLN_OFF) |
627 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
628 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
629 (port->id << ITCT_HDR_PORT_ID_OFF));
630 itct->qw0 = cpu_to_le64(qw0);
631
632 /* qw1 */
633 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
634 itct->sas_addr = __swab64(itct->sas_addr);
635
636 /* qw2 */
637 if (!dev_is_sata(device))
638 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
639 (0x1ULL << ITCT_HDR_RTOLT_OFF));
640 }
641
642 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba,
643 struct hisi_sas_device *sas_dev)
644 {
645 DECLARE_COMPLETION_ONSTACK(completion);
646 u64 dev_id = sas_dev->device_id;
647 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
648 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
649
650 sas_dev->completion = &completion;
651
652 /* clear the itct interrupt state */
653 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
654 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
655 ENT_INT_SRC3_ITC_INT_MSK);
656
657 /* clear the itct table*/
658 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
659 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
660
661 wait_for_completion(sas_dev->completion);
662 memset(itct, 0, sizeof(struct hisi_sas_itct));
663 }
664
665 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
666 struct domain_device *device)
667 {
668 struct hisi_sas_slot *slot, *slot2;
669 struct hisi_sas_device *sas_dev = device->lldd_dev;
670 u32 cfg_abt_set_query_iptt;
671
672 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
673 CFG_ABT_SET_QUERY_IPTT);
674 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
675 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
676 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
677 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
678 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
679 cfg_abt_set_query_iptt);
680 }
681 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
682 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
683 cfg_abt_set_query_iptt);
684 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
685 1 << CFG_ABT_SET_IPTT_DONE_OFF);
686 }
687
688 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
689 {
690 struct device *dev = hisi_hba->dev;
691 int ret;
692 u32 val;
693
694 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
695
696 /* Disable all of the PHYs */
697 hisi_sas_stop_phys(hisi_hba);
698 udelay(50);
699
700 /* Ensure axi bus idle */
701 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
702 20000, 1000000);
703 if (ret) {
704 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
705 return -EIO;
706 }
707
708 if (ACPI_HANDLE(dev)) {
709 acpi_status s;
710
711 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
712 if (ACPI_FAILURE(s)) {
713 dev_err(dev, "Reset failed\n");
714 return -EIO;
715 }
716 } else {
717 dev_err(dev, "no reset method!\n");
718 return -EINVAL;
719 }
720
721 return 0;
722 }
723
724 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
725 {
726 struct device *dev = hisi_hba->dev;
727 int rc;
728
729 rc = reset_hw_v3_hw(hisi_hba);
730 if (rc) {
731 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
732 return rc;
733 }
734
735 msleep(100);
736 init_reg_v3_hw(hisi_hba);
737
738 return 0;
739 }
740
741 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
742 {
743 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
744
745 cfg |= PHY_CFG_ENA_MSK;
746 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
747 }
748
749 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
750 {
751 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
752
753 cfg &= ~PHY_CFG_ENA_MSK;
754 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
755 }
756
757 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
758 {
759 config_id_frame_v3_hw(hisi_hba, phy_no);
760 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
761 enable_phy_v3_hw(hisi_hba, phy_no);
762 }
763
764 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
765 {
766 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
767 u32 txid_auto;
768
769 disable_phy_v3_hw(hisi_hba, phy_no);
770 if (phy->identify.device_type == SAS_END_DEVICE) {
771 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
772 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
773 txid_auto | TX_HARDRST_MSK);
774 }
775 msleep(100);
776 start_phy_v3_hw(hisi_hba, phy_no);
777 }
778
779 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
780 {
781 return SAS_LINK_RATE_12_0_GBPS;
782 }
783
784 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
785 {
786 int i;
787
788 for (i = 0; i < hisi_hba->n_phy; i++) {
789 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
790 struct asd_sas_phy *sas_phy = &phy->sas_phy;
791
792 if (!sas_phy->phy->enabled)
793 continue;
794
795 start_phy_v3_hw(hisi_hba, i);
796 }
797 }
798
799 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
800 {
801 u32 sl_control;
802
803 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
804 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
805 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
806 msleep(1);
807 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
808 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
809 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
810 }
811
812 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
813 {
814 int i, bitmap = 0;
815 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
816 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
817
818 for (i = 0; i < hisi_hba->n_phy; i++)
819 if (phy_state & BIT(i))
820 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
821 bitmap |= BIT(i);
822
823 return bitmap;
824 }
825
826 /**
827 * The callpath to this function and upto writing the write
828 * queue pointer should be safe from interruption.
829 */
830 static int
831 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
832 {
833 struct device *dev = hisi_hba->dev;
834 int queue = dq->id;
835 u32 r, w;
836
837 w = dq->wr_point;
838 r = hisi_sas_read32_relaxed(hisi_hba,
839 DLVRY_Q_0_RD_PTR + (queue * 0x14));
840 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
841 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
842 queue, r, w);
843 return -EAGAIN;
844 }
845
846 return 0;
847 }
848
849 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
850 {
851 struct hisi_hba *hisi_hba = dq->hisi_hba;
852 int dlvry_queue = dq->slot_prep->dlvry_queue;
853 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
854
855 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
856 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
857 dq->wr_point);
858 }
859
860 static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
861 struct hisi_sas_slot *slot,
862 struct hisi_sas_cmd_hdr *hdr,
863 struct scatterlist *scatter,
864 int n_elem)
865 {
866 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
867 struct device *dev = hisi_hba->dev;
868 struct scatterlist *sg;
869 int i;
870
871 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
872 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
873 n_elem);
874 return -EINVAL;
875 }
876
877 for_each_sg(scatter, sg, n_elem, i) {
878 struct hisi_sas_sge *entry = &sge_page->sge[i];
879
880 entry->addr = cpu_to_le64(sg_dma_address(sg));
881 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
882 entry->data_len = cpu_to_le32(sg_dma_len(sg));
883 entry->data_off = 0;
884 }
885
886 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
887
888 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
889
890 return 0;
891 }
892
893 static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
894 struct hisi_sas_slot *slot, int is_tmf,
895 struct hisi_sas_tmf_task *tmf)
896 {
897 struct sas_task *task = slot->task;
898 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
899 struct domain_device *device = task->dev;
900 struct hisi_sas_device *sas_dev = device->lldd_dev;
901 struct hisi_sas_port *port = slot->port;
902 struct sas_ssp_task *ssp_task = &task->ssp_task;
903 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
904 int has_data = 0, rc, priority = is_tmf;
905 u8 *buf_cmd;
906 u32 dw1 = 0, dw2 = 0;
907
908 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
909 (2 << CMD_HDR_TLR_CTRL_OFF) |
910 (port->id << CMD_HDR_PORT_OFF) |
911 (priority << CMD_HDR_PRIORITY_OFF) |
912 (1 << CMD_HDR_CMD_OFF)); /* ssp */
913
914 dw1 = 1 << CMD_HDR_VDTL_OFF;
915 if (is_tmf) {
916 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
917 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
918 } else {
919 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
920 switch (scsi_cmnd->sc_data_direction) {
921 case DMA_TO_DEVICE:
922 has_data = 1;
923 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
924 break;
925 case DMA_FROM_DEVICE:
926 has_data = 1;
927 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
928 break;
929 default:
930 dw1 &= ~CMD_HDR_DIR_MSK;
931 }
932 }
933
934 /* map itct entry */
935 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
936 hdr->dw1 = cpu_to_le32(dw1);
937
938 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
939 + 3) / 4) << CMD_HDR_CFL_OFF) |
940 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
941 (2 << CMD_HDR_SG_MOD_OFF);
942 hdr->dw2 = cpu_to_le32(dw2);
943 hdr->transfer_tags = cpu_to_le32(slot->idx);
944
945 if (has_data) {
946 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
947 slot->n_elem);
948 if (rc)
949 return rc;
950 }
951
952 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
953 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
954 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
955
956 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
957 sizeof(struct ssp_frame_hdr);
958
959 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
960 if (!is_tmf) {
961 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
962 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
963 } else {
964 buf_cmd[10] = tmf->tmf;
965 switch (tmf->tmf) {
966 case TMF_ABORT_TASK:
967 case TMF_QUERY_TASK:
968 buf_cmd[12] =
969 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
970 buf_cmd[13] =
971 tmf->tag_of_task_to_be_managed & 0xff;
972 break;
973 default:
974 break;
975 }
976 }
977
978 return 0;
979 }
980
981 static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
982 struct hisi_sas_slot *slot)
983 {
984 struct sas_task *task = slot->task;
985 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
986 struct domain_device *device = task->dev;
987 struct device *dev = hisi_hba->dev;
988 struct hisi_sas_port *port = slot->port;
989 struct scatterlist *sg_req, *sg_resp;
990 struct hisi_sas_device *sas_dev = device->lldd_dev;
991 dma_addr_t req_dma_addr;
992 unsigned int req_len, resp_len;
993 int elem, rc;
994
995 /*
996 * DMA-map SMP request, response buffers
997 */
998 /* req */
999 sg_req = &task->smp_task.smp_req;
1000 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1001 if (!elem)
1002 return -ENOMEM;
1003 req_len = sg_dma_len(sg_req);
1004 req_dma_addr = sg_dma_address(sg_req);
1005
1006 /* resp */
1007 sg_resp = &task->smp_task.smp_resp;
1008 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1009 if (!elem) {
1010 rc = -ENOMEM;
1011 goto err_out_req;
1012 }
1013 resp_len = sg_dma_len(sg_resp);
1014 if ((req_len & 0x3) || (resp_len & 0x3)) {
1015 rc = -EINVAL;
1016 goto err_out_resp;
1017 }
1018
1019 /* create header */
1020 /* dw0 */
1021 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1022 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1023 (2 << CMD_HDR_CMD_OFF)); /* smp */
1024
1025 /* map itct entry */
1026 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1027 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1028 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1029
1030 /* dw2 */
1031 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1032 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1033 CMD_HDR_MRFL_OFF));
1034
1035 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1036
1037 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1038 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1039
1040 return 0;
1041
1042 err_out_resp:
1043 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1044 DMA_FROM_DEVICE);
1045 err_out_req:
1046 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1047 DMA_TO_DEVICE);
1048 return rc;
1049 }
1050
1051 static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1052 struct hisi_sas_slot *slot)
1053 {
1054 struct sas_task *task = slot->task;
1055 struct domain_device *device = task->dev;
1056 struct domain_device *parent_dev = device->parent;
1057 struct hisi_sas_device *sas_dev = device->lldd_dev;
1058 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1059 struct asd_sas_port *sas_port = device->port;
1060 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1061 u8 *buf_cmd;
1062 int has_data = 0, rc = 0, hdr_tag = 0;
1063 u32 dw1 = 0, dw2 = 0;
1064
1065 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1066 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1067 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1068 else
1069 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1070
1071 switch (task->data_dir) {
1072 case DMA_TO_DEVICE:
1073 has_data = 1;
1074 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1075 break;
1076 case DMA_FROM_DEVICE:
1077 has_data = 1;
1078 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1079 break;
1080 default:
1081 dw1 &= ~CMD_HDR_DIR_MSK;
1082 }
1083
1084 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1085 (task->ata_task.fis.control & ATA_SRST))
1086 dw1 |= 1 << CMD_HDR_RESET_OFF;
1087
1088 dw1 |= (hisi_sas_get_ata_protocol(
1089 &task->ata_task.fis, task->data_dir))
1090 << CMD_HDR_FRAME_TYPE_OFF;
1091 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1092
1093 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1094 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1095
1096 hdr->dw1 = cpu_to_le32(dw1);
1097
1098 /* dw2 */
1099 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
1100 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1101 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1102 }
1103
1104 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1105 2 << CMD_HDR_SG_MOD_OFF;
1106 hdr->dw2 = cpu_to_le32(dw2);
1107
1108 /* dw3 */
1109 hdr->transfer_tags = cpu_to_le32(slot->idx);
1110
1111 if (has_data) {
1112 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1113 slot->n_elem);
1114 if (rc)
1115 return rc;
1116 }
1117
1118 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1119 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1120 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1121
1122 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1123
1124 if (likely(!task->ata_task.device_control_reg_update))
1125 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1126 /* fill in command FIS */
1127 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1128
1129 return 0;
1130 }
1131
1132 static int prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1133 struct hisi_sas_slot *slot,
1134 int device_id, int abort_flag, int tag_to_abort)
1135 {
1136 struct sas_task *task = slot->task;
1137 struct domain_device *dev = task->dev;
1138 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1139 struct hisi_sas_port *port = slot->port;
1140
1141 /* dw0 */
1142 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1143 (port->id << CMD_HDR_PORT_OFF) |
1144 (dev_is_sata(dev)
1145 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1146 (abort_flag
1147 << CMD_HDR_ABORT_FLAG_OFF));
1148
1149 /* dw1 */
1150 hdr->dw1 = cpu_to_le32(device_id
1151 << CMD_HDR_DEV_ID_OFF);
1152
1153 /* dw7 */
1154 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1155 hdr->transfer_tags = cpu_to_le32(slot->idx);
1156
1157 return 0;
1158 }
1159
1160 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1161 {
1162 int i, res;
1163 u32 context, port_id, link_rate;
1164 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1165 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1166 struct device *dev = hisi_hba->dev;
1167
1168 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1169
1170 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1171 port_id = (port_id >> (4 * phy_no)) & 0xf;
1172 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1173 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1174
1175 if (port_id == 0xf) {
1176 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1177 res = IRQ_NONE;
1178 goto end;
1179 }
1180 sas_phy->linkrate = link_rate;
1181 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1182
1183 /* Check for SATA dev */
1184 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1185 if (context & (1 << phy_no)) {
1186 struct hisi_sas_initial_fis *initial_fis;
1187 struct dev_to_host_fis *fis;
1188 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1189
1190 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1191 initial_fis = &hisi_hba->initial_fis[phy_no];
1192 fis = &initial_fis->fis;
1193 sas_phy->oob_mode = SATA_OOB_MODE;
1194 attached_sas_addr[0] = 0x50;
1195 attached_sas_addr[7] = phy_no;
1196 memcpy(sas_phy->attached_sas_addr,
1197 attached_sas_addr,
1198 SAS_ADDR_SIZE);
1199 memcpy(sas_phy->frame_rcvd, fis,
1200 sizeof(struct dev_to_host_fis));
1201 phy->phy_type |= PORT_TYPE_SATA;
1202 phy->identify.device_type = SAS_SATA_DEV;
1203 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1204 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1205 } else {
1206 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1207 struct sas_identify_frame *id =
1208 (struct sas_identify_frame *)frame_rcvd;
1209
1210 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1211 for (i = 0; i < 6; i++) {
1212 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1213 RX_IDAF_DWORD0 + (i * 4));
1214 frame_rcvd[i] = __swab32(idaf);
1215 }
1216 sas_phy->oob_mode = SAS_OOB_MODE;
1217 memcpy(sas_phy->attached_sas_addr,
1218 &id->sas_addr,
1219 SAS_ADDR_SIZE);
1220 phy->phy_type |= PORT_TYPE_SAS;
1221 phy->identify.device_type = id->dev_type;
1222 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1223 if (phy->identify.device_type == SAS_END_DEVICE)
1224 phy->identify.target_port_protocols =
1225 SAS_PROTOCOL_SSP;
1226 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1227 phy->identify.target_port_protocols =
1228 SAS_PROTOCOL_SMP;
1229 }
1230
1231 phy->port_id = port_id;
1232 phy->phy_attached = 1;
1233 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1234 res = IRQ_HANDLED;
1235 end:
1236 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1237 CHL_INT0_SL_PHY_ENABLE_MSK);
1238 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1239
1240 return res;
1241 }
1242
1243 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1244 {
1245 u32 phy_state, sl_ctrl, txid_auto;
1246 struct device *dev = hisi_hba->dev;
1247
1248 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1249
1250 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1251 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1252 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1253
1254 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1255 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1256 sl_ctrl&(~SL_CTA_MSK));
1257
1258 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1259 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1260 txid_auto | CT3_MSK);
1261
1262 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1263 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1264
1265 return IRQ_HANDLED;
1266 }
1267
1268 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1269 {
1270 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1271 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1272 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1273
1274 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1275 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1276 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1277 CHL_INT0_SL_RX_BCST_ACK_MSK);
1278 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1279
1280 return IRQ_HANDLED;
1281 }
1282
1283 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1284 {
1285 struct hisi_hba *hisi_hba = p;
1286 u32 irq_msk;
1287 int phy_no = 0;
1288 irqreturn_t res = IRQ_NONE;
1289
1290 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1291 & 0x11111111;
1292 while (irq_msk) {
1293 if (irq_msk & 1) {
1294 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1295 CHL_INT0);
1296 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1297 int rdy = phy_state & (1 << phy_no);
1298
1299 if (rdy) {
1300 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1301 /* phy up */
1302 if (phy_up_v3_hw(phy_no, hisi_hba)
1303 == IRQ_HANDLED)
1304 res = IRQ_HANDLED;
1305 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1306 /* phy bcast */
1307 if (phy_bcast_v3_hw(phy_no, hisi_hba)
1308 == IRQ_HANDLED)
1309 res = IRQ_HANDLED;
1310 } else {
1311 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1312 /* phy down */
1313 if (phy_down_v3_hw(phy_no, hisi_hba)
1314 == IRQ_HANDLED)
1315 res = IRQ_HANDLED;
1316 }
1317 }
1318 irq_msk >>= 4;
1319 phy_no++;
1320 }
1321
1322 return res;
1323 }
1324
1325 static const struct hisi_sas_hw_error port_axi_error[] = {
1326 {
1327 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1328 .msg = "dma_tx_axi_wr_err",
1329 },
1330 {
1331 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1332 .msg = "dma_tx_axi_rd_err",
1333 },
1334 {
1335 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1336 .msg = "dma_rx_axi_wr_err",
1337 },
1338 {
1339 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1340 .msg = "dma_rx_axi_rd_err",
1341 },
1342 };
1343
1344 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1345 {
1346 struct hisi_hba *hisi_hba = p;
1347 struct device *dev = hisi_hba->dev;
1348 u32 irq_msk;
1349 int phy_no = 0;
1350
1351 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1352 & 0xeeeeeeee;
1353
1354 while (irq_msk) {
1355 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1356 CHL_INT0);
1357 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1358 CHL_INT1);
1359 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1360 CHL_INT2);
1361 u32 irq_msk1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1362 CHL_INT1_MSK);
1363 u32 irq_msk2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1364 CHL_INT2_MSK);
1365
1366 irq_value1 &= ~irq_msk1;
1367 irq_value2 &= ~irq_msk2;
1368
1369 if ((irq_msk & (4 << (phy_no * 4))) &&
1370 irq_value1) {
1371 int i;
1372
1373 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1374 const struct hisi_sas_hw_error *error =
1375 &port_axi_error[i];
1376
1377 if (!(irq_value1 & error->irq_msk))
1378 continue;
1379
1380 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1381 error->msg, phy_no, irq_value1);
1382 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1383 }
1384
1385 hisi_sas_phy_write32(hisi_hba, phy_no,
1386 CHL_INT1, irq_value1);
1387 }
1388
1389 if (irq_msk & (8 << (phy_no * 4)) && irq_value2) {
1390 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1391
1392 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1393 dev_warn(dev, "phy%d identify timeout\n",
1394 phy_no);
1395 hisi_sas_notify_phy_event(phy,
1396 HISI_PHYE_LINK_RESET);
1397
1398 }
1399
1400 if (irq_value2 & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1401 u32 reg_value = hisi_sas_phy_read32(hisi_hba,
1402 phy_no, STP_LINK_TIMEOUT_STATE);
1403
1404 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1405 phy_no, reg_value);
1406 if (reg_value & BIT(4))
1407 hisi_sas_notify_phy_event(phy,
1408 HISI_PHYE_LINK_RESET);
1409 }
1410
1411 hisi_sas_phy_write32(hisi_hba, phy_no,
1412 CHL_INT2, irq_value2);
1413 }
1414
1415
1416 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1417 hisi_sas_phy_write32(hisi_hba, phy_no,
1418 CHL_INT0, irq_value0
1419 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1420 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1421 & (~CHL_INT0_NOT_RDY_MSK));
1422 }
1423 irq_msk &= ~(0xe << (phy_no * 4));
1424 phy_no++;
1425 }
1426
1427 return IRQ_HANDLED;
1428 }
1429
1430 static const struct hisi_sas_hw_error axi_error[] = {
1431 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1432 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1433 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1434 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1435 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1436 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1437 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1438 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1439 {},
1440 };
1441
1442 static const struct hisi_sas_hw_error fifo_error[] = {
1443 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
1444 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
1445 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1446 { .msk = BIT(11), .msg = "CMDP_FIFO" },
1447 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1448 {},
1449 };
1450
1451 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1452 {
1453 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1454 .msg = "write pointer and depth",
1455 },
1456 {
1457 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
1458 .msg = "iptt no match slot",
1459 },
1460 {
1461 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
1462 .msg = "read pointer and depth",
1463 },
1464 {
1465 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
1466 .reg = HGC_AXI_FIFO_ERR_INFO,
1467 .sub = axi_error,
1468 },
1469 {
1470 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
1471 .reg = HGC_AXI_FIFO_ERR_INFO,
1472 .sub = fifo_error,
1473 },
1474 {
1475 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
1476 .msg = "LM add/fetch list",
1477 },
1478 {
1479 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
1480 .msg = "SAS_HGC_ABT fetch LM list",
1481 },
1482 };
1483
1484 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
1485 {
1486 u32 irq_value, irq_msk;
1487 struct hisi_hba *hisi_hba = p;
1488 struct device *dev = hisi_hba->dev;
1489 int i;
1490
1491 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1492 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
1493
1494 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
1495 irq_value &= ~irq_msk;
1496
1497 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
1498 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
1499
1500 if (!(irq_value & error->irq_msk))
1501 continue;
1502
1503 if (error->sub) {
1504 const struct hisi_sas_hw_error *sub = error->sub;
1505 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
1506
1507 for (; sub->msk || sub->msg; sub++) {
1508 if (!(err_value & sub->msk))
1509 continue;
1510
1511 dev_err(dev, "%s error (0x%x) found!\n",
1512 sub->msg, irq_value);
1513 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1514 }
1515 } else {
1516 dev_err(dev, "%s error (0x%x) found!\n",
1517 error->msg, irq_value);
1518 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1519 }
1520 }
1521
1522 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
1523 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
1524 u32 dev_id = reg_val & ITCT_DEV_MSK;
1525 struct hisi_sas_device *sas_dev =
1526 &hisi_hba->devices[dev_id];
1527
1528 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
1529 dev_dbg(dev, "clear ITCT ok\n");
1530 complete(sas_dev->completion);
1531 }
1532
1533 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
1534 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
1535
1536 return IRQ_HANDLED;
1537 }
1538
1539 static void
1540 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1541 struct hisi_sas_slot *slot)
1542 {
1543 struct task_status_struct *ts = &task->task_status;
1544 struct hisi_sas_complete_v3_hdr *complete_queue =
1545 hisi_hba->complete_hdr[slot->cmplt_queue];
1546 struct hisi_sas_complete_v3_hdr *complete_hdr =
1547 &complete_queue[slot->cmplt_queue_slot];
1548 struct hisi_sas_err_record_v3 *record =
1549 hisi_sas_status_buf_addr_mem(slot);
1550 u32 dma_rx_err_type = record->dma_rx_err_type;
1551 u32 trans_tx_fail_type = record->trans_tx_fail_type;
1552
1553 switch (task->task_proto) {
1554 case SAS_PROTOCOL_SSP:
1555 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1556 ts->residual = trans_tx_fail_type;
1557 ts->stat = SAS_DATA_UNDERRUN;
1558 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1559 ts->stat = SAS_QUEUE_FULL;
1560 slot->abort = 1;
1561 } else {
1562 ts->stat = SAS_OPEN_REJECT;
1563 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1564 }
1565 break;
1566 case SAS_PROTOCOL_SATA:
1567 case SAS_PROTOCOL_STP:
1568 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1569 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1570 ts->residual = trans_tx_fail_type;
1571 ts->stat = SAS_DATA_UNDERRUN;
1572 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1573 ts->stat = SAS_PHY_DOWN;
1574 slot->abort = 1;
1575 } else {
1576 ts->stat = SAS_OPEN_REJECT;
1577 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1578 }
1579 hisi_sas_sata_done(task, slot);
1580 break;
1581 case SAS_PROTOCOL_SMP:
1582 ts->stat = SAM_STAT_CHECK_CONDITION;
1583 break;
1584 default:
1585 break;
1586 }
1587 }
1588
1589 static int
1590 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1591 {
1592 struct sas_task *task = slot->task;
1593 struct hisi_sas_device *sas_dev;
1594 struct device *dev = hisi_hba->dev;
1595 struct task_status_struct *ts;
1596 struct domain_device *device;
1597 struct sas_ha_struct *ha;
1598 enum exec_status sts;
1599 struct hisi_sas_complete_v3_hdr *complete_queue =
1600 hisi_hba->complete_hdr[slot->cmplt_queue];
1601 struct hisi_sas_complete_v3_hdr *complete_hdr =
1602 &complete_queue[slot->cmplt_queue_slot];
1603 unsigned long flags;
1604 bool is_internal = slot->is_internal;
1605
1606 if (unlikely(!task || !task->lldd_task || !task->dev))
1607 return -EINVAL;
1608
1609 ts = &task->task_status;
1610 device = task->dev;
1611 ha = device->port->ha;
1612 sas_dev = device->lldd_dev;
1613
1614 spin_lock_irqsave(&task->task_state_lock, flags);
1615 task->task_state_flags &=
1616 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1617 spin_unlock_irqrestore(&task->task_state_lock, flags);
1618
1619 memset(ts, 0, sizeof(*ts));
1620 ts->resp = SAS_TASK_COMPLETE;
1621
1622 if (unlikely(!sas_dev)) {
1623 dev_dbg(dev, "slot complete: port has not device\n");
1624 ts->stat = SAS_PHY_DOWN;
1625 goto out;
1626 }
1627
1628 /*
1629 * Use SAS+TMF status codes
1630 */
1631 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1632 >> CMPLT_HDR_ABORT_STAT_OFF) {
1633 case STAT_IO_ABORTED:
1634 /* this IO has been aborted by abort command */
1635 ts->stat = SAS_ABORTED_TASK;
1636 goto out;
1637 case STAT_IO_COMPLETE:
1638 /* internal abort command complete */
1639 ts->stat = TMF_RESP_FUNC_SUCC;
1640 goto out;
1641 case STAT_IO_NO_DEVICE:
1642 ts->stat = TMF_RESP_FUNC_COMPLETE;
1643 goto out;
1644 case STAT_IO_NOT_VALID:
1645 /*
1646 * abort single IO, the controller can't find the IO
1647 */
1648 ts->stat = TMF_RESP_FUNC_FAILED;
1649 goto out;
1650 default:
1651 break;
1652 }
1653
1654 /* check for erroneous completion */
1655 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1656 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
1657
1658 slot_err_v3_hw(hisi_hba, task, slot);
1659 if (ts->stat != SAS_DATA_UNDERRUN)
1660 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
1661 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
1662 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
1663 slot->idx, task, sas_dev->device_id,
1664 complete_hdr->dw0, complete_hdr->dw1,
1665 complete_hdr->act, complete_hdr->dw3,
1666 error_info[0], error_info[1],
1667 error_info[2], error_info[3]);
1668 if (unlikely(slot->abort))
1669 return ts->stat;
1670 goto out;
1671 }
1672
1673 switch (task->task_proto) {
1674 case SAS_PROTOCOL_SSP: {
1675 struct ssp_response_iu *iu =
1676 hisi_sas_status_buf_addr_mem(slot) +
1677 sizeof(struct hisi_sas_err_record);
1678
1679 sas_ssp_task_response(dev, task, iu);
1680 break;
1681 }
1682 case SAS_PROTOCOL_SMP: {
1683 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1684 void *to;
1685
1686 ts->stat = SAM_STAT_GOOD;
1687 to = kmap_atomic(sg_page(sg_resp));
1688
1689 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1690 DMA_FROM_DEVICE);
1691 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1692 DMA_TO_DEVICE);
1693 memcpy(to + sg_resp->offset,
1694 hisi_sas_status_buf_addr_mem(slot) +
1695 sizeof(struct hisi_sas_err_record),
1696 sg_dma_len(sg_resp));
1697 kunmap_atomic(to);
1698 break;
1699 }
1700 case SAS_PROTOCOL_SATA:
1701 case SAS_PROTOCOL_STP:
1702 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1703 ts->stat = SAM_STAT_GOOD;
1704 hisi_sas_sata_done(task, slot);
1705 break;
1706 default:
1707 ts->stat = SAM_STAT_CHECK_CONDITION;
1708 break;
1709 }
1710
1711 if (!slot->port->port_attached) {
1712 dev_warn(dev, "slot complete: port %d has removed\n",
1713 slot->port->sas_port.id);
1714 ts->stat = SAS_PHY_DOWN;
1715 }
1716
1717 out:
1718 hisi_sas_slot_task_free(hisi_hba, task, slot);
1719 sts = ts->stat;
1720 spin_lock_irqsave(&task->task_state_lock, flags);
1721 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
1722 spin_unlock_irqrestore(&task->task_state_lock, flags);
1723 dev_info(dev, "slot complete: task(%p) aborted\n", task);
1724 return SAS_ABORTED_TASK;
1725 }
1726 task->task_state_flags |= SAS_TASK_STATE_DONE;
1727 spin_unlock_irqrestore(&task->task_state_lock, flags);
1728
1729 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
1730 spin_lock_irqsave(&device->done_lock, flags);
1731 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
1732 spin_unlock_irqrestore(&device->done_lock, flags);
1733 dev_info(dev, "slot complete: task(%p) ignored\n ",
1734 task);
1735 return sts;
1736 }
1737 spin_unlock_irqrestore(&device->done_lock, flags);
1738 }
1739
1740 if (task->task_done)
1741 task->task_done(task);
1742
1743 return sts;
1744 }
1745
1746 static void cq_tasklet_v3_hw(unsigned long val)
1747 {
1748 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1749 struct hisi_hba *hisi_hba = cq->hisi_hba;
1750 struct hisi_sas_slot *slot;
1751 struct hisi_sas_complete_v3_hdr *complete_queue;
1752 u32 rd_point = cq->rd_point, wr_point;
1753 int queue = cq->id;
1754
1755 complete_queue = hisi_hba->complete_hdr[queue];
1756
1757 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1758 (0x14 * queue));
1759
1760 while (rd_point != wr_point) {
1761 struct hisi_sas_complete_v3_hdr *complete_hdr;
1762 struct device *dev = hisi_hba->dev;
1763 int iptt;
1764
1765 complete_hdr = &complete_queue[rd_point];
1766
1767 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1768 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
1769 slot = &hisi_hba->slot_info[iptt];
1770 slot->cmplt_queue_slot = rd_point;
1771 slot->cmplt_queue = queue;
1772 slot_complete_v3_hw(hisi_hba, slot);
1773 } else
1774 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
1775
1776 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1777 rd_point = 0;
1778 }
1779
1780 /* update rd_point */
1781 cq->rd_point = rd_point;
1782 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1783 }
1784
1785 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1786 {
1787 struct hisi_sas_cq *cq = p;
1788 struct hisi_hba *hisi_hba = cq->hisi_hba;
1789 int queue = cq->id;
1790
1791 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1792
1793 tasklet_schedule(&cq->tasklet);
1794
1795 return IRQ_HANDLED;
1796 }
1797
1798 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1799 {
1800 struct device *dev = hisi_hba->dev;
1801 struct pci_dev *pdev = hisi_hba->pci_dev;
1802 int vectors, rc;
1803 int i, k;
1804 int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1805
1806 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1807 max_msi, PCI_IRQ_MSI);
1808 if (vectors < max_msi) {
1809 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1810 return -ENOENT;
1811 }
1812
1813 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1814 int_phy_up_down_bcast_v3_hw, 0,
1815 DRV_NAME " phy", hisi_hba);
1816 if (rc) {
1817 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1818 rc = -ENOENT;
1819 goto free_irq_vectors;
1820 }
1821
1822 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1823 int_chnl_int_v3_hw, 0,
1824 DRV_NAME " channel", hisi_hba);
1825 if (rc) {
1826 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1827 rc = -ENOENT;
1828 goto free_phy_irq;
1829 }
1830
1831 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
1832 fatal_axi_int_v3_hw, 0,
1833 DRV_NAME " fatal", hisi_hba);
1834 if (rc) {
1835 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
1836 rc = -ENOENT;
1837 goto free_chnl_interrupt;
1838 }
1839
1840 /* Init tasklets for cq only */
1841 for (i = 0; i < hisi_hba->queue_count; i++) {
1842 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1843 struct tasklet_struct *t = &cq->tasklet;
1844
1845 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1846 cq_interrupt_v3_hw, 0,
1847 DRV_NAME " cq", cq);
1848 if (rc) {
1849 dev_err(dev,
1850 "could not request cq%d interrupt, rc=%d\n",
1851 i, rc);
1852 rc = -ENOENT;
1853 goto free_cq_irqs;
1854 }
1855
1856 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1857 }
1858
1859 return 0;
1860
1861 free_cq_irqs:
1862 for (k = 0; k < i; k++) {
1863 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1864
1865 free_irq(pci_irq_vector(pdev, k+16), cq);
1866 }
1867 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
1868 free_chnl_interrupt:
1869 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1870 free_phy_irq:
1871 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1872 free_irq_vectors:
1873 pci_free_irq_vectors(pdev);
1874 return rc;
1875 }
1876
1877 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1878 {
1879 int rc;
1880
1881 rc = hw_init_v3_hw(hisi_hba);
1882 if (rc)
1883 return rc;
1884
1885 rc = interrupt_init_v3_hw(hisi_hba);
1886 if (rc)
1887 return rc;
1888
1889 return 0;
1890 }
1891
1892 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
1893 struct sas_phy_linkrates *r)
1894 {
1895 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1896 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1897 enum sas_linkrate min, max;
1898 u32 prog_phy_link_rate = 0x800;
1899
1900 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1901 max = sas_phy->phy->maximum_linkrate;
1902 min = r->minimum_linkrate;
1903 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1904 max = r->maximum_linkrate;
1905 min = sas_phy->phy->minimum_linkrate;
1906 } else
1907 return;
1908
1909 sas_phy->phy->maximum_linkrate = max;
1910 sas_phy->phy->minimum_linkrate = min;
1911 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
1912
1913 disable_phy_v3_hw(hisi_hba, phy_no);
1914 msleep(100);
1915 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1916 prog_phy_link_rate);
1917 start_phy_v3_hw(hisi_hba, phy_no);
1918 }
1919
1920 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
1921 {
1922 struct pci_dev *pdev = hisi_hba->pci_dev;
1923 int i;
1924
1925 synchronize_irq(pci_irq_vector(pdev, 1));
1926 synchronize_irq(pci_irq_vector(pdev, 2));
1927 synchronize_irq(pci_irq_vector(pdev, 11));
1928 for (i = 0; i < hisi_hba->queue_count; i++) {
1929 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
1930 synchronize_irq(pci_irq_vector(pdev, i + 16));
1931 }
1932
1933 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
1934 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
1935 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
1936 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1937
1938 for (i = 0; i < hisi_hba->n_phy; i++) {
1939 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1940 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
1941 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
1942 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
1943 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
1944 }
1945 }
1946
1947 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
1948 {
1949 return hisi_sas_read32(hisi_hba, PHY_STATE);
1950 }
1951
1952 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1953 {
1954 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1955 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1956 struct sas_phy *sphy = sas_phy->phy;
1957 u32 reg_value;
1958
1959 /* loss dword sync */
1960 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1961 sphy->loss_of_dword_sync_count += reg_value;
1962
1963 /* phy reset problem */
1964 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1965 sphy->phy_reset_problem_count += reg_value;
1966
1967 /* invalid dword */
1968 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1969 sphy->invalid_dword_count += reg_value;
1970
1971 /* disparity err */
1972 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1973 sphy->running_disparity_error_count += reg_value;
1974
1975 }
1976
1977 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
1978 {
1979 struct device *dev = hisi_hba->dev;
1980 int rc;
1981 u32 status;
1982
1983 interrupt_disable_v3_hw(hisi_hba);
1984 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
1985 hisi_sas_kill_tasklets(hisi_hba);
1986
1987 hisi_sas_stop_phys(hisi_hba);
1988
1989 mdelay(10);
1990
1991 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
1992
1993 /* wait until bus idle */
1994 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
1995 AM_CURR_TRANS_RETURN, status,
1996 status == 0x3, 10, 100);
1997 if (rc) {
1998 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
1999 return rc;
2000 }
2001
2002 hisi_sas_init_mem(hisi_hba);
2003
2004 return hw_init_v3_hw(hisi_hba);
2005 }
2006
2007 static const struct hisi_sas_hw hisi_sas_v3_hw = {
2008 .hw_init = hisi_sas_v3_init,
2009 .setup_itct = setup_itct_v3_hw,
2010 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
2011 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
2012 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
2013 .clear_itct = clear_itct_v3_hw,
2014 .sl_notify = sl_notify_v3_hw,
2015 .prep_ssp = prep_ssp_v3_hw,
2016 .prep_smp = prep_smp_v3_hw,
2017 .prep_stp = prep_ata_v3_hw,
2018 .prep_abort = prep_abort_v3_hw,
2019 .get_free_slot = get_free_slot_v3_hw,
2020 .start_delivery = start_delivery_v3_hw,
2021 .slot_complete = slot_complete_v3_hw,
2022 .phys_init = phys_init_v3_hw,
2023 .phy_start = start_phy_v3_hw,
2024 .phy_disable = disable_phy_v3_hw,
2025 .phy_hard_reset = phy_hard_reset_v3_hw,
2026 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
2027 .phy_set_linkrate = phy_set_linkrate_v3_hw,
2028 .dereg_device = dereg_device_v3_hw,
2029 .soft_reset = soft_reset_v3_hw,
2030 .get_phys_state = get_phys_state_v3_hw,
2031 .get_events = phy_get_events_v3_hw,
2032 };
2033
2034 static struct Scsi_Host *
2035 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
2036 {
2037 struct Scsi_Host *shost;
2038 struct hisi_hba *hisi_hba;
2039 struct device *dev = &pdev->dev;
2040
2041 shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
2042 if (!shost) {
2043 dev_err(dev, "shost alloc failed\n");
2044 return NULL;
2045 }
2046 hisi_hba = shost_priv(shost);
2047
2048 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
2049 hisi_hba->hw = &hisi_sas_v3_hw;
2050 hisi_hba->pci_dev = pdev;
2051 hisi_hba->dev = dev;
2052 hisi_hba->shost = shost;
2053 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
2054
2055 timer_setup(&hisi_hba->timer, NULL, 0);
2056
2057 if (hisi_sas_get_fw_info(hisi_hba) < 0)
2058 goto err_out;
2059
2060 if (hisi_sas_alloc(hisi_hba, shost)) {
2061 hisi_sas_free(hisi_hba);
2062 goto err_out;
2063 }
2064
2065 return shost;
2066 err_out:
2067 scsi_host_put(shost);
2068 dev_err(dev, "shost alloc failed\n");
2069 return NULL;
2070 }
2071
2072 static int
2073 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2074 {
2075 struct Scsi_Host *shost;
2076 struct hisi_hba *hisi_hba;
2077 struct device *dev = &pdev->dev;
2078 struct asd_sas_phy **arr_phy;
2079 struct asd_sas_port **arr_port;
2080 struct sas_ha_struct *sha;
2081 int rc, phy_nr, port_nr, i;
2082
2083 rc = pci_enable_device(pdev);
2084 if (rc)
2085 goto err_out;
2086
2087 pci_set_master(pdev);
2088
2089 rc = pci_request_regions(pdev, DRV_NAME);
2090 if (rc)
2091 goto err_out_disable_device;
2092
2093 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
2094 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
2095 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2096 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2097 dev_err(dev, "No usable DMA addressing method\n");
2098 rc = -EIO;
2099 goto err_out_regions;
2100 }
2101 }
2102
2103 shost = hisi_sas_shost_alloc_pci(pdev);
2104 if (!shost) {
2105 rc = -ENOMEM;
2106 goto err_out_regions;
2107 }
2108
2109 sha = SHOST_TO_SAS_HA(shost);
2110 hisi_hba = shost_priv(shost);
2111 dev_set_drvdata(dev, sha);
2112
2113 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
2114 if (!hisi_hba->regs) {
2115 dev_err(dev, "cannot map register.\n");
2116 rc = -ENOMEM;
2117 goto err_out_ha;
2118 }
2119
2120 phy_nr = port_nr = hisi_hba->n_phy;
2121
2122 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
2123 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
2124 if (!arr_phy || !arr_port) {
2125 rc = -ENOMEM;
2126 goto err_out_ha;
2127 }
2128
2129 sha->sas_phy = arr_phy;
2130 sha->sas_port = arr_port;
2131 sha->core.shost = shost;
2132 sha->lldd_ha = hisi_hba;
2133
2134 shost->transportt = hisi_sas_stt;
2135 shost->max_id = HISI_SAS_MAX_DEVICES;
2136 shost->max_lun = ~0;
2137 shost->max_channel = 1;
2138 shost->max_cmd_len = 16;
2139 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
2140 shost->can_queue = hisi_hba->hw->max_command_entries;
2141 shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
2142
2143 sha->sas_ha_name = DRV_NAME;
2144 sha->dev = dev;
2145 sha->lldd_module = THIS_MODULE;
2146 sha->sas_addr = &hisi_hba->sas_addr[0];
2147 sha->num_phys = hisi_hba->n_phy;
2148 sha->core.shost = hisi_hba->shost;
2149
2150 for (i = 0; i < hisi_hba->n_phy; i++) {
2151 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
2152 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
2153 }
2154
2155 hisi_sas_init_add(hisi_hba);
2156
2157 rc = scsi_add_host(shost, dev);
2158 if (rc)
2159 goto err_out_ha;
2160
2161 rc = sas_register_ha(sha);
2162 if (rc)
2163 goto err_out_register_ha;
2164
2165 rc = hisi_hba->hw->hw_init(hisi_hba);
2166 if (rc)
2167 goto err_out_register_ha;
2168
2169 scsi_scan_host(shost);
2170
2171 return 0;
2172
2173 err_out_register_ha:
2174 scsi_remove_host(shost);
2175 err_out_ha:
2176 scsi_host_put(shost);
2177 err_out_regions:
2178 pci_release_regions(pdev);
2179 err_out_disable_device:
2180 pci_disable_device(pdev);
2181 err_out:
2182 return rc;
2183 }
2184
2185 static void
2186 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
2187 {
2188 int i;
2189
2190 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2191 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2192 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2193 for (i = 0; i < hisi_hba->queue_count; i++) {
2194 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2195
2196 free_irq(pci_irq_vector(pdev, i+16), cq);
2197 }
2198 pci_free_irq_vectors(pdev);
2199 }
2200
2201 static void hisi_sas_v3_remove(struct pci_dev *pdev)
2202 {
2203 struct device *dev = &pdev->dev;
2204 struct sas_ha_struct *sha = dev_get_drvdata(dev);
2205 struct hisi_hba *hisi_hba = sha->lldd_ha;
2206 struct Scsi_Host *shost = sha->core.shost;
2207
2208 if (timer_pending(&hisi_hba->timer))
2209 del_timer(&hisi_hba->timer);
2210
2211 sas_unregister_ha(sha);
2212 sas_remove_host(sha->core.shost);
2213
2214 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
2215 hisi_sas_kill_tasklets(hisi_hba);
2216 pci_release_regions(pdev);
2217 pci_disable_device(pdev);
2218 hisi_sas_free(hisi_hba);
2219 scsi_host_put(shost);
2220 }
2221
2222 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = {
2223 { .irq_msk = BIT(19), .msg = "HILINK_INT" },
2224 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" },
2225 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" },
2226 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" },
2227 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" },
2228 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" },
2229 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" },
2230 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" },
2231 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" },
2232 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" },
2233 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" },
2234 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" },
2235 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" },
2236 };
2237
2238 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = {
2239 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" },
2240 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" },
2241 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" },
2242 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" },
2243 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" },
2244 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" },
2245 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" },
2246 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" },
2247 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" },
2248 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" },
2249 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" },
2250 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" },
2251 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" },
2252 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" },
2253 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" },
2254 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" },
2255 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" },
2256 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" },
2257 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" },
2258 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" },
2259 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" },
2260 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" },
2261 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" },
2262 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" },
2263 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" },
2264 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" },
2265 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" },
2266 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" },
2267 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" },
2268 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" },
2269 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" },
2270 };
2271
2272 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = {
2273 { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" },
2274 { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" },
2275 { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" },
2276 { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" },
2277 { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" },
2278 { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" },
2279 { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" },
2280 { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" },
2281 { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" },
2282 { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" },
2283 { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" },
2284 { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" },
2285 { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" },
2286 { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" },
2287 { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" },
2288 { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" },
2289 { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" },
2290 { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" },
2291 { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" },
2292 { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" },
2293 };
2294
2295 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba)
2296 {
2297 struct device *dev = hisi_hba->dev;
2298 const struct hisi_sas_hw_error *ras_error;
2299 bool need_reset = false;
2300 u32 irq_value;
2301 int i;
2302
2303 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0);
2304 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) {
2305 ras_error = &sas_ras_intr0_nfe[i];
2306 if (ras_error->irq_msk & irq_value) {
2307 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n",
2308 ras_error->msg, irq_value);
2309 need_reset = true;
2310 }
2311 }
2312 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value);
2313
2314 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1);
2315 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) {
2316 ras_error = &sas_ras_intr1_nfe[i];
2317 if (ras_error->irq_msk & irq_value) {
2318 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n",
2319 ras_error->msg, irq_value);
2320 need_reset = true;
2321 }
2322 }
2323 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value);
2324
2325 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2);
2326 for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) {
2327 ras_error = &sas_ras_intr2_nfe[i];
2328 if (ras_error->irq_msk & irq_value) {
2329 dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n",
2330 ras_error->msg, irq_value);
2331 need_reset = true;
2332 }
2333 }
2334 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value);
2335
2336 return need_reset;
2337 }
2338
2339 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev,
2340 pci_channel_state_t state)
2341 {
2342 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2343 struct hisi_hba *hisi_hba = sha->lldd_ha;
2344 struct device *dev = hisi_hba->dev;
2345
2346 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state);
2347 if (state == pci_channel_io_perm_failure)
2348 return PCI_ERS_RESULT_DISCONNECT;
2349
2350 if (process_non_fatal_error_v3_hw(hisi_hba))
2351 return PCI_ERS_RESULT_NEED_RESET;
2352
2353 return PCI_ERS_RESULT_CAN_RECOVER;
2354 }
2355
2356 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev)
2357 {
2358 return PCI_ERS_RESULT_RECOVERED;
2359 }
2360
2361 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev)
2362 {
2363 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2364 struct hisi_hba *hisi_hba = sha->lldd_ha;
2365 struct device *dev = hisi_hba->dev;
2366 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r);
2367
2368 dev_info(dev, "PCI error: slot reset callback!!\n");
2369 queue_work(hisi_hba->wq, &r.work);
2370 wait_for_completion(r.completion);
2371 if (r.done)
2372 return PCI_ERS_RESULT_RECOVERED;
2373
2374 return PCI_ERS_RESULT_DISCONNECT;
2375 }
2376
2377 enum {
2378 /* instances of the controller */
2379 hip08,
2380 };
2381
2382 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state)
2383 {
2384 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2385 struct hisi_hba *hisi_hba = sha->lldd_ha;
2386 struct device *dev = hisi_hba->dev;
2387 struct Scsi_Host *shost = hisi_hba->shost;
2388 u32 device_state, status;
2389 int rc;
2390 u32 reg_val;
2391 unsigned long flags;
2392
2393 if (!pdev->pm_cap) {
2394 dev_err(dev, "PCI PM not supported\n");
2395 return -ENODEV;
2396 }
2397
2398 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2399 scsi_block_requests(shost);
2400 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2401 flush_workqueue(hisi_hba->wq);
2402 /* disable DQ/PHY/bus */
2403 interrupt_disable_v3_hw(hisi_hba);
2404 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2405 hisi_sas_kill_tasklets(hisi_hba);
2406
2407 hisi_sas_stop_phys(hisi_hba);
2408
2409 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2410 AM_CTRL_GLOBAL);
2411 reg_val |= 0x1;
2412 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2413 AM_CTRL_GLOBAL, reg_val);
2414
2415 /* wait until bus idle */
2416 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2417 AM_CURR_TRANS_RETURN, status,
2418 status == 0x3, 10, 100);
2419 if (rc) {
2420 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
2421 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2422 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2423 scsi_unblock_requests(shost);
2424 return rc;
2425 }
2426
2427 hisi_sas_init_mem(hisi_hba);
2428
2429 device_state = pci_choose_state(pdev, state);
2430 dev_warn(dev, "entering operating state [D%d]\n",
2431 device_state);
2432 pci_save_state(pdev);
2433 pci_disable_device(pdev);
2434 pci_set_power_state(pdev, device_state);
2435
2436 spin_lock_irqsave(&hisi_hba->lock, flags);
2437 hisi_sas_release_tasks(hisi_hba);
2438 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2439
2440 sas_suspend_ha(sha);
2441 return 0;
2442 }
2443
2444 static int hisi_sas_v3_resume(struct pci_dev *pdev)
2445 {
2446 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2447 struct hisi_hba *hisi_hba = sha->lldd_ha;
2448 struct Scsi_Host *shost = hisi_hba->shost;
2449 struct device *dev = hisi_hba->dev;
2450 unsigned int rc;
2451 u32 device_state = pdev->current_state;
2452
2453 dev_warn(dev, "resuming from operating state [D%d]\n",
2454 device_state);
2455 pci_set_power_state(pdev, PCI_D0);
2456 pci_enable_wake(pdev, PCI_D0, 0);
2457 pci_restore_state(pdev);
2458 rc = pci_enable_device(pdev);
2459 if (rc)
2460 dev_err(dev, "enable device failed during resume (%d)\n", rc);
2461
2462 pci_set_master(pdev);
2463 scsi_unblock_requests(shost);
2464 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2465
2466 sas_prep_resume_ha(sha);
2467 init_reg_v3_hw(hisi_hba);
2468 hisi_hba->hw->phys_init(hisi_hba);
2469 sas_resume_ha(sha);
2470 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2471
2472 return 0;
2473 }
2474
2475 static const struct pci_device_id sas_v3_pci_table[] = {
2476 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
2477 {}
2478 };
2479 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
2480
2481 static const struct pci_error_handlers hisi_sas_err_handler = {
2482 .error_detected = hisi_sas_error_detected_v3_hw,
2483 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw,
2484 .slot_reset = hisi_sas_slot_reset_v3_hw,
2485 };
2486
2487 static struct pci_driver sas_v3_pci_driver = {
2488 .name = DRV_NAME,
2489 .id_table = sas_v3_pci_table,
2490 .probe = hisi_sas_v3_probe,
2491 .remove = hisi_sas_v3_remove,
2492 .suspend = hisi_sas_v3_suspend,
2493 .resume = hisi_sas_v3_resume,
2494 .err_handler = &hisi_sas_err_handler,
2495 };
2496
2497 module_pci_driver(sas_v3_pci_driver);
2498
2499 MODULE_LICENSE("GPL");
2500 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2501 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2502 MODULE_ALIAS("pci:" DRV_NAME);
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