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scsi: hisi_sas: add v3 hw MODULE_DEVICE_TABLE()
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v3_hw.c
1 /*
2 * Copyright (c) 2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 #include "hisi_sas.h"
12 #define DRV_NAME "hisi_sas_v3_hw"
13
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
26 #define ITCT_CLR 0x44
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CFG_1US_TIMER_TRSH 0xcc
55 #define CHNL_INT_STATUS 0x148
56 #define HGC_AXI_FIFO_ERR_INFO 0x154
57 #define AXI_ERR_INFO_OFF 0
58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
59 #define FIFO_ERR_INFO_OFF 8
60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
61 #define INT_COAL_EN 0x19c
62 #define OQ_INT_COAL_TIME 0x1a0
63 #define OQ_INT_COAL_CNT 0x1a4
64 #define ENT_INT_COAL_TIME 0x1a8
65 #define ENT_INT_COAL_CNT 0x1ac
66 #define OQ_INT_SRC 0x1b0
67 #define OQ_INT_SRC_MSK 0x1b4
68 #define ENT_INT_SRC1 0x1b8
69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
73 #define ENT_INT_SRC2 0x1bc
74 #define ENT_INT_SRC3 0x1c0
75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
78 #define ENT_INT_SRC3_AXI_OFF 11
79 #define ENT_INT_SRC3_FIFO_OFF 12
80 #define ENT_INT_SRC3_LM_OFF 14
81 #define ENT_INT_SRC3_ITC_INT_OFF 15
82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
83 #define ENT_INT_SRC3_ABT_OFF 16
84 #define ENT_INT_SRC_MSK1 0x1c4
85 #define ENT_INT_SRC_MSK2 0x1c8
86 #define ENT_INT_SRC_MSK3 0x1cc
87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
89 #define CHNL_ENT_INT_MSK 0x1d4
90 #define HGC_COM_INT_MSK 0x1d8
91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
92 #define SAS_ECC_INTR 0x1e8
93 #define SAS_ECC_INTR_MSK 0x1ec
94 #define HGC_ERR_STAT_EN 0x238
95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
97 #define DLVRY_Q_0_DEPTH 0x268
98 #define DLVRY_Q_0_WR_PTR 0x26c
99 #define DLVRY_Q_0_RD_PTR 0x270
100 #define HYPER_STREAM_ID_EN_CFG 0xc80
101 #define OQ0_INT_SRC_MSK 0xc90
102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
104 #define COMPL_Q_0_DEPTH 0x4e8
105 #define COMPL_Q_0_WR_PTR 0x4ec
106 #define COMPL_Q_0_RD_PTR 0x4f0
107 #define AWQOS_AWCACHE_CFG 0xc84
108 #define ARQOS_ARCACHE_CFG 0xc88
109
110 /* phy registers requiring init */
111 #define PORT_BASE (0x2000)
112 #define PHY_CFG (PORT_BASE + 0x0)
113 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
114 #define PHY_CFG_ENA_OFF 0
115 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
116 #define PHY_CFG_DC_OPT_OFF 2
117 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
118 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
119 #define PHY_CTRL (PORT_BASE + 0x14)
120 #define PHY_CTRL_RESET_OFF 0
121 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
122 #define SL_CFG (PORT_BASE + 0x84)
123 #define SL_CONTROL (PORT_BASE + 0x94)
124 #define SL_CONTROL_NOTIFY_EN_OFF 0
125 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
126 #define SL_CTA_OFF 17
127 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
128 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
129 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
130 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
131 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
132 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
133 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
134 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
135 #define TXID_AUTO (PORT_BASE + 0xb8)
136 #define CT3_OFF 1
137 #define CT3_MSK (0x1 << CT3_OFF)
138 #define TX_HARDRST_OFF 2
139 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
140 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
141 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
142 #define STP_LINK_TIMER (PORT_BASE + 0x120)
143 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
144 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
145 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
146 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
147 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
148 #define CHL_INT0 (PORT_BASE + 0x1b4)
149 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
150 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
151 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
152 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
153 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
154 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
155 #define CHL_INT0_NOT_RDY_OFF 4
156 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
157 #define CHL_INT0_PHY_RDY_OFF 5
158 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
159 #define CHL_INT1 (PORT_BASE + 0x1b8)
160 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
161 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
162 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
163 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
164 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
165 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
166 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
167 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
168 #define CHL_INT2 (PORT_BASE + 0x1bc)
169 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
170 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
171 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
172 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
173 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
174 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
175 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
176 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
177 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
178 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
179 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
180 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
181 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
182 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
183 #define DMA_TX_STATUS_BUSY_OFF 0
184 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
185 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
186 #define DMA_RX_STATUS_BUSY_OFF 0
187 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
188
189 #define COARSETUNE_TIME (PORT_BASE + 0x304)
190 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
191 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
192 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
193 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
194
195 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
196 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
197 #error Max ITCT exceeded
198 #endif
199
200 #define AXI_MASTER_CFG_BASE (0x5000)
201 #define AM_CTRL_GLOBAL (0x0)
202 #define AM_CURR_TRANS_RETURN (0x150)
203
204 #define AM_CFG_MAX_TRANS (0x5010)
205 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
206 #define AXI_CFG (0x5100)
207 #define AM_ROB_ECC_ERR_ADDR (0x510c)
208 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
209 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
210 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
211 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
212
213 /* RAS registers need init */
214 #define RAS_BASE (0x6000)
215 #define SAS_RAS_INTR0 (RAS_BASE)
216 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
217 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
218 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
219
220 /* HW dma structures */
221 /* Delivery queue header */
222 /* dw0 */
223 #define CMD_HDR_ABORT_FLAG_OFF 0
224 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
225 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
226 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
227 #define CMD_HDR_RESP_REPORT_OFF 5
228 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
229 #define CMD_HDR_TLR_CTRL_OFF 6
230 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
231 #define CMD_HDR_PORT_OFF 18
232 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
233 #define CMD_HDR_PRIORITY_OFF 27
234 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
235 #define CMD_HDR_CMD_OFF 29
236 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
237 /* dw1 */
238 #define CMD_HDR_UNCON_CMD_OFF 3
239 #define CMD_HDR_DIR_OFF 5
240 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
241 #define CMD_HDR_RESET_OFF 7
242 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
243 #define CMD_HDR_VDTL_OFF 10
244 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
245 #define CMD_HDR_FRAME_TYPE_OFF 11
246 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
247 #define CMD_HDR_DEV_ID_OFF 16
248 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
249 /* dw2 */
250 #define CMD_HDR_CFL_OFF 0
251 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
252 #define CMD_HDR_NCQ_TAG_OFF 10
253 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
254 #define CMD_HDR_MRFL_OFF 15
255 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
256 #define CMD_HDR_SG_MOD_OFF 24
257 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
258 /* dw3 */
259 #define CMD_HDR_IPTT_OFF 0
260 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
261 /* dw6 */
262 #define CMD_HDR_DIF_SGL_LEN_OFF 0
263 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
264 #define CMD_HDR_DATA_SGL_LEN_OFF 16
265 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
266 /* dw7 */
267 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
268 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
269 #define CMD_HDR_ABORT_IPTT_OFF 16
270 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
271
272 /* Completion header */
273 /* dw0 */
274 #define CMPLT_HDR_CMPLT_OFF 0
275 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
276 #define CMPLT_HDR_ERROR_PHASE_OFF 2
277 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
278 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
279 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
280 #define CMPLT_HDR_ERX_OFF 12
281 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
282 #define CMPLT_HDR_ABORT_STAT_OFF 13
283 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
284 /* abort_stat */
285 #define STAT_IO_NOT_VALID 0x1
286 #define STAT_IO_NO_DEVICE 0x2
287 #define STAT_IO_COMPLETE 0x3
288 #define STAT_IO_ABORTED 0x4
289 /* dw1 */
290 #define CMPLT_HDR_IPTT_OFF 0
291 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
292 #define CMPLT_HDR_DEV_ID_OFF 16
293 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
294 /* dw3 */
295 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
296 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
297
298 /* ITCT header */
299 /* qw0 */
300 #define ITCT_HDR_DEV_TYPE_OFF 0
301 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
302 #define ITCT_HDR_VALID_OFF 2
303 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
304 #define ITCT_HDR_MCR_OFF 5
305 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
306 #define ITCT_HDR_VLN_OFF 9
307 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
308 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
309 #define ITCT_HDR_AWT_CONTINUE_OFF 25
310 #define ITCT_HDR_PORT_ID_OFF 28
311 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
312 /* qw2 */
313 #define ITCT_HDR_INLT_OFF 0
314 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
315 #define ITCT_HDR_RTOLT_OFF 48
316 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
317
318 struct hisi_sas_complete_v3_hdr {
319 __le32 dw0;
320 __le32 dw1;
321 __le32 act;
322 __le32 dw3;
323 };
324
325 struct hisi_sas_err_record_v3 {
326 /* dw0 */
327 __le32 trans_tx_fail_type;
328
329 /* dw1 */
330 __le32 trans_rx_fail_type;
331
332 /* dw2 */
333 __le16 dma_tx_err_type;
334 __le16 sipc_rx_err_type;
335
336 /* dw3 */
337 __le32 dma_rx_err_type;
338 };
339
340 #define RX_DATA_LEN_UNDERFLOW_OFF 6
341 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
342
343 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
344 #define HISI_SAS_MSI_COUNT_V3_HW 32
345
346 enum {
347 HISI_SAS_PHY_PHY_UPDOWN,
348 HISI_SAS_PHY_CHNL_INT,
349 HISI_SAS_PHY_INT_NR
350 };
351
352 #define DIR_NO_DATA 0
353 #define DIR_TO_INI 1
354 #define DIR_TO_DEVICE 2
355 #define DIR_RESERVED 3
356
357 #define CMD_IS_UNCONSTRAINT(cmd) \
358 ((cmd == ATA_CMD_READ_LOG_EXT) || \
359 (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
360 (cmd == ATA_CMD_DEV_RESET))
361
362 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
363 {
364 void __iomem *regs = hisi_hba->regs + off;
365
366 return readl(regs);
367 }
368
369 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
370 {
371 void __iomem *regs = hisi_hba->regs + off;
372
373 return readl_relaxed(regs);
374 }
375
376 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
377 {
378 void __iomem *regs = hisi_hba->regs + off;
379
380 writel(val, regs);
381 }
382
383 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
384 u32 off, u32 val)
385 {
386 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
387
388 writel(val, regs);
389 }
390
391 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
392 int phy_no, u32 off)
393 {
394 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
395
396 return readl(regs);
397 }
398
399 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
400 {
401 int i;
402
403 /* Global registers init */
404 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
405 (u32)((1ULL << hisi_hba->queue_count) - 1));
406 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
407 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
408 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
409 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
410 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
411 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
412 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
413 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
414 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
415 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
416 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
417 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
418 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff);
419 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
420 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
421 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
422 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
423 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
424 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
425 for (i = 0; i < hisi_hba->queue_count; i++)
426 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
427
428 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
429
430 for (i = 0; i < hisi_hba->n_phy; i++) {
431 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
432 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
433 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
434 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
435 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
436 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
437 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff87ffff);
438 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
439 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
440 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
441 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
442 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
443 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
444 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
445 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
446
447 /* used for 12G negotiate */
448 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
449 }
450
451 for (i = 0; i < hisi_hba->queue_count; i++) {
452 /* Delivery queue */
453 hisi_sas_write32(hisi_hba,
454 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
455 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
456
457 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
458 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
459
460 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
461 HISI_SAS_QUEUE_SLOTS);
462
463 /* Completion queue */
464 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
465 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
466
467 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
468 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
469
470 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
471 HISI_SAS_QUEUE_SLOTS);
472 }
473
474 /* itct */
475 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
476 lower_32_bits(hisi_hba->itct_dma));
477
478 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
479 upper_32_bits(hisi_hba->itct_dma));
480
481 /* iost */
482 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
483 lower_32_bits(hisi_hba->iost_dma));
484
485 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
486 upper_32_bits(hisi_hba->iost_dma));
487
488 /* breakpoint */
489 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
490 lower_32_bits(hisi_hba->breakpoint_dma));
491
492 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
493 upper_32_bits(hisi_hba->breakpoint_dma));
494
495 /* SATA broken msg */
496 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
497 lower_32_bits(hisi_hba->sata_breakpoint_dma));
498
499 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
500 upper_32_bits(hisi_hba->sata_breakpoint_dma));
501
502 /* SATA initial fis */
503 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
504 lower_32_bits(hisi_hba->initial_fis_dma));
505
506 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
507 upper_32_bits(hisi_hba->initial_fis_dma));
508
509 /* RAS registers init */
510 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
511 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
512 }
513
514 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
515 {
516 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
517
518 cfg &= ~PHY_CFG_DC_OPT_MSK;
519 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
520 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
521 }
522
523 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
524 {
525 struct sas_identify_frame identify_frame;
526 u32 *identify_buffer;
527
528 memset(&identify_frame, 0, sizeof(identify_frame));
529 identify_frame.dev_type = SAS_END_DEVICE;
530 identify_frame.frame_type = 0;
531 identify_frame._un1 = 1;
532 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
533 identify_frame.target_bits = SAS_PROTOCOL_NONE;
534 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
535 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
536 identify_frame.phy_id = phy_no;
537 identify_buffer = (u32 *)(&identify_frame);
538
539 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
540 __swab32(identify_buffer[0]));
541 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
542 __swab32(identify_buffer[1]));
543 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
544 __swab32(identify_buffer[2]));
545 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
546 __swab32(identify_buffer[3]));
547 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
548 __swab32(identify_buffer[4]));
549 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
550 __swab32(identify_buffer[5]));
551 }
552
553 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
554 struct hisi_sas_device *sas_dev)
555 {
556 struct domain_device *device = sas_dev->sas_device;
557 struct device *dev = hisi_hba->dev;
558 u64 qw0, device_id = sas_dev->device_id;
559 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
560 struct domain_device *parent_dev = device->parent;
561 struct asd_sas_port *sas_port = device->port;
562 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
563
564 memset(itct, 0, sizeof(*itct));
565
566 /* qw0 */
567 qw0 = 0;
568 switch (sas_dev->dev_type) {
569 case SAS_END_DEVICE:
570 case SAS_EDGE_EXPANDER_DEVICE:
571 case SAS_FANOUT_EXPANDER_DEVICE:
572 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
573 break;
574 case SAS_SATA_DEV:
575 case SAS_SATA_PENDING:
576 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
577 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
578 else
579 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
580 break;
581 default:
582 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
583 sas_dev->dev_type);
584 }
585
586 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
587 (device->linkrate << ITCT_HDR_MCR_OFF) |
588 (1 << ITCT_HDR_VLN_OFF) |
589 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
590 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
591 (port->id << ITCT_HDR_PORT_ID_OFF));
592 itct->qw0 = cpu_to_le64(qw0);
593
594 /* qw1 */
595 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
596 itct->sas_addr = __swab64(itct->sas_addr);
597
598 /* qw2 */
599 if (!dev_is_sata(device))
600 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
601 (0x1ULL << ITCT_HDR_RTOLT_OFF));
602 }
603
604 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba,
605 struct hisi_sas_device *sas_dev)
606 {
607 DECLARE_COMPLETION_ONSTACK(completion);
608 u64 dev_id = sas_dev->device_id;
609 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
610 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
611
612 sas_dev->completion = &completion;
613
614 /* clear the itct interrupt state */
615 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
616 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
617 ENT_INT_SRC3_ITC_INT_MSK);
618
619 /* clear the itct table*/
620 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
621 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
622
623 wait_for_completion(sas_dev->completion);
624 memset(itct, 0, sizeof(struct hisi_sas_itct));
625 }
626
627 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
628 struct domain_device *device)
629 {
630 struct hisi_sas_slot *slot, *slot2;
631 struct hisi_sas_device *sas_dev = device->lldd_dev;
632 u32 cfg_abt_set_query_iptt;
633
634 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
635 CFG_ABT_SET_QUERY_IPTT);
636 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
637 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
638 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
639 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
640 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
641 cfg_abt_set_query_iptt);
642 }
643 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
644 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
645 cfg_abt_set_query_iptt);
646 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
647 1 << CFG_ABT_SET_IPTT_DONE_OFF);
648 }
649
650 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
651 {
652 struct device *dev = hisi_hba->dev;
653 int ret;
654 u32 val;
655
656 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
657
658 /* Disable all of the PHYs */
659 hisi_sas_stop_phys(hisi_hba);
660 udelay(50);
661
662 /* Ensure axi bus idle */
663 ret = readl_poll_timeout(hisi_hba->regs + AXI_CFG, val, !val,
664 20000, 1000000);
665 if (ret) {
666 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
667 return -EIO;
668 }
669
670 if (ACPI_HANDLE(dev)) {
671 acpi_status s;
672
673 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
674 if (ACPI_FAILURE(s)) {
675 dev_err(dev, "Reset failed\n");
676 return -EIO;
677 }
678 } else
679 dev_err(dev, "no reset method!\n");
680
681 return 0;
682 }
683
684 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
685 {
686 struct device *dev = hisi_hba->dev;
687 int rc;
688
689 rc = reset_hw_v3_hw(hisi_hba);
690 if (rc) {
691 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
692 return rc;
693 }
694
695 msleep(100);
696 init_reg_v3_hw(hisi_hba);
697
698 return 0;
699 }
700
701 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
702 {
703 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
704
705 cfg |= PHY_CFG_ENA_MSK;
706 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
707 }
708
709 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
710 {
711 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
712
713 cfg &= ~PHY_CFG_ENA_MSK;
714 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
715 }
716
717 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
718 {
719 config_id_frame_v3_hw(hisi_hba, phy_no);
720 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
721 enable_phy_v3_hw(hisi_hba, phy_no);
722 }
723
724 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
725 {
726 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
727 u32 txid_auto;
728
729 disable_phy_v3_hw(hisi_hba, phy_no);
730 if (phy->identify.device_type == SAS_END_DEVICE) {
731 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
732 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
733 txid_auto | TX_HARDRST_MSK);
734 }
735 msleep(100);
736 start_phy_v3_hw(hisi_hba, phy_no);
737 }
738
739 enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
740 {
741 return SAS_LINK_RATE_12_0_GBPS;
742 }
743
744 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
745 {
746 int i;
747
748 for (i = 0; i < hisi_hba->n_phy; i++) {
749 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
750 struct asd_sas_phy *sas_phy = &phy->sas_phy;
751
752 if (!sas_phy->phy->enabled)
753 continue;
754
755 start_phy_v3_hw(hisi_hba, i);
756 }
757 }
758
759 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
760 {
761 u32 sl_control;
762
763 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
764 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
765 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
766 msleep(1);
767 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
768 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
769 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
770 }
771
772 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
773 {
774 int i, bitmap = 0;
775 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
776 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
777
778 for (i = 0; i < hisi_hba->n_phy; i++)
779 if (phy_state & BIT(i))
780 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
781 bitmap |= BIT(i);
782
783 return bitmap;
784 }
785
786 /**
787 * The callpath to this function and upto writing the write
788 * queue pointer should be safe from interruption.
789 */
790 static int
791 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
792 {
793 struct device *dev = hisi_hba->dev;
794 int queue = dq->id;
795 u32 r, w;
796
797 w = dq->wr_point;
798 r = hisi_sas_read32_relaxed(hisi_hba,
799 DLVRY_Q_0_RD_PTR + (queue * 0x14));
800 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
801 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
802 queue, r, w);
803 return -EAGAIN;
804 }
805
806 return 0;
807 }
808
809 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
810 {
811 struct hisi_hba *hisi_hba = dq->hisi_hba;
812 int dlvry_queue = dq->slot_prep->dlvry_queue;
813 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
814
815 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
816 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
817 dq->wr_point);
818 }
819
820 static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
821 struct hisi_sas_slot *slot,
822 struct hisi_sas_cmd_hdr *hdr,
823 struct scatterlist *scatter,
824 int n_elem)
825 {
826 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
827 struct device *dev = hisi_hba->dev;
828 struct scatterlist *sg;
829 int i;
830
831 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
832 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
833 n_elem);
834 return -EINVAL;
835 }
836
837 for_each_sg(scatter, sg, n_elem, i) {
838 struct hisi_sas_sge *entry = &sge_page->sge[i];
839
840 entry->addr = cpu_to_le64(sg_dma_address(sg));
841 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
842 entry->data_len = cpu_to_le32(sg_dma_len(sg));
843 entry->data_off = 0;
844 }
845
846 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
847
848 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
849
850 return 0;
851 }
852
853 static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
854 struct hisi_sas_slot *slot, int is_tmf,
855 struct hisi_sas_tmf_task *tmf)
856 {
857 struct sas_task *task = slot->task;
858 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
859 struct domain_device *device = task->dev;
860 struct hisi_sas_device *sas_dev = device->lldd_dev;
861 struct hisi_sas_port *port = slot->port;
862 struct sas_ssp_task *ssp_task = &task->ssp_task;
863 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
864 int has_data = 0, rc, priority = is_tmf;
865 u8 *buf_cmd;
866 u32 dw1 = 0, dw2 = 0;
867
868 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
869 (2 << CMD_HDR_TLR_CTRL_OFF) |
870 (port->id << CMD_HDR_PORT_OFF) |
871 (priority << CMD_HDR_PRIORITY_OFF) |
872 (1 << CMD_HDR_CMD_OFF)); /* ssp */
873
874 dw1 = 1 << CMD_HDR_VDTL_OFF;
875 if (is_tmf) {
876 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
877 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
878 } else {
879 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
880 switch (scsi_cmnd->sc_data_direction) {
881 case DMA_TO_DEVICE:
882 has_data = 1;
883 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
884 break;
885 case DMA_FROM_DEVICE:
886 has_data = 1;
887 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
888 break;
889 default:
890 dw1 &= ~CMD_HDR_DIR_MSK;
891 }
892 }
893
894 /* map itct entry */
895 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
896 hdr->dw1 = cpu_to_le32(dw1);
897
898 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
899 + 3) / 4) << CMD_HDR_CFL_OFF) |
900 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
901 (2 << CMD_HDR_SG_MOD_OFF);
902 hdr->dw2 = cpu_to_le32(dw2);
903 hdr->transfer_tags = cpu_to_le32(slot->idx);
904
905 if (has_data) {
906 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
907 slot->n_elem);
908 if (rc)
909 return rc;
910 }
911
912 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
913 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
914 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
915
916 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
917 sizeof(struct ssp_frame_hdr);
918
919 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
920 if (!is_tmf) {
921 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
922 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
923 } else {
924 buf_cmd[10] = tmf->tmf;
925 switch (tmf->tmf) {
926 case TMF_ABORT_TASK:
927 case TMF_QUERY_TASK:
928 buf_cmd[12] =
929 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
930 buf_cmd[13] =
931 tmf->tag_of_task_to_be_managed & 0xff;
932 break;
933 default:
934 break;
935 }
936 }
937
938 return 0;
939 }
940
941 static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
942 struct hisi_sas_slot *slot)
943 {
944 struct sas_task *task = slot->task;
945 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
946 struct domain_device *device = task->dev;
947 struct device *dev = hisi_hba->dev;
948 struct hisi_sas_port *port = slot->port;
949 struct scatterlist *sg_req, *sg_resp;
950 struct hisi_sas_device *sas_dev = device->lldd_dev;
951 dma_addr_t req_dma_addr;
952 unsigned int req_len, resp_len;
953 int elem, rc;
954
955 /*
956 * DMA-map SMP request, response buffers
957 */
958 /* req */
959 sg_req = &task->smp_task.smp_req;
960 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
961 if (!elem)
962 return -ENOMEM;
963 req_len = sg_dma_len(sg_req);
964 req_dma_addr = sg_dma_address(sg_req);
965
966 /* resp */
967 sg_resp = &task->smp_task.smp_resp;
968 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
969 if (!elem) {
970 rc = -ENOMEM;
971 goto err_out_req;
972 }
973 resp_len = sg_dma_len(sg_resp);
974 if ((req_len & 0x3) || (resp_len & 0x3)) {
975 rc = -EINVAL;
976 goto err_out_resp;
977 }
978
979 /* create header */
980 /* dw0 */
981 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
982 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
983 (2 << CMD_HDR_CMD_OFF)); /* smp */
984
985 /* map itct entry */
986 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
987 (1 << CMD_HDR_FRAME_TYPE_OFF) |
988 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
989
990 /* dw2 */
991 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
992 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
993 CMD_HDR_MRFL_OFF));
994
995 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
996
997 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
998 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
999
1000 return 0;
1001
1002 err_out_resp:
1003 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1004 DMA_FROM_DEVICE);
1005 err_out_req:
1006 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1007 DMA_TO_DEVICE);
1008 return rc;
1009 }
1010
1011 static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1012 struct hisi_sas_slot *slot)
1013 {
1014 struct sas_task *task = slot->task;
1015 struct domain_device *device = task->dev;
1016 struct domain_device *parent_dev = device->parent;
1017 struct hisi_sas_device *sas_dev = device->lldd_dev;
1018 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1019 struct asd_sas_port *sas_port = device->port;
1020 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1021 u8 *buf_cmd;
1022 int has_data = 0, rc = 0, hdr_tag = 0;
1023 u32 dw1 = 0, dw2 = 0;
1024
1025 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1026 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1027 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1028 else
1029 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1030
1031 switch (task->data_dir) {
1032 case DMA_TO_DEVICE:
1033 has_data = 1;
1034 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1035 break;
1036 case DMA_FROM_DEVICE:
1037 has_data = 1;
1038 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1039 break;
1040 default:
1041 dw1 &= ~CMD_HDR_DIR_MSK;
1042 }
1043
1044 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1045 (task->ata_task.fis.control & ATA_SRST))
1046 dw1 |= 1 << CMD_HDR_RESET_OFF;
1047
1048 dw1 |= (hisi_sas_get_ata_protocol(
1049 &task->ata_task.fis, task->data_dir))
1050 << CMD_HDR_FRAME_TYPE_OFF;
1051 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1052
1053 if (CMD_IS_UNCONSTRAINT(task->ata_task.fis.command))
1054 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1055
1056 hdr->dw1 = cpu_to_le32(dw1);
1057
1058 /* dw2 */
1059 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
1060 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1061 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1062 }
1063
1064 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1065 2 << CMD_HDR_SG_MOD_OFF;
1066 hdr->dw2 = cpu_to_le32(dw2);
1067
1068 /* dw3 */
1069 hdr->transfer_tags = cpu_to_le32(slot->idx);
1070
1071 if (has_data) {
1072 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1073 slot->n_elem);
1074 if (rc)
1075 return rc;
1076 }
1077
1078 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1079 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1080 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1081
1082 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1083
1084 if (likely(!task->ata_task.device_control_reg_update))
1085 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1086 /* fill in command FIS */
1087 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1088
1089 return 0;
1090 }
1091
1092 static int prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1093 struct hisi_sas_slot *slot,
1094 int device_id, int abort_flag, int tag_to_abort)
1095 {
1096 struct sas_task *task = slot->task;
1097 struct domain_device *dev = task->dev;
1098 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1099 struct hisi_sas_port *port = slot->port;
1100
1101 /* dw0 */
1102 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1103 (port->id << CMD_HDR_PORT_OFF) |
1104 ((dev_is_sata(dev) ? 1:0)
1105 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1106 (abort_flag
1107 << CMD_HDR_ABORT_FLAG_OFF));
1108
1109 /* dw1 */
1110 hdr->dw1 = cpu_to_le32(device_id
1111 << CMD_HDR_DEV_ID_OFF);
1112
1113 /* dw7 */
1114 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1115 hdr->transfer_tags = cpu_to_le32(slot->idx);
1116
1117 return 0;
1118 }
1119
1120 static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1121 {
1122 int i, res = 0;
1123 u32 context, port_id, link_rate, hard_phy_linkrate;
1124 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1125 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1126 struct device *dev = hisi_hba->dev;
1127
1128 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1129
1130 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1131 port_id = (port_id >> (4 * phy_no)) & 0xf;
1132 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1133 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1134
1135 if (port_id == 0xf) {
1136 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1137 res = IRQ_NONE;
1138 goto end;
1139 }
1140 sas_phy->linkrate = link_rate;
1141 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1142 HARD_PHY_LINKRATE);
1143 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1144 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1145 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1146
1147 /* Check for SATA dev */
1148 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1149 if (context & (1 << phy_no)) {
1150 struct hisi_sas_initial_fis *initial_fis;
1151 struct dev_to_host_fis *fis;
1152 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1153
1154 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1155 initial_fis = &hisi_hba->initial_fis[phy_no];
1156 fis = &initial_fis->fis;
1157 sas_phy->oob_mode = SATA_OOB_MODE;
1158 attached_sas_addr[0] = 0x50;
1159 attached_sas_addr[7] = phy_no;
1160 memcpy(sas_phy->attached_sas_addr,
1161 attached_sas_addr,
1162 SAS_ADDR_SIZE);
1163 memcpy(sas_phy->frame_rcvd, fis,
1164 sizeof(struct dev_to_host_fis));
1165 phy->phy_type |= PORT_TYPE_SATA;
1166 phy->identify.device_type = SAS_SATA_DEV;
1167 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1168 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1169 } else {
1170 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1171 struct sas_identify_frame *id =
1172 (struct sas_identify_frame *)frame_rcvd;
1173
1174 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1175 for (i = 0; i < 6; i++) {
1176 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1177 RX_IDAF_DWORD0 + (i * 4));
1178 frame_rcvd[i] = __swab32(idaf);
1179 }
1180 sas_phy->oob_mode = SAS_OOB_MODE;
1181 memcpy(sas_phy->attached_sas_addr,
1182 &id->sas_addr,
1183 SAS_ADDR_SIZE);
1184 phy->phy_type |= PORT_TYPE_SAS;
1185 phy->identify.device_type = id->dev_type;
1186 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1187 if (phy->identify.device_type == SAS_END_DEVICE)
1188 phy->identify.target_port_protocols =
1189 SAS_PROTOCOL_SSP;
1190 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1191 phy->identify.target_port_protocols =
1192 SAS_PROTOCOL_SMP;
1193 }
1194
1195 phy->port_id = port_id;
1196 phy->phy_attached = 1;
1197 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1198
1199 end:
1200 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1201 CHL_INT0_SL_PHY_ENABLE_MSK);
1202 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1203
1204 return res;
1205 }
1206
1207 static int phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1208 {
1209 u32 phy_state, sl_ctrl, txid_auto;
1210 struct device *dev = hisi_hba->dev;
1211
1212 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1213
1214 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1215 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1216 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1217
1218 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1219 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1220 sl_ctrl&(~SL_CTA_MSK));
1221
1222 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1223 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1224 txid_auto | CT3_MSK);
1225
1226 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1227 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1228
1229 return 0;
1230 }
1231
1232 static void phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1233 {
1234 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1235 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1236 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1237
1238 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1239 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1240 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1241 CHL_INT0_SL_RX_BCST_ACK_MSK);
1242 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1243 }
1244
1245 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1246 {
1247 struct hisi_hba *hisi_hba = p;
1248 u32 irq_msk;
1249 int phy_no = 0;
1250 irqreturn_t res = IRQ_NONE;
1251
1252 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1253 & 0x11111111;
1254 while (irq_msk) {
1255 if (irq_msk & 1) {
1256 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1257 CHL_INT0);
1258 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1259 int rdy = phy_state & (1 << phy_no);
1260
1261 if (rdy) {
1262 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1263 /* phy up */
1264 if (phy_up_v3_hw(phy_no, hisi_hba)
1265 == IRQ_HANDLED)
1266 res = IRQ_HANDLED;
1267 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1268 /* phy bcast */
1269 phy_bcast_v3_hw(phy_no, hisi_hba);
1270 } else {
1271 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1272 /* phy down */
1273 if (phy_down_v3_hw(phy_no, hisi_hba)
1274 == IRQ_HANDLED)
1275 res = IRQ_HANDLED;
1276 }
1277 }
1278 irq_msk >>= 4;
1279 phy_no++;
1280 }
1281
1282 return res;
1283 }
1284
1285 static const struct hisi_sas_hw_error port_axi_error[] = {
1286 {
1287 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1288 .msg = "dma_tx_axi_wr_err",
1289 },
1290 {
1291 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1292 .msg = "dma_tx_axi_rd_err",
1293 },
1294 {
1295 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1296 .msg = "dma_rx_axi_wr_err",
1297 },
1298 {
1299 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1300 .msg = "dma_rx_axi_rd_err",
1301 },
1302 };
1303
1304 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1305 {
1306 struct hisi_hba *hisi_hba = p;
1307 struct device *dev = hisi_hba->dev;
1308 u32 ent_msk, ent_tmp, irq_msk;
1309 int phy_no = 0;
1310
1311 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1312 ent_tmp = ent_msk;
1313 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1314 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1315
1316 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1317 & 0xeeeeeeee;
1318
1319 while (irq_msk) {
1320 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1321 CHL_INT0);
1322 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1323 CHL_INT1);
1324 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1325 CHL_INT2);
1326
1327 if ((irq_msk & (4 << (phy_no * 4))) &&
1328 irq_value1) {
1329 int i;
1330
1331 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1332 const struct hisi_sas_hw_error *error =
1333 &port_axi_error[i];
1334
1335 if (!(irq_value1 & error->irq_msk))
1336 continue;
1337
1338 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1339 error->msg, phy_no, irq_value1);
1340 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1341 }
1342
1343 hisi_sas_phy_write32(hisi_hba, phy_no,
1344 CHL_INT1, irq_value1);
1345 }
1346
1347 if (irq_msk & (8 << (phy_no * 4)) && irq_value2) {
1348 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1349
1350 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1351 dev_warn(dev, "phy%d identify timeout\n",
1352 phy_no);
1353 hisi_sas_notify_phy_event(phy,
1354 HISI_PHYE_LINK_RESET);
1355
1356 }
1357
1358 if (irq_value2 & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1359 u32 reg_value = hisi_sas_phy_read32(hisi_hba,
1360 phy_no, STP_LINK_TIMEOUT_STATE);
1361
1362 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1363 phy_no, reg_value);
1364 if (reg_value & BIT(4))
1365 hisi_sas_notify_phy_event(phy,
1366 HISI_PHYE_LINK_RESET);
1367 }
1368
1369 hisi_sas_phy_write32(hisi_hba, phy_no,
1370 CHL_INT2, irq_value2);
1371 }
1372
1373
1374 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1375 hisi_sas_phy_write32(hisi_hba, phy_no,
1376 CHL_INT0, irq_value0
1377 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1378 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1379 & (~CHL_INT0_NOT_RDY_MSK));
1380 }
1381 irq_msk &= ~(0xe << (phy_no * 4));
1382 phy_no++;
1383 }
1384
1385 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1386
1387 return IRQ_HANDLED;
1388 }
1389
1390 static const struct hisi_sas_hw_error axi_error[] = {
1391 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1392 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1393 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1394 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1395 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1396 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1397 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1398 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1399 {},
1400 };
1401
1402 static const struct hisi_sas_hw_error fifo_error[] = {
1403 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
1404 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
1405 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1406 { .msk = BIT(11), .msg = "CMDP_FIFO" },
1407 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1408 {},
1409 };
1410
1411 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1412 {
1413 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1414 .msg = "write pointer and depth",
1415 },
1416 {
1417 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
1418 .msg = "iptt no match slot",
1419 },
1420 {
1421 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
1422 .msg = "read pointer and depth",
1423 },
1424 {
1425 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
1426 .reg = HGC_AXI_FIFO_ERR_INFO,
1427 .sub = axi_error,
1428 },
1429 {
1430 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
1431 .reg = HGC_AXI_FIFO_ERR_INFO,
1432 .sub = fifo_error,
1433 },
1434 {
1435 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
1436 .msg = "LM add/fetch list",
1437 },
1438 {
1439 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
1440 .msg = "SAS_HGC_ABT fetch LM list",
1441 },
1442 };
1443
1444 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
1445 {
1446 u32 irq_value, irq_msk;
1447 struct hisi_hba *hisi_hba = p;
1448 struct device *dev = hisi_hba->dev;
1449 int i;
1450
1451 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1452 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
1453
1454 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
1455
1456 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
1457 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
1458
1459 if (!(irq_value & error->irq_msk))
1460 continue;
1461
1462 if (error->sub) {
1463 const struct hisi_sas_hw_error *sub = error->sub;
1464 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
1465
1466 for (; sub->msk || sub->msg; sub++) {
1467 if (!(err_value & sub->msk))
1468 continue;
1469
1470 dev_err(dev, "%s error (0x%x) found!\n",
1471 sub->msg, irq_value);
1472 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1473 }
1474 } else {
1475 dev_err(dev, "%s error (0x%x) found!\n",
1476 error->msg, irq_value);
1477 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1478 }
1479 }
1480
1481 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
1482 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
1483 u32 dev_id = reg_val & ITCT_DEV_MSK;
1484 struct hisi_sas_device *sas_dev =
1485 &hisi_hba->devices[dev_id];
1486
1487 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
1488 dev_dbg(dev, "clear ITCT ok\n");
1489 complete(sas_dev->completion);
1490 }
1491
1492 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
1493 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
1494
1495 return IRQ_HANDLED;
1496 }
1497
1498 static void
1499 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1500 struct hisi_sas_slot *slot)
1501 {
1502 struct task_status_struct *ts = &task->task_status;
1503 struct hisi_sas_complete_v3_hdr *complete_queue =
1504 hisi_hba->complete_hdr[slot->cmplt_queue];
1505 struct hisi_sas_complete_v3_hdr *complete_hdr =
1506 &complete_queue[slot->cmplt_queue_slot];
1507 struct hisi_sas_err_record_v3 *record =
1508 hisi_sas_status_buf_addr_mem(slot);
1509 u32 dma_rx_err_type = record->dma_rx_err_type;
1510 u32 trans_tx_fail_type = record->trans_tx_fail_type;
1511
1512 switch (task->task_proto) {
1513 case SAS_PROTOCOL_SSP:
1514 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1515 ts->residual = trans_tx_fail_type;
1516 ts->stat = SAS_DATA_UNDERRUN;
1517 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1518 ts->stat = SAS_QUEUE_FULL;
1519 slot->abort = 1;
1520 } else {
1521 ts->stat = SAS_OPEN_REJECT;
1522 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1523 }
1524 break;
1525 case SAS_PROTOCOL_SATA:
1526 case SAS_PROTOCOL_STP:
1527 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1528 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1529 ts->residual = trans_tx_fail_type;
1530 ts->stat = SAS_DATA_UNDERRUN;
1531 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1532 ts->stat = SAS_PHY_DOWN;
1533 slot->abort = 1;
1534 } else {
1535 ts->stat = SAS_OPEN_REJECT;
1536 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1537 }
1538 hisi_sas_sata_done(task, slot);
1539 break;
1540 case SAS_PROTOCOL_SMP:
1541 ts->stat = SAM_STAT_CHECK_CONDITION;
1542 break;
1543 default:
1544 break;
1545 }
1546 }
1547
1548 static int
1549 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1550 {
1551 struct sas_task *task = slot->task;
1552 struct hisi_sas_device *sas_dev;
1553 struct device *dev = hisi_hba->dev;
1554 struct task_status_struct *ts;
1555 struct domain_device *device;
1556 enum exec_status sts;
1557 struct hisi_sas_complete_v3_hdr *complete_queue =
1558 hisi_hba->complete_hdr[slot->cmplt_queue];
1559 struct hisi_sas_complete_v3_hdr *complete_hdr =
1560 &complete_queue[slot->cmplt_queue_slot];
1561 int aborted;
1562 unsigned long flags;
1563
1564 if (unlikely(!task || !task->lldd_task || !task->dev))
1565 return -EINVAL;
1566
1567 ts = &task->task_status;
1568 device = task->dev;
1569 sas_dev = device->lldd_dev;
1570
1571 spin_lock_irqsave(&task->task_state_lock, flags);
1572 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1573 task->task_state_flags &=
1574 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1575 spin_unlock_irqrestore(&task->task_state_lock, flags);
1576
1577 memset(ts, 0, sizeof(*ts));
1578 ts->resp = SAS_TASK_COMPLETE;
1579 if (unlikely(aborted)) {
1580 dev_dbg(dev, "slot complete: task(%p) aborted\n", task);
1581 ts->stat = SAS_ABORTED_TASK;
1582 spin_lock_irqsave(&hisi_hba->lock, flags);
1583 hisi_sas_slot_task_free(hisi_hba, task, slot);
1584 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1585 return -1;
1586 }
1587
1588 if (unlikely(!sas_dev)) {
1589 dev_dbg(dev, "slot complete: port has not device\n");
1590 ts->stat = SAS_PHY_DOWN;
1591 goto out;
1592 }
1593
1594 /*
1595 * Use SAS+TMF status codes
1596 */
1597 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1598 >> CMPLT_HDR_ABORT_STAT_OFF) {
1599 case STAT_IO_ABORTED:
1600 /* this IO has been aborted by abort command */
1601 ts->stat = SAS_ABORTED_TASK;
1602 goto out;
1603 case STAT_IO_COMPLETE:
1604 /* internal abort command complete */
1605 ts->stat = TMF_RESP_FUNC_SUCC;
1606 goto out;
1607 case STAT_IO_NO_DEVICE:
1608 ts->stat = TMF_RESP_FUNC_COMPLETE;
1609 goto out;
1610 case STAT_IO_NOT_VALID:
1611 /*
1612 * abort single IO, the controller can't find the IO
1613 */
1614 ts->stat = TMF_RESP_FUNC_FAILED;
1615 goto out;
1616 default:
1617 break;
1618 }
1619
1620 /* check for erroneous completion */
1621 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1622 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
1623
1624 slot_err_v3_hw(hisi_hba, task, slot);
1625 if (ts->stat != SAS_DATA_UNDERRUN)
1626 dev_info(dev, "erroneous completion iptt=%d task=%p "
1627 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
1628 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
1629 slot->idx, task,
1630 complete_hdr->dw0, complete_hdr->dw1,
1631 complete_hdr->act, complete_hdr->dw3,
1632 error_info[0], error_info[1],
1633 error_info[2], error_info[3]);
1634 if (unlikely(slot->abort))
1635 return ts->stat;
1636 goto out;
1637 }
1638
1639 switch (task->task_proto) {
1640 case SAS_PROTOCOL_SSP: {
1641 struct ssp_response_iu *iu =
1642 hisi_sas_status_buf_addr_mem(slot) +
1643 sizeof(struct hisi_sas_err_record);
1644
1645 sas_ssp_task_response(dev, task, iu);
1646 break;
1647 }
1648 case SAS_PROTOCOL_SMP: {
1649 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1650 void *to;
1651
1652 ts->stat = SAM_STAT_GOOD;
1653 to = kmap_atomic(sg_page(sg_resp));
1654
1655 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1656 DMA_FROM_DEVICE);
1657 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1658 DMA_TO_DEVICE);
1659 memcpy(to + sg_resp->offset,
1660 hisi_sas_status_buf_addr_mem(slot) +
1661 sizeof(struct hisi_sas_err_record),
1662 sg_dma_len(sg_resp));
1663 kunmap_atomic(to);
1664 break;
1665 }
1666 case SAS_PROTOCOL_SATA:
1667 case SAS_PROTOCOL_STP:
1668 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1669 ts->stat = SAM_STAT_GOOD;
1670 hisi_sas_sata_done(task, slot);
1671 break;
1672 default:
1673 ts->stat = SAM_STAT_CHECK_CONDITION;
1674 break;
1675 }
1676
1677 if (!slot->port->port_attached) {
1678 dev_warn(dev, "slot complete: port %d has removed\n",
1679 slot->port->sas_port.id);
1680 ts->stat = SAS_PHY_DOWN;
1681 }
1682
1683 out:
1684 spin_lock_irqsave(&task->task_state_lock, flags);
1685 task->task_state_flags |= SAS_TASK_STATE_DONE;
1686 spin_unlock_irqrestore(&task->task_state_lock, flags);
1687 spin_lock_irqsave(&hisi_hba->lock, flags);
1688 hisi_sas_slot_task_free(hisi_hba, task, slot);
1689 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1690 sts = ts->stat;
1691
1692 if (task->task_done)
1693 task->task_done(task);
1694
1695 return sts;
1696 }
1697
1698 static void cq_tasklet_v3_hw(unsigned long val)
1699 {
1700 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1701 struct hisi_hba *hisi_hba = cq->hisi_hba;
1702 struct hisi_sas_slot *slot;
1703 struct hisi_sas_complete_v3_hdr *complete_queue;
1704 u32 rd_point = cq->rd_point, wr_point;
1705 int queue = cq->id;
1706 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
1707
1708 complete_queue = hisi_hba->complete_hdr[queue];
1709
1710 spin_lock(&dq->lock);
1711 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1712 (0x14 * queue));
1713
1714 while (rd_point != wr_point) {
1715 struct hisi_sas_complete_v3_hdr *complete_hdr;
1716 int iptt;
1717
1718 complete_hdr = &complete_queue[rd_point];
1719
1720 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1721 slot = &hisi_hba->slot_info[iptt];
1722 slot->cmplt_queue_slot = rd_point;
1723 slot->cmplt_queue = queue;
1724 slot_complete_v3_hw(hisi_hba, slot);
1725
1726 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1727 rd_point = 0;
1728 }
1729
1730 /* update rd_point */
1731 cq->rd_point = rd_point;
1732 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1733 spin_unlock(&dq->lock);
1734 }
1735
1736 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1737 {
1738 struct hisi_sas_cq *cq = p;
1739 struct hisi_hba *hisi_hba = cq->hisi_hba;
1740 int queue = cq->id;
1741
1742 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1743
1744 tasklet_schedule(&cq->tasklet);
1745
1746 return IRQ_HANDLED;
1747 }
1748
1749 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1750 {
1751 struct device *dev = hisi_hba->dev;
1752 struct pci_dev *pdev = hisi_hba->pci_dev;
1753 int vectors, rc;
1754 int i, k;
1755 int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1756
1757 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1758 max_msi, PCI_IRQ_MSI);
1759 if (vectors < max_msi) {
1760 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1761 return -ENOENT;
1762 }
1763
1764 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1765 int_phy_up_down_bcast_v3_hw, 0,
1766 DRV_NAME " phy", hisi_hba);
1767 if (rc) {
1768 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1769 rc = -ENOENT;
1770 goto free_irq_vectors;
1771 }
1772
1773 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1774 int_chnl_int_v3_hw, 0,
1775 DRV_NAME " channel", hisi_hba);
1776 if (rc) {
1777 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1778 rc = -ENOENT;
1779 goto free_phy_irq;
1780 }
1781
1782 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
1783 fatal_axi_int_v3_hw, 0,
1784 DRV_NAME " fatal", hisi_hba);
1785 if (rc) {
1786 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
1787 rc = -ENOENT;
1788 goto free_chnl_interrupt;
1789 }
1790
1791 /* Init tasklets for cq only */
1792 for (i = 0; i < hisi_hba->queue_count; i++) {
1793 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1794 struct tasklet_struct *t = &cq->tasklet;
1795
1796 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1797 cq_interrupt_v3_hw, 0,
1798 DRV_NAME " cq", cq);
1799 if (rc) {
1800 dev_err(dev,
1801 "could not request cq%d interrupt, rc=%d\n",
1802 i, rc);
1803 rc = -ENOENT;
1804 goto free_cq_irqs;
1805 }
1806
1807 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1808 }
1809
1810 return 0;
1811
1812 free_cq_irqs:
1813 for (k = 0; k < i; k++) {
1814 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1815
1816 free_irq(pci_irq_vector(pdev, k+16), cq);
1817 }
1818 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
1819 free_chnl_interrupt:
1820 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1821 free_phy_irq:
1822 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1823 free_irq_vectors:
1824 pci_free_irq_vectors(pdev);
1825 return rc;
1826 }
1827
1828 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1829 {
1830 int rc;
1831
1832 rc = hw_init_v3_hw(hisi_hba);
1833 if (rc)
1834 return rc;
1835
1836 rc = interrupt_init_v3_hw(hisi_hba);
1837 if (rc)
1838 return rc;
1839
1840 return 0;
1841 }
1842
1843 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
1844 struct sas_phy_linkrates *r)
1845 {
1846 u32 prog_phy_link_rate =
1847 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1848 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1849 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1850 int i;
1851 enum sas_linkrate min, max;
1852 u32 rate_mask = 0;
1853
1854 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1855 max = sas_phy->phy->maximum_linkrate;
1856 min = r->minimum_linkrate;
1857 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1858 max = r->maximum_linkrate;
1859 min = sas_phy->phy->minimum_linkrate;
1860 } else
1861 return;
1862
1863 sas_phy->phy->maximum_linkrate = max;
1864 sas_phy->phy->minimum_linkrate = min;
1865
1866 min -= SAS_LINK_RATE_1_5_GBPS;
1867 max -= SAS_LINK_RATE_1_5_GBPS;
1868
1869 for (i = 0; i <= max; i++)
1870 rate_mask |= 1 << (i * 2);
1871
1872 prog_phy_link_rate &= ~0xff;
1873 prog_phy_link_rate |= rate_mask;
1874
1875 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1876 prog_phy_link_rate);
1877
1878 phy_hard_reset_v3_hw(hisi_hba, phy_no);
1879 }
1880
1881 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
1882 {
1883 struct pci_dev *pdev = hisi_hba->pci_dev;
1884 int i;
1885
1886 synchronize_irq(pci_irq_vector(pdev, 1));
1887 synchronize_irq(pci_irq_vector(pdev, 2));
1888 synchronize_irq(pci_irq_vector(pdev, 11));
1889 for (i = 0; i < hisi_hba->queue_count; i++) {
1890 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
1891 synchronize_irq(pci_irq_vector(pdev, i + 16));
1892 }
1893
1894 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
1895 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
1896 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
1897 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1898
1899 for (i = 0; i < hisi_hba->n_phy; i++) {
1900 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1901 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
1902 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
1903 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
1904 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
1905 }
1906 }
1907
1908 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
1909 {
1910 return hisi_sas_read32(hisi_hba, PHY_STATE);
1911 }
1912
1913 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1914 {
1915 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1916 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1917 struct sas_phy *sphy = sas_phy->phy;
1918 u32 reg_value;
1919
1920 /* loss dword sync */
1921 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1922 sphy->loss_of_dword_sync_count += reg_value;
1923
1924 /* phy reset problem */
1925 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1926 sphy->phy_reset_problem_count += reg_value;
1927
1928 /* invalid dword */
1929 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1930 sphy->invalid_dword_count += reg_value;
1931
1932 /* disparity err */
1933 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1934 sphy->running_disparity_error_count += reg_value;
1935
1936 }
1937
1938 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
1939 {
1940 struct device *dev = hisi_hba->dev;
1941 int rc;
1942 u32 status;
1943
1944 interrupt_disable_v3_hw(hisi_hba);
1945 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
1946 hisi_sas_kill_tasklets(hisi_hba);
1947
1948 hisi_sas_stop_phys(hisi_hba);
1949
1950 mdelay(10);
1951
1952 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
1953
1954 /* wait until bus idle */
1955 rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
1956 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
1957 if (rc) {
1958 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
1959 return rc;
1960 }
1961
1962 hisi_sas_init_mem(hisi_hba);
1963
1964 return hw_init_v3_hw(hisi_hba);
1965 }
1966
1967 static const struct hisi_sas_hw hisi_sas_v3_hw = {
1968 .hw_init = hisi_sas_v3_init,
1969 .setup_itct = setup_itct_v3_hw,
1970 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
1971 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
1972 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
1973 .clear_itct = clear_itct_v3_hw,
1974 .sl_notify = sl_notify_v3_hw,
1975 .prep_ssp = prep_ssp_v3_hw,
1976 .prep_smp = prep_smp_v3_hw,
1977 .prep_stp = prep_ata_v3_hw,
1978 .prep_abort = prep_abort_v3_hw,
1979 .get_free_slot = get_free_slot_v3_hw,
1980 .start_delivery = start_delivery_v3_hw,
1981 .slot_complete = slot_complete_v3_hw,
1982 .phys_init = phys_init_v3_hw,
1983 .phy_start = start_phy_v3_hw,
1984 .phy_disable = disable_phy_v3_hw,
1985 .phy_hard_reset = phy_hard_reset_v3_hw,
1986 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
1987 .phy_set_linkrate = phy_set_linkrate_v3_hw,
1988 .dereg_device = dereg_device_v3_hw,
1989 .soft_reset = soft_reset_v3_hw,
1990 .get_phys_state = get_phys_state_v3_hw,
1991 .get_events = phy_get_events_v3_hw,
1992 };
1993
1994 static struct Scsi_Host *
1995 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
1996 {
1997 struct Scsi_Host *shost;
1998 struct hisi_hba *hisi_hba;
1999 struct device *dev = &pdev->dev;
2000
2001 shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
2002 if (!shost) {
2003 dev_err(dev, "shost alloc failed\n");
2004 return NULL;
2005 }
2006 hisi_hba = shost_priv(shost);
2007
2008 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
2009 hisi_hba->hw = &hisi_sas_v3_hw;
2010 hisi_hba->pci_dev = pdev;
2011 hisi_hba->dev = dev;
2012 hisi_hba->shost = shost;
2013 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
2014
2015 timer_setup(&hisi_hba->timer, NULL, 0);
2016
2017 if (hisi_sas_get_fw_info(hisi_hba) < 0)
2018 goto err_out;
2019
2020 if (hisi_sas_alloc(hisi_hba, shost)) {
2021 hisi_sas_free(hisi_hba);
2022 goto err_out;
2023 }
2024
2025 return shost;
2026 err_out:
2027 scsi_host_put(shost);
2028 dev_err(dev, "shost alloc failed\n");
2029 return NULL;
2030 }
2031
2032 static int
2033 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2034 {
2035 struct Scsi_Host *shost;
2036 struct hisi_hba *hisi_hba;
2037 struct device *dev = &pdev->dev;
2038 struct asd_sas_phy **arr_phy;
2039 struct asd_sas_port **arr_port;
2040 struct sas_ha_struct *sha;
2041 int rc, phy_nr, port_nr, i;
2042
2043 rc = pci_enable_device(pdev);
2044 if (rc)
2045 goto err_out;
2046
2047 pci_set_master(pdev);
2048
2049 rc = pci_request_regions(pdev, DRV_NAME);
2050 if (rc)
2051 goto err_out_disable_device;
2052
2053 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
2054 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
2055 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2056 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2057 dev_err(dev, "No usable DMA addressing method\n");
2058 rc = -EIO;
2059 goto err_out_regions;
2060 }
2061 }
2062
2063 shost = hisi_sas_shost_alloc_pci(pdev);
2064 if (!shost) {
2065 rc = -ENOMEM;
2066 goto err_out_regions;
2067 }
2068
2069 sha = SHOST_TO_SAS_HA(shost);
2070 hisi_hba = shost_priv(shost);
2071 dev_set_drvdata(dev, sha);
2072
2073 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
2074 if (!hisi_hba->regs) {
2075 dev_err(dev, "cannot map register.\n");
2076 rc = -ENOMEM;
2077 goto err_out_ha;
2078 }
2079
2080 phy_nr = port_nr = hisi_hba->n_phy;
2081
2082 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
2083 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
2084 if (!arr_phy || !arr_port) {
2085 rc = -ENOMEM;
2086 goto err_out_ha;
2087 }
2088
2089 sha->sas_phy = arr_phy;
2090 sha->sas_port = arr_port;
2091 sha->core.shost = shost;
2092 sha->lldd_ha = hisi_hba;
2093
2094 shost->transportt = hisi_sas_stt;
2095 shost->max_id = HISI_SAS_MAX_DEVICES;
2096 shost->max_lun = ~0;
2097 shost->max_channel = 1;
2098 shost->max_cmd_len = 16;
2099 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
2100 shost->can_queue = hisi_hba->hw->max_command_entries;
2101 shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
2102
2103 sha->sas_ha_name = DRV_NAME;
2104 sha->dev = dev;
2105 sha->lldd_module = THIS_MODULE;
2106 sha->sas_addr = &hisi_hba->sas_addr[0];
2107 sha->num_phys = hisi_hba->n_phy;
2108 sha->core.shost = hisi_hba->shost;
2109
2110 for (i = 0; i < hisi_hba->n_phy; i++) {
2111 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
2112 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
2113 }
2114
2115 hisi_sas_init_add(hisi_hba);
2116
2117 rc = scsi_add_host(shost, dev);
2118 if (rc)
2119 goto err_out_ha;
2120
2121 rc = sas_register_ha(sha);
2122 if (rc)
2123 goto err_out_register_ha;
2124
2125 rc = hisi_hba->hw->hw_init(hisi_hba);
2126 if (rc)
2127 goto err_out_register_ha;
2128
2129 scsi_scan_host(shost);
2130
2131 return 0;
2132
2133 err_out_register_ha:
2134 scsi_remove_host(shost);
2135 err_out_ha:
2136 scsi_host_put(shost);
2137 err_out_regions:
2138 pci_release_regions(pdev);
2139 err_out_disable_device:
2140 pci_disable_device(pdev);
2141 err_out:
2142 return rc;
2143 }
2144
2145 static void
2146 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
2147 {
2148 int i;
2149
2150 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2151 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2152 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2153 for (i = 0; i < hisi_hba->queue_count; i++) {
2154 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2155
2156 free_irq(pci_irq_vector(pdev, i+16), cq);
2157 }
2158 pci_free_irq_vectors(pdev);
2159 }
2160
2161 static void hisi_sas_v3_remove(struct pci_dev *pdev)
2162 {
2163 struct device *dev = &pdev->dev;
2164 struct sas_ha_struct *sha = dev_get_drvdata(dev);
2165 struct hisi_hba *hisi_hba = sha->lldd_ha;
2166 struct Scsi_Host *shost = sha->core.shost;
2167
2168 sas_unregister_ha(sha);
2169 sas_remove_host(sha->core.shost);
2170
2171 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
2172 hisi_sas_kill_tasklets(hisi_hba);
2173 pci_release_regions(pdev);
2174 pci_disable_device(pdev);
2175 hisi_sas_free(hisi_hba);
2176 scsi_host_put(shost);
2177 }
2178
2179 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = {
2180 { .irq_msk = BIT(19), .msg = "HILINK_INT" },
2181 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" },
2182 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" },
2183 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" },
2184 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" },
2185 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" },
2186 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" },
2187 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" },
2188 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" },
2189 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" },
2190 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" },
2191 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" },
2192 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" },
2193 };
2194
2195 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = {
2196 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" },
2197 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" },
2198 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" },
2199 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" },
2200 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" },
2201 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" },
2202 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" },
2203 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" },
2204 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" },
2205 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" },
2206 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" },
2207 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" },
2208 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" },
2209 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" },
2210 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" },
2211 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" },
2212 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" },
2213 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" },
2214 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" },
2215 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" },
2216 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" },
2217 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" },
2218 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" },
2219 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" },
2220 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" },
2221 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" },
2222 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" },
2223 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" },
2224 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" },
2225 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" },
2226 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" },
2227 };
2228
2229 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba)
2230 {
2231 struct device *dev = hisi_hba->dev;
2232 const struct hisi_sas_hw_error *ras_error;
2233 bool need_reset = false;
2234 u32 irq_value;
2235 int i;
2236
2237 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0);
2238 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) {
2239 ras_error = &sas_ras_intr0_nfe[i];
2240 if (ras_error->irq_msk & irq_value) {
2241 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n",
2242 ras_error->msg, irq_value);
2243 need_reset = true;
2244 }
2245 }
2246 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value);
2247
2248 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1);
2249 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) {
2250 ras_error = &sas_ras_intr1_nfe[i];
2251 if (ras_error->irq_msk & irq_value) {
2252 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n",
2253 ras_error->msg, irq_value);
2254 need_reset = true;
2255 }
2256 }
2257 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value);
2258
2259 return need_reset;
2260 }
2261
2262 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev,
2263 pci_channel_state_t state)
2264 {
2265 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2266 struct hisi_hba *hisi_hba = sha->lldd_ha;
2267 struct device *dev = hisi_hba->dev;
2268
2269 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state);
2270 if (state == pci_channel_io_perm_failure)
2271 return PCI_ERS_RESULT_DISCONNECT;
2272
2273 if (process_non_fatal_error_v3_hw(hisi_hba))
2274 return PCI_ERS_RESULT_NEED_RESET;
2275
2276 return PCI_ERS_RESULT_CAN_RECOVER;
2277 }
2278
2279 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev)
2280 {
2281 return PCI_ERS_RESULT_RECOVERED;
2282 }
2283
2284 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev)
2285 {
2286 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2287 struct hisi_hba *hisi_hba = sha->lldd_ha;
2288 struct device *dev = hisi_hba->dev;
2289 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r);
2290
2291 dev_info(dev, "PCI error: slot reset callback!!\n");
2292 queue_work(hisi_hba->wq, &r.work);
2293 wait_for_completion(r.completion);
2294 if (r.done)
2295 return PCI_ERS_RESULT_RECOVERED;
2296
2297 return PCI_ERS_RESULT_DISCONNECT;
2298 }
2299
2300 enum {
2301 /* instances of the controller */
2302 hip08,
2303 };
2304
2305 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state)
2306 {
2307 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2308 struct hisi_hba *hisi_hba = sha->lldd_ha;
2309 struct device *dev = hisi_hba->dev;
2310 struct Scsi_Host *shost = hisi_hba->shost;
2311 u32 device_state, status;
2312 int rc;
2313 u32 reg_val;
2314 unsigned long flags;
2315
2316 if (!pdev->pm_cap) {
2317 dev_err(dev, "PCI PM not supported\n");
2318 return -ENODEV;
2319 }
2320
2321 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2322 scsi_block_requests(shost);
2323 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2324 flush_workqueue(hisi_hba->wq);
2325 /* disable DQ/PHY/bus */
2326 interrupt_disable_v3_hw(hisi_hba);
2327 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2328 hisi_sas_kill_tasklets(hisi_hba);
2329
2330 hisi_sas_stop_phys(hisi_hba);
2331
2332 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2333 AM_CTRL_GLOBAL);
2334 reg_val |= 0x1;
2335 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2336 AM_CTRL_GLOBAL, reg_val);
2337
2338 /* wait until bus idle */
2339 rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
2340 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
2341 if (rc) {
2342 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
2343 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2344 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2345 scsi_unblock_requests(shost);
2346 return rc;
2347 }
2348
2349 hisi_sas_init_mem(hisi_hba);
2350
2351 device_state = pci_choose_state(pdev, state);
2352 dev_warn(dev, "entering operating state [D%d]\n",
2353 device_state);
2354 pci_save_state(pdev);
2355 pci_disable_device(pdev);
2356 pci_set_power_state(pdev, device_state);
2357
2358 spin_lock_irqsave(&hisi_hba->lock, flags);
2359 hisi_sas_release_tasks(hisi_hba);
2360 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2361
2362 sas_suspend_ha(sha);
2363 return 0;
2364 }
2365
2366 static int hisi_sas_v3_resume(struct pci_dev *pdev)
2367 {
2368 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2369 struct hisi_hba *hisi_hba = sha->lldd_ha;
2370 struct Scsi_Host *shost = hisi_hba->shost;
2371 struct device *dev = hisi_hba->dev;
2372 unsigned int rc;
2373 u32 device_state = pdev->current_state;
2374
2375 dev_warn(dev, "resuming from operating state [D%d]\n",
2376 device_state);
2377 pci_set_power_state(pdev, PCI_D0);
2378 pci_enable_wake(pdev, PCI_D0, 0);
2379 pci_restore_state(pdev);
2380 rc = pci_enable_device(pdev);
2381 if (rc)
2382 dev_err(dev, "enable device failed during resume (%d)\n", rc);
2383
2384 pci_set_master(pdev);
2385 scsi_unblock_requests(shost);
2386 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2387
2388 sas_prep_resume_ha(sha);
2389 init_reg_v3_hw(hisi_hba);
2390 hisi_hba->hw->phys_init(hisi_hba);
2391 sas_resume_ha(sha);
2392 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2393
2394 return 0;
2395 }
2396
2397 static const struct pci_device_id sas_v3_pci_table[] = {
2398 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
2399 {}
2400 };
2401 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
2402
2403 static const struct pci_error_handlers hisi_sas_err_handler = {
2404 .error_detected = hisi_sas_error_detected_v3_hw,
2405 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw,
2406 .slot_reset = hisi_sas_slot_reset_v3_hw,
2407 };
2408
2409 static struct pci_driver sas_v3_pci_driver = {
2410 .name = DRV_NAME,
2411 .id_table = sas_v3_pci_table,
2412 .probe = hisi_sas_v3_probe,
2413 .remove = hisi_sas_v3_remove,
2414 .suspend = hisi_sas_v3_suspend,
2415 .resume = hisi_sas_v3_resume,
2416 .err_handler = &hisi_sas_err_handler,
2417 };
2418
2419 module_pci_driver(sas_v3_pci_driver);
2420
2421 MODULE_LICENSE("GPL");
2422 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2423 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2424 MODULE_ALIAS("pci:" DRV_NAME);
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