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scsi: hisi_sas: Create a scsi_host_template per HW module
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v3_hw.c
1 /*
2 * Copyright (c) 2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 #include "hisi_sas.h"
12 #define DRV_NAME "hisi_sas_v3_hw"
13
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
26 #define ITCT_CLR 0x44
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CFG_1US_TIMER_TRSH 0xcc
55 #define CHNL_INT_STATUS 0x148
56 #define HGC_AXI_FIFO_ERR_INFO 0x154
57 #define AXI_ERR_INFO_OFF 0
58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
59 #define FIFO_ERR_INFO_OFF 8
60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
61 #define INT_COAL_EN 0x19c
62 #define OQ_INT_COAL_TIME 0x1a0
63 #define OQ_INT_COAL_CNT 0x1a4
64 #define ENT_INT_COAL_TIME 0x1a8
65 #define ENT_INT_COAL_CNT 0x1ac
66 #define OQ_INT_SRC 0x1b0
67 #define OQ_INT_SRC_MSK 0x1b4
68 #define ENT_INT_SRC1 0x1b8
69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
73 #define ENT_INT_SRC2 0x1bc
74 #define ENT_INT_SRC3 0x1c0
75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
78 #define ENT_INT_SRC3_AXI_OFF 11
79 #define ENT_INT_SRC3_FIFO_OFF 12
80 #define ENT_INT_SRC3_LM_OFF 14
81 #define ENT_INT_SRC3_ITC_INT_OFF 15
82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
83 #define ENT_INT_SRC3_ABT_OFF 16
84 #define ENT_INT_SRC_MSK1 0x1c4
85 #define ENT_INT_SRC_MSK2 0x1c8
86 #define ENT_INT_SRC_MSK3 0x1cc
87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
89 #define CHNL_ENT_INT_MSK 0x1d4
90 #define HGC_COM_INT_MSK 0x1d8
91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
92 #define SAS_ECC_INTR 0x1e8
93 #define SAS_ECC_INTR_MSK 0x1ec
94 #define HGC_ERR_STAT_EN 0x238
95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
97 #define DLVRY_Q_0_DEPTH 0x268
98 #define DLVRY_Q_0_WR_PTR 0x26c
99 #define DLVRY_Q_0_RD_PTR 0x270
100 #define HYPER_STREAM_ID_EN_CFG 0xc80
101 #define OQ0_INT_SRC_MSK 0xc90
102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
104 #define COMPL_Q_0_DEPTH 0x4e8
105 #define COMPL_Q_0_WR_PTR 0x4ec
106 #define COMPL_Q_0_RD_PTR 0x4f0
107 #define AWQOS_AWCACHE_CFG 0xc84
108 #define ARQOS_ARCACHE_CFG 0xc88
109 #define HILINK_ERR_DFX 0xe04
110 #define SAS_GPIO_CFG_0 0x1000
111 #define SAS_GPIO_CFG_1 0x1004
112 #define SAS_GPIO_TX_0_1 0x1040
113 #define SAS_CFG_DRIVE_VLD 0x1070
114
115 /* phy registers requiring init */
116 #define PORT_BASE (0x2000)
117 #define PHY_CFG (PORT_BASE + 0x0)
118 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
119 #define PHY_CFG_ENA_OFF 0
120 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
121 #define PHY_CFG_DC_OPT_OFF 2
122 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
123 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
124 #define PHY_CTRL (PORT_BASE + 0x14)
125 #define PHY_CTRL_RESET_OFF 0
126 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
127 #define SL_CFG (PORT_BASE + 0x84)
128 #define SL_CONTROL (PORT_BASE + 0x94)
129 #define SL_CONTROL_NOTIFY_EN_OFF 0
130 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
131 #define SL_CTA_OFF 17
132 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
133 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
134 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
135 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
136 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
137 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
138 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
139 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
140 #define TXID_AUTO (PORT_BASE + 0xb8)
141 #define CT3_OFF 1
142 #define CT3_MSK (0x1 << CT3_OFF)
143 #define TX_HARDRST_OFF 2
144 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
145 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
146 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
147 #define STP_LINK_TIMER (PORT_BASE + 0x120)
148 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
149 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
150 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
151 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
152 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
153 #define CHL_INT0 (PORT_BASE + 0x1b4)
154 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
155 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
156 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
157 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
158 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
159 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
160 #define CHL_INT0_NOT_RDY_OFF 4
161 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
162 #define CHL_INT0_PHY_RDY_OFF 5
163 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
164 #define CHL_INT1 (PORT_BASE + 0x1b8)
165 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
166 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
167 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
168 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
169 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
170 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
171 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
172 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
173 #define CHL_INT2 (PORT_BASE + 0x1bc)
174 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
175 #define CHL_INT2_RX_INVLD_DW_OFF 30
176 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
177 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
178 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
179 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
180 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
181 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
182 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
183 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
184 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
185 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
186 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
187 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
188 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
189 #define DMA_TX_STATUS_BUSY_OFF 0
190 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
191 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
192 #define DMA_RX_STATUS_BUSY_OFF 0
193 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
194
195 #define COARSETUNE_TIME (PORT_BASE + 0x304)
196 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
197 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
198 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
199 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
200
201 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
202 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
203 #error Max ITCT exceeded
204 #endif
205
206 #define AXI_MASTER_CFG_BASE (0x5000)
207 #define AM_CTRL_GLOBAL (0x0)
208 #define AM_CURR_TRANS_RETURN (0x150)
209
210 #define AM_CFG_MAX_TRANS (0x5010)
211 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
212 #define AXI_CFG (0x5100)
213 #define AM_ROB_ECC_ERR_ADDR (0x510c)
214 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
215 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
216 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
217 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
218
219 /* RAS registers need init */
220 #define RAS_BASE (0x6000)
221 #define SAS_RAS_INTR0 (RAS_BASE)
222 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
223 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
224 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
225 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c)
226 #define SAS_RAS_INTR2 (RAS_BASE + 0x20)
227 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24)
228
229 /* HW dma structures */
230 /* Delivery queue header */
231 /* dw0 */
232 #define CMD_HDR_ABORT_FLAG_OFF 0
233 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
234 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
235 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
236 #define CMD_HDR_RESP_REPORT_OFF 5
237 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
238 #define CMD_HDR_TLR_CTRL_OFF 6
239 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
240 #define CMD_HDR_PORT_OFF 18
241 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
242 #define CMD_HDR_PRIORITY_OFF 27
243 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
244 #define CMD_HDR_CMD_OFF 29
245 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
246 /* dw1 */
247 #define CMD_HDR_UNCON_CMD_OFF 3
248 #define CMD_HDR_DIR_OFF 5
249 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
250 #define CMD_HDR_RESET_OFF 7
251 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
252 #define CMD_HDR_VDTL_OFF 10
253 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
254 #define CMD_HDR_FRAME_TYPE_OFF 11
255 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
256 #define CMD_HDR_DEV_ID_OFF 16
257 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
258 /* dw2 */
259 #define CMD_HDR_CFL_OFF 0
260 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
261 #define CMD_HDR_NCQ_TAG_OFF 10
262 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
263 #define CMD_HDR_MRFL_OFF 15
264 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
265 #define CMD_HDR_SG_MOD_OFF 24
266 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
267 /* dw3 */
268 #define CMD_HDR_IPTT_OFF 0
269 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
270 /* dw6 */
271 #define CMD_HDR_DIF_SGL_LEN_OFF 0
272 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
273 #define CMD_HDR_DATA_SGL_LEN_OFF 16
274 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
275 /* dw7 */
276 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
277 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
278 #define CMD_HDR_ABORT_IPTT_OFF 16
279 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
280
281 /* Completion header */
282 /* dw0 */
283 #define CMPLT_HDR_CMPLT_OFF 0
284 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
285 #define CMPLT_HDR_ERROR_PHASE_OFF 2
286 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
287 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
288 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
289 #define CMPLT_HDR_ERX_OFF 12
290 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
291 #define CMPLT_HDR_ABORT_STAT_OFF 13
292 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
293 /* abort_stat */
294 #define STAT_IO_NOT_VALID 0x1
295 #define STAT_IO_NO_DEVICE 0x2
296 #define STAT_IO_COMPLETE 0x3
297 #define STAT_IO_ABORTED 0x4
298 /* dw1 */
299 #define CMPLT_HDR_IPTT_OFF 0
300 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
301 #define CMPLT_HDR_DEV_ID_OFF 16
302 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
303 /* dw3 */
304 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
305 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
306
307 /* ITCT header */
308 /* qw0 */
309 #define ITCT_HDR_DEV_TYPE_OFF 0
310 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
311 #define ITCT_HDR_VALID_OFF 2
312 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
313 #define ITCT_HDR_MCR_OFF 5
314 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
315 #define ITCT_HDR_VLN_OFF 9
316 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
317 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
318 #define ITCT_HDR_AWT_CONTINUE_OFF 25
319 #define ITCT_HDR_PORT_ID_OFF 28
320 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
321 /* qw2 */
322 #define ITCT_HDR_INLT_OFF 0
323 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
324 #define ITCT_HDR_RTOLT_OFF 48
325 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
326
327 struct hisi_sas_complete_v3_hdr {
328 __le32 dw0;
329 __le32 dw1;
330 __le32 act;
331 __le32 dw3;
332 };
333
334 struct hisi_sas_err_record_v3 {
335 /* dw0 */
336 __le32 trans_tx_fail_type;
337
338 /* dw1 */
339 __le32 trans_rx_fail_type;
340
341 /* dw2 */
342 __le16 dma_tx_err_type;
343 __le16 sipc_rx_err_type;
344
345 /* dw3 */
346 __le32 dma_rx_err_type;
347 };
348
349 #define RX_DATA_LEN_UNDERFLOW_OFF 6
350 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
351
352 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
353 #define HISI_SAS_MSI_COUNT_V3_HW 32
354
355 #define DIR_NO_DATA 0
356 #define DIR_TO_INI 1
357 #define DIR_TO_DEVICE 2
358 #define DIR_RESERVED 3
359
360 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
361 ((fis.command == ATA_CMD_READ_LOG_EXT) || \
362 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
363 ((fis.command == ATA_CMD_DEV_RESET) && \
364 ((fis.control & ATA_SRST) != 0)))
365
366 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
367 {
368 void __iomem *regs = hisi_hba->regs + off;
369
370 return readl(regs);
371 }
372
373 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
374 {
375 void __iomem *regs = hisi_hba->regs + off;
376
377 return readl_relaxed(regs);
378 }
379
380 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
381 {
382 void __iomem *regs = hisi_hba->regs + off;
383
384 writel(val, regs);
385 }
386
387 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
388 u32 off, u32 val)
389 {
390 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
391
392 writel(val, regs);
393 }
394
395 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
396 int phy_no, u32 off)
397 {
398 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
399
400 return readl(regs);
401 }
402
403 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \
404 timeout_us) \
405 ({ \
406 void __iomem *regs = hisi_hba->regs + off; \
407 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \
408 })
409
410 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \
411 timeout_us) \
412 ({ \
413 void __iomem *regs = hisi_hba->regs + off; \
414 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
415 })
416
417 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
418 {
419 struct pci_dev *pdev = hisi_hba->pci_dev;
420 int i;
421
422 /* Global registers init */
423 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
424 (u32)((1ULL << hisi_hba->queue_count) - 1));
425 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
426 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
427 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
428 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
429 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
430 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
431 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
432 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
433 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
434 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
435 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
436 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
437 if (pdev->revision >= 0x21)
438 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7fff);
439 else
440 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff);
441 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
442 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
443 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
444 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
445 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
446 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
447 for (i = 0; i < hisi_hba->queue_count; i++)
448 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
449
450 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
451
452 for (i = 0; i < hisi_hba->n_phy; i++) {
453 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
454 struct asd_sas_phy *sas_phy = &phy->sas_phy;
455 u32 prog_phy_link_rate = 0x800;
456
457 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
458 SAS_LINK_RATE_1_5_GBPS)) {
459 prog_phy_link_rate = 0x855;
460 } else {
461 enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
462
463 prog_phy_link_rate =
464 hisi_sas_get_prog_phy_linkrate_mask(max) |
465 0x800;
466 }
467 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
468 prog_phy_link_rate);
469 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
470 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
471 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
472 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
473 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
474 if (pdev->revision >= 0x21)
475 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
476 0xffffffff);
477 else
478 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
479 0xff87ffff);
480 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
481 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
482 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
483 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
484 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
485 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
486 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
487 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
488
489 /* used for 12G negotiate */
490 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
491 }
492
493 for (i = 0; i < hisi_hba->queue_count; i++) {
494 /* Delivery queue */
495 hisi_sas_write32(hisi_hba,
496 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
497 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
498
499 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
500 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
501
502 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
503 HISI_SAS_QUEUE_SLOTS);
504
505 /* Completion queue */
506 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
507 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
508
509 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
510 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
511
512 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
513 HISI_SAS_QUEUE_SLOTS);
514 }
515
516 /* itct */
517 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
518 lower_32_bits(hisi_hba->itct_dma));
519
520 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
521 upper_32_bits(hisi_hba->itct_dma));
522
523 /* iost */
524 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
525 lower_32_bits(hisi_hba->iost_dma));
526
527 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
528 upper_32_bits(hisi_hba->iost_dma));
529
530 /* breakpoint */
531 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
532 lower_32_bits(hisi_hba->breakpoint_dma));
533
534 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
535 upper_32_bits(hisi_hba->breakpoint_dma));
536
537 /* SATA broken msg */
538 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
539 lower_32_bits(hisi_hba->sata_breakpoint_dma));
540
541 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
542 upper_32_bits(hisi_hba->sata_breakpoint_dma));
543
544 /* SATA initial fis */
545 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
546 lower_32_bits(hisi_hba->initial_fis_dma));
547
548 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
549 upper_32_bits(hisi_hba->initial_fis_dma));
550
551 /* RAS registers init */
552 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
553 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
554 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
555 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
556
557 /* LED registers init */
558 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
559 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
560 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
561 /* Configure blink generator rate A to 1Hz and B to 4Hz */
562 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
563 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
564 }
565
566 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
567 {
568 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
569
570 cfg &= ~PHY_CFG_DC_OPT_MSK;
571 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
572 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
573 }
574
575 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
576 {
577 struct sas_identify_frame identify_frame;
578 u32 *identify_buffer;
579
580 memset(&identify_frame, 0, sizeof(identify_frame));
581 identify_frame.dev_type = SAS_END_DEVICE;
582 identify_frame.frame_type = 0;
583 identify_frame._un1 = 1;
584 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
585 identify_frame.target_bits = SAS_PROTOCOL_NONE;
586 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
587 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
588 identify_frame.phy_id = phy_no;
589 identify_buffer = (u32 *)(&identify_frame);
590
591 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
592 __swab32(identify_buffer[0]));
593 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
594 __swab32(identify_buffer[1]));
595 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
596 __swab32(identify_buffer[2]));
597 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
598 __swab32(identify_buffer[3]));
599 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
600 __swab32(identify_buffer[4]));
601 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
602 __swab32(identify_buffer[5]));
603 }
604
605 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
606 struct hisi_sas_device *sas_dev)
607 {
608 struct domain_device *device = sas_dev->sas_device;
609 struct device *dev = hisi_hba->dev;
610 u64 qw0, device_id = sas_dev->device_id;
611 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
612 struct domain_device *parent_dev = device->parent;
613 struct asd_sas_port *sas_port = device->port;
614 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
615
616 memset(itct, 0, sizeof(*itct));
617
618 /* qw0 */
619 qw0 = 0;
620 switch (sas_dev->dev_type) {
621 case SAS_END_DEVICE:
622 case SAS_EDGE_EXPANDER_DEVICE:
623 case SAS_FANOUT_EXPANDER_DEVICE:
624 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
625 break;
626 case SAS_SATA_DEV:
627 case SAS_SATA_PENDING:
628 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
629 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
630 else
631 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
632 break;
633 default:
634 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
635 sas_dev->dev_type);
636 }
637
638 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
639 (device->linkrate << ITCT_HDR_MCR_OFF) |
640 (1 << ITCT_HDR_VLN_OFF) |
641 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
642 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
643 (port->id << ITCT_HDR_PORT_ID_OFF));
644 itct->qw0 = cpu_to_le64(qw0);
645
646 /* qw1 */
647 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
648 itct->sas_addr = __swab64(itct->sas_addr);
649
650 /* qw2 */
651 if (!dev_is_sata(device))
652 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
653 (0x1ULL << ITCT_HDR_RTOLT_OFF));
654 }
655
656 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba,
657 struct hisi_sas_device *sas_dev)
658 {
659 DECLARE_COMPLETION_ONSTACK(completion);
660 u64 dev_id = sas_dev->device_id;
661 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
662 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
663
664 sas_dev->completion = &completion;
665
666 /* clear the itct interrupt state */
667 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
668 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
669 ENT_INT_SRC3_ITC_INT_MSK);
670
671 /* clear the itct table*/
672 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
673 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
674
675 wait_for_completion(sas_dev->completion);
676 memset(itct, 0, sizeof(struct hisi_sas_itct));
677 }
678
679 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
680 struct domain_device *device)
681 {
682 struct hisi_sas_slot *slot, *slot2;
683 struct hisi_sas_device *sas_dev = device->lldd_dev;
684 u32 cfg_abt_set_query_iptt;
685
686 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
687 CFG_ABT_SET_QUERY_IPTT);
688 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
689 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
690 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
691 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
692 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
693 cfg_abt_set_query_iptt);
694 }
695 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
696 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
697 cfg_abt_set_query_iptt);
698 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
699 1 << CFG_ABT_SET_IPTT_DONE_OFF);
700 }
701
702 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
703 {
704 struct device *dev = hisi_hba->dev;
705 int ret;
706 u32 val;
707
708 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
709
710 /* Disable all of the PHYs */
711 hisi_sas_stop_phys(hisi_hba);
712 udelay(50);
713
714 /* Ensure axi bus idle */
715 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
716 20000, 1000000);
717 if (ret) {
718 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
719 return -EIO;
720 }
721
722 if (ACPI_HANDLE(dev)) {
723 acpi_status s;
724
725 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
726 if (ACPI_FAILURE(s)) {
727 dev_err(dev, "Reset failed\n");
728 return -EIO;
729 }
730 } else {
731 dev_err(dev, "no reset method!\n");
732 return -EINVAL;
733 }
734
735 return 0;
736 }
737
738 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
739 {
740 struct device *dev = hisi_hba->dev;
741 int rc;
742
743 rc = reset_hw_v3_hw(hisi_hba);
744 if (rc) {
745 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
746 return rc;
747 }
748
749 msleep(100);
750 init_reg_v3_hw(hisi_hba);
751
752 return 0;
753 }
754
755 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
756 {
757 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
758
759 cfg |= PHY_CFG_ENA_MSK;
760 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
761 }
762
763 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
764 {
765 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
766
767 cfg &= ~PHY_CFG_ENA_MSK;
768 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
769 }
770
771 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
772 {
773 config_id_frame_v3_hw(hisi_hba, phy_no);
774 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
775 enable_phy_v3_hw(hisi_hba, phy_no);
776 }
777
778 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
779 {
780 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
781 u32 txid_auto;
782
783 disable_phy_v3_hw(hisi_hba, phy_no);
784 if (phy->identify.device_type == SAS_END_DEVICE) {
785 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
786 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
787 txid_auto | TX_HARDRST_MSK);
788 }
789 msleep(100);
790 start_phy_v3_hw(hisi_hba, phy_no);
791 }
792
793 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
794 {
795 return SAS_LINK_RATE_12_0_GBPS;
796 }
797
798 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
799 {
800 int i;
801
802 for (i = 0; i < hisi_hba->n_phy; i++) {
803 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
804 struct asd_sas_phy *sas_phy = &phy->sas_phy;
805
806 if (!sas_phy->phy->enabled)
807 continue;
808
809 start_phy_v3_hw(hisi_hba, i);
810 }
811 }
812
813 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
814 {
815 u32 sl_control;
816
817 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
818 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
819 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
820 msleep(1);
821 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
822 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
823 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
824 }
825
826 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
827 {
828 int i, bitmap = 0;
829 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
830 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
831
832 for (i = 0; i < hisi_hba->n_phy; i++)
833 if (phy_state & BIT(i))
834 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
835 bitmap |= BIT(i);
836
837 return bitmap;
838 }
839
840 /**
841 * The callpath to this function and upto writing the write
842 * queue pointer should be safe from interruption.
843 */
844 static int
845 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
846 {
847 struct device *dev = hisi_hba->dev;
848 int queue = dq->id;
849 u32 r, w;
850
851 w = dq->wr_point;
852 r = hisi_sas_read32_relaxed(hisi_hba,
853 DLVRY_Q_0_RD_PTR + (queue * 0x14));
854 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
855 dev_warn(dev, "full queue=%d r=%d w=%d\n",
856 queue, r, w);
857 return -EAGAIN;
858 }
859
860 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
861
862 return w;
863 }
864
865 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
866 {
867 struct hisi_hba *hisi_hba = dq->hisi_hba;
868 struct hisi_sas_slot *s, *s1;
869 struct list_head *dq_list;
870 int dlvry_queue = dq->id;
871 int wp, count = 0;
872
873 dq_list = &dq->list;
874 list_for_each_entry_safe(s, s1, &dq->list, delivery) {
875 if (!s->ready)
876 break;
877 count++;
878 wp = (s->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
879 list_del(&s->delivery);
880 }
881
882 if (!count)
883 return;
884
885 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
886 }
887
888 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
889 struct hisi_sas_slot *slot,
890 struct hisi_sas_cmd_hdr *hdr,
891 struct scatterlist *scatter,
892 int n_elem)
893 {
894 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
895 struct scatterlist *sg;
896 int i;
897
898 for_each_sg(scatter, sg, n_elem, i) {
899 struct hisi_sas_sge *entry = &sge_page->sge[i];
900
901 entry->addr = cpu_to_le64(sg_dma_address(sg));
902 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
903 entry->data_len = cpu_to_le32(sg_dma_len(sg));
904 entry->data_off = 0;
905 }
906
907 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
908
909 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
910 }
911
912 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
913 struct hisi_sas_slot *slot, int is_tmf,
914 struct hisi_sas_tmf_task *tmf)
915 {
916 struct sas_task *task = slot->task;
917 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
918 struct domain_device *device = task->dev;
919 struct hisi_sas_device *sas_dev = device->lldd_dev;
920 struct hisi_sas_port *port = slot->port;
921 struct sas_ssp_task *ssp_task = &task->ssp_task;
922 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
923 int has_data = 0, priority = is_tmf;
924 u8 *buf_cmd;
925 u32 dw1 = 0, dw2 = 0;
926
927 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
928 (2 << CMD_HDR_TLR_CTRL_OFF) |
929 (port->id << CMD_HDR_PORT_OFF) |
930 (priority << CMD_HDR_PRIORITY_OFF) |
931 (1 << CMD_HDR_CMD_OFF)); /* ssp */
932
933 dw1 = 1 << CMD_HDR_VDTL_OFF;
934 if (is_tmf) {
935 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
936 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
937 } else {
938 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
939 switch (scsi_cmnd->sc_data_direction) {
940 case DMA_TO_DEVICE:
941 has_data = 1;
942 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
943 break;
944 case DMA_FROM_DEVICE:
945 has_data = 1;
946 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
947 break;
948 default:
949 dw1 &= ~CMD_HDR_DIR_MSK;
950 }
951 }
952
953 /* map itct entry */
954 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
955 hdr->dw1 = cpu_to_le32(dw1);
956
957 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
958 + 3) / 4) << CMD_HDR_CFL_OFF) |
959 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
960 (2 << CMD_HDR_SG_MOD_OFF);
961 hdr->dw2 = cpu_to_le32(dw2);
962 hdr->transfer_tags = cpu_to_le32(slot->idx);
963
964 if (has_data)
965 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
966 slot->n_elem);
967
968 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
969 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
970 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
971
972 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
973 sizeof(struct ssp_frame_hdr);
974
975 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
976 if (!is_tmf) {
977 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
978 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
979 } else {
980 buf_cmd[10] = tmf->tmf;
981 switch (tmf->tmf) {
982 case TMF_ABORT_TASK:
983 case TMF_QUERY_TASK:
984 buf_cmd[12] =
985 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
986 buf_cmd[13] =
987 tmf->tag_of_task_to_be_managed & 0xff;
988 break;
989 default:
990 break;
991 }
992 }
993 }
994
995 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
996 struct hisi_sas_slot *slot)
997 {
998 struct sas_task *task = slot->task;
999 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1000 struct domain_device *device = task->dev;
1001 struct hisi_sas_port *port = slot->port;
1002 struct scatterlist *sg_req;
1003 struct hisi_sas_device *sas_dev = device->lldd_dev;
1004 dma_addr_t req_dma_addr;
1005 unsigned int req_len;
1006
1007 /* req */
1008 sg_req = &task->smp_task.smp_req;
1009 req_len = sg_dma_len(sg_req);
1010 req_dma_addr = sg_dma_address(sg_req);
1011
1012 /* create header */
1013 /* dw0 */
1014 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1015 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1016 (2 << CMD_HDR_CMD_OFF)); /* smp */
1017
1018 /* map itct entry */
1019 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1020 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1021 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1022
1023 /* dw2 */
1024 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1025 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1026 CMD_HDR_MRFL_OFF));
1027
1028 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1029
1030 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1031 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1032
1033 }
1034
1035 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1036 struct hisi_sas_slot *slot)
1037 {
1038 struct sas_task *task = slot->task;
1039 struct domain_device *device = task->dev;
1040 struct domain_device *parent_dev = device->parent;
1041 struct hisi_sas_device *sas_dev = device->lldd_dev;
1042 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1043 struct asd_sas_port *sas_port = device->port;
1044 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1045 u8 *buf_cmd;
1046 int has_data = 0, hdr_tag = 0;
1047 u32 dw1 = 0, dw2 = 0;
1048
1049 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1050 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1051 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1052 else
1053 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1054
1055 switch (task->data_dir) {
1056 case DMA_TO_DEVICE:
1057 has_data = 1;
1058 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1059 break;
1060 case DMA_FROM_DEVICE:
1061 has_data = 1;
1062 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1063 break;
1064 default:
1065 dw1 &= ~CMD_HDR_DIR_MSK;
1066 }
1067
1068 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1069 (task->ata_task.fis.control & ATA_SRST))
1070 dw1 |= 1 << CMD_HDR_RESET_OFF;
1071
1072 dw1 |= (hisi_sas_get_ata_protocol(
1073 &task->ata_task.fis, task->data_dir))
1074 << CMD_HDR_FRAME_TYPE_OFF;
1075 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1076
1077 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1078 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1079
1080 hdr->dw1 = cpu_to_le32(dw1);
1081
1082 /* dw2 */
1083 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
1084 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1085 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1086 }
1087
1088 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1089 2 << CMD_HDR_SG_MOD_OFF;
1090 hdr->dw2 = cpu_to_le32(dw2);
1091
1092 /* dw3 */
1093 hdr->transfer_tags = cpu_to_le32(slot->idx);
1094
1095 if (has_data)
1096 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1097 slot->n_elem);
1098
1099 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1100 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1101 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1102
1103 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1104
1105 if (likely(!task->ata_task.device_control_reg_update))
1106 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1107 /* fill in command FIS */
1108 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1109 }
1110
1111 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1112 struct hisi_sas_slot *slot,
1113 int device_id, int abort_flag, int tag_to_abort)
1114 {
1115 struct sas_task *task = slot->task;
1116 struct domain_device *dev = task->dev;
1117 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1118 struct hisi_sas_port *port = slot->port;
1119
1120 /* dw0 */
1121 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1122 (port->id << CMD_HDR_PORT_OFF) |
1123 (dev_is_sata(dev)
1124 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1125 (abort_flag
1126 << CMD_HDR_ABORT_FLAG_OFF));
1127
1128 /* dw1 */
1129 hdr->dw1 = cpu_to_le32(device_id
1130 << CMD_HDR_DEV_ID_OFF);
1131
1132 /* dw7 */
1133 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1134 hdr->transfer_tags = cpu_to_le32(slot->idx);
1135
1136 }
1137
1138 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1139 {
1140 int i, res;
1141 u32 context, port_id, link_rate;
1142 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1143 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1144 struct device *dev = hisi_hba->dev;
1145
1146 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1147
1148 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1149 port_id = (port_id >> (4 * phy_no)) & 0xf;
1150 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1151 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1152
1153 if (port_id == 0xf) {
1154 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1155 res = IRQ_NONE;
1156 goto end;
1157 }
1158 sas_phy->linkrate = link_rate;
1159 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1160
1161 /* Check for SATA dev */
1162 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1163 if (context & (1 << phy_no)) {
1164 struct hisi_sas_initial_fis *initial_fis;
1165 struct dev_to_host_fis *fis;
1166 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1167
1168 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1169 initial_fis = &hisi_hba->initial_fis[phy_no];
1170 fis = &initial_fis->fis;
1171 sas_phy->oob_mode = SATA_OOB_MODE;
1172 attached_sas_addr[0] = 0x50;
1173 attached_sas_addr[7] = phy_no;
1174 memcpy(sas_phy->attached_sas_addr,
1175 attached_sas_addr,
1176 SAS_ADDR_SIZE);
1177 memcpy(sas_phy->frame_rcvd, fis,
1178 sizeof(struct dev_to_host_fis));
1179 phy->phy_type |= PORT_TYPE_SATA;
1180 phy->identify.device_type = SAS_SATA_DEV;
1181 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1182 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1183 } else {
1184 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1185 struct sas_identify_frame *id =
1186 (struct sas_identify_frame *)frame_rcvd;
1187
1188 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1189 for (i = 0; i < 6; i++) {
1190 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1191 RX_IDAF_DWORD0 + (i * 4));
1192 frame_rcvd[i] = __swab32(idaf);
1193 }
1194 sas_phy->oob_mode = SAS_OOB_MODE;
1195 memcpy(sas_phy->attached_sas_addr,
1196 &id->sas_addr,
1197 SAS_ADDR_SIZE);
1198 phy->phy_type |= PORT_TYPE_SAS;
1199 phy->identify.device_type = id->dev_type;
1200 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1201 if (phy->identify.device_type == SAS_END_DEVICE)
1202 phy->identify.target_port_protocols =
1203 SAS_PROTOCOL_SSP;
1204 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1205 phy->identify.target_port_protocols =
1206 SAS_PROTOCOL_SMP;
1207 }
1208
1209 phy->port_id = port_id;
1210 phy->phy_attached = 1;
1211 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1212 res = IRQ_HANDLED;
1213 end:
1214 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1215 CHL_INT0_SL_PHY_ENABLE_MSK);
1216 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1217
1218 return res;
1219 }
1220
1221 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1222 {
1223 u32 phy_state, sl_ctrl, txid_auto;
1224 struct device *dev = hisi_hba->dev;
1225
1226 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1227
1228 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1229 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1230 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1231
1232 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1233 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1234 sl_ctrl&(~SL_CTA_MSK));
1235
1236 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1237 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1238 txid_auto | CT3_MSK);
1239
1240 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1241 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1242
1243 return IRQ_HANDLED;
1244 }
1245
1246 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1247 {
1248 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1249 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1250 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1251
1252 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1253 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1254 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1255 CHL_INT0_SL_RX_BCST_ACK_MSK);
1256 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1257
1258 return IRQ_HANDLED;
1259 }
1260
1261 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1262 {
1263 struct hisi_hba *hisi_hba = p;
1264 u32 irq_msk;
1265 int phy_no = 0;
1266 irqreturn_t res = IRQ_NONE;
1267
1268 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1269 & 0x11111111;
1270 while (irq_msk) {
1271 if (irq_msk & 1) {
1272 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1273 CHL_INT0);
1274 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1275 int rdy = phy_state & (1 << phy_no);
1276
1277 if (rdy) {
1278 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1279 /* phy up */
1280 if (phy_up_v3_hw(phy_no, hisi_hba)
1281 == IRQ_HANDLED)
1282 res = IRQ_HANDLED;
1283 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1284 /* phy bcast */
1285 if (phy_bcast_v3_hw(phy_no, hisi_hba)
1286 == IRQ_HANDLED)
1287 res = IRQ_HANDLED;
1288 } else {
1289 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1290 /* phy down */
1291 if (phy_down_v3_hw(phy_no, hisi_hba)
1292 == IRQ_HANDLED)
1293 res = IRQ_HANDLED;
1294 }
1295 }
1296 irq_msk >>= 4;
1297 phy_no++;
1298 }
1299
1300 return res;
1301 }
1302
1303 static const struct hisi_sas_hw_error port_axi_error[] = {
1304 {
1305 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1306 .msg = "dma_tx_axi_wr_err",
1307 },
1308 {
1309 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1310 .msg = "dma_tx_axi_rd_err",
1311 },
1312 {
1313 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1314 .msg = "dma_rx_axi_wr_err",
1315 },
1316 {
1317 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1318 .msg = "dma_rx_axi_rd_err",
1319 },
1320 };
1321
1322 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1323 {
1324 struct hisi_hba *hisi_hba = p;
1325 struct device *dev = hisi_hba->dev;
1326 struct pci_dev *pci_dev = hisi_hba->pci_dev;
1327 u32 irq_msk;
1328 int phy_no = 0;
1329
1330 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1331 & 0xeeeeeeee;
1332
1333 while (irq_msk) {
1334 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1335 CHL_INT0);
1336 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1337 CHL_INT1);
1338 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1339 CHL_INT2);
1340 u32 irq_msk1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1341 CHL_INT1_MSK);
1342 u32 irq_msk2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1343 CHL_INT2_MSK);
1344
1345 irq_value1 &= ~irq_msk1;
1346 irq_value2 &= ~irq_msk2;
1347
1348 if ((irq_msk & (4 << (phy_no * 4))) &&
1349 irq_value1) {
1350 int i;
1351
1352 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1353 const struct hisi_sas_hw_error *error =
1354 &port_axi_error[i];
1355
1356 if (!(irq_value1 & error->irq_msk))
1357 continue;
1358
1359 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1360 error->msg, phy_no, irq_value1);
1361 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1362 }
1363
1364 hisi_sas_phy_write32(hisi_hba, phy_no,
1365 CHL_INT1, irq_value1);
1366 }
1367
1368 if (irq_msk & (8 << (phy_no * 4)) && irq_value2) {
1369 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1370
1371 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1372 dev_warn(dev, "phy%d identify timeout\n",
1373 phy_no);
1374 hisi_sas_notify_phy_event(phy,
1375 HISI_PHYE_LINK_RESET);
1376
1377 }
1378
1379 if (irq_value2 & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1380 u32 reg_value = hisi_sas_phy_read32(hisi_hba,
1381 phy_no, STP_LINK_TIMEOUT_STATE);
1382
1383 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1384 phy_no, reg_value);
1385 if (reg_value & BIT(4))
1386 hisi_sas_notify_phy_event(phy,
1387 HISI_PHYE_LINK_RESET);
1388 }
1389
1390 hisi_sas_phy_write32(hisi_hba, phy_no,
1391 CHL_INT2, irq_value2);
1392
1393 if ((irq_value2 & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1394 (pci_dev->revision == 0x20)) {
1395 u32 reg_value;
1396 int rc;
1397
1398 rc = hisi_sas_read32_poll_timeout_atomic(
1399 HILINK_ERR_DFX, reg_value,
1400 !((reg_value >> 8) & BIT(phy_no)),
1401 1000, 10000);
1402 if (rc) {
1403 disable_phy_v3_hw(hisi_hba, phy_no);
1404 hisi_sas_phy_write32(hisi_hba, phy_no,
1405 CHL_INT2,
1406 BIT(CHL_INT2_RX_INVLD_DW_OFF));
1407 hisi_sas_phy_read32(hisi_hba, phy_no,
1408 ERR_CNT_INVLD_DW);
1409 mdelay(1);
1410 enable_phy_v3_hw(hisi_hba, phy_no);
1411 }
1412 }
1413 }
1414
1415 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1416 hisi_sas_phy_write32(hisi_hba, phy_no,
1417 CHL_INT0, irq_value0
1418 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1419 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1420 & (~CHL_INT0_NOT_RDY_MSK));
1421 }
1422 irq_msk &= ~(0xe << (phy_no * 4));
1423 phy_no++;
1424 }
1425
1426 return IRQ_HANDLED;
1427 }
1428
1429 static const struct hisi_sas_hw_error axi_error[] = {
1430 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1431 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1432 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1433 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1434 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1435 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1436 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1437 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1438 {},
1439 };
1440
1441 static const struct hisi_sas_hw_error fifo_error[] = {
1442 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
1443 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
1444 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1445 { .msk = BIT(11), .msg = "CMDP_FIFO" },
1446 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1447 {},
1448 };
1449
1450 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1451 {
1452 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1453 .msg = "write pointer and depth",
1454 },
1455 {
1456 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
1457 .msg = "iptt no match slot",
1458 },
1459 {
1460 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
1461 .msg = "read pointer and depth",
1462 },
1463 {
1464 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
1465 .reg = HGC_AXI_FIFO_ERR_INFO,
1466 .sub = axi_error,
1467 },
1468 {
1469 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
1470 .reg = HGC_AXI_FIFO_ERR_INFO,
1471 .sub = fifo_error,
1472 },
1473 {
1474 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
1475 .msg = "LM add/fetch list",
1476 },
1477 {
1478 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
1479 .msg = "SAS_HGC_ABT fetch LM list",
1480 },
1481 };
1482
1483 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
1484 {
1485 u32 irq_value, irq_msk;
1486 struct hisi_hba *hisi_hba = p;
1487 struct device *dev = hisi_hba->dev;
1488 int i;
1489
1490 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1491 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
1492
1493 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
1494 irq_value &= ~irq_msk;
1495
1496 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
1497 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
1498
1499 if (!(irq_value & error->irq_msk))
1500 continue;
1501
1502 if (error->sub) {
1503 const struct hisi_sas_hw_error *sub = error->sub;
1504 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
1505
1506 for (; sub->msk || sub->msg; sub++) {
1507 if (!(err_value & sub->msk))
1508 continue;
1509
1510 dev_err(dev, "%s error (0x%x) found!\n",
1511 sub->msg, irq_value);
1512 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1513 }
1514 } else {
1515 dev_err(dev, "%s error (0x%x) found!\n",
1516 error->msg, irq_value);
1517 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1518 }
1519 }
1520
1521 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
1522 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
1523 u32 dev_id = reg_val & ITCT_DEV_MSK;
1524 struct hisi_sas_device *sas_dev =
1525 &hisi_hba->devices[dev_id];
1526
1527 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
1528 dev_dbg(dev, "clear ITCT ok\n");
1529 complete(sas_dev->completion);
1530 }
1531
1532 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
1533 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
1534
1535 return IRQ_HANDLED;
1536 }
1537
1538 static void
1539 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1540 struct hisi_sas_slot *slot)
1541 {
1542 struct task_status_struct *ts = &task->task_status;
1543 struct hisi_sas_complete_v3_hdr *complete_queue =
1544 hisi_hba->complete_hdr[slot->cmplt_queue];
1545 struct hisi_sas_complete_v3_hdr *complete_hdr =
1546 &complete_queue[slot->cmplt_queue_slot];
1547 struct hisi_sas_err_record_v3 *record =
1548 hisi_sas_status_buf_addr_mem(slot);
1549 u32 dma_rx_err_type = record->dma_rx_err_type;
1550 u32 trans_tx_fail_type = record->trans_tx_fail_type;
1551
1552 switch (task->task_proto) {
1553 case SAS_PROTOCOL_SSP:
1554 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1555 ts->residual = trans_tx_fail_type;
1556 ts->stat = SAS_DATA_UNDERRUN;
1557 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1558 ts->stat = SAS_QUEUE_FULL;
1559 slot->abort = 1;
1560 } else {
1561 ts->stat = SAS_OPEN_REJECT;
1562 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1563 }
1564 break;
1565 case SAS_PROTOCOL_SATA:
1566 case SAS_PROTOCOL_STP:
1567 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1568 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1569 ts->residual = trans_tx_fail_type;
1570 ts->stat = SAS_DATA_UNDERRUN;
1571 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1572 ts->stat = SAS_PHY_DOWN;
1573 slot->abort = 1;
1574 } else {
1575 ts->stat = SAS_OPEN_REJECT;
1576 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1577 }
1578 hisi_sas_sata_done(task, slot);
1579 break;
1580 case SAS_PROTOCOL_SMP:
1581 ts->stat = SAM_STAT_CHECK_CONDITION;
1582 break;
1583 default:
1584 break;
1585 }
1586 }
1587
1588 static int
1589 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1590 {
1591 struct sas_task *task = slot->task;
1592 struct hisi_sas_device *sas_dev;
1593 struct device *dev = hisi_hba->dev;
1594 struct task_status_struct *ts;
1595 struct domain_device *device;
1596 struct sas_ha_struct *ha;
1597 enum exec_status sts;
1598 struct hisi_sas_complete_v3_hdr *complete_queue =
1599 hisi_hba->complete_hdr[slot->cmplt_queue];
1600 struct hisi_sas_complete_v3_hdr *complete_hdr =
1601 &complete_queue[slot->cmplt_queue_slot];
1602 unsigned long flags;
1603 bool is_internal = slot->is_internal;
1604
1605 if (unlikely(!task || !task->lldd_task || !task->dev))
1606 return -EINVAL;
1607
1608 ts = &task->task_status;
1609 device = task->dev;
1610 ha = device->port->ha;
1611 sas_dev = device->lldd_dev;
1612
1613 spin_lock_irqsave(&task->task_state_lock, flags);
1614 task->task_state_flags &=
1615 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1616 spin_unlock_irqrestore(&task->task_state_lock, flags);
1617
1618 memset(ts, 0, sizeof(*ts));
1619 ts->resp = SAS_TASK_COMPLETE;
1620
1621 if (unlikely(!sas_dev)) {
1622 dev_dbg(dev, "slot complete: port has not device\n");
1623 ts->stat = SAS_PHY_DOWN;
1624 goto out;
1625 }
1626
1627 /*
1628 * Use SAS+TMF status codes
1629 */
1630 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1631 >> CMPLT_HDR_ABORT_STAT_OFF) {
1632 case STAT_IO_ABORTED:
1633 /* this IO has been aborted by abort command */
1634 ts->stat = SAS_ABORTED_TASK;
1635 goto out;
1636 case STAT_IO_COMPLETE:
1637 /* internal abort command complete */
1638 ts->stat = TMF_RESP_FUNC_SUCC;
1639 goto out;
1640 case STAT_IO_NO_DEVICE:
1641 ts->stat = TMF_RESP_FUNC_COMPLETE;
1642 goto out;
1643 case STAT_IO_NOT_VALID:
1644 /*
1645 * abort single IO, the controller can't find the IO
1646 */
1647 ts->stat = TMF_RESP_FUNC_FAILED;
1648 goto out;
1649 default:
1650 break;
1651 }
1652
1653 /* check for erroneous completion */
1654 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1655 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
1656
1657 slot_err_v3_hw(hisi_hba, task, slot);
1658 if (ts->stat != SAS_DATA_UNDERRUN)
1659 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
1660 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
1661 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
1662 slot->idx, task, sas_dev->device_id,
1663 complete_hdr->dw0, complete_hdr->dw1,
1664 complete_hdr->act, complete_hdr->dw3,
1665 error_info[0], error_info[1],
1666 error_info[2], error_info[3]);
1667 if (unlikely(slot->abort))
1668 return ts->stat;
1669 goto out;
1670 }
1671
1672 switch (task->task_proto) {
1673 case SAS_PROTOCOL_SSP: {
1674 struct ssp_response_iu *iu =
1675 hisi_sas_status_buf_addr_mem(slot) +
1676 sizeof(struct hisi_sas_err_record);
1677
1678 sas_ssp_task_response(dev, task, iu);
1679 break;
1680 }
1681 case SAS_PROTOCOL_SMP: {
1682 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1683 void *to;
1684
1685 ts->stat = SAM_STAT_GOOD;
1686 to = kmap_atomic(sg_page(sg_resp));
1687
1688 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1689 DMA_FROM_DEVICE);
1690 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1691 DMA_TO_DEVICE);
1692 memcpy(to + sg_resp->offset,
1693 hisi_sas_status_buf_addr_mem(slot) +
1694 sizeof(struct hisi_sas_err_record),
1695 sg_dma_len(sg_resp));
1696 kunmap_atomic(to);
1697 break;
1698 }
1699 case SAS_PROTOCOL_SATA:
1700 case SAS_PROTOCOL_STP:
1701 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1702 ts->stat = SAM_STAT_GOOD;
1703 hisi_sas_sata_done(task, slot);
1704 break;
1705 default:
1706 ts->stat = SAM_STAT_CHECK_CONDITION;
1707 break;
1708 }
1709
1710 if (!slot->port->port_attached) {
1711 dev_warn(dev, "slot complete: port %d has removed\n",
1712 slot->port->sas_port.id);
1713 ts->stat = SAS_PHY_DOWN;
1714 }
1715
1716 out:
1717 hisi_sas_slot_task_free(hisi_hba, task, slot);
1718 sts = ts->stat;
1719 spin_lock_irqsave(&task->task_state_lock, flags);
1720 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
1721 spin_unlock_irqrestore(&task->task_state_lock, flags);
1722 dev_info(dev, "slot complete: task(%p) aborted\n", task);
1723 return SAS_ABORTED_TASK;
1724 }
1725 task->task_state_flags |= SAS_TASK_STATE_DONE;
1726 spin_unlock_irqrestore(&task->task_state_lock, flags);
1727
1728 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
1729 spin_lock_irqsave(&device->done_lock, flags);
1730 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
1731 spin_unlock_irqrestore(&device->done_lock, flags);
1732 dev_info(dev, "slot complete: task(%p) ignored\n ",
1733 task);
1734 return sts;
1735 }
1736 spin_unlock_irqrestore(&device->done_lock, flags);
1737 }
1738
1739 if (task->task_done)
1740 task->task_done(task);
1741
1742 return sts;
1743 }
1744
1745 static void cq_tasklet_v3_hw(unsigned long val)
1746 {
1747 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1748 struct hisi_hba *hisi_hba = cq->hisi_hba;
1749 struct hisi_sas_slot *slot;
1750 struct hisi_sas_complete_v3_hdr *complete_queue;
1751 u32 rd_point = cq->rd_point, wr_point;
1752 int queue = cq->id;
1753
1754 complete_queue = hisi_hba->complete_hdr[queue];
1755
1756 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1757 (0x14 * queue));
1758
1759 while (rd_point != wr_point) {
1760 struct hisi_sas_complete_v3_hdr *complete_hdr;
1761 struct device *dev = hisi_hba->dev;
1762 int iptt;
1763
1764 complete_hdr = &complete_queue[rd_point];
1765
1766 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1767 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
1768 slot = &hisi_hba->slot_info[iptt];
1769 slot->cmplt_queue_slot = rd_point;
1770 slot->cmplt_queue = queue;
1771 slot_complete_v3_hw(hisi_hba, slot);
1772 } else
1773 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
1774
1775 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1776 rd_point = 0;
1777 }
1778
1779 /* update rd_point */
1780 cq->rd_point = rd_point;
1781 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1782 }
1783
1784 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1785 {
1786 struct hisi_sas_cq *cq = p;
1787 struct hisi_hba *hisi_hba = cq->hisi_hba;
1788 int queue = cq->id;
1789
1790 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1791
1792 tasklet_schedule(&cq->tasklet);
1793
1794 return IRQ_HANDLED;
1795 }
1796
1797 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1798 {
1799 struct device *dev = hisi_hba->dev;
1800 struct pci_dev *pdev = hisi_hba->pci_dev;
1801 int vectors, rc;
1802 int i, k;
1803 int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1804
1805 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1806 max_msi, PCI_IRQ_MSI);
1807 if (vectors < max_msi) {
1808 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1809 return -ENOENT;
1810 }
1811
1812 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1813 int_phy_up_down_bcast_v3_hw, 0,
1814 DRV_NAME " phy", hisi_hba);
1815 if (rc) {
1816 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1817 rc = -ENOENT;
1818 goto free_irq_vectors;
1819 }
1820
1821 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1822 int_chnl_int_v3_hw, 0,
1823 DRV_NAME " channel", hisi_hba);
1824 if (rc) {
1825 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1826 rc = -ENOENT;
1827 goto free_phy_irq;
1828 }
1829
1830 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
1831 fatal_axi_int_v3_hw, 0,
1832 DRV_NAME " fatal", hisi_hba);
1833 if (rc) {
1834 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
1835 rc = -ENOENT;
1836 goto free_chnl_interrupt;
1837 }
1838
1839 /* Init tasklets for cq only */
1840 for (i = 0; i < hisi_hba->queue_count; i++) {
1841 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1842 struct tasklet_struct *t = &cq->tasklet;
1843
1844 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1845 cq_interrupt_v3_hw, 0,
1846 DRV_NAME " cq", cq);
1847 if (rc) {
1848 dev_err(dev,
1849 "could not request cq%d interrupt, rc=%d\n",
1850 i, rc);
1851 rc = -ENOENT;
1852 goto free_cq_irqs;
1853 }
1854
1855 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1856 }
1857
1858 return 0;
1859
1860 free_cq_irqs:
1861 for (k = 0; k < i; k++) {
1862 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1863
1864 free_irq(pci_irq_vector(pdev, k+16), cq);
1865 }
1866 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
1867 free_chnl_interrupt:
1868 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1869 free_phy_irq:
1870 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1871 free_irq_vectors:
1872 pci_free_irq_vectors(pdev);
1873 return rc;
1874 }
1875
1876 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1877 {
1878 int rc;
1879
1880 rc = hw_init_v3_hw(hisi_hba);
1881 if (rc)
1882 return rc;
1883
1884 rc = interrupt_init_v3_hw(hisi_hba);
1885 if (rc)
1886 return rc;
1887
1888 return 0;
1889 }
1890
1891 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
1892 struct sas_phy_linkrates *r)
1893 {
1894 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1895 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1896 enum sas_linkrate min, max;
1897 u32 prog_phy_link_rate = 0x800;
1898
1899 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1900 max = sas_phy->phy->maximum_linkrate;
1901 min = r->minimum_linkrate;
1902 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1903 max = r->maximum_linkrate;
1904 min = sas_phy->phy->minimum_linkrate;
1905 } else
1906 return;
1907
1908 sas_phy->phy->maximum_linkrate = max;
1909 sas_phy->phy->minimum_linkrate = min;
1910 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
1911
1912 disable_phy_v3_hw(hisi_hba, phy_no);
1913 msleep(100);
1914 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1915 prog_phy_link_rate);
1916 start_phy_v3_hw(hisi_hba, phy_no);
1917 }
1918
1919 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
1920 {
1921 struct pci_dev *pdev = hisi_hba->pci_dev;
1922 int i;
1923
1924 synchronize_irq(pci_irq_vector(pdev, 1));
1925 synchronize_irq(pci_irq_vector(pdev, 2));
1926 synchronize_irq(pci_irq_vector(pdev, 11));
1927 for (i = 0; i < hisi_hba->queue_count; i++) {
1928 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
1929 synchronize_irq(pci_irq_vector(pdev, i + 16));
1930 }
1931
1932 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
1933 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
1934 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
1935 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1936
1937 for (i = 0; i < hisi_hba->n_phy; i++) {
1938 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1939 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
1940 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
1941 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
1942 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
1943 }
1944 }
1945
1946 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
1947 {
1948 return hisi_sas_read32(hisi_hba, PHY_STATE);
1949 }
1950
1951 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1952 {
1953 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1954 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1955 struct sas_phy *sphy = sas_phy->phy;
1956 u32 reg_value;
1957
1958 /* loss dword sync */
1959 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1960 sphy->loss_of_dword_sync_count += reg_value;
1961
1962 /* phy reset problem */
1963 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1964 sphy->phy_reset_problem_count += reg_value;
1965
1966 /* invalid dword */
1967 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1968 sphy->invalid_dword_count += reg_value;
1969
1970 /* disparity err */
1971 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1972 sphy->running_disparity_error_count += reg_value;
1973
1974 }
1975
1976 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
1977 {
1978 struct device *dev = hisi_hba->dev;
1979 int rc;
1980 u32 status;
1981
1982 interrupt_disable_v3_hw(hisi_hba);
1983 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
1984 hisi_sas_kill_tasklets(hisi_hba);
1985
1986 hisi_sas_stop_phys(hisi_hba);
1987
1988 mdelay(10);
1989
1990 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
1991
1992 /* wait until bus idle */
1993 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
1994 AM_CURR_TRANS_RETURN, status,
1995 status == 0x3, 10, 100);
1996 if (rc) {
1997 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
1998 return rc;
1999 }
2000
2001 hisi_sas_init_mem(hisi_hba);
2002
2003 return hw_init_v3_hw(hisi_hba);
2004 }
2005
2006 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2007 u8 reg_index, u8 reg_count, u8 *write_data)
2008 {
2009 struct device *dev = hisi_hba->dev;
2010 u32 *data = (u32 *)write_data;
2011 int i;
2012
2013 switch (reg_type) {
2014 case SAS_GPIO_REG_TX:
2015 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2016 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2017 reg_index, reg_index + reg_count - 1);
2018 return -EINVAL;
2019 }
2020
2021 for (i = 0; i < reg_count; i++)
2022 hisi_sas_write32(hisi_hba,
2023 SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2024 data[i]);
2025 break;
2026 default:
2027 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2028 reg_type);
2029 return -EINVAL;
2030 }
2031
2032 return 0;
2033 }
2034
2035 static struct scsi_host_template sht_v3_hw = {
2036 .name = DRV_NAME,
2037 .module = THIS_MODULE,
2038 .queuecommand = sas_queuecommand,
2039 .target_alloc = sas_target_alloc,
2040 .slave_configure = hisi_sas_slave_configure,
2041 .scan_finished = hisi_sas_scan_finished,
2042 .scan_start = hisi_sas_scan_start,
2043 .change_queue_depth = sas_change_queue_depth,
2044 .bios_param = sas_bios_param,
2045 .can_queue = 1,
2046 .this_id = -1,
2047 .sg_tablesize = SG_ALL,
2048 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
2049 .use_clustering = ENABLE_CLUSTERING,
2050 .eh_device_reset_handler = sas_eh_device_reset_handler,
2051 .eh_target_reset_handler = sas_eh_target_reset_handler,
2052 .target_destroy = sas_target_destroy,
2053 .ioctl = sas_ioctl,
2054 .shost_attrs = host_attrs,
2055 };
2056
2057 static const struct hisi_sas_hw hisi_sas_v3_hw = {
2058 .hw_init = hisi_sas_v3_init,
2059 .setup_itct = setup_itct_v3_hw,
2060 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
2061 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
2062 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
2063 .clear_itct = clear_itct_v3_hw,
2064 .sl_notify = sl_notify_v3_hw,
2065 .prep_ssp = prep_ssp_v3_hw,
2066 .prep_smp = prep_smp_v3_hw,
2067 .prep_stp = prep_ata_v3_hw,
2068 .prep_abort = prep_abort_v3_hw,
2069 .get_free_slot = get_free_slot_v3_hw,
2070 .start_delivery = start_delivery_v3_hw,
2071 .slot_complete = slot_complete_v3_hw,
2072 .phys_init = phys_init_v3_hw,
2073 .phy_start = start_phy_v3_hw,
2074 .phy_disable = disable_phy_v3_hw,
2075 .phy_hard_reset = phy_hard_reset_v3_hw,
2076 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
2077 .phy_set_linkrate = phy_set_linkrate_v3_hw,
2078 .dereg_device = dereg_device_v3_hw,
2079 .soft_reset = soft_reset_v3_hw,
2080 .get_phys_state = get_phys_state_v3_hw,
2081 .get_events = phy_get_events_v3_hw,
2082 .write_gpio = write_gpio_v3_hw,
2083 };
2084
2085 static struct Scsi_Host *
2086 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
2087 {
2088 struct Scsi_Host *shost;
2089 struct hisi_hba *hisi_hba;
2090 struct device *dev = &pdev->dev;
2091
2092 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
2093 if (!shost) {
2094 dev_err(dev, "shost alloc failed\n");
2095 return NULL;
2096 }
2097 hisi_hba = shost_priv(shost);
2098
2099 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
2100 hisi_hba->hw = &hisi_sas_v3_hw;
2101 hisi_hba->pci_dev = pdev;
2102 hisi_hba->dev = dev;
2103 hisi_hba->shost = shost;
2104 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
2105
2106 timer_setup(&hisi_hba->timer, NULL, 0);
2107
2108 if (hisi_sas_get_fw_info(hisi_hba) < 0)
2109 goto err_out;
2110
2111 if (hisi_sas_alloc(hisi_hba, shost)) {
2112 hisi_sas_free(hisi_hba);
2113 goto err_out;
2114 }
2115
2116 return shost;
2117 err_out:
2118 scsi_host_put(shost);
2119 dev_err(dev, "shost alloc failed\n");
2120 return NULL;
2121 }
2122
2123 static int
2124 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2125 {
2126 struct Scsi_Host *shost;
2127 struct hisi_hba *hisi_hba;
2128 struct device *dev = &pdev->dev;
2129 struct asd_sas_phy **arr_phy;
2130 struct asd_sas_port **arr_port;
2131 struct sas_ha_struct *sha;
2132 int rc, phy_nr, port_nr, i;
2133
2134 rc = pci_enable_device(pdev);
2135 if (rc)
2136 goto err_out;
2137
2138 pci_set_master(pdev);
2139
2140 rc = pci_request_regions(pdev, DRV_NAME);
2141 if (rc)
2142 goto err_out_disable_device;
2143
2144 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
2145 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
2146 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2147 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2148 dev_err(dev, "No usable DMA addressing method\n");
2149 rc = -EIO;
2150 goto err_out_regions;
2151 }
2152 }
2153
2154 shost = hisi_sas_shost_alloc_pci(pdev);
2155 if (!shost) {
2156 rc = -ENOMEM;
2157 goto err_out_regions;
2158 }
2159
2160 sha = SHOST_TO_SAS_HA(shost);
2161 hisi_hba = shost_priv(shost);
2162 dev_set_drvdata(dev, sha);
2163
2164 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
2165 if (!hisi_hba->regs) {
2166 dev_err(dev, "cannot map register.\n");
2167 rc = -ENOMEM;
2168 goto err_out_ha;
2169 }
2170
2171 phy_nr = port_nr = hisi_hba->n_phy;
2172
2173 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
2174 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
2175 if (!arr_phy || !arr_port) {
2176 rc = -ENOMEM;
2177 goto err_out_ha;
2178 }
2179
2180 sha->sas_phy = arr_phy;
2181 sha->sas_port = arr_port;
2182 sha->core.shost = shost;
2183 sha->lldd_ha = hisi_hba;
2184
2185 shost->transportt = hisi_sas_stt;
2186 shost->max_id = HISI_SAS_MAX_DEVICES;
2187 shost->max_lun = ~0;
2188 shost->max_channel = 1;
2189 shost->max_cmd_len = 16;
2190 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
2191 shost->can_queue = hisi_hba->hw->max_command_entries;
2192 shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
2193
2194 sha->sas_ha_name = DRV_NAME;
2195 sha->dev = dev;
2196 sha->lldd_module = THIS_MODULE;
2197 sha->sas_addr = &hisi_hba->sas_addr[0];
2198 sha->num_phys = hisi_hba->n_phy;
2199 sha->core.shost = hisi_hba->shost;
2200
2201 for (i = 0; i < hisi_hba->n_phy; i++) {
2202 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
2203 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
2204 }
2205
2206 hisi_sas_init_add(hisi_hba);
2207
2208 rc = scsi_add_host(shost, dev);
2209 if (rc)
2210 goto err_out_ha;
2211
2212 rc = sas_register_ha(sha);
2213 if (rc)
2214 goto err_out_register_ha;
2215
2216 rc = hisi_hba->hw->hw_init(hisi_hba);
2217 if (rc)
2218 goto err_out_register_ha;
2219
2220 scsi_scan_host(shost);
2221
2222 return 0;
2223
2224 err_out_register_ha:
2225 scsi_remove_host(shost);
2226 err_out_ha:
2227 scsi_host_put(shost);
2228 err_out_regions:
2229 pci_release_regions(pdev);
2230 err_out_disable_device:
2231 pci_disable_device(pdev);
2232 err_out:
2233 return rc;
2234 }
2235
2236 static void
2237 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
2238 {
2239 int i;
2240
2241 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2242 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2243 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2244 for (i = 0; i < hisi_hba->queue_count; i++) {
2245 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2246
2247 free_irq(pci_irq_vector(pdev, i+16), cq);
2248 }
2249 pci_free_irq_vectors(pdev);
2250 }
2251
2252 static void hisi_sas_v3_remove(struct pci_dev *pdev)
2253 {
2254 struct device *dev = &pdev->dev;
2255 struct sas_ha_struct *sha = dev_get_drvdata(dev);
2256 struct hisi_hba *hisi_hba = sha->lldd_ha;
2257 struct Scsi_Host *shost = sha->core.shost;
2258
2259 if (timer_pending(&hisi_hba->timer))
2260 del_timer(&hisi_hba->timer);
2261
2262 sas_unregister_ha(sha);
2263 sas_remove_host(sha->core.shost);
2264
2265 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
2266 hisi_sas_kill_tasklets(hisi_hba);
2267 pci_release_regions(pdev);
2268 pci_disable_device(pdev);
2269 hisi_sas_free(hisi_hba);
2270 scsi_host_put(shost);
2271 }
2272
2273 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = {
2274 { .irq_msk = BIT(19), .msg = "HILINK_INT" },
2275 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" },
2276 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" },
2277 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" },
2278 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" },
2279 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" },
2280 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" },
2281 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" },
2282 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" },
2283 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" },
2284 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" },
2285 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" },
2286 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" },
2287 };
2288
2289 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = {
2290 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" },
2291 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" },
2292 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" },
2293 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" },
2294 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" },
2295 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" },
2296 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" },
2297 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" },
2298 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" },
2299 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" },
2300 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" },
2301 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" },
2302 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" },
2303 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" },
2304 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" },
2305 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" },
2306 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" },
2307 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" },
2308 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" },
2309 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" },
2310 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" },
2311 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" },
2312 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" },
2313 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" },
2314 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" },
2315 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" },
2316 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" },
2317 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" },
2318 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" },
2319 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" },
2320 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" },
2321 };
2322
2323 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = {
2324 { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" },
2325 { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" },
2326 { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" },
2327 { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" },
2328 { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" },
2329 { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" },
2330 { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" },
2331 { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" },
2332 { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" },
2333 { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" },
2334 { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" },
2335 { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" },
2336 { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" },
2337 { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" },
2338 { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" },
2339 { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" },
2340 { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" },
2341 { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" },
2342 { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" },
2343 { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" },
2344 };
2345
2346 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba)
2347 {
2348 struct device *dev = hisi_hba->dev;
2349 const struct hisi_sas_hw_error *ras_error;
2350 bool need_reset = false;
2351 u32 irq_value;
2352 int i;
2353
2354 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0);
2355 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) {
2356 ras_error = &sas_ras_intr0_nfe[i];
2357 if (ras_error->irq_msk & irq_value) {
2358 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n",
2359 ras_error->msg, irq_value);
2360 need_reset = true;
2361 }
2362 }
2363 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value);
2364
2365 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1);
2366 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) {
2367 ras_error = &sas_ras_intr1_nfe[i];
2368 if (ras_error->irq_msk & irq_value) {
2369 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n",
2370 ras_error->msg, irq_value);
2371 need_reset = true;
2372 }
2373 }
2374 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value);
2375
2376 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2);
2377 for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) {
2378 ras_error = &sas_ras_intr2_nfe[i];
2379 if (ras_error->irq_msk & irq_value) {
2380 dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n",
2381 ras_error->msg, irq_value);
2382 need_reset = true;
2383 }
2384 }
2385 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value);
2386
2387 return need_reset;
2388 }
2389
2390 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev,
2391 pci_channel_state_t state)
2392 {
2393 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2394 struct hisi_hba *hisi_hba = sha->lldd_ha;
2395 struct device *dev = hisi_hba->dev;
2396
2397 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state);
2398 if (state == pci_channel_io_perm_failure)
2399 return PCI_ERS_RESULT_DISCONNECT;
2400
2401 if (process_non_fatal_error_v3_hw(hisi_hba))
2402 return PCI_ERS_RESULT_NEED_RESET;
2403
2404 return PCI_ERS_RESULT_CAN_RECOVER;
2405 }
2406
2407 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev)
2408 {
2409 return PCI_ERS_RESULT_RECOVERED;
2410 }
2411
2412 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev)
2413 {
2414 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2415 struct hisi_hba *hisi_hba = sha->lldd_ha;
2416 struct device *dev = hisi_hba->dev;
2417 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r);
2418
2419 dev_info(dev, "PCI error: slot reset callback!!\n");
2420 queue_work(hisi_hba->wq, &r.work);
2421 wait_for_completion(r.completion);
2422 if (r.done)
2423 return PCI_ERS_RESULT_RECOVERED;
2424
2425 return PCI_ERS_RESULT_DISCONNECT;
2426 }
2427
2428 enum {
2429 /* instances of the controller */
2430 hip08,
2431 };
2432
2433 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state)
2434 {
2435 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2436 struct hisi_hba *hisi_hba = sha->lldd_ha;
2437 struct device *dev = hisi_hba->dev;
2438 struct Scsi_Host *shost = hisi_hba->shost;
2439 u32 device_state, status;
2440 int rc;
2441 u32 reg_val;
2442
2443 if (!pdev->pm_cap) {
2444 dev_err(dev, "PCI PM not supported\n");
2445 return -ENODEV;
2446 }
2447
2448 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2449 scsi_block_requests(shost);
2450 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2451 flush_workqueue(hisi_hba->wq);
2452 /* disable DQ/PHY/bus */
2453 interrupt_disable_v3_hw(hisi_hba);
2454 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2455 hisi_sas_kill_tasklets(hisi_hba);
2456
2457 hisi_sas_stop_phys(hisi_hba);
2458
2459 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2460 AM_CTRL_GLOBAL);
2461 reg_val |= 0x1;
2462 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2463 AM_CTRL_GLOBAL, reg_val);
2464
2465 /* wait until bus idle */
2466 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2467 AM_CURR_TRANS_RETURN, status,
2468 status == 0x3, 10, 100);
2469 if (rc) {
2470 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
2471 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2472 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2473 scsi_unblock_requests(shost);
2474 return rc;
2475 }
2476
2477 hisi_sas_init_mem(hisi_hba);
2478
2479 device_state = pci_choose_state(pdev, state);
2480 dev_warn(dev, "entering operating state [D%d]\n",
2481 device_state);
2482 pci_save_state(pdev);
2483 pci_disable_device(pdev);
2484 pci_set_power_state(pdev, device_state);
2485
2486 hisi_sas_release_tasks(hisi_hba);
2487
2488 sas_suspend_ha(sha);
2489 return 0;
2490 }
2491
2492 static int hisi_sas_v3_resume(struct pci_dev *pdev)
2493 {
2494 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2495 struct hisi_hba *hisi_hba = sha->lldd_ha;
2496 struct Scsi_Host *shost = hisi_hba->shost;
2497 struct device *dev = hisi_hba->dev;
2498 unsigned int rc;
2499 u32 device_state = pdev->current_state;
2500
2501 dev_warn(dev, "resuming from operating state [D%d]\n",
2502 device_state);
2503 pci_set_power_state(pdev, PCI_D0);
2504 pci_enable_wake(pdev, PCI_D0, 0);
2505 pci_restore_state(pdev);
2506 rc = pci_enable_device(pdev);
2507 if (rc)
2508 dev_err(dev, "enable device failed during resume (%d)\n", rc);
2509
2510 pci_set_master(pdev);
2511 scsi_unblock_requests(shost);
2512 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2513
2514 sas_prep_resume_ha(sha);
2515 init_reg_v3_hw(hisi_hba);
2516 hisi_hba->hw->phys_init(hisi_hba);
2517 sas_resume_ha(sha);
2518 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2519
2520 return 0;
2521 }
2522
2523 static const struct pci_device_id sas_v3_pci_table[] = {
2524 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
2525 {}
2526 };
2527 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
2528
2529 static const struct pci_error_handlers hisi_sas_err_handler = {
2530 .error_detected = hisi_sas_error_detected_v3_hw,
2531 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw,
2532 .slot_reset = hisi_sas_slot_reset_v3_hw,
2533 };
2534
2535 static struct pci_driver sas_v3_pci_driver = {
2536 .name = DRV_NAME,
2537 .id_table = sas_v3_pci_table,
2538 .probe = hisi_sas_v3_probe,
2539 .remove = hisi_sas_v3_remove,
2540 .suspend = hisi_sas_v3_suspend,
2541 .resume = hisi_sas_v3_resume,
2542 .err_handler = &hisi_sas_err_handler,
2543 };
2544
2545 module_pci_driver(sas_v3_pci_driver);
2546
2547 MODULE_LICENSE("GPL");
2548 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2549 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2550 MODULE_ALIAS("pci:" DRV_NAME);
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