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UBUNTU: SAUCE: scsi: hisi_sas: export device table of v3 hw to userspace
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v3_hw.c
1 /*
2 * Copyright (c) 2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 #include "hisi_sas.h"
12 #define DRV_NAME "hisi_sas_v3_hw"
13
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
26 #define ITCT_CLR 0x44
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CFG_1US_TIMER_TRSH 0xcc
55 #define CHNL_INT_STATUS 0x148
56 #define HGC_AXI_FIFO_ERR_INFO 0x154
57 #define AXI_ERR_INFO_OFF 0
58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
59 #define FIFO_ERR_INFO_OFF 8
60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
61 #define INT_COAL_EN 0x19c
62 #define OQ_INT_COAL_TIME 0x1a0
63 #define OQ_INT_COAL_CNT 0x1a4
64 #define ENT_INT_COAL_TIME 0x1a8
65 #define ENT_INT_COAL_CNT 0x1ac
66 #define OQ_INT_SRC 0x1b0
67 #define OQ_INT_SRC_MSK 0x1b4
68 #define ENT_INT_SRC1 0x1b8
69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
73 #define ENT_INT_SRC2 0x1bc
74 #define ENT_INT_SRC3 0x1c0
75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
78 #define ENT_INT_SRC3_AXI_OFF 11
79 #define ENT_INT_SRC3_FIFO_OFF 12
80 #define ENT_INT_SRC3_LM_OFF 14
81 #define ENT_INT_SRC3_ITC_INT_OFF 15
82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
83 #define ENT_INT_SRC3_ABT_OFF 16
84 #define ENT_INT_SRC_MSK1 0x1c4
85 #define ENT_INT_SRC_MSK2 0x1c8
86 #define ENT_INT_SRC_MSK3 0x1cc
87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
89 #define CHNL_ENT_INT_MSK 0x1d4
90 #define HGC_COM_INT_MSK 0x1d8
91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
92 #define SAS_ECC_INTR 0x1e8
93 #define SAS_ECC_INTR_MSK 0x1ec
94 #define HGC_ERR_STAT_EN 0x238
95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
97 #define DLVRY_Q_0_DEPTH 0x268
98 #define DLVRY_Q_0_WR_PTR 0x26c
99 #define DLVRY_Q_0_RD_PTR 0x270
100 #define HYPER_STREAM_ID_EN_CFG 0xc80
101 #define OQ0_INT_SRC_MSK 0xc90
102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
104 #define COMPL_Q_0_DEPTH 0x4e8
105 #define COMPL_Q_0_WR_PTR 0x4ec
106 #define COMPL_Q_0_RD_PTR 0x4f0
107 #define AWQOS_AWCACHE_CFG 0xc84
108 #define ARQOS_ARCACHE_CFG 0xc88
109
110 /* phy registers requiring init */
111 #define PORT_BASE (0x2000)
112 #define PHY_CFG (PORT_BASE + 0x0)
113 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
114 #define PHY_CFG_ENA_OFF 0
115 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
116 #define PHY_CFG_DC_OPT_OFF 2
117 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
118 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
119 #define PHY_CTRL (PORT_BASE + 0x14)
120 #define PHY_CTRL_RESET_OFF 0
121 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
122 #define SL_CFG (PORT_BASE + 0x84)
123 #define SL_CONTROL (PORT_BASE + 0x94)
124 #define SL_CONTROL_NOTIFY_EN_OFF 0
125 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
126 #define SL_CTA_OFF 17
127 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
128 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
129 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
130 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
131 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
132 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
133 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
134 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
135 #define TXID_AUTO (PORT_BASE + 0xb8)
136 #define CT3_OFF 1
137 #define CT3_MSK (0x1 << CT3_OFF)
138 #define TX_HARDRST_OFF 2
139 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
140 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
141 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
142 #define STP_LINK_TIMER (PORT_BASE + 0x120)
143 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
144 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
145 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
146 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
147 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
148 #define CHL_INT0 (PORT_BASE + 0x1b4)
149 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
150 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
151 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
152 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
153 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
154 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
155 #define CHL_INT0_NOT_RDY_OFF 4
156 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
157 #define CHL_INT0_PHY_RDY_OFF 5
158 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
159 #define CHL_INT1 (PORT_BASE + 0x1b8)
160 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
161 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
162 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
163 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
164 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
165 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
166 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
167 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
168 #define CHL_INT2 (PORT_BASE + 0x1bc)
169 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
170 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
171 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
172 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
173 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
174 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
175 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
176 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
177 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
178 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
179 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
180 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
181 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
182 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
183 #define DMA_TX_STATUS_BUSY_OFF 0
184 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
185 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
186 #define DMA_RX_STATUS_BUSY_OFF 0
187 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
188
189 #define COARSETUNE_TIME (PORT_BASE + 0x304)
190 #define SAS_TXDEEMPH_G1 (PORT_BASE + 0x350)
191 #define SAS_TXDEEMPH_G2 (PORT_BASE + 0x354)
192 #define SAS_TXDEEMPH_G3 (PORT_BASE + 0x358)
193 #define SAS_TXDEEMPH_G4 (PORT_BASE + 0x35c)
194 #define SATA_TXDEEMPH_G1 (PORT_BASE + 0x360)
195 #define SATA_TXDEEMPH_G2 (PORT_BASE + 0x364)
196 #define SATA_TXDEEMPH_G3 (PORT_BASE + 0x368)
197 #define SATA_TXDEEMPH_G4 (PORT_BASE + 0x36c)
198
199 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
200 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
201 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
202 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
203
204 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
205 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
206 #error Max ITCT exceeded
207 #endif
208
209 #define AXI_MASTER_CFG_BASE (0x5000)
210 #define AM_CTRL_GLOBAL (0x0)
211 #define AM_CURR_TRANS_RETURN (0x150)
212
213 #define AM_CFG_MAX_TRANS (0x5010)
214 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
215 #define AXI_CFG (0x5100)
216 #define AM_ROB_ECC_ERR_ADDR (0x510c)
217 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
218 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
219 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
220 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
221
222 /* RAS registers need init */
223 #define RAS_BASE (0x6000)
224 #define SAS_RAS_INTR0 (RAS_BASE)
225 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
226 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
227 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
228
229 /* HW dma structures */
230 /* Delivery queue header */
231 /* dw0 */
232 #define CMD_HDR_ABORT_FLAG_OFF 0
233 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
234 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
235 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
236 #define CMD_HDR_RESP_REPORT_OFF 5
237 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
238 #define CMD_HDR_TLR_CTRL_OFF 6
239 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
240 #define CMD_HDR_PORT_OFF 18
241 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
242 #define CMD_HDR_PRIORITY_OFF 27
243 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
244 #define CMD_HDR_CMD_OFF 29
245 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
246 /* dw1 */
247 #define CMD_HDR_UNCON_CMD_OFF 3
248 #define CMD_HDR_DIR_OFF 5
249 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
250 #define CMD_HDR_RESET_OFF 7
251 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
252 #define CMD_HDR_VDTL_OFF 10
253 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
254 #define CMD_HDR_FRAME_TYPE_OFF 11
255 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
256 #define CMD_HDR_DEV_ID_OFF 16
257 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
258 /* dw2 */
259 #define CMD_HDR_CFL_OFF 0
260 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
261 #define CMD_HDR_NCQ_TAG_OFF 10
262 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
263 #define CMD_HDR_MRFL_OFF 15
264 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
265 #define CMD_HDR_SG_MOD_OFF 24
266 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
267 /* dw3 */
268 #define CMD_HDR_IPTT_OFF 0
269 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
270 /* dw6 */
271 #define CMD_HDR_DIF_SGL_LEN_OFF 0
272 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
273 #define CMD_HDR_DATA_SGL_LEN_OFF 16
274 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
275 /* dw7 */
276 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
277 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
278 #define CMD_HDR_ABORT_IPTT_OFF 16
279 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
280
281 /* Completion header */
282 /* dw0 */
283 #define CMPLT_HDR_CMPLT_OFF 0
284 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
285 #define CMPLT_HDR_ERROR_PHASE_OFF 2
286 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
287 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
288 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
289 #define CMPLT_HDR_ERX_OFF 12
290 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
291 #define CMPLT_HDR_ABORT_STAT_OFF 13
292 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
293 /* abort_stat */
294 #define STAT_IO_NOT_VALID 0x1
295 #define STAT_IO_NO_DEVICE 0x2
296 #define STAT_IO_COMPLETE 0x3
297 #define STAT_IO_ABORTED 0x4
298 /* dw1 */
299 #define CMPLT_HDR_IPTT_OFF 0
300 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
301 #define CMPLT_HDR_DEV_ID_OFF 16
302 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
303 /* dw3 */
304 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
305 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
306
307 /* ITCT header */
308 /* qw0 */
309 #define ITCT_HDR_DEV_TYPE_OFF 0
310 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
311 #define ITCT_HDR_VALID_OFF 2
312 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
313 #define ITCT_HDR_MCR_OFF 5
314 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
315 #define ITCT_HDR_VLN_OFF 9
316 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
317 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
318 #define ITCT_HDR_AWT_CONTINUE_OFF 25
319 #define ITCT_HDR_PORT_ID_OFF 28
320 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
321 /* qw2 */
322 #define ITCT_HDR_INLT_OFF 0
323 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
324 #define ITCT_HDR_RTOLT_OFF 48
325 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
326
327 struct hisi_sas_complete_v3_hdr {
328 __le32 dw0;
329 __le32 dw1;
330 __le32 act;
331 __le32 dw3;
332 };
333
334 struct hisi_sas_err_record_v3 {
335 /* dw0 */
336 __le32 trans_tx_fail_type;
337
338 /* dw1 */
339 __le32 trans_rx_fail_type;
340
341 /* dw2 */
342 __le16 dma_tx_err_type;
343 __le16 sipc_rx_err_type;
344
345 /* dw3 */
346 __le32 dma_rx_err_type;
347 };
348
349 #define RX_DATA_LEN_UNDERFLOW_OFF 6
350 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
351
352 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
353 #define HISI_SAS_MSI_COUNT_V3_HW 32
354
355 enum {
356 HISI_SAS_PHY_PHY_UPDOWN,
357 HISI_SAS_PHY_CHNL_INT,
358 HISI_SAS_PHY_INT_NR
359 };
360
361 #define DIR_NO_DATA 0
362 #define DIR_TO_INI 1
363 #define DIR_TO_DEVICE 2
364 #define DIR_RESERVED 3
365
366 #define CMD_IS_UNCONSTRAINT(cmd) \
367 ((cmd == ATA_CMD_READ_LOG_EXT) || \
368 (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
369 (cmd == ATA_CMD_DEV_RESET))
370
371 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
372 {
373 void __iomem *regs = hisi_hba->regs + off;
374
375 return readl(regs);
376 }
377
378 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
379 {
380 void __iomem *regs = hisi_hba->regs + off;
381
382 return readl_relaxed(regs);
383 }
384
385 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
386 {
387 void __iomem *regs = hisi_hba->regs + off;
388
389 writel(val, regs);
390 }
391
392 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
393 u32 off, u32 val)
394 {
395 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
396
397 writel(val, regs);
398 }
399
400 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
401 int phy_no, u32 off)
402 {
403 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
404
405 return readl(regs);
406 }
407
408 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
409 {
410 int i;
411
412 /* Global registers init */
413 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
414 (u32)((1ULL << hisi_hba->queue_count) - 1));
415 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
416 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
417 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
418 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
419 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
420 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
421 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
422 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
423 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
424 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
425 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
426 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff);
427 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
428 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
429 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
430 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
431 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
432 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
433 for (i = 0; i < hisi_hba->queue_count; i++)
434 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
435
436 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
437
438 for (i = 0; i < hisi_hba->n_phy; i++) {
439 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
440 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
441 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
442 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
443 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
444 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
445 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff87ffff);
446 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
447 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
448 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
449 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
450 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
451 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
452 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
453
454 /* used for 12G negotiate */
455 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
456 hisi_sas_phy_write32(hisi_hba, i, SAS_TXDEEMPH_G1, 0x8d04);
457 hisi_sas_phy_write32(hisi_hba, i, SAS_TXDEEMPH_G2, 0x8d04);
458 hisi_sas_phy_write32(hisi_hba, i, SAS_TXDEEMPH_G3, 0x8d04);
459 hisi_sas_phy_write32(hisi_hba, i, SAS_TXDEEMPH_G4, 0x8d04);
460 hisi_sas_phy_write32(hisi_hba, i, SATA_TXDEEMPH_G1, 0x8d04);
461 hisi_sas_phy_write32(hisi_hba, i, SATA_TXDEEMPH_G2, 0x8d04);
462 hisi_sas_phy_write32(hisi_hba, i, SATA_TXDEEMPH_G3, 0x8d04);
463 hisi_sas_phy_write32(hisi_hba, i, SATA_TXDEEMPH_G4, 0x8d04);
464
465 /* disable stp link timer */
466 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x2710);
467 }
468 for (i = 0; i < hisi_hba->queue_count; i++) {
469 /* Delivery queue */
470 hisi_sas_write32(hisi_hba,
471 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
472 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
473
474 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
475 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
476
477 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
478 HISI_SAS_QUEUE_SLOTS);
479
480 /* Completion queue */
481 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
482 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
483
484 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
485 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
486
487 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
488 HISI_SAS_QUEUE_SLOTS);
489 }
490
491 /* itct */
492 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
493 lower_32_bits(hisi_hba->itct_dma));
494
495 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
496 upper_32_bits(hisi_hba->itct_dma));
497
498 /* iost */
499 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
500 lower_32_bits(hisi_hba->iost_dma));
501
502 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
503 upper_32_bits(hisi_hba->iost_dma));
504
505 /* breakpoint */
506 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
507 lower_32_bits(hisi_hba->breakpoint_dma));
508
509 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
510 upper_32_bits(hisi_hba->breakpoint_dma));
511
512 /* SATA broken msg */
513 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
514 lower_32_bits(hisi_hba->sata_breakpoint_dma));
515
516 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
517 upper_32_bits(hisi_hba->sata_breakpoint_dma));
518
519 /* SATA initial fis */
520 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
521 lower_32_bits(hisi_hba->initial_fis_dma));
522
523 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
524 upper_32_bits(hisi_hba->initial_fis_dma));
525
526 /* RAS registers init */
527 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
528 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
529 }
530
531 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
532 {
533 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
534
535 cfg &= ~PHY_CFG_DC_OPT_MSK;
536 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
537 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
538 }
539
540 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
541 {
542 struct sas_identify_frame identify_frame;
543 u32 *identify_buffer;
544
545 memset(&identify_frame, 0, sizeof(identify_frame));
546 identify_frame.dev_type = SAS_END_DEVICE;
547 identify_frame.frame_type = 0;
548 identify_frame._un1 = 1;
549 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
550 identify_frame.target_bits = SAS_PROTOCOL_NONE;
551 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
552 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
553 identify_frame.phy_id = phy_no;
554 identify_buffer = (u32 *)(&identify_frame);
555
556 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
557 __swab32(identify_buffer[0]));
558 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
559 __swab32(identify_buffer[1]));
560 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
561 __swab32(identify_buffer[2]));
562 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
563 __swab32(identify_buffer[3]));
564 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
565 __swab32(identify_buffer[4]));
566 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
567 __swab32(identify_buffer[5]));
568 }
569
570 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
571 struct hisi_sas_device *sas_dev)
572 {
573 struct domain_device *device = sas_dev->sas_device;
574 struct device *dev = hisi_hba->dev;
575 u64 qw0, device_id = sas_dev->device_id;
576 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
577 struct domain_device *parent_dev = device->parent;
578 struct asd_sas_port *sas_port = device->port;
579 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
580
581 memset(itct, 0, sizeof(*itct));
582
583 /* qw0 */
584 qw0 = 0;
585 switch (sas_dev->dev_type) {
586 case SAS_END_DEVICE:
587 case SAS_EDGE_EXPANDER_DEVICE:
588 case SAS_FANOUT_EXPANDER_DEVICE:
589 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
590 break;
591 case SAS_SATA_DEV:
592 case SAS_SATA_PENDING:
593 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
594 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
595 else
596 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
597 break;
598 default:
599 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
600 sas_dev->dev_type);
601 }
602
603 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
604 (device->linkrate << ITCT_HDR_MCR_OFF) |
605 (1 << ITCT_HDR_VLN_OFF) |
606 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
607 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
608 (port->id << ITCT_HDR_PORT_ID_OFF));
609 itct->qw0 = cpu_to_le64(qw0);
610
611 /* qw1 */
612 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
613 itct->sas_addr = __swab64(itct->sas_addr);
614
615 /* qw2 */
616 if (!dev_is_sata(device))
617 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
618 (0x1ULL << ITCT_HDR_RTOLT_OFF));
619 }
620
621 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba,
622 struct hisi_sas_device *sas_dev)
623 {
624 DECLARE_COMPLETION_ONSTACK(completion);
625 u64 dev_id = sas_dev->device_id;
626 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
627 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
628
629 sas_dev->completion = &completion;
630
631 /* clear the itct interrupt state */
632 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
633 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
634 ENT_INT_SRC3_ITC_INT_MSK);
635
636 /* clear the itct table*/
637 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
638 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
639
640 wait_for_completion(sas_dev->completion);
641 memset(itct, 0, sizeof(struct hisi_sas_itct));
642 }
643
644 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
645 struct domain_device *device)
646 {
647 struct hisi_sas_slot *slot, *slot2;
648 struct hisi_sas_device *sas_dev = device->lldd_dev;
649 u32 cfg_abt_set_query_iptt;
650
651 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
652 CFG_ABT_SET_QUERY_IPTT);
653 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
654 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
655 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
656 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
657 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
658 cfg_abt_set_query_iptt);
659 }
660 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
661 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
662 cfg_abt_set_query_iptt);
663 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
664 1 << CFG_ABT_SET_IPTT_DONE_OFF);
665 }
666
667 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
668 {
669 struct device *dev = hisi_hba->dev;
670 int ret;
671 u32 val;
672
673 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
674
675 /* Disable all of the PHYs */
676 hisi_sas_stop_phys(hisi_hba);
677 udelay(50);
678
679 /* Ensure axi bus idle */
680 ret = readl_poll_timeout(hisi_hba->regs + AXI_CFG, val, !val,
681 20000, 1000000);
682 if (ret) {
683 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
684 return -EIO;
685 }
686
687 if (ACPI_HANDLE(dev)) {
688 acpi_status s;
689
690 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
691 if (ACPI_FAILURE(s)) {
692 dev_err(dev, "Reset failed\n");
693 return -EIO;
694 }
695 } else
696 dev_err(dev, "no reset method!\n");
697
698 return 0;
699 }
700
701 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
702 {
703 struct device *dev = hisi_hba->dev;
704 int rc;
705
706 rc = reset_hw_v3_hw(hisi_hba);
707 if (rc) {
708 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
709 return rc;
710 }
711
712 msleep(100);
713 init_reg_v3_hw(hisi_hba);
714
715 return 0;
716 }
717
718 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
719 {
720 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
721
722 cfg |= PHY_CFG_ENA_MSK;
723 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
724 }
725
726 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
727 {
728 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
729
730 cfg &= ~PHY_CFG_ENA_MSK;
731 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
732 }
733
734 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
735 {
736 config_id_frame_v3_hw(hisi_hba, phy_no);
737 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
738 enable_phy_v3_hw(hisi_hba, phy_no);
739 }
740
741 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
742 {
743 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
744 u32 txid_auto;
745
746 disable_phy_v3_hw(hisi_hba, phy_no);
747 if (phy->identify.device_type == SAS_END_DEVICE) {
748 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
749 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
750 txid_auto | TX_HARDRST_MSK);
751 }
752 msleep(100);
753 start_phy_v3_hw(hisi_hba, phy_no);
754 }
755
756 enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
757 {
758 return SAS_LINK_RATE_12_0_GBPS;
759 }
760
761 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
762 {
763 int i;
764
765 for (i = 0; i < hisi_hba->n_phy; i++) {
766 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
767 struct asd_sas_phy *sas_phy = &phy->sas_phy;
768
769 if (!sas_phy->phy->enabled)
770 continue;
771
772 start_phy_v3_hw(hisi_hba, i);
773 }
774 }
775
776 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
777 {
778 u32 sl_control;
779
780 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
781 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
782 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
783 msleep(1);
784 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
785 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
786 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
787 }
788
789 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
790 {
791 int i, bitmap = 0;
792 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
793 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
794
795 for (i = 0; i < hisi_hba->n_phy; i++)
796 if (phy_state & BIT(i))
797 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
798 bitmap |= BIT(i);
799
800 return bitmap;
801 }
802
803 /**
804 * The callpath to this function and upto writing the write
805 * queue pointer should be safe from interruption.
806 */
807 static int
808 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
809 {
810 struct device *dev = hisi_hba->dev;
811 int queue = dq->id;
812 u32 r, w;
813
814 w = dq->wr_point;
815 r = hisi_sas_read32_relaxed(hisi_hba,
816 DLVRY_Q_0_RD_PTR + (queue * 0x14));
817 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
818 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
819 queue, r, w);
820 return -EAGAIN;
821 }
822
823 return 0;
824 }
825
826 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
827 {
828 struct hisi_hba *hisi_hba = dq->hisi_hba;
829 int dlvry_queue = dq->slot_prep->dlvry_queue;
830 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
831
832 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
833 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
834 dq->wr_point);
835 }
836
837 static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
838 struct hisi_sas_slot *slot,
839 struct hisi_sas_cmd_hdr *hdr,
840 struct scatterlist *scatter,
841 int n_elem)
842 {
843 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
844 struct device *dev = hisi_hba->dev;
845 struct scatterlist *sg;
846 int i;
847
848 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
849 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
850 n_elem);
851 return -EINVAL;
852 }
853
854 for_each_sg(scatter, sg, n_elem, i) {
855 struct hisi_sas_sge *entry = &sge_page->sge[i];
856
857 entry->addr = cpu_to_le64(sg_dma_address(sg));
858 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
859 entry->data_len = cpu_to_le32(sg_dma_len(sg));
860 entry->data_off = 0;
861 }
862
863 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
864
865 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
866
867 return 0;
868 }
869
870 static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
871 struct hisi_sas_slot *slot, int is_tmf,
872 struct hisi_sas_tmf_task *tmf)
873 {
874 struct sas_task *task = slot->task;
875 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
876 struct domain_device *device = task->dev;
877 struct hisi_sas_device *sas_dev = device->lldd_dev;
878 struct hisi_sas_port *port = slot->port;
879 struct sas_ssp_task *ssp_task = &task->ssp_task;
880 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
881 int has_data = 0, rc, priority = is_tmf;
882 u8 *buf_cmd;
883 u32 dw1 = 0, dw2 = 0;
884
885 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
886 (2 << CMD_HDR_TLR_CTRL_OFF) |
887 (port->id << CMD_HDR_PORT_OFF) |
888 (priority << CMD_HDR_PRIORITY_OFF) |
889 (1 << CMD_HDR_CMD_OFF)); /* ssp */
890
891 dw1 = 1 << CMD_HDR_VDTL_OFF;
892 if (is_tmf) {
893 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
894 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
895 } else {
896 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
897 switch (scsi_cmnd->sc_data_direction) {
898 case DMA_TO_DEVICE:
899 has_data = 1;
900 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
901 break;
902 case DMA_FROM_DEVICE:
903 has_data = 1;
904 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
905 break;
906 default:
907 dw1 &= ~CMD_HDR_DIR_MSK;
908 }
909 }
910
911 /* map itct entry */
912 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
913 hdr->dw1 = cpu_to_le32(dw1);
914
915 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
916 + 3) / 4) << CMD_HDR_CFL_OFF) |
917 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
918 (2 << CMD_HDR_SG_MOD_OFF);
919 hdr->dw2 = cpu_to_le32(dw2);
920 hdr->transfer_tags = cpu_to_le32(slot->idx);
921
922 if (has_data) {
923 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
924 slot->n_elem);
925 if (rc)
926 return rc;
927 }
928
929 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
930 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
931 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
932
933 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
934 sizeof(struct ssp_frame_hdr);
935
936 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
937 if (!is_tmf) {
938 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
939 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
940 } else {
941 buf_cmd[10] = tmf->tmf;
942 switch (tmf->tmf) {
943 case TMF_ABORT_TASK:
944 case TMF_QUERY_TASK:
945 buf_cmd[12] =
946 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
947 buf_cmd[13] =
948 tmf->tag_of_task_to_be_managed & 0xff;
949 break;
950 default:
951 break;
952 }
953 }
954
955 return 0;
956 }
957
958 static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
959 struct hisi_sas_slot *slot)
960 {
961 struct sas_task *task = slot->task;
962 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
963 struct domain_device *device = task->dev;
964 struct device *dev = hisi_hba->dev;
965 struct hisi_sas_port *port = slot->port;
966 struct scatterlist *sg_req, *sg_resp;
967 struct hisi_sas_device *sas_dev = device->lldd_dev;
968 dma_addr_t req_dma_addr;
969 unsigned int req_len, resp_len;
970 int elem, rc;
971
972 /*
973 * DMA-map SMP request, response buffers
974 */
975 /* req */
976 sg_req = &task->smp_task.smp_req;
977 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
978 if (!elem)
979 return -ENOMEM;
980 req_len = sg_dma_len(sg_req);
981 req_dma_addr = sg_dma_address(sg_req);
982
983 /* resp */
984 sg_resp = &task->smp_task.smp_resp;
985 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
986 if (!elem) {
987 rc = -ENOMEM;
988 goto err_out_req;
989 }
990 resp_len = sg_dma_len(sg_resp);
991 if ((req_len & 0x3) || (resp_len & 0x3)) {
992 rc = -EINVAL;
993 goto err_out_resp;
994 }
995
996 /* create header */
997 /* dw0 */
998 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
999 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1000 (2 << CMD_HDR_CMD_OFF)); /* smp */
1001
1002 /* map itct entry */
1003 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1004 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1005 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1006
1007 /* dw2 */
1008 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1009 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1010 CMD_HDR_MRFL_OFF));
1011
1012 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1013
1014 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1015 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1016
1017 return 0;
1018
1019 err_out_resp:
1020 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1021 DMA_FROM_DEVICE);
1022 err_out_req:
1023 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1024 DMA_TO_DEVICE);
1025 return rc;
1026 }
1027
1028 static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1029 struct hisi_sas_slot *slot)
1030 {
1031 struct sas_task *task = slot->task;
1032 struct domain_device *device = task->dev;
1033 struct domain_device *parent_dev = device->parent;
1034 struct hisi_sas_device *sas_dev = device->lldd_dev;
1035 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1036 struct asd_sas_port *sas_port = device->port;
1037 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1038 u8 *buf_cmd;
1039 int has_data = 0, rc = 0, hdr_tag = 0;
1040 u32 dw1 = 0, dw2 = 0;
1041
1042 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1043 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1044 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1045 else
1046 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1047
1048 switch (task->data_dir) {
1049 case DMA_TO_DEVICE:
1050 has_data = 1;
1051 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1052 break;
1053 case DMA_FROM_DEVICE:
1054 has_data = 1;
1055 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1056 break;
1057 default:
1058 dw1 &= ~CMD_HDR_DIR_MSK;
1059 }
1060
1061 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1062 (task->ata_task.fis.control & ATA_SRST))
1063 dw1 |= 1 << CMD_HDR_RESET_OFF;
1064
1065 dw1 |= (hisi_sas_get_ata_protocol(
1066 &task->ata_task.fis, task->data_dir))
1067 << CMD_HDR_FRAME_TYPE_OFF;
1068 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1069
1070 if (CMD_IS_UNCONSTRAINT(task->ata_task.fis.command))
1071 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1072
1073 hdr->dw1 = cpu_to_le32(dw1);
1074
1075 /* dw2 */
1076 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
1077 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1078 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1079 }
1080
1081 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1082 2 << CMD_HDR_SG_MOD_OFF;
1083 hdr->dw2 = cpu_to_le32(dw2);
1084
1085 /* dw3 */
1086 hdr->transfer_tags = cpu_to_le32(slot->idx);
1087
1088 if (has_data) {
1089 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1090 slot->n_elem);
1091 if (rc)
1092 return rc;
1093 }
1094
1095 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1096 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1097 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1098
1099 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1100
1101 if (likely(!task->ata_task.device_control_reg_update))
1102 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1103 /* fill in command FIS */
1104 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1105
1106 return 0;
1107 }
1108
1109 static int prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1110 struct hisi_sas_slot *slot,
1111 int device_id, int abort_flag, int tag_to_abort)
1112 {
1113 struct sas_task *task = slot->task;
1114 struct domain_device *dev = task->dev;
1115 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1116 struct hisi_sas_port *port = slot->port;
1117
1118 /* dw0 */
1119 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1120 (port->id << CMD_HDR_PORT_OFF) |
1121 ((dev_is_sata(dev) ? 1:0)
1122 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1123 (abort_flag
1124 << CMD_HDR_ABORT_FLAG_OFF));
1125
1126 /* dw1 */
1127 hdr->dw1 = cpu_to_le32(device_id
1128 << CMD_HDR_DEV_ID_OFF);
1129
1130 /* dw7 */
1131 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1132 hdr->transfer_tags = cpu_to_le32(slot->idx);
1133
1134 return 0;
1135 }
1136
1137 static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1138 {
1139 int i, res = 0;
1140 u32 context, port_id, link_rate, hard_phy_linkrate;
1141 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1142 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1143 struct device *dev = hisi_hba->dev;
1144
1145 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1146
1147 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1148 port_id = (port_id >> (4 * phy_no)) & 0xf;
1149 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1150 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1151
1152 if (port_id == 0xf) {
1153 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1154 res = IRQ_NONE;
1155 goto end;
1156 }
1157 sas_phy->linkrate = link_rate;
1158 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1159 HARD_PHY_LINKRATE);
1160 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1161 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1162 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1163
1164 /* Check for SATA dev */
1165 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1166 if (context & (1 << phy_no)) {
1167 struct hisi_sas_initial_fis *initial_fis;
1168 struct dev_to_host_fis *fis;
1169 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1170
1171 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1172 initial_fis = &hisi_hba->initial_fis[phy_no];
1173 fis = &initial_fis->fis;
1174 sas_phy->oob_mode = SATA_OOB_MODE;
1175 attached_sas_addr[0] = 0x50;
1176 attached_sas_addr[7] = phy_no;
1177 memcpy(sas_phy->attached_sas_addr,
1178 attached_sas_addr,
1179 SAS_ADDR_SIZE);
1180 memcpy(sas_phy->frame_rcvd, fis,
1181 sizeof(struct dev_to_host_fis));
1182 phy->phy_type |= PORT_TYPE_SATA;
1183 phy->identify.device_type = SAS_SATA_DEV;
1184 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1185 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1186 } else {
1187 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1188 struct sas_identify_frame *id =
1189 (struct sas_identify_frame *)frame_rcvd;
1190
1191 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1192 for (i = 0; i < 6; i++) {
1193 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1194 RX_IDAF_DWORD0 + (i * 4));
1195 frame_rcvd[i] = __swab32(idaf);
1196 }
1197 sas_phy->oob_mode = SAS_OOB_MODE;
1198 memcpy(sas_phy->attached_sas_addr,
1199 &id->sas_addr,
1200 SAS_ADDR_SIZE);
1201 phy->phy_type |= PORT_TYPE_SAS;
1202 phy->identify.device_type = id->dev_type;
1203 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1204 if (phy->identify.device_type == SAS_END_DEVICE)
1205 phy->identify.target_port_protocols =
1206 SAS_PROTOCOL_SSP;
1207 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1208 phy->identify.target_port_protocols =
1209 SAS_PROTOCOL_SMP;
1210 }
1211
1212 phy->port_id = port_id;
1213 phy->phy_attached = 1;
1214 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1215
1216 end:
1217 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1218 CHL_INT0_SL_PHY_ENABLE_MSK);
1219 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1220
1221 return res;
1222 }
1223
1224 static int phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1225 {
1226 u32 phy_state, sl_ctrl, txid_auto;
1227 struct device *dev = hisi_hba->dev;
1228
1229 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1230
1231 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1232 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1233 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1234
1235 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1236 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1237 sl_ctrl&(~SL_CTA_MSK));
1238
1239 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1240 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1241 txid_auto | CT3_MSK);
1242
1243 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1244 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1245
1246 return 0;
1247 }
1248
1249 static void phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1250 {
1251 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1252 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1253 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1254
1255 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1256 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1257 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1258 CHL_INT0_SL_RX_BCST_ACK_MSK);
1259 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1260 }
1261
1262 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1263 {
1264 struct hisi_hba *hisi_hba = p;
1265 u32 irq_msk;
1266 int phy_no = 0;
1267 irqreturn_t res = IRQ_NONE;
1268
1269 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1270 & 0x11111111;
1271 while (irq_msk) {
1272 if (irq_msk & 1) {
1273 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1274 CHL_INT0);
1275 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1276 int rdy = phy_state & (1 << phy_no);
1277
1278 if (rdy) {
1279 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1280 /* phy up */
1281 if (phy_up_v3_hw(phy_no, hisi_hba)
1282 == IRQ_HANDLED)
1283 res = IRQ_HANDLED;
1284 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1285 /* phy bcast */
1286 phy_bcast_v3_hw(phy_no, hisi_hba);
1287 } else {
1288 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1289 /* phy down */
1290 if (phy_down_v3_hw(phy_no, hisi_hba)
1291 == IRQ_HANDLED)
1292 res = IRQ_HANDLED;
1293 }
1294 }
1295 irq_msk >>= 4;
1296 phy_no++;
1297 }
1298
1299 return res;
1300 }
1301
1302 static const struct hisi_sas_hw_error port_axi_error[] = {
1303 {
1304 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1305 .msg = "dma_tx_axi_wr_err",
1306 },
1307 {
1308 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1309 .msg = "dma_tx_axi_rd_err",
1310 },
1311 {
1312 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1313 .msg = "dma_rx_axi_wr_err",
1314 },
1315 {
1316 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1317 .msg = "dma_rx_axi_rd_err",
1318 },
1319 };
1320
1321 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1322 {
1323 struct hisi_hba *hisi_hba = p;
1324 struct device *dev = hisi_hba->dev;
1325 u32 ent_msk, ent_tmp, irq_msk;
1326 int phy_no = 0;
1327
1328 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1329 ent_tmp = ent_msk;
1330 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1331 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1332
1333 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1334 & 0xeeeeeeee;
1335
1336 while (irq_msk) {
1337 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1338 CHL_INT0);
1339 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1340 CHL_INT1);
1341 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1342 CHL_INT2);
1343
1344 if ((irq_msk & (4 << (phy_no * 4))) &&
1345 irq_value1) {
1346 int i;
1347
1348 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1349 const struct hisi_sas_hw_error *error =
1350 &port_axi_error[i];
1351
1352 if (!(irq_value1 & error->irq_msk))
1353 continue;
1354
1355 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1356 error->msg, phy_no, irq_value1);
1357 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1358 }
1359
1360 hisi_sas_phy_write32(hisi_hba, phy_no,
1361 CHL_INT1, irq_value1);
1362 }
1363
1364 if (irq_msk & (8 << (phy_no * 4)) && irq_value2) {
1365 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1366
1367 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1368 dev_warn(dev, "phy%d identify timeout\n",
1369 phy_no);
1370 hisi_sas_notify_phy_event(phy,
1371 HISI_PHYE_LINK_RESET);
1372
1373 }
1374
1375 if (irq_value2 & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1376 u32 reg_value = hisi_sas_phy_read32(hisi_hba,
1377 phy_no, STP_LINK_TIMEOUT_STATE);
1378
1379 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1380 phy_no, reg_value);
1381 if (reg_value & BIT(4))
1382 hisi_sas_notify_phy_event(phy,
1383 HISI_PHYE_LINK_RESET);
1384 }
1385
1386 hisi_sas_phy_write32(hisi_hba, phy_no,
1387 CHL_INT2, irq_value2);
1388 }
1389
1390
1391 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1392 hisi_sas_phy_write32(hisi_hba, phy_no,
1393 CHL_INT0, irq_value0
1394 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1395 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1396 & (~CHL_INT0_NOT_RDY_MSK));
1397 }
1398 irq_msk &= ~(0xe << (phy_no * 4));
1399 phy_no++;
1400 }
1401
1402 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1403
1404 return IRQ_HANDLED;
1405 }
1406
1407 static const struct hisi_sas_hw_error axi_error[] = {
1408 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1409 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1410 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1411 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1412 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1413 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1414 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1415 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1416 {},
1417 };
1418
1419 static const struct hisi_sas_hw_error fifo_error[] = {
1420 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
1421 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
1422 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1423 { .msk = BIT(11), .msg = "CMDP_FIFO" },
1424 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1425 {},
1426 };
1427
1428 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1429 {
1430 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1431 .msg = "write pointer and depth",
1432 },
1433 {
1434 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
1435 .msg = "iptt no match slot",
1436 },
1437 {
1438 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
1439 .msg = "read pointer and depth",
1440 },
1441 {
1442 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
1443 .reg = HGC_AXI_FIFO_ERR_INFO,
1444 .sub = axi_error,
1445 },
1446 {
1447 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
1448 .reg = HGC_AXI_FIFO_ERR_INFO,
1449 .sub = fifo_error,
1450 },
1451 {
1452 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
1453 .msg = "LM add/fetch list",
1454 },
1455 {
1456 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
1457 .msg = "SAS_HGC_ABT fetch LM list",
1458 },
1459 };
1460
1461 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
1462 {
1463 u32 irq_value, irq_msk;
1464 struct hisi_hba *hisi_hba = p;
1465 struct device *dev = hisi_hba->dev;
1466 int i;
1467
1468 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1469 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
1470
1471 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
1472
1473 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
1474 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
1475
1476 if (!(irq_value & error->irq_msk))
1477 continue;
1478
1479 if (error->sub) {
1480 const struct hisi_sas_hw_error *sub = error->sub;
1481 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
1482
1483 for (; sub->msk || sub->msg; sub++) {
1484 if (!(err_value & sub->msk))
1485 continue;
1486
1487 dev_err(dev, "%s error (0x%x) found!\n",
1488 sub->msg, irq_value);
1489 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1490 }
1491 } else {
1492 dev_err(dev, "%s error (0x%x) found!\n",
1493 error->msg, irq_value);
1494 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1495 }
1496 }
1497
1498 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
1499 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
1500 u32 dev_id = reg_val & ITCT_DEV_MSK;
1501 struct hisi_sas_device *sas_dev =
1502 &hisi_hba->devices[dev_id];
1503
1504 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
1505 dev_dbg(dev, "clear ITCT ok\n");
1506 complete(sas_dev->completion);
1507 }
1508
1509 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
1510 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
1511
1512 return IRQ_HANDLED;
1513 }
1514
1515 static void
1516 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1517 struct hisi_sas_slot *slot)
1518 {
1519 struct task_status_struct *ts = &task->task_status;
1520 struct hisi_sas_complete_v3_hdr *complete_queue =
1521 hisi_hba->complete_hdr[slot->cmplt_queue];
1522 struct hisi_sas_complete_v3_hdr *complete_hdr =
1523 &complete_queue[slot->cmplt_queue_slot];
1524 struct hisi_sas_err_record_v3 *record =
1525 hisi_sas_status_buf_addr_mem(slot);
1526 u32 dma_rx_err_type = record->dma_rx_err_type;
1527 u32 trans_tx_fail_type = record->trans_tx_fail_type;
1528
1529 switch (task->task_proto) {
1530 case SAS_PROTOCOL_SSP:
1531 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1532 ts->residual = trans_tx_fail_type;
1533 ts->stat = SAS_DATA_UNDERRUN;
1534 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1535 ts->stat = SAS_QUEUE_FULL;
1536 slot->abort = 1;
1537 } else {
1538 ts->stat = SAS_OPEN_REJECT;
1539 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1540 }
1541 break;
1542 case SAS_PROTOCOL_SATA:
1543 case SAS_PROTOCOL_STP:
1544 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1545 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1546 ts->residual = trans_tx_fail_type;
1547 ts->stat = SAS_DATA_UNDERRUN;
1548 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1549 ts->stat = SAS_PHY_DOWN;
1550 slot->abort = 1;
1551 } else {
1552 ts->stat = SAS_OPEN_REJECT;
1553 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1554 }
1555 hisi_sas_sata_done(task, slot);
1556 break;
1557 case SAS_PROTOCOL_SMP:
1558 ts->stat = SAM_STAT_CHECK_CONDITION;
1559 break;
1560 default:
1561 break;
1562 }
1563 }
1564
1565 static int
1566 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1567 {
1568 struct sas_task *task = slot->task;
1569 struct hisi_sas_device *sas_dev;
1570 struct device *dev = hisi_hba->dev;
1571 struct task_status_struct *ts;
1572 struct domain_device *device;
1573 enum exec_status sts;
1574 struct hisi_sas_complete_v3_hdr *complete_queue =
1575 hisi_hba->complete_hdr[slot->cmplt_queue];
1576 struct hisi_sas_complete_v3_hdr *complete_hdr =
1577 &complete_queue[slot->cmplt_queue_slot];
1578 int aborted;
1579 unsigned long flags;
1580
1581 if (unlikely(!task || !task->lldd_task || !task->dev))
1582 return -EINVAL;
1583
1584 ts = &task->task_status;
1585 device = task->dev;
1586 sas_dev = device->lldd_dev;
1587
1588 spin_lock_irqsave(&task->task_state_lock, flags);
1589 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1590 task->task_state_flags &=
1591 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1592 spin_unlock_irqrestore(&task->task_state_lock, flags);
1593
1594 memset(ts, 0, sizeof(*ts));
1595 ts->resp = SAS_TASK_COMPLETE;
1596 if (unlikely(aborted)) {
1597 dev_dbg(dev, "slot complete: task(%p) aborted\n", task);
1598 ts->stat = SAS_ABORTED_TASK;
1599 spin_lock_irqsave(&hisi_hba->lock, flags);
1600 hisi_sas_slot_task_free(hisi_hba, task, slot);
1601 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1602 return -1;
1603 }
1604
1605 if (unlikely(!sas_dev)) {
1606 dev_dbg(dev, "slot complete: port has not device\n");
1607 ts->stat = SAS_PHY_DOWN;
1608 goto out;
1609 }
1610
1611 /*
1612 * Use SAS+TMF status codes
1613 */
1614 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1615 >> CMPLT_HDR_ABORT_STAT_OFF) {
1616 case STAT_IO_ABORTED:
1617 /* this IO has been aborted by abort command */
1618 ts->stat = SAS_ABORTED_TASK;
1619 goto out;
1620 case STAT_IO_COMPLETE:
1621 /* internal abort command complete */
1622 ts->stat = TMF_RESP_FUNC_SUCC;
1623 goto out;
1624 case STAT_IO_NO_DEVICE:
1625 ts->stat = TMF_RESP_FUNC_COMPLETE;
1626 goto out;
1627 case STAT_IO_NOT_VALID:
1628 /*
1629 * abort single IO, the controller can't find the IO
1630 */
1631 ts->stat = TMF_RESP_FUNC_FAILED;
1632 goto out;
1633 default:
1634 break;
1635 }
1636
1637 /* check for erroneous completion */
1638 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1639 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
1640
1641 slot_err_v3_hw(hisi_hba, task, slot);
1642 if (ts->stat != SAS_DATA_UNDERRUN)
1643 dev_info(dev, "erroneous completion iptt=%d task=%p "
1644 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
1645 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
1646 slot->idx, task,
1647 complete_hdr->dw0, complete_hdr->dw1,
1648 complete_hdr->act, complete_hdr->dw3,
1649 error_info[0], error_info[1],
1650 error_info[2], error_info[3]);
1651 if (unlikely(slot->abort))
1652 return ts->stat;
1653 goto out;
1654 }
1655
1656 switch (task->task_proto) {
1657 case SAS_PROTOCOL_SSP: {
1658 struct ssp_response_iu *iu =
1659 hisi_sas_status_buf_addr_mem(slot) +
1660 sizeof(struct hisi_sas_err_record);
1661
1662 sas_ssp_task_response(dev, task, iu);
1663 break;
1664 }
1665 case SAS_PROTOCOL_SMP: {
1666 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1667 void *to;
1668
1669 ts->stat = SAM_STAT_GOOD;
1670 to = kmap_atomic(sg_page(sg_resp));
1671
1672 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1673 DMA_FROM_DEVICE);
1674 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1675 DMA_TO_DEVICE);
1676 memcpy(to + sg_resp->offset,
1677 hisi_sas_status_buf_addr_mem(slot) +
1678 sizeof(struct hisi_sas_err_record),
1679 sg_dma_len(sg_resp));
1680 kunmap_atomic(to);
1681 break;
1682 }
1683 case SAS_PROTOCOL_SATA:
1684 case SAS_PROTOCOL_STP:
1685 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1686 ts->stat = SAM_STAT_GOOD;
1687 hisi_sas_sata_done(task, slot);
1688 break;
1689 default:
1690 ts->stat = SAM_STAT_CHECK_CONDITION;
1691 break;
1692 }
1693
1694 if (!slot->port->port_attached) {
1695 dev_warn(dev, "slot complete: port %d has removed\n",
1696 slot->port->sas_port.id);
1697 ts->stat = SAS_PHY_DOWN;
1698 }
1699
1700 out:
1701 spin_lock_irqsave(&task->task_state_lock, flags);
1702 task->task_state_flags |= SAS_TASK_STATE_DONE;
1703 spin_unlock_irqrestore(&task->task_state_lock, flags);
1704 spin_lock_irqsave(&hisi_hba->lock, flags);
1705 hisi_sas_slot_task_free(hisi_hba, task, slot);
1706 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1707 sts = ts->stat;
1708
1709 if (task->task_done)
1710 task->task_done(task);
1711
1712 return sts;
1713 }
1714
1715 static void cq_tasklet_v3_hw(unsigned long val)
1716 {
1717 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1718 struct hisi_hba *hisi_hba = cq->hisi_hba;
1719 struct hisi_sas_slot *slot;
1720 struct hisi_sas_complete_v3_hdr *complete_queue;
1721 u32 rd_point = cq->rd_point, wr_point;
1722 int queue = cq->id;
1723 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
1724
1725 complete_queue = hisi_hba->complete_hdr[queue];
1726
1727 spin_lock(&dq->lock);
1728 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1729 (0x14 * queue));
1730
1731 while (rd_point != wr_point) {
1732 struct hisi_sas_complete_v3_hdr *complete_hdr;
1733 int iptt;
1734
1735 complete_hdr = &complete_queue[rd_point];
1736
1737 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1738 slot = &hisi_hba->slot_info[iptt];
1739 slot->cmplt_queue_slot = rd_point;
1740 slot->cmplt_queue = queue;
1741 slot_complete_v3_hw(hisi_hba, slot);
1742
1743 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1744 rd_point = 0;
1745 }
1746
1747 /* update rd_point */
1748 cq->rd_point = rd_point;
1749 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1750 spin_unlock(&dq->lock);
1751 }
1752
1753 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1754 {
1755 struct hisi_sas_cq *cq = p;
1756 struct hisi_hba *hisi_hba = cq->hisi_hba;
1757 int queue = cq->id;
1758
1759 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1760
1761 tasklet_schedule(&cq->tasklet);
1762
1763 return IRQ_HANDLED;
1764 }
1765
1766 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1767 {
1768 struct device *dev = hisi_hba->dev;
1769 struct pci_dev *pdev = hisi_hba->pci_dev;
1770 int vectors, rc;
1771 int i, k;
1772 int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1773
1774 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1775 max_msi, PCI_IRQ_MSI);
1776 if (vectors < max_msi) {
1777 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1778 return -ENOENT;
1779 }
1780
1781 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1782 int_phy_up_down_bcast_v3_hw, 0,
1783 DRV_NAME " phy", hisi_hba);
1784 if (rc) {
1785 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1786 rc = -ENOENT;
1787 goto free_irq_vectors;
1788 }
1789
1790 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1791 int_chnl_int_v3_hw, 0,
1792 DRV_NAME " channel", hisi_hba);
1793 if (rc) {
1794 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1795 rc = -ENOENT;
1796 goto free_phy_irq;
1797 }
1798
1799 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
1800 fatal_axi_int_v3_hw, 0,
1801 DRV_NAME " fatal", hisi_hba);
1802 if (rc) {
1803 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
1804 rc = -ENOENT;
1805 goto free_chnl_interrupt;
1806 }
1807
1808 /* Init tasklets for cq only */
1809 for (i = 0; i < hisi_hba->queue_count; i++) {
1810 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1811 struct tasklet_struct *t = &cq->tasklet;
1812
1813 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1814 cq_interrupt_v3_hw, 0,
1815 DRV_NAME " cq", cq);
1816 if (rc) {
1817 dev_err(dev,
1818 "could not request cq%d interrupt, rc=%d\n",
1819 i, rc);
1820 rc = -ENOENT;
1821 goto free_cq_irqs;
1822 }
1823
1824 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1825 }
1826
1827 return 0;
1828
1829 free_cq_irqs:
1830 for (k = 0; k < i; k++) {
1831 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1832
1833 free_irq(pci_irq_vector(pdev, k+16), cq);
1834 }
1835 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
1836 free_chnl_interrupt:
1837 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1838 free_phy_irq:
1839 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1840 free_irq_vectors:
1841 pci_free_irq_vectors(pdev);
1842 return rc;
1843 }
1844
1845 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1846 {
1847 int rc;
1848
1849 rc = hw_init_v3_hw(hisi_hba);
1850 if (rc)
1851 return rc;
1852
1853 rc = interrupt_init_v3_hw(hisi_hba);
1854 if (rc)
1855 return rc;
1856
1857 return 0;
1858 }
1859
1860 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
1861 struct sas_phy_linkrates *r)
1862 {
1863 u32 prog_phy_link_rate =
1864 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1865 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1866 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1867 int i;
1868 enum sas_linkrate min, max;
1869 u32 rate_mask = 0;
1870
1871 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1872 max = sas_phy->phy->maximum_linkrate;
1873 min = r->minimum_linkrate;
1874 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1875 max = r->maximum_linkrate;
1876 min = sas_phy->phy->minimum_linkrate;
1877 } else
1878 return;
1879
1880 sas_phy->phy->maximum_linkrate = max;
1881 sas_phy->phy->minimum_linkrate = min;
1882
1883 min -= SAS_LINK_RATE_1_5_GBPS;
1884 max -= SAS_LINK_RATE_1_5_GBPS;
1885
1886 for (i = 0; i <= max; i++)
1887 rate_mask |= 1 << (i * 2);
1888
1889 prog_phy_link_rate &= ~0xff;
1890 prog_phy_link_rate |= rate_mask;
1891
1892 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1893 prog_phy_link_rate);
1894
1895 phy_hard_reset_v3_hw(hisi_hba, phy_no);
1896 }
1897
1898 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
1899 {
1900 struct pci_dev *pdev = hisi_hba->pci_dev;
1901 int i;
1902
1903 synchronize_irq(pci_irq_vector(pdev, 1));
1904 synchronize_irq(pci_irq_vector(pdev, 2));
1905 synchronize_irq(pci_irq_vector(pdev, 11));
1906 for (i = 0; i < hisi_hba->queue_count; i++) {
1907 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
1908 synchronize_irq(pci_irq_vector(pdev, i + 16));
1909 }
1910
1911 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
1912 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
1913 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
1914 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1915
1916 for (i = 0; i < hisi_hba->n_phy; i++) {
1917 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1918 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
1919 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
1920 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
1921 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
1922 }
1923 }
1924
1925 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
1926 {
1927 return hisi_sas_read32(hisi_hba, PHY_STATE);
1928 }
1929
1930 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1931 {
1932 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1933 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1934 struct sas_phy *sphy = sas_phy->phy;
1935 u32 reg_value;
1936
1937 /* loss dword sync */
1938 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1939 sphy->loss_of_dword_sync_count += reg_value;
1940
1941 /* phy reset problem */
1942 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1943 sphy->phy_reset_problem_count += reg_value;
1944
1945 /* invalid dword */
1946 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1947 sphy->invalid_dword_count += reg_value;
1948
1949 /* disparity err */
1950 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1951 sphy->running_disparity_error_count += reg_value;
1952
1953 }
1954
1955 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
1956 {
1957 struct device *dev = hisi_hba->dev;
1958 int rc;
1959 u32 status;
1960
1961 interrupt_disable_v3_hw(hisi_hba);
1962 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
1963 hisi_sas_kill_tasklets(hisi_hba);
1964
1965 hisi_sas_stop_phys(hisi_hba);
1966
1967 mdelay(10);
1968
1969 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
1970
1971 /* wait until bus idle */
1972 rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
1973 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
1974 if (rc) {
1975 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
1976 return rc;
1977 }
1978
1979 hisi_sas_init_mem(hisi_hba);
1980
1981 return hw_init_v3_hw(hisi_hba);
1982 }
1983
1984 static const struct hisi_sas_hw hisi_sas_v3_hw = {
1985 .hw_init = hisi_sas_v3_init,
1986 .setup_itct = setup_itct_v3_hw,
1987 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
1988 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
1989 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
1990 .clear_itct = clear_itct_v3_hw,
1991 .sl_notify = sl_notify_v3_hw,
1992 .prep_ssp = prep_ssp_v3_hw,
1993 .prep_smp = prep_smp_v3_hw,
1994 .prep_stp = prep_ata_v3_hw,
1995 .prep_abort = prep_abort_v3_hw,
1996 .get_free_slot = get_free_slot_v3_hw,
1997 .start_delivery = start_delivery_v3_hw,
1998 .slot_complete = slot_complete_v3_hw,
1999 .phys_init = phys_init_v3_hw,
2000 .phy_start = start_phy_v3_hw,
2001 .phy_disable = disable_phy_v3_hw,
2002 .phy_hard_reset = phy_hard_reset_v3_hw,
2003 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
2004 .phy_set_linkrate = phy_set_linkrate_v3_hw,
2005 .dereg_device = dereg_device_v3_hw,
2006 .soft_reset = soft_reset_v3_hw,
2007 .get_phys_state = get_phys_state_v3_hw,
2008 .get_events = phy_get_events_v3_hw,
2009 };
2010
2011 static struct Scsi_Host *
2012 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
2013 {
2014 struct Scsi_Host *shost;
2015 struct hisi_hba *hisi_hba;
2016 struct device *dev = &pdev->dev;
2017
2018 shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
2019 if (!shost) {
2020 dev_err(dev, "shost alloc failed\n");
2021 return NULL;
2022 }
2023 hisi_hba = shost_priv(shost);
2024
2025 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
2026 hisi_hba->hw = &hisi_sas_v3_hw;
2027 hisi_hba->pci_dev = pdev;
2028 hisi_hba->dev = dev;
2029 hisi_hba->shost = shost;
2030 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
2031
2032 timer_setup(&hisi_hba->timer, NULL, 0);
2033
2034 if (hisi_sas_get_fw_info(hisi_hba) < 0)
2035 goto err_out;
2036
2037 if (hisi_sas_alloc(hisi_hba, shost)) {
2038 hisi_sas_free(hisi_hba);
2039 goto err_out;
2040 }
2041
2042 return shost;
2043 err_out:
2044 scsi_host_put(shost);
2045 dev_err(dev, "shost alloc failed\n");
2046 return NULL;
2047 }
2048
2049 static int
2050 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2051 {
2052 struct Scsi_Host *shost;
2053 struct hisi_hba *hisi_hba;
2054 struct device *dev = &pdev->dev;
2055 struct asd_sas_phy **arr_phy;
2056 struct asd_sas_port **arr_port;
2057 struct sas_ha_struct *sha;
2058 int rc, phy_nr, port_nr, i;
2059
2060 rc = pci_enable_device(pdev);
2061 if (rc)
2062 goto err_out;
2063
2064 pci_set_master(pdev);
2065
2066 rc = pci_request_regions(pdev, DRV_NAME);
2067 if (rc)
2068 goto err_out_disable_device;
2069
2070 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
2071 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
2072 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2073 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2074 dev_err(dev, "No usable DMA addressing method\n");
2075 rc = -EIO;
2076 goto err_out_regions;
2077 }
2078 }
2079
2080 shost = hisi_sas_shost_alloc_pci(pdev);
2081 if (!shost) {
2082 rc = -ENOMEM;
2083 goto err_out_regions;
2084 }
2085
2086 sha = SHOST_TO_SAS_HA(shost);
2087 hisi_hba = shost_priv(shost);
2088 dev_set_drvdata(dev, sha);
2089
2090 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
2091 if (!hisi_hba->regs) {
2092 dev_err(dev, "cannot map register.\n");
2093 rc = -ENOMEM;
2094 goto err_out_ha;
2095 }
2096
2097 phy_nr = port_nr = hisi_hba->n_phy;
2098
2099 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
2100 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
2101 if (!arr_phy || !arr_port) {
2102 rc = -ENOMEM;
2103 goto err_out_ha;
2104 }
2105
2106 sha->sas_phy = arr_phy;
2107 sha->sas_port = arr_port;
2108 sha->core.shost = shost;
2109 sha->lldd_ha = hisi_hba;
2110
2111 shost->transportt = hisi_sas_stt;
2112 shost->max_id = HISI_SAS_MAX_DEVICES;
2113 shost->max_lun = ~0;
2114 shost->max_channel = 1;
2115 shost->max_cmd_len = 16;
2116 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
2117 shost->can_queue = hisi_hba->hw->max_command_entries;
2118 shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
2119
2120 sha->sas_ha_name = DRV_NAME;
2121 sha->dev = dev;
2122 sha->lldd_module = THIS_MODULE;
2123 sha->sas_addr = &hisi_hba->sas_addr[0];
2124 sha->num_phys = hisi_hba->n_phy;
2125 sha->core.shost = hisi_hba->shost;
2126
2127 for (i = 0; i < hisi_hba->n_phy; i++) {
2128 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
2129 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
2130 }
2131
2132 hisi_sas_init_add(hisi_hba);
2133
2134 rc = scsi_add_host(shost, dev);
2135 if (rc)
2136 goto err_out_ha;
2137
2138 rc = sas_register_ha(sha);
2139 if (rc)
2140 goto err_out_register_ha;
2141
2142 rc = hisi_hba->hw->hw_init(hisi_hba);
2143 if (rc)
2144 goto err_out_register_ha;
2145
2146 scsi_scan_host(shost);
2147
2148 return 0;
2149
2150 err_out_register_ha:
2151 scsi_remove_host(shost);
2152 err_out_ha:
2153 scsi_host_put(shost);
2154 err_out_regions:
2155 pci_release_regions(pdev);
2156 err_out_disable_device:
2157 pci_disable_device(pdev);
2158 err_out:
2159 return rc;
2160 }
2161
2162 static void
2163 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
2164 {
2165 int i;
2166
2167 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2168 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2169 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2170 for (i = 0; i < hisi_hba->queue_count; i++) {
2171 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2172
2173 free_irq(pci_irq_vector(pdev, i+16), cq);
2174 }
2175 pci_free_irq_vectors(pdev);
2176 }
2177
2178 static void hisi_sas_v3_remove(struct pci_dev *pdev)
2179 {
2180 struct device *dev = &pdev->dev;
2181 struct sas_ha_struct *sha = dev_get_drvdata(dev);
2182 struct hisi_hba *hisi_hba = sha->lldd_ha;
2183 struct Scsi_Host *shost = sha->core.shost;
2184
2185 sas_unregister_ha(sha);
2186 sas_remove_host(sha->core.shost);
2187
2188 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
2189 hisi_sas_kill_tasklets(hisi_hba);
2190 pci_release_regions(pdev);
2191 pci_disable_device(pdev);
2192 hisi_sas_free(hisi_hba);
2193 scsi_host_put(shost);
2194 }
2195
2196 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = {
2197 { .irq_msk = BIT(19), .msg = "HILINK_INT" },
2198 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" },
2199 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" },
2200 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" },
2201 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" },
2202 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" },
2203 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" },
2204 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" },
2205 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" },
2206 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" },
2207 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" },
2208 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" },
2209 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" },
2210 };
2211
2212 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = {
2213 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" },
2214 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" },
2215 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" },
2216 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" },
2217 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" },
2218 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" },
2219 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" },
2220 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" },
2221 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" },
2222 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" },
2223 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" },
2224 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" },
2225 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" },
2226 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" },
2227 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" },
2228 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" },
2229 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" },
2230 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" },
2231 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" },
2232 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" },
2233 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" },
2234 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" },
2235 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" },
2236 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" },
2237 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" },
2238 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" },
2239 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" },
2240 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" },
2241 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" },
2242 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" },
2243 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" },
2244 };
2245
2246 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba)
2247 {
2248 struct device *dev = hisi_hba->dev;
2249 const struct hisi_sas_hw_error *ras_error;
2250 bool need_reset = false;
2251 u32 irq_value;
2252 int i;
2253
2254 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0);
2255 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) {
2256 ras_error = &sas_ras_intr0_nfe[i];
2257 if (ras_error->irq_msk & irq_value) {
2258 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n",
2259 ras_error->msg, irq_value);
2260 need_reset = true;
2261 }
2262 }
2263 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value);
2264
2265 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1);
2266 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) {
2267 ras_error = &sas_ras_intr1_nfe[i];
2268 if (ras_error->irq_msk & irq_value) {
2269 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n",
2270 ras_error->msg, irq_value);
2271 need_reset = true;
2272 }
2273 }
2274 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value);
2275
2276 return need_reset;
2277 }
2278
2279 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev,
2280 pci_channel_state_t state)
2281 {
2282 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2283 struct hisi_hba *hisi_hba = sha->lldd_ha;
2284 struct device *dev = hisi_hba->dev;
2285
2286 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state);
2287 if (state == pci_channel_io_perm_failure)
2288 return PCI_ERS_RESULT_DISCONNECT;
2289
2290 if (process_non_fatal_error_v3_hw(hisi_hba))
2291 return PCI_ERS_RESULT_NEED_RESET;
2292
2293 return PCI_ERS_RESULT_CAN_RECOVER;
2294 }
2295
2296 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev)
2297 {
2298 return PCI_ERS_RESULT_RECOVERED;
2299 }
2300
2301 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev)
2302 {
2303 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2304 struct hisi_hba *hisi_hba = sha->lldd_ha;
2305 struct device *dev = hisi_hba->dev;
2306 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r);
2307
2308 dev_info(dev, "PCI error: slot reset callback!!\n");
2309 queue_work(hisi_hba->wq, &r.work);
2310 wait_for_completion(r.completion);
2311 if (r.done)
2312 return PCI_ERS_RESULT_RECOVERED;
2313
2314 return PCI_ERS_RESULT_DISCONNECT;
2315 }
2316
2317 enum {
2318 /* instances of the controller */
2319 hip08,
2320 };
2321
2322 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state)
2323 {
2324 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2325 struct hisi_hba *hisi_hba = sha->lldd_ha;
2326 struct device *dev = hisi_hba->dev;
2327 struct Scsi_Host *shost = hisi_hba->shost;
2328 u32 device_state, status;
2329 int rc;
2330 u32 reg_val;
2331 unsigned long flags;
2332
2333 if (!pdev->pm_cap) {
2334 dev_err(dev, "PCI PM not supported\n");
2335 return -ENODEV;
2336 }
2337
2338 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2339 scsi_block_requests(shost);
2340 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2341 flush_workqueue(hisi_hba->wq);
2342 /* disable DQ/PHY/bus */
2343 interrupt_disable_v3_hw(hisi_hba);
2344 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2345 hisi_sas_kill_tasklets(hisi_hba);
2346
2347 hisi_sas_stop_phys(hisi_hba);
2348
2349 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2350 AM_CTRL_GLOBAL);
2351 reg_val |= 0x1;
2352 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2353 AM_CTRL_GLOBAL, reg_val);
2354
2355 /* wait until bus idle */
2356 rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
2357 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
2358 if (rc) {
2359 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
2360 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2361 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2362 scsi_unblock_requests(shost);
2363 return rc;
2364 }
2365
2366 hisi_sas_init_mem(hisi_hba);
2367
2368 device_state = pci_choose_state(pdev, state);
2369 dev_warn(dev, "entering operating state [D%d]\n",
2370 device_state);
2371 pci_save_state(pdev);
2372 pci_disable_device(pdev);
2373 pci_set_power_state(pdev, device_state);
2374
2375 spin_lock_irqsave(&hisi_hba->lock, flags);
2376 hisi_sas_release_tasks(hisi_hba);
2377 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2378
2379 sas_suspend_ha(sha);
2380 return 0;
2381 }
2382
2383 static int hisi_sas_v3_resume(struct pci_dev *pdev)
2384 {
2385 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2386 struct hisi_hba *hisi_hba = sha->lldd_ha;
2387 struct Scsi_Host *shost = hisi_hba->shost;
2388 struct device *dev = hisi_hba->dev;
2389 unsigned int rc;
2390 u32 device_state = pdev->current_state;
2391
2392 dev_warn(dev, "resuming from operating state [D%d]\n",
2393 device_state);
2394 pci_set_power_state(pdev, PCI_D0);
2395 pci_enable_wake(pdev, PCI_D0, 0);
2396 pci_restore_state(pdev);
2397 rc = pci_enable_device(pdev);
2398 if (rc)
2399 dev_err(dev, "enable device failed during resume (%d)\n", rc);
2400
2401 pci_set_master(pdev);
2402 scsi_unblock_requests(shost);
2403 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2404
2405 sas_prep_resume_ha(sha);
2406 init_reg_v3_hw(hisi_hba);
2407 hisi_hba->hw->phys_init(hisi_hba);
2408 sas_resume_ha(sha);
2409 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2410
2411 return 0;
2412 }
2413
2414 static const struct pci_device_id sas_v3_pci_table[] = {
2415 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
2416 {}
2417 };
2418 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
2419
2420 static const struct pci_error_handlers hisi_sas_err_handler = {
2421 .error_detected = hisi_sas_error_detected_v3_hw,
2422 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw,
2423 .slot_reset = hisi_sas_slot_reset_v3_hw,
2424 };
2425
2426 static struct pci_driver sas_v3_pci_driver = {
2427 .name = DRV_NAME,
2428 .id_table = sas_v3_pci_table,
2429 .probe = hisi_sas_v3_probe,
2430 .remove = hisi_sas_v3_remove,
2431 .suspend = hisi_sas_v3_suspend,
2432 .resume = hisi_sas_v3_resume,
2433 .err_handler = &hisi_sas_err_handler,
2434 };
2435
2436 module_pci_driver(sas_v3_pci_driver);
2437
2438 MODULE_LICENSE("GPL");
2439 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2440 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2441 MODULE_ALIAS("platform:" DRV_NAME);
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