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scsi: hisi_sas: config ATA de-reset as an constrained command for v3 hw
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v3_hw.c
1 /*
2 * Copyright (c) 2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 #include "hisi_sas.h"
12 #define DRV_NAME "hisi_sas_v3_hw"
13
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
26 #define ITCT_CLR 0x44
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CFG_1US_TIMER_TRSH 0xcc
55 #define CHNL_INT_STATUS 0x148
56 #define HGC_AXI_FIFO_ERR_INFO 0x154
57 #define AXI_ERR_INFO_OFF 0
58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
59 #define FIFO_ERR_INFO_OFF 8
60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
61 #define INT_COAL_EN 0x19c
62 #define OQ_INT_COAL_TIME 0x1a0
63 #define OQ_INT_COAL_CNT 0x1a4
64 #define ENT_INT_COAL_TIME 0x1a8
65 #define ENT_INT_COAL_CNT 0x1ac
66 #define OQ_INT_SRC 0x1b0
67 #define OQ_INT_SRC_MSK 0x1b4
68 #define ENT_INT_SRC1 0x1b8
69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
73 #define ENT_INT_SRC2 0x1bc
74 #define ENT_INT_SRC3 0x1c0
75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
78 #define ENT_INT_SRC3_AXI_OFF 11
79 #define ENT_INT_SRC3_FIFO_OFF 12
80 #define ENT_INT_SRC3_LM_OFF 14
81 #define ENT_INT_SRC3_ITC_INT_OFF 15
82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
83 #define ENT_INT_SRC3_ABT_OFF 16
84 #define ENT_INT_SRC_MSK1 0x1c4
85 #define ENT_INT_SRC_MSK2 0x1c8
86 #define ENT_INT_SRC_MSK3 0x1cc
87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
89 #define CHNL_ENT_INT_MSK 0x1d4
90 #define HGC_COM_INT_MSK 0x1d8
91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
92 #define SAS_ECC_INTR 0x1e8
93 #define SAS_ECC_INTR_MSK 0x1ec
94 #define HGC_ERR_STAT_EN 0x238
95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
97 #define DLVRY_Q_0_DEPTH 0x268
98 #define DLVRY_Q_0_WR_PTR 0x26c
99 #define DLVRY_Q_0_RD_PTR 0x270
100 #define HYPER_STREAM_ID_EN_CFG 0xc80
101 #define OQ0_INT_SRC_MSK 0xc90
102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
104 #define COMPL_Q_0_DEPTH 0x4e8
105 #define COMPL_Q_0_WR_PTR 0x4ec
106 #define COMPL_Q_0_RD_PTR 0x4f0
107 #define AWQOS_AWCACHE_CFG 0xc84
108 #define ARQOS_ARCACHE_CFG 0xc88
109
110 /* phy registers requiring init */
111 #define PORT_BASE (0x2000)
112 #define PHY_CFG (PORT_BASE + 0x0)
113 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
114 #define PHY_CFG_ENA_OFF 0
115 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
116 #define PHY_CFG_DC_OPT_OFF 2
117 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
118 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
119 #define PHY_CTRL (PORT_BASE + 0x14)
120 #define PHY_CTRL_RESET_OFF 0
121 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
122 #define SL_CFG (PORT_BASE + 0x84)
123 #define SL_CONTROL (PORT_BASE + 0x94)
124 #define SL_CONTROL_NOTIFY_EN_OFF 0
125 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
126 #define SL_CTA_OFF 17
127 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
128 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
129 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
130 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
131 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
132 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
133 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
134 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
135 #define TXID_AUTO (PORT_BASE + 0xb8)
136 #define CT3_OFF 1
137 #define CT3_MSK (0x1 << CT3_OFF)
138 #define TX_HARDRST_OFF 2
139 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
140 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
141 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
142 #define STP_LINK_TIMER (PORT_BASE + 0x120)
143 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
144 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
145 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
146 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
147 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
148 #define CHL_INT0 (PORT_BASE + 0x1b4)
149 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
150 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
151 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
152 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
153 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
154 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
155 #define CHL_INT0_NOT_RDY_OFF 4
156 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
157 #define CHL_INT0_PHY_RDY_OFF 5
158 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
159 #define CHL_INT1 (PORT_BASE + 0x1b8)
160 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
161 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
162 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
163 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
164 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
165 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
166 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
167 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
168 #define CHL_INT2 (PORT_BASE + 0x1bc)
169 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
170 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
171 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
172 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
173 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
174 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
175 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
176 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
177 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
178 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
179 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
180 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
181 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
182 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
183 #define DMA_TX_STATUS_BUSY_OFF 0
184 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
185 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
186 #define DMA_RX_STATUS_BUSY_OFF 0
187 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
188
189 #define COARSETUNE_TIME (PORT_BASE + 0x304)
190 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
191 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
192 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
193 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
194
195 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
196 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
197 #error Max ITCT exceeded
198 #endif
199
200 #define AXI_MASTER_CFG_BASE (0x5000)
201 #define AM_CTRL_GLOBAL (0x0)
202 #define AM_CURR_TRANS_RETURN (0x150)
203
204 #define AM_CFG_MAX_TRANS (0x5010)
205 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
206 #define AXI_CFG (0x5100)
207 #define AM_ROB_ECC_ERR_ADDR (0x510c)
208 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
209 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
210 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
211 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
212
213 /* RAS registers need init */
214 #define RAS_BASE (0x6000)
215 #define SAS_RAS_INTR0 (RAS_BASE)
216 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
217 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
218 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
219 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c)
220 #define SAS_RAS_INTR2 (RAS_BASE + 0x20)
221 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24)
222
223 /* HW dma structures */
224 /* Delivery queue header */
225 /* dw0 */
226 #define CMD_HDR_ABORT_FLAG_OFF 0
227 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
228 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
229 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
230 #define CMD_HDR_RESP_REPORT_OFF 5
231 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
232 #define CMD_HDR_TLR_CTRL_OFF 6
233 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
234 #define CMD_HDR_PORT_OFF 18
235 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
236 #define CMD_HDR_PRIORITY_OFF 27
237 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
238 #define CMD_HDR_CMD_OFF 29
239 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
240 /* dw1 */
241 #define CMD_HDR_UNCON_CMD_OFF 3
242 #define CMD_HDR_DIR_OFF 5
243 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
244 #define CMD_HDR_RESET_OFF 7
245 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
246 #define CMD_HDR_VDTL_OFF 10
247 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
248 #define CMD_HDR_FRAME_TYPE_OFF 11
249 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
250 #define CMD_HDR_DEV_ID_OFF 16
251 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
252 /* dw2 */
253 #define CMD_HDR_CFL_OFF 0
254 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
255 #define CMD_HDR_NCQ_TAG_OFF 10
256 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
257 #define CMD_HDR_MRFL_OFF 15
258 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
259 #define CMD_HDR_SG_MOD_OFF 24
260 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
261 /* dw3 */
262 #define CMD_HDR_IPTT_OFF 0
263 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
264 /* dw6 */
265 #define CMD_HDR_DIF_SGL_LEN_OFF 0
266 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
267 #define CMD_HDR_DATA_SGL_LEN_OFF 16
268 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
269 /* dw7 */
270 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
271 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
272 #define CMD_HDR_ABORT_IPTT_OFF 16
273 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
274
275 /* Completion header */
276 /* dw0 */
277 #define CMPLT_HDR_CMPLT_OFF 0
278 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
279 #define CMPLT_HDR_ERROR_PHASE_OFF 2
280 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
281 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
282 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
283 #define CMPLT_HDR_ERX_OFF 12
284 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
285 #define CMPLT_HDR_ABORT_STAT_OFF 13
286 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
287 /* abort_stat */
288 #define STAT_IO_NOT_VALID 0x1
289 #define STAT_IO_NO_DEVICE 0x2
290 #define STAT_IO_COMPLETE 0x3
291 #define STAT_IO_ABORTED 0x4
292 /* dw1 */
293 #define CMPLT_HDR_IPTT_OFF 0
294 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
295 #define CMPLT_HDR_DEV_ID_OFF 16
296 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
297 /* dw3 */
298 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
299 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
300
301 /* ITCT header */
302 /* qw0 */
303 #define ITCT_HDR_DEV_TYPE_OFF 0
304 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
305 #define ITCT_HDR_VALID_OFF 2
306 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
307 #define ITCT_HDR_MCR_OFF 5
308 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
309 #define ITCT_HDR_VLN_OFF 9
310 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
311 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
312 #define ITCT_HDR_AWT_CONTINUE_OFF 25
313 #define ITCT_HDR_PORT_ID_OFF 28
314 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
315 /* qw2 */
316 #define ITCT_HDR_INLT_OFF 0
317 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
318 #define ITCT_HDR_RTOLT_OFF 48
319 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
320
321 struct hisi_sas_complete_v3_hdr {
322 __le32 dw0;
323 __le32 dw1;
324 __le32 act;
325 __le32 dw3;
326 };
327
328 struct hisi_sas_err_record_v3 {
329 /* dw0 */
330 __le32 trans_tx_fail_type;
331
332 /* dw1 */
333 __le32 trans_rx_fail_type;
334
335 /* dw2 */
336 __le16 dma_tx_err_type;
337 __le16 sipc_rx_err_type;
338
339 /* dw3 */
340 __le32 dma_rx_err_type;
341 };
342
343 #define RX_DATA_LEN_UNDERFLOW_OFF 6
344 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
345
346 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
347 #define HISI_SAS_MSI_COUNT_V3_HW 32
348
349 #define DIR_NO_DATA 0
350 #define DIR_TO_INI 1
351 #define DIR_TO_DEVICE 2
352 #define DIR_RESERVED 3
353
354 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
355 ((fis.command == ATA_CMD_READ_LOG_EXT) || \
356 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
357 ((fis.command == ATA_CMD_DEV_RESET) && \
358 ((fis.control & ATA_SRST) != 0)))
359
360 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
361 {
362 void __iomem *regs = hisi_hba->regs + off;
363
364 return readl(regs);
365 }
366
367 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
368 {
369 void __iomem *regs = hisi_hba->regs + off;
370
371 return readl_relaxed(regs);
372 }
373
374 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
375 {
376 void __iomem *regs = hisi_hba->regs + off;
377
378 writel(val, regs);
379 }
380
381 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
382 u32 off, u32 val)
383 {
384 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
385
386 writel(val, regs);
387 }
388
389 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
390 int phy_no, u32 off)
391 {
392 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
393
394 return readl(regs);
395 }
396
397 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
398 {
399 struct pci_dev *pdev = hisi_hba->pci_dev;
400 int i;
401
402 /* Global registers init */
403 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
404 (u32)((1ULL << hisi_hba->queue_count) - 1));
405 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
406 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
407 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
408 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
409 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
410 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
411 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
412 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
413 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
414 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
415 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
416 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
417 if (pdev->revision >= 0x21)
418 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7fff);
419 else
420 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff);
421 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
422 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
423 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
424 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
425 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
426 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
427 for (i = 0; i < hisi_hba->queue_count; i++)
428 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
429
430 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
431
432 for (i = 0; i < hisi_hba->n_phy; i++) {
433 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
434 struct asd_sas_phy *sas_phy = &phy->sas_phy;
435 u32 prog_phy_link_rate = 0x800;
436
437 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
438 SAS_LINK_RATE_1_5_GBPS)) {
439 prog_phy_link_rate = 0x855;
440 } else {
441 enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
442
443 prog_phy_link_rate =
444 hisi_sas_get_prog_phy_linkrate_mask(max) |
445 0x800;
446 }
447 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
448 prog_phy_link_rate);
449 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
450 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
451 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
452 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
453 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
454 if (pdev->revision >= 0x21)
455 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
456 0xffffffff);
457 else
458 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
459 0xff87ffff);
460 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
461 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
462 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
463 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
464 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
465 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
466 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
467 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
468
469 /* used for 12G negotiate */
470 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
471 }
472
473 for (i = 0; i < hisi_hba->queue_count; i++) {
474 /* Delivery queue */
475 hisi_sas_write32(hisi_hba,
476 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
477 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
478
479 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
480 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
481
482 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
483 HISI_SAS_QUEUE_SLOTS);
484
485 /* Completion queue */
486 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
487 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
488
489 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
490 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
491
492 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
493 HISI_SAS_QUEUE_SLOTS);
494 }
495
496 /* itct */
497 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
498 lower_32_bits(hisi_hba->itct_dma));
499
500 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
501 upper_32_bits(hisi_hba->itct_dma));
502
503 /* iost */
504 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
505 lower_32_bits(hisi_hba->iost_dma));
506
507 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
508 upper_32_bits(hisi_hba->iost_dma));
509
510 /* breakpoint */
511 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
512 lower_32_bits(hisi_hba->breakpoint_dma));
513
514 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
515 upper_32_bits(hisi_hba->breakpoint_dma));
516
517 /* SATA broken msg */
518 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
519 lower_32_bits(hisi_hba->sata_breakpoint_dma));
520
521 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
522 upper_32_bits(hisi_hba->sata_breakpoint_dma));
523
524 /* SATA initial fis */
525 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
526 lower_32_bits(hisi_hba->initial_fis_dma));
527
528 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
529 upper_32_bits(hisi_hba->initial_fis_dma));
530
531 /* RAS registers init */
532 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
533 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
534 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
535 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
536 }
537
538 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
539 {
540 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
541
542 cfg &= ~PHY_CFG_DC_OPT_MSK;
543 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
544 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
545 }
546
547 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
548 {
549 struct sas_identify_frame identify_frame;
550 u32 *identify_buffer;
551
552 memset(&identify_frame, 0, sizeof(identify_frame));
553 identify_frame.dev_type = SAS_END_DEVICE;
554 identify_frame.frame_type = 0;
555 identify_frame._un1 = 1;
556 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
557 identify_frame.target_bits = SAS_PROTOCOL_NONE;
558 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
559 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
560 identify_frame.phy_id = phy_no;
561 identify_buffer = (u32 *)(&identify_frame);
562
563 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
564 __swab32(identify_buffer[0]));
565 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
566 __swab32(identify_buffer[1]));
567 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
568 __swab32(identify_buffer[2]));
569 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
570 __swab32(identify_buffer[3]));
571 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
572 __swab32(identify_buffer[4]));
573 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
574 __swab32(identify_buffer[5]));
575 }
576
577 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
578 struct hisi_sas_device *sas_dev)
579 {
580 struct domain_device *device = sas_dev->sas_device;
581 struct device *dev = hisi_hba->dev;
582 u64 qw0, device_id = sas_dev->device_id;
583 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
584 struct domain_device *parent_dev = device->parent;
585 struct asd_sas_port *sas_port = device->port;
586 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
587
588 memset(itct, 0, sizeof(*itct));
589
590 /* qw0 */
591 qw0 = 0;
592 switch (sas_dev->dev_type) {
593 case SAS_END_DEVICE:
594 case SAS_EDGE_EXPANDER_DEVICE:
595 case SAS_FANOUT_EXPANDER_DEVICE:
596 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
597 break;
598 case SAS_SATA_DEV:
599 case SAS_SATA_PENDING:
600 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
601 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
602 else
603 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
604 break;
605 default:
606 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
607 sas_dev->dev_type);
608 }
609
610 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
611 (device->linkrate << ITCT_HDR_MCR_OFF) |
612 (1 << ITCT_HDR_VLN_OFF) |
613 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
614 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
615 (port->id << ITCT_HDR_PORT_ID_OFF));
616 itct->qw0 = cpu_to_le64(qw0);
617
618 /* qw1 */
619 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
620 itct->sas_addr = __swab64(itct->sas_addr);
621
622 /* qw2 */
623 if (!dev_is_sata(device))
624 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
625 (0x1ULL << ITCT_HDR_RTOLT_OFF));
626 }
627
628 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba,
629 struct hisi_sas_device *sas_dev)
630 {
631 DECLARE_COMPLETION_ONSTACK(completion);
632 u64 dev_id = sas_dev->device_id;
633 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
634 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
635
636 sas_dev->completion = &completion;
637
638 /* clear the itct interrupt state */
639 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
640 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
641 ENT_INT_SRC3_ITC_INT_MSK);
642
643 /* clear the itct table*/
644 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
645 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
646
647 wait_for_completion(sas_dev->completion);
648 memset(itct, 0, sizeof(struct hisi_sas_itct));
649 }
650
651 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
652 struct domain_device *device)
653 {
654 struct hisi_sas_slot *slot, *slot2;
655 struct hisi_sas_device *sas_dev = device->lldd_dev;
656 u32 cfg_abt_set_query_iptt;
657
658 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
659 CFG_ABT_SET_QUERY_IPTT);
660 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
661 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
662 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
663 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
664 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
665 cfg_abt_set_query_iptt);
666 }
667 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
668 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
669 cfg_abt_set_query_iptt);
670 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
671 1 << CFG_ABT_SET_IPTT_DONE_OFF);
672 }
673
674 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
675 {
676 struct device *dev = hisi_hba->dev;
677 int ret;
678 u32 val;
679
680 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
681
682 /* Disable all of the PHYs */
683 hisi_sas_stop_phys(hisi_hba);
684 udelay(50);
685
686 /* Ensure axi bus idle */
687 ret = readl_poll_timeout(hisi_hba->regs + AXI_CFG, val, !val,
688 20000, 1000000);
689 if (ret) {
690 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
691 return -EIO;
692 }
693
694 if (ACPI_HANDLE(dev)) {
695 acpi_status s;
696
697 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
698 if (ACPI_FAILURE(s)) {
699 dev_err(dev, "Reset failed\n");
700 return -EIO;
701 }
702 } else {
703 dev_err(dev, "no reset method!\n");
704 return -EINVAL;
705 }
706
707 return 0;
708 }
709
710 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
711 {
712 struct device *dev = hisi_hba->dev;
713 int rc;
714
715 rc = reset_hw_v3_hw(hisi_hba);
716 if (rc) {
717 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
718 return rc;
719 }
720
721 msleep(100);
722 init_reg_v3_hw(hisi_hba);
723
724 return 0;
725 }
726
727 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
728 {
729 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
730
731 cfg |= PHY_CFG_ENA_MSK;
732 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
733 }
734
735 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
736 {
737 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
738
739 cfg &= ~PHY_CFG_ENA_MSK;
740 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
741 }
742
743 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
744 {
745 config_id_frame_v3_hw(hisi_hba, phy_no);
746 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
747 enable_phy_v3_hw(hisi_hba, phy_no);
748 }
749
750 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
751 {
752 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
753 u32 txid_auto;
754
755 disable_phy_v3_hw(hisi_hba, phy_no);
756 if (phy->identify.device_type == SAS_END_DEVICE) {
757 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
758 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
759 txid_auto | TX_HARDRST_MSK);
760 }
761 msleep(100);
762 start_phy_v3_hw(hisi_hba, phy_no);
763 }
764
765 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
766 {
767 return SAS_LINK_RATE_12_0_GBPS;
768 }
769
770 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
771 {
772 int i;
773
774 for (i = 0; i < hisi_hba->n_phy; i++) {
775 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
776 struct asd_sas_phy *sas_phy = &phy->sas_phy;
777
778 if (!sas_phy->phy->enabled)
779 continue;
780
781 start_phy_v3_hw(hisi_hba, i);
782 }
783 }
784
785 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
786 {
787 u32 sl_control;
788
789 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
790 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
791 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
792 msleep(1);
793 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
794 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
795 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
796 }
797
798 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
799 {
800 int i, bitmap = 0;
801 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
802 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
803
804 for (i = 0; i < hisi_hba->n_phy; i++)
805 if (phy_state & BIT(i))
806 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
807 bitmap |= BIT(i);
808
809 return bitmap;
810 }
811
812 /**
813 * The callpath to this function and upto writing the write
814 * queue pointer should be safe from interruption.
815 */
816 static int
817 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
818 {
819 struct device *dev = hisi_hba->dev;
820 int queue = dq->id;
821 u32 r, w;
822
823 w = dq->wr_point;
824 r = hisi_sas_read32_relaxed(hisi_hba,
825 DLVRY_Q_0_RD_PTR + (queue * 0x14));
826 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
827 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
828 queue, r, w);
829 return -EAGAIN;
830 }
831
832 return 0;
833 }
834
835 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
836 {
837 struct hisi_hba *hisi_hba = dq->hisi_hba;
838 int dlvry_queue = dq->slot_prep->dlvry_queue;
839 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
840
841 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
842 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
843 dq->wr_point);
844 }
845
846 static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
847 struct hisi_sas_slot *slot,
848 struct hisi_sas_cmd_hdr *hdr,
849 struct scatterlist *scatter,
850 int n_elem)
851 {
852 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
853 struct device *dev = hisi_hba->dev;
854 struct scatterlist *sg;
855 int i;
856
857 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
858 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
859 n_elem);
860 return -EINVAL;
861 }
862
863 for_each_sg(scatter, sg, n_elem, i) {
864 struct hisi_sas_sge *entry = &sge_page->sge[i];
865
866 entry->addr = cpu_to_le64(sg_dma_address(sg));
867 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
868 entry->data_len = cpu_to_le32(sg_dma_len(sg));
869 entry->data_off = 0;
870 }
871
872 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
873
874 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
875
876 return 0;
877 }
878
879 static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
880 struct hisi_sas_slot *slot, int is_tmf,
881 struct hisi_sas_tmf_task *tmf)
882 {
883 struct sas_task *task = slot->task;
884 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
885 struct domain_device *device = task->dev;
886 struct hisi_sas_device *sas_dev = device->lldd_dev;
887 struct hisi_sas_port *port = slot->port;
888 struct sas_ssp_task *ssp_task = &task->ssp_task;
889 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
890 int has_data = 0, rc, priority = is_tmf;
891 u8 *buf_cmd;
892 u32 dw1 = 0, dw2 = 0;
893
894 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
895 (2 << CMD_HDR_TLR_CTRL_OFF) |
896 (port->id << CMD_HDR_PORT_OFF) |
897 (priority << CMD_HDR_PRIORITY_OFF) |
898 (1 << CMD_HDR_CMD_OFF)); /* ssp */
899
900 dw1 = 1 << CMD_HDR_VDTL_OFF;
901 if (is_tmf) {
902 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
903 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
904 } else {
905 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
906 switch (scsi_cmnd->sc_data_direction) {
907 case DMA_TO_DEVICE:
908 has_data = 1;
909 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
910 break;
911 case DMA_FROM_DEVICE:
912 has_data = 1;
913 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
914 break;
915 default:
916 dw1 &= ~CMD_HDR_DIR_MSK;
917 }
918 }
919
920 /* map itct entry */
921 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
922 hdr->dw1 = cpu_to_le32(dw1);
923
924 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
925 + 3) / 4) << CMD_HDR_CFL_OFF) |
926 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
927 (2 << CMD_HDR_SG_MOD_OFF);
928 hdr->dw2 = cpu_to_le32(dw2);
929 hdr->transfer_tags = cpu_to_le32(slot->idx);
930
931 if (has_data) {
932 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
933 slot->n_elem);
934 if (rc)
935 return rc;
936 }
937
938 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
939 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
940 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
941
942 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
943 sizeof(struct ssp_frame_hdr);
944
945 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
946 if (!is_tmf) {
947 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
948 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
949 } else {
950 buf_cmd[10] = tmf->tmf;
951 switch (tmf->tmf) {
952 case TMF_ABORT_TASK:
953 case TMF_QUERY_TASK:
954 buf_cmd[12] =
955 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
956 buf_cmd[13] =
957 tmf->tag_of_task_to_be_managed & 0xff;
958 break;
959 default:
960 break;
961 }
962 }
963
964 return 0;
965 }
966
967 static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
968 struct hisi_sas_slot *slot)
969 {
970 struct sas_task *task = slot->task;
971 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
972 struct domain_device *device = task->dev;
973 struct device *dev = hisi_hba->dev;
974 struct hisi_sas_port *port = slot->port;
975 struct scatterlist *sg_req, *sg_resp;
976 struct hisi_sas_device *sas_dev = device->lldd_dev;
977 dma_addr_t req_dma_addr;
978 unsigned int req_len, resp_len;
979 int elem, rc;
980
981 /*
982 * DMA-map SMP request, response buffers
983 */
984 /* req */
985 sg_req = &task->smp_task.smp_req;
986 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
987 if (!elem)
988 return -ENOMEM;
989 req_len = sg_dma_len(sg_req);
990 req_dma_addr = sg_dma_address(sg_req);
991
992 /* resp */
993 sg_resp = &task->smp_task.smp_resp;
994 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
995 if (!elem) {
996 rc = -ENOMEM;
997 goto err_out_req;
998 }
999 resp_len = sg_dma_len(sg_resp);
1000 if ((req_len & 0x3) || (resp_len & 0x3)) {
1001 rc = -EINVAL;
1002 goto err_out_resp;
1003 }
1004
1005 /* create header */
1006 /* dw0 */
1007 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1008 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1009 (2 << CMD_HDR_CMD_OFF)); /* smp */
1010
1011 /* map itct entry */
1012 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1013 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1014 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1015
1016 /* dw2 */
1017 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1018 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1019 CMD_HDR_MRFL_OFF));
1020
1021 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1022
1023 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1024 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1025
1026 return 0;
1027
1028 err_out_resp:
1029 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1030 DMA_FROM_DEVICE);
1031 err_out_req:
1032 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1033 DMA_TO_DEVICE);
1034 return rc;
1035 }
1036
1037 static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1038 struct hisi_sas_slot *slot)
1039 {
1040 struct sas_task *task = slot->task;
1041 struct domain_device *device = task->dev;
1042 struct domain_device *parent_dev = device->parent;
1043 struct hisi_sas_device *sas_dev = device->lldd_dev;
1044 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1045 struct asd_sas_port *sas_port = device->port;
1046 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1047 u8 *buf_cmd;
1048 int has_data = 0, rc = 0, hdr_tag = 0;
1049 u32 dw1 = 0, dw2 = 0;
1050
1051 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1052 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1053 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1054 else
1055 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1056
1057 switch (task->data_dir) {
1058 case DMA_TO_DEVICE:
1059 has_data = 1;
1060 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1061 break;
1062 case DMA_FROM_DEVICE:
1063 has_data = 1;
1064 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1065 break;
1066 default:
1067 dw1 &= ~CMD_HDR_DIR_MSK;
1068 }
1069
1070 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1071 (task->ata_task.fis.control & ATA_SRST))
1072 dw1 |= 1 << CMD_HDR_RESET_OFF;
1073
1074 dw1 |= (hisi_sas_get_ata_protocol(
1075 &task->ata_task.fis, task->data_dir))
1076 << CMD_HDR_FRAME_TYPE_OFF;
1077 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1078
1079 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1080 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1081
1082 hdr->dw1 = cpu_to_le32(dw1);
1083
1084 /* dw2 */
1085 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
1086 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1087 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1088 }
1089
1090 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1091 2 << CMD_HDR_SG_MOD_OFF;
1092 hdr->dw2 = cpu_to_le32(dw2);
1093
1094 /* dw3 */
1095 hdr->transfer_tags = cpu_to_le32(slot->idx);
1096
1097 if (has_data) {
1098 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1099 slot->n_elem);
1100 if (rc)
1101 return rc;
1102 }
1103
1104 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1105 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1106 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1107
1108 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1109
1110 if (likely(!task->ata_task.device_control_reg_update))
1111 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1112 /* fill in command FIS */
1113 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1114
1115 return 0;
1116 }
1117
1118 static int prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1119 struct hisi_sas_slot *slot,
1120 int device_id, int abort_flag, int tag_to_abort)
1121 {
1122 struct sas_task *task = slot->task;
1123 struct domain_device *dev = task->dev;
1124 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1125 struct hisi_sas_port *port = slot->port;
1126
1127 /* dw0 */
1128 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1129 (port->id << CMD_HDR_PORT_OFF) |
1130 (dev_is_sata(dev)
1131 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1132 (abort_flag
1133 << CMD_HDR_ABORT_FLAG_OFF));
1134
1135 /* dw1 */
1136 hdr->dw1 = cpu_to_le32(device_id
1137 << CMD_HDR_DEV_ID_OFF);
1138
1139 /* dw7 */
1140 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1141 hdr->transfer_tags = cpu_to_le32(slot->idx);
1142
1143 return 0;
1144 }
1145
1146 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1147 {
1148 int i, res;
1149 u32 context, port_id, link_rate;
1150 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1151 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1152 struct device *dev = hisi_hba->dev;
1153
1154 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1155
1156 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1157 port_id = (port_id >> (4 * phy_no)) & 0xf;
1158 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1159 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1160
1161 if (port_id == 0xf) {
1162 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1163 res = IRQ_NONE;
1164 goto end;
1165 }
1166 sas_phy->linkrate = link_rate;
1167 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1168
1169 /* Check for SATA dev */
1170 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1171 if (context & (1 << phy_no)) {
1172 struct hisi_sas_initial_fis *initial_fis;
1173 struct dev_to_host_fis *fis;
1174 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1175
1176 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1177 initial_fis = &hisi_hba->initial_fis[phy_no];
1178 fis = &initial_fis->fis;
1179 sas_phy->oob_mode = SATA_OOB_MODE;
1180 attached_sas_addr[0] = 0x50;
1181 attached_sas_addr[7] = phy_no;
1182 memcpy(sas_phy->attached_sas_addr,
1183 attached_sas_addr,
1184 SAS_ADDR_SIZE);
1185 memcpy(sas_phy->frame_rcvd, fis,
1186 sizeof(struct dev_to_host_fis));
1187 phy->phy_type |= PORT_TYPE_SATA;
1188 phy->identify.device_type = SAS_SATA_DEV;
1189 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1190 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1191 } else {
1192 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1193 struct sas_identify_frame *id =
1194 (struct sas_identify_frame *)frame_rcvd;
1195
1196 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1197 for (i = 0; i < 6; i++) {
1198 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1199 RX_IDAF_DWORD0 + (i * 4));
1200 frame_rcvd[i] = __swab32(idaf);
1201 }
1202 sas_phy->oob_mode = SAS_OOB_MODE;
1203 memcpy(sas_phy->attached_sas_addr,
1204 &id->sas_addr,
1205 SAS_ADDR_SIZE);
1206 phy->phy_type |= PORT_TYPE_SAS;
1207 phy->identify.device_type = id->dev_type;
1208 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1209 if (phy->identify.device_type == SAS_END_DEVICE)
1210 phy->identify.target_port_protocols =
1211 SAS_PROTOCOL_SSP;
1212 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1213 phy->identify.target_port_protocols =
1214 SAS_PROTOCOL_SMP;
1215 }
1216
1217 phy->port_id = port_id;
1218 phy->phy_attached = 1;
1219 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1220 res = IRQ_HANDLED;
1221 end:
1222 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1223 CHL_INT0_SL_PHY_ENABLE_MSK);
1224 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1225
1226 return res;
1227 }
1228
1229 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1230 {
1231 u32 phy_state, sl_ctrl, txid_auto;
1232 struct device *dev = hisi_hba->dev;
1233
1234 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1235
1236 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1237 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1238 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1239
1240 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1241 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1242 sl_ctrl&(~SL_CTA_MSK));
1243
1244 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1245 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1246 txid_auto | CT3_MSK);
1247
1248 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1249 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1250
1251 return IRQ_HANDLED;
1252 }
1253
1254 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1255 {
1256 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1257 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1258 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1259
1260 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1261 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1262 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1263 CHL_INT0_SL_RX_BCST_ACK_MSK);
1264 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1265
1266 return IRQ_HANDLED;
1267 }
1268
1269 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1270 {
1271 struct hisi_hba *hisi_hba = p;
1272 u32 irq_msk;
1273 int phy_no = 0;
1274 irqreturn_t res = IRQ_NONE;
1275
1276 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1277 & 0x11111111;
1278 while (irq_msk) {
1279 if (irq_msk & 1) {
1280 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1281 CHL_INT0);
1282 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1283 int rdy = phy_state & (1 << phy_no);
1284
1285 if (rdy) {
1286 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1287 /* phy up */
1288 if (phy_up_v3_hw(phy_no, hisi_hba)
1289 == IRQ_HANDLED)
1290 res = IRQ_HANDLED;
1291 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1292 /* phy bcast */
1293 if (phy_bcast_v3_hw(phy_no, hisi_hba)
1294 == IRQ_HANDLED)
1295 res = IRQ_HANDLED;
1296 } else {
1297 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1298 /* phy down */
1299 if (phy_down_v3_hw(phy_no, hisi_hba)
1300 == IRQ_HANDLED)
1301 res = IRQ_HANDLED;
1302 }
1303 }
1304 irq_msk >>= 4;
1305 phy_no++;
1306 }
1307
1308 return res;
1309 }
1310
1311 static const struct hisi_sas_hw_error port_axi_error[] = {
1312 {
1313 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1314 .msg = "dma_tx_axi_wr_err",
1315 },
1316 {
1317 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1318 .msg = "dma_tx_axi_rd_err",
1319 },
1320 {
1321 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1322 .msg = "dma_rx_axi_wr_err",
1323 },
1324 {
1325 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1326 .msg = "dma_rx_axi_rd_err",
1327 },
1328 };
1329
1330 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1331 {
1332 struct hisi_hba *hisi_hba = p;
1333 struct device *dev = hisi_hba->dev;
1334 u32 ent_msk, ent_tmp, irq_msk;
1335 int phy_no = 0;
1336
1337 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1338 ent_tmp = ent_msk;
1339 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1340 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1341
1342 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1343 & 0xeeeeeeee;
1344
1345 while (irq_msk) {
1346 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1347 CHL_INT0);
1348 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1349 CHL_INT1);
1350 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1351 CHL_INT2);
1352 u32 irq_msk1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1353 CHL_INT1_MSK);
1354 u32 irq_msk2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1355 CHL_INT2_MSK);
1356
1357 irq_value1 &= ~irq_msk1;
1358 irq_value2 &= ~irq_msk2;
1359
1360 if ((irq_msk & (4 << (phy_no * 4))) &&
1361 irq_value1) {
1362 int i;
1363
1364 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1365 const struct hisi_sas_hw_error *error =
1366 &port_axi_error[i];
1367
1368 if (!(irq_value1 & error->irq_msk))
1369 continue;
1370
1371 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1372 error->msg, phy_no, irq_value1);
1373 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1374 }
1375
1376 hisi_sas_phy_write32(hisi_hba, phy_no,
1377 CHL_INT1, irq_value1);
1378 }
1379
1380 if (irq_msk & (8 << (phy_no * 4)) && irq_value2) {
1381 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1382
1383 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1384 dev_warn(dev, "phy%d identify timeout\n",
1385 phy_no);
1386 hisi_sas_notify_phy_event(phy,
1387 HISI_PHYE_LINK_RESET);
1388
1389 }
1390
1391 if (irq_value2 & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1392 u32 reg_value = hisi_sas_phy_read32(hisi_hba,
1393 phy_no, STP_LINK_TIMEOUT_STATE);
1394
1395 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1396 phy_no, reg_value);
1397 if (reg_value & BIT(4))
1398 hisi_sas_notify_phy_event(phy,
1399 HISI_PHYE_LINK_RESET);
1400 }
1401
1402 hisi_sas_phy_write32(hisi_hba, phy_no,
1403 CHL_INT2, irq_value2);
1404 }
1405
1406
1407 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1408 hisi_sas_phy_write32(hisi_hba, phy_no,
1409 CHL_INT0, irq_value0
1410 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1411 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1412 & (~CHL_INT0_NOT_RDY_MSK));
1413 }
1414 irq_msk &= ~(0xe << (phy_no * 4));
1415 phy_no++;
1416 }
1417
1418 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1419
1420 return IRQ_HANDLED;
1421 }
1422
1423 static const struct hisi_sas_hw_error axi_error[] = {
1424 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1425 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1426 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1427 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1428 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1429 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1430 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1431 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1432 {},
1433 };
1434
1435 static const struct hisi_sas_hw_error fifo_error[] = {
1436 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
1437 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
1438 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1439 { .msk = BIT(11), .msg = "CMDP_FIFO" },
1440 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1441 {},
1442 };
1443
1444 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1445 {
1446 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1447 .msg = "write pointer and depth",
1448 },
1449 {
1450 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
1451 .msg = "iptt no match slot",
1452 },
1453 {
1454 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
1455 .msg = "read pointer and depth",
1456 },
1457 {
1458 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
1459 .reg = HGC_AXI_FIFO_ERR_INFO,
1460 .sub = axi_error,
1461 },
1462 {
1463 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
1464 .reg = HGC_AXI_FIFO_ERR_INFO,
1465 .sub = fifo_error,
1466 },
1467 {
1468 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
1469 .msg = "LM add/fetch list",
1470 },
1471 {
1472 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
1473 .msg = "SAS_HGC_ABT fetch LM list",
1474 },
1475 };
1476
1477 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
1478 {
1479 u32 irq_value, irq_msk;
1480 struct hisi_hba *hisi_hba = p;
1481 struct device *dev = hisi_hba->dev;
1482 int i;
1483
1484 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1485 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
1486
1487 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
1488 irq_value &= ~irq_msk;
1489
1490 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
1491 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
1492
1493 if (!(irq_value & error->irq_msk))
1494 continue;
1495
1496 if (error->sub) {
1497 const struct hisi_sas_hw_error *sub = error->sub;
1498 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
1499
1500 for (; sub->msk || sub->msg; sub++) {
1501 if (!(err_value & sub->msk))
1502 continue;
1503
1504 dev_err(dev, "%s error (0x%x) found!\n",
1505 sub->msg, irq_value);
1506 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1507 }
1508 } else {
1509 dev_err(dev, "%s error (0x%x) found!\n",
1510 error->msg, irq_value);
1511 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1512 }
1513 }
1514
1515 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
1516 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
1517 u32 dev_id = reg_val & ITCT_DEV_MSK;
1518 struct hisi_sas_device *sas_dev =
1519 &hisi_hba->devices[dev_id];
1520
1521 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
1522 dev_dbg(dev, "clear ITCT ok\n");
1523 complete(sas_dev->completion);
1524 }
1525
1526 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
1527 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
1528
1529 return IRQ_HANDLED;
1530 }
1531
1532 static void
1533 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1534 struct hisi_sas_slot *slot)
1535 {
1536 struct task_status_struct *ts = &task->task_status;
1537 struct hisi_sas_complete_v3_hdr *complete_queue =
1538 hisi_hba->complete_hdr[slot->cmplt_queue];
1539 struct hisi_sas_complete_v3_hdr *complete_hdr =
1540 &complete_queue[slot->cmplt_queue_slot];
1541 struct hisi_sas_err_record_v3 *record =
1542 hisi_sas_status_buf_addr_mem(slot);
1543 u32 dma_rx_err_type = record->dma_rx_err_type;
1544 u32 trans_tx_fail_type = record->trans_tx_fail_type;
1545
1546 switch (task->task_proto) {
1547 case SAS_PROTOCOL_SSP:
1548 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1549 ts->residual = trans_tx_fail_type;
1550 ts->stat = SAS_DATA_UNDERRUN;
1551 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1552 ts->stat = SAS_QUEUE_FULL;
1553 slot->abort = 1;
1554 } else {
1555 ts->stat = SAS_OPEN_REJECT;
1556 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1557 }
1558 break;
1559 case SAS_PROTOCOL_SATA:
1560 case SAS_PROTOCOL_STP:
1561 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1562 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1563 ts->residual = trans_tx_fail_type;
1564 ts->stat = SAS_DATA_UNDERRUN;
1565 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1566 ts->stat = SAS_PHY_DOWN;
1567 slot->abort = 1;
1568 } else {
1569 ts->stat = SAS_OPEN_REJECT;
1570 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1571 }
1572 hisi_sas_sata_done(task, slot);
1573 break;
1574 case SAS_PROTOCOL_SMP:
1575 ts->stat = SAM_STAT_CHECK_CONDITION;
1576 break;
1577 default:
1578 break;
1579 }
1580 }
1581
1582 static int
1583 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1584 {
1585 struct sas_task *task = slot->task;
1586 struct hisi_sas_device *sas_dev;
1587 struct device *dev = hisi_hba->dev;
1588 struct task_status_struct *ts;
1589 struct domain_device *device;
1590 struct sas_ha_struct *ha;
1591 enum exec_status sts;
1592 struct hisi_sas_complete_v3_hdr *complete_queue =
1593 hisi_hba->complete_hdr[slot->cmplt_queue];
1594 struct hisi_sas_complete_v3_hdr *complete_hdr =
1595 &complete_queue[slot->cmplt_queue_slot];
1596 unsigned long flags;
1597 bool is_internal = slot->is_internal;
1598
1599 if (unlikely(!task || !task->lldd_task || !task->dev))
1600 return -EINVAL;
1601
1602 ts = &task->task_status;
1603 device = task->dev;
1604 ha = device->port->ha;
1605 sas_dev = device->lldd_dev;
1606
1607 spin_lock_irqsave(&task->task_state_lock, flags);
1608 task->task_state_flags &=
1609 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1610 spin_unlock_irqrestore(&task->task_state_lock, flags);
1611
1612 memset(ts, 0, sizeof(*ts));
1613 ts->resp = SAS_TASK_COMPLETE;
1614
1615 if (unlikely(!sas_dev)) {
1616 dev_dbg(dev, "slot complete: port has not device\n");
1617 ts->stat = SAS_PHY_DOWN;
1618 goto out;
1619 }
1620
1621 /*
1622 * Use SAS+TMF status codes
1623 */
1624 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1625 >> CMPLT_HDR_ABORT_STAT_OFF) {
1626 case STAT_IO_ABORTED:
1627 /* this IO has been aborted by abort command */
1628 ts->stat = SAS_ABORTED_TASK;
1629 goto out;
1630 case STAT_IO_COMPLETE:
1631 /* internal abort command complete */
1632 ts->stat = TMF_RESP_FUNC_SUCC;
1633 goto out;
1634 case STAT_IO_NO_DEVICE:
1635 ts->stat = TMF_RESP_FUNC_COMPLETE;
1636 goto out;
1637 case STAT_IO_NOT_VALID:
1638 /*
1639 * abort single IO, the controller can't find the IO
1640 */
1641 ts->stat = TMF_RESP_FUNC_FAILED;
1642 goto out;
1643 default:
1644 break;
1645 }
1646
1647 /* check for erroneous completion */
1648 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1649 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
1650
1651 slot_err_v3_hw(hisi_hba, task, slot);
1652 if (ts->stat != SAS_DATA_UNDERRUN)
1653 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
1654 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
1655 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
1656 slot->idx, task, sas_dev->device_id,
1657 complete_hdr->dw0, complete_hdr->dw1,
1658 complete_hdr->act, complete_hdr->dw3,
1659 error_info[0], error_info[1],
1660 error_info[2], error_info[3]);
1661 if (unlikely(slot->abort))
1662 return ts->stat;
1663 goto out;
1664 }
1665
1666 switch (task->task_proto) {
1667 case SAS_PROTOCOL_SSP: {
1668 struct ssp_response_iu *iu =
1669 hisi_sas_status_buf_addr_mem(slot) +
1670 sizeof(struct hisi_sas_err_record);
1671
1672 sas_ssp_task_response(dev, task, iu);
1673 break;
1674 }
1675 case SAS_PROTOCOL_SMP: {
1676 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1677 void *to;
1678
1679 ts->stat = SAM_STAT_GOOD;
1680 to = kmap_atomic(sg_page(sg_resp));
1681
1682 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1683 DMA_FROM_DEVICE);
1684 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1685 DMA_TO_DEVICE);
1686 memcpy(to + sg_resp->offset,
1687 hisi_sas_status_buf_addr_mem(slot) +
1688 sizeof(struct hisi_sas_err_record),
1689 sg_dma_len(sg_resp));
1690 kunmap_atomic(to);
1691 break;
1692 }
1693 case SAS_PROTOCOL_SATA:
1694 case SAS_PROTOCOL_STP:
1695 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1696 ts->stat = SAM_STAT_GOOD;
1697 hisi_sas_sata_done(task, slot);
1698 break;
1699 default:
1700 ts->stat = SAM_STAT_CHECK_CONDITION;
1701 break;
1702 }
1703
1704 if (!slot->port->port_attached) {
1705 dev_warn(dev, "slot complete: port %d has removed\n",
1706 slot->port->sas_port.id);
1707 ts->stat = SAS_PHY_DOWN;
1708 }
1709
1710 out:
1711 hisi_sas_slot_task_free(hisi_hba, task, slot);
1712 sts = ts->stat;
1713 spin_lock_irqsave(&task->task_state_lock, flags);
1714 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
1715 spin_unlock_irqrestore(&task->task_state_lock, flags);
1716 dev_info(dev, "slot complete: task(%p) aborted\n", task);
1717 return SAS_ABORTED_TASK;
1718 }
1719 task->task_state_flags |= SAS_TASK_STATE_DONE;
1720 spin_unlock_irqrestore(&task->task_state_lock, flags);
1721
1722 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
1723 spin_lock_irqsave(&device->done_lock, flags);
1724 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
1725 spin_unlock_irqrestore(&device->done_lock, flags);
1726 dev_info(dev, "slot complete: task(%p) ignored\n ",
1727 task);
1728 return sts;
1729 }
1730 spin_unlock_irqrestore(&device->done_lock, flags);
1731 }
1732
1733 if (task->task_done)
1734 task->task_done(task);
1735
1736 return sts;
1737 }
1738
1739 static void cq_tasklet_v3_hw(unsigned long val)
1740 {
1741 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1742 struct hisi_hba *hisi_hba = cq->hisi_hba;
1743 struct hisi_sas_slot *slot;
1744 struct hisi_sas_complete_v3_hdr *complete_queue;
1745 u32 rd_point = cq->rd_point, wr_point;
1746 int queue = cq->id;
1747
1748 complete_queue = hisi_hba->complete_hdr[queue];
1749
1750 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1751 (0x14 * queue));
1752
1753 while (rd_point != wr_point) {
1754 struct hisi_sas_complete_v3_hdr *complete_hdr;
1755 struct device *dev = hisi_hba->dev;
1756 int iptt;
1757
1758 complete_hdr = &complete_queue[rd_point];
1759
1760 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1761 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
1762 slot = &hisi_hba->slot_info[iptt];
1763 slot->cmplt_queue_slot = rd_point;
1764 slot->cmplt_queue = queue;
1765 slot_complete_v3_hw(hisi_hba, slot);
1766 } else
1767 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
1768
1769 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1770 rd_point = 0;
1771 }
1772
1773 /* update rd_point */
1774 cq->rd_point = rd_point;
1775 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1776 }
1777
1778 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1779 {
1780 struct hisi_sas_cq *cq = p;
1781 struct hisi_hba *hisi_hba = cq->hisi_hba;
1782 int queue = cq->id;
1783
1784 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1785
1786 tasklet_schedule(&cq->tasklet);
1787
1788 return IRQ_HANDLED;
1789 }
1790
1791 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1792 {
1793 struct device *dev = hisi_hba->dev;
1794 struct pci_dev *pdev = hisi_hba->pci_dev;
1795 int vectors, rc;
1796 int i, k;
1797 int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1798
1799 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1800 max_msi, PCI_IRQ_MSI);
1801 if (vectors < max_msi) {
1802 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1803 return -ENOENT;
1804 }
1805
1806 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1807 int_phy_up_down_bcast_v3_hw, 0,
1808 DRV_NAME " phy", hisi_hba);
1809 if (rc) {
1810 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1811 rc = -ENOENT;
1812 goto free_irq_vectors;
1813 }
1814
1815 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1816 int_chnl_int_v3_hw, 0,
1817 DRV_NAME " channel", hisi_hba);
1818 if (rc) {
1819 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1820 rc = -ENOENT;
1821 goto free_phy_irq;
1822 }
1823
1824 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
1825 fatal_axi_int_v3_hw, 0,
1826 DRV_NAME " fatal", hisi_hba);
1827 if (rc) {
1828 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
1829 rc = -ENOENT;
1830 goto free_chnl_interrupt;
1831 }
1832
1833 /* Init tasklets for cq only */
1834 for (i = 0; i < hisi_hba->queue_count; i++) {
1835 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1836 struct tasklet_struct *t = &cq->tasklet;
1837
1838 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1839 cq_interrupt_v3_hw, 0,
1840 DRV_NAME " cq", cq);
1841 if (rc) {
1842 dev_err(dev,
1843 "could not request cq%d interrupt, rc=%d\n",
1844 i, rc);
1845 rc = -ENOENT;
1846 goto free_cq_irqs;
1847 }
1848
1849 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1850 }
1851
1852 return 0;
1853
1854 free_cq_irqs:
1855 for (k = 0; k < i; k++) {
1856 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1857
1858 free_irq(pci_irq_vector(pdev, k+16), cq);
1859 }
1860 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
1861 free_chnl_interrupt:
1862 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1863 free_phy_irq:
1864 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1865 free_irq_vectors:
1866 pci_free_irq_vectors(pdev);
1867 return rc;
1868 }
1869
1870 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1871 {
1872 int rc;
1873
1874 rc = hw_init_v3_hw(hisi_hba);
1875 if (rc)
1876 return rc;
1877
1878 rc = interrupt_init_v3_hw(hisi_hba);
1879 if (rc)
1880 return rc;
1881
1882 return 0;
1883 }
1884
1885 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
1886 struct sas_phy_linkrates *r)
1887 {
1888 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1889 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1890 enum sas_linkrate min, max;
1891 u32 prog_phy_link_rate = 0x800;
1892
1893 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1894 max = sas_phy->phy->maximum_linkrate;
1895 min = r->minimum_linkrate;
1896 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1897 max = r->maximum_linkrate;
1898 min = sas_phy->phy->minimum_linkrate;
1899 } else
1900 return;
1901
1902 sas_phy->phy->maximum_linkrate = max;
1903 sas_phy->phy->minimum_linkrate = min;
1904 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
1905
1906 disable_phy_v3_hw(hisi_hba, phy_no);
1907 msleep(100);
1908 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1909 prog_phy_link_rate);
1910 start_phy_v3_hw(hisi_hba, phy_no);
1911 }
1912
1913 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
1914 {
1915 struct pci_dev *pdev = hisi_hba->pci_dev;
1916 int i;
1917
1918 synchronize_irq(pci_irq_vector(pdev, 1));
1919 synchronize_irq(pci_irq_vector(pdev, 2));
1920 synchronize_irq(pci_irq_vector(pdev, 11));
1921 for (i = 0; i < hisi_hba->queue_count; i++) {
1922 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
1923 synchronize_irq(pci_irq_vector(pdev, i + 16));
1924 }
1925
1926 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
1927 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
1928 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
1929 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1930
1931 for (i = 0; i < hisi_hba->n_phy; i++) {
1932 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1933 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
1934 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
1935 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
1936 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
1937 }
1938 }
1939
1940 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
1941 {
1942 return hisi_sas_read32(hisi_hba, PHY_STATE);
1943 }
1944
1945 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1946 {
1947 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1948 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1949 struct sas_phy *sphy = sas_phy->phy;
1950 u32 reg_value;
1951
1952 /* loss dword sync */
1953 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1954 sphy->loss_of_dword_sync_count += reg_value;
1955
1956 /* phy reset problem */
1957 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1958 sphy->phy_reset_problem_count += reg_value;
1959
1960 /* invalid dword */
1961 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1962 sphy->invalid_dword_count += reg_value;
1963
1964 /* disparity err */
1965 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1966 sphy->running_disparity_error_count += reg_value;
1967
1968 }
1969
1970 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
1971 {
1972 struct device *dev = hisi_hba->dev;
1973 int rc;
1974 u32 status;
1975
1976 interrupt_disable_v3_hw(hisi_hba);
1977 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
1978 hisi_sas_kill_tasklets(hisi_hba);
1979
1980 hisi_sas_stop_phys(hisi_hba);
1981
1982 mdelay(10);
1983
1984 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
1985
1986 /* wait until bus idle */
1987 rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
1988 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
1989 if (rc) {
1990 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
1991 return rc;
1992 }
1993
1994 hisi_sas_init_mem(hisi_hba);
1995
1996 return hw_init_v3_hw(hisi_hba);
1997 }
1998
1999 static const struct hisi_sas_hw hisi_sas_v3_hw = {
2000 .hw_init = hisi_sas_v3_init,
2001 .setup_itct = setup_itct_v3_hw,
2002 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
2003 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
2004 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
2005 .clear_itct = clear_itct_v3_hw,
2006 .sl_notify = sl_notify_v3_hw,
2007 .prep_ssp = prep_ssp_v3_hw,
2008 .prep_smp = prep_smp_v3_hw,
2009 .prep_stp = prep_ata_v3_hw,
2010 .prep_abort = prep_abort_v3_hw,
2011 .get_free_slot = get_free_slot_v3_hw,
2012 .start_delivery = start_delivery_v3_hw,
2013 .slot_complete = slot_complete_v3_hw,
2014 .phys_init = phys_init_v3_hw,
2015 .phy_start = start_phy_v3_hw,
2016 .phy_disable = disable_phy_v3_hw,
2017 .phy_hard_reset = phy_hard_reset_v3_hw,
2018 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
2019 .phy_set_linkrate = phy_set_linkrate_v3_hw,
2020 .dereg_device = dereg_device_v3_hw,
2021 .soft_reset = soft_reset_v3_hw,
2022 .get_phys_state = get_phys_state_v3_hw,
2023 .get_events = phy_get_events_v3_hw,
2024 };
2025
2026 static struct Scsi_Host *
2027 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
2028 {
2029 struct Scsi_Host *shost;
2030 struct hisi_hba *hisi_hba;
2031 struct device *dev = &pdev->dev;
2032
2033 shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
2034 if (!shost) {
2035 dev_err(dev, "shost alloc failed\n");
2036 return NULL;
2037 }
2038 hisi_hba = shost_priv(shost);
2039
2040 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
2041 hisi_hba->hw = &hisi_sas_v3_hw;
2042 hisi_hba->pci_dev = pdev;
2043 hisi_hba->dev = dev;
2044 hisi_hba->shost = shost;
2045 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
2046
2047 timer_setup(&hisi_hba->timer, NULL, 0);
2048
2049 if (hisi_sas_get_fw_info(hisi_hba) < 0)
2050 goto err_out;
2051
2052 if (hisi_sas_alloc(hisi_hba, shost)) {
2053 hisi_sas_free(hisi_hba);
2054 goto err_out;
2055 }
2056
2057 return shost;
2058 err_out:
2059 scsi_host_put(shost);
2060 dev_err(dev, "shost alloc failed\n");
2061 return NULL;
2062 }
2063
2064 static int
2065 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2066 {
2067 struct Scsi_Host *shost;
2068 struct hisi_hba *hisi_hba;
2069 struct device *dev = &pdev->dev;
2070 struct asd_sas_phy **arr_phy;
2071 struct asd_sas_port **arr_port;
2072 struct sas_ha_struct *sha;
2073 int rc, phy_nr, port_nr, i;
2074
2075 rc = pci_enable_device(pdev);
2076 if (rc)
2077 goto err_out;
2078
2079 pci_set_master(pdev);
2080
2081 rc = pci_request_regions(pdev, DRV_NAME);
2082 if (rc)
2083 goto err_out_disable_device;
2084
2085 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
2086 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
2087 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2088 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2089 dev_err(dev, "No usable DMA addressing method\n");
2090 rc = -EIO;
2091 goto err_out_regions;
2092 }
2093 }
2094
2095 shost = hisi_sas_shost_alloc_pci(pdev);
2096 if (!shost) {
2097 rc = -ENOMEM;
2098 goto err_out_regions;
2099 }
2100
2101 sha = SHOST_TO_SAS_HA(shost);
2102 hisi_hba = shost_priv(shost);
2103 dev_set_drvdata(dev, sha);
2104
2105 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
2106 if (!hisi_hba->regs) {
2107 dev_err(dev, "cannot map register.\n");
2108 rc = -ENOMEM;
2109 goto err_out_ha;
2110 }
2111
2112 phy_nr = port_nr = hisi_hba->n_phy;
2113
2114 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
2115 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
2116 if (!arr_phy || !arr_port) {
2117 rc = -ENOMEM;
2118 goto err_out_ha;
2119 }
2120
2121 sha->sas_phy = arr_phy;
2122 sha->sas_port = arr_port;
2123 sha->core.shost = shost;
2124 sha->lldd_ha = hisi_hba;
2125
2126 shost->transportt = hisi_sas_stt;
2127 shost->max_id = HISI_SAS_MAX_DEVICES;
2128 shost->max_lun = ~0;
2129 shost->max_channel = 1;
2130 shost->max_cmd_len = 16;
2131 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
2132 shost->can_queue = hisi_hba->hw->max_command_entries;
2133 shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
2134
2135 sha->sas_ha_name = DRV_NAME;
2136 sha->dev = dev;
2137 sha->lldd_module = THIS_MODULE;
2138 sha->sas_addr = &hisi_hba->sas_addr[0];
2139 sha->num_phys = hisi_hba->n_phy;
2140 sha->core.shost = hisi_hba->shost;
2141
2142 for (i = 0; i < hisi_hba->n_phy; i++) {
2143 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
2144 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
2145 }
2146
2147 hisi_sas_init_add(hisi_hba);
2148
2149 rc = scsi_add_host(shost, dev);
2150 if (rc)
2151 goto err_out_ha;
2152
2153 rc = sas_register_ha(sha);
2154 if (rc)
2155 goto err_out_register_ha;
2156
2157 rc = hisi_hba->hw->hw_init(hisi_hba);
2158 if (rc)
2159 goto err_out_register_ha;
2160
2161 scsi_scan_host(shost);
2162
2163 return 0;
2164
2165 err_out_register_ha:
2166 scsi_remove_host(shost);
2167 err_out_ha:
2168 scsi_host_put(shost);
2169 err_out_regions:
2170 pci_release_regions(pdev);
2171 err_out_disable_device:
2172 pci_disable_device(pdev);
2173 err_out:
2174 return rc;
2175 }
2176
2177 static void
2178 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
2179 {
2180 int i;
2181
2182 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2183 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2184 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2185 for (i = 0; i < hisi_hba->queue_count; i++) {
2186 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2187
2188 free_irq(pci_irq_vector(pdev, i+16), cq);
2189 }
2190 pci_free_irq_vectors(pdev);
2191 }
2192
2193 static void hisi_sas_v3_remove(struct pci_dev *pdev)
2194 {
2195 struct device *dev = &pdev->dev;
2196 struct sas_ha_struct *sha = dev_get_drvdata(dev);
2197 struct hisi_hba *hisi_hba = sha->lldd_ha;
2198 struct Scsi_Host *shost = sha->core.shost;
2199
2200 if (timer_pending(&hisi_hba->timer))
2201 del_timer(&hisi_hba->timer);
2202
2203 sas_unregister_ha(sha);
2204 sas_remove_host(sha->core.shost);
2205
2206 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
2207 hisi_sas_kill_tasklets(hisi_hba);
2208 pci_release_regions(pdev);
2209 pci_disable_device(pdev);
2210 hisi_sas_free(hisi_hba);
2211 scsi_host_put(shost);
2212 }
2213
2214 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = {
2215 { .irq_msk = BIT(19), .msg = "HILINK_INT" },
2216 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" },
2217 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" },
2218 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" },
2219 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" },
2220 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" },
2221 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" },
2222 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" },
2223 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" },
2224 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" },
2225 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" },
2226 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" },
2227 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" },
2228 };
2229
2230 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = {
2231 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" },
2232 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" },
2233 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" },
2234 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" },
2235 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" },
2236 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" },
2237 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" },
2238 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" },
2239 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" },
2240 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" },
2241 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" },
2242 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" },
2243 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" },
2244 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" },
2245 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" },
2246 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" },
2247 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" },
2248 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" },
2249 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" },
2250 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" },
2251 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" },
2252 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" },
2253 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" },
2254 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" },
2255 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" },
2256 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" },
2257 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" },
2258 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" },
2259 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" },
2260 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" },
2261 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" },
2262 };
2263
2264 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = {
2265 { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" },
2266 { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" },
2267 { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" },
2268 { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" },
2269 { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" },
2270 { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" },
2271 { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" },
2272 { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" },
2273 { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" },
2274 { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" },
2275 { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" },
2276 { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" },
2277 { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" },
2278 { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" },
2279 { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" },
2280 { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" },
2281 { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" },
2282 { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" },
2283 { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" },
2284 { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" },
2285 };
2286
2287 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba)
2288 {
2289 struct device *dev = hisi_hba->dev;
2290 const struct hisi_sas_hw_error *ras_error;
2291 bool need_reset = false;
2292 u32 irq_value;
2293 int i;
2294
2295 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0);
2296 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) {
2297 ras_error = &sas_ras_intr0_nfe[i];
2298 if (ras_error->irq_msk & irq_value) {
2299 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n",
2300 ras_error->msg, irq_value);
2301 need_reset = true;
2302 }
2303 }
2304 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value);
2305
2306 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1);
2307 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) {
2308 ras_error = &sas_ras_intr1_nfe[i];
2309 if (ras_error->irq_msk & irq_value) {
2310 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n",
2311 ras_error->msg, irq_value);
2312 need_reset = true;
2313 }
2314 }
2315 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value);
2316
2317 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2);
2318 for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) {
2319 ras_error = &sas_ras_intr2_nfe[i];
2320 if (ras_error->irq_msk & irq_value) {
2321 dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n",
2322 ras_error->msg, irq_value);
2323 need_reset = true;
2324 }
2325 }
2326 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value);
2327
2328 return need_reset;
2329 }
2330
2331 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev,
2332 pci_channel_state_t state)
2333 {
2334 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2335 struct hisi_hba *hisi_hba = sha->lldd_ha;
2336 struct device *dev = hisi_hba->dev;
2337
2338 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state);
2339 if (state == pci_channel_io_perm_failure)
2340 return PCI_ERS_RESULT_DISCONNECT;
2341
2342 if (process_non_fatal_error_v3_hw(hisi_hba))
2343 return PCI_ERS_RESULT_NEED_RESET;
2344
2345 return PCI_ERS_RESULT_CAN_RECOVER;
2346 }
2347
2348 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev)
2349 {
2350 return PCI_ERS_RESULT_RECOVERED;
2351 }
2352
2353 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev)
2354 {
2355 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2356 struct hisi_hba *hisi_hba = sha->lldd_ha;
2357 struct device *dev = hisi_hba->dev;
2358 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r);
2359
2360 dev_info(dev, "PCI error: slot reset callback!!\n");
2361 queue_work(hisi_hba->wq, &r.work);
2362 wait_for_completion(r.completion);
2363 if (r.done)
2364 return PCI_ERS_RESULT_RECOVERED;
2365
2366 return PCI_ERS_RESULT_DISCONNECT;
2367 }
2368
2369 enum {
2370 /* instances of the controller */
2371 hip08,
2372 };
2373
2374 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state)
2375 {
2376 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2377 struct hisi_hba *hisi_hba = sha->lldd_ha;
2378 struct device *dev = hisi_hba->dev;
2379 struct Scsi_Host *shost = hisi_hba->shost;
2380 u32 device_state, status;
2381 int rc;
2382 u32 reg_val;
2383 unsigned long flags;
2384
2385 if (!pdev->pm_cap) {
2386 dev_err(dev, "PCI PM not supported\n");
2387 return -ENODEV;
2388 }
2389
2390 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2391 scsi_block_requests(shost);
2392 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2393 flush_workqueue(hisi_hba->wq);
2394 /* disable DQ/PHY/bus */
2395 interrupt_disable_v3_hw(hisi_hba);
2396 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2397 hisi_sas_kill_tasklets(hisi_hba);
2398
2399 hisi_sas_stop_phys(hisi_hba);
2400
2401 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2402 AM_CTRL_GLOBAL);
2403 reg_val |= 0x1;
2404 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2405 AM_CTRL_GLOBAL, reg_val);
2406
2407 /* wait until bus idle */
2408 rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
2409 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
2410 if (rc) {
2411 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
2412 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2413 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2414 scsi_unblock_requests(shost);
2415 return rc;
2416 }
2417
2418 hisi_sas_init_mem(hisi_hba);
2419
2420 device_state = pci_choose_state(pdev, state);
2421 dev_warn(dev, "entering operating state [D%d]\n",
2422 device_state);
2423 pci_save_state(pdev);
2424 pci_disable_device(pdev);
2425 pci_set_power_state(pdev, device_state);
2426
2427 spin_lock_irqsave(&hisi_hba->lock, flags);
2428 hisi_sas_release_tasks(hisi_hba);
2429 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2430
2431 sas_suspend_ha(sha);
2432 return 0;
2433 }
2434
2435 static int hisi_sas_v3_resume(struct pci_dev *pdev)
2436 {
2437 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2438 struct hisi_hba *hisi_hba = sha->lldd_ha;
2439 struct Scsi_Host *shost = hisi_hba->shost;
2440 struct device *dev = hisi_hba->dev;
2441 unsigned int rc;
2442 u32 device_state = pdev->current_state;
2443
2444 dev_warn(dev, "resuming from operating state [D%d]\n",
2445 device_state);
2446 pci_set_power_state(pdev, PCI_D0);
2447 pci_enable_wake(pdev, PCI_D0, 0);
2448 pci_restore_state(pdev);
2449 rc = pci_enable_device(pdev);
2450 if (rc)
2451 dev_err(dev, "enable device failed during resume (%d)\n", rc);
2452
2453 pci_set_master(pdev);
2454 scsi_unblock_requests(shost);
2455 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2456
2457 sas_prep_resume_ha(sha);
2458 init_reg_v3_hw(hisi_hba);
2459 hisi_hba->hw->phys_init(hisi_hba);
2460 sas_resume_ha(sha);
2461 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2462
2463 return 0;
2464 }
2465
2466 static const struct pci_device_id sas_v3_pci_table[] = {
2467 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
2468 {}
2469 };
2470 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
2471
2472 static const struct pci_error_handlers hisi_sas_err_handler = {
2473 .error_detected = hisi_sas_error_detected_v3_hw,
2474 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw,
2475 .slot_reset = hisi_sas_slot_reset_v3_hw,
2476 };
2477
2478 static struct pci_driver sas_v3_pci_driver = {
2479 .name = DRV_NAME,
2480 .id_table = sas_v3_pci_table,
2481 .probe = hisi_sas_v3_probe,
2482 .remove = hisi_sas_v3_remove,
2483 .suspend = hisi_sas_v3_suspend,
2484 .resume = hisi_sas_v3_resume,
2485 .err_handler = &hisi_sas_err_handler,
2486 };
2487
2488 module_pci_driver(sas_v3_pci_driver);
2489
2490 MODULE_LICENSE("GPL");
2491 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2492 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2493 MODULE_ALIAS("pci:" DRV_NAME);
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