2 * Copyright (c) 2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
12 #define DRV_NAME "hisi_sas_v3_hw"
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CFG_1US_TIMER_TRSH 0xcc
55 #define CHNL_INT_STATUS 0x148
56 #define HGC_AXI_FIFO_ERR_INFO 0x154
57 #define AXI_ERR_INFO_OFF 0
58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
59 #define FIFO_ERR_INFO_OFF 8
60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
61 #define INT_COAL_EN 0x19c
62 #define OQ_INT_COAL_TIME 0x1a0
63 #define OQ_INT_COAL_CNT 0x1a4
64 #define ENT_INT_COAL_TIME 0x1a8
65 #define ENT_INT_COAL_CNT 0x1ac
66 #define OQ_INT_SRC 0x1b0
67 #define OQ_INT_SRC_MSK 0x1b4
68 #define ENT_INT_SRC1 0x1b8
69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
73 #define ENT_INT_SRC2 0x1bc
74 #define ENT_INT_SRC3 0x1c0
75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
78 #define ENT_INT_SRC3_AXI_OFF 11
79 #define ENT_INT_SRC3_FIFO_OFF 12
80 #define ENT_INT_SRC3_LM_OFF 14
81 #define ENT_INT_SRC3_ITC_INT_OFF 15
82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
83 #define ENT_INT_SRC3_ABT_OFF 16
84 #define ENT_INT_SRC_MSK1 0x1c4
85 #define ENT_INT_SRC_MSK2 0x1c8
86 #define ENT_INT_SRC_MSK3 0x1cc
87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
89 #define CHNL_ENT_INT_MSK 0x1d4
90 #define HGC_COM_INT_MSK 0x1d8
91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
92 #define SAS_ECC_INTR 0x1e8
93 #define SAS_ECC_INTR_MSK 0x1ec
94 #define HGC_ERR_STAT_EN 0x238
95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
97 #define DLVRY_Q_0_DEPTH 0x268
98 #define DLVRY_Q_0_WR_PTR 0x26c
99 #define DLVRY_Q_0_RD_PTR 0x270
100 #define HYPER_STREAM_ID_EN_CFG 0xc80
101 #define OQ0_INT_SRC_MSK 0xc90
102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
104 #define COMPL_Q_0_DEPTH 0x4e8
105 #define COMPL_Q_0_WR_PTR 0x4ec
106 #define COMPL_Q_0_RD_PTR 0x4f0
107 #define AWQOS_AWCACHE_CFG 0xc84
108 #define ARQOS_ARCACHE_CFG 0xc88
110 /* phy registers requiring init */
111 #define PORT_BASE (0x2000)
112 #define PHY_CFG (PORT_BASE + 0x0)
113 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
114 #define PHY_CFG_ENA_OFF 0
115 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
116 #define PHY_CFG_DC_OPT_OFF 2
117 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
118 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
119 #define PHY_CTRL (PORT_BASE + 0x14)
120 #define PHY_CTRL_RESET_OFF 0
121 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
122 #define SL_CFG (PORT_BASE + 0x84)
123 #define SL_CONTROL (PORT_BASE + 0x94)
124 #define SL_CONTROL_NOTIFY_EN_OFF 0
125 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
126 #define SL_CTA_OFF 17
127 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
128 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
129 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
130 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
131 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
132 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
133 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
134 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
135 #define TXID_AUTO (PORT_BASE + 0xb8)
137 #define CT3_MSK (0x1 << CT3_OFF)
138 #define TX_HARDRST_OFF 2
139 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
140 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
141 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
142 #define STP_LINK_TIMER (PORT_BASE + 0x120)
143 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
144 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
145 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
146 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
147 #define CHL_INT0 (PORT_BASE + 0x1b4)
148 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
149 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
150 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
151 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
152 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
153 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
154 #define CHL_INT0_NOT_RDY_OFF 4
155 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
156 #define CHL_INT0_PHY_RDY_OFF 5
157 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
158 #define CHL_INT1 (PORT_BASE + 0x1b8)
159 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
160 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
161 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
162 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
163 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
164 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
165 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
166 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
167 #define CHL_INT2 (PORT_BASE + 0x1bc)
168 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
169 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
170 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
171 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
172 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
173 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
174 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
175 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
176 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
177 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
178 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
179 #define DMA_TX_STATUS_BUSY_OFF 0
180 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
181 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
182 #define DMA_RX_STATUS_BUSY_OFF 0
183 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
184 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
185 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
186 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
187 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
189 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
190 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
191 #error Max ITCT exceeded
194 #define AXI_MASTER_CFG_BASE (0x5000)
195 #define AM_CTRL_GLOBAL (0x0)
196 #define AM_CURR_TRANS_RETURN (0x150)
198 #define AM_CFG_MAX_TRANS (0x5010)
199 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
200 #define AXI_CFG (0x5100)
201 #define AM_ROB_ECC_ERR_ADDR (0x510c)
202 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
203 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
204 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
205 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
207 /* HW dma structures */
208 /* Delivery queue header */
210 #define CMD_HDR_ABORT_FLAG_OFF 0
211 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
212 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
213 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
214 #define CMD_HDR_RESP_REPORT_OFF 5
215 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
216 #define CMD_HDR_TLR_CTRL_OFF 6
217 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
218 #define CMD_HDR_PORT_OFF 18
219 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
220 #define CMD_HDR_PRIORITY_OFF 27
221 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
222 #define CMD_HDR_CMD_OFF 29
223 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
225 #define CMD_HDR_UNCON_CMD_OFF 3
226 #define CMD_HDR_DIR_OFF 5
227 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
228 #define CMD_HDR_RESET_OFF 7
229 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
230 #define CMD_HDR_VDTL_OFF 10
231 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
232 #define CMD_HDR_FRAME_TYPE_OFF 11
233 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
234 #define CMD_HDR_DEV_ID_OFF 16
235 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
237 #define CMD_HDR_CFL_OFF 0
238 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
239 #define CMD_HDR_NCQ_TAG_OFF 10
240 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
241 #define CMD_HDR_MRFL_OFF 15
242 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
243 #define CMD_HDR_SG_MOD_OFF 24
244 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
246 #define CMD_HDR_IPTT_OFF 0
247 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
249 #define CMD_HDR_DIF_SGL_LEN_OFF 0
250 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
251 #define CMD_HDR_DATA_SGL_LEN_OFF 16
252 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
254 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
255 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
256 #define CMD_HDR_ABORT_IPTT_OFF 16
257 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
259 /* Completion header */
261 #define CMPLT_HDR_CMPLT_OFF 0
262 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
263 #define CMPLT_HDR_ERROR_PHASE_OFF 2
264 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
265 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
266 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
267 #define CMPLT_HDR_ERX_OFF 12
268 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
269 #define CMPLT_HDR_ABORT_STAT_OFF 13
270 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
272 #define STAT_IO_NOT_VALID 0x1
273 #define STAT_IO_NO_DEVICE 0x2
274 #define STAT_IO_COMPLETE 0x3
275 #define STAT_IO_ABORTED 0x4
277 #define CMPLT_HDR_IPTT_OFF 0
278 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
279 #define CMPLT_HDR_DEV_ID_OFF 16
280 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
282 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
283 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
287 #define ITCT_HDR_DEV_TYPE_OFF 0
288 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
289 #define ITCT_HDR_VALID_OFF 2
290 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
291 #define ITCT_HDR_MCR_OFF 5
292 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
293 #define ITCT_HDR_VLN_OFF 9
294 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
295 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
296 #define ITCT_HDR_AWT_CONTINUE_OFF 25
297 #define ITCT_HDR_PORT_ID_OFF 28
298 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
300 #define ITCT_HDR_INLT_OFF 0
301 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
302 #define ITCT_HDR_RTOLT_OFF 48
303 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
305 struct hisi_sas_complete_v3_hdr
{
312 struct hisi_sas_err_record_v3
{
314 __le32 trans_tx_fail_type
;
317 __le32 trans_rx_fail_type
;
320 __le16 dma_tx_err_type
;
321 __le16 sipc_rx_err_type
;
324 __le32 dma_rx_err_type
;
327 #define RX_DATA_LEN_UNDERFLOW_OFF 6
328 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
330 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
331 #define HISI_SAS_MSI_COUNT_V3_HW 32
334 HISI_SAS_PHY_PHY_UPDOWN
,
335 HISI_SAS_PHY_CHNL_INT
,
339 #define DIR_NO_DATA 0
341 #define DIR_TO_DEVICE 2
342 #define DIR_RESERVED 3
344 #define CMD_IS_UNCONSTRAINT(cmd) \
345 ((cmd == ATA_CMD_READ_LOG_EXT) || \
346 (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
347 (cmd == ATA_CMD_DEV_RESET))
349 static u32
hisi_sas_read32(struct hisi_hba
*hisi_hba
, u32 off
)
351 void __iomem
*regs
= hisi_hba
->regs
+ off
;
356 static u32
hisi_sas_read32_relaxed(struct hisi_hba
*hisi_hba
, u32 off
)
358 void __iomem
*regs
= hisi_hba
->regs
+ off
;
360 return readl_relaxed(regs
);
363 static void hisi_sas_write32(struct hisi_hba
*hisi_hba
, u32 off
, u32 val
)
365 void __iomem
*regs
= hisi_hba
->regs
+ off
;
370 static void hisi_sas_phy_write32(struct hisi_hba
*hisi_hba
, int phy_no
,
373 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
378 static u32
hisi_sas_phy_read32(struct hisi_hba
*hisi_hba
,
381 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
386 static void init_reg_v3_hw(struct hisi_hba
*hisi_hba
)
390 /* Global registers init */
391 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
,
392 (u32
)((1ULL << hisi_hba
->queue_count
) - 1));
393 hisi_sas_write32(hisi_hba
, CFG_MAX_TAG
, 0xfff0400);
394 hisi_sas_write32(hisi_hba
, HGC_SAS_TXFAIL_RETRY_CTRL
, 0x108);
395 hisi_sas_write32(hisi_hba
, CFG_1US_TIMER_TRSH
, 0xd);
396 hisi_sas_write32(hisi_hba
, INT_COAL_EN
, 0x1);
397 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_TIME
, 0x1);
398 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_CNT
, 0x1);
399 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 0xffff);
400 hisi_sas_write32(hisi_hba
, ENT_INT_SRC1
, 0xffffffff);
401 hisi_sas_write32(hisi_hba
, ENT_INT_SRC2
, 0xffffffff);
402 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
, 0xffffffff);
403 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0xfefefefe);
404 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0xfefefefe);
405 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0xfffe20ff);
406 hisi_sas_write32(hisi_hba
, CHNL_PHYUPDOWN_INT_MSK
, 0x0);
407 hisi_sas_write32(hisi_hba
, CHNL_ENT_INT_MSK
, 0x0);
408 hisi_sas_write32(hisi_hba
, HGC_COM_INT_MSK
, 0x0);
409 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0x0);
410 hisi_sas_write32(hisi_hba
, AWQOS_AWCACHE_CFG
, 0xf0f0);
411 hisi_sas_write32(hisi_hba
, ARQOS_ARCACHE_CFG
, 0xf0f0);
412 for (i
= 0; i
< hisi_hba
->queue_count
; i
++)
413 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+0x4*i
, 0);
415 hisi_sas_write32(hisi_hba
, HYPER_STREAM_ID_EN_CFG
, 1);
416 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
, 0x30000);
418 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
419 hisi_sas_phy_write32(hisi_hba
, i
, PROG_PHY_LINK_RATE
, 0x801);
420 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT0
, 0xffffffff);
421 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1
, 0xffffffff);
422 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2
, 0xffffffff);
423 hisi_sas_phy_write32(hisi_hba
, i
, RXOP_CHECK_CFG_H
, 0x1000);
424 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xff87ffff);
425 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0x8ffffbff);
426 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL_RDY_MSK
, 0x0);
427 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_NOT_RDY_MSK
, 0x0);
428 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_DWS_RESET_MSK
, 0x0);
429 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_PHY_ENA_MSK
, 0x0);
430 hisi_sas_phy_write32(hisi_hba
, i
, SL_RX_BCAST_CHK_MSK
, 0x0);
431 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_OOB_RESTART_MSK
, 0x0);
432 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL
, 0x199b4fa);
433 hisi_sas_phy_write32(hisi_hba
, i
, SAS_SSP_CON_TIMER_CFG
,
435 hisi_sas_phy_write32(hisi_hba
, i
, SAS_STP_CON_TIMER_CFG
,
437 hisi_sas_phy_write32(hisi_hba
, i
, STP_LINK_TIMER
,
439 hisi_sas_phy_write32(hisi_hba
, i
, CON_CFG_DRIVER
,
442 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
444 hisi_sas_write32(hisi_hba
,
445 DLVRY_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
446 upper_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
448 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
449 lower_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
451 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_DEPTH
+ (i
* 0x14),
452 HISI_SAS_QUEUE_SLOTS
);
454 /* Completion queue */
455 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
456 upper_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
458 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
459 lower_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
461 hisi_sas_write32(hisi_hba
, COMPL_Q_0_DEPTH
+ (i
* 0x14),
462 HISI_SAS_QUEUE_SLOTS
);
466 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_LO
,
467 lower_32_bits(hisi_hba
->itct_dma
));
469 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_HI
,
470 upper_32_bits(hisi_hba
->itct_dma
));
473 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_LO
,
474 lower_32_bits(hisi_hba
->iost_dma
));
476 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_HI
,
477 upper_32_bits(hisi_hba
->iost_dma
));
480 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_LO
,
481 lower_32_bits(hisi_hba
->breakpoint_dma
));
483 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_HI
,
484 upper_32_bits(hisi_hba
->breakpoint_dma
));
486 /* SATA broken msg */
487 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_LO
,
488 lower_32_bits(hisi_hba
->sata_breakpoint_dma
));
490 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_HI
,
491 upper_32_bits(hisi_hba
->sata_breakpoint_dma
));
493 /* SATA initial fis */
494 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_LO
,
495 lower_32_bits(hisi_hba
->initial_fis_dma
));
497 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_HI
,
498 upper_32_bits(hisi_hba
->initial_fis_dma
));
501 static void config_phy_opt_mode_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
503 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
505 cfg
&= ~PHY_CFG_DC_OPT_MSK
;
506 cfg
|= 1 << PHY_CFG_DC_OPT_OFF
;
507 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
510 static void config_id_frame_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
512 struct sas_identify_frame identify_frame
;
513 u32
*identify_buffer
;
515 memset(&identify_frame
, 0, sizeof(identify_frame
));
516 identify_frame
.dev_type
= SAS_END_DEVICE
;
517 identify_frame
.frame_type
= 0;
518 identify_frame
._un1
= 1;
519 identify_frame
.initiator_bits
= SAS_PROTOCOL_ALL
;
520 identify_frame
.target_bits
= SAS_PROTOCOL_NONE
;
521 memcpy(&identify_frame
._un4_11
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
522 memcpy(&identify_frame
.sas_addr
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
523 identify_frame
.phy_id
= phy_no
;
524 identify_buffer
= (u32
*)(&identify_frame
);
526 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD0
,
527 __swab32(identify_buffer
[0]));
528 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD1
,
529 __swab32(identify_buffer
[1]));
530 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD2
,
531 __swab32(identify_buffer
[2]));
532 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD3
,
533 __swab32(identify_buffer
[3]));
534 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD4
,
535 __swab32(identify_buffer
[4]));
536 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD5
,
537 __swab32(identify_buffer
[5]));
540 static void setup_itct_v3_hw(struct hisi_hba
*hisi_hba
,
541 struct hisi_sas_device
*sas_dev
)
543 struct domain_device
*device
= sas_dev
->sas_device
;
544 struct device
*dev
= hisi_hba
->dev
;
545 u64 qw0
, device_id
= sas_dev
->device_id
;
546 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[device_id
];
547 struct domain_device
*parent_dev
= device
->parent
;
548 struct asd_sas_port
*sas_port
= device
->port
;
549 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
551 memset(itct
, 0, sizeof(*itct
));
555 switch (sas_dev
->dev_type
) {
557 case SAS_EDGE_EXPANDER_DEVICE
:
558 case SAS_FANOUT_EXPANDER_DEVICE
:
559 qw0
= HISI_SAS_DEV_TYPE_SSP
<< ITCT_HDR_DEV_TYPE_OFF
;
562 case SAS_SATA_PENDING
:
563 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
564 qw0
= HISI_SAS_DEV_TYPE_STP
<< ITCT_HDR_DEV_TYPE_OFF
;
566 qw0
= HISI_SAS_DEV_TYPE_SATA
<< ITCT_HDR_DEV_TYPE_OFF
;
569 dev_warn(dev
, "setup itct: unsupported dev type (%d)\n",
573 qw0
|= ((1 << ITCT_HDR_VALID_OFF
) |
574 (device
->linkrate
<< ITCT_HDR_MCR_OFF
) |
575 (1 << ITCT_HDR_VLN_OFF
) |
576 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF
) |
577 (1 << ITCT_HDR_AWT_CONTINUE_OFF
) |
578 (port
->id
<< ITCT_HDR_PORT_ID_OFF
));
579 itct
->qw0
= cpu_to_le64(qw0
);
582 memcpy(&itct
->sas_addr
, device
->sas_addr
, SAS_ADDR_SIZE
);
583 itct
->sas_addr
= __swab64(itct
->sas_addr
);
586 if (!dev_is_sata(device
))
587 itct
->qw2
= cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF
) |
588 (0x1ULL
<< ITCT_HDR_RTOLT_OFF
));
591 static void clear_itct_v3_hw(struct hisi_hba
*hisi_hba
,
592 struct hisi_sas_device
*sas_dev
)
594 DECLARE_COMPLETION_ONSTACK(completion
);
595 u64 dev_id
= sas_dev
->device_id
;
596 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[dev_id
];
597 u32 reg_val
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
599 sas_dev
->completion
= &completion
;
601 /* clear the itct interrupt state */
602 if (ENT_INT_SRC3_ITC_INT_MSK
& reg_val
)
603 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
604 ENT_INT_SRC3_ITC_INT_MSK
);
606 /* clear the itct table*/
607 reg_val
= ITCT_CLR_EN_MSK
| (dev_id
& ITCT_DEV_MSK
);
608 hisi_sas_write32(hisi_hba
, ITCT_CLR
, reg_val
);
610 wait_for_completion(sas_dev
->completion
);
611 memset(itct
, 0, sizeof(struct hisi_sas_itct
));
614 static void dereg_device_v3_hw(struct hisi_hba
*hisi_hba
,
615 struct domain_device
*device
)
617 struct hisi_sas_slot
*slot
, *slot2
;
618 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
619 u32 cfg_abt_set_query_iptt
;
621 cfg_abt_set_query_iptt
= hisi_sas_read32(hisi_hba
,
622 CFG_ABT_SET_QUERY_IPTT
);
623 list_for_each_entry_safe(slot
, slot2
, &sas_dev
->list
, entry
) {
624 cfg_abt_set_query_iptt
&= ~CFG_SET_ABORTED_IPTT_MSK
;
625 cfg_abt_set_query_iptt
|= (1 << CFG_SET_ABORTED_EN_OFF
) |
626 (slot
->idx
<< CFG_SET_ABORTED_IPTT_OFF
);
627 hisi_sas_write32(hisi_hba
, CFG_ABT_SET_QUERY_IPTT
,
628 cfg_abt_set_query_iptt
);
630 cfg_abt_set_query_iptt
&= ~(1 << CFG_SET_ABORTED_EN_OFF
);
631 hisi_sas_write32(hisi_hba
, CFG_ABT_SET_QUERY_IPTT
,
632 cfg_abt_set_query_iptt
);
633 hisi_sas_write32(hisi_hba
, CFG_ABT_SET_IPTT_DONE
,
634 1 << CFG_ABT_SET_IPTT_DONE_OFF
);
637 static int reset_hw_v3_hw(struct hisi_hba
*hisi_hba
)
639 struct device
*dev
= hisi_hba
->dev
;
643 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0);
645 /* Disable all of the PHYs */
646 hisi_sas_stop_phys(hisi_hba
);
649 /* Ensure axi bus idle */
650 ret
= readl_poll_timeout(hisi_hba
->regs
+ AXI_CFG
, val
, !val
,
653 dev_err(dev
, "axi bus is not idle, ret = %d!\n", ret
);
657 if (ACPI_HANDLE(dev
)) {
660 s
= acpi_evaluate_object(ACPI_HANDLE(dev
), "_RST", NULL
, NULL
);
661 if (ACPI_FAILURE(s
)) {
662 dev_err(dev
, "Reset failed\n");
666 dev_err(dev
, "no reset method!\n");
671 static int hw_init_v3_hw(struct hisi_hba
*hisi_hba
)
673 struct device
*dev
= hisi_hba
->dev
;
676 rc
= reset_hw_v3_hw(hisi_hba
);
678 dev_err(dev
, "hisi_sas_reset_hw failed, rc=%d", rc
);
683 init_reg_v3_hw(hisi_hba
);
688 static void enable_phy_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
690 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
692 cfg
|= PHY_CFG_ENA_MSK
;
693 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
696 static void disable_phy_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
698 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
700 cfg
&= ~PHY_CFG_ENA_MSK
;
701 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
704 static void start_phy_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
706 config_id_frame_v3_hw(hisi_hba
, phy_no
);
707 config_phy_opt_mode_v3_hw(hisi_hba
, phy_no
);
708 enable_phy_v3_hw(hisi_hba
, phy_no
);
711 static void phy_hard_reset_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
713 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
716 disable_phy_v3_hw(hisi_hba
, phy_no
);
717 if (phy
->identify
.device_type
== SAS_END_DEVICE
) {
718 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
719 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
720 txid_auto
| TX_HARDRST_MSK
);
723 start_phy_v3_hw(hisi_hba
, phy_no
);
726 enum sas_linkrate
phy_get_max_linkrate_v3_hw(void)
728 return SAS_LINK_RATE_12_0_GBPS
;
731 static void phys_init_v3_hw(struct hisi_hba
*hisi_hba
)
735 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
736 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[i
];
737 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
739 if (!sas_phy
->phy
->enabled
)
742 start_phy_v3_hw(hisi_hba
, i
);
746 static void sl_notify_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
750 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
751 sl_control
|= SL_CONTROL_NOTIFY_EN_MSK
;
752 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
754 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
755 sl_control
&= ~SL_CONTROL_NOTIFY_EN_MSK
;
756 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
759 static int get_wideport_bitmap_v3_hw(struct hisi_hba
*hisi_hba
, int port_id
)
762 u32 phy_port_num_ma
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
763 u32 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
765 for (i
= 0; i
< hisi_hba
->n_phy
; i
++)
766 if (phy_state
& BIT(i
))
767 if (((phy_port_num_ma
>> (i
* 4)) & 0xf) == port_id
)
774 * The callpath to this function and upto writing the write
775 * queue pointer should be safe from interruption.
778 get_free_slot_v3_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_dq
*dq
)
780 struct device
*dev
= hisi_hba
->dev
;
785 r
= hisi_sas_read32_relaxed(hisi_hba
,
786 DLVRY_Q_0_RD_PTR
+ (queue
* 0x14));
787 if (r
== (w
+1) % HISI_SAS_QUEUE_SLOTS
) {
788 dev_warn(dev
, "full queue=%d r=%d w=%d\n\n",
796 static void start_delivery_v3_hw(struct hisi_sas_dq
*dq
)
798 struct hisi_hba
*hisi_hba
= dq
->hisi_hba
;
799 int dlvry_queue
= dq
->slot_prep
->dlvry_queue
;
800 int dlvry_queue_slot
= dq
->slot_prep
->dlvry_queue_slot
;
802 dq
->wr_point
= ++dlvry_queue_slot
% HISI_SAS_QUEUE_SLOTS
;
803 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_WR_PTR
+ (dlvry_queue
* 0x14),
807 static int prep_prd_sge_v3_hw(struct hisi_hba
*hisi_hba
,
808 struct hisi_sas_slot
*slot
,
809 struct hisi_sas_cmd_hdr
*hdr
,
810 struct scatterlist
*scatter
,
813 struct hisi_sas_sge_page
*sge_page
= hisi_sas_sge_addr_mem(slot
);
814 struct device
*dev
= hisi_hba
->dev
;
815 struct scatterlist
*sg
;
818 if (n_elem
> HISI_SAS_SGE_PAGE_CNT
) {
819 dev_err(dev
, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
824 for_each_sg(scatter
, sg
, n_elem
, i
) {
825 struct hisi_sas_sge
*entry
= &sge_page
->sge
[i
];
827 entry
->addr
= cpu_to_le64(sg_dma_address(sg
));
828 entry
->page_ctrl_0
= entry
->page_ctrl_1
= 0;
829 entry
->data_len
= cpu_to_le32(sg_dma_len(sg
));
833 hdr
->prd_table_addr
= cpu_to_le64(hisi_sas_sge_addr_dma(slot
));
835 hdr
->sg_len
= cpu_to_le32(n_elem
<< CMD_HDR_DATA_SGL_LEN_OFF
);
840 static int prep_ssp_v3_hw(struct hisi_hba
*hisi_hba
,
841 struct hisi_sas_slot
*slot
, int is_tmf
,
842 struct hisi_sas_tmf_task
*tmf
)
844 struct sas_task
*task
= slot
->task
;
845 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
846 struct domain_device
*device
= task
->dev
;
847 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
848 struct hisi_sas_port
*port
= slot
->port
;
849 struct sas_ssp_task
*ssp_task
= &task
->ssp_task
;
850 struct scsi_cmnd
*scsi_cmnd
= ssp_task
->cmd
;
851 int has_data
= 0, rc
, priority
= is_tmf
;
853 u32 dw1
= 0, dw2
= 0;
855 hdr
->dw0
= cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF
) |
856 (2 << CMD_HDR_TLR_CTRL_OFF
) |
857 (port
->id
<< CMD_HDR_PORT_OFF
) |
858 (priority
<< CMD_HDR_PRIORITY_OFF
) |
859 (1 << CMD_HDR_CMD_OFF
)); /* ssp */
861 dw1
= 1 << CMD_HDR_VDTL_OFF
;
863 dw1
|= 2 << CMD_HDR_FRAME_TYPE_OFF
;
864 dw1
|= DIR_NO_DATA
<< CMD_HDR_DIR_OFF
;
866 dw1
|= 1 << CMD_HDR_FRAME_TYPE_OFF
;
867 switch (scsi_cmnd
->sc_data_direction
) {
870 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
872 case DMA_FROM_DEVICE
:
874 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
877 dw1
&= ~CMD_HDR_DIR_MSK
;
882 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
883 hdr
->dw1
= cpu_to_le32(dw1
);
885 dw2
= (((sizeof(struct ssp_command_iu
) + sizeof(struct ssp_frame_hdr
)
886 + 3) / 4) << CMD_HDR_CFL_OFF
) |
887 ((HISI_SAS_MAX_SSP_RESP_SZ
/ 4) << CMD_HDR_MRFL_OFF
) |
888 (2 << CMD_HDR_SG_MOD_OFF
);
889 hdr
->dw2
= cpu_to_le32(dw2
);
890 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
893 rc
= prep_prd_sge_v3_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
899 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
900 hdr
->cmd_table_addr
= cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot
));
901 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
903 buf_cmd
= hisi_sas_cmd_hdr_addr_mem(slot
) +
904 sizeof(struct ssp_frame_hdr
);
906 memcpy(buf_cmd
, &task
->ssp_task
.LUN
, 8);
908 buf_cmd
[9] = ssp_task
->task_attr
| (ssp_task
->task_prio
<< 3);
909 memcpy(buf_cmd
+ 12, scsi_cmnd
->cmnd
, scsi_cmnd
->cmd_len
);
911 buf_cmd
[10] = tmf
->tmf
;
916 (tmf
->tag_of_task_to_be_managed
>> 8) & 0xff;
918 tmf
->tag_of_task_to_be_managed
& 0xff;
928 static int prep_smp_v3_hw(struct hisi_hba
*hisi_hba
,
929 struct hisi_sas_slot
*slot
)
931 struct sas_task
*task
= slot
->task
;
932 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
933 struct domain_device
*device
= task
->dev
;
934 struct device
*dev
= hisi_hba
->dev
;
935 struct hisi_sas_port
*port
= slot
->port
;
936 struct scatterlist
*sg_req
, *sg_resp
;
937 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
938 dma_addr_t req_dma_addr
;
939 unsigned int req_len
, resp_len
;
943 * DMA-map SMP request, response buffers
946 sg_req
= &task
->smp_task
.smp_req
;
947 elem
= dma_map_sg(dev
, sg_req
, 1, DMA_TO_DEVICE
);
950 req_len
= sg_dma_len(sg_req
);
951 req_dma_addr
= sg_dma_address(sg_req
);
954 sg_resp
= &task
->smp_task
.smp_resp
;
955 elem
= dma_map_sg(dev
, sg_resp
, 1, DMA_FROM_DEVICE
);
960 resp_len
= sg_dma_len(sg_resp
);
961 if ((req_len
& 0x3) || (resp_len
& 0x3)) {
968 hdr
->dw0
= cpu_to_le32((port
->id
<< CMD_HDR_PORT_OFF
) |
969 (1 << CMD_HDR_PRIORITY_OFF
) | /* high pri */
970 (2 << CMD_HDR_CMD_OFF
)); /* smp */
973 hdr
->dw1
= cpu_to_le32((sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
) |
974 (1 << CMD_HDR_FRAME_TYPE_OFF
) |
975 (DIR_NO_DATA
<< CMD_HDR_DIR_OFF
));
978 hdr
->dw2
= cpu_to_le32((((req_len
- 4) / 4) << CMD_HDR_CFL_OFF
) |
979 (HISI_SAS_MAX_SMP_RESP_SZ
/ 4 <<
982 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
<< CMD_HDR_IPTT_OFF
);
984 hdr
->cmd_table_addr
= cpu_to_le64(req_dma_addr
);
985 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
990 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_resp
, 1,
993 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_req
, 1,
998 static int prep_ata_v3_hw(struct hisi_hba
*hisi_hba
,
999 struct hisi_sas_slot
*slot
)
1001 struct sas_task
*task
= slot
->task
;
1002 struct domain_device
*device
= task
->dev
;
1003 struct domain_device
*parent_dev
= device
->parent
;
1004 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
1005 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1006 struct asd_sas_port
*sas_port
= device
->port
;
1007 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
1009 int has_data
= 0, rc
= 0, hdr_tag
= 0;
1010 u32 dw1
= 0, dw2
= 0;
1012 hdr
->dw0
= cpu_to_le32(port
->id
<< CMD_HDR_PORT_OFF
);
1013 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
1014 hdr
->dw0
|= cpu_to_le32(3 << CMD_HDR_CMD_OFF
);
1016 hdr
->dw0
|= cpu_to_le32(4 << CMD_HDR_CMD_OFF
);
1018 switch (task
->data_dir
) {
1021 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
1023 case DMA_FROM_DEVICE
:
1025 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
1028 dw1
&= ~CMD_HDR_DIR_MSK
;
1031 if ((task
->ata_task
.fis
.command
== ATA_CMD_DEV_RESET
) &&
1032 (task
->ata_task
.fis
.control
& ATA_SRST
))
1033 dw1
|= 1 << CMD_HDR_RESET_OFF
;
1035 dw1
|= (hisi_sas_get_ata_protocol(
1036 task
->ata_task
.fis
.command
, task
->data_dir
))
1037 << CMD_HDR_FRAME_TYPE_OFF
;
1038 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
1040 if (CMD_IS_UNCONSTRAINT(task
->ata_task
.fis
.command
))
1041 dw1
|= 1 << CMD_HDR_UNCON_CMD_OFF
;
1043 hdr
->dw1
= cpu_to_le32(dw1
);
1046 if (task
->ata_task
.use_ncq
&& hisi_sas_get_ncq_tag(task
, &hdr_tag
)) {
1047 task
->ata_task
.fis
.sector_count
|= (u8
) (hdr_tag
<< 3);
1048 dw2
|= hdr_tag
<< CMD_HDR_NCQ_TAG_OFF
;
1051 dw2
|= (HISI_SAS_MAX_STP_RESP_SZ
/ 4) << CMD_HDR_CFL_OFF
|
1052 2 << CMD_HDR_SG_MOD_OFF
;
1053 hdr
->dw2
= cpu_to_le32(dw2
);
1056 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
1059 rc
= prep_prd_sge_v3_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
1065 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
1066 hdr
->cmd_table_addr
= cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot
));
1067 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
1069 buf_cmd
= hisi_sas_cmd_hdr_addr_mem(slot
);
1071 if (likely(!task
->ata_task
.device_control_reg_update
))
1072 task
->ata_task
.fis
.flags
|= 0x80; /* C=1: update ATA cmd reg */
1073 /* fill in command FIS */
1074 memcpy(buf_cmd
, &task
->ata_task
.fis
, sizeof(struct host_to_dev_fis
));
1079 static int prep_abort_v3_hw(struct hisi_hba
*hisi_hba
,
1080 struct hisi_sas_slot
*slot
,
1081 int device_id
, int abort_flag
, int tag_to_abort
)
1083 struct sas_task
*task
= slot
->task
;
1084 struct domain_device
*dev
= task
->dev
;
1085 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1086 struct hisi_sas_port
*port
= slot
->port
;
1089 hdr
->dw0
= cpu_to_le32((5 << CMD_HDR_CMD_OFF
) | /*abort*/
1090 (port
->id
<< CMD_HDR_PORT_OFF
) |
1091 ((dev_is_sata(dev
) ? 1:0)
1092 << CMD_HDR_ABORT_DEVICE_TYPE_OFF
) |
1094 << CMD_HDR_ABORT_FLAG_OFF
));
1097 hdr
->dw1
= cpu_to_le32(device_id
1098 << CMD_HDR_DEV_ID_OFF
);
1101 hdr
->dw7
= cpu_to_le32(tag_to_abort
<< CMD_HDR_ABORT_IPTT_OFF
);
1102 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
1107 static int phy_up_v3_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
1110 u32 context
, port_id
, link_rate
, hard_phy_linkrate
;
1111 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1112 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1113 struct device
*dev
= hisi_hba
->dev
;
1115 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 1);
1117 port_id
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
1118 port_id
= (port_id
>> (4 * phy_no
)) & 0xf;
1119 link_rate
= hisi_sas_read32(hisi_hba
, PHY_CONN_RATE
);
1120 link_rate
= (link_rate
>> (phy_no
* 4)) & 0xf;
1122 if (port_id
== 0xf) {
1123 dev_err(dev
, "phyup: phy%d invalid portid\n", phy_no
);
1127 sas_phy
->linkrate
= link_rate
;
1128 hard_phy_linkrate
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1130 phy
->maximum_linkrate
= hard_phy_linkrate
& 0xf;
1131 phy
->minimum_linkrate
= (hard_phy_linkrate
>> 4) & 0xf;
1132 phy
->phy_type
&= ~(PORT_TYPE_SAS
| PORT_TYPE_SATA
);
1134 /* Check for SATA dev */
1135 context
= hisi_sas_read32(hisi_hba
, PHY_CONTEXT
);
1136 if (context
& (1 << phy_no
)) {
1137 struct hisi_sas_initial_fis
*initial_fis
;
1138 struct dev_to_host_fis
*fis
;
1139 u8 attached_sas_addr
[SAS_ADDR_SIZE
] = {0};
1141 dev_info(dev
, "phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
1142 initial_fis
= &hisi_hba
->initial_fis
[phy_no
];
1143 fis
= &initial_fis
->fis
;
1144 sas_phy
->oob_mode
= SATA_OOB_MODE
;
1145 attached_sas_addr
[0] = 0x50;
1146 attached_sas_addr
[7] = phy_no
;
1147 memcpy(sas_phy
->attached_sas_addr
,
1150 memcpy(sas_phy
->frame_rcvd
, fis
,
1151 sizeof(struct dev_to_host_fis
));
1152 phy
->phy_type
|= PORT_TYPE_SATA
;
1153 phy
->identify
.device_type
= SAS_SATA_DEV
;
1154 phy
->frame_rcvd_size
= sizeof(struct dev_to_host_fis
);
1155 phy
->identify
.target_port_protocols
= SAS_PROTOCOL_SATA
;
1157 u32
*frame_rcvd
= (u32
*)sas_phy
->frame_rcvd
;
1158 struct sas_identify_frame
*id
=
1159 (struct sas_identify_frame
*)frame_rcvd
;
1161 dev_info(dev
, "phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
1162 for (i
= 0; i
< 6; i
++) {
1163 u32 idaf
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1164 RX_IDAF_DWORD0
+ (i
* 4));
1165 frame_rcvd
[i
] = __swab32(idaf
);
1167 sas_phy
->oob_mode
= SAS_OOB_MODE
;
1168 memcpy(sas_phy
->attached_sas_addr
,
1171 phy
->phy_type
|= PORT_TYPE_SAS
;
1172 phy
->identify
.device_type
= id
->dev_type
;
1173 phy
->frame_rcvd_size
= sizeof(struct sas_identify_frame
);
1174 if (phy
->identify
.device_type
== SAS_END_DEVICE
)
1175 phy
->identify
.target_port_protocols
=
1177 else if (phy
->identify
.device_type
!= SAS_PHY_UNUSED
)
1178 phy
->identify
.target_port_protocols
=
1182 phy
->port_id
= port_id
;
1183 phy
->phy_attached
= 1;
1184 queue_work(hisi_hba
->wq
, &phy
->phyup_ws
);
1187 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
1188 CHL_INT0_SL_PHY_ENABLE_MSK
);
1189 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 0);
1194 static int phy_down_v3_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
1196 u32 phy_state
, sl_ctrl
, txid_auto
;
1197 struct device
*dev
= hisi_hba
->dev
;
1199 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 1);
1201 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1202 dev_info(dev
, "phydown: phy%d phy_state=0x%x\n", phy_no
, phy_state
);
1203 hisi_sas_phy_down(hisi_hba
, phy_no
, (phy_state
& 1 << phy_no
) ? 1 : 0);
1205 sl_ctrl
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
1206 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
,
1207 sl_ctrl
&(~SL_CTA_MSK
));
1209 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
1210 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
1211 txid_auto
| CT3_MSK
);
1213 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
, CHL_INT0_NOT_RDY_MSK
);
1214 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 0);
1219 static void phy_bcast_v3_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
1221 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1222 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1223 struct sas_ha_struct
*sas_ha
= &hisi_hba
->sha
;
1225 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 1);
1226 sas_ha
->notify_port_event(sas_phy
, PORTE_BROADCAST_RCVD
);
1227 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
1228 CHL_INT0_SL_RX_BCST_ACK_MSK
);
1229 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 0);
1232 static irqreturn_t
int_phy_up_down_bcast_v3_hw(int irq_no
, void *p
)
1234 struct hisi_hba
*hisi_hba
= p
;
1237 irqreturn_t res
= IRQ_NONE
;
1239 irq_msk
= hisi_sas_read32(hisi_hba
, CHNL_INT_STATUS
)
1243 u32 irq_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1245 u32 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1246 int rdy
= phy_state
& (1 << phy_no
);
1249 if (irq_value
& CHL_INT0_SL_PHY_ENABLE_MSK
)
1251 if (phy_up_v3_hw(phy_no
, hisi_hba
)
1254 if (irq_value
& CHL_INT0_SL_RX_BCST_ACK_MSK
)
1256 phy_bcast_v3_hw(phy_no
, hisi_hba
);
1258 if (irq_value
& CHL_INT0_NOT_RDY_MSK
)
1260 if (phy_down_v3_hw(phy_no
, hisi_hba
)
1272 static const struct hisi_sas_hw_error port_axi_error
[] = {
1274 .irq_msk
= BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF
),
1275 .msg
= "dma_tx_axi_wr_err",
1278 .irq_msk
= BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF
),
1279 .msg
= "dma_tx_axi_rd_err",
1282 .irq_msk
= BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF
),
1283 .msg
= "dma_rx_axi_wr_err",
1286 .irq_msk
= BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF
),
1287 .msg
= "dma_rx_axi_rd_err",
1291 static irqreturn_t
int_chnl_int_v3_hw(int irq_no
, void *p
)
1293 struct hisi_hba
*hisi_hba
= p
;
1294 struct device
*dev
= hisi_hba
->dev
;
1295 u32 ent_msk
, ent_tmp
, irq_msk
;
1298 ent_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
1300 ent_msk
|= ENT_INT_SRC_MSK3_ENT95_MSK_MSK
;
1301 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_msk
);
1303 irq_msk
= hisi_sas_read32(hisi_hba
, CHNL_INT_STATUS
)
1307 u32 irq_value0
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1309 u32 irq_value1
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1311 u32 irq_value2
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1314 if ((irq_msk
& (4 << (phy_no
* 4))) &&
1318 for (i
= 0; i
< ARRAY_SIZE(port_axi_error
); i
++) {
1319 const struct hisi_sas_hw_error
*error
=
1322 if (!(irq_value1
& error
->irq_msk
))
1325 dev_warn(dev
, "%s error (phy%d 0x%x) found!\n",
1326 error
->msg
, phy_no
, irq_value1
);
1327 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
1330 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1331 CHL_INT1
, irq_value1
);
1334 if (irq_msk
& (8 << (phy_no
* 4)) && irq_value2
)
1335 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1336 CHL_INT2
, irq_value2
);
1339 if (irq_msk
& (2 << (phy_no
* 4)) && irq_value0
) {
1340 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1341 CHL_INT0
, irq_value0
1342 & (~CHL_INT0_SL_RX_BCST_ACK_MSK
)
1343 & (~CHL_INT0_SL_PHY_ENABLE_MSK
)
1344 & (~CHL_INT0_NOT_RDY_MSK
));
1346 irq_msk
&= ~(0xe << (phy_no
* 4));
1350 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_tmp
);
1355 static const struct hisi_sas_hw_error axi_error
[] = {
1356 { .msk
= BIT(0), .msg
= "IOST_AXI_W_ERR" },
1357 { .msk
= BIT(1), .msg
= "IOST_AXI_R_ERR" },
1358 { .msk
= BIT(2), .msg
= "ITCT_AXI_W_ERR" },
1359 { .msk
= BIT(3), .msg
= "ITCT_AXI_R_ERR" },
1360 { .msk
= BIT(4), .msg
= "SATA_AXI_W_ERR" },
1361 { .msk
= BIT(5), .msg
= "SATA_AXI_R_ERR" },
1362 { .msk
= BIT(6), .msg
= "DQE_AXI_R_ERR" },
1363 { .msk
= BIT(7), .msg
= "CQE_AXI_W_ERR" },
1367 static const struct hisi_sas_hw_error fifo_error
[] = {
1368 { .msk
= BIT(8), .msg
= "CQE_WINFO_FIFO" },
1369 { .msk
= BIT(9), .msg
= "CQE_MSG_FIFIO" },
1370 { .msk
= BIT(10), .msg
= "GETDQE_FIFO" },
1371 { .msk
= BIT(11), .msg
= "CMDP_FIFO" },
1372 { .msk
= BIT(12), .msg
= "AWTCTRL_FIFO" },
1376 static const struct hisi_sas_hw_error fatal_axi_error
[] = {
1378 .irq_msk
= BIT(ENT_INT_SRC3_WP_DEPTH_OFF
),
1379 .msg
= "write pointer and depth",
1382 .irq_msk
= BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF
),
1383 .msg
= "iptt no match slot",
1386 .irq_msk
= BIT(ENT_INT_SRC3_RP_DEPTH_OFF
),
1387 .msg
= "read pointer and depth",
1390 .irq_msk
= BIT(ENT_INT_SRC3_AXI_OFF
),
1391 .reg
= HGC_AXI_FIFO_ERR_INFO
,
1395 .irq_msk
= BIT(ENT_INT_SRC3_FIFO_OFF
),
1396 .reg
= HGC_AXI_FIFO_ERR_INFO
,
1400 .irq_msk
= BIT(ENT_INT_SRC3_LM_OFF
),
1401 .msg
= "LM add/fetch list",
1404 .irq_msk
= BIT(ENT_INT_SRC3_ABT_OFF
),
1405 .msg
= "SAS_HGC_ABT fetch LM list",
1409 static irqreturn_t
fatal_axi_int_v3_hw(int irq_no
, void *p
)
1411 u32 irq_value
, irq_msk
;
1412 struct hisi_hba
*hisi_hba
= p
;
1413 struct device
*dev
= hisi_hba
->dev
;
1416 irq_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
1417 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, irq_msk
| 0x1df00);
1419 irq_value
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
1421 for (i
= 0; i
< ARRAY_SIZE(fatal_axi_error
); i
++) {
1422 const struct hisi_sas_hw_error
*error
= &fatal_axi_error
[i
];
1424 if (!(irq_value
& error
->irq_msk
))
1428 const struct hisi_sas_hw_error
*sub
= error
->sub
;
1429 u32 err_value
= hisi_sas_read32(hisi_hba
, error
->reg
);
1431 for (; sub
->msk
|| sub
->msg
; sub
++) {
1432 if (!(err_value
& sub
->msk
))
1435 dev_warn(dev
, "%s error (0x%x) found!\n",
1436 sub
->msg
, irq_value
);
1437 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
1440 dev_warn(dev
, "%s error (0x%x) found!\n",
1441 error
->msg
, irq_value
);
1442 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
1446 if (irq_value
& BIT(ENT_INT_SRC3_ITC_INT_OFF
)) {
1447 u32 reg_val
= hisi_sas_read32(hisi_hba
, ITCT_CLR
);
1448 u32 dev_id
= reg_val
& ITCT_DEV_MSK
;
1449 struct hisi_sas_device
*sas_dev
=
1450 &hisi_hba
->devices
[dev_id
];
1452 hisi_sas_write32(hisi_hba
, ITCT_CLR
, 0);
1453 dev_dbg(dev
, "clear ITCT ok\n");
1454 complete(sas_dev
->completion
);
1457 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
, irq_value
& 0x1df00);
1458 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, irq_msk
);
1464 slot_err_v3_hw(struct hisi_hba
*hisi_hba
, struct sas_task
*task
,
1465 struct hisi_sas_slot
*slot
)
1467 struct task_status_struct
*ts
= &task
->task_status
;
1468 struct hisi_sas_complete_v3_hdr
*complete_queue
=
1469 hisi_hba
->complete_hdr
[slot
->cmplt_queue
];
1470 struct hisi_sas_complete_v3_hdr
*complete_hdr
=
1471 &complete_queue
[slot
->cmplt_queue_slot
];
1472 struct hisi_sas_err_record_v3
*record
=
1473 hisi_sas_status_buf_addr_mem(slot
);
1474 u32 dma_rx_err_type
= record
->dma_rx_err_type
;
1475 u32 trans_tx_fail_type
= record
->trans_tx_fail_type
;
1477 switch (task
->task_proto
) {
1478 case SAS_PROTOCOL_SSP
:
1479 if (dma_rx_err_type
& RX_DATA_LEN_UNDERFLOW_MSK
) {
1480 ts
->residual
= trans_tx_fail_type
;
1481 ts
->stat
= SAS_DATA_UNDERRUN
;
1482 } else if (complete_hdr
->dw3
& CMPLT_HDR_IO_IN_TARGET_MSK
) {
1483 ts
->stat
= SAS_QUEUE_FULL
;
1486 ts
->stat
= SAS_OPEN_REJECT
;
1487 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
1490 case SAS_PROTOCOL_SATA
:
1491 case SAS_PROTOCOL_STP
:
1492 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
1493 if (dma_rx_err_type
& RX_DATA_LEN_UNDERFLOW_MSK
) {
1494 ts
->residual
= trans_tx_fail_type
;
1495 ts
->stat
= SAS_DATA_UNDERRUN
;
1496 } else if (complete_hdr
->dw3
& CMPLT_HDR_IO_IN_TARGET_MSK
) {
1497 ts
->stat
= SAS_PHY_DOWN
;
1500 ts
->stat
= SAS_OPEN_REJECT
;
1501 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
1503 hisi_sas_sata_done(task
, slot
);
1505 case SAS_PROTOCOL_SMP
:
1506 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
1514 slot_complete_v3_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_slot
*slot
)
1516 struct sas_task
*task
= slot
->task
;
1517 struct hisi_sas_device
*sas_dev
;
1518 struct device
*dev
= hisi_hba
->dev
;
1519 struct task_status_struct
*ts
;
1520 struct domain_device
*device
;
1521 enum exec_status sts
;
1522 struct hisi_sas_complete_v3_hdr
*complete_queue
=
1523 hisi_hba
->complete_hdr
[slot
->cmplt_queue
];
1524 struct hisi_sas_complete_v3_hdr
*complete_hdr
=
1525 &complete_queue
[slot
->cmplt_queue_slot
];
1527 unsigned long flags
;
1529 if (unlikely(!task
|| !task
->lldd_task
|| !task
->dev
))
1532 ts
= &task
->task_status
;
1534 sas_dev
= device
->lldd_dev
;
1536 spin_lock_irqsave(&task
->task_state_lock
, flags
);
1537 aborted
= task
->task_state_flags
& SAS_TASK_STATE_ABORTED
;
1538 task
->task_state_flags
&=
1539 ~(SAS_TASK_STATE_PENDING
| SAS_TASK_AT_INITIATOR
);
1540 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
1542 memset(ts
, 0, sizeof(*ts
));
1543 ts
->resp
= SAS_TASK_COMPLETE
;
1544 if (unlikely(aborted
)) {
1545 ts
->stat
= SAS_ABORTED_TASK
;
1546 spin_lock_irqsave(&hisi_hba
->lock
, flags
);
1547 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
1548 spin_unlock_irqrestore(&hisi_hba
->lock
, flags
);
1552 if (unlikely(!sas_dev
)) {
1553 dev_dbg(dev
, "slot complete: port has not device\n");
1554 ts
->stat
= SAS_PHY_DOWN
;
1559 * Use SAS+TMF status codes
1561 switch ((complete_hdr
->dw0
& CMPLT_HDR_ABORT_STAT_MSK
)
1562 >> CMPLT_HDR_ABORT_STAT_OFF
) {
1563 case STAT_IO_ABORTED
:
1564 /* this IO has been aborted by abort command */
1565 ts
->stat
= SAS_ABORTED_TASK
;
1567 case STAT_IO_COMPLETE
:
1568 /* internal abort command complete */
1569 ts
->stat
= TMF_RESP_FUNC_SUCC
;
1571 case STAT_IO_NO_DEVICE
:
1572 ts
->stat
= TMF_RESP_FUNC_COMPLETE
;
1574 case STAT_IO_NOT_VALID
:
1576 * abort single IO, the controller can't find the IO
1578 ts
->stat
= TMF_RESP_FUNC_FAILED
;
1584 /* check for erroneous completion */
1585 if ((complete_hdr
->dw0
& CMPLT_HDR_CMPLT_MSK
) == 0x3) {
1586 slot_err_v3_hw(hisi_hba
, task
, slot
);
1587 if (unlikely(slot
->abort
))
1592 switch (task
->task_proto
) {
1593 case SAS_PROTOCOL_SSP
: {
1594 struct ssp_response_iu
*iu
=
1595 hisi_sas_status_buf_addr_mem(slot
) +
1596 sizeof(struct hisi_sas_err_record
);
1598 sas_ssp_task_response(dev
, task
, iu
);
1601 case SAS_PROTOCOL_SMP
: {
1602 struct scatterlist
*sg_resp
= &task
->smp_task
.smp_resp
;
1605 ts
->stat
= SAM_STAT_GOOD
;
1606 to
= kmap_atomic(sg_page(sg_resp
));
1608 dma_unmap_sg(dev
, &task
->smp_task
.smp_resp
, 1,
1610 dma_unmap_sg(dev
, &task
->smp_task
.smp_req
, 1,
1612 memcpy(to
+ sg_resp
->offset
,
1613 hisi_sas_status_buf_addr_mem(slot
) +
1614 sizeof(struct hisi_sas_err_record
),
1615 sg_dma_len(sg_resp
));
1619 case SAS_PROTOCOL_SATA
:
1620 case SAS_PROTOCOL_STP
:
1621 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
1622 ts
->stat
= SAM_STAT_GOOD
;
1623 hisi_sas_sata_done(task
, slot
);
1626 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
1630 if (!slot
->port
->port_attached
) {
1631 dev_err(dev
, "slot complete: port %d has removed\n",
1632 slot
->port
->sas_port
.id
);
1633 ts
->stat
= SAS_PHY_DOWN
;
1637 spin_lock_irqsave(&task
->task_state_lock
, flags
);
1638 task
->task_state_flags
|= SAS_TASK_STATE_DONE
;
1639 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
1640 spin_lock_irqsave(&hisi_hba
->lock
, flags
);
1641 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
1642 spin_unlock_irqrestore(&hisi_hba
->lock
, flags
);
1645 if (task
->task_done
)
1646 task
->task_done(task
);
1651 static void cq_tasklet_v3_hw(unsigned long val
)
1653 struct hisi_sas_cq
*cq
= (struct hisi_sas_cq
*)val
;
1654 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
1655 struct hisi_sas_slot
*slot
;
1656 struct hisi_sas_complete_v3_hdr
*complete_queue
;
1657 u32 rd_point
= cq
->rd_point
, wr_point
;
1659 struct hisi_sas_dq
*dq
= &hisi_hba
->dq
[queue
];
1661 complete_queue
= hisi_hba
->complete_hdr
[queue
];
1663 spin_lock(&dq
->lock
);
1664 wr_point
= hisi_sas_read32(hisi_hba
, COMPL_Q_0_WR_PTR
+
1667 while (rd_point
!= wr_point
) {
1668 struct hisi_sas_complete_v3_hdr
*complete_hdr
;
1671 complete_hdr
= &complete_queue
[rd_point
];
1673 iptt
= (complete_hdr
->dw1
) & CMPLT_HDR_IPTT_MSK
;
1674 slot
= &hisi_hba
->slot_info
[iptt
];
1675 slot
->cmplt_queue_slot
= rd_point
;
1676 slot
->cmplt_queue
= queue
;
1677 slot_complete_v3_hw(hisi_hba
, slot
);
1679 if (++rd_point
>= HISI_SAS_QUEUE_SLOTS
)
1683 /* update rd_point */
1684 cq
->rd_point
= rd_point
;
1685 hisi_sas_write32(hisi_hba
, COMPL_Q_0_RD_PTR
+ (0x14 * queue
), rd_point
);
1686 spin_unlock(&dq
->lock
);
1689 static irqreturn_t
cq_interrupt_v3_hw(int irq_no
, void *p
)
1691 struct hisi_sas_cq
*cq
= p
;
1692 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
1695 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 1 << queue
);
1697 tasklet_schedule(&cq
->tasklet
);
1702 static int interrupt_init_v3_hw(struct hisi_hba
*hisi_hba
)
1704 struct device
*dev
= hisi_hba
->dev
;
1705 struct pci_dev
*pdev
= hisi_hba
->pci_dev
;
1708 int max_msi
= HISI_SAS_MSI_COUNT_V3_HW
;
1710 vectors
= pci_alloc_irq_vectors(hisi_hba
->pci_dev
, 1,
1711 max_msi
, PCI_IRQ_MSI
);
1712 if (vectors
< max_msi
) {
1713 dev_err(dev
, "could not allocate all msi (%d)\n", vectors
);
1717 rc
= devm_request_irq(dev
, pci_irq_vector(pdev
, 1),
1718 int_phy_up_down_bcast_v3_hw
, 0,
1719 DRV_NAME
" phy", hisi_hba
);
1721 dev_err(dev
, "could not request phy interrupt, rc=%d\n", rc
);
1723 goto free_irq_vectors
;
1726 rc
= devm_request_irq(dev
, pci_irq_vector(pdev
, 2),
1727 int_chnl_int_v3_hw
, 0,
1728 DRV_NAME
" channel", hisi_hba
);
1730 dev_err(dev
, "could not request chnl interrupt, rc=%d\n", rc
);
1735 rc
= devm_request_irq(dev
, pci_irq_vector(pdev
, 11),
1736 fatal_axi_int_v3_hw
, 0,
1737 DRV_NAME
" fatal", hisi_hba
);
1739 dev_err(dev
, "could not request fatal interrupt, rc=%d\n", rc
);
1741 goto free_chnl_interrupt
;
1744 /* Init tasklets for cq only */
1745 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
1746 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[i
];
1747 struct tasklet_struct
*t
= &cq
->tasklet
;
1749 rc
= devm_request_irq(dev
, pci_irq_vector(pdev
, i
+16),
1750 cq_interrupt_v3_hw
, 0,
1751 DRV_NAME
" cq", cq
);
1754 "could not request cq%d interrupt, rc=%d\n",
1760 tasklet_init(t
, cq_tasklet_v3_hw
, (unsigned long)cq
);
1766 for (k
= 0; k
< i
; k
++) {
1767 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[k
];
1769 free_irq(pci_irq_vector(pdev
, k
+16), cq
);
1771 free_irq(pci_irq_vector(pdev
, 11), hisi_hba
);
1772 free_chnl_interrupt
:
1773 free_irq(pci_irq_vector(pdev
, 2), hisi_hba
);
1775 free_irq(pci_irq_vector(pdev
, 1), hisi_hba
);
1777 pci_free_irq_vectors(pdev
);
1781 static int hisi_sas_v3_init(struct hisi_hba
*hisi_hba
)
1785 rc
= hw_init_v3_hw(hisi_hba
);
1789 rc
= interrupt_init_v3_hw(hisi_hba
);
1796 static void phy_set_linkrate_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
,
1797 struct sas_phy_linkrates
*r
)
1799 u32 prog_phy_link_rate
=
1800 hisi_sas_phy_read32(hisi_hba
, phy_no
, PROG_PHY_LINK_RATE
);
1801 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1802 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1804 enum sas_linkrate min
, max
;
1807 if (r
->maximum_linkrate
== SAS_LINK_RATE_UNKNOWN
) {
1808 max
= sas_phy
->phy
->maximum_linkrate
;
1809 min
= r
->minimum_linkrate
;
1810 } else if (r
->minimum_linkrate
== SAS_LINK_RATE_UNKNOWN
) {
1811 max
= r
->maximum_linkrate
;
1812 min
= sas_phy
->phy
->minimum_linkrate
;
1816 sas_phy
->phy
->maximum_linkrate
= max
;
1817 sas_phy
->phy
->minimum_linkrate
= min
;
1819 min
-= SAS_LINK_RATE_1_5_GBPS
;
1820 max
-= SAS_LINK_RATE_1_5_GBPS
;
1822 for (i
= 0; i
<= max
; i
++)
1823 rate_mask
|= 1 << (i
* 2);
1825 prog_phy_link_rate
&= ~0xff;
1826 prog_phy_link_rate
|= rate_mask
;
1828 hisi_sas_phy_write32(hisi_hba
, phy_no
, PROG_PHY_LINK_RATE
,
1829 prog_phy_link_rate
);
1831 phy_hard_reset_v3_hw(hisi_hba
, phy_no
);
1834 static void interrupt_disable_v3_hw(struct hisi_hba
*hisi_hba
)
1836 struct pci_dev
*pdev
= hisi_hba
->pci_dev
;
1839 synchronize_irq(pci_irq_vector(pdev
, 1));
1840 synchronize_irq(pci_irq_vector(pdev
, 2));
1841 synchronize_irq(pci_irq_vector(pdev
, 11));
1842 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
1843 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+ 0x4 * i
, 0x1);
1844 synchronize_irq(pci_irq_vector(pdev
, i
+ 16));
1847 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0xffffffff);
1848 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0xffffffff);
1849 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0xffffffff);
1850 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0xffffffff);
1852 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1853 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xffffffff);
1854 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0xffffffff);
1855 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_NOT_RDY_MSK
, 0x1);
1856 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_PHY_ENA_MSK
, 0x1);
1857 hisi_sas_phy_write32(hisi_hba
, i
, SL_RX_BCAST_CHK_MSK
, 0x1);
1861 static u32
get_phys_state_v3_hw(struct hisi_hba
*hisi_hba
)
1863 return hisi_sas_read32(hisi_hba
, PHY_STATE
);
1866 static void phy_get_events_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1868 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1869 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1870 struct sas_phy
*sphy
= sas_phy
->phy
;
1873 /* loss dword sync */
1874 reg_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
, ERR_CNT_DWS_LOST
);
1875 sphy
->loss_of_dword_sync_count
+= reg_value
;
1877 /* phy reset problem */
1878 reg_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
, ERR_CNT_RESET_PROB
);
1879 sphy
->phy_reset_problem_count
+= reg_value
;
1882 reg_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
, ERR_CNT_INVLD_DW
);
1883 sphy
->invalid_dword_count
+= reg_value
;
1886 reg_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
, ERR_CNT_DISP_ERR
);
1887 sphy
->running_disparity_error_count
+= reg_value
;
1891 static int soft_reset_v3_hw(struct hisi_hba
*hisi_hba
)
1893 struct device
*dev
= hisi_hba
->dev
;
1897 interrupt_disable_v3_hw(hisi_hba
);
1898 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0x0);
1899 hisi_sas_kill_tasklets(hisi_hba
);
1901 hisi_sas_stop_phys(hisi_hba
);
1905 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
+ AM_CTRL_GLOBAL
, 0x1);
1907 /* wait until bus idle */
1908 rc
= readl_poll_timeout(hisi_hba
->regs
+ AXI_MASTER_CFG_BASE
+
1909 AM_CURR_TRANS_RETURN
, status
, status
== 0x3, 10, 100);
1911 dev_err(dev
, "axi bus is not idle, rc = %d\n", rc
);
1915 hisi_sas_init_mem(hisi_hba
);
1917 return hw_init_v3_hw(hisi_hba
);
1920 static const struct hisi_sas_hw hisi_sas_v3_hw
= {
1921 .hw_init
= hisi_sas_v3_init
,
1922 .setup_itct
= setup_itct_v3_hw
,
1923 .max_command_entries
= HISI_SAS_COMMAND_ENTRIES_V3_HW
,
1924 .get_wideport_bitmap
= get_wideport_bitmap_v3_hw
,
1925 .complete_hdr_size
= sizeof(struct hisi_sas_complete_v3_hdr
),
1926 .clear_itct
= clear_itct_v3_hw
,
1927 .sl_notify
= sl_notify_v3_hw
,
1928 .prep_ssp
= prep_ssp_v3_hw
,
1929 .prep_smp
= prep_smp_v3_hw
,
1930 .prep_stp
= prep_ata_v3_hw
,
1931 .prep_abort
= prep_abort_v3_hw
,
1932 .get_free_slot
= get_free_slot_v3_hw
,
1933 .start_delivery
= start_delivery_v3_hw
,
1934 .slot_complete
= slot_complete_v3_hw
,
1935 .phys_init
= phys_init_v3_hw
,
1936 .phy_start
= start_phy_v3_hw
,
1937 .phy_disable
= disable_phy_v3_hw
,
1938 .phy_hard_reset
= phy_hard_reset_v3_hw
,
1939 .phy_get_max_linkrate
= phy_get_max_linkrate_v3_hw
,
1940 .phy_set_linkrate
= phy_set_linkrate_v3_hw
,
1941 .dereg_device
= dereg_device_v3_hw
,
1942 .soft_reset
= soft_reset_v3_hw
,
1943 .get_phys_state
= get_phys_state_v3_hw
,
1944 .get_events
= phy_get_events_v3_hw
,
1947 static struct Scsi_Host
*
1948 hisi_sas_shost_alloc_pci(struct pci_dev
*pdev
)
1950 struct Scsi_Host
*shost
;
1951 struct hisi_hba
*hisi_hba
;
1952 struct device
*dev
= &pdev
->dev
;
1954 shost
= scsi_host_alloc(hisi_sas_sht
, sizeof(*hisi_hba
));
1956 dev_err(dev
, "shost alloc failed\n");
1959 hisi_hba
= shost_priv(shost
);
1961 INIT_WORK(&hisi_hba
->rst_work
, hisi_sas_rst_work_handler
);
1962 hisi_hba
->hw
= &hisi_sas_v3_hw
;
1963 hisi_hba
->pci_dev
= pdev
;
1964 hisi_hba
->dev
= dev
;
1965 hisi_hba
->shost
= shost
;
1966 SHOST_TO_SAS_HA(shost
) = &hisi_hba
->sha
;
1968 timer_setup(&hisi_hba
->timer
, NULL
, 0);
1970 if (hisi_sas_get_fw_info(hisi_hba
) < 0)
1973 if (hisi_sas_alloc(hisi_hba
, shost
)) {
1974 hisi_sas_free(hisi_hba
);
1980 scsi_host_put(shost
);
1981 dev_err(dev
, "shost alloc failed\n");
1986 hisi_sas_v3_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1988 struct Scsi_Host
*shost
;
1989 struct hisi_hba
*hisi_hba
;
1990 struct device
*dev
= &pdev
->dev
;
1991 struct asd_sas_phy
**arr_phy
;
1992 struct asd_sas_port
**arr_port
;
1993 struct sas_ha_struct
*sha
;
1994 int rc
, phy_nr
, port_nr
, i
;
1996 rc
= pci_enable_device(pdev
);
2000 pci_set_master(pdev
);
2002 rc
= pci_request_regions(pdev
, DRV_NAME
);
2004 goto err_out_disable_device
;
2006 if ((pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) != 0) ||
2007 (pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64)) != 0)) {
2008 if ((pci_set_dma_mask(pdev
, DMA_BIT_MASK(32)) != 0) ||
2009 (pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)) != 0)) {
2010 dev_err(dev
, "No usable DMA addressing method\n");
2012 goto err_out_regions
;
2016 shost
= hisi_sas_shost_alloc_pci(pdev
);
2019 goto err_out_regions
;
2022 sha
= SHOST_TO_SAS_HA(shost
);
2023 hisi_hba
= shost_priv(shost
);
2024 dev_set_drvdata(dev
, sha
);
2026 hisi_hba
->regs
= pcim_iomap(pdev
, 5, 0);
2027 if (!hisi_hba
->regs
) {
2028 dev_err(dev
, "cannot map register.\n");
2033 phy_nr
= port_nr
= hisi_hba
->n_phy
;
2035 arr_phy
= devm_kcalloc(dev
, phy_nr
, sizeof(void *), GFP_KERNEL
);
2036 arr_port
= devm_kcalloc(dev
, port_nr
, sizeof(void *), GFP_KERNEL
);
2037 if (!arr_phy
|| !arr_port
) {
2042 sha
->sas_phy
= arr_phy
;
2043 sha
->sas_port
= arr_port
;
2044 sha
->core
.shost
= shost
;
2045 sha
->lldd_ha
= hisi_hba
;
2047 shost
->transportt
= hisi_sas_stt
;
2048 shost
->max_id
= HISI_SAS_MAX_DEVICES
;
2049 shost
->max_lun
= ~0;
2050 shost
->max_channel
= 1;
2051 shost
->max_cmd_len
= 16;
2052 shost
->sg_tablesize
= min_t(u16
, SG_ALL
, HISI_SAS_SGE_PAGE_CNT
);
2053 shost
->can_queue
= hisi_hba
->hw
->max_command_entries
;
2054 shost
->cmd_per_lun
= hisi_hba
->hw
->max_command_entries
;
2056 sha
->sas_ha_name
= DRV_NAME
;
2058 sha
->lldd_module
= THIS_MODULE
;
2059 sha
->sas_addr
= &hisi_hba
->sas_addr
[0];
2060 sha
->num_phys
= hisi_hba
->n_phy
;
2061 sha
->core
.shost
= hisi_hba
->shost
;
2063 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
2064 sha
->sas_phy
[i
] = &hisi_hba
->phy
[i
].sas_phy
;
2065 sha
->sas_port
[i
] = &hisi_hba
->port
[i
].sas_port
;
2068 hisi_sas_init_add(hisi_hba
);
2070 rc
= scsi_add_host(shost
, dev
);
2074 rc
= sas_register_ha(sha
);
2076 goto err_out_register_ha
;
2078 rc
= hisi_hba
->hw
->hw_init(hisi_hba
);
2080 goto err_out_register_ha
;
2082 scsi_scan_host(shost
);
2086 err_out_register_ha
:
2087 scsi_remove_host(shost
);
2089 scsi_host_put(shost
);
2091 pci_release_regions(pdev
);
2092 err_out_disable_device
:
2093 pci_disable_device(pdev
);
2099 hisi_sas_v3_destroy_irqs(struct pci_dev
*pdev
, struct hisi_hba
*hisi_hba
)
2103 free_irq(pci_irq_vector(pdev
, 1), hisi_hba
);
2104 free_irq(pci_irq_vector(pdev
, 2), hisi_hba
);
2105 free_irq(pci_irq_vector(pdev
, 11), hisi_hba
);
2106 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
2107 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[i
];
2109 free_irq(pci_irq_vector(pdev
, i
+16), cq
);
2111 pci_free_irq_vectors(pdev
);
2114 static void hisi_sas_v3_remove(struct pci_dev
*pdev
)
2116 struct device
*dev
= &pdev
->dev
;
2117 struct sas_ha_struct
*sha
= dev_get_drvdata(dev
);
2118 struct hisi_hba
*hisi_hba
= sha
->lldd_ha
;
2119 struct Scsi_Host
*shost
= sha
->core
.shost
;
2121 sas_unregister_ha(sha
);
2122 sas_remove_host(sha
->core
.shost
);
2124 hisi_sas_v3_destroy_irqs(pdev
, hisi_hba
);
2125 hisi_sas_kill_tasklets(hisi_hba
);
2126 pci_release_regions(pdev
);
2127 pci_disable_device(pdev
);
2128 hisi_sas_free(hisi_hba
);
2129 scsi_host_put(shost
);
2133 /* instances of the controller */
2137 static const struct pci_device_id sas_v3_pci_table
[] = {
2138 { PCI_VDEVICE(HUAWEI
, 0xa230), hip08
},
2142 static struct pci_driver sas_v3_pci_driver
= {
2144 .id_table
= sas_v3_pci_table
,
2145 .probe
= hisi_sas_v3_probe
,
2146 .remove
= hisi_sas_v3_remove
,
2149 module_pci_driver(sas_v3_pci_driver
);
2151 MODULE_LICENSE("GPL");
2152 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2153 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2154 MODULE_ALIAS("platform:" DRV_NAME
);