2 * Copyright (c) 2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
12 #define DRV_NAME "hisi_sas_v3_hw"
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CFG_1US_TIMER_TRSH 0xcc
55 #define CHNL_INT_STATUS 0x148
56 #define HGC_AXI_FIFO_ERR_INFO 0x154
57 #define AXI_ERR_INFO_OFF 0
58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
59 #define FIFO_ERR_INFO_OFF 8
60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
61 #define INT_COAL_EN 0x19c
62 #define OQ_INT_COAL_TIME 0x1a0
63 #define OQ_INT_COAL_CNT 0x1a4
64 #define ENT_INT_COAL_TIME 0x1a8
65 #define ENT_INT_COAL_CNT 0x1ac
66 #define OQ_INT_SRC 0x1b0
67 #define OQ_INT_SRC_MSK 0x1b4
68 #define ENT_INT_SRC1 0x1b8
69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
73 #define ENT_INT_SRC2 0x1bc
74 #define ENT_INT_SRC3 0x1c0
75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
78 #define ENT_INT_SRC3_AXI_OFF 11
79 #define ENT_INT_SRC3_FIFO_OFF 12
80 #define ENT_INT_SRC3_LM_OFF 14
81 #define ENT_INT_SRC3_ITC_INT_OFF 15
82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
83 #define ENT_INT_SRC3_ABT_OFF 16
84 #define ENT_INT_SRC_MSK1 0x1c4
85 #define ENT_INT_SRC_MSK2 0x1c8
86 #define ENT_INT_SRC_MSK3 0x1cc
87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
89 #define CHNL_ENT_INT_MSK 0x1d4
90 #define HGC_COM_INT_MSK 0x1d8
91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
92 #define SAS_ECC_INTR 0x1e8
93 #define SAS_ECC_INTR_MSK 0x1ec
94 #define HGC_ERR_STAT_EN 0x238
95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
97 #define DLVRY_Q_0_DEPTH 0x268
98 #define DLVRY_Q_0_WR_PTR 0x26c
99 #define DLVRY_Q_0_RD_PTR 0x270
100 #define HYPER_STREAM_ID_EN_CFG 0xc80
101 #define OQ0_INT_SRC_MSK 0xc90
102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
104 #define COMPL_Q_0_DEPTH 0x4e8
105 #define COMPL_Q_0_WR_PTR 0x4ec
106 #define COMPL_Q_0_RD_PTR 0x4f0
107 #define AWQOS_AWCACHE_CFG 0xc84
108 #define ARQOS_ARCACHE_CFG 0xc88
110 /* phy registers requiring init */
111 #define PORT_BASE (0x2000)
112 #define PHY_CFG (PORT_BASE + 0x0)
113 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
114 #define PHY_CFG_ENA_OFF 0
115 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
116 #define PHY_CFG_DC_OPT_OFF 2
117 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
118 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
119 #define PHY_CTRL (PORT_BASE + 0x14)
120 #define PHY_CTRL_RESET_OFF 0
121 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
122 #define SL_CFG (PORT_BASE + 0x84)
123 #define SL_CONTROL (PORT_BASE + 0x94)
124 #define SL_CONTROL_NOTIFY_EN_OFF 0
125 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
126 #define SL_CTA_OFF 17
127 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
128 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
129 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
130 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
131 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
132 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
133 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
134 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
135 #define TXID_AUTO (PORT_BASE + 0xb8)
137 #define CT3_MSK (0x1 << CT3_OFF)
138 #define TX_HARDRST_OFF 2
139 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
140 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
141 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
142 #define STP_LINK_TIMER (PORT_BASE + 0x120)
143 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
144 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
145 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
146 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
147 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
148 #define CHL_INT0 (PORT_BASE + 0x1b4)
149 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
150 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
151 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
152 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
153 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
154 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
155 #define CHL_INT0_NOT_RDY_OFF 4
156 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
157 #define CHL_INT0_PHY_RDY_OFF 5
158 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
159 #define CHL_INT1 (PORT_BASE + 0x1b8)
160 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
161 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
162 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
163 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
164 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
165 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
166 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
167 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
168 #define CHL_INT2 (PORT_BASE + 0x1bc)
169 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
170 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
171 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
172 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
173 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
174 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
175 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
176 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
177 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
178 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
179 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
180 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
181 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
182 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
183 #define DMA_TX_STATUS_BUSY_OFF 0
184 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
185 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
186 #define DMA_RX_STATUS_BUSY_OFF 0
187 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
189 #define COARSETUNE_TIME (PORT_BASE + 0x304)
190 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
191 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
192 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
193 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
195 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
196 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
197 #error Max ITCT exceeded
200 #define AXI_MASTER_CFG_BASE (0x5000)
201 #define AM_CTRL_GLOBAL (0x0)
202 #define AM_CURR_TRANS_RETURN (0x150)
204 #define AM_CFG_MAX_TRANS (0x5010)
205 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
206 #define AXI_CFG (0x5100)
207 #define AM_ROB_ECC_ERR_ADDR (0x510c)
208 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
209 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
210 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
211 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
213 /* RAS registers need init */
214 #define RAS_BASE (0x6000)
215 #define SAS_RAS_INTR0 (RAS_BASE)
216 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
217 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
218 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
219 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c)
220 #define SAS_RAS_INTR2 (RAS_BASE + 0x20)
221 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24)
223 /* HW dma structures */
224 /* Delivery queue header */
226 #define CMD_HDR_ABORT_FLAG_OFF 0
227 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
228 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
229 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
230 #define CMD_HDR_RESP_REPORT_OFF 5
231 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
232 #define CMD_HDR_TLR_CTRL_OFF 6
233 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
234 #define CMD_HDR_PORT_OFF 18
235 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
236 #define CMD_HDR_PRIORITY_OFF 27
237 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
238 #define CMD_HDR_CMD_OFF 29
239 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
241 #define CMD_HDR_UNCON_CMD_OFF 3
242 #define CMD_HDR_DIR_OFF 5
243 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
244 #define CMD_HDR_RESET_OFF 7
245 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
246 #define CMD_HDR_VDTL_OFF 10
247 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
248 #define CMD_HDR_FRAME_TYPE_OFF 11
249 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
250 #define CMD_HDR_DEV_ID_OFF 16
251 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
253 #define CMD_HDR_CFL_OFF 0
254 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
255 #define CMD_HDR_NCQ_TAG_OFF 10
256 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
257 #define CMD_HDR_MRFL_OFF 15
258 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
259 #define CMD_HDR_SG_MOD_OFF 24
260 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
262 #define CMD_HDR_IPTT_OFF 0
263 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
265 #define CMD_HDR_DIF_SGL_LEN_OFF 0
266 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
267 #define CMD_HDR_DATA_SGL_LEN_OFF 16
268 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
270 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
271 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
272 #define CMD_HDR_ABORT_IPTT_OFF 16
273 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
275 /* Completion header */
277 #define CMPLT_HDR_CMPLT_OFF 0
278 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
279 #define CMPLT_HDR_ERROR_PHASE_OFF 2
280 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
281 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
282 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
283 #define CMPLT_HDR_ERX_OFF 12
284 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
285 #define CMPLT_HDR_ABORT_STAT_OFF 13
286 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
288 #define STAT_IO_NOT_VALID 0x1
289 #define STAT_IO_NO_DEVICE 0x2
290 #define STAT_IO_COMPLETE 0x3
291 #define STAT_IO_ABORTED 0x4
293 #define CMPLT_HDR_IPTT_OFF 0
294 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
295 #define CMPLT_HDR_DEV_ID_OFF 16
296 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
298 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
299 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
303 #define ITCT_HDR_DEV_TYPE_OFF 0
304 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
305 #define ITCT_HDR_VALID_OFF 2
306 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
307 #define ITCT_HDR_MCR_OFF 5
308 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
309 #define ITCT_HDR_VLN_OFF 9
310 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
311 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
312 #define ITCT_HDR_AWT_CONTINUE_OFF 25
313 #define ITCT_HDR_PORT_ID_OFF 28
314 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
316 #define ITCT_HDR_INLT_OFF 0
317 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
318 #define ITCT_HDR_RTOLT_OFF 48
319 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
321 struct hisi_sas_complete_v3_hdr
{
328 struct hisi_sas_err_record_v3
{
330 __le32 trans_tx_fail_type
;
333 __le32 trans_rx_fail_type
;
336 __le16 dma_tx_err_type
;
337 __le16 sipc_rx_err_type
;
340 __le32 dma_rx_err_type
;
343 #define RX_DATA_LEN_UNDERFLOW_OFF 6
344 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
346 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
347 #define HISI_SAS_MSI_COUNT_V3_HW 32
349 #define DIR_NO_DATA 0
351 #define DIR_TO_DEVICE 2
352 #define DIR_RESERVED 3
354 #define CMD_IS_UNCONSTRAINT(cmd) \
355 ((cmd == ATA_CMD_READ_LOG_EXT) || \
356 (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
357 (cmd == ATA_CMD_DEV_RESET))
359 static u32
hisi_sas_read32(struct hisi_hba
*hisi_hba
, u32 off
)
361 void __iomem
*regs
= hisi_hba
->regs
+ off
;
366 static u32
hisi_sas_read32_relaxed(struct hisi_hba
*hisi_hba
, u32 off
)
368 void __iomem
*regs
= hisi_hba
->regs
+ off
;
370 return readl_relaxed(regs
);
373 static void hisi_sas_write32(struct hisi_hba
*hisi_hba
, u32 off
, u32 val
)
375 void __iomem
*regs
= hisi_hba
->regs
+ off
;
380 static void hisi_sas_phy_write32(struct hisi_hba
*hisi_hba
, int phy_no
,
383 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
388 static u32
hisi_sas_phy_read32(struct hisi_hba
*hisi_hba
,
391 void __iomem
*regs
= hisi_hba
->regs
+ (0x400 * phy_no
) + off
;
396 static void init_reg_v3_hw(struct hisi_hba
*hisi_hba
)
398 struct pci_dev
*pdev
= hisi_hba
->pci_dev
;
401 /* Global registers init */
402 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
,
403 (u32
)((1ULL << hisi_hba
->queue_count
) - 1));
404 hisi_sas_write32(hisi_hba
, CFG_MAX_TAG
, 0xfff0400);
405 hisi_sas_write32(hisi_hba
, HGC_SAS_TXFAIL_RETRY_CTRL
, 0x108);
406 hisi_sas_write32(hisi_hba
, CFG_1US_TIMER_TRSH
, 0xd);
407 hisi_sas_write32(hisi_hba
, INT_COAL_EN
, 0x1);
408 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_TIME
, 0x1);
409 hisi_sas_write32(hisi_hba
, OQ_INT_COAL_CNT
, 0x1);
410 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 0xffff);
411 hisi_sas_write32(hisi_hba
, ENT_INT_SRC1
, 0xffffffff);
412 hisi_sas_write32(hisi_hba
, ENT_INT_SRC2
, 0xffffffff);
413 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
, 0xffffffff);
414 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0xfefefefe);
415 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0xfefefefe);
416 if (pdev
->revision
>= 0x21)
417 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0xffff7fff);
419 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0xfffe20ff);
420 hisi_sas_write32(hisi_hba
, CHNL_PHYUPDOWN_INT_MSK
, 0x0);
421 hisi_sas_write32(hisi_hba
, CHNL_ENT_INT_MSK
, 0x0);
422 hisi_sas_write32(hisi_hba
, HGC_COM_INT_MSK
, 0x0);
423 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0x0);
424 hisi_sas_write32(hisi_hba
, AWQOS_AWCACHE_CFG
, 0xf0f0);
425 hisi_sas_write32(hisi_hba
, ARQOS_ARCACHE_CFG
, 0xf0f0);
426 for (i
= 0; i
< hisi_hba
->queue_count
; i
++)
427 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+0x4*i
, 0);
429 hisi_sas_write32(hisi_hba
, HYPER_STREAM_ID_EN_CFG
, 1);
431 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
432 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[i
];
433 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
434 u32 prog_phy_link_rate
= 0x800;
436 if (!sas_phy
->phy
|| (sas_phy
->phy
->maximum_linkrate
<
437 SAS_LINK_RATE_1_5_GBPS
)) {
438 prog_phy_link_rate
= 0x855;
440 enum sas_linkrate max
= sas_phy
->phy
->maximum_linkrate
;
443 hisi_sas_get_prog_phy_linkrate_mask(max
) |
446 hisi_sas_phy_write32(hisi_hba
, i
, PROG_PHY_LINK_RATE
,
448 hisi_sas_phy_write32(hisi_hba
, i
, SAS_RX_TRAIN_TIMER
, 0x13e80);
449 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT0
, 0xffffffff);
450 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1
, 0xffffffff);
451 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2
, 0xffffffff);
452 hisi_sas_phy_write32(hisi_hba
, i
, RXOP_CHECK_CFG_H
, 0x1000);
453 if (pdev
->revision
>= 0x21)
454 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
,
457 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
,
459 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0xffffbfe);
460 hisi_sas_phy_write32(hisi_hba
, i
, PHY_CTRL_RDY_MSK
, 0x0);
461 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_NOT_RDY_MSK
, 0x0);
462 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_DWS_RESET_MSK
, 0x0);
463 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_PHY_ENA_MSK
, 0x0);
464 hisi_sas_phy_write32(hisi_hba
, i
, SL_RX_BCAST_CHK_MSK
, 0x0);
465 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_OOB_RESTART_MSK
, 0x1);
466 hisi_sas_phy_write32(hisi_hba
, i
, STP_LINK_TIMER
, 0x7f7a120);
468 /* used for 12G negotiate */
469 hisi_sas_phy_write32(hisi_hba
, i
, COARSETUNE_TIME
, 0x1e);
472 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
474 hisi_sas_write32(hisi_hba
,
475 DLVRY_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
476 upper_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
478 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
479 lower_32_bits(hisi_hba
->cmd_hdr_dma
[i
]));
481 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_DEPTH
+ (i
* 0x14),
482 HISI_SAS_QUEUE_SLOTS
);
484 /* Completion queue */
485 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_HI
+ (i
* 0x14),
486 upper_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
488 hisi_sas_write32(hisi_hba
, COMPL_Q_0_BASE_ADDR_LO
+ (i
* 0x14),
489 lower_32_bits(hisi_hba
->complete_hdr_dma
[i
]));
491 hisi_sas_write32(hisi_hba
, COMPL_Q_0_DEPTH
+ (i
* 0x14),
492 HISI_SAS_QUEUE_SLOTS
);
496 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_LO
,
497 lower_32_bits(hisi_hba
->itct_dma
));
499 hisi_sas_write32(hisi_hba
, ITCT_BASE_ADDR_HI
,
500 upper_32_bits(hisi_hba
->itct_dma
));
503 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_LO
,
504 lower_32_bits(hisi_hba
->iost_dma
));
506 hisi_sas_write32(hisi_hba
, IOST_BASE_ADDR_HI
,
507 upper_32_bits(hisi_hba
->iost_dma
));
510 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_LO
,
511 lower_32_bits(hisi_hba
->breakpoint_dma
));
513 hisi_sas_write32(hisi_hba
, IO_BROKEN_MSG_ADDR_HI
,
514 upper_32_bits(hisi_hba
->breakpoint_dma
));
516 /* SATA broken msg */
517 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_LO
,
518 lower_32_bits(hisi_hba
->sata_breakpoint_dma
));
520 hisi_sas_write32(hisi_hba
, IO_SATA_BROKEN_MSG_ADDR_HI
,
521 upper_32_bits(hisi_hba
->sata_breakpoint_dma
));
523 /* SATA initial fis */
524 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_LO
,
525 lower_32_bits(hisi_hba
->initial_fis_dma
));
527 hisi_sas_write32(hisi_hba
, SATA_INITI_D2H_STORE_ADDR_HI
,
528 upper_32_bits(hisi_hba
->initial_fis_dma
));
530 /* RAS registers init */
531 hisi_sas_write32(hisi_hba
, SAS_RAS_INTR0_MASK
, 0x0);
532 hisi_sas_write32(hisi_hba
, SAS_RAS_INTR1_MASK
, 0x0);
533 hisi_sas_write32(hisi_hba
, SAS_RAS_INTR2_MASK
, 0x0);
534 hisi_sas_write32(hisi_hba
, CFG_SAS_RAS_INTR_MASK
, 0x0);
537 static void config_phy_opt_mode_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
539 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
541 cfg
&= ~PHY_CFG_DC_OPT_MSK
;
542 cfg
|= 1 << PHY_CFG_DC_OPT_OFF
;
543 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
546 static void config_id_frame_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
548 struct sas_identify_frame identify_frame
;
549 u32
*identify_buffer
;
551 memset(&identify_frame
, 0, sizeof(identify_frame
));
552 identify_frame
.dev_type
= SAS_END_DEVICE
;
553 identify_frame
.frame_type
= 0;
554 identify_frame
._un1
= 1;
555 identify_frame
.initiator_bits
= SAS_PROTOCOL_ALL
;
556 identify_frame
.target_bits
= SAS_PROTOCOL_NONE
;
557 memcpy(&identify_frame
._un4_11
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
558 memcpy(&identify_frame
.sas_addr
[0], hisi_hba
->sas_addr
, SAS_ADDR_SIZE
);
559 identify_frame
.phy_id
= phy_no
;
560 identify_buffer
= (u32
*)(&identify_frame
);
562 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD0
,
563 __swab32(identify_buffer
[0]));
564 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD1
,
565 __swab32(identify_buffer
[1]));
566 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD2
,
567 __swab32(identify_buffer
[2]));
568 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD3
,
569 __swab32(identify_buffer
[3]));
570 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD4
,
571 __swab32(identify_buffer
[4]));
572 hisi_sas_phy_write32(hisi_hba
, phy_no
, TX_ID_DWORD5
,
573 __swab32(identify_buffer
[5]));
576 static void setup_itct_v3_hw(struct hisi_hba
*hisi_hba
,
577 struct hisi_sas_device
*sas_dev
)
579 struct domain_device
*device
= sas_dev
->sas_device
;
580 struct device
*dev
= hisi_hba
->dev
;
581 u64 qw0
, device_id
= sas_dev
->device_id
;
582 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[device_id
];
583 struct domain_device
*parent_dev
= device
->parent
;
584 struct asd_sas_port
*sas_port
= device
->port
;
585 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
587 memset(itct
, 0, sizeof(*itct
));
591 switch (sas_dev
->dev_type
) {
593 case SAS_EDGE_EXPANDER_DEVICE
:
594 case SAS_FANOUT_EXPANDER_DEVICE
:
595 qw0
= HISI_SAS_DEV_TYPE_SSP
<< ITCT_HDR_DEV_TYPE_OFF
;
598 case SAS_SATA_PENDING
:
599 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
600 qw0
= HISI_SAS_DEV_TYPE_STP
<< ITCT_HDR_DEV_TYPE_OFF
;
602 qw0
= HISI_SAS_DEV_TYPE_SATA
<< ITCT_HDR_DEV_TYPE_OFF
;
605 dev_warn(dev
, "setup itct: unsupported dev type (%d)\n",
609 qw0
|= ((1 << ITCT_HDR_VALID_OFF
) |
610 (device
->linkrate
<< ITCT_HDR_MCR_OFF
) |
611 (1 << ITCT_HDR_VLN_OFF
) |
612 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF
) |
613 (1 << ITCT_HDR_AWT_CONTINUE_OFF
) |
614 (port
->id
<< ITCT_HDR_PORT_ID_OFF
));
615 itct
->qw0
= cpu_to_le64(qw0
);
618 memcpy(&itct
->sas_addr
, device
->sas_addr
, SAS_ADDR_SIZE
);
619 itct
->sas_addr
= __swab64(itct
->sas_addr
);
622 if (!dev_is_sata(device
))
623 itct
->qw2
= cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF
) |
624 (0x1ULL
<< ITCT_HDR_RTOLT_OFF
));
627 static void clear_itct_v3_hw(struct hisi_hba
*hisi_hba
,
628 struct hisi_sas_device
*sas_dev
)
630 DECLARE_COMPLETION_ONSTACK(completion
);
631 u64 dev_id
= sas_dev
->device_id
;
632 struct hisi_sas_itct
*itct
= &hisi_hba
->itct
[dev_id
];
633 u32 reg_val
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
635 sas_dev
->completion
= &completion
;
637 /* clear the itct interrupt state */
638 if (ENT_INT_SRC3_ITC_INT_MSK
& reg_val
)
639 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
,
640 ENT_INT_SRC3_ITC_INT_MSK
);
642 /* clear the itct table*/
643 reg_val
= ITCT_CLR_EN_MSK
| (dev_id
& ITCT_DEV_MSK
);
644 hisi_sas_write32(hisi_hba
, ITCT_CLR
, reg_val
);
646 wait_for_completion(sas_dev
->completion
);
647 memset(itct
, 0, sizeof(struct hisi_sas_itct
));
650 static void dereg_device_v3_hw(struct hisi_hba
*hisi_hba
,
651 struct domain_device
*device
)
653 struct hisi_sas_slot
*slot
, *slot2
;
654 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
655 u32 cfg_abt_set_query_iptt
;
657 cfg_abt_set_query_iptt
= hisi_sas_read32(hisi_hba
,
658 CFG_ABT_SET_QUERY_IPTT
);
659 list_for_each_entry_safe(slot
, slot2
, &sas_dev
->list
, entry
) {
660 cfg_abt_set_query_iptt
&= ~CFG_SET_ABORTED_IPTT_MSK
;
661 cfg_abt_set_query_iptt
|= (1 << CFG_SET_ABORTED_EN_OFF
) |
662 (slot
->idx
<< CFG_SET_ABORTED_IPTT_OFF
);
663 hisi_sas_write32(hisi_hba
, CFG_ABT_SET_QUERY_IPTT
,
664 cfg_abt_set_query_iptt
);
666 cfg_abt_set_query_iptt
&= ~(1 << CFG_SET_ABORTED_EN_OFF
);
667 hisi_sas_write32(hisi_hba
, CFG_ABT_SET_QUERY_IPTT
,
668 cfg_abt_set_query_iptt
);
669 hisi_sas_write32(hisi_hba
, CFG_ABT_SET_IPTT_DONE
,
670 1 << CFG_ABT_SET_IPTT_DONE_OFF
);
673 static int reset_hw_v3_hw(struct hisi_hba
*hisi_hba
)
675 struct device
*dev
= hisi_hba
->dev
;
679 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0);
681 /* Disable all of the PHYs */
682 hisi_sas_stop_phys(hisi_hba
);
685 /* Ensure axi bus idle */
686 ret
= readl_poll_timeout(hisi_hba
->regs
+ AXI_CFG
, val
, !val
,
689 dev_err(dev
, "axi bus is not idle, ret = %d!\n", ret
);
693 if (ACPI_HANDLE(dev
)) {
696 s
= acpi_evaluate_object(ACPI_HANDLE(dev
), "_RST", NULL
, NULL
);
697 if (ACPI_FAILURE(s
)) {
698 dev_err(dev
, "Reset failed\n");
702 dev_err(dev
, "no reset method!\n");
709 static int hw_init_v3_hw(struct hisi_hba
*hisi_hba
)
711 struct device
*dev
= hisi_hba
->dev
;
714 rc
= reset_hw_v3_hw(hisi_hba
);
716 dev_err(dev
, "hisi_sas_reset_hw failed, rc=%d", rc
);
721 init_reg_v3_hw(hisi_hba
);
726 static void enable_phy_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
728 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
730 cfg
|= PHY_CFG_ENA_MSK
;
731 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
734 static void disable_phy_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
736 u32 cfg
= hisi_sas_phy_read32(hisi_hba
, phy_no
, PHY_CFG
);
738 cfg
&= ~PHY_CFG_ENA_MSK
;
739 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHY_CFG
, cfg
);
742 static void start_phy_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
744 config_id_frame_v3_hw(hisi_hba
, phy_no
);
745 config_phy_opt_mode_v3_hw(hisi_hba
, phy_no
);
746 enable_phy_v3_hw(hisi_hba
, phy_no
);
749 static void phy_hard_reset_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
751 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
754 disable_phy_v3_hw(hisi_hba
, phy_no
);
755 if (phy
->identify
.device_type
== SAS_END_DEVICE
) {
756 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
757 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
758 txid_auto
| TX_HARDRST_MSK
);
761 start_phy_v3_hw(hisi_hba
, phy_no
);
764 static enum sas_linkrate
phy_get_max_linkrate_v3_hw(void)
766 return SAS_LINK_RATE_12_0_GBPS
;
769 static void phys_init_v3_hw(struct hisi_hba
*hisi_hba
)
773 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
774 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[i
];
775 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
777 if (!sas_phy
->phy
->enabled
)
780 start_phy_v3_hw(hisi_hba
, i
);
784 static void sl_notify_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
788 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
789 sl_control
|= SL_CONTROL_NOTIFY_EN_MSK
;
790 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
792 sl_control
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
793 sl_control
&= ~SL_CONTROL_NOTIFY_EN_MSK
;
794 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
, sl_control
);
797 static int get_wideport_bitmap_v3_hw(struct hisi_hba
*hisi_hba
, int port_id
)
800 u32 phy_port_num_ma
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
801 u32 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
803 for (i
= 0; i
< hisi_hba
->n_phy
; i
++)
804 if (phy_state
& BIT(i
))
805 if (((phy_port_num_ma
>> (i
* 4)) & 0xf) == port_id
)
812 * The callpath to this function and upto writing the write
813 * queue pointer should be safe from interruption.
816 get_free_slot_v3_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_dq
*dq
)
818 struct device
*dev
= hisi_hba
->dev
;
823 r
= hisi_sas_read32_relaxed(hisi_hba
,
824 DLVRY_Q_0_RD_PTR
+ (queue
* 0x14));
825 if (r
== (w
+1) % HISI_SAS_QUEUE_SLOTS
) {
826 dev_warn(dev
, "full queue=%d r=%d w=%d\n\n",
834 static void start_delivery_v3_hw(struct hisi_sas_dq
*dq
)
836 struct hisi_hba
*hisi_hba
= dq
->hisi_hba
;
837 int dlvry_queue
= dq
->slot_prep
->dlvry_queue
;
838 int dlvry_queue_slot
= dq
->slot_prep
->dlvry_queue_slot
;
840 dq
->wr_point
= ++dlvry_queue_slot
% HISI_SAS_QUEUE_SLOTS
;
841 hisi_sas_write32(hisi_hba
, DLVRY_Q_0_WR_PTR
+ (dlvry_queue
* 0x14),
845 static int prep_prd_sge_v3_hw(struct hisi_hba
*hisi_hba
,
846 struct hisi_sas_slot
*slot
,
847 struct hisi_sas_cmd_hdr
*hdr
,
848 struct scatterlist
*scatter
,
851 struct hisi_sas_sge_page
*sge_page
= hisi_sas_sge_addr_mem(slot
);
852 struct device
*dev
= hisi_hba
->dev
;
853 struct scatterlist
*sg
;
856 if (n_elem
> HISI_SAS_SGE_PAGE_CNT
) {
857 dev_err(dev
, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
862 for_each_sg(scatter
, sg
, n_elem
, i
) {
863 struct hisi_sas_sge
*entry
= &sge_page
->sge
[i
];
865 entry
->addr
= cpu_to_le64(sg_dma_address(sg
));
866 entry
->page_ctrl_0
= entry
->page_ctrl_1
= 0;
867 entry
->data_len
= cpu_to_le32(sg_dma_len(sg
));
871 hdr
->prd_table_addr
= cpu_to_le64(hisi_sas_sge_addr_dma(slot
));
873 hdr
->sg_len
= cpu_to_le32(n_elem
<< CMD_HDR_DATA_SGL_LEN_OFF
);
878 static int prep_ssp_v3_hw(struct hisi_hba
*hisi_hba
,
879 struct hisi_sas_slot
*slot
, int is_tmf
,
880 struct hisi_sas_tmf_task
*tmf
)
882 struct sas_task
*task
= slot
->task
;
883 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
884 struct domain_device
*device
= task
->dev
;
885 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
886 struct hisi_sas_port
*port
= slot
->port
;
887 struct sas_ssp_task
*ssp_task
= &task
->ssp_task
;
888 struct scsi_cmnd
*scsi_cmnd
= ssp_task
->cmd
;
889 int has_data
= 0, rc
, priority
= is_tmf
;
891 u32 dw1
= 0, dw2
= 0;
893 hdr
->dw0
= cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF
) |
894 (2 << CMD_HDR_TLR_CTRL_OFF
) |
895 (port
->id
<< CMD_HDR_PORT_OFF
) |
896 (priority
<< CMD_HDR_PRIORITY_OFF
) |
897 (1 << CMD_HDR_CMD_OFF
)); /* ssp */
899 dw1
= 1 << CMD_HDR_VDTL_OFF
;
901 dw1
|= 2 << CMD_HDR_FRAME_TYPE_OFF
;
902 dw1
|= DIR_NO_DATA
<< CMD_HDR_DIR_OFF
;
904 dw1
|= 1 << CMD_HDR_FRAME_TYPE_OFF
;
905 switch (scsi_cmnd
->sc_data_direction
) {
908 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
910 case DMA_FROM_DEVICE
:
912 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
915 dw1
&= ~CMD_HDR_DIR_MSK
;
920 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
921 hdr
->dw1
= cpu_to_le32(dw1
);
923 dw2
= (((sizeof(struct ssp_command_iu
) + sizeof(struct ssp_frame_hdr
)
924 + 3) / 4) << CMD_HDR_CFL_OFF
) |
925 ((HISI_SAS_MAX_SSP_RESP_SZ
/ 4) << CMD_HDR_MRFL_OFF
) |
926 (2 << CMD_HDR_SG_MOD_OFF
);
927 hdr
->dw2
= cpu_to_le32(dw2
);
928 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
931 rc
= prep_prd_sge_v3_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
937 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
938 hdr
->cmd_table_addr
= cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot
));
939 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
941 buf_cmd
= hisi_sas_cmd_hdr_addr_mem(slot
) +
942 sizeof(struct ssp_frame_hdr
);
944 memcpy(buf_cmd
, &task
->ssp_task
.LUN
, 8);
946 buf_cmd
[9] = ssp_task
->task_attr
| (ssp_task
->task_prio
<< 3);
947 memcpy(buf_cmd
+ 12, scsi_cmnd
->cmnd
, scsi_cmnd
->cmd_len
);
949 buf_cmd
[10] = tmf
->tmf
;
954 (tmf
->tag_of_task_to_be_managed
>> 8) & 0xff;
956 tmf
->tag_of_task_to_be_managed
& 0xff;
966 static int prep_smp_v3_hw(struct hisi_hba
*hisi_hba
,
967 struct hisi_sas_slot
*slot
)
969 struct sas_task
*task
= slot
->task
;
970 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
971 struct domain_device
*device
= task
->dev
;
972 struct device
*dev
= hisi_hba
->dev
;
973 struct hisi_sas_port
*port
= slot
->port
;
974 struct scatterlist
*sg_req
, *sg_resp
;
975 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
976 dma_addr_t req_dma_addr
;
977 unsigned int req_len
, resp_len
;
981 * DMA-map SMP request, response buffers
984 sg_req
= &task
->smp_task
.smp_req
;
985 elem
= dma_map_sg(dev
, sg_req
, 1, DMA_TO_DEVICE
);
988 req_len
= sg_dma_len(sg_req
);
989 req_dma_addr
= sg_dma_address(sg_req
);
992 sg_resp
= &task
->smp_task
.smp_resp
;
993 elem
= dma_map_sg(dev
, sg_resp
, 1, DMA_FROM_DEVICE
);
998 resp_len
= sg_dma_len(sg_resp
);
999 if ((req_len
& 0x3) || (resp_len
& 0x3)) {
1006 hdr
->dw0
= cpu_to_le32((port
->id
<< CMD_HDR_PORT_OFF
) |
1007 (1 << CMD_HDR_PRIORITY_OFF
) | /* high pri */
1008 (2 << CMD_HDR_CMD_OFF
)); /* smp */
1010 /* map itct entry */
1011 hdr
->dw1
= cpu_to_le32((sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
) |
1012 (1 << CMD_HDR_FRAME_TYPE_OFF
) |
1013 (DIR_NO_DATA
<< CMD_HDR_DIR_OFF
));
1016 hdr
->dw2
= cpu_to_le32((((req_len
- 4) / 4) << CMD_HDR_CFL_OFF
) |
1017 (HISI_SAS_MAX_SMP_RESP_SZ
/ 4 <<
1020 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
<< CMD_HDR_IPTT_OFF
);
1022 hdr
->cmd_table_addr
= cpu_to_le64(req_dma_addr
);
1023 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
1028 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_resp
, 1,
1031 dma_unmap_sg(dev
, &slot
->task
->smp_task
.smp_req
, 1,
1036 static int prep_ata_v3_hw(struct hisi_hba
*hisi_hba
,
1037 struct hisi_sas_slot
*slot
)
1039 struct sas_task
*task
= slot
->task
;
1040 struct domain_device
*device
= task
->dev
;
1041 struct domain_device
*parent_dev
= device
->parent
;
1042 struct hisi_sas_device
*sas_dev
= device
->lldd_dev
;
1043 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1044 struct asd_sas_port
*sas_port
= device
->port
;
1045 struct hisi_sas_port
*port
= to_hisi_sas_port(sas_port
);
1047 int has_data
= 0, rc
= 0, hdr_tag
= 0;
1048 u32 dw1
= 0, dw2
= 0;
1050 hdr
->dw0
= cpu_to_le32(port
->id
<< CMD_HDR_PORT_OFF
);
1051 if (parent_dev
&& DEV_IS_EXPANDER(parent_dev
->dev_type
))
1052 hdr
->dw0
|= cpu_to_le32(3 << CMD_HDR_CMD_OFF
);
1054 hdr
->dw0
|= cpu_to_le32(4 << CMD_HDR_CMD_OFF
);
1056 switch (task
->data_dir
) {
1059 dw1
|= DIR_TO_DEVICE
<< CMD_HDR_DIR_OFF
;
1061 case DMA_FROM_DEVICE
:
1063 dw1
|= DIR_TO_INI
<< CMD_HDR_DIR_OFF
;
1066 dw1
&= ~CMD_HDR_DIR_MSK
;
1069 if ((task
->ata_task
.fis
.command
== ATA_CMD_DEV_RESET
) &&
1070 (task
->ata_task
.fis
.control
& ATA_SRST
))
1071 dw1
|= 1 << CMD_HDR_RESET_OFF
;
1073 dw1
|= (hisi_sas_get_ata_protocol(
1074 &task
->ata_task
.fis
, task
->data_dir
))
1075 << CMD_HDR_FRAME_TYPE_OFF
;
1076 dw1
|= sas_dev
->device_id
<< CMD_HDR_DEV_ID_OFF
;
1078 if (CMD_IS_UNCONSTRAINT(task
->ata_task
.fis
.command
))
1079 dw1
|= 1 << CMD_HDR_UNCON_CMD_OFF
;
1081 hdr
->dw1
= cpu_to_le32(dw1
);
1084 if (task
->ata_task
.use_ncq
&& hisi_sas_get_ncq_tag(task
, &hdr_tag
)) {
1085 task
->ata_task
.fis
.sector_count
|= (u8
) (hdr_tag
<< 3);
1086 dw2
|= hdr_tag
<< CMD_HDR_NCQ_TAG_OFF
;
1089 dw2
|= (HISI_SAS_MAX_STP_RESP_SZ
/ 4) << CMD_HDR_CFL_OFF
|
1090 2 << CMD_HDR_SG_MOD_OFF
;
1091 hdr
->dw2
= cpu_to_le32(dw2
);
1094 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
1097 rc
= prep_prd_sge_v3_hw(hisi_hba
, slot
, hdr
, task
->scatter
,
1103 hdr
->data_transfer_len
= cpu_to_le32(task
->total_xfer_len
);
1104 hdr
->cmd_table_addr
= cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot
));
1105 hdr
->sts_buffer_addr
= cpu_to_le64(hisi_sas_status_buf_addr_dma(slot
));
1107 buf_cmd
= hisi_sas_cmd_hdr_addr_mem(slot
);
1109 if (likely(!task
->ata_task
.device_control_reg_update
))
1110 task
->ata_task
.fis
.flags
|= 0x80; /* C=1: update ATA cmd reg */
1111 /* fill in command FIS */
1112 memcpy(buf_cmd
, &task
->ata_task
.fis
, sizeof(struct host_to_dev_fis
));
1117 static int prep_abort_v3_hw(struct hisi_hba
*hisi_hba
,
1118 struct hisi_sas_slot
*slot
,
1119 int device_id
, int abort_flag
, int tag_to_abort
)
1121 struct sas_task
*task
= slot
->task
;
1122 struct domain_device
*dev
= task
->dev
;
1123 struct hisi_sas_cmd_hdr
*hdr
= slot
->cmd_hdr
;
1124 struct hisi_sas_port
*port
= slot
->port
;
1127 hdr
->dw0
= cpu_to_le32((5 << CMD_HDR_CMD_OFF
) | /*abort*/
1128 (port
->id
<< CMD_HDR_PORT_OFF
) |
1130 << CMD_HDR_ABORT_DEVICE_TYPE_OFF
) |
1132 << CMD_HDR_ABORT_FLAG_OFF
));
1135 hdr
->dw1
= cpu_to_le32(device_id
1136 << CMD_HDR_DEV_ID_OFF
);
1139 hdr
->dw7
= cpu_to_le32(tag_to_abort
<< CMD_HDR_ABORT_IPTT_OFF
);
1140 hdr
->transfer_tags
= cpu_to_le32(slot
->idx
);
1145 static irqreturn_t
phy_up_v3_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
1148 u32 context
, port_id
, link_rate
;
1149 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1150 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1151 struct device
*dev
= hisi_hba
->dev
;
1153 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 1);
1155 port_id
= hisi_sas_read32(hisi_hba
, PHY_PORT_NUM_MA
);
1156 port_id
= (port_id
>> (4 * phy_no
)) & 0xf;
1157 link_rate
= hisi_sas_read32(hisi_hba
, PHY_CONN_RATE
);
1158 link_rate
= (link_rate
>> (phy_no
* 4)) & 0xf;
1160 if (port_id
== 0xf) {
1161 dev_err(dev
, "phyup: phy%d invalid portid\n", phy_no
);
1165 sas_phy
->linkrate
= link_rate
;
1166 phy
->phy_type
&= ~(PORT_TYPE_SAS
| PORT_TYPE_SATA
);
1168 /* Check for SATA dev */
1169 context
= hisi_sas_read32(hisi_hba
, PHY_CONTEXT
);
1170 if (context
& (1 << phy_no
)) {
1171 struct hisi_sas_initial_fis
*initial_fis
;
1172 struct dev_to_host_fis
*fis
;
1173 u8 attached_sas_addr
[SAS_ADDR_SIZE
] = {0};
1175 dev_info(dev
, "phyup: phy%d link_rate=%d(sata)\n", phy_no
, link_rate
);
1176 initial_fis
= &hisi_hba
->initial_fis
[phy_no
];
1177 fis
= &initial_fis
->fis
;
1178 sas_phy
->oob_mode
= SATA_OOB_MODE
;
1179 attached_sas_addr
[0] = 0x50;
1180 attached_sas_addr
[7] = phy_no
;
1181 memcpy(sas_phy
->attached_sas_addr
,
1184 memcpy(sas_phy
->frame_rcvd
, fis
,
1185 sizeof(struct dev_to_host_fis
));
1186 phy
->phy_type
|= PORT_TYPE_SATA
;
1187 phy
->identify
.device_type
= SAS_SATA_DEV
;
1188 phy
->frame_rcvd_size
= sizeof(struct dev_to_host_fis
);
1189 phy
->identify
.target_port_protocols
= SAS_PROTOCOL_SATA
;
1191 u32
*frame_rcvd
= (u32
*)sas_phy
->frame_rcvd
;
1192 struct sas_identify_frame
*id
=
1193 (struct sas_identify_frame
*)frame_rcvd
;
1195 dev_info(dev
, "phyup: phy%d link_rate=%d\n", phy_no
, link_rate
);
1196 for (i
= 0; i
< 6; i
++) {
1197 u32 idaf
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1198 RX_IDAF_DWORD0
+ (i
* 4));
1199 frame_rcvd
[i
] = __swab32(idaf
);
1201 sas_phy
->oob_mode
= SAS_OOB_MODE
;
1202 memcpy(sas_phy
->attached_sas_addr
,
1205 phy
->phy_type
|= PORT_TYPE_SAS
;
1206 phy
->identify
.device_type
= id
->dev_type
;
1207 phy
->frame_rcvd_size
= sizeof(struct sas_identify_frame
);
1208 if (phy
->identify
.device_type
== SAS_END_DEVICE
)
1209 phy
->identify
.target_port_protocols
=
1211 else if (phy
->identify
.device_type
!= SAS_PHY_UNUSED
)
1212 phy
->identify
.target_port_protocols
=
1216 phy
->port_id
= port_id
;
1217 phy
->phy_attached
= 1;
1218 hisi_sas_notify_phy_event(phy
, HISI_PHYE_PHY_UP
);
1221 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
1222 CHL_INT0_SL_PHY_ENABLE_MSK
);
1223 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_PHY_ENA_MSK
, 0);
1228 static irqreturn_t
phy_down_v3_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
1230 u32 phy_state
, sl_ctrl
, txid_auto
;
1231 struct device
*dev
= hisi_hba
->dev
;
1233 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 1);
1235 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1236 dev_info(dev
, "phydown: phy%d phy_state=0x%x\n", phy_no
, phy_state
);
1237 hisi_sas_phy_down(hisi_hba
, phy_no
, (phy_state
& 1 << phy_no
) ? 1 : 0);
1239 sl_ctrl
= hisi_sas_phy_read32(hisi_hba
, phy_no
, SL_CONTROL
);
1240 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_CONTROL
,
1241 sl_ctrl
&(~SL_CTA_MSK
));
1243 txid_auto
= hisi_sas_phy_read32(hisi_hba
, phy_no
, TXID_AUTO
);
1244 hisi_sas_phy_write32(hisi_hba
, phy_no
, TXID_AUTO
,
1245 txid_auto
| CT3_MSK
);
1247 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
, CHL_INT0_NOT_RDY_MSK
);
1248 hisi_sas_phy_write32(hisi_hba
, phy_no
, PHYCTRL_NOT_RDY_MSK
, 0);
1253 static irqreturn_t
phy_bcast_v3_hw(int phy_no
, struct hisi_hba
*hisi_hba
)
1255 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1256 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1257 struct sas_ha_struct
*sas_ha
= &hisi_hba
->sha
;
1259 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 1);
1260 sas_ha
->notify_port_event(sas_phy
, PORTE_BROADCAST_RCVD
);
1261 hisi_sas_phy_write32(hisi_hba
, phy_no
, CHL_INT0
,
1262 CHL_INT0_SL_RX_BCST_ACK_MSK
);
1263 hisi_sas_phy_write32(hisi_hba
, phy_no
, SL_RX_BCAST_CHK_MSK
, 0);
1268 static irqreturn_t
int_phy_up_down_bcast_v3_hw(int irq_no
, void *p
)
1270 struct hisi_hba
*hisi_hba
= p
;
1273 irqreturn_t res
= IRQ_NONE
;
1275 irq_msk
= hisi_sas_read32(hisi_hba
, CHNL_INT_STATUS
)
1279 u32 irq_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1281 u32 phy_state
= hisi_sas_read32(hisi_hba
, PHY_STATE
);
1282 int rdy
= phy_state
& (1 << phy_no
);
1285 if (irq_value
& CHL_INT0_SL_PHY_ENABLE_MSK
)
1287 if (phy_up_v3_hw(phy_no
, hisi_hba
)
1290 if (irq_value
& CHL_INT0_SL_RX_BCST_ACK_MSK
)
1292 if (phy_bcast_v3_hw(phy_no
, hisi_hba
)
1296 if (irq_value
& CHL_INT0_NOT_RDY_MSK
)
1298 if (phy_down_v3_hw(phy_no
, hisi_hba
)
1310 static const struct hisi_sas_hw_error port_axi_error
[] = {
1312 .irq_msk
= BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF
),
1313 .msg
= "dma_tx_axi_wr_err",
1316 .irq_msk
= BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF
),
1317 .msg
= "dma_tx_axi_rd_err",
1320 .irq_msk
= BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF
),
1321 .msg
= "dma_rx_axi_wr_err",
1324 .irq_msk
= BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF
),
1325 .msg
= "dma_rx_axi_rd_err",
1329 static irqreturn_t
int_chnl_int_v3_hw(int irq_no
, void *p
)
1331 struct hisi_hba
*hisi_hba
= p
;
1332 struct device
*dev
= hisi_hba
->dev
;
1333 u32 ent_msk
, ent_tmp
, irq_msk
;
1336 ent_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
1338 ent_msk
|= ENT_INT_SRC_MSK3_ENT95_MSK_MSK
;
1339 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_msk
);
1341 irq_msk
= hisi_sas_read32(hisi_hba
, CHNL_INT_STATUS
)
1345 u32 irq_value0
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1347 u32 irq_value1
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1349 u32 irq_value2
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1351 u32 irq_msk1
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1353 u32 irq_msk2
= hisi_sas_phy_read32(hisi_hba
, phy_no
,
1356 irq_value1
&= ~irq_msk1
;
1357 irq_value2
&= ~irq_msk2
;
1359 if ((irq_msk
& (4 << (phy_no
* 4))) &&
1363 for (i
= 0; i
< ARRAY_SIZE(port_axi_error
); i
++) {
1364 const struct hisi_sas_hw_error
*error
=
1367 if (!(irq_value1
& error
->irq_msk
))
1370 dev_err(dev
, "%s error (phy%d 0x%x) found!\n",
1371 error
->msg
, phy_no
, irq_value1
);
1372 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
1375 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1376 CHL_INT1
, irq_value1
);
1379 if (irq_msk
& (8 << (phy_no
* 4)) && irq_value2
) {
1380 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1382 if (irq_value2
& BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF
)) {
1383 dev_warn(dev
, "phy%d identify timeout\n",
1385 hisi_sas_notify_phy_event(phy
,
1386 HISI_PHYE_LINK_RESET
);
1390 if (irq_value2
& BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF
)) {
1391 u32 reg_value
= hisi_sas_phy_read32(hisi_hba
,
1392 phy_no
, STP_LINK_TIMEOUT_STATE
);
1394 dev_warn(dev
, "phy%d stp link timeout (0x%x)\n",
1396 if (reg_value
& BIT(4))
1397 hisi_sas_notify_phy_event(phy
,
1398 HISI_PHYE_LINK_RESET
);
1401 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1402 CHL_INT2
, irq_value2
);
1406 if (irq_msk
& (2 << (phy_no
* 4)) && irq_value0
) {
1407 hisi_sas_phy_write32(hisi_hba
, phy_no
,
1408 CHL_INT0
, irq_value0
1409 & (~CHL_INT0_SL_RX_BCST_ACK_MSK
)
1410 & (~CHL_INT0_SL_PHY_ENABLE_MSK
)
1411 & (~CHL_INT0_NOT_RDY_MSK
));
1413 irq_msk
&= ~(0xe << (phy_no
* 4));
1417 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, ent_tmp
);
1422 static const struct hisi_sas_hw_error axi_error
[] = {
1423 { .msk
= BIT(0), .msg
= "IOST_AXI_W_ERR" },
1424 { .msk
= BIT(1), .msg
= "IOST_AXI_R_ERR" },
1425 { .msk
= BIT(2), .msg
= "ITCT_AXI_W_ERR" },
1426 { .msk
= BIT(3), .msg
= "ITCT_AXI_R_ERR" },
1427 { .msk
= BIT(4), .msg
= "SATA_AXI_W_ERR" },
1428 { .msk
= BIT(5), .msg
= "SATA_AXI_R_ERR" },
1429 { .msk
= BIT(6), .msg
= "DQE_AXI_R_ERR" },
1430 { .msk
= BIT(7), .msg
= "CQE_AXI_W_ERR" },
1434 static const struct hisi_sas_hw_error fifo_error
[] = {
1435 { .msk
= BIT(8), .msg
= "CQE_WINFO_FIFO" },
1436 { .msk
= BIT(9), .msg
= "CQE_MSG_FIFIO" },
1437 { .msk
= BIT(10), .msg
= "GETDQE_FIFO" },
1438 { .msk
= BIT(11), .msg
= "CMDP_FIFO" },
1439 { .msk
= BIT(12), .msg
= "AWTCTRL_FIFO" },
1443 static const struct hisi_sas_hw_error fatal_axi_error
[] = {
1445 .irq_msk
= BIT(ENT_INT_SRC3_WP_DEPTH_OFF
),
1446 .msg
= "write pointer and depth",
1449 .irq_msk
= BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF
),
1450 .msg
= "iptt no match slot",
1453 .irq_msk
= BIT(ENT_INT_SRC3_RP_DEPTH_OFF
),
1454 .msg
= "read pointer and depth",
1457 .irq_msk
= BIT(ENT_INT_SRC3_AXI_OFF
),
1458 .reg
= HGC_AXI_FIFO_ERR_INFO
,
1462 .irq_msk
= BIT(ENT_INT_SRC3_FIFO_OFF
),
1463 .reg
= HGC_AXI_FIFO_ERR_INFO
,
1467 .irq_msk
= BIT(ENT_INT_SRC3_LM_OFF
),
1468 .msg
= "LM add/fetch list",
1471 .irq_msk
= BIT(ENT_INT_SRC3_ABT_OFF
),
1472 .msg
= "SAS_HGC_ABT fetch LM list",
1476 static irqreturn_t
fatal_axi_int_v3_hw(int irq_no
, void *p
)
1478 u32 irq_value
, irq_msk
;
1479 struct hisi_hba
*hisi_hba
= p
;
1480 struct device
*dev
= hisi_hba
->dev
;
1483 irq_msk
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC_MSK3
);
1484 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, irq_msk
| 0x1df00);
1486 irq_value
= hisi_sas_read32(hisi_hba
, ENT_INT_SRC3
);
1487 irq_value
&= ~irq_msk
;
1489 for (i
= 0; i
< ARRAY_SIZE(fatal_axi_error
); i
++) {
1490 const struct hisi_sas_hw_error
*error
= &fatal_axi_error
[i
];
1492 if (!(irq_value
& error
->irq_msk
))
1496 const struct hisi_sas_hw_error
*sub
= error
->sub
;
1497 u32 err_value
= hisi_sas_read32(hisi_hba
, error
->reg
);
1499 for (; sub
->msk
|| sub
->msg
; sub
++) {
1500 if (!(err_value
& sub
->msk
))
1503 dev_err(dev
, "%s error (0x%x) found!\n",
1504 sub
->msg
, irq_value
);
1505 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
1508 dev_err(dev
, "%s error (0x%x) found!\n",
1509 error
->msg
, irq_value
);
1510 queue_work(hisi_hba
->wq
, &hisi_hba
->rst_work
);
1514 if (irq_value
& BIT(ENT_INT_SRC3_ITC_INT_OFF
)) {
1515 u32 reg_val
= hisi_sas_read32(hisi_hba
, ITCT_CLR
);
1516 u32 dev_id
= reg_val
& ITCT_DEV_MSK
;
1517 struct hisi_sas_device
*sas_dev
=
1518 &hisi_hba
->devices
[dev_id
];
1520 hisi_sas_write32(hisi_hba
, ITCT_CLR
, 0);
1521 dev_dbg(dev
, "clear ITCT ok\n");
1522 complete(sas_dev
->completion
);
1525 hisi_sas_write32(hisi_hba
, ENT_INT_SRC3
, irq_value
& 0x1df00);
1526 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, irq_msk
);
1532 slot_err_v3_hw(struct hisi_hba
*hisi_hba
, struct sas_task
*task
,
1533 struct hisi_sas_slot
*slot
)
1535 struct task_status_struct
*ts
= &task
->task_status
;
1536 struct hisi_sas_complete_v3_hdr
*complete_queue
=
1537 hisi_hba
->complete_hdr
[slot
->cmplt_queue
];
1538 struct hisi_sas_complete_v3_hdr
*complete_hdr
=
1539 &complete_queue
[slot
->cmplt_queue_slot
];
1540 struct hisi_sas_err_record_v3
*record
=
1541 hisi_sas_status_buf_addr_mem(slot
);
1542 u32 dma_rx_err_type
= record
->dma_rx_err_type
;
1543 u32 trans_tx_fail_type
= record
->trans_tx_fail_type
;
1545 switch (task
->task_proto
) {
1546 case SAS_PROTOCOL_SSP
:
1547 if (dma_rx_err_type
& RX_DATA_LEN_UNDERFLOW_MSK
) {
1548 ts
->residual
= trans_tx_fail_type
;
1549 ts
->stat
= SAS_DATA_UNDERRUN
;
1550 } else if (complete_hdr
->dw3
& CMPLT_HDR_IO_IN_TARGET_MSK
) {
1551 ts
->stat
= SAS_QUEUE_FULL
;
1554 ts
->stat
= SAS_OPEN_REJECT
;
1555 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
1558 case SAS_PROTOCOL_SATA
:
1559 case SAS_PROTOCOL_STP
:
1560 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
1561 if (dma_rx_err_type
& RX_DATA_LEN_UNDERFLOW_MSK
) {
1562 ts
->residual
= trans_tx_fail_type
;
1563 ts
->stat
= SAS_DATA_UNDERRUN
;
1564 } else if (complete_hdr
->dw3
& CMPLT_HDR_IO_IN_TARGET_MSK
) {
1565 ts
->stat
= SAS_PHY_DOWN
;
1568 ts
->stat
= SAS_OPEN_REJECT
;
1569 ts
->open_rej_reason
= SAS_OREJ_RSVD_RETRY
;
1571 hisi_sas_sata_done(task
, slot
);
1573 case SAS_PROTOCOL_SMP
:
1574 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
1582 slot_complete_v3_hw(struct hisi_hba
*hisi_hba
, struct hisi_sas_slot
*slot
)
1584 struct sas_task
*task
= slot
->task
;
1585 struct hisi_sas_device
*sas_dev
;
1586 struct device
*dev
= hisi_hba
->dev
;
1587 struct task_status_struct
*ts
;
1588 struct domain_device
*device
;
1589 struct sas_ha_struct
*ha
;
1590 enum exec_status sts
;
1591 struct hisi_sas_complete_v3_hdr
*complete_queue
=
1592 hisi_hba
->complete_hdr
[slot
->cmplt_queue
];
1593 struct hisi_sas_complete_v3_hdr
*complete_hdr
=
1594 &complete_queue
[slot
->cmplt_queue_slot
];
1595 unsigned long flags
;
1596 bool is_internal
= slot
->is_internal
;
1598 if (unlikely(!task
|| !task
->lldd_task
|| !task
->dev
))
1601 ts
= &task
->task_status
;
1603 ha
= device
->port
->ha
;
1604 sas_dev
= device
->lldd_dev
;
1606 spin_lock_irqsave(&task
->task_state_lock
, flags
);
1607 task
->task_state_flags
&=
1608 ~(SAS_TASK_STATE_PENDING
| SAS_TASK_AT_INITIATOR
);
1609 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
1611 memset(ts
, 0, sizeof(*ts
));
1612 ts
->resp
= SAS_TASK_COMPLETE
;
1614 if (unlikely(!sas_dev
)) {
1615 dev_dbg(dev
, "slot complete: port has not device\n");
1616 ts
->stat
= SAS_PHY_DOWN
;
1621 * Use SAS+TMF status codes
1623 switch ((complete_hdr
->dw0
& CMPLT_HDR_ABORT_STAT_MSK
)
1624 >> CMPLT_HDR_ABORT_STAT_OFF
) {
1625 case STAT_IO_ABORTED
:
1626 /* this IO has been aborted by abort command */
1627 ts
->stat
= SAS_ABORTED_TASK
;
1629 case STAT_IO_COMPLETE
:
1630 /* internal abort command complete */
1631 ts
->stat
= TMF_RESP_FUNC_SUCC
;
1633 case STAT_IO_NO_DEVICE
:
1634 ts
->stat
= TMF_RESP_FUNC_COMPLETE
;
1636 case STAT_IO_NOT_VALID
:
1638 * abort single IO, the controller can't find the IO
1640 ts
->stat
= TMF_RESP_FUNC_FAILED
;
1646 /* check for erroneous completion */
1647 if ((complete_hdr
->dw0
& CMPLT_HDR_CMPLT_MSK
) == 0x3) {
1648 u32
*error_info
= hisi_sas_status_buf_addr_mem(slot
);
1650 slot_err_v3_hw(hisi_hba
, task
, slot
);
1651 if (ts
->stat
!= SAS_DATA_UNDERRUN
)
1652 dev_info(dev
, "erroneous completion iptt=%d task=%p dev id=%d "
1653 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
1654 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
1655 slot
->idx
, task
, sas_dev
->device_id
,
1656 complete_hdr
->dw0
, complete_hdr
->dw1
,
1657 complete_hdr
->act
, complete_hdr
->dw3
,
1658 error_info
[0], error_info
[1],
1659 error_info
[2], error_info
[3]);
1660 if (unlikely(slot
->abort
))
1665 switch (task
->task_proto
) {
1666 case SAS_PROTOCOL_SSP
: {
1667 struct ssp_response_iu
*iu
=
1668 hisi_sas_status_buf_addr_mem(slot
) +
1669 sizeof(struct hisi_sas_err_record
);
1671 sas_ssp_task_response(dev
, task
, iu
);
1674 case SAS_PROTOCOL_SMP
: {
1675 struct scatterlist
*sg_resp
= &task
->smp_task
.smp_resp
;
1678 ts
->stat
= SAM_STAT_GOOD
;
1679 to
= kmap_atomic(sg_page(sg_resp
));
1681 dma_unmap_sg(dev
, &task
->smp_task
.smp_resp
, 1,
1683 dma_unmap_sg(dev
, &task
->smp_task
.smp_req
, 1,
1685 memcpy(to
+ sg_resp
->offset
,
1686 hisi_sas_status_buf_addr_mem(slot
) +
1687 sizeof(struct hisi_sas_err_record
),
1688 sg_dma_len(sg_resp
));
1692 case SAS_PROTOCOL_SATA
:
1693 case SAS_PROTOCOL_STP
:
1694 case SAS_PROTOCOL_SATA
| SAS_PROTOCOL_STP
:
1695 ts
->stat
= SAM_STAT_GOOD
;
1696 hisi_sas_sata_done(task
, slot
);
1699 ts
->stat
= SAM_STAT_CHECK_CONDITION
;
1703 if (!slot
->port
->port_attached
) {
1704 dev_warn(dev
, "slot complete: port %d has removed\n",
1705 slot
->port
->sas_port
.id
);
1706 ts
->stat
= SAS_PHY_DOWN
;
1710 hisi_sas_slot_task_free(hisi_hba
, task
, slot
);
1712 spin_lock_irqsave(&task
->task_state_lock
, flags
);
1713 if (task
->task_state_flags
& SAS_TASK_STATE_ABORTED
) {
1714 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
1715 dev_info(dev
, "slot complete: task(%p) aborted\n", task
);
1716 return SAS_ABORTED_TASK
;
1718 task
->task_state_flags
|= SAS_TASK_STATE_DONE
;
1719 spin_unlock_irqrestore(&task
->task_state_lock
, flags
);
1721 if (!is_internal
&& (task
->task_proto
!= SAS_PROTOCOL_SMP
)) {
1722 spin_lock_irqsave(&device
->done_lock
, flags
);
1723 if (test_bit(SAS_HA_FROZEN
, &ha
->state
)) {
1724 spin_unlock_irqrestore(&device
->done_lock
, flags
);
1725 dev_info(dev
, "slot complete: task(%p) ignored\n ",
1729 spin_unlock_irqrestore(&device
->done_lock
, flags
);
1732 if (task
->task_done
)
1733 task
->task_done(task
);
1738 static void cq_tasklet_v3_hw(unsigned long val
)
1740 struct hisi_sas_cq
*cq
= (struct hisi_sas_cq
*)val
;
1741 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
1742 struct hisi_sas_slot
*slot
;
1743 struct hisi_sas_complete_v3_hdr
*complete_queue
;
1744 u32 rd_point
= cq
->rd_point
, wr_point
;
1747 complete_queue
= hisi_hba
->complete_hdr
[queue
];
1749 wr_point
= hisi_sas_read32(hisi_hba
, COMPL_Q_0_WR_PTR
+
1752 while (rd_point
!= wr_point
) {
1753 struct hisi_sas_complete_v3_hdr
*complete_hdr
;
1754 struct device
*dev
= hisi_hba
->dev
;
1757 complete_hdr
= &complete_queue
[rd_point
];
1759 iptt
= (complete_hdr
->dw1
) & CMPLT_HDR_IPTT_MSK
;
1760 if (likely(iptt
< HISI_SAS_COMMAND_ENTRIES_V3_HW
)) {
1761 slot
= &hisi_hba
->slot_info
[iptt
];
1762 slot
->cmplt_queue_slot
= rd_point
;
1763 slot
->cmplt_queue
= queue
;
1764 slot_complete_v3_hw(hisi_hba
, slot
);
1766 dev_err(dev
, "IPTT %d is invalid, discard it.\n", iptt
);
1768 if (++rd_point
>= HISI_SAS_QUEUE_SLOTS
)
1772 /* update rd_point */
1773 cq
->rd_point
= rd_point
;
1774 hisi_sas_write32(hisi_hba
, COMPL_Q_0_RD_PTR
+ (0x14 * queue
), rd_point
);
1777 static irqreturn_t
cq_interrupt_v3_hw(int irq_no
, void *p
)
1779 struct hisi_sas_cq
*cq
= p
;
1780 struct hisi_hba
*hisi_hba
= cq
->hisi_hba
;
1783 hisi_sas_write32(hisi_hba
, OQ_INT_SRC
, 1 << queue
);
1785 tasklet_schedule(&cq
->tasklet
);
1790 static int interrupt_init_v3_hw(struct hisi_hba
*hisi_hba
)
1792 struct device
*dev
= hisi_hba
->dev
;
1793 struct pci_dev
*pdev
= hisi_hba
->pci_dev
;
1796 int max_msi
= HISI_SAS_MSI_COUNT_V3_HW
;
1798 vectors
= pci_alloc_irq_vectors(hisi_hba
->pci_dev
, 1,
1799 max_msi
, PCI_IRQ_MSI
);
1800 if (vectors
< max_msi
) {
1801 dev_err(dev
, "could not allocate all msi (%d)\n", vectors
);
1805 rc
= devm_request_irq(dev
, pci_irq_vector(pdev
, 1),
1806 int_phy_up_down_bcast_v3_hw
, 0,
1807 DRV_NAME
" phy", hisi_hba
);
1809 dev_err(dev
, "could not request phy interrupt, rc=%d\n", rc
);
1811 goto free_irq_vectors
;
1814 rc
= devm_request_irq(dev
, pci_irq_vector(pdev
, 2),
1815 int_chnl_int_v3_hw
, 0,
1816 DRV_NAME
" channel", hisi_hba
);
1818 dev_err(dev
, "could not request chnl interrupt, rc=%d\n", rc
);
1823 rc
= devm_request_irq(dev
, pci_irq_vector(pdev
, 11),
1824 fatal_axi_int_v3_hw
, 0,
1825 DRV_NAME
" fatal", hisi_hba
);
1827 dev_err(dev
, "could not request fatal interrupt, rc=%d\n", rc
);
1829 goto free_chnl_interrupt
;
1832 /* Init tasklets for cq only */
1833 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
1834 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[i
];
1835 struct tasklet_struct
*t
= &cq
->tasklet
;
1837 rc
= devm_request_irq(dev
, pci_irq_vector(pdev
, i
+16),
1838 cq_interrupt_v3_hw
, 0,
1839 DRV_NAME
" cq", cq
);
1842 "could not request cq%d interrupt, rc=%d\n",
1848 tasklet_init(t
, cq_tasklet_v3_hw
, (unsigned long)cq
);
1854 for (k
= 0; k
< i
; k
++) {
1855 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[k
];
1857 free_irq(pci_irq_vector(pdev
, k
+16), cq
);
1859 free_irq(pci_irq_vector(pdev
, 11), hisi_hba
);
1860 free_chnl_interrupt
:
1861 free_irq(pci_irq_vector(pdev
, 2), hisi_hba
);
1863 free_irq(pci_irq_vector(pdev
, 1), hisi_hba
);
1865 pci_free_irq_vectors(pdev
);
1869 static int hisi_sas_v3_init(struct hisi_hba
*hisi_hba
)
1873 rc
= hw_init_v3_hw(hisi_hba
);
1877 rc
= interrupt_init_v3_hw(hisi_hba
);
1884 static void phy_set_linkrate_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
,
1885 struct sas_phy_linkrates
*r
)
1887 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1888 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1889 enum sas_linkrate min
, max
;
1890 u32 prog_phy_link_rate
= 0x800;
1892 if (r
->maximum_linkrate
== SAS_LINK_RATE_UNKNOWN
) {
1893 max
= sas_phy
->phy
->maximum_linkrate
;
1894 min
= r
->minimum_linkrate
;
1895 } else if (r
->minimum_linkrate
== SAS_LINK_RATE_UNKNOWN
) {
1896 max
= r
->maximum_linkrate
;
1897 min
= sas_phy
->phy
->minimum_linkrate
;
1901 sas_phy
->phy
->maximum_linkrate
= max
;
1902 sas_phy
->phy
->minimum_linkrate
= min
;
1903 prog_phy_link_rate
|= hisi_sas_get_prog_phy_linkrate_mask(max
);
1905 disable_phy_v3_hw(hisi_hba
, phy_no
);
1907 hisi_sas_phy_write32(hisi_hba
, phy_no
, PROG_PHY_LINK_RATE
,
1908 prog_phy_link_rate
);
1909 start_phy_v3_hw(hisi_hba
, phy_no
);
1912 static void interrupt_disable_v3_hw(struct hisi_hba
*hisi_hba
)
1914 struct pci_dev
*pdev
= hisi_hba
->pci_dev
;
1917 synchronize_irq(pci_irq_vector(pdev
, 1));
1918 synchronize_irq(pci_irq_vector(pdev
, 2));
1919 synchronize_irq(pci_irq_vector(pdev
, 11));
1920 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
1921 hisi_sas_write32(hisi_hba
, OQ0_INT_SRC_MSK
+ 0x4 * i
, 0x1);
1922 synchronize_irq(pci_irq_vector(pdev
, i
+ 16));
1925 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK1
, 0xffffffff);
1926 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK2
, 0xffffffff);
1927 hisi_sas_write32(hisi_hba
, ENT_INT_SRC_MSK3
, 0xffffffff);
1928 hisi_sas_write32(hisi_hba
, SAS_ECC_INTR_MSK
, 0xffffffff);
1930 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
1931 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT1_MSK
, 0xffffffff);
1932 hisi_sas_phy_write32(hisi_hba
, i
, CHL_INT2_MSK
, 0xffffffff);
1933 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_NOT_RDY_MSK
, 0x1);
1934 hisi_sas_phy_write32(hisi_hba
, i
, PHYCTRL_PHY_ENA_MSK
, 0x1);
1935 hisi_sas_phy_write32(hisi_hba
, i
, SL_RX_BCAST_CHK_MSK
, 0x1);
1939 static u32
get_phys_state_v3_hw(struct hisi_hba
*hisi_hba
)
1941 return hisi_sas_read32(hisi_hba
, PHY_STATE
);
1944 static void phy_get_events_v3_hw(struct hisi_hba
*hisi_hba
, int phy_no
)
1946 struct hisi_sas_phy
*phy
= &hisi_hba
->phy
[phy_no
];
1947 struct asd_sas_phy
*sas_phy
= &phy
->sas_phy
;
1948 struct sas_phy
*sphy
= sas_phy
->phy
;
1951 /* loss dword sync */
1952 reg_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
, ERR_CNT_DWS_LOST
);
1953 sphy
->loss_of_dword_sync_count
+= reg_value
;
1955 /* phy reset problem */
1956 reg_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
, ERR_CNT_RESET_PROB
);
1957 sphy
->phy_reset_problem_count
+= reg_value
;
1960 reg_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
, ERR_CNT_INVLD_DW
);
1961 sphy
->invalid_dword_count
+= reg_value
;
1964 reg_value
= hisi_sas_phy_read32(hisi_hba
, phy_no
, ERR_CNT_DISP_ERR
);
1965 sphy
->running_disparity_error_count
+= reg_value
;
1969 static int soft_reset_v3_hw(struct hisi_hba
*hisi_hba
)
1971 struct device
*dev
= hisi_hba
->dev
;
1975 interrupt_disable_v3_hw(hisi_hba
);
1976 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0x0);
1977 hisi_sas_kill_tasklets(hisi_hba
);
1979 hisi_sas_stop_phys(hisi_hba
);
1983 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
+ AM_CTRL_GLOBAL
, 0x1);
1985 /* wait until bus idle */
1986 rc
= readl_poll_timeout(hisi_hba
->regs
+ AXI_MASTER_CFG_BASE
+
1987 AM_CURR_TRANS_RETURN
, status
, status
== 0x3, 10, 100);
1989 dev_err(dev
, "axi bus is not idle, rc = %d\n", rc
);
1993 hisi_sas_init_mem(hisi_hba
);
1995 return hw_init_v3_hw(hisi_hba
);
1998 static const struct hisi_sas_hw hisi_sas_v3_hw
= {
1999 .hw_init
= hisi_sas_v3_init
,
2000 .setup_itct
= setup_itct_v3_hw
,
2001 .max_command_entries
= HISI_SAS_COMMAND_ENTRIES_V3_HW
,
2002 .get_wideport_bitmap
= get_wideport_bitmap_v3_hw
,
2003 .complete_hdr_size
= sizeof(struct hisi_sas_complete_v3_hdr
),
2004 .clear_itct
= clear_itct_v3_hw
,
2005 .sl_notify
= sl_notify_v3_hw
,
2006 .prep_ssp
= prep_ssp_v3_hw
,
2007 .prep_smp
= prep_smp_v3_hw
,
2008 .prep_stp
= prep_ata_v3_hw
,
2009 .prep_abort
= prep_abort_v3_hw
,
2010 .get_free_slot
= get_free_slot_v3_hw
,
2011 .start_delivery
= start_delivery_v3_hw
,
2012 .slot_complete
= slot_complete_v3_hw
,
2013 .phys_init
= phys_init_v3_hw
,
2014 .phy_start
= start_phy_v3_hw
,
2015 .phy_disable
= disable_phy_v3_hw
,
2016 .phy_hard_reset
= phy_hard_reset_v3_hw
,
2017 .phy_get_max_linkrate
= phy_get_max_linkrate_v3_hw
,
2018 .phy_set_linkrate
= phy_set_linkrate_v3_hw
,
2019 .dereg_device
= dereg_device_v3_hw
,
2020 .soft_reset
= soft_reset_v3_hw
,
2021 .get_phys_state
= get_phys_state_v3_hw
,
2022 .get_events
= phy_get_events_v3_hw
,
2025 static struct Scsi_Host
*
2026 hisi_sas_shost_alloc_pci(struct pci_dev
*pdev
)
2028 struct Scsi_Host
*shost
;
2029 struct hisi_hba
*hisi_hba
;
2030 struct device
*dev
= &pdev
->dev
;
2032 shost
= scsi_host_alloc(hisi_sas_sht
, sizeof(*hisi_hba
));
2034 dev_err(dev
, "shost alloc failed\n");
2037 hisi_hba
= shost_priv(shost
);
2039 INIT_WORK(&hisi_hba
->rst_work
, hisi_sas_rst_work_handler
);
2040 hisi_hba
->hw
= &hisi_sas_v3_hw
;
2041 hisi_hba
->pci_dev
= pdev
;
2042 hisi_hba
->dev
= dev
;
2043 hisi_hba
->shost
= shost
;
2044 SHOST_TO_SAS_HA(shost
) = &hisi_hba
->sha
;
2046 timer_setup(&hisi_hba
->timer
, NULL
, 0);
2048 if (hisi_sas_get_fw_info(hisi_hba
) < 0)
2051 if (hisi_sas_alloc(hisi_hba
, shost
)) {
2052 hisi_sas_free(hisi_hba
);
2058 scsi_host_put(shost
);
2059 dev_err(dev
, "shost alloc failed\n");
2064 hisi_sas_v3_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2066 struct Scsi_Host
*shost
;
2067 struct hisi_hba
*hisi_hba
;
2068 struct device
*dev
= &pdev
->dev
;
2069 struct asd_sas_phy
**arr_phy
;
2070 struct asd_sas_port
**arr_port
;
2071 struct sas_ha_struct
*sha
;
2072 int rc
, phy_nr
, port_nr
, i
;
2074 rc
= pci_enable_device(pdev
);
2078 pci_set_master(pdev
);
2080 rc
= pci_request_regions(pdev
, DRV_NAME
);
2082 goto err_out_disable_device
;
2084 if ((pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) != 0) ||
2085 (pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64)) != 0)) {
2086 if ((pci_set_dma_mask(pdev
, DMA_BIT_MASK(32)) != 0) ||
2087 (pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)) != 0)) {
2088 dev_err(dev
, "No usable DMA addressing method\n");
2090 goto err_out_regions
;
2094 shost
= hisi_sas_shost_alloc_pci(pdev
);
2097 goto err_out_regions
;
2100 sha
= SHOST_TO_SAS_HA(shost
);
2101 hisi_hba
= shost_priv(shost
);
2102 dev_set_drvdata(dev
, sha
);
2104 hisi_hba
->regs
= pcim_iomap(pdev
, 5, 0);
2105 if (!hisi_hba
->regs
) {
2106 dev_err(dev
, "cannot map register.\n");
2111 phy_nr
= port_nr
= hisi_hba
->n_phy
;
2113 arr_phy
= devm_kcalloc(dev
, phy_nr
, sizeof(void *), GFP_KERNEL
);
2114 arr_port
= devm_kcalloc(dev
, port_nr
, sizeof(void *), GFP_KERNEL
);
2115 if (!arr_phy
|| !arr_port
) {
2120 sha
->sas_phy
= arr_phy
;
2121 sha
->sas_port
= arr_port
;
2122 sha
->core
.shost
= shost
;
2123 sha
->lldd_ha
= hisi_hba
;
2125 shost
->transportt
= hisi_sas_stt
;
2126 shost
->max_id
= HISI_SAS_MAX_DEVICES
;
2127 shost
->max_lun
= ~0;
2128 shost
->max_channel
= 1;
2129 shost
->max_cmd_len
= 16;
2130 shost
->sg_tablesize
= min_t(u16
, SG_ALL
, HISI_SAS_SGE_PAGE_CNT
);
2131 shost
->can_queue
= hisi_hba
->hw
->max_command_entries
;
2132 shost
->cmd_per_lun
= hisi_hba
->hw
->max_command_entries
;
2134 sha
->sas_ha_name
= DRV_NAME
;
2136 sha
->lldd_module
= THIS_MODULE
;
2137 sha
->sas_addr
= &hisi_hba
->sas_addr
[0];
2138 sha
->num_phys
= hisi_hba
->n_phy
;
2139 sha
->core
.shost
= hisi_hba
->shost
;
2141 for (i
= 0; i
< hisi_hba
->n_phy
; i
++) {
2142 sha
->sas_phy
[i
] = &hisi_hba
->phy
[i
].sas_phy
;
2143 sha
->sas_port
[i
] = &hisi_hba
->port
[i
].sas_port
;
2146 hisi_sas_init_add(hisi_hba
);
2148 rc
= scsi_add_host(shost
, dev
);
2152 rc
= sas_register_ha(sha
);
2154 goto err_out_register_ha
;
2156 rc
= hisi_hba
->hw
->hw_init(hisi_hba
);
2158 goto err_out_register_ha
;
2160 scsi_scan_host(shost
);
2164 err_out_register_ha
:
2165 scsi_remove_host(shost
);
2167 scsi_host_put(shost
);
2169 pci_release_regions(pdev
);
2170 err_out_disable_device
:
2171 pci_disable_device(pdev
);
2177 hisi_sas_v3_destroy_irqs(struct pci_dev
*pdev
, struct hisi_hba
*hisi_hba
)
2181 free_irq(pci_irq_vector(pdev
, 1), hisi_hba
);
2182 free_irq(pci_irq_vector(pdev
, 2), hisi_hba
);
2183 free_irq(pci_irq_vector(pdev
, 11), hisi_hba
);
2184 for (i
= 0; i
< hisi_hba
->queue_count
; i
++) {
2185 struct hisi_sas_cq
*cq
= &hisi_hba
->cq
[i
];
2187 free_irq(pci_irq_vector(pdev
, i
+16), cq
);
2189 pci_free_irq_vectors(pdev
);
2192 static void hisi_sas_v3_remove(struct pci_dev
*pdev
)
2194 struct device
*dev
= &pdev
->dev
;
2195 struct sas_ha_struct
*sha
= dev_get_drvdata(dev
);
2196 struct hisi_hba
*hisi_hba
= sha
->lldd_ha
;
2197 struct Scsi_Host
*shost
= sha
->core
.shost
;
2199 if (timer_pending(&hisi_hba
->timer
))
2200 del_timer(&hisi_hba
->timer
);
2202 sas_unregister_ha(sha
);
2203 sas_remove_host(sha
->core
.shost
);
2205 hisi_sas_v3_destroy_irqs(pdev
, hisi_hba
);
2206 hisi_sas_kill_tasklets(hisi_hba
);
2207 pci_release_regions(pdev
);
2208 pci_disable_device(pdev
);
2209 hisi_sas_free(hisi_hba
);
2210 scsi_host_put(shost
);
2213 static const struct hisi_sas_hw_error sas_ras_intr0_nfe
[] = {
2214 { .irq_msk
= BIT(19), .msg
= "HILINK_INT" },
2215 { .irq_msk
= BIT(20), .msg
= "HILINK_PLL0_OUT_OF_LOCK" },
2216 { .irq_msk
= BIT(21), .msg
= "HILINK_PLL1_OUT_OF_LOCK" },
2217 { .irq_msk
= BIT(22), .msg
= "HILINK_LOSS_OF_REFCLK0" },
2218 { .irq_msk
= BIT(23), .msg
= "HILINK_LOSS_OF_REFCLK1" },
2219 { .irq_msk
= BIT(24), .msg
= "DMAC0_TX_POISON" },
2220 { .irq_msk
= BIT(25), .msg
= "DMAC1_TX_POISON" },
2221 { .irq_msk
= BIT(26), .msg
= "DMAC2_TX_POISON" },
2222 { .irq_msk
= BIT(27), .msg
= "DMAC3_TX_POISON" },
2223 { .irq_msk
= BIT(28), .msg
= "DMAC4_TX_POISON" },
2224 { .irq_msk
= BIT(29), .msg
= "DMAC5_TX_POISON" },
2225 { .irq_msk
= BIT(30), .msg
= "DMAC6_TX_POISON" },
2226 { .irq_msk
= BIT(31), .msg
= "DMAC7_TX_POISON" },
2229 static const struct hisi_sas_hw_error sas_ras_intr1_nfe
[] = {
2230 { .irq_msk
= BIT(0), .msg
= "RXM_CFG_MEM3_ECC2B_INTR" },
2231 { .irq_msk
= BIT(1), .msg
= "RXM_CFG_MEM2_ECC2B_INTR" },
2232 { .irq_msk
= BIT(2), .msg
= "RXM_CFG_MEM1_ECC2B_INTR" },
2233 { .irq_msk
= BIT(3), .msg
= "RXM_CFG_MEM0_ECC2B_INTR" },
2234 { .irq_msk
= BIT(4), .msg
= "HGC_CQE_ECC2B_INTR" },
2235 { .irq_msk
= BIT(5), .msg
= "LM_CFG_IOSTL_ECC2B_INTR" },
2236 { .irq_msk
= BIT(6), .msg
= "LM_CFG_ITCTL_ECC2B_INTR" },
2237 { .irq_msk
= BIT(7), .msg
= "HGC_ITCT_ECC2B_INTR" },
2238 { .irq_msk
= BIT(8), .msg
= "HGC_IOST_ECC2B_INTR" },
2239 { .irq_msk
= BIT(9), .msg
= "HGC_DQE_ECC2B_INTR" },
2240 { .irq_msk
= BIT(10), .msg
= "DMAC0_RAM_ECC2B_INTR" },
2241 { .irq_msk
= BIT(11), .msg
= "DMAC1_RAM_ECC2B_INTR" },
2242 { .irq_msk
= BIT(12), .msg
= "DMAC2_RAM_ECC2B_INTR" },
2243 { .irq_msk
= BIT(13), .msg
= "DMAC3_RAM_ECC2B_INTR" },
2244 { .irq_msk
= BIT(14), .msg
= "DMAC4_RAM_ECC2B_INTR" },
2245 { .irq_msk
= BIT(15), .msg
= "DMAC5_RAM_ECC2B_INTR" },
2246 { .irq_msk
= BIT(16), .msg
= "DMAC6_RAM_ECC2B_INTR" },
2247 { .irq_msk
= BIT(17), .msg
= "DMAC7_RAM_ECC2B_INTR" },
2248 { .irq_msk
= BIT(18), .msg
= "OOO_RAM_ECC2B_INTR" },
2249 { .irq_msk
= BIT(20), .msg
= "HGC_DQE_POISON_INTR" },
2250 { .irq_msk
= BIT(21), .msg
= "HGC_IOST_POISON_INTR" },
2251 { .irq_msk
= BIT(22), .msg
= "HGC_ITCT_POISON_INTR" },
2252 { .irq_msk
= BIT(23), .msg
= "HGC_ITCT_NCQ_POISON_INTR" },
2253 { .irq_msk
= BIT(24), .msg
= "DMAC0_RX_POISON" },
2254 { .irq_msk
= BIT(25), .msg
= "DMAC1_RX_POISON" },
2255 { .irq_msk
= BIT(26), .msg
= "DMAC2_RX_POISON" },
2256 { .irq_msk
= BIT(27), .msg
= "DMAC3_RX_POISON" },
2257 { .irq_msk
= BIT(28), .msg
= "DMAC4_RX_POISON" },
2258 { .irq_msk
= BIT(29), .msg
= "DMAC5_RX_POISON" },
2259 { .irq_msk
= BIT(30), .msg
= "DMAC6_RX_POISON" },
2260 { .irq_msk
= BIT(31), .msg
= "DMAC7_RX_POISON" },
2263 static const struct hisi_sas_hw_error sas_ras_intr2_nfe
[] = {
2264 { .irq_msk
= BIT(0), .msg
= "DMAC0_AXI_BUS_ERR" },
2265 { .irq_msk
= BIT(1), .msg
= "DMAC1_AXI_BUS_ERR" },
2266 { .irq_msk
= BIT(2), .msg
= "DMAC2_AXI_BUS_ERR" },
2267 { .irq_msk
= BIT(3), .msg
= "DMAC3_AXI_BUS_ERR" },
2268 { .irq_msk
= BIT(4), .msg
= "DMAC4_AXI_BUS_ERR" },
2269 { .irq_msk
= BIT(5), .msg
= "DMAC5_AXI_BUS_ERR" },
2270 { .irq_msk
= BIT(6), .msg
= "DMAC6_AXI_BUS_ERR" },
2271 { .irq_msk
= BIT(7), .msg
= "DMAC7_AXI_BUS_ERR" },
2272 { .irq_msk
= BIT(8), .msg
= "DMAC0_FIFO_OMIT_ERR" },
2273 { .irq_msk
= BIT(9), .msg
= "DMAC1_FIFO_OMIT_ERR" },
2274 { .irq_msk
= BIT(10), .msg
= "DMAC2_FIFO_OMIT_ERR" },
2275 { .irq_msk
= BIT(11), .msg
= "DMAC3_FIFO_OMIT_ERR" },
2276 { .irq_msk
= BIT(12), .msg
= "DMAC4_FIFO_OMIT_ERR" },
2277 { .irq_msk
= BIT(13), .msg
= "DMAC5_FIFO_OMIT_ERR" },
2278 { .irq_msk
= BIT(14), .msg
= "DMAC6_FIFO_OMIT_ERR" },
2279 { .irq_msk
= BIT(15), .msg
= "DMAC7_FIFO_OMIT_ERR" },
2280 { .irq_msk
= BIT(16), .msg
= "HGC_RLSE_SLOT_UNMATCH" },
2281 { .irq_msk
= BIT(17), .msg
= "HGC_LM_ADD_FCH_LIST_ERR" },
2282 { .irq_msk
= BIT(18), .msg
= "HGC_AXI_BUS_ERR" },
2283 { .irq_msk
= BIT(19), .msg
= "HGC_FIFO_OMIT_ERR" },
2286 static bool process_non_fatal_error_v3_hw(struct hisi_hba
*hisi_hba
)
2288 struct device
*dev
= hisi_hba
->dev
;
2289 const struct hisi_sas_hw_error
*ras_error
;
2290 bool need_reset
= false;
2294 irq_value
= hisi_sas_read32(hisi_hba
, SAS_RAS_INTR0
);
2295 for (i
= 0; i
< ARRAY_SIZE(sas_ras_intr0_nfe
); i
++) {
2296 ras_error
= &sas_ras_intr0_nfe
[i
];
2297 if (ras_error
->irq_msk
& irq_value
) {
2298 dev_warn(dev
, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n",
2299 ras_error
->msg
, irq_value
);
2303 hisi_sas_write32(hisi_hba
, SAS_RAS_INTR0
, irq_value
);
2305 irq_value
= hisi_sas_read32(hisi_hba
, SAS_RAS_INTR1
);
2306 for (i
= 0; i
< ARRAY_SIZE(sas_ras_intr1_nfe
); i
++) {
2307 ras_error
= &sas_ras_intr1_nfe
[i
];
2308 if (ras_error
->irq_msk
& irq_value
) {
2309 dev_warn(dev
, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n",
2310 ras_error
->msg
, irq_value
);
2314 hisi_sas_write32(hisi_hba
, SAS_RAS_INTR1
, irq_value
);
2316 irq_value
= hisi_sas_read32(hisi_hba
, SAS_RAS_INTR2
);
2317 for (i
= 0; i
< ARRAY_SIZE(sas_ras_intr2_nfe
); i
++) {
2318 ras_error
= &sas_ras_intr2_nfe
[i
];
2319 if (ras_error
->irq_msk
& irq_value
) {
2320 dev_warn(dev
, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n",
2321 ras_error
->msg
, irq_value
);
2325 hisi_sas_write32(hisi_hba
, SAS_RAS_INTR2
, irq_value
);
2330 static pci_ers_result_t
hisi_sas_error_detected_v3_hw(struct pci_dev
*pdev
,
2331 pci_channel_state_t state
)
2333 struct sas_ha_struct
*sha
= pci_get_drvdata(pdev
);
2334 struct hisi_hba
*hisi_hba
= sha
->lldd_ha
;
2335 struct device
*dev
= hisi_hba
->dev
;
2337 dev_info(dev
, "PCI error: detected callback, state(%d)!!\n", state
);
2338 if (state
== pci_channel_io_perm_failure
)
2339 return PCI_ERS_RESULT_DISCONNECT
;
2341 if (process_non_fatal_error_v3_hw(hisi_hba
))
2342 return PCI_ERS_RESULT_NEED_RESET
;
2344 return PCI_ERS_RESULT_CAN_RECOVER
;
2347 static pci_ers_result_t
hisi_sas_mmio_enabled_v3_hw(struct pci_dev
*pdev
)
2349 return PCI_ERS_RESULT_RECOVERED
;
2352 static pci_ers_result_t
hisi_sas_slot_reset_v3_hw(struct pci_dev
*pdev
)
2354 struct sas_ha_struct
*sha
= pci_get_drvdata(pdev
);
2355 struct hisi_hba
*hisi_hba
= sha
->lldd_ha
;
2356 struct device
*dev
= hisi_hba
->dev
;
2357 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r
);
2359 dev_info(dev
, "PCI error: slot reset callback!!\n");
2360 queue_work(hisi_hba
->wq
, &r
.work
);
2361 wait_for_completion(r
.completion
);
2363 return PCI_ERS_RESULT_RECOVERED
;
2365 return PCI_ERS_RESULT_DISCONNECT
;
2369 /* instances of the controller */
2373 static int hisi_sas_v3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2375 struct sas_ha_struct
*sha
= pci_get_drvdata(pdev
);
2376 struct hisi_hba
*hisi_hba
= sha
->lldd_ha
;
2377 struct device
*dev
= hisi_hba
->dev
;
2378 struct Scsi_Host
*shost
= hisi_hba
->shost
;
2379 u32 device_state
, status
;
2382 unsigned long flags
;
2384 if (!pdev
->pm_cap
) {
2385 dev_err(dev
, "PCI PM not supported\n");
2389 set_bit(HISI_SAS_RESET_BIT
, &hisi_hba
->flags
);
2390 scsi_block_requests(shost
);
2391 set_bit(HISI_SAS_REJECT_CMD_BIT
, &hisi_hba
->flags
);
2392 flush_workqueue(hisi_hba
->wq
);
2393 /* disable DQ/PHY/bus */
2394 interrupt_disable_v3_hw(hisi_hba
);
2395 hisi_sas_write32(hisi_hba
, DLVRY_QUEUE_ENABLE
, 0x0);
2396 hisi_sas_kill_tasklets(hisi_hba
);
2398 hisi_sas_stop_phys(hisi_hba
);
2400 reg_val
= hisi_sas_read32(hisi_hba
, AXI_MASTER_CFG_BASE
+
2403 hisi_sas_write32(hisi_hba
, AXI_MASTER_CFG_BASE
+
2404 AM_CTRL_GLOBAL
, reg_val
);
2406 /* wait until bus idle */
2407 rc
= readl_poll_timeout(hisi_hba
->regs
+ AXI_MASTER_CFG_BASE
+
2408 AM_CURR_TRANS_RETURN
, status
, status
== 0x3, 10, 100);
2410 dev_err(dev
, "axi bus is not idle, rc = %d\n", rc
);
2411 clear_bit(HISI_SAS_REJECT_CMD_BIT
, &hisi_hba
->flags
);
2412 clear_bit(HISI_SAS_RESET_BIT
, &hisi_hba
->flags
);
2413 scsi_unblock_requests(shost
);
2417 hisi_sas_init_mem(hisi_hba
);
2419 device_state
= pci_choose_state(pdev
, state
);
2420 dev_warn(dev
, "entering operating state [D%d]\n",
2422 pci_save_state(pdev
);
2423 pci_disable_device(pdev
);
2424 pci_set_power_state(pdev
, device_state
);
2426 spin_lock_irqsave(&hisi_hba
->lock
, flags
);
2427 hisi_sas_release_tasks(hisi_hba
);
2428 spin_unlock_irqrestore(&hisi_hba
->lock
, flags
);
2430 sas_suspend_ha(sha
);
2434 static int hisi_sas_v3_resume(struct pci_dev
*pdev
)
2436 struct sas_ha_struct
*sha
= pci_get_drvdata(pdev
);
2437 struct hisi_hba
*hisi_hba
= sha
->lldd_ha
;
2438 struct Scsi_Host
*shost
= hisi_hba
->shost
;
2439 struct device
*dev
= hisi_hba
->dev
;
2441 u32 device_state
= pdev
->current_state
;
2443 dev_warn(dev
, "resuming from operating state [D%d]\n",
2445 pci_set_power_state(pdev
, PCI_D0
);
2446 pci_enable_wake(pdev
, PCI_D0
, 0);
2447 pci_restore_state(pdev
);
2448 rc
= pci_enable_device(pdev
);
2450 dev_err(dev
, "enable device failed during resume (%d)\n", rc
);
2452 pci_set_master(pdev
);
2453 scsi_unblock_requests(shost
);
2454 clear_bit(HISI_SAS_REJECT_CMD_BIT
, &hisi_hba
->flags
);
2456 sas_prep_resume_ha(sha
);
2457 init_reg_v3_hw(hisi_hba
);
2458 hisi_hba
->hw
->phys_init(hisi_hba
);
2460 clear_bit(HISI_SAS_RESET_BIT
, &hisi_hba
->flags
);
2465 static const struct pci_device_id sas_v3_pci_table
[] = {
2466 { PCI_VDEVICE(HUAWEI
, 0xa230), hip08
},
2469 MODULE_DEVICE_TABLE(pci
, sas_v3_pci_table
);
2471 static const struct pci_error_handlers hisi_sas_err_handler
= {
2472 .error_detected
= hisi_sas_error_detected_v3_hw
,
2473 .mmio_enabled
= hisi_sas_mmio_enabled_v3_hw
,
2474 .slot_reset
= hisi_sas_slot_reset_v3_hw
,
2477 static struct pci_driver sas_v3_pci_driver
= {
2479 .id_table
= sas_v3_pci_table
,
2480 .probe
= hisi_sas_v3_probe
,
2481 .remove
= hisi_sas_v3_remove
,
2482 .suspend
= hisi_sas_v3_suspend
,
2483 .resume
= hisi_sas_v3_resume
,
2484 .err_handler
= &hisi_sas_err_handler
,
2487 module_pci_driver(sas_v3_pci_driver
);
2489 MODULE_LICENSE("GPL");
2490 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2491 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2492 MODULE_ALIAS("pci:" DRV_NAME
);