2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2016 Microsemi Corporation
4 * Copyright 2014-2015 PMC-Sierra, Inc.
5 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
14 * NON INFRINGEMENT. See the GNU General Public License for more details.
16 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
22 #include <scsi/scsicam.h>
29 struct access_method
{
30 void (*submit_command
)(struct ctlr_info
*h
,
31 struct CommandList
*c
);
32 void (*set_intr_mask
)(struct ctlr_info
*h
, unsigned long val
);
33 bool (*intr_pending
)(struct ctlr_info
*h
);
34 unsigned long (*command_completed
)(struct ctlr_info
*h
, u8 q
);
37 /* for SAS hosts and SAS expanders */
38 struct hpsa_sas_node
{
39 struct device
*parent_dev
;
40 struct list_head port_list_head
;
43 struct hpsa_sas_port
{
44 struct list_head port_list_entry
;
46 struct sas_port
*port
;
48 struct list_head phy_list_head
;
49 struct hpsa_sas_node
*parent_node
;
50 struct sas_rphy
*rphy
;
54 struct list_head phy_list_entry
;
56 struct hpsa_sas_port
*parent_port
;
61 struct hpsa_scsi_dev_t
{
63 int bus
, target
, lun
; /* as presented to the OS */
64 unsigned char scsi3addr
[8]; /* as presented to the HW */
65 u8 physical_device
: 1;
67 u8 removed
: 1; /* device is marked for death */
68 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
69 unsigned char device_id
[16]; /* from inquiry pg. 0x83 */
71 unsigned char vendor
[8]; /* bytes 8-15 of inquiry data */
72 unsigned char model
[16]; /* bytes 16-31 of inquiry data */
73 unsigned char rev
; /* byte 2 of inquiry data */
74 unsigned char raid_level
; /* from inquiry page 0xC1 */
75 unsigned char volume_offline
; /* discovered via TUR or VPD */
76 u16 queue_depth
; /* max queue_depth for this device */
77 atomic_t reset_cmds_out
; /* Count of commands to-be affected */
78 atomic_t ioaccel_cmds_out
; /* Only used for physical devices
79 * counts commands sent to physical
80 * device via "ioaccel" path.
87 u16 phys_connector
[8];
88 int offload_config
; /* I/O accel RAID offload configured */
89 int offload_enabled
; /* I/O accel RAID offload enabled */
90 int offload_to_be_enabled
;
91 int hba_ioaccel_enabled
;
92 int offload_to_mirror
; /* Send next I/O accelerator RAID
93 * offload request to mirror drive
95 struct raid_map_data raid_map
; /* I/O accelerator RAID map */
98 * Pointers from logical drive map indices to the phys drives that
99 * make those logical drives. Note, multiple logical drives may
100 * share physical drives. You can have for instance 5 physical
101 * drives with 3 logical drives each using those same 5 physical
102 * disks. We need these pointers for counting i/o's out to physical
103 * devices in order to honor physical device queue depth limits.
105 struct hpsa_scsi_dev_t
*phys_disk
[RAID_MAP_MAX_ENTRIES
];
108 struct hpsa_sas_port
*sas_port
;
109 int external
; /* 1-from external array 0-not <0-unknown */
112 struct reply_queue_buffer
{
121 struct bmic_controller_parameters
{
123 u8 enable_command_list_verification
;
124 u8 backed_out_write_drives
;
125 u16 stripes_for_parity
;
126 u8 parity_distribution_mode_flags
;
127 u16 max_driver_requests
;
128 u16 elevator_trend_count
;
130 u8 force_scan_complete
;
131 u8 scsi_transfer_mode
;
135 u8 host_sdb_asic_fix
;
136 u8 pdpi_burst_from_host_disabled
;
137 char software_name
[64];
138 char hardware_name
[32];
140 u8 snapshot_priority
;
142 u8 post_prompt_timeout
;
143 u8 automatic_drive_slamming
;
146 u8 cache_nvram_flags
;
147 u8 drive_config_flags
;
149 u8 temp_warning_level
;
150 u8 temp_shutdown_level
;
151 u8 temp_condition_reset
;
152 u8 max_coalesce_commands
;
153 u32 max_coalesce_delay
;
164 struct pci_dev
*pdev
;
169 int nr_cmds
; /* Number of commands allowed on this controller */
170 #define HPSA_CMDS_RESERVED_FOR_ABORTS 2
171 #define HPSA_CMDS_RESERVED_FOR_DRIVER 1
172 struct CfgTable __iomem
*cfgtable
;
173 int interrupts_enabled
;
175 atomic_t commands_outstanding
;
176 # define PERF_MODE_INT 0
177 # define DOORBELL_INT 1
178 # define SIMPLE_MODE_INT 2
179 # define MEMQ_MODE_INT 3
180 unsigned int msix_vectors
;
181 int intr_mode
; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
182 struct access_method access
;
184 /* queue and queue Info */
189 u8 max_cmd_sg_entries
;
191 struct SGDescriptor
**cmd_sg_list
;
192 struct ioaccel2_sg_element
**ioaccel2_cmd_sg_list
;
194 /* pointers to command and error info pool */
195 struct CommandList
*cmd_pool
;
196 dma_addr_t cmd_pool_dhandle
;
197 struct io_accel1_cmd
*ioaccel_cmd_pool
;
198 dma_addr_t ioaccel_cmd_pool_dhandle
;
199 struct io_accel2_cmd
*ioaccel2_cmd_pool
;
200 dma_addr_t ioaccel2_cmd_pool_dhandle
;
201 struct ErrorInfo
*errinfo_pool
;
202 dma_addr_t errinfo_pool_dhandle
;
203 unsigned long *cmd_pool_bits
;
206 spinlock_t scan_lock
;
207 wait_queue_head_t scan_wait_queue
;
209 struct Scsi_Host
*scsi_host
;
210 spinlock_t devlock
; /* to protect hba[ctlr]->dev[]; */
211 int ndevices
; /* number of used elements in .dev[] array. */
212 struct hpsa_scsi_dev_t
*dev
[HPSA_MAX_DEVICES
];
214 * Performant mode tables.
218 struct TransTable_struct __iomem
*transtable
;
219 unsigned long transMethod
;
221 /* cap concurrent passthrus at some reasonable maximum */
222 #define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
223 atomic_t passthru_cmds_avail
;
226 * Performant mode completion buffers
228 size_t reply_queue_size
;
229 struct reply_queue_buffer reply_queue
[MAX_REPLY_QUEUES
];
231 u32
*blockFetchTable
;
232 u32
*ioaccel1_blockFetchTable
;
233 u32
*ioaccel2_blockFetchTable
;
234 u32 __iomem
*ioaccel2_bft2_regs
;
235 unsigned char *hba_inquiry_data
;
240 u64 last_intr_timestamp
;
242 u64 last_heartbeat_timestamp
;
243 u32 heartbeat_sample_interval
;
244 atomic_t firmware_flash_in_progress
;
245 u32 __percpu
*lockup_detected
;
246 struct delayed_work monitor_ctlr_work
;
247 struct delayed_work rescan_ctlr_work
;
248 struct delayed_work event_monitor_work
;
249 int remove_in_progress
;
250 /* Address of h->q[x] is passed to intr handler to know which queue */
251 u8 q
[MAX_REPLY_QUEUES
];
252 char intrname
[MAX_REPLY_QUEUES
][16]; /* "hpsa0-msix00" names */
253 u32 TMFSupportFlags
; /* cache what task mgmt funcs are supported. */
254 #define HPSATMF_BITS_SUPPORTED (1 << 0)
255 #define HPSATMF_PHYS_LUN_RESET (1 << 1)
256 #define HPSATMF_PHYS_NEX_RESET (1 << 2)
257 #define HPSATMF_PHYS_TASK_ABORT (1 << 3)
258 #define HPSATMF_PHYS_TSET_ABORT (1 << 4)
259 #define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
260 #define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
261 #define HPSATMF_PHYS_QRY_TASK (1 << 7)
262 #define HPSATMF_PHYS_QRY_TSET (1 << 8)
263 #define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
264 #define HPSATMF_IOACCEL_ENABLED (1 << 15)
265 #define HPSATMF_MASK_SUPPORTED (1 << 16)
266 #define HPSATMF_LOG_LUN_RESET (1 << 17)
267 #define HPSATMF_LOG_NEX_RESET (1 << 18)
268 #define HPSATMF_LOG_TASK_ABORT (1 << 19)
269 #define HPSATMF_LOG_TSET_ABORT (1 << 20)
270 #define HPSATMF_LOG_CLEAR_ACA (1 << 21)
271 #define HPSATMF_LOG_CLEAR_TSET (1 << 22)
272 #define HPSATMF_LOG_QRY_TASK (1 << 23)
273 #define HPSATMF_LOG_QRY_TSET (1 << 24)
274 #define HPSATMF_LOG_QRY_ASYNC (1 << 25)
276 #define CTLR_STATE_CHANGE_EVENT (1 << 0)
277 #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
278 #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
279 #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
280 #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
281 #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
282 #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
284 #define RESCAN_REQUIRED_EVENT_BITS \
285 (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
286 CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
287 CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
288 CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
289 CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
290 spinlock_t offline_device_lock
;
291 struct list_head offline_device_list
;
292 int acciopath_status
;
294 int raid_offload_debug
;
295 int discovery_polling
;
296 struct ReportLUNdata
*lastlogicals
;
297 int needs_abort_tags_swizzled
;
298 struct workqueue_struct
*resubmit_wq
;
299 struct workqueue_struct
*rescan_ctlr_wq
;
300 atomic_t abort_cmds_available
;
301 wait_queue_head_t event_sync_wait_queue
;
302 struct mutex reset_mutex
;
303 u8 reset_in_progress
;
304 struct hpsa_sas_node
*sas_host
;
305 spinlock_t reset_lock
;
308 struct offline_device_entry
{
309 unsigned char scsi3addr
[8];
310 struct list_head offline_list
;
313 #define HPSA_ABORT_MSG 0
314 #define HPSA_DEVICE_RESET_MSG 1
315 #define HPSA_RESET_TYPE_CONTROLLER 0x00
316 #define HPSA_RESET_TYPE_BUS 0x01
317 #define HPSA_RESET_TYPE_LUN 0x04
318 #define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */
319 #define HPSA_MSG_SEND_RETRY_LIMIT 10
320 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
322 /* Maximum time in seconds driver will wait for command completions
323 * when polling before giving up.
325 #define HPSA_MAX_POLL_TIME_SECS (20)
327 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
328 * how many times to retry TEST UNIT READY on a device
329 * while waiting for it to become ready before giving up.
330 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
331 * between sending TURs while waiting for a device
334 #define HPSA_TUR_RETRY_LIMIT (20)
335 #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
337 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
338 * to become ready, in seconds, before giving up on it.
339 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
340 * between polling the board to see if it is ready, in
341 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
342 * HPSA_BOARD_READY_ITERATIONS are derived from those.
344 #define HPSA_BOARD_READY_WAIT_SECS (120)
345 #define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
346 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
347 #define HPSA_BOARD_READY_POLL_INTERVAL \
348 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
349 #define HPSA_BOARD_READY_ITERATIONS \
350 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
351 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
352 #define HPSA_BOARD_NOT_READY_ITERATIONS \
353 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
354 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
355 #define HPSA_POST_RESET_PAUSE_MSECS (3000)
356 #define HPSA_POST_RESET_NOOP_RETRIES (12)
358 /* Defining the diffent access_menthods */
360 * Memory mapped FIFO interface (SMART 53xx cards)
362 #define SA5_DOORBELL 0x20
363 #define SA5_REQUEST_PORT_OFFSET 0x40
364 #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0
365 #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4
366 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
367 #define SA5_REPLY_PORT_OFFSET 0x44
368 #define SA5_INTR_STATUS 0x30
369 #define SA5_SCRATCHPAD_OFFSET 0xB0
371 #define SA5_CTCFG_OFFSET 0xB4
372 #define SA5_CTMEM_OFFSET 0xB8
374 #define SA5_INTR_OFF 0x08
375 #define SA5B_INTR_OFF 0x04
376 #define SA5_INTR_PENDING 0x08
377 #define SA5B_INTR_PENDING 0x04
378 #define FIFO_EMPTY 0xffffffff
379 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
381 #define HPSA_ERROR_BIT 0x02
383 /* Performant mode flags */
384 #define SA5_PERF_INTR_PENDING 0x04
385 #define SA5_PERF_INTR_OFF 0x05
386 #define SA5_OUTDB_STATUS_PERF_BIT 0x01
387 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
388 #define SA5_OUTDB_CLEAR 0xA0
389 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
390 #define SA5_OUTDB_STATUS 0x9C
393 #define HPSA_INTR_ON 1
394 #define HPSA_INTR_OFF 0
397 * Inbound Post Queue offsets for IO Accelerator Mode 2
399 #define IOACCEL2_INBOUND_POSTQ_32 0x48
400 #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
401 #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
403 #define HPSA_PHYSICAL_DEVICE_BUS 0
404 #define HPSA_RAID_VOLUME_BUS 1
405 #define HPSA_EXTERNAL_RAID_VOLUME_BUS 2
406 #define HPSA_HBA_BUS 0
407 #define HPSA_LEGACY_HBA_BUS 3
410 Send the command to the hardware
412 static void SA5_submit_command(struct ctlr_info
*h
,
413 struct CommandList
*c
)
415 writel(c
->busaddr
, h
->vaddr
+ SA5_REQUEST_PORT_OFFSET
);
416 (void) readl(h
->vaddr
+ SA5_SCRATCHPAD_OFFSET
);
419 static void SA5_submit_command_no_read(struct ctlr_info
*h
,
420 struct CommandList
*c
)
422 writel(c
->busaddr
, h
->vaddr
+ SA5_REQUEST_PORT_OFFSET
);
425 static void SA5_submit_command_ioaccel2(struct ctlr_info
*h
,
426 struct CommandList
*c
)
428 writel(c
->busaddr
, h
->vaddr
+ SA5_REQUEST_PORT_OFFSET
);
432 * This card is the opposite of the other cards.
433 * 0 turns interrupts on...
434 * 0x08 turns them off...
436 static void SA5_intr_mask(struct ctlr_info
*h
, unsigned long val
)
438 if (val
) { /* Turn interrupts on */
439 h
->interrupts_enabled
= 1;
440 writel(0, h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
441 (void) readl(h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
442 } else { /* Turn them off */
443 h
->interrupts_enabled
= 0;
445 h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
446 (void) readl(h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
450 static void SA5_performant_intr_mask(struct ctlr_info
*h
, unsigned long val
)
452 if (val
) { /* turn on interrupts */
453 h
->interrupts_enabled
= 1;
454 writel(0, h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
455 (void) readl(h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
457 h
->interrupts_enabled
= 0;
458 writel(SA5_PERF_INTR_OFF
,
459 h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
460 (void) readl(h
->vaddr
+ SA5_REPLY_INTR_MASK_OFFSET
);
464 static unsigned long SA5_performant_completed(struct ctlr_info
*h
, u8 q
)
466 struct reply_queue_buffer
*rq
= &h
->reply_queue
[q
];
467 unsigned long register_value
= FIFO_EMPTY
;
469 /* msi auto clears the interrupt pending bit. */
470 if (unlikely(!(h
->pdev
->msi_enabled
|| h
->msix_vectors
))) {
471 /* flush the controller write of the reply queue by reading
472 * outbound doorbell status register.
474 (void) readl(h
->vaddr
+ SA5_OUTDB_STATUS
);
475 writel(SA5_OUTDB_CLEAR_PERF_BIT
, h
->vaddr
+ SA5_OUTDB_CLEAR
);
476 /* Do a read in order to flush the write to the controller
479 (void) readl(h
->vaddr
+ SA5_OUTDB_STATUS
);
482 if ((((u32
) rq
->head
[rq
->current_entry
]) & 1) == rq
->wraparound
) {
483 register_value
= rq
->head
[rq
->current_entry
];
485 atomic_dec(&h
->commands_outstanding
);
487 register_value
= FIFO_EMPTY
;
489 /* Check for wraparound */
490 if (rq
->current_entry
== h
->max_commands
) {
491 rq
->current_entry
= 0;
494 return register_value
;
498 * returns value read from hardware.
499 * returns FIFO_EMPTY if there is nothing to read
501 static unsigned long SA5_completed(struct ctlr_info
*h
,
502 __attribute__((unused
)) u8 q
)
504 unsigned long register_value
505 = readl(h
->vaddr
+ SA5_REPLY_PORT_OFFSET
);
507 if (register_value
!= FIFO_EMPTY
)
508 atomic_dec(&h
->commands_outstanding
);
511 if (register_value
!= FIFO_EMPTY
)
512 dev_dbg(&h
->pdev
->dev
, "Read %lx back from board\n",
515 dev_dbg(&h
->pdev
->dev
, "FIFO Empty read\n");
518 return register_value
;
521 * Returns true if an interrupt is pending..
523 static bool SA5_intr_pending(struct ctlr_info
*h
)
525 unsigned long register_value
=
526 readl(h
->vaddr
+ SA5_INTR_STATUS
);
527 return register_value
& SA5_INTR_PENDING
;
530 static bool SA5_performant_intr_pending(struct ctlr_info
*h
)
532 unsigned long register_value
= readl(h
->vaddr
+ SA5_INTR_STATUS
);
537 /* Read outbound doorbell to flush */
538 register_value
= readl(h
->vaddr
+ SA5_OUTDB_STATUS
);
539 return register_value
& SA5_OUTDB_STATUS_PERF_BIT
;
542 #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
544 static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info
*h
)
546 unsigned long register_value
= readl(h
->vaddr
+ SA5_INTR_STATUS
);
548 return (register_value
& SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT
) ?
552 #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
553 #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
554 #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
555 #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
557 static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info
*h
, u8 q
)
560 struct reply_queue_buffer
*rq
= &h
->reply_queue
[q
];
562 BUG_ON(q
>= h
->nreply_queues
);
564 register_value
= rq
->head
[rq
->current_entry
];
565 if (register_value
!= IOACCEL_MODE1_REPLY_UNUSED
) {
566 rq
->head
[rq
->current_entry
] = IOACCEL_MODE1_REPLY_UNUSED
;
567 if (++rq
->current_entry
== rq
->size
)
568 rq
->current_entry
= 0;
572 * Don't really need to write the new index after each command,
573 * but with current driver design this is easiest.
576 writel((q
<< 24) | rq
->current_entry
, h
->vaddr
+
577 IOACCEL_MODE1_CONSUMER_INDEX
);
578 atomic_dec(&h
->commands_outstanding
);
580 return (unsigned long) register_value
;
583 static struct access_method SA5_access
= {
584 .submit_command
= SA5_submit_command
,
585 .set_intr_mask
= SA5_intr_mask
,
586 .intr_pending
= SA5_intr_pending
,
587 .command_completed
= SA5_completed
,
590 static struct access_method SA5_ioaccel_mode1_access
= {
591 .submit_command
= SA5_submit_command
,
592 .set_intr_mask
= SA5_performant_intr_mask
,
593 .intr_pending
= SA5_ioaccel_mode1_intr_pending
,
594 .command_completed
= SA5_ioaccel_mode1_completed
,
597 static struct access_method SA5_ioaccel_mode2_access
= {
598 .submit_command
= SA5_submit_command_ioaccel2
,
599 .set_intr_mask
= SA5_performant_intr_mask
,
600 .intr_pending
= SA5_performant_intr_pending
,
601 .command_completed
= SA5_performant_completed
,
604 static struct access_method SA5_performant_access
= {
605 .submit_command
= SA5_submit_command
,
606 .set_intr_mask
= SA5_performant_intr_mask
,
607 .intr_pending
= SA5_performant_intr_pending
,
608 .command_completed
= SA5_performant_completed
,
611 static struct access_method SA5_performant_access_no_read
= {
612 .submit_command
= SA5_submit_command_no_read
,
613 .set_intr_mask
= SA5_performant_intr_mask
,
614 .intr_pending
= SA5_performant_intr_pending
,
615 .command_completed
= SA5_performant_completed
,
621 struct access_method
*access
;