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1 /*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21 #ifndef HPSA_H
22 #define HPSA_H
23
24 #include <scsi/scsicam.h>
25
26 #define IO_OK 0
27 #define IO_ERROR 1
28
29 struct ctlr_info;
30
31 struct access_method {
32 void (*submit_command)(struct ctlr_info *h,
33 struct CommandList *c);
34 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
35 bool (*intr_pending)(struct ctlr_info *h);
36 unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
37 };
38
39 struct hpsa_scsi_dev_t {
40 int devtype;
41 int bus, target, lun; /* as presented to the OS */
42 unsigned char scsi3addr[8]; /* as presented to the HW */
43 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
44 unsigned char device_id[16]; /* from inquiry pg. 0x83 */
45 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
46 unsigned char model[16]; /* bytes 16-31 of inquiry data */
47 unsigned char raid_level; /* from inquiry page 0xC1 */
48 unsigned char volume_offline; /* discovered via TUR or VPD */
49 u32 ioaccel_handle;
50 int offload_config; /* I/O accel RAID offload configured */
51 int offload_enabled; /* I/O accel RAID offload enabled */
52 int offload_to_mirror; /* Send next I/O accelerator RAID
53 * offload request to mirror drive
54 */
55 struct raid_map_data raid_map; /* I/O accelerator RAID map */
56
57 };
58
59 struct reply_queue_buffer {
60 u64 *head;
61 size_t size;
62 u8 wraparound;
63 u32 current_entry;
64 dma_addr_t busaddr;
65 };
66
67 #pragma pack(1)
68 struct bmic_controller_parameters {
69 u8 led_flags;
70 u8 enable_command_list_verification;
71 u8 backed_out_write_drives;
72 u16 stripes_for_parity;
73 u8 parity_distribution_mode_flags;
74 u16 max_driver_requests;
75 u16 elevator_trend_count;
76 u8 disable_elevator;
77 u8 force_scan_complete;
78 u8 scsi_transfer_mode;
79 u8 force_narrow;
80 u8 rebuild_priority;
81 u8 expand_priority;
82 u8 host_sdb_asic_fix;
83 u8 pdpi_burst_from_host_disabled;
84 char software_name[64];
85 char hardware_name[32];
86 u8 bridge_revision;
87 u8 snapshot_priority;
88 u32 os_specific;
89 u8 post_prompt_timeout;
90 u8 automatic_drive_slamming;
91 u8 reserved1;
92 u8 nvram_flags;
93 #define HBA_MODE_ENABLED_FLAG (1 << 3)
94 u8 cache_nvram_flags;
95 u8 drive_config_flags;
96 u16 reserved2;
97 u8 temp_warning_level;
98 u8 temp_shutdown_level;
99 u8 temp_condition_reset;
100 u8 max_coalesce_commands;
101 u32 max_coalesce_delay;
102 u8 orca_password[4];
103 u8 access_id[16];
104 u8 reserved[356];
105 };
106 #pragma pack()
107
108 struct ctlr_info {
109 int ctlr;
110 char devname[8];
111 char *product_name;
112 struct pci_dev *pdev;
113 u32 board_id;
114 void __iomem *vaddr;
115 unsigned long paddr;
116 int nr_cmds; /* Number of commands allowed on this controller */
117 #define HPSA_CMDS_RESERVED_FOR_ABORTS 2
118 #define HPSA_CMDS_RESERVED_FOR_DRIVER 1
119 struct CfgTable __iomem *cfgtable;
120 int interrupts_enabled;
121 int max_commands;
122 atomic_t commands_outstanding;
123 # define PERF_MODE_INT 0
124 # define DOORBELL_INT 1
125 # define SIMPLE_MODE_INT 2
126 # define MEMQ_MODE_INT 3
127 unsigned int intr[MAX_REPLY_QUEUES];
128 unsigned int msix_vector;
129 unsigned int msi_vector;
130 int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
131 struct access_method access;
132 char hba_mode_enabled;
133
134 /* queue and queue Info */
135 unsigned int Qdepth;
136 unsigned int maxSG;
137 spinlock_t lock;
138 int maxsgentries;
139 u8 max_cmd_sg_entries;
140 int chainsize;
141 struct SGDescriptor **cmd_sg_list;
142
143 /* pointers to command and error info pool */
144 struct CommandList *cmd_pool;
145 dma_addr_t cmd_pool_dhandle;
146 struct io_accel1_cmd *ioaccel_cmd_pool;
147 dma_addr_t ioaccel_cmd_pool_dhandle;
148 struct io_accel2_cmd *ioaccel2_cmd_pool;
149 dma_addr_t ioaccel2_cmd_pool_dhandle;
150 struct ErrorInfo *errinfo_pool;
151 dma_addr_t errinfo_pool_dhandle;
152 unsigned long *cmd_pool_bits;
153 int scan_finished;
154 spinlock_t scan_lock;
155 wait_queue_head_t scan_wait_queue;
156
157 struct Scsi_Host *scsi_host;
158 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
159 int ndevices; /* number of used elements in .dev[] array. */
160 struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
161 /*
162 * Performant mode tables.
163 */
164 u32 trans_support;
165 u32 trans_offset;
166 struct TransTable_struct __iomem *transtable;
167 unsigned long transMethod;
168
169 /* cap concurrent passthrus at some reasonable maximum */
170 #define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
171 spinlock_t passthru_count_lock; /* protects passthru_count */
172 int passthru_count;
173
174 /*
175 * Performant mode completion buffers
176 */
177 size_t reply_queue_size;
178 struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
179 u8 nreply_queues;
180 u32 *blockFetchTable;
181 u32 *ioaccel1_blockFetchTable;
182 u32 *ioaccel2_blockFetchTable;
183 u32 __iomem *ioaccel2_bft2_regs;
184 unsigned char *hba_inquiry_data;
185 u32 driver_support;
186 u32 fw_support;
187 int ioaccel_support;
188 int ioaccel_maxsg;
189 u64 last_intr_timestamp;
190 u32 last_heartbeat;
191 u64 last_heartbeat_timestamp;
192 u32 heartbeat_sample_interval;
193 atomic_t firmware_flash_in_progress;
194 u32 __percpu *lockup_detected;
195 struct delayed_work monitor_ctlr_work;
196 int remove_in_progress;
197 /* Address of h->q[x] is passed to intr handler to know which queue */
198 u8 q[MAX_REPLY_QUEUES];
199 u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
200 #define HPSATMF_BITS_SUPPORTED (1 << 0)
201 #define HPSATMF_PHYS_LUN_RESET (1 << 1)
202 #define HPSATMF_PHYS_NEX_RESET (1 << 2)
203 #define HPSATMF_PHYS_TASK_ABORT (1 << 3)
204 #define HPSATMF_PHYS_TSET_ABORT (1 << 4)
205 #define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
206 #define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
207 #define HPSATMF_PHYS_QRY_TASK (1 << 7)
208 #define HPSATMF_PHYS_QRY_TSET (1 << 8)
209 #define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
210 #define HPSATMF_MASK_SUPPORTED (1 << 16)
211 #define HPSATMF_LOG_LUN_RESET (1 << 17)
212 #define HPSATMF_LOG_NEX_RESET (1 << 18)
213 #define HPSATMF_LOG_TASK_ABORT (1 << 19)
214 #define HPSATMF_LOG_TSET_ABORT (1 << 20)
215 #define HPSATMF_LOG_CLEAR_ACA (1 << 21)
216 #define HPSATMF_LOG_CLEAR_TSET (1 << 22)
217 #define HPSATMF_LOG_QRY_TASK (1 << 23)
218 #define HPSATMF_LOG_QRY_TSET (1 << 24)
219 #define HPSATMF_LOG_QRY_ASYNC (1 << 25)
220 u32 events;
221 #define CTLR_STATE_CHANGE_EVENT (1 << 0)
222 #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
223 #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
224 #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
225 #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
226 #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
227 #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
228
229 #define RESCAN_REQUIRED_EVENT_BITS \
230 (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
231 CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
232 CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
233 CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
234 CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
235 spinlock_t offline_device_lock;
236 struct list_head offline_device_list;
237 int acciopath_status;
238 int drv_req_rescan; /* flag for driver to request rescan event */
239 int raid_offload_debug;
240 };
241
242 struct offline_device_entry {
243 unsigned char scsi3addr[8];
244 struct list_head offline_list;
245 };
246
247 #define HPSA_ABORT_MSG 0
248 #define HPSA_DEVICE_RESET_MSG 1
249 #define HPSA_RESET_TYPE_CONTROLLER 0x00
250 #define HPSA_RESET_TYPE_BUS 0x01
251 #define HPSA_RESET_TYPE_TARGET 0x03
252 #define HPSA_RESET_TYPE_LUN 0x04
253 #define HPSA_MSG_SEND_RETRY_LIMIT 10
254 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
255
256 /* Maximum time in seconds driver will wait for command completions
257 * when polling before giving up.
258 */
259 #define HPSA_MAX_POLL_TIME_SECS (20)
260
261 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
262 * how many times to retry TEST UNIT READY on a device
263 * while waiting for it to become ready before giving up.
264 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
265 * between sending TURs while waiting for a device
266 * to become ready.
267 */
268 #define HPSA_TUR_RETRY_LIMIT (20)
269 #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
270
271 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
272 * to become ready, in seconds, before giving up on it.
273 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
274 * between polling the board to see if it is ready, in
275 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
276 * HPSA_BOARD_READY_ITERATIONS are derived from those.
277 */
278 #define HPSA_BOARD_READY_WAIT_SECS (120)
279 #define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
280 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
281 #define HPSA_BOARD_READY_POLL_INTERVAL \
282 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
283 #define HPSA_BOARD_READY_ITERATIONS \
284 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
285 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
286 #define HPSA_BOARD_NOT_READY_ITERATIONS \
287 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
288 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
289 #define HPSA_POST_RESET_PAUSE_MSECS (3000)
290 #define HPSA_POST_RESET_NOOP_RETRIES (12)
291
292 /* Defining the diffent access_menthods */
293 /*
294 * Memory mapped FIFO interface (SMART 53xx cards)
295 */
296 #define SA5_DOORBELL 0x20
297 #define SA5_REQUEST_PORT_OFFSET 0x40
298 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
299 #define SA5_REPLY_PORT_OFFSET 0x44
300 #define SA5_INTR_STATUS 0x30
301 #define SA5_SCRATCHPAD_OFFSET 0xB0
302
303 #define SA5_CTCFG_OFFSET 0xB4
304 #define SA5_CTMEM_OFFSET 0xB8
305
306 #define SA5_INTR_OFF 0x08
307 #define SA5B_INTR_OFF 0x04
308 #define SA5_INTR_PENDING 0x08
309 #define SA5B_INTR_PENDING 0x04
310 #define FIFO_EMPTY 0xffffffff
311 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
312
313 #define HPSA_ERROR_BIT 0x02
314
315 /* Performant mode flags */
316 #define SA5_PERF_INTR_PENDING 0x04
317 #define SA5_PERF_INTR_OFF 0x05
318 #define SA5_OUTDB_STATUS_PERF_BIT 0x01
319 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
320 #define SA5_OUTDB_CLEAR 0xA0
321 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
322 #define SA5_OUTDB_STATUS 0x9C
323
324
325 #define HPSA_INTR_ON 1
326 #define HPSA_INTR_OFF 0
327
328 /*
329 * Inbound Post Queue offsets for IO Accelerator Mode 2
330 */
331 #define IOACCEL2_INBOUND_POSTQ_32 0x48
332 #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
333 #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
334
335 /*
336 Send the command to the hardware
337 */
338 static void SA5_submit_command(struct ctlr_info *h,
339 struct CommandList *c)
340 {
341 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
342 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
343 }
344
345 static void SA5_submit_command_no_read(struct ctlr_info *h,
346 struct CommandList *c)
347 {
348 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
349 }
350
351 static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
352 struct CommandList *c)
353 {
354 if (c->cmd_type == CMD_IOACCEL2)
355 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
356 else
357 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
358 }
359
360 /*
361 * This card is the opposite of the other cards.
362 * 0 turns interrupts on...
363 * 0x08 turns them off...
364 */
365 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
366 {
367 if (val) { /* Turn interrupts on */
368 h->interrupts_enabled = 1;
369 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
370 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
371 } else { /* Turn them off */
372 h->interrupts_enabled = 0;
373 writel(SA5_INTR_OFF,
374 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
375 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
376 }
377 }
378
379 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
380 {
381 if (val) { /* turn on interrupts */
382 h->interrupts_enabled = 1;
383 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
384 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
385 } else {
386 h->interrupts_enabled = 0;
387 writel(SA5_PERF_INTR_OFF,
388 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
389 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
390 }
391 }
392
393 static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
394 {
395 struct reply_queue_buffer *rq = &h->reply_queue[q];
396 unsigned long register_value = FIFO_EMPTY;
397
398 /* msi auto clears the interrupt pending bit. */
399 if (!(h->msi_vector || h->msix_vector)) {
400 /* flush the controller write of the reply queue by reading
401 * outbound doorbell status register.
402 */
403 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
404 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
405 /* Do a read in order to flush the write to the controller
406 * (as per spec.)
407 */
408 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
409 }
410
411 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
412 register_value = rq->head[rq->current_entry];
413 rq->current_entry++;
414 atomic_dec(&h->commands_outstanding);
415 } else {
416 register_value = FIFO_EMPTY;
417 }
418 /* Check for wraparound */
419 if (rq->current_entry == h->max_commands) {
420 rq->current_entry = 0;
421 rq->wraparound ^= 1;
422 }
423 return register_value;
424 }
425
426 /*
427 * returns value read from hardware.
428 * returns FIFO_EMPTY if there is nothing to read
429 */
430 static unsigned long SA5_completed(struct ctlr_info *h,
431 __attribute__((unused)) u8 q)
432 {
433 unsigned long register_value
434 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
435
436 if (register_value != FIFO_EMPTY)
437 atomic_dec(&h->commands_outstanding);
438
439 #ifdef HPSA_DEBUG
440 if (register_value != FIFO_EMPTY)
441 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
442 register_value);
443 else
444 dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
445 #endif
446
447 return register_value;
448 }
449 /*
450 * Returns true if an interrupt is pending..
451 */
452 static bool SA5_intr_pending(struct ctlr_info *h)
453 {
454 unsigned long register_value =
455 readl(h->vaddr + SA5_INTR_STATUS);
456 return register_value & SA5_INTR_PENDING;
457 }
458
459 static bool SA5_performant_intr_pending(struct ctlr_info *h)
460 {
461 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
462
463 if (!register_value)
464 return false;
465
466 if (h->msi_vector || h->msix_vector)
467 return true;
468
469 /* Read outbound doorbell to flush */
470 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
471 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
472 }
473
474 #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
475
476 static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
477 {
478 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
479
480 return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
481 true : false;
482 }
483
484 #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
485 #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
486 #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
487 #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
488
489 static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
490 {
491 u64 register_value;
492 struct reply_queue_buffer *rq = &h->reply_queue[q];
493
494 BUG_ON(q >= h->nreply_queues);
495
496 register_value = rq->head[rq->current_entry];
497 if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
498 rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
499 if (++rq->current_entry == rq->size)
500 rq->current_entry = 0;
501 /*
502 * @todo
503 *
504 * Don't really need to write the new index after each command,
505 * but with current driver design this is easiest.
506 */
507 wmb();
508 writel((q << 24) | rq->current_entry, h->vaddr +
509 IOACCEL_MODE1_CONSUMER_INDEX);
510 atomic_dec(&h->commands_outstanding);
511 }
512 return (unsigned long) register_value;
513 }
514
515 static struct access_method SA5_access = {
516 SA5_submit_command,
517 SA5_intr_mask,
518 SA5_intr_pending,
519 SA5_completed,
520 };
521
522 static struct access_method SA5_ioaccel_mode1_access = {
523 SA5_submit_command,
524 SA5_performant_intr_mask,
525 SA5_ioaccel_mode1_intr_pending,
526 SA5_ioaccel_mode1_completed,
527 };
528
529 static struct access_method SA5_ioaccel_mode2_access = {
530 SA5_submit_command_ioaccel2,
531 SA5_performant_intr_mask,
532 SA5_performant_intr_pending,
533 SA5_performant_completed,
534 };
535
536 static struct access_method SA5_performant_access = {
537 SA5_submit_command,
538 SA5_performant_intr_mask,
539 SA5_performant_intr_pending,
540 SA5_performant_completed,
541 };
542
543 static struct access_method SA5_performant_access_no_read = {
544 SA5_submit_command_no_read,
545 SA5_performant_intr_mask,
546 SA5_performant_intr_pending,
547 SA5_performant_completed,
548 };
549
550 struct board_type {
551 u32 board_id;
552 char *product_name;
553 struct access_method *access;
554 };
555
556 #endif /* HPSA_H */
557
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