drivers/scsi/hpsa_cmd.h

   1 /*
   2  *    Disk Array driver for HP Smart Array SAS controllers
   3  *    Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
   4  *
   5  *    This program is free software; you can redistribute it and/or modify
   6  *    it under the terms of the GNU General Public License as published by
   7  *    the Free Software Foundation; version 2 of the License.
   8  *
   9  *    This program is distributed in the hope that it will be useful,
  10  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  12  *    NON INFRINGEMENT.  See the GNU General Public License for more details.
  13  *
  14  *    You should have received a copy of the GNU General Public License
  15  *    along with this program; if not, write to the Free Software
  16  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  *
  18  *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
  19  *
  20  */
  21 #ifndef HPSA_CMD_H
  22 #define HPSA_CMD_H
  23
  24 /* general boundary defintions */
  25 #define SENSEINFOBYTES          32 /* may vary between hbas */
  26 #define SG_ENTRIES_IN_CMD       32 /* Max SG entries excluding chain blocks */
  27 #define HPSA_SG_CHAIN           0x80000000
  28 #define HPSA_SG_LAST            0x40000000
  29 #define MAXREPLYQS              256
  30
  31 /* Command Status value */
  32 #define CMD_SUCCESS             0x0000
  33 #define CMD_TARGET_STATUS       0x0001
  34 #define CMD_DATA_UNDERRUN       0x0002
  35 #define CMD_DATA_OVERRUN        0x0003
  36 #define CMD_INVALID             0x0004
  37 #define CMD_PROTOCOL_ERR        0x0005
  38 #define CMD_HARDWARE_ERR        0x0006
  39 #define CMD_CONNECTION_LOST     0x0007
  40 #define CMD_ABORTED             0x0008
  41 #define CMD_ABORT_FAILED        0x0009
  42 #define CMD_UNSOLICITED_ABORT   0x000A
  43 #define CMD_TIMEOUT             0x000B
  44 #define CMD_UNABORTABLE         0x000C
  45 #define CMD_IOACCEL_DISABLED    0x000E
  46
  47
  48 /* Unit Attentions ASC's as defined for the MSA2012sa */
  49 #define POWER_OR_RESET                  0x29
  50 #define STATE_CHANGED                   0x2a
  51 #define UNIT_ATTENTION_CLEARED          0x2f
  52 #define LUN_FAILED                      0x3e
  53 #define REPORT_LUNS_CHANGED             0x3f
  54
  55 /* Unit Attentions ASCQ's as defined for the MSA2012sa */
  56
  57         /* These ASCQ's defined for ASC = POWER_OR_RESET */
  58 #define POWER_ON_RESET                  0x00
  59 #define POWER_ON_REBOOT                 0x01
  60 #define SCSI_BUS_RESET                  0x02
  61 #define MSA_TARGET_RESET                0x03
  62 #define CONTROLLER_FAILOVER             0x04
  63 #define TRANSCEIVER_SE                  0x05
  64 #define TRANSCEIVER_LVD                 0x06
  65
  66         /* These ASCQ's defined for ASC = STATE_CHANGED */
  67 #define RESERVATION_PREEMPTED           0x03
  68 #define ASYM_ACCESS_CHANGED             0x06
  69 #define LUN_CAPACITY_CHANGED            0x09
  70
  71 /* transfer direction */
  72 #define XFER_NONE               0x00
  73 #define XFER_WRITE              0x01
  74 #define XFER_READ               0x02
  75 #define XFER_RSVD               0x03
  76
  77 /* task attribute */
  78 #define ATTR_UNTAGGED           0x00
  79 #define ATTR_SIMPLE             0x04
  80 #define ATTR_HEADOFQUEUE        0x05
  81 #define ATTR_ORDERED            0x06
  82 #define ATTR_ACA                0x07
  83
  84 /* cdb type */
  85 #define TYPE_CMD                0x00
  86 #define TYPE_MSG                0x01
  87 #define TYPE_IOACCEL2_CMD       0x81 /* 0x81 is not used by hardware */
  88
  89 /* Message Types  */
  90 #define HPSA_TASK_MANAGEMENT    0x00
  91 #define HPSA_RESET              0x01
  92 #define HPSA_SCAN               0x02
  93 #define HPSA_NOOP               0x03
  94
  95 #define HPSA_CTLR_RESET_TYPE    0x00
  96 #define HPSA_BUS_RESET_TYPE     0x01
  97 #define HPSA_TARGET_RESET_TYPE  0x03
  98 #define HPSA_LUN_RESET_TYPE     0x04
  99 #define HPSA_NEXUS_RESET_TYPE   0x05
 100
 101 /* Task Management Functions */
 102 #define HPSA_TMF_ABORT_TASK     0x00
 103 #define HPSA_TMF_ABORT_TASK_SET 0x01
 104 #define HPSA_TMF_CLEAR_ACA      0x02
 105 #define HPSA_TMF_CLEAR_TASK_SET 0x03
 106 #define HPSA_TMF_QUERY_TASK     0x04
 107 #define HPSA_TMF_QUERY_TASK_SET 0x05
 108 #define HPSA_TMF_QUERY_ASYNCEVENT 0x06
 109
 110
 111
 112 /* config space register offsets */
 113 #define CFG_VENDORID            0x00
 114 #define CFG_DEVICEID            0x02
 115 #define CFG_I2OBAR              0x10
 116 #define CFG_MEM1BAR             0x14
 117
 118 /* i2o space register offsets */
 119 #define I2O_IBDB_SET            0x20
 120 #define I2O_IBDB_CLEAR          0x70
 121 #define I2O_INT_STATUS          0x30
 122 #define I2O_INT_MASK            0x34
 123 #define I2O_IBPOST_Q            0x40
 124 #define I2O_OBPOST_Q            0x44
 125 #define I2O_DMA1_CFG            0x214
 126
 127 /* Configuration Table */
 128 #define CFGTBL_ChangeReq        0x00000001l
 129 #define CFGTBL_AccCmds          0x00000001l
 130 #define DOORBELL_CTLR_RESET     0x00000004l
 131 #define DOORBELL_CTLR_RESET2    0x00000020l
 132 #define DOORBELL_CLEAR_EVENTS   0x00000040l
 133
 134 #define CFGTBL_Trans_Simple     0x00000002l
 135 #define CFGTBL_Trans_Performant 0x00000004l
 136 #define CFGTBL_Trans_io_accel1  0x00000080l
 137 #define CFGTBL_Trans_io_accel2  0x00000100l
 138 #define CFGTBL_Trans_use_short_tags 0x20000000l
 139 #define CFGTBL_Trans_enable_directed_msix (1 << 30)
 140
 141 #define CFGTBL_BusType_Ultra2   0x00000001l
 142 #define CFGTBL_BusType_Ultra3   0x00000002l
 143 #define CFGTBL_BusType_Fibre1G  0x00000100l
 144 #define CFGTBL_BusType_Fibre2G  0x00000200l
 145
 146 /* VPD Inquiry types */
 147 #define HPSA_VPD_SUPPORTED_PAGES        0x00
 148 #define HPSA_VPD_LV_DEVICE_GEOMETRY     0xC1
 149 #define HPSA_VPD_LV_IOACCEL_STATUS      0xC2
 150 #define HPSA_VPD_LV_STATUS              0xC3
 151 #define HPSA_VPD_HEADER_SZ              4
 152
 153 /* Logical volume states */
 154 #define HPSA_VPD_LV_STATUS_UNSUPPORTED                  -1
 155 #define HPSA_LV_OK                                      0x0
 156 #define HPSA_LV_UNDERGOING_ERASE                        0x0F
 157 #define HPSA_LV_UNDERGOING_RPI                          0x12
 158 #define HPSA_LV_PENDING_RPI                             0x13
 159 #define HPSA_LV_ENCRYPTED_NO_KEY                        0x14
 160 #define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER    0x15
 161 #define HPSA_LV_UNDERGOING_ENCRYPTION                   0x16
 162 #define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING          0x17
 163 #define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER   0x18
 164 #define HPSA_LV_PENDING_ENCRYPTION                      0x19
 165 #define HPSA_LV_PENDING_ENCRYPTION_REKEYING             0x1A
 166
 167 struct vals32 {
 168         u32   lower;
 169         u32   upper;
 170 };
 171
 172 union u64bit {
 173         struct vals32 val32;
 174         u64 val;
 175 };
 176
 177 /* FIXME this is a per controller value (barf!) */
 178 #define HPSA_MAX_LUN 1024
 179 #define HPSA_MAX_PHYS_LUN 1024
 180 #define MAX_EXT_TARGETS 32
 181 #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
 182         MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
 183
 184 /* SCSI-3 Commands */
 185 #pragma pack(1)
 186
 187 #define HPSA_INQUIRY 0x12
 188 struct InquiryData {
 189         u8 data_byte[36];
 190 };
 191
 192 #define HPSA_REPORT_LOG 0xc2    /* Report Logical LUNs */
 193 #define HPSA_REPORT_PHYS 0xc3   /* Report Physical LUNs */
 194 #define HPSA_REPORT_PHYS_EXTENDED 0x02
 195 #define HPSA_CISS_READ  0xc0    /* CISS Read */
 196 #define HPSA_GET_RAID_MAP 0xc8  /* CISS Get RAID Layout Map */
 197
 198 #define RAID_MAP_MAX_ENTRIES   256
 199
 200 struct raid_map_disk_data {
 201         u32   ioaccel_handle;         /**< Handle to access this disk via the
 202                                         *  I/O accelerator */
 203         u8    xor_mult[2];            /**< XOR multipliers for this position,
 204                                         *  valid for data disks only */
 205         u8    reserved[2];
 206 };
 207
 208 struct raid_map_data {
 209         u32   structure_size;           /* Size of entire structure in bytes */
 210         u32   volume_blk_size;          /* bytes / block in the volume */
 211         u64   volume_blk_cnt;           /* logical blocks on the volume */
 212         u8    phys_blk_shift;           /* Shift factor to convert between
 213                                          * units of logical blocks and physical
 214                                          * disk blocks */
 215         u8    parity_rotation_shift;    /* Shift factor to convert between units
 216                                          * of logical stripes and physical
 217                                          * stripes */
 218         u16   strip_size;               /* blocks used on each disk / stripe */
 219         u64   disk_starting_blk;        /* First disk block used in volume */
 220         u64   disk_blk_cnt;             /* disk blocks used by volume / disk */
 221         u16   data_disks_per_row;       /* data disk entries / row in the map */
 222         u16   metadata_disks_per_row;   /* mirror/parity disk entries / row
 223                                          * in the map */
 224         u16   row_cnt;                  /* rows in each layout map */
 225         u16   layout_map_count;         /* layout maps (1 map per mirror/parity
 226                                          * group) */
 227         u16   flags;                    /* Bit 0 set if encryption enabled */
 228 #define RAID_MAP_FLAG_ENCRYPT_ON  0x01
 229         u16   dekindex;                 /* Data encryption key index. */
 230         u8    reserved[16];
 231         struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES];
 232 };
 233
 234 struct ReportLUNdata {
 235         u8 LUNListLength[4];
 236         u8 extended_response_flag;
 237         u8 reserved[3];
 238         u8 LUN[HPSA_MAX_LUN][8];
 239 };
 240
 241 struct ReportExtendedLUNdata {
 242         u8 LUNListLength[4];
 243         u8 extended_response_flag;
 244         u8 reserved[3];
 245         u8 LUN[HPSA_MAX_LUN][24];
 246 };
 247
 248 struct SenseSubsystem_info {
 249         u8 reserved[36];
 250         u8 portname[8];
 251         u8 reserved1[1108];
 252 };
 253
 254 /* BMIC commands */
 255 #define BMIC_READ 0x26
 256 #define BMIC_WRITE 0x27
 257 #define BMIC_CACHE_FLUSH 0xc2
 258 #define HPSA_CACHE_FLUSH 0x01   /* C2 was already being used by HPSA */
 259 #define BMIC_FLASH_FIRMWARE 0xF7
 260 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
 261
 262 /* Command List Structure */
 263 union SCSI3Addr {
 264         struct {
 265                 u8 Dev;
 266                 u8 Bus:6;
 267                 u8 Mode:2;        /* b00 */
 268         } PeripDev;
 269         struct {
 270                 u8 DevLSB;
 271                 u8 DevMSB:6;
 272                 u8 Mode:2;        /* b01 */
 273         } LogDev;
 274         struct {
 275                 u8 Dev:5;
 276                 u8 Bus:3;
 277                 u8 Targ:6;
 278                 u8 Mode:2;        /* b10 */
 279         } LogUnit;
 280 };
 281
 282 struct PhysDevAddr {
 283         u32             TargetId:24;
 284         u32             Bus:6;
 285         u32             Mode:2;
 286         /* 2 level target device addr */
 287         union SCSI3Addr  Target[2];
 288 };
 289
 290 struct LogDevAddr {
 291         u32            VolId:30;
 292         u32            Mode:2;
 293         u8             reserved[4];
 294 };
 295
 296 union LUNAddr {
 297         u8               LunAddrBytes[8];
 298         union SCSI3Addr    SCSI3Lun[4];
 299         struct PhysDevAddr PhysDev;
 300         struct LogDevAddr  LogDev;
 301 };
 302
 303 struct CommandListHeader {
 304         u8              ReplyQueue;
 305         u8              SGList;
 306         u16             SGTotal;
 307         struct vals32     Tag;
 308         union LUNAddr     LUN;
 309 };
 310
 311 struct RequestBlock {
 312         u8   CDBLen;
 313         struct {
 314                 u8 Type:3;
 315                 u8 Attribute:3;
 316                 u8 Direction:2;
 317         } Type;
 318         u16  Timeout;
 319         u8   CDB[16];
 320 };
 321
 322 struct ErrDescriptor {
 323         struct vals32 Addr;
 324         u32  Len;
 325 };
 326
 327 struct SGDescriptor {
 328         struct vals32 Addr;
 329         u32  Len;
 330         u32  Ext;
 331 };
 332
 333 union MoreErrInfo {
 334         struct {
 335                 u8  Reserved[3];
 336                 u8  Type;
 337                 u32 ErrorInfo;
 338         } Common_Info;
 339         struct {
 340                 u8  Reserved[2];
 341                 u8  offense_size; /* size of offending entry */
 342                 u8  offense_num;  /* byte # of offense 0-base */
 343                 u32 offense_value;
 344         } Invalid_Cmd;
 345 };
 346 struct ErrorInfo {
 347         u8               ScsiStatus;
 348         u8               SenseLen;
 349         u16              CommandStatus;
 350         u32              ResidualCnt;
 351         union MoreErrInfo  MoreErrInfo;
 352         u8               SenseInfo[SENSEINFOBYTES];
 353 };
 354 /* Command types */
 355 #define CMD_IOCTL_PEND  0x01
 356 #define CMD_SCSI        0x03
 357 #define CMD_IOACCEL1    0x04
 358 #define CMD_IOACCEL2    0x05
 359
 360 #define DIRECT_LOOKUP_SHIFT 5
 361 #define DIRECT_LOOKUP_BIT 0x10
 362 #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
 363
 364 #define HPSA_ERROR_BIT          0x02
 365 struct ctlr_info; /* defined in hpsa.h */
 366 /* The size of this structure needs to be divisible by 32
 367  * on all architectures because low 5 bits of the addresses
 368  * are used as follows:
 369  *
 370  * bit 0: to device, used to indicate "performant mode" command
 371  *        from device, indidcates error status.
 372  * bit 1-3: to device, indicates block fetch table entry for
 373  *          reducing DMA in fetching commands from host memory.
 374  * bit 4: used to indicate whether tag is "direct lookup" (index),
 375  *        or a bus address.
 376  */
 377
 378 struct CommandList {
 379         struct CommandListHeader Header;
 380         struct RequestBlock      Request;
 381         struct ErrDescriptor     ErrDesc;
 382         struct SGDescriptor      SG[SG_ENTRIES_IN_CMD];
 383         /* information associated with the command */
 384         u32                        busaddr; /* physical addr of this record */
 385         struct ErrorInfo *err_info; /* pointer to the allocated mem */
 386         struct ctlr_info           *h;
 387         int                        cmd_type;
 388         long                       cmdindex;
 389         struct list_head list;
 390         struct completion *waiting;
 391         void   *scsi_cmd;
 392
 393 /* on 64 bit architectures, to get this to be 32-byte-aligned
 394  * it so happens we need PAD_64 bytes of padding, on 32 bit systems,
 395  * we need PAD_32 bytes of padding (see below).   This does that.
 396  * If it happens that 64 bit and 32 bit systems need different
 397  * padding, PAD_32 and PAD_64 can be set independently, and.
 398  * the code below will do the right thing.
 399  */
 400 #define IS_32_BIT ((8 - sizeof(long))/4)
 401 #define IS_64_BIT (!IS_32_BIT)
 402 #define PAD_32 (40)
 403 #define PAD_64 (12)
 404 #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
 405         u8 pad[COMMANDLIST_PAD];
 406 };
 407
 408 /* Max S/G elements in I/O accelerator command */
 409 #define IOACCEL1_MAXSGENTRIES           24
 410 #define IOACCEL2_MAXSGENTRIES           28
 411
 412 /*
 413  * Structure for I/O accelerator (mode 1) commands.
 414  * Note that this structure must be 128-byte aligned in size.
 415  */
 416 struct io_accel1_cmd {
 417         u16 dev_handle;                 /* 0x00 - 0x01 */
 418         u8  reserved1;                  /* 0x02 */
 419         u8  function;                   /* 0x03 */
 420         u8  reserved2[8];               /* 0x04 - 0x0B */
 421         u32 err_info;                   /* 0x0C - 0x0F */
 422         u8  reserved3[2];               /* 0x10 - 0x11 */
 423         u8  err_info_len;               /* 0x12 */
 424         u8  reserved4;                  /* 0x13 */
 425         u8  sgl_offset;                 /* 0x14 */
 426         u8  reserved5[7];               /* 0x15 - 0x1B */
 427         u32 transfer_len;               /* 0x1C - 0x1F */
 428         u8  reserved6[4];               /* 0x20 - 0x23 */
 429         u16 io_flags;                   /* 0x24 - 0x25 */
 430         u8  reserved7[14];              /* 0x26 - 0x33 */
 431         u8  LUN[8];                     /* 0x34 - 0x3B */
 432         u32 control;                    /* 0x3C - 0x3F */
 433         u8  CDB[16];                    /* 0x40 - 0x4F */
 434         u8  reserved8[16];              /* 0x50 - 0x5F */
 435         u16 host_context_flags;         /* 0x60 - 0x61 */
 436         u16 timeout_sec;                /* 0x62 - 0x63 */
 437         u8  ReplyQueue;                 /* 0x64 */
 438         u8  reserved9[3];               /* 0x65 - 0x67 */
 439         struct vals32 Tag;              /* 0x68 - 0x6F */
 440         struct vals32 host_addr;        /* 0x70 - 0x77 */
 441         u8  CISS_LUN[8];                /* 0x78 - 0x7F */
 442         struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES];
 443 #define IOACCEL1_PAD_64 0
 444 #define IOACCEL1_PAD_32 0
 445 #define IOACCEL1_PAD (IS_32_BIT * IOACCEL1_PAD_32 + \
 446                         IS_64_BIT * IOACCEL1_PAD_64)
 447         u8 pad[IOACCEL1_PAD];
 448 };
 449
 450 #define IOACCEL1_FUNCTION_SCSIIO        0x00
 451 #define IOACCEL1_SGLOFFSET              32
 452
 453 #define IOACCEL1_IOFLAGS_IO_REQ         0x4000
 454 #define IOACCEL1_IOFLAGS_CDBLEN_MASK    0x001F
 455 #define IOACCEL1_IOFLAGS_CDBLEN_MAX     16
 456
 457 #define IOACCEL1_CONTROL_NODATAXFER     0x00000000
 458 #define IOACCEL1_CONTROL_DATA_OUT       0x01000000
 459 #define IOACCEL1_CONTROL_DATA_IN        0x02000000
 460 #define IOACCEL1_CONTROL_TASKPRIO_MASK  0x00007800
 461 #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11
 462 #define IOACCEL1_CONTROL_SIMPLEQUEUE    0x00000000
 463 #define IOACCEL1_CONTROL_HEADOFQUEUE    0x00000100
 464 #define IOACCEL1_CONTROL_ORDEREDQUEUE   0x00000200
 465 #define IOACCEL1_CONTROL_ACA            0x00000400
 466
 467 #define IOACCEL1_HCFLAGS_CISS_FORMAT    0x0013
 468
 469 #define IOACCEL1_BUSADDR_CMDTYPE        0x00000060
 470
 471 struct ioaccel2_sg_element {
 472         u64 address;
 473         u32 length;
 474         u8 reserved[3];
 475         u8 chain_indicator;
 476 #define IOACCEL2_CHAIN 0x80
 477 };
 478
 479 /*
 480  * SCSI Response Format structure for IO Accelerator Mode 2
 481  */
 482 struct io_accel2_scsi_response {
 483         u8 IU_type;
 484 #define IOACCEL2_IU_TYPE_SRF                    0x60
 485         u8 reserved1[3];
 486         u8 req_id[4];           /* request identifier */
 487         u8 reserved2[4];
 488         u8 serv_response;               /* service response */
 489 #define IOACCEL2_SERV_RESPONSE_COMPLETE         0x000
 490 #define IOACCEL2_SERV_RESPONSE_FAILURE          0x001
 491 #define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE     0x002
 492 #define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS      0x003
 493 #define IOACCEL2_SERV_RESPONSE_TMF_REJECTED     0x004
 494 #define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN    0x005
 495         u8 status;                      /* status */
 496 #define IOACCEL2_STATUS_SR_TASK_COMP_GOOD       0x00
 497 #define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND   0x02
 498 #define IOACCEL2_STATUS_SR_TASK_COMP_BUSY       0x08
 499 #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON    0x18
 500 #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL   0x28
 501 #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED    0x40
 502 #define IOACCEL2_STATUS_SR_IOACCEL_DISABLED     0x0E
 503         u8 data_present;                /* low 2 bits */
 504 #define IOACCEL2_NO_DATAPRESENT         0x000
 505 #define IOACCEL2_RESPONSE_DATAPRESENT   0x001
 506 #define IOACCEL2_SENSE_DATA_PRESENT     0x002
 507 #define IOACCEL2_RESERVED               0x003
 508         u8 sense_data_len;              /* sense/response data length */
 509         u8 resid_cnt[4];                /* residual count */
 510         u8 sense_data_buff[32];         /* sense/response data buffer */
 511 };
 512
 513 #define IOACCEL2_64_PAD 76
 514 #define IOACCEL2_32_PAD 76
 515 #define IOACCEL2_PAD (IS_32_BIT * IOACCEL2_32_PAD + \
 516                         IS_64_BIT * IOACCEL2_64_PAD)
 517 /*
 518  * Structure for I/O accelerator (mode 2 or m2) commands.
 519  * Note that this structure must be 128-byte aligned in size.
 520  */
 521 struct io_accel2_cmd {
 522         u8  IU_type;                    /* IU Type */
 523         u8  direction;                  /* direction, memtype, and encryption */
 524 #define IOACCEL2_DIRECTION_MASK         0x03 /* bits 0,1: direction  */
 525 #define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */
 526                                              /*     0b=PCIe, 1b=DDR */
 527 #define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */
 528                                              /*     0=off, 1=on */
 529         u8  reply_queue;                /* Reply Queue ID */
 530         u8  reserved1;                  /* Reserved */
 531         u32 scsi_nexus;                 /* Device Handle */
 532         u32 Tag;                        /* cciss tag, lower 4 bytes only */
 533         u32 tweak_lower;                /* Encryption tweak, lower 4 bytes */
 534         u8  cdb[16];                    /* SCSI Command Descriptor Block */
 535         u8  cciss_lun[8];               /* 8 byte SCSI address */
 536         u32 data_len;                   /* Total bytes to transfer */
 537         u8  cmd_priority_task_attr;     /* priority and task attrs */
 538 #define IOACCEL2_PRIORITY_MASK 0x78
 539 #define IOACCEL2_ATTR_MASK 0x07
 540         u8  sg_count;                   /* Number of sg elements */
 541         u16 dekindex;                   /* Data encryption key index */
 542         u64 err_ptr;                    /* Error Pointer */
 543         u32 err_len;                    /* Error Length*/
 544         u32 tweak_upper;                /* Encryption tweak, upper 4 bytes */
 545         struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES];
 546         struct io_accel2_scsi_response error_data;
 547         u8 pad[IOACCEL2_PAD];
 548 };
 549
 550 /*
 551  * defines for Mode 2 command struct
 552  * FIXME: this can't be all I need mfm
 553  */
 554 #define IOACCEL2_IU_TYPE        0x40
 555 #define IOACCEL2_IU_TMF_TYPE    0x41
 556 #define IOACCEL2_DIR_NO_DATA    0x00
 557 #define IOACCEL2_DIR_DATA_IN    0x01
 558 #define IOACCEL2_DIR_DATA_OUT   0x02
 559 /*
 560  * SCSI Task Management Request format for Accelerator Mode 2
 561  */
 562 struct hpsa_tmf_struct {
 563         u8 iu_type;             /* Information Unit Type */
 564         u8 reply_queue;         /* Reply Queue ID */
 565         u8 tmf;                 /* Task Management Function */
 566         u8 reserved1;           /* byte 3 Reserved */
 567         u32 it_nexus;           /* SCSI I-T Nexus */
 568         u8 lun_id[8];           /* LUN ID for TMF request */
 569         struct vals32 Tag;      /* cciss tag associated w/ request */
 570         struct vals32 abort_tag;/* cciss tag of SCSI cmd or task to abort */
 571         u64 error_ptr;          /* Error Pointer */
 572         u32 error_len;          /* Error Length */
 573 };
 574
 575 /* Configuration Table Structure */
 576 struct HostWrite {
 577         u32 TransportRequest;
 578         u32 command_pool_addr_hi;
 579         u32 CoalIntDelay;
 580         u32 CoalIntCount;
 581 };
 582
 583 #define SIMPLE_MODE     0x02
 584 #define PERFORMANT_MODE 0x04
 585 #define MEMQ_MODE       0x08
 586 #define IOACCEL_MODE_1  0x80
 587
 588 #define DRIVER_SUPPORT_UA_ENABLE        0x00000001
 589
 590 struct CfgTable {
 591         u8            Signature[4];
 592         u32             SpecValence;
 593         u32           TransportSupport;
 594         u32           TransportActive;
 595         struct          HostWrite HostWrite;
 596         u32           CmdsOutMax;
 597         u32           BusTypes;
 598         u32           TransMethodOffset;
 599         u8            ServerName[16];
 600         u32           HeartBeat;
 601         u32           driver_support;
 602 #define                 ENABLE_SCSI_PREFETCH 0x100
 603 #define                 ENABLE_UNIT_ATTN 0x01
 604         u32             MaxScatterGatherElements;
 605         u32             MaxLogicalUnits;
 606         u32             MaxPhysicalDevices;
 607         u32             MaxPhysicalDrivesPerLogicalUnit;
 608         u32             MaxPerformantModeCommands;
 609         u32             MaxBlockFetch;
 610         u32             PowerConservationSupport;
 611         u32             PowerConservationEnable;
 612         u32             TMFSupportFlags;
 613         u8              TMFTagMask[8];
 614         u8              reserved[0x78 - 0x70];
 615         u32             misc_fw_support; /* offset 0x78 */
 616 #define                 MISC_FW_DOORBELL_RESET (0x02)
 617 #define                 MISC_FW_DOORBELL_RESET2 (0x010)
 618 #define                 MISC_FW_RAID_OFFLOAD_BASIC (0x020)
 619 #define                 MISC_FW_EVENT_NOTIFY (0x080)
 620         u8              driver_version[32];
 621         u32             max_cached_write_size;
 622         u8              driver_scratchpad[16];
 623         u32             max_error_info_length;
 624         u32             io_accel_max_embedded_sg_count;
 625         u32             io_accel_request_size_offset;
 626         u32             event_notify;
 627 #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30)
 628 #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31)
 629         u32             clear_event_notify;
 630 };
 631
 632 #define NUM_BLOCKFETCH_ENTRIES 8
 633 struct TransTable_struct {
 634         u32            BlockFetch[NUM_BLOCKFETCH_ENTRIES];
 635         u32            RepQSize;
 636         u32            RepQCount;
 637         u32            RepQCtrAddrLow32;
 638         u32            RepQCtrAddrHigh32;
 639 #define MAX_REPLY_QUEUES 8
 640         struct vals32  RepQAddr[MAX_REPLY_QUEUES];
 641 };
 642
 643 struct hpsa_pci_info {
 644         unsigned char   bus;
 645         unsigned char   dev_fn;
 646         unsigned short  domain;
 647         u32             board_id;
 648 };
 649
 650 #pragma pack()
 651 #endif /* HPSA_CMD_H */