]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/scsi/ipr.h
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
cpufreq: conservative: Fix next frequency selection
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / ipr.h
1 /*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
24 */
25
26 #ifndef _IPR_H
27 #define _IPR_H
28
29 #include <asm/unaligned.h>
30 #include <linux/types.h>
31 #include <linux/completion.h>
32 #include <linux/libata.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/irq_poll.h>
36 #include <scsi/scsi.h>
37 #include <scsi/scsi_cmnd.h>
38
39 /*
40 * Literals
41 */
42 #define IPR_DRIVER_VERSION "2.6.3"
43 #define IPR_DRIVER_DATE "(October 17, 2015)"
44
45 /*
46 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
47 * ops per device for devices not running tagged command queuing.
48 * This can be adjusted at runtime through sysfs device attributes.
49 */
50 #define IPR_MAX_CMD_PER_LUN 6
51 #define IPR_MAX_CMD_PER_ATA_LUN 1
52
53 /*
54 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
55 * ops the mid-layer can send to the adapter.
56 */
57 #define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds)
58
59 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
60
61 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
62 #define PCI_DEVICE_ID_IBM_CROCODILE 0x034A
63 #define PCI_DEVICE_ID_IBM_RATTLESNAKE 0x04DA
64
65 #define IPR_SUBS_DEV_ID_2780 0x0264
66 #define IPR_SUBS_DEV_ID_5702 0x0266
67 #define IPR_SUBS_DEV_ID_5703 0x0278
68 #define IPR_SUBS_DEV_ID_572E 0x028D
69 #define IPR_SUBS_DEV_ID_573E 0x02D3
70 #define IPR_SUBS_DEV_ID_573D 0x02D4
71 #define IPR_SUBS_DEV_ID_571A 0x02C0
72 #define IPR_SUBS_DEV_ID_571B 0x02BE
73 #define IPR_SUBS_DEV_ID_571E 0x02BF
74 #define IPR_SUBS_DEV_ID_571F 0x02D5
75 #define IPR_SUBS_DEV_ID_572A 0x02C1
76 #define IPR_SUBS_DEV_ID_572B 0x02C2
77 #define IPR_SUBS_DEV_ID_572F 0x02C3
78 #define IPR_SUBS_DEV_ID_574E 0x030A
79 #define IPR_SUBS_DEV_ID_575B 0x030D
80 #define IPR_SUBS_DEV_ID_575C 0x0338
81 #define IPR_SUBS_DEV_ID_57B3 0x033A
82 #define IPR_SUBS_DEV_ID_57B7 0x0360
83 #define IPR_SUBS_DEV_ID_57B8 0x02C2
84
85 #define IPR_SUBS_DEV_ID_57B4 0x033B
86 #define IPR_SUBS_DEV_ID_57B2 0x035F
87 #define IPR_SUBS_DEV_ID_57C0 0x0352
88 #define IPR_SUBS_DEV_ID_57C3 0x0353
89 #define IPR_SUBS_DEV_ID_57C4 0x0354
90 #define IPR_SUBS_DEV_ID_57C6 0x0357
91 #define IPR_SUBS_DEV_ID_57CC 0x035C
92
93 #define IPR_SUBS_DEV_ID_57B5 0x033C
94 #define IPR_SUBS_DEV_ID_57CE 0x035E
95 #define IPR_SUBS_DEV_ID_57B1 0x0355
96
97 #define IPR_SUBS_DEV_ID_574D 0x0356
98 #define IPR_SUBS_DEV_ID_57C8 0x035D
99
100 #define IPR_SUBS_DEV_ID_57D5 0x03FB
101 #define IPR_SUBS_DEV_ID_57D6 0x03FC
102 #define IPR_SUBS_DEV_ID_57D7 0x03FF
103 #define IPR_SUBS_DEV_ID_57D8 0x03FE
104 #define IPR_SUBS_DEV_ID_57D9 0x046D
105 #define IPR_SUBS_DEV_ID_57DA 0x04CA
106 #define IPR_SUBS_DEV_ID_57EB 0x0474
107 #define IPR_SUBS_DEV_ID_57EC 0x0475
108 #define IPR_SUBS_DEV_ID_57ED 0x0499
109 #define IPR_SUBS_DEV_ID_57EE 0x049A
110 #define IPR_SUBS_DEV_ID_57EF 0x049B
111 #define IPR_SUBS_DEV_ID_57F0 0x049C
112 #define IPR_SUBS_DEV_ID_2CCA 0x04C7
113 #define IPR_SUBS_DEV_ID_2CD2 0x04C8
114 #define IPR_SUBS_DEV_ID_2CCD 0x04C9
115 #define IPR_SUBS_DEV_ID_580A 0x04FC
116 #define IPR_SUBS_DEV_ID_580B 0x04FB
117 #define IPR_NAME "ipr"
118
119 /*
120 * Return codes
121 */
122 #define IPR_RC_JOB_CONTINUE 1
123 #define IPR_RC_JOB_RETURN 2
124
125 /*
126 * IOASCs
127 */
128 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
129 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
130 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
131 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
132 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
133 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
134 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
135 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
136 #define IPR_IOASC_HW_CMD_FAILED 0x046E0000
137 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
138 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
139 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
140 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
141 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
142 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
143 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
144 #define IPR_IOASC_IR_NON_OPTIMIZED 0x05258200
145
146 #define IPR_FIRST_DRIVER_IOASC 0x10000000
147 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
148 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
149
150 /* Driver data flags */
151 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
152 #define IPR_USE_PCI_WARM_RESET 0x00000002
153
154 #define IPR_DEFAULT_MAX_ERROR_DUMP 984
155 #define IPR_NUM_LOG_HCAMS 2
156 #define IPR_NUM_CFG_CHG_HCAMS 2
157 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
158
159 #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
160 #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
161
162 #define IPR_MAX_NUM_TARGETS_PER_BUS 256
163 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
164 #define IPR_VSET_BUS 0xff
165 #define IPR_IOA_BUS 0xff
166 #define IPR_IOA_TARGET 0xff
167 #define IPR_IOA_LUN 0xff
168 #define IPR_MAX_NUM_BUSES 16
169
170 #define IPR_NUM_RESET_RELOAD_RETRIES 3
171
172 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
173 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
174 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
175
176 #define IPR_MAX_COMMANDS 100
177 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
178 IPR_NUM_INTERNAL_CMD_BLKS)
179
180 #define IPR_MAX_PHYSICAL_DEVS 192
181 #define IPR_DEFAULT_SIS64_DEVS 1024
182 #define IPR_MAX_SIS64_DEVS 4096
183
184 #define IPR_MAX_SGLIST 64
185 #define IPR_IOA_MAX_SECTORS 32767
186 #define IPR_VSET_MAX_SECTORS 512
187 #define IPR_MAX_CDB_LEN 16
188 #define IPR_MAX_HRRQ_RETRIES 3
189
190 #define IPR_DEFAULT_BUS_WIDTH 16
191 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
192 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
193 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
194 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
195
196 #define IPR_IOA_RES_HANDLE 0xffffffff
197 #define IPR_INVALID_RES_HANDLE 0
198 #define IPR_IOA_RES_ADDR 0x00ffffff
199
200 /*
201 * Adapter Commands
202 */
203 #define IPR_CANCEL_REQUEST 0xC0
204 #define IPR_CANCEL_64BIT_IOARCB 0x01
205 #define IPR_QUERY_RSRC_STATE 0xC2
206 #define IPR_RESET_DEVICE 0xC3
207 #define IPR_RESET_TYPE_SELECT 0x80
208 #define IPR_LUN_RESET 0x40
209 #define IPR_TARGET_RESET 0x20
210 #define IPR_BUS_RESET 0x10
211 #define IPR_ATA_PHY_RESET 0x80
212 #define IPR_ID_HOST_RR_Q 0xC4
213 #define IPR_QUERY_IOA_CONFIG 0xC5
214 #define IPR_CANCEL_ALL_REQUESTS 0xCE
215 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
216 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
217 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
218 #define IPR_SET_SUPPORTED_DEVICES 0xFB
219 #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
220 #define IPR_IOA_SHUTDOWN 0xF7
221 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
222 #define IPR_IOA_SERVICE_ACTION 0xD2
223
224 /* IOA Service Actions */
225 #define IPR_IOA_SA_CHANGE_CACHE_PARAMS 0x14
226
227 /*
228 * Timeouts
229 */
230 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
231 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
232 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
233 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
234 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
235 #define IPR_CANCEL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
236 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
237 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
238 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
239 #define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ)
240 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
241 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
242 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
243 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
244 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
245 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
246 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
247 #define IPR_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ)
248 #define IPR_PCI_RESET_TIMEOUT (HZ / 2)
249 #define IPR_SIS32_DUMP_TIMEOUT (15 * HZ)
250 #define IPR_SIS64_DUMP_TIMEOUT (40 * HZ)
251 #define IPR_DUMP_DELAY_SECONDS 4
252 #define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
253
254 /*
255 * SCSI Literals
256 */
257 #define IPR_VENDOR_ID_LEN 8
258 #define IPR_PROD_ID_LEN 16
259 #define IPR_SERIAL_NUM_LEN 8
260
261 /*
262 * Hardware literals
263 */
264 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
265 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
266 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
267 #define IPR_GET_FMT2_BAR_SEL(mbx) \
268 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
269 #define IPR_SDT_FMT2_BAR0_SEL 0x0
270 #define IPR_SDT_FMT2_BAR1_SEL 0x1
271 #define IPR_SDT_FMT2_BAR2_SEL 0x2
272 #define IPR_SDT_FMT2_BAR3_SEL 0x3
273 #define IPR_SDT_FMT2_BAR4_SEL 0x4
274 #define IPR_SDT_FMT2_BAR5_SEL 0x5
275 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
276 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
277 #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
278 #define IPR_DOORBELL 0x82800000
279 #define IPR_RUNTIME_RESET 0x40000000
280
281 #define IPR_IPL_INIT_MIN_STAGE_TIME 5
282 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 30
283 #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
284 #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
285 #define IPR_IPL_INIT_STAGE_MASK 0xff000000
286 #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
287 #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
288
289 #define IPR_PCII_MAILBOX_STABLE (0x80000000 >> 4)
290 #define IPR_WAIT_FOR_MAILBOX (2 * HZ)
291
292 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
293 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
294 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
295 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
296 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
297 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
298 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
299 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
300 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
301 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
302 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
303
304 #define IPR_PCII_ERROR_INTERRUPTS \
305 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
306 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
307
308 #define IPR_PCII_OPER_INTERRUPTS \
309 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
310
311 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
312 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
313 #define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
314
315 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
316 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
317
318 /*
319 * Dump literals
320 */
321 #define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
322 #define IPR_FMT3_MAX_IOA_DUMP_SIZE (80 * 1024 * 1024)
323 #define IPR_FMT2_NUM_SDT_ENTRIES 511
324 #define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF
325 #define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
326 #define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
327
328 /*
329 * Misc literals
330 */
331 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
332 #define IPR_MAX_MSIX_VECTORS 0x10
333 #define IPR_MAX_HRRQ_NUM 0x10
334 #define IPR_INIT_HRRQ 0x0
335
336 /*
337 * Adapter interface types
338 */
339
340 struct ipr_res_addr {
341 u8 reserved;
342 u8 bus;
343 u8 target;
344 u8 lun;
345 #define IPR_GET_PHYS_LOC(res_addr) \
346 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
347 }__attribute__((packed, aligned (4)));
348
349 struct ipr_std_inq_vpids {
350 u8 vendor_id[IPR_VENDOR_ID_LEN];
351 u8 product_id[IPR_PROD_ID_LEN];
352 }__attribute__((packed));
353
354 struct ipr_vpd {
355 struct ipr_std_inq_vpids vpids;
356 u8 sn[IPR_SERIAL_NUM_LEN];
357 }__attribute__((packed));
358
359 struct ipr_ext_vpd {
360 struct ipr_vpd vpd;
361 __be32 wwid[2];
362 }__attribute__((packed));
363
364 struct ipr_ext_vpd64 {
365 struct ipr_vpd vpd;
366 __be32 wwid[4];
367 }__attribute__((packed));
368
369 struct ipr_std_inq_data {
370 u8 peri_qual_dev_type;
371 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
372 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
373
374 u8 removeable_medium_rsvd;
375 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
376
377 #define IPR_IS_DASD_DEVICE(std_inq) \
378 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
379 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
380
381 #define IPR_IS_SES_DEVICE(std_inq) \
382 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
383
384 u8 version;
385 u8 aen_naca_fmt;
386 u8 additional_len;
387 u8 sccs_rsvd;
388 u8 bq_enc_multi;
389 u8 sync_cmdq_flags;
390
391 struct ipr_std_inq_vpids vpids;
392
393 u8 ros_rsvd_ram_rsvd[4];
394
395 u8 serial_num[IPR_SERIAL_NUM_LEN];
396 }__attribute__ ((packed));
397
398 #define IPR_RES_TYPE_AF_DASD 0x00
399 #define IPR_RES_TYPE_GENERIC_SCSI 0x01
400 #define IPR_RES_TYPE_VOLUME_SET 0x02
401 #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
402 #define IPR_RES_TYPE_GENERIC_ATA 0x04
403 #define IPR_RES_TYPE_ARRAY 0x05
404 #define IPR_RES_TYPE_IOAFP 0xff
405
406 struct ipr_config_table_entry {
407 u8 proto;
408 #define IPR_PROTO_SATA 0x02
409 #define IPR_PROTO_SATA_ATAPI 0x03
410 #define IPR_PROTO_SAS_STP 0x06
411 #define IPR_PROTO_SAS_STP_ATAPI 0x07
412 u8 array_id;
413 u8 flags;
414 #define IPR_IS_IOA_RESOURCE 0x80
415 u8 rsvd_subtype;
416
417 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
418 #define IPR_QUEUE_FROZEN_MODEL 0
419 #define IPR_QUEUE_NACA_MODEL 1
420
421 struct ipr_res_addr res_addr;
422 __be32 res_handle;
423 __be32 lun_wwn[2];
424 struct ipr_std_inq_data std_inq_data;
425 }__attribute__ ((packed, aligned (4)));
426
427 struct ipr_config_table_entry64 {
428 u8 res_type;
429 u8 proto;
430 u8 vset_num;
431 u8 array_id;
432 __be16 flags;
433 __be16 res_flags;
434 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
435 __be32 res_handle;
436 u8 dev_id_type;
437 u8 reserved[3];
438 __be64 dev_id;
439 __be64 lun;
440 __be64 lun_wwn[2];
441 #define IPR_MAX_RES_PATH_LENGTH 48
442 __be64 res_path;
443 struct ipr_std_inq_data std_inq_data;
444 u8 reserved2[4];
445 __be64 reserved3[2];
446 u8 reserved4[8];
447 }__attribute__ ((packed, aligned (8)));
448
449 struct ipr_config_table_hdr {
450 u8 num_entries;
451 u8 flags;
452 #define IPR_UCODE_DOWNLOAD_REQ 0x10
453 __be16 reserved;
454 }__attribute__((packed, aligned (4)));
455
456 struct ipr_config_table_hdr64 {
457 __be16 num_entries;
458 __be16 reserved;
459 u8 flags;
460 u8 reserved2[11];
461 }__attribute__((packed, aligned (4)));
462
463 struct ipr_config_table {
464 struct ipr_config_table_hdr hdr;
465 struct ipr_config_table_entry dev[0];
466 }__attribute__((packed, aligned (4)));
467
468 struct ipr_config_table64 {
469 struct ipr_config_table_hdr64 hdr64;
470 struct ipr_config_table_entry64 dev[0];
471 }__attribute__((packed, aligned (8)));
472
473 struct ipr_config_table_entry_wrapper {
474 union {
475 struct ipr_config_table_entry *cfgte;
476 struct ipr_config_table_entry64 *cfgte64;
477 } u;
478 };
479
480 struct ipr_hostrcb_cfg_ch_not {
481 union {
482 struct ipr_config_table_entry cfgte;
483 struct ipr_config_table_entry64 cfgte64;
484 } u;
485 u8 reserved[936];
486 }__attribute__((packed, aligned (4)));
487
488 struct ipr_supported_device {
489 __be16 data_length;
490 u8 reserved;
491 u8 num_records;
492 struct ipr_std_inq_vpids vpids;
493 u8 reserved2[16];
494 }__attribute__((packed, aligned (4)));
495
496 struct ipr_hrr_queue {
497 struct ipr_ioa_cfg *ioa_cfg;
498 __be32 *host_rrq;
499 dma_addr_t host_rrq_dma;
500 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
501 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
502 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
503 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
504 #define IPR_ID_HRRQ_SELE_ENABLE 0x02
505 volatile __be32 *hrrq_start;
506 volatile __be32 *hrrq_end;
507 volatile __be32 *hrrq_curr;
508
509 struct list_head hrrq_free_q;
510 struct list_head hrrq_pending_q;
511 spinlock_t _lock;
512 spinlock_t *lock;
513
514 volatile u32 toggle_bit;
515 u32 size;
516 u32 min_cmd_id;
517 u32 max_cmd_id;
518 u8 allow_interrupts:1;
519 u8 ioa_is_dead:1;
520 u8 allow_cmds:1;
521 u8 removing_ioa:1;
522
523 struct irq_poll iopoll;
524 };
525
526 /* Command packet structure */
527 struct ipr_cmd_pkt {
528 u8 reserved; /* Reserved by IOA */
529 u8 hrrq_id;
530 u8 request_type;
531 #define IPR_RQTYPE_SCSICDB 0x00
532 #define IPR_RQTYPE_IOACMD 0x01
533 #define IPR_RQTYPE_HCAM 0x02
534 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
535 #define IPR_RQTYPE_PIPE 0x05
536
537 u8 reserved2;
538
539 u8 flags_hi;
540 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
541 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
542 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
543 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
544 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
545
546 u8 flags_lo;
547 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
548 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
549 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
550 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
551 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
552 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
553 #define IPR_FLAGS_LO_ACA_TASK 0x08
554
555 u8 cdb[16];
556 __be16 timeout;
557 }__attribute__ ((packed, aligned(4)));
558
559 struct ipr_ioarcb_ata_regs { /* 22 bytes */
560 u8 flags;
561 #define IPR_ATA_FLAG_PACKET_CMD 0x80
562 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
563 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
564 u8 reserved[3];
565
566 __be16 data;
567 u8 feature;
568 u8 nsect;
569 u8 lbal;
570 u8 lbam;
571 u8 lbah;
572 u8 device;
573 u8 command;
574 u8 reserved2[3];
575 u8 hob_feature;
576 u8 hob_nsect;
577 u8 hob_lbal;
578 u8 hob_lbam;
579 u8 hob_lbah;
580 u8 ctl;
581 }__attribute__ ((packed, aligned(2)));
582
583 struct ipr_ioadl_desc {
584 __be32 flags_and_data_len;
585 #define IPR_IOADL_FLAGS_MASK 0xff000000
586 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
587 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
588 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
589 #define IPR_IOADL_FLAGS_READ 0x48000000
590 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
591 #define IPR_IOADL_FLAGS_WRITE 0x68000000
592 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
593 #define IPR_IOADL_FLAGS_LAST 0x01000000
594
595 __be32 address;
596 }__attribute__((packed, aligned (8)));
597
598 struct ipr_ioadl64_desc {
599 __be32 flags;
600 __be32 data_len;
601 __be64 address;
602 }__attribute__((packed, aligned (16)));
603
604 struct ipr_ata64_ioadl {
605 struct ipr_ioarcb_ata_regs regs;
606 u16 reserved[5];
607 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
608 }__attribute__((packed, aligned (16)));
609
610 struct ipr_ioarcb_add_data {
611 union {
612 struct ipr_ioarcb_ata_regs regs;
613 struct ipr_ioadl_desc ioadl[5];
614 __be32 add_cmd_parms[10];
615 } u;
616 }__attribute__ ((packed, aligned (4)));
617
618 struct ipr_ioarcb_sis64_add_addr_ecb {
619 __be64 ioasa_host_pci_addr;
620 __be64 data_ioadl_addr;
621 __be64 reserved;
622 __be32 ext_control_buf[4];
623 }__attribute__((packed, aligned (8)));
624
625 /* IOA Request Control Block 128 bytes */
626 struct ipr_ioarcb {
627 union {
628 __be32 ioarcb_host_pci_addr;
629 __be64 ioarcb_host_pci_addr64;
630 } a;
631 __be32 res_handle;
632 __be32 host_response_handle;
633 __be32 reserved1;
634 __be32 reserved2;
635 __be32 reserved3;
636
637 __be32 data_transfer_length;
638 __be32 read_data_transfer_length;
639 __be32 write_ioadl_addr;
640 __be32 ioadl_len;
641 __be32 read_ioadl_addr;
642 __be32 read_ioadl_len;
643
644 __be32 ioasa_host_pci_addr;
645 __be16 ioasa_len;
646 __be16 reserved4;
647
648 struct ipr_cmd_pkt cmd_pkt;
649
650 __be16 add_cmd_parms_offset;
651 __be16 add_cmd_parms_len;
652
653 union {
654 struct ipr_ioarcb_add_data add_data;
655 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
656 } u;
657
658 }__attribute__((packed, aligned (4)));
659
660 struct ipr_ioasa_vset {
661 __be32 failing_lba_hi;
662 __be32 failing_lba_lo;
663 __be32 reserved;
664 }__attribute__((packed, aligned (4)));
665
666 struct ipr_ioasa_af_dasd {
667 __be32 failing_lba;
668 __be32 reserved[2];
669 }__attribute__((packed, aligned (4)));
670
671 struct ipr_ioasa_gpdd {
672 u8 end_state;
673 u8 bus_phase;
674 __be16 reserved;
675 __be32 ioa_data[2];
676 }__attribute__((packed, aligned (4)));
677
678 struct ipr_ioasa_gata {
679 u8 error;
680 u8 nsect; /* Interrupt reason */
681 u8 lbal;
682 u8 lbam;
683 u8 lbah;
684 u8 device;
685 u8 status;
686 u8 alt_status; /* ATA CTL */
687 u8 hob_nsect;
688 u8 hob_lbal;
689 u8 hob_lbam;
690 u8 hob_lbah;
691 }__attribute__((packed, aligned (4)));
692
693 struct ipr_auto_sense {
694 __be16 auto_sense_len;
695 __be16 ioa_data_len;
696 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
697 };
698
699 struct ipr_ioasa_hdr {
700 __be32 ioasc;
701 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
702 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
703 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
704 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
705
706 __be16 ret_stat_len; /* Length of the returned IOASA */
707
708 __be16 avail_stat_len; /* Total Length of status available. */
709
710 __be32 residual_data_len; /* number of bytes in the host data */
711 /* buffers that were not used by the IOARCB command. */
712
713 __be32 ilid;
714 #define IPR_NO_ILID 0
715 #define IPR_DRIVER_ILID 0xffffffff
716
717 __be32 fd_ioasc;
718
719 __be32 fd_phys_locator;
720
721 __be32 fd_res_handle;
722
723 __be32 ioasc_specific; /* status code specific field */
724 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
725 #define IPR_AUTOSENSE_VALID 0x40000000
726 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000
727 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
728 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
729 #define IPR_FIELD_POINTER_MASK 0x0000ffff
730
731 }__attribute__((packed, aligned (4)));
732
733 struct ipr_ioasa {
734 struct ipr_ioasa_hdr hdr;
735
736 union {
737 struct ipr_ioasa_vset vset;
738 struct ipr_ioasa_af_dasd dasd;
739 struct ipr_ioasa_gpdd gpdd;
740 struct ipr_ioasa_gata gata;
741 } u;
742
743 struct ipr_auto_sense auto_sense;
744 }__attribute__((packed, aligned (4)));
745
746 struct ipr_ioasa64 {
747 struct ipr_ioasa_hdr hdr;
748 u8 fd_res_path[8];
749
750 union {
751 struct ipr_ioasa_vset vset;
752 struct ipr_ioasa_af_dasd dasd;
753 struct ipr_ioasa_gpdd gpdd;
754 struct ipr_ioasa_gata gata;
755 } u;
756
757 struct ipr_auto_sense auto_sense;
758 }__attribute__((packed, aligned (4)));
759
760 struct ipr_mode_parm_hdr {
761 u8 length;
762 u8 medium_type;
763 u8 device_spec_parms;
764 u8 block_desc_len;
765 }__attribute__((packed));
766
767 struct ipr_mode_pages {
768 struct ipr_mode_parm_hdr hdr;
769 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
770 }__attribute__((packed));
771
772 struct ipr_mode_page_hdr {
773 u8 ps_page_code;
774 #define IPR_MODE_PAGE_PS 0x80
775 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
776 u8 page_length;
777 }__attribute__ ((packed));
778
779 struct ipr_dev_bus_entry {
780 struct ipr_res_addr res_addr;
781 u8 flags;
782 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
783 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
784 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
785 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
786 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
787 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
788 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
789
790 u8 scsi_id;
791 u8 bus_width;
792 u8 extended_reset_delay;
793 #define IPR_EXTENDED_RESET_DELAY 7
794
795 __be32 max_xfer_rate;
796
797 u8 spinup_delay;
798 u8 reserved3;
799 __be16 reserved4;
800 }__attribute__((packed, aligned (4)));
801
802 struct ipr_mode_page28 {
803 struct ipr_mode_page_hdr hdr;
804 u8 num_entries;
805 u8 entry_length;
806 struct ipr_dev_bus_entry bus[0];
807 }__attribute__((packed));
808
809 struct ipr_mode_page24 {
810 struct ipr_mode_page_hdr hdr;
811 u8 flags;
812 #define IPR_ENABLE_DUAL_IOA_AF 0x80
813 }__attribute__((packed));
814
815 struct ipr_ioa_vpd {
816 struct ipr_std_inq_data std_inq_data;
817 u8 ascii_part_num[12];
818 u8 reserved[40];
819 u8 ascii_plant_code[4];
820 }__attribute__((packed));
821
822 struct ipr_inquiry_page3 {
823 u8 peri_qual_dev_type;
824 u8 page_code;
825 u8 reserved1;
826 u8 page_length;
827 u8 ascii_len;
828 u8 reserved2[3];
829 u8 load_id[4];
830 u8 major_release;
831 u8 card_type;
832 u8 minor_release[2];
833 u8 ptf_number[4];
834 u8 patch_number[4];
835 }__attribute__((packed));
836
837 struct ipr_inquiry_cap {
838 u8 peri_qual_dev_type;
839 u8 page_code;
840 u8 reserved1;
841 u8 page_length;
842 u8 ascii_len;
843 u8 reserved2;
844 u8 sis_version[2];
845 u8 cap;
846 #define IPR_CAP_DUAL_IOA_RAID 0x80
847 u8 reserved3[15];
848 }__attribute__((packed));
849
850 #define IPR_INQUIRY_PAGE0_ENTRIES 20
851 struct ipr_inquiry_page0 {
852 u8 peri_qual_dev_type;
853 u8 page_code;
854 u8 reserved1;
855 u8 len;
856 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
857 }__attribute__((packed));
858
859 struct ipr_inquiry_pageC4 {
860 u8 peri_qual_dev_type;
861 u8 page_code;
862 u8 reserved1;
863 u8 len;
864 u8 cache_cap[4];
865 #define IPR_CAP_SYNC_CACHE 0x08
866 u8 reserved2[20];
867 } __packed;
868
869 struct ipr_hostrcb_device_data_entry {
870 struct ipr_vpd vpd;
871 struct ipr_res_addr dev_res_addr;
872 struct ipr_vpd new_vpd;
873 struct ipr_vpd ioa_last_with_dev_vpd;
874 struct ipr_vpd cfc_last_with_dev_vpd;
875 __be32 ioa_data[5];
876 }__attribute__((packed, aligned (4)));
877
878 struct ipr_hostrcb_device_data_entry_enhanced {
879 struct ipr_ext_vpd vpd;
880 u8 ccin[4];
881 struct ipr_res_addr dev_res_addr;
882 struct ipr_ext_vpd new_vpd;
883 u8 new_ccin[4];
884 struct ipr_ext_vpd ioa_last_with_dev_vpd;
885 struct ipr_ext_vpd cfc_last_with_dev_vpd;
886 }__attribute__((packed, aligned (4)));
887
888 struct ipr_hostrcb64_device_data_entry_enhanced {
889 struct ipr_ext_vpd vpd;
890 u8 ccin[4];
891 u8 res_path[8];
892 struct ipr_ext_vpd new_vpd;
893 u8 new_ccin[4];
894 struct ipr_ext_vpd ioa_last_with_dev_vpd;
895 struct ipr_ext_vpd cfc_last_with_dev_vpd;
896 }__attribute__((packed, aligned (4)));
897
898 struct ipr_hostrcb_array_data_entry {
899 struct ipr_vpd vpd;
900 struct ipr_res_addr expected_dev_res_addr;
901 struct ipr_res_addr dev_res_addr;
902 }__attribute__((packed, aligned (4)));
903
904 struct ipr_hostrcb64_array_data_entry {
905 struct ipr_ext_vpd vpd;
906 u8 ccin[4];
907 u8 expected_res_path[8];
908 u8 res_path[8];
909 }__attribute__((packed, aligned (4)));
910
911 struct ipr_hostrcb_array_data_entry_enhanced {
912 struct ipr_ext_vpd vpd;
913 u8 ccin[4];
914 struct ipr_res_addr expected_dev_res_addr;
915 struct ipr_res_addr dev_res_addr;
916 }__attribute__((packed, aligned (4)));
917
918 struct ipr_hostrcb_type_ff_error {
919 __be32 ioa_data[758];
920 }__attribute__((packed, aligned (4)));
921
922 struct ipr_hostrcb_type_01_error {
923 __be32 seek_counter;
924 __be32 read_counter;
925 u8 sense_data[32];
926 __be32 ioa_data[236];
927 }__attribute__((packed, aligned (4)));
928
929 struct ipr_hostrcb_type_21_error {
930 __be32 wwn[4];
931 u8 res_path[8];
932 u8 primary_problem_desc[32];
933 u8 second_problem_desc[32];
934 __be32 sense_data[8];
935 __be32 cdb[4];
936 __be32 residual_trans_length;
937 __be32 length_of_error;
938 __be32 ioa_data[236];
939 }__attribute__((packed, aligned (4)));
940
941 struct ipr_hostrcb_type_02_error {
942 struct ipr_vpd ioa_vpd;
943 struct ipr_vpd cfc_vpd;
944 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
945 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
946 __be32 ioa_data[3];
947 }__attribute__((packed, aligned (4)));
948
949 struct ipr_hostrcb_type_12_error {
950 struct ipr_ext_vpd ioa_vpd;
951 struct ipr_ext_vpd cfc_vpd;
952 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
953 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
954 __be32 ioa_data[3];
955 }__attribute__((packed, aligned (4)));
956
957 struct ipr_hostrcb_type_03_error {
958 struct ipr_vpd ioa_vpd;
959 struct ipr_vpd cfc_vpd;
960 __be32 errors_detected;
961 __be32 errors_logged;
962 u8 ioa_data[12];
963 struct ipr_hostrcb_device_data_entry dev[3];
964 }__attribute__((packed, aligned (4)));
965
966 struct ipr_hostrcb_type_13_error {
967 struct ipr_ext_vpd ioa_vpd;
968 struct ipr_ext_vpd cfc_vpd;
969 __be32 errors_detected;
970 __be32 errors_logged;
971 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
972 }__attribute__((packed, aligned (4)));
973
974 struct ipr_hostrcb_type_23_error {
975 struct ipr_ext_vpd ioa_vpd;
976 struct ipr_ext_vpd cfc_vpd;
977 __be32 errors_detected;
978 __be32 errors_logged;
979 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
980 }__attribute__((packed, aligned (4)));
981
982 struct ipr_hostrcb_type_04_error {
983 struct ipr_vpd ioa_vpd;
984 struct ipr_vpd cfc_vpd;
985 u8 ioa_data[12];
986 struct ipr_hostrcb_array_data_entry array_member[10];
987 __be32 exposed_mode_adn;
988 __be32 array_id;
989 struct ipr_vpd incomp_dev_vpd;
990 __be32 ioa_data2;
991 struct ipr_hostrcb_array_data_entry array_member2[8];
992 struct ipr_res_addr last_func_vset_res_addr;
993 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
994 u8 protection_level[8];
995 }__attribute__((packed, aligned (4)));
996
997 struct ipr_hostrcb_type_14_error {
998 struct ipr_ext_vpd ioa_vpd;
999 struct ipr_ext_vpd cfc_vpd;
1000 __be32 exposed_mode_adn;
1001 __be32 array_id;
1002 struct ipr_res_addr last_func_vset_res_addr;
1003 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
1004 u8 protection_level[8];
1005 __be32 num_entries;
1006 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
1007 }__attribute__((packed, aligned (4)));
1008
1009 struct ipr_hostrcb_type_24_error {
1010 struct ipr_ext_vpd ioa_vpd;
1011 struct ipr_ext_vpd cfc_vpd;
1012 u8 reserved[2];
1013 u8 exposed_mode_adn;
1014 #define IPR_INVALID_ARRAY_DEV_NUM 0xff
1015 u8 array_id;
1016 u8 last_res_path[8];
1017 u8 protection_level[8];
1018 struct ipr_ext_vpd64 array_vpd;
1019 u8 description[16];
1020 u8 reserved2[3];
1021 u8 num_entries;
1022 struct ipr_hostrcb64_array_data_entry array_member[32];
1023 }__attribute__((packed, aligned (4)));
1024
1025 struct ipr_hostrcb_type_07_error {
1026 u8 failure_reason[64];
1027 struct ipr_vpd vpd;
1028 __be32 data[222];
1029 }__attribute__((packed, aligned (4)));
1030
1031 struct ipr_hostrcb_type_17_error {
1032 u8 failure_reason[64];
1033 struct ipr_ext_vpd vpd;
1034 __be32 data[476];
1035 }__attribute__((packed, aligned (4)));
1036
1037 struct ipr_hostrcb_config_element {
1038 u8 type_status;
1039 #define IPR_PATH_CFG_TYPE_MASK 0xF0
1040 #define IPR_PATH_CFG_NOT_EXIST 0x00
1041 #define IPR_PATH_CFG_IOA_PORT 0x10
1042 #define IPR_PATH_CFG_EXP_PORT 0x20
1043 #define IPR_PATH_CFG_DEVICE_PORT 0x30
1044 #define IPR_PATH_CFG_DEVICE_LUN 0x40
1045
1046 #define IPR_PATH_CFG_STATUS_MASK 0x0F
1047 #define IPR_PATH_CFG_NO_PROB 0x00
1048 #define IPR_PATH_CFG_DEGRADED 0x01
1049 #define IPR_PATH_CFG_FAILED 0x02
1050 #define IPR_PATH_CFG_SUSPECT 0x03
1051 #define IPR_PATH_NOT_DETECTED 0x04
1052 #define IPR_PATH_INCORRECT_CONN 0x05
1053
1054 u8 cascaded_expander;
1055 u8 phy;
1056 u8 link_rate;
1057 #define IPR_PHY_LINK_RATE_MASK 0x0F
1058
1059 __be32 wwid[2];
1060 }__attribute__((packed, aligned (4)));
1061
1062 struct ipr_hostrcb64_config_element {
1063 __be16 length;
1064 u8 descriptor_id;
1065 #define IPR_DESCRIPTOR_MASK 0xC0
1066 #define IPR_DESCRIPTOR_SIS64 0x00
1067
1068 u8 reserved;
1069 u8 type_status;
1070
1071 u8 reserved2[2];
1072 u8 link_rate;
1073
1074 u8 res_path[8];
1075 __be32 wwid[2];
1076 }__attribute__((packed, aligned (8)));
1077
1078 struct ipr_hostrcb_fabric_desc {
1079 __be16 length;
1080 u8 ioa_port;
1081 u8 cascaded_expander;
1082 u8 phy;
1083 u8 path_state;
1084 #define IPR_PATH_ACTIVE_MASK 0xC0
1085 #define IPR_PATH_NO_INFO 0x00
1086 #define IPR_PATH_ACTIVE 0x40
1087 #define IPR_PATH_NOT_ACTIVE 0x80
1088
1089 #define IPR_PATH_STATE_MASK 0x0F
1090 #define IPR_PATH_STATE_NO_INFO 0x00
1091 #define IPR_PATH_HEALTHY 0x01
1092 #define IPR_PATH_DEGRADED 0x02
1093 #define IPR_PATH_FAILED 0x03
1094
1095 __be16 num_entries;
1096 struct ipr_hostrcb_config_element elem[1];
1097 }__attribute__((packed, aligned (4)));
1098
1099 struct ipr_hostrcb64_fabric_desc {
1100 __be16 length;
1101 u8 descriptor_id;
1102
1103 u8 reserved[2];
1104 u8 path_state;
1105
1106 u8 reserved2[2];
1107 u8 res_path[8];
1108 u8 reserved3[6];
1109 __be16 num_entries;
1110 struct ipr_hostrcb64_config_element elem[1];
1111 }__attribute__((packed, aligned (8)));
1112
1113 #define for_each_hrrq(hrrq, ioa_cfg) \
1114 for (hrrq = (ioa_cfg)->hrrq; \
1115 hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
1116
1117 #define for_each_fabric_cfg(fabric, cfg) \
1118 for (cfg = (fabric)->elem; \
1119 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1120 cfg++)
1121
1122 struct ipr_hostrcb_type_20_error {
1123 u8 failure_reason[64];
1124 u8 reserved[3];
1125 u8 num_entries;
1126 struct ipr_hostrcb_fabric_desc desc[1];
1127 }__attribute__((packed, aligned (4)));
1128
1129 struct ipr_hostrcb_type_30_error {
1130 u8 failure_reason[64];
1131 u8 reserved[3];
1132 u8 num_entries;
1133 struct ipr_hostrcb64_fabric_desc desc[1];
1134 }__attribute__((packed, aligned (4)));
1135
1136 struct ipr_hostrcb_error {
1137 __be32 fd_ioasc;
1138 struct ipr_res_addr fd_res_addr;
1139 __be32 fd_res_handle;
1140 __be32 prc;
1141 union {
1142 struct ipr_hostrcb_type_ff_error type_ff_error;
1143 struct ipr_hostrcb_type_01_error type_01_error;
1144 struct ipr_hostrcb_type_02_error type_02_error;
1145 struct ipr_hostrcb_type_03_error type_03_error;
1146 struct ipr_hostrcb_type_04_error type_04_error;
1147 struct ipr_hostrcb_type_07_error type_07_error;
1148 struct ipr_hostrcb_type_12_error type_12_error;
1149 struct ipr_hostrcb_type_13_error type_13_error;
1150 struct ipr_hostrcb_type_14_error type_14_error;
1151 struct ipr_hostrcb_type_17_error type_17_error;
1152 struct ipr_hostrcb_type_20_error type_20_error;
1153 } u;
1154 }__attribute__((packed, aligned (4)));
1155
1156 struct ipr_hostrcb64_error {
1157 __be32 fd_ioasc;
1158 __be32 ioa_fw_level;
1159 __be32 fd_res_handle;
1160 __be32 prc;
1161 __be64 fd_dev_id;
1162 __be64 fd_lun;
1163 u8 fd_res_path[8];
1164 __be64 time_stamp;
1165 u8 reserved[16];
1166 union {
1167 struct ipr_hostrcb_type_ff_error type_ff_error;
1168 struct ipr_hostrcb_type_12_error type_12_error;
1169 struct ipr_hostrcb_type_17_error type_17_error;
1170 struct ipr_hostrcb_type_21_error type_21_error;
1171 struct ipr_hostrcb_type_23_error type_23_error;
1172 struct ipr_hostrcb_type_24_error type_24_error;
1173 struct ipr_hostrcb_type_30_error type_30_error;
1174 } u;
1175 }__attribute__((packed, aligned (8)));
1176
1177 struct ipr_hostrcb_raw {
1178 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1179 }__attribute__((packed, aligned (4)));
1180
1181 struct ipr_hcam {
1182 u8 op_code;
1183 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1184 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1185
1186 u8 notify_type;
1187 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1188 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1189 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1190 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1191 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1192
1193 u8 notifications_lost;
1194 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1195 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1196
1197 u8 flags;
1198 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
1199 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1200
1201 u8 overlay_id;
1202 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1203 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1204 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1205 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1206 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1207 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1208 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1209 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1210 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1211 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1212 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1213 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1214 #define IPR_HOST_RCB_OVERLAY_ID_21 0x21
1215 #define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1216 #define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1217 #define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1218 #define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1219 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1220
1221 u8 reserved1[3];
1222 __be32 ilid;
1223 __be32 time_since_last_ioa_reset;
1224 __be32 reserved2;
1225 __be32 length;
1226
1227 union {
1228 struct ipr_hostrcb_error error;
1229 struct ipr_hostrcb64_error error64;
1230 struct ipr_hostrcb_cfg_ch_not ccn;
1231 struct ipr_hostrcb_raw raw;
1232 } u;
1233 }__attribute__((packed, aligned (4)));
1234
1235 struct ipr_hostrcb {
1236 struct ipr_hcam hcam;
1237 dma_addr_t hostrcb_dma;
1238 struct list_head queue;
1239 struct ipr_ioa_cfg *ioa_cfg;
1240 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1241 };
1242
1243 /* IPR smart dump table structures */
1244 struct ipr_sdt_entry {
1245 __be32 start_token;
1246 __be32 end_token;
1247 u8 reserved[4];
1248
1249 u8 flags;
1250 #define IPR_SDT_ENDIAN 0x80
1251 #define IPR_SDT_VALID_ENTRY 0x20
1252
1253 u8 resv;
1254 __be16 priority;
1255 }__attribute__((packed, aligned (4)));
1256
1257 struct ipr_sdt_header {
1258 __be32 state;
1259 __be32 num_entries;
1260 __be32 num_entries_used;
1261 __be32 dump_size;
1262 }__attribute__((packed, aligned (4)));
1263
1264 struct ipr_sdt {
1265 struct ipr_sdt_header hdr;
1266 struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1267 }__attribute__((packed, aligned (4)));
1268
1269 struct ipr_uc_sdt {
1270 struct ipr_sdt_header hdr;
1271 struct ipr_sdt_entry entry[1];
1272 }__attribute__((packed, aligned (4)));
1273
1274 /*
1275 * Driver types
1276 */
1277 struct ipr_bus_attributes {
1278 u8 bus;
1279 u8 qas_enabled;
1280 u8 bus_width;
1281 u8 reserved;
1282 u32 max_xfer_rate;
1283 };
1284
1285 struct ipr_sata_port {
1286 struct ipr_ioa_cfg *ioa_cfg;
1287 struct ata_port *ap;
1288 struct ipr_resource_entry *res;
1289 struct ipr_ioasa_gata ioasa;
1290 };
1291
1292 struct ipr_resource_entry {
1293 u8 needs_sync_complete:1;
1294 u8 in_erp:1;
1295 u8 add_to_ml:1;
1296 u8 del_from_ml:1;
1297 u8 resetting_device:1;
1298 u8 reset_occurred:1;
1299 u8 raw_mode:1;
1300
1301 u32 bus; /* AKA channel */
1302 u32 target; /* AKA id */
1303 u32 lun;
1304 #define IPR_ARRAY_VIRTUAL_BUS 0x1
1305 #define IPR_VSET_VIRTUAL_BUS 0x2
1306 #define IPR_IOAFP_VIRTUAL_BUS 0x3
1307
1308 #define IPR_GET_RES_PHYS_LOC(res) \
1309 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1310
1311 u8 ata_class;
1312 u8 type;
1313
1314 u16 flags;
1315 u16 res_flags;
1316
1317 u8 qmodel;
1318 struct ipr_std_inq_data std_inq_data;
1319
1320 __be32 res_handle;
1321 __be64 dev_id;
1322 u64 lun_wwn;
1323 struct scsi_lun dev_lun;
1324 u8 res_path[8];
1325
1326 struct ipr_ioa_cfg *ioa_cfg;
1327 struct scsi_device *sdev;
1328 struct ipr_sata_port *sata_port;
1329 struct list_head queue;
1330 }; /* struct ipr_resource_entry */
1331
1332 struct ipr_resource_hdr {
1333 u16 num_entries;
1334 u16 reserved;
1335 };
1336
1337 struct ipr_misc_cbs {
1338 struct ipr_ioa_vpd ioa_vpd;
1339 struct ipr_inquiry_page0 page0_data;
1340 struct ipr_inquiry_page3 page3_data;
1341 struct ipr_inquiry_cap cap;
1342 struct ipr_inquiry_pageC4 pageC4_data;
1343 struct ipr_mode_pages mode_pages;
1344 struct ipr_supported_device supp_dev;
1345 };
1346
1347 struct ipr_interrupt_offsets {
1348 unsigned long set_interrupt_mask_reg;
1349 unsigned long clr_interrupt_mask_reg;
1350 unsigned long clr_interrupt_mask_reg32;
1351 unsigned long sense_interrupt_mask_reg;
1352 unsigned long sense_interrupt_mask_reg32;
1353 unsigned long clr_interrupt_reg;
1354 unsigned long clr_interrupt_reg32;
1355
1356 unsigned long sense_interrupt_reg;
1357 unsigned long sense_interrupt_reg32;
1358 unsigned long ioarrin_reg;
1359 unsigned long sense_uproc_interrupt_reg;
1360 unsigned long sense_uproc_interrupt_reg32;
1361 unsigned long set_uproc_interrupt_reg;
1362 unsigned long set_uproc_interrupt_reg32;
1363 unsigned long clr_uproc_interrupt_reg;
1364 unsigned long clr_uproc_interrupt_reg32;
1365
1366 unsigned long init_feedback_reg;
1367
1368 unsigned long dump_addr_reg;
1369 unsigned long dump_data_reg;
1370
1371 #define IPR_ENDIAN_SWAP_KEY 0x00080800
1372 unsigned long endian_swap_reg;
1373 };
1374
1375 struct ipr_interrupts {
1376 void __iomem *set_interrupt_mask_reg;
1377 void __iomem *clr_interrupt_mask_reg;
1378 void __iomem *clr_interrupt_mask_reg32;
1379 void __iomem *sense_interrupt_mask_reg;
1380 void __iomem *sense_interrupt_mask_reg32;
1381 void __iomem *clr_interrupt_reg;
1382 void __iomem *clr_interrupt_reg32;
1383
1384 void __iomem *sense_interrupt_reg;
1385 void __iomem *sense_interrupt_reg32;
1386 void __iomem *ioarrin_reg;
1387 void __iomem *sense_uproc_interrupt_reg;
1388 void __iomem *sense_uproc_interrupt_reg32;
1389 void __iomem *set_uproc_interrupt_reg;
1390 void __iomem *set_uproc_interrupt_reg32;
1391 void __iomem *clr_uproc_interrupt_reg;
1392 void __iomem *clr_uproc_interrupt_reg32;
1393
1394 void __iomem *init_feedback_reg;
1395
1396 void __iomem *dump_addr_reg;
1397 void __iomem *dump_data_reg;
1398
1399 void __iomem *endian_swap_reg;
1400 };
1401
1402 struct ipr_chip_cfg_t {
1403 u32 mailbox;
1404 u16 max_cmds;
1405 u8 cache_line_size;
1406 u8 clear_isr;
1407 u32 iopoll_weight;
1408 struct ipr_interrupt_offsets regs;
1409 };
1410
1411 struct ipr_chip_t {
1412 u16 vendor;
1413 u16 device;
1414 u16 intr_type;
1415 #define IPR_USE_LSI 0x00
1416 #define IPR_USE_MSI 0x01
1417 #define IPR_USE_MSIX 0x02
1418 u16 sis_type;
1419 #define IPR_SIS32 0x00
1420 #define IPR_SIS64 0x01
1421 u16 bist_method;
1422 #define IPR_PCI_CFG 0x00
1423 #define IPR_MMIO 0x01
1424 const struct ipr_chip_cfg_t *cfg;
1425 };
1426
1427 enum ipr_shutdown_type {
1428 IPR_SHUTDOWN_NORMAL = 0x00,
1429 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1430 IPR_SHUTDOWN_ABBREV = 0x80,
1431 IPR_SHUTDOWN_NONE = 0x100,
1432 IPR_SHUTDOWN_QUIESCE = 0x101,
1433 };
1434
1435 struct ipr_trace_entry {
1436 u32 time;
1437
1438 u8 op_code;
1439 u8 ata_op_code;
1440 u8 type;
1441 #define IPR_TRACE_START 0x00
1442 #define IPR_TRACE_FINISH 0xff
1443 u8 cmd_index;
1444
1445 __be32 res_handle;
1446 union {
1447 u32 ioasc;
1448 u32 add_data;
1449 u32 res_addr;
1450 } u;
1451 };
1452
1453 struct ipr_sglist {
1454 u32 order;
1455 u32 num_sg;
1456 u32 num_dma_sg;
1457 u32 buffer_len;
1458 struct scatterlist scatterlist[1];
1459 };
1460
1461 enum ipr_sdt_state {
1462 INACTIVE,
1463 WAIT_FOR_DUMP,
1464 GET_DUMP,
1465 READ_DUMP,
1466 ABORT_DUMP,
1467 DUMP_OBTAINED
1468 };
1469
1470 /* Per-controller data */
1471 struct ipr_ioa_cfg {
1472 char eye_catcher[8];
1473 #define IPR_EYECATCHER "iprcfg"
1474
1475 struct list_head queue;
1476
1477 u8 in_reset_reload:1;
1478 u8 in_ioa_bringdown:1;
1479 u8 ioa_unit_checked:1;
1480 u8 dump_taken:1;
1481 u8 scan_enabled:1;
1482 u8 scan_done:1;
1483 u8 needs_hard_reset:1;
1484 u8 dual_raid:1;
1485 u8 needs_warm_reset:1;
1486 u8 msi_received:1;
1487 u8 sis64:1;
1488 u8 dump_timeout:1;
1489 u8 cfg_locked:1;
1490 u8 clear_isr:1;
1491 u8 probe_done:1;
1492
1493 u8 revid;
1494
1495 /*
1496 * Bitmaps for SIS64 generated target values
1497 */
1498 unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1499 unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1500 unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1501
1502 u16 type; /* CCIN of the card */
1503
1504 u8 log_level;
1505 #define IPR_MAX_LOG_LEVEL 4
1506 #define IPR_DEFAULT_LOG_LEVEL 2
1507
1508 #define IPR_NUM_TRACE_INDEX_BITS 8
1509 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1510 #define IPR_TRACE_INDEX_MASK (IPR_NUM_TRACE_ENTRIES - 1)
1511 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1512 char trace_start[8];
1513 #define IPR_TRACE_START_LABEL "trace"
1514 struct ipr_trace_entry *trace;
1515 atomic_t trace_index;
1516
1517 char cfg_table_start[8];
1518 #define IPR_CFG_TBL_START "cfg"
1519 union {
1520 struct ipr_config_table *cfg_table;
1521 struct ipr_config_table64 *cfg_table64;
1522 } u;
1523 dma_addr_t cfg_table_dma;
1524 u32 cfg_table_size;
1525 u32 max_devs_supported;
1526
1527 char resource_table_label[8];
1528 #define IPR_RES_TABLE_LABEL "res_tbl"
1529 struct ipr_resource_entry *res_entries;
1530 struct list_head free_res_q;
1531 struct list_head used_res_q;
1532
1533 char ipr_hcam_label[8];
1534 #define IPR_HCAM_LABEL "hcams"
1535 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1536 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1537 struct list_head hostrcb_free_q;
1538 struct list_head hostrcb_pending_q;
1539
1540 struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
1541 u32 hrrq_num;
1542 atomic_t hrrq_index;
1543 u16 identify_hrrq_index;
1544
1545 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1546
1547 unsigned int transop_timeout;
1548 const struct ipr_chip_cfg_t *chip_cfg;
1549 const struct ipr_chip_t *ipr_chip;
1550
1551 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1552 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1553 void __iomem *ioa_mailbox;
1554 struct ipr_interrupts regs;
1555
1556 u16 saved_pcix_cmd_reg;
1557 u16 reset_retries;
1558
1559 u32 errors_logged;
1560 u32 doorbell;
1561
1562 struct Scsi_Host *host;
1563 struct pci_dev *pdev;
1564 struct ipr_sglist *ucode_sglist;
1565 u8 saved_mode_page_len;
1566
1567 struct work_struct work_q;
1568 struct workqueue_struct *reset_work_q;
1569
1570 wait_queue_head_t reset_wait_q;
1571 wait_queue_head_t msi_wait_q;
1572 wait_queue_head_t eeh_wait_q;
1573
1574 struct ipr_dump *dump;
1575 enum ipr_sdt_state sdt_state;
1576
1577 struct ipr_misc_cbs *vpd_cbs;
1578 dma_addr_t vpd_cbs_dma;
1579
1580 struct dma_pool *ipr_cmd_pool;
1581
1582 struct ipr_cmnd *reset_cmd;
1583 int (*reset) (struct ipr_cmnd *);
1584
1585 struct ata_host ata_host;
1586 char ipr_cmd_label[8];
1587 #define IPR_CMD_LABEL "ipr_cmd"
1588 u32 max_cmds;
1589 struct ipr_cmnd **ipr_cmnd_list;
1590 dma_addr_t *ipr_cmnd_list_dma;
1591
1592 u16 intr_flag;
1593 unsigned int nvectors;
1594
1595 struct {
1596 unsigned short vec;
1597 char desc[22];
1598 } vectors_info[IPR_MAX_MSIX_VECTORS];
1599
1600 u32 iopoll_weight;
1601
1602 }; /* struct ipr_ioa_cfg */
1603
1604 struct ipr_cmnd {
1605 struct ipr_ioarcb ioarcb;
1606 union {
1607 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1608 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1609 struct ipr_ata64_ioadl ata_ioadl;
1610 } i;
1611 union {
1612 struct ipr_ioasa ioasa;
1613 struct ipr_ioasa64 ioasa64;
1614 } s;
1615 struct list_head queue;
1616 struct scsi_cmnd *scsi_cmd;
1617 struct ata_queued_cmd *qc;
1618 struct completion completion;
1619 struct timer_list timer;
1620 struct work_struct work;
1621 void (*fast_done) (struct ipr_cmnd *);
1622 void (*done) (struct ipr_cmnd *);
1623 int (*job_step) (struct ipr_cmnd *);
1624 int (*job_step_failed) (struct ipr_cmnd *);
1625 u16 cmd_index;
1626 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1627 dma_addr_t sense_buffer_dma;
1628 unsigned short dma_use_sg;
1629 dma_addr_t dma_addr;
1630 struct ipr_cmnd *sibling;
1631 union {
1632 enum ipr_shutdown_type shutdown_type;
1633 struct ipr_hostrcb *hostrcb;
1634 unsigned long time_left;
1635 unsigned long scratch;
1636 struct ipr_resource_entry *res;
1637 struct scsi_device *sdev;
1638 } u;
1639
1640 struct completion *eh_comp;
1641 struct ipr_hrr_queue *hrrq;
1642 struct ipr_ioa_cfg *ioa_cfg;
1643 };
1644
1645 struct ipr_ses_table_entry {
1646 char product_id[17];
1647 char compare_product_id_byte[17];
1648 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1649 };
1650
1651 struct ipr_dump_header {
1652 u32 eye_catcher;
1653 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1654 u32 len;
1655 u32 num_entries;
1656 u32 first_entry_offset;
1657 u32 status;
1658 #define IPR_DUMP_STATUS_SUCCESS 0
1659 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1660 #define IPR_DUMP_STATUS_FAILED 0xffffffff
1661 u32 os;
1662 #define IPR_DUMP_OS_LINUX 0x4C4E5558
1663 u32 driver_name;
1664 #define IPR_DUMP_DRIVER_NAME 0x49505232
1665 }__attribute__((packed, aligned (4)));
1666
1667 struct ipr_dump_entry_header {
1668 u32 eye_catcher;
1669 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1670 u32 len;
1671 u32 num_elems;
1672 u32 offset;
1673 u32 data_type;
1674 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1675 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1676 u32 id;
1677 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1678 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1679 #define IPR_DUMP_TRACE_ID 0x54524143
1680 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1681 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1682 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1683 #define IPR_DUMP_PEND_OPS 0x414F5053
1684 u32 status;
1685 }__attribute__((packed, aligned (4)));
1686
1687 struct ipr_dump_location_entry {
1688 struct ipr_dump_entry_header hdr;
1689 u8 location[20];
1690 }__attribute__((packed));
1691
1692 struct ipr_dump_trace_entry {
1693 struct ipr_dump_entry_header hdr;
1694 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1695 }__attribute__((packed, aligned (4)));
1696
1697 struct ipr_dump_version_entry {
1698 struct ipr_dump_entry_header hdr;
1699 u8 version[sizeof(IPR_DRIVER_VERSION)];
1700 };
1701
1702 struct ipr_dump_ioa_type_entry {
1703 struct ipr_dump_entry_header hdr;
1704 u32 type;
1705 u32 fw_version;
1706 };
1707
1708 struct ipr_driver_dump {
1709 struct ipr_dump_header hdr;
1710 struct ipr_dump_version_entry version_entry;
1711 struct ipr_dump_location_entry location_entry;
1712 struct ipr_dump_ioa_type_entry ioa_type_entry;
1713 struct ipr_dump_trace_entry trace_entry;
1714 }__attribute__((packed));
1715
1716 struct ipr_ioa_dump {
1717 struct ipr_dump_entry_header hdr;
1718 struct ipr_sdt sdt;
1719 __be32 **ioa_data;
1720 u32 reserved;
1721 u32 next_page_index;
1722 u32 page_offset;
1723 u32 format;
1724 }__attribute__((packed, aligned (4)));
1725
1726 struct ipr_dump {
1727 struct kref kref;
1728 struct ipr_ioa_cfg *ioa_cfg;
1729 struct ipr_driver_dump driver_dump;
1730 struct ipr_ioa_dump ioa_dump;
1731 };
1732
1733 struct ipr_error_table_t {
1734 u32 ioasc;
1735 int log_ioasa;
1736 int log_hcam;
1737 char *error;
1738 };
1739
1740 struct ipr_software_inq_lid_info {
1741 __be32 load_id;
1742 __be32 timestamp[3];
1743 }__attribute__((packed, aligned (4)));
1744
1745 struct ipr_ucode_image_header {
1746 __be32 header_length;
1747 __be32 lid_table_offset;
1748 u8 major_release;
1749 u8 card_type;
1750 u8 minor_release[2];
1751 u8 reserved[20];
1752 char eyecatcher[16];
1753 __be32 num_lids;
1754 struct ipr_software_inq_lid_info lid[1];
1755 }__attribute__((packed, aligned (4)));
1756
1757 /*
1758 * Macros
1759 */
1760 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1761
1762 #ifdef CONFIG_SCSI_IPR_TRACE
1763 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1764 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1765 #else
1766 #define ipr_create_trace_file(kobj, attr) 0
1767 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1768 #endif
1769
1770 #ifdef CONFIG_SCSI_IPR_DUMP
1771 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1772 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1773 #else
1774 #define ipr_create_dump_file(kobj, attr) 0
1775 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1776 #endif
1777
1778 /*
1779 * Error logging macros
1780 */
1781 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1782 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1783 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1784
1785 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1786 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1787 bus, target, lun, ##__VA_ARGS__)
1788
1789 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1790 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1791
1792 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1793 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1794 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1795
1796 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1797 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1798
1799 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1800 { \
1801 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1802 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1803 } else { \
1804 ipr_err(fmt": %d:%d:%d:%d\n", \
1805 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1806 (res).bus, (res).target, (res).lun); \
1807 } \
1808 }
1809
1810 #define ipr_hcam_err(hostrcb, fmt, ...) \
1811 { \
1812 if (ipr_is_device(hostrcb)) { \
1813 if ((hostrcb)->ioa_cfg->sis64) { \
1814 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1815 ipr_format_res_path(hostrcb->ioa_cfg, \
1816 hostrcb->hcam.u.error64.fd_res_path, \
1817 hostrcb->rp_buffer, \
1818 sizeof(hostrcb->rp_buffer)), \
1819 __VA_ARGS__); \
1820 } else { \
1821 ipr_ra_err((hostrcb)->ioa_cfg, \
1822 (hostrcb)->hcam.u.error.fd_res_addr, \
1823 fmt, __VA_ARGS__); \
1824 } \
1825 } else { \
1826 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1827 } \
1828 }
1829
1830 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1831 __FILE__, __func__, __LINE__)
1832
1833 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1834 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1835
1836 #define ipr_err_separator \
1837 ipr_err("----------------------------------------------------------\n")
1838
1839
1840 /*
1841 * Inlines
1842 */
1843
1844 /**
1845 * ipr_is_ioa_resource - Determine if a resource is the IOA
1846 * @res: resource entry struct
1847 *
1848 * Return value:
1849 * 1 if IOA / 0 if not IOA
1850 **/
1851 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1852 {
1853 return res->type == IPR_RES_TYPE_IOAFP;
1854 }
1855
1856 /**
1857 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1858 * @res: resource entry struct
1859 *
1860 * Return value:
1861 * 1 if AF DASD / 0 if not AF DASD
1862 **/
1863 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1864 {
1865 return res->type == IPR_RES_TYPE_AF_DASD ||
1866 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1867 }
1868
1869 /**
1870 * ipr_is_vset_device - Determine if a resource is a VSET
1871 * @res: resource entry struct
1872 *
1873 * Return value:
1874 * 1 if VSET / 0 if not VSET
1875 **/
1876 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1877 {
1878 return res->type == IPR_RES_TYPE_VOLUME_SET;
1879 }
1880
1881 /**
1882 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1883 * @res: resource entry struct
1884 *
1885 * Return value:
1886 * 1 if GSCSI / 0 if not GSCSI
1887 **/
1888 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1889 {
1890 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1891 }
1892
1893 /**
1894 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1895 * @res: resource entry struct
1896 *
1897 * Return value:
1898 * 1 if SCSI disk / 0 if not SCSI disk
1899 **/
1900 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1901 {
1902 if (ipr_is_af_dasd_device(res) ||
1903 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1904 return 1;
1905 else
1906 return 0;
1907 }
1908
1909 /**
1910 * ipr_is_gata - Determine if a resource is a generic ATA resource
1911 * @res: resource entry struct
1912 *
1913 * Return value:
1914 * 1 if GATA / 0 if not GATA
1915 **/
1916 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1917 {
1918 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1919 }
1920
1921 /**
1922 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1923 * @res: resource entry struct
1924 *
1925 * Return value:
1926 * 1 if NACA queueing model / 0 if not NACA queueing model
1927 **/
1928 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1929 {
1930 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1931 return 1;
1932 return 0;
1933 }
1934
1935 /**
1936 * ipr_is_device - Determine if the hostrcb structure is related to a device
1937 * @hostrcb: host resource control blocks struct
1938 *
1939 * Return value:
1940 * 1 if AF / 0 if not AF
1941 **/
1942 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1943 {
1944 struct ipr_res_addr *res_addr;
1945 u8 *res_path;
1946
1947 if (hostrcb->ioa_cfg->sis64) {
1948 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1949 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1950 res_path[0] == 0x81) && res_path[2] != 0xFF)
1951 return 1;
1952 } else {
1953 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1954
1955 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1956 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1957 return 1;
1958 }
1959 return 0;
1960 }
1961
1962 /**
1963 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1964 * @sdt_word: SDT address
1965 *
1966 * Return value:
1967 * 1 if format 2 / 0 if not
1968 **/
1969 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1970 {
1971 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1972
1973 switch (bar_sel) {
1974 case IPR_SDT_FMT2_BAR0_SEL:
1975 case IPR_SDT_FMT2_BAR1_SEL:
1976 case IPR_SDT_FMT2_BAR2_SEL:
1977 case IPR_SDT_FMT2_BAR3_SEL:
1978 case IPR_SDT_FMT2_BAR4_SEL:
1979 case IPR_SDT_FMT2_BAR5_SEL:
1980 case IPR_SDT_FMT2_EXP_ROM_SEL:
1981 return 1;
1982 };
1983
1984 return 0;
1985 }
1986
1987 #ifndef writeq
1988 static inline void writeq(u64 val, void __iomem *addr)
1989 {
1990 writel(((u32) (val >> 32)), addr);
1991 writel(((u32) (val)), (addr + 4));
1992 }
1993 #endif
1994
1995 #endif /* _IPR_H */
ubuntu-bionic-kernel mirror