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[SCSI] aic7xxx_old, eata_pio, ips, libsas: don't zero out sense_buffer in queuecommand
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / ips.c
1 /*****************************************************************************/
2 /* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
3 /* */
4 /* Written By: Keith Mitchell, IBM Corporation */
5 /* Jack Hammer, Adaptec, Inc. */
6 /* David Jeffery, Adaptec, Inc. */
7 /* */
8 /* Copyright (C) 2000 IBM Corporation */
9 /* Copyright (C) 2002,2003 Adaptec, Inc. */
10 /* */
11 /* This program is free software; you can redistribute it and/or modify */
12 /* it under the terms of the GNU General Public License as published by */
13 /* the Free Software Foundation; either version 2 of the License, or */
14 /* (at your option) any later version. */
15 /* */
16 /* This program is distributed in the hope that it will be useful, */
17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19 /* GNU General Public License for more details. */
20 /* */
21 /* NO WARRANTY */
22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26 /* solely responsible for determining the appropriateness of using and */
27 /* distributing the Program and assumes all risks associated with its */
28 /* exercise of rights under this Agreement, including but not limited to */
29 /* the risks and costs of program errors, damage to or loss of data, */
30 /* programs or equipment, and unavailability or interruption of operations. */
31 /* */
32 /* DISCLAIMER OF LIABILITY */
33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40 /* */
41 /* You should have received a copy of the GNU General Public License */
42 /* along with this program; if not, write to the Free Software */
43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44 /* */
45 /* Bugs/Comments/Suggestions about this driver should be mailed to: */
46 /* ipslinux@adaptec.com */
47 /* */
48 /* For system support issues, contact your local IBM Customer support. */
49 /* Directions to find IBM Customer Support for each country can be found at: */
50 /* http://www.ibm.com/planetwide/ */
51 /* */
52 /*****************************************************************************/
53
54 /*****************************************************************************/
55 /* Change Log */
56 /* */
57 /* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
58 /* 0.99.03 - Make interrupt routine handle all completed request on the */
59 /* adapter not just the first one */
60 /* - Make sure passthru commands get woken up if we run out of */
61 /* SCBs */
62 /* - Send all of the commands on the queue at once rather than */
63 /* one at a time since the card will support it. */
64 /* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
65 /* the interface to the utilities to change */
66 /* - Fix error recovery code */
67 /* 0.99.05 - Fix an oops when we get certain passthru commands */
68 /* 1.00.00 - Initial Public Release */
69 /* Functionally equivalent to 0.99.05 */
70 /* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
71 /* - Change version to 3.60 to coincide with release numbering. */
72 /* 3.60.01 - Remove bogus error check in passthru routine */
73 /* 3.60.02 - Make DCDB direction based on lookup table */
74 /* - Only allow one DCDB command to a SCSI ID at a time */
75 /* 4.00.00 - Add support for ServeRAID 4 */
76 /* 4.00.01 - Add support for First Failure Data Capture */
77 /* 4.00.02 - Fix problem with PT DCDB with no buffer */
78 /* 4.00.03 - Add alternative passthru interface */
79 /* - Add ability to flash BIOS */
80 /* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
81 /* 4.00.05 - Remove wish_block from init routine */
82 /* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
83 /* 2.3.18 and later */
84 /* - Sync with other changes from the 2.3 kernels */
85 /* 4.00.06 - Fix timeout with initial FFDC command */
86 /* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */
87 /* 4.10.00 - Add support for ServeRAID 4M/4L */
88 /* 4.10.13 - Fix for dynamic unload and proc file system */
89 /* 4.20.03 - Rename version to coincide with new release schedules */
90 /* Performance fixes */
91 /* Fix truncation of /proc files with cat */
92 /* Merge in changes through kernel 2.4.0test1ac21 */
93 /* 4.20.13 - Fix some failure cases / reset code */
94 /* - Hook into the reboot_notifier to flush the controller cache */
95 /* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
96 /* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
97 /* - Add IPSSEND Flash Support */
98 /* - Set Sense Data for Unknown SCSI Command */
99 /* - Use Slot Number from NVRAM Page 5 */
100 /* - Restore caller's DCDB Structure */
101 /* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
102 /* 4.70.13 - Don't Send CDB's if we already know the device is not present */
103 /* - Don't release HA Lock in ips_next() until SC taken off queue */
104 /* - Unregister SCSI device in ips_release() */
105 /* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
106 /* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
107 /* Code Clean-Up for 2.4.x kernel */
108 /* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
109 /* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
110 /* - Don't Issue Internal FFDC Command if there are Active Commands */
111 /* - Close Window for getting too many IOCTL's active */
112 /* 4.80.00 - Make ia64 Safe */
113 /* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
114 /* - Adjustments to Device Queue Depth */
115 /* 4.80.14 - Take all semaphores off stack */
116 /* - Clean Up New_IOCTL path */
117 /* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
118 /* - 5 second delay needed after resetting an i960 adapter */
119 /* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
120 /* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
121 /* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
122 /* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
123 /* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
124 /* 4.90.11 - Don't actually RESET unless it's physically required */
125 /* - Remove unused compile options */
126 /* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
127 /* - Get rid on IOCTL_NEW_COMMAND code */
128 /* - Add Extended DCDB Commands for Tape Support in 5I */
129 /* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
130 /* 5.10.15 - remove unused code (sem, macros, etc.) */
131 /* 5.30.00 - use __devexit_p() */
132 /* 6.00.00 - Add 6x Adapters and Battery Flash */
133 /* 6.10.00 - Remove 1G Addressing Limitations */
134 /* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
135 /* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
136 /* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */
137 /* - Fix path/name for scsi_hosts.h include for 2.6 kernels */
138 /* - Fix sort order of 7k */
139 /* - Remove 3 unused "inline" functions */
140 /* 7.12.xx - Use STATIC functions whereever possible */
141 /* - Clean up deprecated MODULE_PARM calls */
142 /* 7.12.05 - Remove Version Matching per IBM request */
143 /*****************************************************************************/
144
145 /*
146 * Conditional Compilation directives for this driver:
147 *
148 * IPS_DEBUG - Turn on debugging info
149 *
150 * Parameters:
151 *
152 * debug:<number> - Set debug level to <number>
153 * NOTE: only works when IPS_DEBUG compile directive is used.
154 * 1 - Normal debug messages
155 * 2 - Verbose debug messages
156 * 11 - Method trace (non interrupt)
157 * 12 - Method trace (includes interrupt)
158 *
159 * noi2o - Don't use I2O Queues (ServeRAID 4 only)
160 * nommap - Don't use memory mapped I/O
161 * ioctlsize - Initial size of the IOCTL buffer
162 */
163
164 #include <asm/io.h>
165 #include <asm/byteorder.h>
166 #include <asm/page.h>
167 #include <linux/stddef.h>
168 #include <linux/version.h>
169 #include <linux/string.h>
170 #include <linux/errno.h>
171 #include <linux/kernel.h>
172 #include <linux/ioport.h>
173 #include <linux/slab.h>
174 #include <linux/delay.h>
175 #include <linux/pci.h>
176 #include <linux/proc_fs.h>
177 #include <linux/reboot.h>
178 #include <linux/interrupt.h>
179
180 #include <linux/blkdev.h>
181 #include <linux/types.h>
182 #include <linux/dma-mapping.h>
183
184 #include <scsi/sg.h>
185 #include "scsi.h"
186 #include <scsi/scsi_host.h>
187
188 #include "ips.h"
189
190 #include <linux/module.h>
191
192 #include <linux/stat.h>
193
194 #include <linux/spinlock.h>
195 #include <linux/init.h>
196
197 #include <linux/smp.h>
198
199 #ifdef MODULE
200 static char *ips = NULL;
201 module_param(ips, charp, 0);
202 #endif
203
204 /*
205 * DRIVER_VER
206 */
207 #define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING
208 #define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " "
209
210 #if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
211 #warning "This driver has only been tested on the x86/ia64/x86_64 platforms"
212 #endif
213
214 #define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
215 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \
216 PCI_DMA_BIDIRECTIONAL : \
217 scb->scsi_cmd->sc_data_direction)
218
219 #ifdef IPS_DEBUG
220 #define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
221 #define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
222 #define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
223 #else
224 #define METHOD_TRACE(s, i)
225 #define DEBUG(i, s)
226 #define DEBUG_VAR(i, s, v...)
227 #endif
228
229 /*
230 * Function prototypes
231 */
232 static int ips_detect(struct scsi_host_template *);
233 static int ips_release(struct Scsi_Host *);
234 static int ips_eh_abort(struct scsi_cmnd *);
235 static int ips_eh_reset(struct scsi_cmnd *);
236 static int ips_queue(struct scsi_cmnd *, void (*)(struct scsi_cmnd *));
237 static const char *ips_info(struct Scsi_Host *);
238 static irqreturn_t do_ipsintr(int, void *);
239 static int ips_hainit(ips_ha_t *);
240 static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
241 static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
242 static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
243 static int ips_online(ips_ha_t *, ips_scb_t *);
244 static int ips_inquiry(ips_ha_t *, ips_scb_t *);
245 static int ips_rdcap(ips_ha_t *, ips_scb_t *);
246 static int ips_msense(ips_ha_t *, ips_scb_t *);
247 static int ips_reqsen(ips_ha_t *, ips_scb_t *);
248 static int ips_deallocatescbs(ips_ha_t *, int);
249 static int ips_allocatescbs(ips_ha_t *);
250 static int ips_reset_copperhead(ips_ha_t *);
251 static int ips_reset_copperhead_memio(ips_ha_t *);
252 static int ips_reset_morpheus(ips_ha_t *);
253 static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
254 static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
255 static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
256 static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
257 static int ips_isintr_copperhead(ips_ha_t *);
258 static int ips_isintr_copperhead_memio(ips_ha_t *);
259 static int ips_isintr_morpheus(ips_ha_t *);
260 static int ips_wait(ips_ha_t *, int, int);
261 static int ips_write_driver_status(ips_ha_t *, int);
262 static int ips_read_adapter_status(ips_ha_t *, int);
263 static int ips_read_subsystem_parameters(ips_ha_t *, int);
264 static int ips_read_config(ips_ha_t *, int);
265 static int ips_clear_adapter(ips_ha_t *, int);
266 static int ips_readwrite_page5(ips_ha_t *, int, int);
267 static int ips_init_copperhead(ips_ha_t *);
268 static int ips_init_copperhead_memio(ips_ha_t *);
269 static int ips_init_morpheus(ips_ha_t *);
270 static int ips_isinit_copperhead(ips_ha_t *);
271 static int ips_isinit_copperhead_memio(ips_ha_t *);
272 static int ips_isinit_morpheus(ips_ha_t *);
273 static int ips_erase_bios(ips_ha_t *);
274 static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
275 static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
276 static int ips_erase_bios_memio(ips_ha_t *);
277 static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
278 static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
279 static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
280 static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
281 static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
282 static void ips_free_flash_copperhead(ips_ha_t * ha);
283 static void ips_get_bios_version(ips_ha_t *, int);
284 static void ips_identify_controller(ips_ha_t *);
285 static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
286 static void ips_enable_int_copperhead(ips_ha_t *);
287 static void ips_enable_int_copperhead_memio(ips_ha_t *);
288 static void ips_enable_int_morpheus(ips_ha_t *);
289 static int ips_intr_copperhead(ips_ha_t *);
290 static int ips_intr_morpheus(ips_ha_t *);
291 static void ips_next(ips_ha_t *, int);
292 static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
293 static void ipsintr_done(ips_ha_t *, struct ips_scb *);
294 static void ips_done(ips_ha_t *, ips_scb_t *);
295 static void ips_free(ips_ha_t *);
296 static void ips_init_scb(ips_ha_t *, ips_scb_t *);
297 static void ips_freescb(ips_ha_t *, ips_scb_t *);
298 static void ips_setup_funclist(ips_ha_t *);
299 static void ips_statinit(ips_ha_t *);
300 static void ips_statinit_memio(ips_ha_t *);
301 static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t);
302 static void ips_ffdc_reset(ips_ha_t *, int);
303 static void ips_ffdc_time(ips_ha_t *);
304 static uint32_t ips_statupd_copperhead(ips_ha_t *);
305 static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
306 static uint32_t ips_statupd_morpheus(ips_ha_t *);
307 static ips_scb_t *ips_getscb(ips_ha_t *);
308 static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
309 static void ips_putq_wait_tail(ips_wait_queue_t *, struct scsi_cmnd *);
310 static void ips_putq_copp_tail(ips_copp_queue_t *,
311 ips_copp_wait_item_t *);
312 static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
313 static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
314 static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_t *);
315 static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_t *,
316 struct scsi_cmnd *);
317 static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
318 ips_copp_wait_item_t *);
319 static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
320
321 static int ips_is_passthru(struct scsi_cmnd *);
322 static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int);
323 static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
324 static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
325 static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data,
326 unsigned int count);
327 static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data,
328 unsigned int count);
329
330 static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
331 static int ips_host_info(ips_ha_t *, char *, off_t, int);
332 static void copy_mem_info(IPS_INFOSTR *, char *, int);
333 static int copy_info(IPS_INFOSTR *, char *, ...);
334 static int ips_abort_init(ips_ha_t * ha, int index);
335 static int ips_init_phase2(int index);
336
337 static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
338 static int ips_register_scsi(int index);
339
340 static int ips_poll_for_flush_complete(ips_ha_t * ha);
341 static void ips_flush_and_reset(ips_ha_t *ha);
342
343 /*
344 * global variables
345 */
346 static const char ips_name[] = "ips";
347 static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
348 static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
349 static unsigned int ips_next_controller;
350 static unsigned int ips_num_controllers;
351 static unsigned int ips_released_controllers;
352 static int ips_hotplug;
353 static int ips_cmd_timeout = 60;
354 static int ips_reset_timeout = 60 * 5;
355 static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
356 static int ips_force_i2o = 1; /* Always use I2O command delivery */
357 static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
358 static int ips_cd_boot; /* Booting from Manager CD */
359 static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
360 static dma_addr_t ips_flashbusaddr;
361 static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
362 static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
363 static struct scsi_host_template ips_driver_template = {
364 .detect = ips_detect,
365 .release = ips_release,
366 .info = ips_info,
367 .queuecommand = ips_queue,
368 .eh_abort_handler = ips_eh_abort,
369 .eh_host_reset_handler = ips_eh_reset,
370 .proc_name = "ips",
371 .proc_info = ips_proc_info,
372 .slave_configure = ips_slave_configure,
373 .bios_param = ips_biosparam,
374 .this_id = -1,
375 .sg_tablesize = IPS_MAX_SG,
376 .cmd_per_lun = 3,
377 .use_clustering = ENABLE_CLUSTERING,
378 };
379
380
381 /* This table describes all ServeRAID Adapters */
382 static struct pci_device_id ips_pci_table[] = {
383 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
384 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
385 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
386 { 0, }
387 };
388
389 MODULE_DEVICE_TABLE( pci, ips_pci_table );
390
391 static char ips_hot_plug_name[] = "ips";
392
393 static int __devinit ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
394 static void __devexit ips_remove_device(struct pci_dev *pci_dev);
395
396 static struct pci_driver ips_pci_driver = {
397 .name = ips_hot_plug_name,
398 .id_table = ips_pci_table,
399 .probe = ips_insert_device,
400 .remove = __devexit_p(ips_remove_device),
401 };
402
403
404 /*
405 * Necessary forward function protoypes
406 */
407 static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
408
409 #define MAX_ADAPTER_NAME 15
410
411 static char ips_adapter_name[][30] = {
412 "ServeRAID",
413 "ServeRAID II",
414 "ServeRAID on motherboard",
415 "ServeRAID on motherboard",
416 "ServeRAID 3H",
417 "ServeRAID 3L",
418 "ServeRAID 4H",
419 "ServeRAID 4M",
420 "ServeRAID 4L",
421 "ServeRAID 4Mx",
422 "ServeRAID 4Lx",
423 "ServeRAID 5i",
424 "ServeRAID 5i",
425 "ServeRAID 6M",
426 "ServeRAID 6i",
427 "ServeRAID 7t",
428 "ServeRAID 7k",
429 "ServeRAID 7M"
430 };
431
432 static struct notifier_block ips_notifier = {
433 ips_halt, NULL, 0
434 };
435
436 /*
437 * Direction table
438 */
439 static char ips_command_direction[] = {
440 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
441 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
442 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
443 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
444 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
445 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
446 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
447 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
448 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
449 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
450 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
451 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
452 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
453 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
454 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
455 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
456 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
457 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
458 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
459 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
460 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
461 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
462 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
463 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
464 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
465 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
466 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
467 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
468 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
469 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
470 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
471 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
472 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
473 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
474 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
475 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
476 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
477 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
478 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
479 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
480 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
482 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
483 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
484 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
485 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
486 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
487 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
488 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
489 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
490 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
491 };
492
493
494 /****************************************************************************/
495 /* */
496 /* Routine Name: ips_setup */
497 /* */
498 /* Routine Description: */
499 /* */
500 /* setup parameters to the driver */
501 /* */
502 /****************************************************************************/
503 static int
504 ips_setup(char *ips_str)
505 {
506
507 int i;
508 char *key;
509 char *value;
510 IPS_OPTION options[] = {
511 {"noi2o", &ips_force_i2o, 0},
512 {"nommap", &ips_force_memio, 0},
513 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
514 {"cdboot", &ips_cd_boot, 0},
515 {"maxcmds", &MaxLiteCmds, 32},
516 };
517
518 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
519 /* Search for value */
520 while ((key = strsep(&ips_str, ",."))) {
521 if (!*key)
522 continue;
523 value = strchr(key, ':');
524 if (value)
525 *value++ = '\0';
526 /*
527 * We now have key/value pairs.
528 * Update the variables
529 */
530 for (i = 0; i < ARRAY_SIZE(options); i++) {
531 if (strnicmp
532 (key, options[i].option_name,
533 strlen(options[i].option_name)) == 0) {
534 if (value)
535 *options[i].option_flag =
536 simple_strtoul(value, NULL, 0);
537 else
538 *options[i].option_flag =
539 options[i].option_value;
540 break;
541 }
542 }
543 }
544
545 return (1);
546 }
547
548 __setup("ips=", ips_setup);
549
550 /****************************************************************************/
551 /* */
552 /* Routine Name: ips_detect */
553 /* */
554 /* Routine Description: */
555 /* */
556 /* Detect and initialize the driver */
557 /* */
558 /* NOTE: this routine is called under the io_request_lock spinlock */
559 /* */
560 /****************************************************************************/
561 static int
562 ips_detect(struct scsi_host_template * SHT)
563 {
564 int i;
565
566 METHOD_TRACE("ips_detect", 1);
567
568 #ifdef MODULE
569 if (ips)
570 ips_setup(ips);
571 #endif
572
573 for (i = 0; i < ips_num_controllers; i++) {
574 if (ips_register_scsi(i))
575 ips_free(ips_ha[i]);
576 ips_released_controllers++;
577 }
578 ips_hotplug = 1;
579 return (ips_num_controllers);
580 }
581
582 /****************************************************************************/
583 /* configure the function pointers to use the functions that will work */
584 /* with the found version of the adapter */
585 /****************************************************************************/
586 static void
587 ips_setup_funclist(ips_ha_t * ha)
588 {
589
590 /*
591 * Setup Functions
592 */
593 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
594 /* morpheus / marco / sebring */
595 ha->func.isintr = ips_isintr_morpheus;
596 ha->func.isinit = ips_isinit_morpheus;
597 ha->func.issue = ips_issue_i2o_memio;
598 ha->func.init = ips_init_morpheus;
599 ha->func.statupd = ips_statupd_morpheus;
600 ha->func.reset = ips_reset_morpheus;
601 ha->func.intr = ips_intr_morpheus;
602 ha->func.enableint = ips_enable_int_morpheus;
603 } else if (IPS_USE_MEMIO(ha)) {
604 /* copperhead w/MEMIO */
605 ha->func.isintr = ips_isintr_copperhead_memio;
606 ha->func.isinit = ips_isinit_copperhead_memio;
607 ha->func.init = ips_init_copperhead_memio;
608 ha->func.statupd = ips_statupd_copperhead_memio;
609 ha->func.statinit = ips_statinit_memio;
610 ha->func.reset = ips_reset_copperhead_memio;
611 ha->func.intr = ips_intr_copperhead;
612 ha->func.erasebios = ips_erase_bios_memio;
613 ha->func.programbios = ips_program_bios_memio;
614 ha->func.verifybios = ips_verify_bios_memio;
615 ha->func.enableint = ips_enable_int_copperhead_memio;
616 if (IPS_USE_I2O_DELIVER(ha))
617 ha->func.issue = ips_issue_i2o_memio;
618 else
619 ha->func.issue = ips_issue_copperhead_memio;
620 } else {
621 /* copperhead */
622 ha->func.isintr = ips_isintr_copperhead;
623 ha->func.isinit = ips_isinit_copperhead;
624 ha->func.init = ips_init_copperhead;
625 ha->func.statupd = ips_statupd_copperhead;
626 ha->func.statinit = ips_statinit;
627 ha->func.reset = ips_reset_copperhead;
628 ha->func.intr = ips_intr_copperhead;
629 ha->func.erasebios = ips_erase_bios;
630 ha->func.programbios = ips_program_bios;
631 ha->func.verifybios = ips_verify_bios;
632 ha->func.enableint = ips_enable_int_copperhead;
633
634 if (IPS_USE_I2O_DELIVER(ha))
635 ha->func.issue = ips_issue_i2o;
636 else
637 ha->func.issue = ips_issue_copperhead;
638 }
639 }
640
641 /****************************************************************************/
642 /* */
643 /* Routine Name: ips_release */
644 /* */
645 /* Routine Description: */
646 /* */
647 /* Remove a driver */
648 /* */
649 /****************************************************************************/
650 static int
651 ips_release(struct Scsi_Host *sh)
652 {
653 ips_scb_t *scb;
654 ips_ha_t *ha;
655 int i;
656
657 METHOD_TRACE("ips_release", 1);
658
659 scsi_remove_host(sh);
660
661 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
662
663 if (i == IPS_MAX_ADAPTERS) {
664 printk(KERN_WARNING
665 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
666 BUG();
667 return (FALSE);
668 }
669
670 ha = IPS_HA(sh);
671
672 if (!ha)
673 return (FALSE);
674
675 /* flush the cache on the controller */
676 scb = &ha->scbs[ha->max_cmds - 1];
677
678 ips_init_scb(ha, scb);
679
680 scb->timeout = ips_cmd_timeout;
681 scb->cdb[0] = IPS_CMD_FLUSH;
682
683 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
684 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
685 scb->cmd.flush_cache.state = IPS_NORM_STATE;
686 scb->cmd.flush_cache.reserved = 0;
687 scb->cmd.flush_cache.reserved2 = 0;
688 scb->cmd.flush_cache.reserved3 = 0;
689 scb->cmd.flush_cache.reserved4 = 0;
690
691 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
692
693 /* send command */
694 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
695 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
696
697 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
698
699 ips_sh[i] = NULL;
700 ips_ha[i] = NULL;
701
702 /* free extra memory */
703 ips_free(ha);
704
705 /* free IRQ */
706 free_irq(ha->pcidev->irq, ha);
707
708 scsi_host_put(sh);
709
710 ips_released_controllers++;
711
712 return (FALSE);
713 }
714
715 /****************************************************************************/
716 /* */
717 /* Routine Name: ips_halt */
718 /* */
719 /* Routine Description: */
720 /* */
721 /* Perform cleanup when the system reboots */
722 /* */
723 /****************************************************************************/
724 static int
725 ips_halt(struct notifier_block *nb, ulong event, void *buf)
726 {
727 ips_scb_t *scb;
728 ips_ha_t *ha;
729 int i;
730
731 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
732 (event != SYS_POWER_OFF))
733 return (NOTIFY_DONE);
734
735 for (i = 0; i < ips_next_controller; i++) {
736 ha = (ips_ha_t *) ips_ha[i];
737
738 if (!ha)
739 continue;
740
741 if (!ha->active)
742 continue;
743
744 /* flush the cache on the controller */
745 scb = &ha->scbs[ha->max_cmds - 1];
746
747 ips_init_scb(ha, scb);
748
749 scb->timeout = ips_cmd_timeout;
750 scb->cdb[0] = IPS_CMD_FLUSH;
751
752 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
753 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
754 scb->cmd.flush_cache.state = IPS_NORM_STATE;
755 scb->cmd.flush_cache.reserved = 0;
756 scb->cmd.flush_cache.reserved2 = 0;
757 scb->cmd.flush_cache.reserved3 = 0;
758 scb->cmd.flush_cache.reserved4 = 0;
759
760 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
761
762 /* send command */
763 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
764 IPS_FAILURE)
765 IPS_PRINTK(KERN_WARNING, ha->pcidev,
766 "Incomplete Flush.\n");
767 else
768 IPS_PRINTK(KERN_WARNING, ha->pcidev,
769 "Flushing Complete.\n");
770 }
771
772 return (NOTIFY_OK);
773 }
774
775 /****************************************************************************/
776 /* */
777 /* Routine Name: ips_eh_abort */
778 /* */
779 /* Routine Description: */
780 /* */
781 /* Abort a command (using the new error code stuff) */
782 /* Note: this routine is called under the io_request_lock */
783 /****************************************************************************/
784 int ips_eh_abort(struct scsi_cmnd *SC)
785 {
786 ips_ha_t *ha;
787 ips_copp_wait_item_t *item;
788 int ret;
789 struct Scsi_Host *host;
790
791 METHOD_TRACE("ips_eh_abort", 1);
792
793 if (!SC)
794 return (FAILED);
795
796 host = SC->device->host;
797 ha = (ips_ha_t *) SC->device->host->hostdata;
798
799 if (!ha)
800 return (FAILED);
801
802 if (!ha->active)
803 return (FAILED);
804
805 spin_lock(host->host_lock);
806
807 /* See if the command is on the copp queue */
808 item = ha->copp_waitlist.head;
809 while ((item) && (item->scsi_cmd != SC))
810 item = item->next;
811
812 if (item) {
813 /* Found it */
814 ips_removeq_copp(&ha->copp_waitlist, item);
815 ret = (SUCCESS);
816
817 /* See if the command is on the wait queue */
818 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
819 /* command not sent yet */
820 ret = (SUCCESS);
821 } else {
822 /* command must have already been sent */
823 ret = (FAILED);
824 }
825
826 spin_unlock(host->host_lock);
827 return ret;
828 }
829
830 /****************************************************************************/
831 /* */
832 /* Routine Name: ips_eh_reset */
833 /* */
834 /* Routine Description: */
835 /* */
836 /* Reset the controller (with new eh error code) */
837 /* */
838 /* NOTE: this routine is called under the io_request_lock spinlock */
839 /* */
840 /****************************************************************************/
841 static int __ips_eh_reset(struct scsi_cmnd *SC)
842 {
843 int ret;
844 int i;
845 ips_ha_t *ha;
846 ips_scb_t *scb;
847 ips_copp_wait_item_t *item;
848
849 METHOD_TRACE("ips_eh_reset", 1);
850
851 #ifdef NO_IPS_RESET
852 return (FAILED);
853 #else
854
855 if (!SC) {
856 DEBUG(1, "Reset called with NULL scsi command");
857
858 return (FAILED);
859 }
860
861 ha = (ips_ha_t *) SC->device->host->hostdata;
862
863 if (!ha) {
864 DEBUG(1, "Reset called with NULL ha struct");
865
866 return (FAILED);
867 }
868
869 if (!ha->active)
870 return (FAILED);
871
872 /* See if the command is on the copp queue */
873 item = ha->copp_waitlist.head;
874 while ((item) && (item->scsi_cmd != SC))
875 item = item->next;
876
877 if (item) {
878 /* Found it */
879 ips_removeq_copp(&ha->copp_waitlist, item);
880 return (SUCCESS);
881 }
882
883 /* See if the command is on the wait queue */
884 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
885 /* command not sent yet */
886 return (SUCCESS);
887 }
888
889 /* An explanation for the casual observer: */
890 /* Part of the function of a RAID controller is automatic error */
891 /* detection and recovery. As such, the only problem that physically */
892 /* resetting an adapter will ever fix is when, for some reason, */
893 /* the driver is not successfully communicating with the adapter. */
894 /* Therefore, we will attempt to flush this adapter. If that succeeds, */
895 /* then there's no real purpose in a physical reset. This will complete */
896 /* much faster and avoids any problems that might be caused by a */
897 /* physical reset ( such as having to fail all the outstanding I/O's ). */
898
899 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
900 scb = &ha->scbs[ha->max_cmds - 1];
901
902 ips_init_scb(ha, scb);
903
904 scb->timeout = ips_cmd_timeout;
905 scb->cdb[0] = IPS_CMD_FLUSH;
906
907 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
908 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
909 scb->cmd.flush_cache.state = IPS_NORM_STATE;
910 scb->cmd.flush_cache.reserved = 0;
911 scb->cmd.flush_cache.reserved2 = 0;
912 scb->cmd.flush_cache.reserved3 = 0;
913 scb->cmd.flush_cache.reserved4 = 0;
914
915 /* Attempt the flush command */
916 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
917 if (ret == IPS_SUCCESS) {
918 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
919 "Reset Request - Flushed Cache\n");
920 return (SUCCESS);
921 }
922 }
923
924 /* Either we can't communicate with the adapter or it's an IOCTL request */
925 /* from a utility. A physical reset is needed at this point. */
926
927 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
928
929 /*
930 * command must have already been sent
931 * reset the controller
932 */
933 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
934 ret = (*ha->func.reset) (ha);
935
936 if (!ret) {
937 struct scsi_cmnd *scsi_cmd;
938
939 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
940 "Controller reset failed - controller now offline.\n");
941
942 /* Now fail all of the active commands */
943 DEBUG_VAR(1, "(%s%d) Failing active commands",
944 ips_name, ha->host_num);
945
946 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
947 scb->scsi_cmd->result = DID_ERROR << 16;
948 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
949 ips_freescb(ha, scb);
950 }
951
952 /* Now fail all of the pending commands */
953 DEBUG_VAR(1, "(%s%d) Failing pending commands",
954 ips_name, ha->host_num);
955
956 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
957 scsi_cmd->result = DID_ERROR;
958 scsi_cmd->scsi_done(scsi_cmd);
959 }
960
961 ha->active = FALSE;
962 return (FAILED);
963 }
964
965 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
966 struct scsi_cmnd *scsi_cmd;
967
968 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
969 "Controller reset failed - controller now offline.\n");
970
971 /* Now fail all of the active commands */
972 DEBUG_VAR(1, "(%s%d) Failing active commands",
973 ips_name, ha->host_num);
974
975 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
976 scb->scsi_cmd->result = DID_ERROR << 16;
977 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
978 ips_freescb(ha, scb);
979 }
980
981 /* Now fail all of the pending commands */
982 DEBUG_VAR(1, "(%s%d) Failing pending commands",
983 ips_name, ha->host_num);
984
985 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
986 scsi_cmd->result = DID_ERROR << 16;
987 scsi_cmd->scsi_done(scsi_cmd);
988 }
989
990 ha->active = FALSE;
991 return (FAILED);
992 }
993
994 /* FFDC */
995 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
996 struct timeval tv;
997
998 do_gettimeofday(&tv);
999 ha->last_ffdc = tv.tv_sec;
1000 ha->reset_count++;
1001 ips_ffdc_reset(ha, IPS_INTR_IORL);
1002 }
1003
1004 /* Now fail all of the active commands */
1005 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
1006
1007 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1008 scb->scsi_cmd->result =
1009 (DID_RESET << 16) | (SUGGEST_RETRY << 24);
1010 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1011 ips_freescb(ha, scb);
1012 }
1013
1014 /* Reset DCDB active command bits */
1015 for (i = 1; i < ha->nbus; i++)
1016 ha->dcdb_active[i - 1] = 0;
1017
1018 /* Reset the number of active IOCTLs */
1019 ha->num_ioctl = 0;
1020
1021 ips_next(ha, IPS_INTR_IORL);
1022
1023 return (SUCCESS);
1024 #endif /* NO_IPS_RESET */
1025
1026 }
1027
1028 static int ips_eh_reset(struct scsi_cmnd *SC)
1029 {
1030 int rc;
1031
1032 spin_lock_irq(SC->device->host->host_lock);
1033 rc = __ips_eh_reset(SC);
1034 spin_unlock_irq(SC->device->host->host_lock);
1035
1036 return rc;
1037 }
1038
1039 /****************************************************************************/
1040 /* */
1041 /* Routine Name: ips_queue */
1042 /* */
1043 /* Routine Description: */
1044 /* */
1045 /* Send a command to the controller */
1046 /* */
1047 /* NOTE: */
1048 /* Linux obtains io_request_lock before calling this function */
1049 /* */
1050 /****************************************************************************/
1051 static int ips_queue(struct scsi_cmnd *SC, void (*done) (struct scsi_cmnd *))
1052 {
1053 ips_ha_t *ha;
1054 ips_passthru_t *pt;
1055
1056 METHOD_TRACE("ips_queue", 1);
1057
1058 ha = (ips_ha_t *) SC->device->host->hostdata;
1059
1060 if (!ha)
1061 return (1);
1062
1063 if (!ha->active)
1064 return (DID_ERROR);
1065
1066 if (ips_is_passthru(SC)) {
1067 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1068 SC->result = DID_BUS_BUSY << 16;
1069 done(SC);
1070
1071 return (0);
1072 }
1073 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1074 SC->result = DID_BUS_BUSY << 16;
1075 done(SC);
1076
1077 return (0);
1078 }
1079
1080 SC->scsi_done = done;
1081
1082 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1083 ips_name,
1084 ha->host_num,
1085 SC->cmnd[0],
1086 SC->device->channel, SC->device->id, SC->device->lun);
1087
1088 /* Check for command to initiator IDs */
1089 if ((scmd_channel(SC) > 0)
1090 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) {
1091 SC->result = DID_NO_CONNECT << 16;
1092 done(SC);
1093
1094 return (0);
1095 }
1096
1097 if (ips_is_passthru(SC)) {
1098
1099 ips_copp_wait_item_t *scratch;
1100
1101 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */
1102 /* There can never be any system activity ( network or disk ), but check */
1103 /* anyway just as a good practice. */
1104 pt = (ips_passthru_t *) scsi_sglist(SC);
1105 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1106 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1107 if (ha->scb_activelist.count != 0) {
1108 SC->result = DID_BUS_BUSY << 16;
1109 done(SC);
1110 return (0);
1111 }
1112 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1113 __ips_eh_reset(SC);
1114 SC->result = DID_OK << 16;
1115 SC->scsi_done(SC);
1116 return (0);
1117 }
1118
1119 /* allocate space for the scribble */
1120 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1121
1122 if (!scratch) {
1123 SC->result = DID_ERROR << 16;
1124 done(SC);
1125
1126 return (0);
1127 }
1128
1129 scratch->scsi_cmd = SC;
1130 scratch->next = NULL;
1131
1132 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1133 } else {
1134 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1135 }
1136
1137 ips_next(ha, IPS_INTR_IORL);
1138
1139 return (0);
1140 }
1141
1142 /****************************************************************************/
1143 /* */
1144 /* Routine Name: ips_biosparam */
1145 /* */
1146 /* Routine Description: */
1147 /* */
1148 /* Set bios geometry for the controller */
1149 /* */
1150 /****************************************************************************/
1151 static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1152 sector_t capacity, int geom[])
1153 {
1154 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1155 int heads;
1156 int sectors;
1157 int cylinders;
1158
1159 METHOD_TRACE("ips_biosparam", 1);
1160
1161 if (!ha)
1162 /* ?!?! host adater info invalid */
1163 return (0);
1164
1165 if (!ha->active)
1166 return (0);
1167
1168 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1169 /* ?!?! Enquiry command failed */
1170 return (0);
1171
1172 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1173 heads = IPS_NORM_HEADS;
1174 sectors = IPS_NORM_SECTORS;
1175 } else {
1176 heads = IPS_COMP_HEADS;
1177 sectors = IPS_COMP_SECTORS;
1178 }
1179
1180 cylinders = (unsigned long) capacity / (heads * sectors);
1181
1182 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1183 heads, sectors, cylinders);
1184
1185 geom[0] = heads;
1186 geom[1] = sectors;
1187 geom[2] = cylinders;
1188
1189 return (0);
1190 }
1191
1192 /****************************************************************************/
1193 /* */
1194 /* Routine Name: ips_slave_configure */
1195 /* */
1196 /* Routine Description: */
1197 /* */
1198 /* Set queue depths on devices once scan is complete */
1199 /* */
1200 /****************************************************************************/
1201 static int
1202 ips_slave_configure(struct scsi_device * SDptr)
1203 {
1204 ips_ha_t *ha;
1205 int min;
1206
1207 ha = IPS_HA(SDptr->host);
1208 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1209 min = ha->max_cmds / 2;
1210 if (ha->enq->ucLogDriveCount <= 2)
1211 min = ha->max_cmds - 1;
1212 scsi_adjust_queue_depth(SDptr, MSG_ORDERED_TAG, min);
1213 }
1214
1215 SDptr->skip_ms_page_8 = 1;
1216 SDptr->skip_ms_page_3f = 1;
1217 return 0;
1218 }
1219
1220 /****************************************************************************/
1221 /* */
1222 /* Routine Name: do_ipsintr */
1223 /* */
1224 /* Routine Description: */
1225 /* */
1226 /* Wrapper for the interrupt handler */
1227 /* */
1228 /****************************************************************************/
1229 static irqreturn_t
1230 do_ipsintr(int irq, void *dev_id)
1231 {
1232 ips_ha_t *ha;
1233 struct Scsi_Host *host;
1234 int irqstatus;
1235
1236 METHOD_TRACE("do_ipsintr", 2);
1237
1238 ha = (ips_ha_t *) dev_id;
1239 if (!ha)
1240 return IRQ_NONE;
1241 host = ips_sh[ha->host_num];
1242 /* interrupt during initialization */
1243 if (!host) {
1244 (*ha->func.intr) (ha);
1245 return IRQ_HANDLED;
1246 }
1247
1248 spin_lock(host->host_lock);
1249
1250 if (!ha->active) {
1251 spin_unlock(host->host_lock);
1252 return IRQ_HANDLED;
1253 }
1254
1255 irqstatus = (*ha->func.intr) (ha);
1256
1257 spin_unlock(host->host_lock);
1258
1259 /* start the next command */
1260 ips_next(ha, IPS_INTR_ON);
1261 return IRQ_RETVAL(irqstatus);
1262 }
1263
1264 /****************************************************************************/
1265 /* */
1266 /* Routine Name: ips_intr_copperhead */
1267 /* */
1268 /* Routine Description: */
1269 /* */
1270 /* Polling interrupt handler */
1271 /* */
1272 /* ASSUMES interrupts are disabled */
1273 /* */
1274 /****************************************************************************/
1275 int
1276 ips_intr_copperhead(ips_ha_t * ha)
1277 {
1278 ips_stat_t *sp;
1279 ips_scb_t *scb;
1280 IPS_STATUS cstatus;
1281 int intrstatus;
1282
1283 METHOD_TRACE("ips_intr", 2);
1284
1285 if (!ha)
1286 return 0;
1287
1288 if (!ha->active)
1289 return 0;
1290
1291 intrstatus = (*ha->func.isintr) (ha);
1292
1293 if (!intrstatus) {
1294 /*
1295 * Unexpected/Shared interrupt
1296 */
1297
1298 return 0;
1299 }
1300
1301 while (TRUE) {
1302 sp = &ha->sp;
1303
1304 intrstatus = (*ha->func.isintr) (ha);
1305
1306 if (!intrstatus)
1307 break;
1308 else
1309 cstatus.value = (*ha->func.statupd) (ha);
1310
1311 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1312 /* Spurious Interupt ? */
1313 continue;
1314 }
1315
1316 ips_chkstatus(ha, &cstatus);
1317 scb = (ips_scb_t *) sp->scb_addr;
1318
1319 /*
1320 * use the callback function to finish things up
1321 * NOTE: interrupts are OFF for this
1322 */
1323 (*scb->callback) (ha, scb);
1324 } /* end while */
1325 return 1;
1326 }
1327
1328 /****************************************************************************/
1329 /* */
1330 /* Routine Name: ips_intr_morpheus */
1331 /* */
1332 /* Routine Description: */
1333 /* */
1334 /* Polling interrupt handler */
1335 /* */
1336 /* ASSUMES interrupts are disabled */
1337 /* */
1338 /****************************************************************************/
1339 int
1340 ips_intr_morpheus(ips_ha_t * ha)
1341 {
1342 ips_stat_t *sp;
1343 ips_scb_t *scb;
1344 IPS_STATUS cstatus;
1345 int intrstatus;
1346
1347 METHOD_TRACE("ips_intr_morpheus", 2);
1348
1349 if (!ha)
1350 return 0;
1351
1352 if (!ha->active)
1353 return 0;
1354
1355 intrstatus = (*ha->func.isintr) (ha);
1356
1357 if (!intrstatus) {
1358 /*
1359 * Unexpected/Shared interrupt
1360 */
1361
1362 return 0;
1363 }
1364
1365 while (TRUE) {
1366 sp = &ha->sp;
1367
1368 intrstatus = (*ha->func.isintr) (ha);
1369
1370 if (!intrstatus)
1371 break;
1372 else
1373 cstatus.value = (*ha->func.statupd) (ha);
1374
1375 if (cstatus.value == 0xffffffff)
1376 /* No more to process */
1377 break;
1378
1379 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1380 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1381 "Spurious interrupt; no ccb.\n");
1382
1383 continue;
1384 }
1385
1386 ips_chkstatus(ha, &cstatus);
1387 scb = (ips_scb_t *) sp->scb_addr;
1388
1389 /*
1390 * use the callback function to finish things up
1391 * NOTE: interrupts are OFF for this
1392 */
1393 (*scb->callback) (ha, scb);
1394 } /* end while */
1395 return 1;
1396 }
1397
1398 /****************************************************************************/
1399 /* */
1400 /* Routine Name: ips_info */
1401 /* */
1402 /* Routine Description: */
1403 /* */
1404 /* Return info about the driver */
1405 /* */
1406 /****************************************************************************/
1407 static const char *
1408 ips_info(struct Scsi_Host *SH)
1409 {
1410 static char buffer[256];
1411 char *bp;
1412 ips_ha_t *ha;
1413
1414 METHOD_TRACE("ips_info", 1);
1415
1416 ha = IPS_HA(SH);
1417
1418 if (!ha)
1419 return (NULL);
1420
1421 bp = &buffer[0];
1422 memset(bp, 0, sizeof (buffer));
1423
1424 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1425 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1426
1427 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1428 strcat(bp, " <");
1429 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1430 strcat(bp, ">");
1431 }
1432
1433 return (bp);
1434 }
1435
1436 /****************************************************************************/
1437 /* */
1438 /* Routine Name: ips_proc_info */
1439 /* */
1440 /* Routine Description: */
1441 /* */
1442 /* The passthru interface for the driver */
1443 /* */
1444 /****************************************************************************/
1445 static int
1446 ips_proc_info(struct Scsi_Host *host, char *buffer, char **start, off_t offset,
1447 int length, int func)
1448 {
1449 int i;
1450 int ret;
1451 ips_ha_t *ha = NULL;
1452
1453 METHOD_TRACE("ips_proc_info", 1);
1454
1455 /* Find our host structure */
1456 for (i = 0; i < ips_next_controller; i++) {
1457 if (ips_sh[i]) {
1458 if (ips_sh[i] == host) {
1459 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1460 break;
1461 }
1462 }
1463 }
1464
1465 if (!ha)
1466 return (-EINVAL);
1467
1468 if (func) {
1469 /* write */
1470 return (0);
1471 } else {
1472 /* read */
1473 if (start)
1474 *start = buffer;
1475
1476 ret = ips_host_info(ha, buffer, offset, length);
1477
1478 return (ret);
1479 }
1480 }
1481
1482 /*--------------------------------------------------------------------------*/
1483 /* Helper Functions */
1484 /*--------------------------------------------------------------------------*/
1485
1486 /****************************************************************************/
1487 /* */
1488 /* Routine Name: ips_is_passthru */
1489 /* */
1490 /* Routine Description: */
1491 /* */
1492 /* Determine if the specified SCSI command is really a passthru command */
1493 /* */
1494 /****************************************************************************/
1495 static int ips_is_passthru(struct scsi_cmnd *SC)
1496 {
1497 unsigned long flags;
1498
1499 METHOD_TRACE("ips_is_passthru", 1);
1500
1501 if (!SC)
1502 return (0);
1503
1504 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1505 (SC->device->channel == 0) &&
1506 (SC->device->id == IPS_ADAPTER_ID) &&
1507 (SC->device->lun == 0) && scsi_sglist(SC)) {
1508 struct scatterlist *sg = scsi_sglist(SC);
1509 char *buffer;
1510
1511 /* kmap_atomic() ensures addressability of the user buffer.*/
1512 /* local_irq_save() protects the KM_IRQ0 address slot. */
1513 local_irq_save(flags);
1514 buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
1515 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1516 buffer[2] == 'P' && buffer[3] == 'P') {
1517 kunmap_atomic(buffer - sg->offset, KM_IRQ0);
1518 local_irq_restore(flags);
1519 return 1;
1520 }
1521 kunmap_atomic(buffer - sg->offset, KM_IRQ0);
1522 local_irq_restore(flags);
1523 }
1524 return 0;
1525 }
1526
1527 /****************************************************************************/
1528 /* */
1529 /* Routine Name: ips_alloc_passthru_buffer */
1530 /* */
1531 /* Routine Description: */
1532 /* allocate a buffer large enough for the ioctl data if the ioctl buffer */
1533 /* is too small or doesn't exist */
1534 /****************************************************************************/
1535 static int
1536 ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1537 {
1538 void *bigger_buf;
1539 dma_addr_t dma_busaddr;
1540
1541 if (ha->ioctl_data && length <= ha->ioctl_len)
1542 return 0;
1543 /* there is no buffer or it's not big enough, allocate a new one */
1544 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr);
1545 if (bigger_buf) {
1546 /* free the old memory */
1547 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data,
1548 ha->ioctl_busaddr);
1549 /* use the new memory */
1550 ha->ioctl_data = (char *) bigger_buf;
1551 ha->ioctl_len = length;
1552 ha->ioctl_busaddr = dma_busaddr;
1553 } else {
1554 return -1;
1555 }
1556 return 0;
1557 }
1558
1559 /****************************************************************************/
1560 /* */
1561 /* Routine Name: ips_make_passthru */
1562 /* */
1563 /* Routine Description: */
1564 /* */
1565 /* Make a passthru command out of the info in the Scsi block */
1566 /* */
1567 /****************************************************************************/
1568 static int
1569 ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr)
1570 {
1571 ips_passthru_t *pt;
1572 int length = 0;
1573 int i, ret;
1574 struct scatterlist *sg = scsi_sglist(SC);
1575
1576 METHOD_TRACE("ips_make_passthru", 1);
1577
1578 scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i)
1579 length += sg[i].length;
1580
1581 if (length < sizeof (ips_passthru_t)) {
1582 /* wrong size */
1583 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1584 ips_name, ha->host_num);
1585 return (IPS_FAILURE);
1586 }
1587 if (ips_alloc_passthru_buffer(ha, length)) {
1588 /* allocation failure! If ha->ioctl_data exists, use it to return
1589 some error codes. Return a failed command to the scsi layer. */
1590 if (ha->ioctl_data) {
1591 pt = (ips_passthru_t *) ha->ioctl_data;
1592 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1593 pt->BasicStatus = 0x0B;
1594 pt->ExtendedStatus = 0x00;
1595 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1596 }
1597 return IPS_FAILURE;
1598 }
1599 ha->ioctl_datasize = length;
1600
1601 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1602 pt = (ips_passthru_t *) ha->ioctl_data;
1603
1604 /*
1605 * Some notes about the passthru interface used
1606 *
1607 * IF the scsi op_code == 0x0d then we assume
1608 * that the data came along with/goes with the
1609 * packet we received from the sg driver. In this
1610 * case the CmdBSize field of the pt structure is
1611 * used for the size of the buffer.
1612 */
1613
1614 switch (pt->CoppCmd) {
1615 case IPS_NUMCTRLS:
1616 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1617 &ips_num_controllers, sizeof (int));
1618 ips_scmd_buf_write(SC, ha->ioctl_data,
1619 sizeof (ips_passthru_t) + sizeof (int));
1620 SC->result = DID_OK << 16;
1621
1622 return (IPS_SUCCESS_IMM);
1623
1624 case IPS_COPPUSRCMD:
1625 case IPS_COPPIOCCMD:
1626 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1627 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1628 /* wrong size */
1629 DEBUG_VAR(1,
1630 "(%s%d) Passthru structure wrong size",
1631 ips_name, ha->host_num);
1632
1633 return (IPS_FAILURE);
1634 }
1635
1636 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
1637 pt->CoppCP.cmd.flashfw.op_code ==
1638 IPS_CMD_RW_BIOSFW) {
1639 ret = ips_flash_copperhead(ha, pt, scb);
1640 ips_scmd_buf_write(SC, ha->ioctl_data,
1641 sizeof (ips_passthru_t));
1642 return ret;
1643 }
1644 if (ips_usrcmd(ha, pt, scb))
1645 return (IPS_SUCCESS);
1646 else
1647 return (IPS_FAILURE);
1648 }
1649
1650 break;
1651
1652 } /* end switch */
1653
1654 return (IPS_FAILURE);
1655 }
1656
1657 /****************************************************************************/
1658 /* Routine Name: ips_flash_copperhead */
1659 /* Routine Description: */
1660 /* Flash the BIOS/FW on a Copperhead style controller */
1661 /****************************************************************************/
1662 static int
1663 ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1664 {
1665 int datasize;
1666
1667 /* Trombone is the only copperhead that can do packet flash, but only
1668 * for firmware. No one said it had to make sence. */
1669 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1670 if (ips_usrcmd(ha, pt, scb))
1671 return IPS_SUCCESS;
1672 else
1673 return IPS_FAILURE;
1674 }
1675 pt->BasicStatus = 0x0B;
1676 pt->ExtendedStatus = 0;
1677 scb->scsi_cmd->result = DID_OK << 16;
1678 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
1679 /* avoid allocating a huge buffer per adapter ( which can fail ). */
1680 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1681 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1682 pt->BasicStatus = 0;
1683 return ips_flash_bios(ha, pt, scb);
1684 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1685 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1686 ha->flash_data = ips_FlashData;
1687 ha->flash_busaddr = ips_flashbusaddr;
1688 ha->flash_len = PAGE_SIZE << 7;
1689 ha->flash_datasize = 0;
1690 } else if (!ha->flash_data) {
1691 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1692 pt->CoppCP.cmd.flashfw.count;
1693 ha->flash_data = pci_alloc_consistent(ha->pcidev,
1694 datasize,
1695 &ha->flash_busaddr);
1696 if (!ha->flash_data){
1697 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1698 return IPS_FAILURE;
1699 }
1700 ha->flash_datasize = 0;
1701 ha->flash_len = datasize;
1702 } else
1703 return IPS_FAILURE;
1704 } else {
1705 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1706 ha->flash_len) {
1707 ips_free_flash_copperhead(ha);
1708 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1709 "failed size sanity check\n");
1710 return IPS_FAILURE;
1711 }
1712 }
1713 if (!ha->flash_data)
1714 return IPS_FAILURE;
1715 pt->BasicStatus = 0;
1716 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1717 pt->CoppCP.cmd.flashfw.count);
1718 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1719 if (pt->CoppCP.cmd.flashfw.packet_num ==
1720 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1721 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1722 return ips_flash_bios(ha, pt, scb);
1723 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1724 return ips_flash_firmware(ha, pt, scb);
1725 }
1726 return IPS_SUCCESS_IMM;
1727 }
1728
1729 /****************************************************************************/
1730 /* Routine Name: ips_flash_bios */
1731 /* Routine Description: */
1732 /* flashes the bios of a copperhead adapter */
1733 /****************************************************************************/
1734 static int
1735 ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1736 {
1737
1738 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1739 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1740 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1741 (!ha->func.verifybios))
1742 goto error;
1743 if ((*ha->func.erasebios) (ha)) {
1744 DEBUG_VAR(1,
1745 "(%s%d) flash bios failed - unable to erase flash",
1746 ips_name, ha->host_num);
1747 goto error;
1748 } else
1749 if ((*ha->func.programbios) (ha,
1750 ha->flash_data +
1751 IPS_BIOS_HEADER,
1752 ha->flash_datasize -
1753 IPS_BIOS_HEADER, 0)) {
1754 DEBUG_VAR(1,
1755 "(%s%d) flash bios failed - unable to flash",
1756 ips_name, ha->host_num);
1757 goto error;
1758 } else
1759 if ((*ha->func.verifybios) (ha,
1760 ha->flash_data +
1761 IPS_BIOS_HEADER,
1762 ha->flash_datasize -
1763 IPS_BIOS_HEADER, 0)) {
1764 DEBUG_VAR(1,
1765 "(%s%d) flash bios failed - unable to verify flash",
1766 ips_name, ha->host_num);
1767 goto error;
1768 }
1769 ips_free_flash_copperhead(ha);
1770 return IPS_SUCCESS_IMM;
1771 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1772 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1773 if (!ha->func.erasebios)
1774 goto error;
1775 if ((*ha->func.erasebios) (ha)) {
1776 DEBUG_VAR(1,
1777 "(%s%d) flash bios failed - unable to erase flash",
1778 ips_name, ha->host_num);
1779 goto error;
1780 }
1781 return IPS_SUCCESS_IMM;
1782 }
1783 error:
1784 pt->BasicStatus = 0x0B;
1785 pt->ExtendedStatus = 0x00;
1786 ips_free_flash_copperhead(ha);
1787 return IPS_FAILURE;
1788 }
1789
1790 /****************************************************************************/
1791 /* */
1792 /* Routine Name: ips_fill_scb_sg_single */
1793 /* */
1794 /* Routine Description: */
1795 /* Fill in a single scb sg_list element from an address */
1796 /* return a -1 if a breakup occurred */
1797 /****************************************************************************/
1798 static int
1799 ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1800 ips_scb_t * scb, int indx, unsigned int e_len)
1801 {
1802
1803 int ret_val = 0;
1804
1805 if ((scb->data_len + e_len) > ha->max_xfer) {
1806 e_len = ha->max_xfer - scb->data_len;
1807 scb->breakup = indx;
1808 ++scb->sg_break;
1809 ret_val = -1;
1810 } else {
1811 scb->breakup = 0;
1812 scb->sg_break = 0;
1813 }
1814 if (IPS_USE_ENH_SGLIST(ha)) {
1815 scb->sg_list.enh_list[indx].address_lo =
1816 cpu_to_le32(pci_dma_lo32(busaddr));
1817 scb->sg_list.enh_list[indx].address_hi =
1818 cpu_to_le32(pci_dma_hi32(busaddr));
1819 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1820 } else {
1821 scb->sg_list.std_list[indx].address =
1822 cpu_to_le32(pci_dma_lo32(busaddr));
1823 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1824 }
1825
1826 ++scb->sg_len;
1827 scb->data_len += e_len;
1828 return ret_val;
1829 }
1830
1831 /****************************************************************************/
1832 /* Routine Name: ips_flash_firmware */
1833 /* Routine Description: */
1834 /* flashes the firmware of a copperhead adapter */
1835 /****************************************************************************/
1836 static int
1837 ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1838 {
1839 IPS_SG_LIST sg_list;
1840 uint32_t cmd_busaddr;
1841
1842 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1843 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1844 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1845 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1846 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1847 } else {
1848 pt->BasicStatus = 0x0B;
1849 pt->ExtendedStatus = 0x00;
1850 ips_free_flash_copperhead(ha);
1851 return IPS_FAILURE;
1852 }
1853 /* Save the S/G list pointer so it doesn't get clobbered */
1854 sg_list.list = scb->sg_list.list;
1855 cmd_busaddr = scb->scb_busaddr;
1856 /* copy in the CP */
1857 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1858 /* FIX stuff that might be wrong */
1859 scb->sg_list.list = sg_list.list;
1860 scb->scb_busaddr = cmd_busaddr;
1861 scb->bus = scb->scsi_cmd->device->channel;
1862 scb->target_id = scb->scsi_cmd->device->id;
1863 scb->lun = scb->scsi_cmd->device->lun;
1864 scb->sg_len = 0;
1865 scb->data_len = 0;
1866 scb->flags = 0;
1867 scb->op_code = 0;
1868 scb->callback = ipsintr_done;
1869 scb->timeout = ips_cmd_timeout;
1870
1871 scb->data_len = ha->flash_datasize;
1872 scb->data_busaddr =
1873 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len,
1874 IPS_DMA_DIR(scb));
1875 scb->flags |= IPS_SCB_MAP_SINGLE;
1876 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1877 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1878 if (pt->TimeOut)
1879 scb->timeout = pt->TimeOut;
1880 scb->scsi_cmd->result = DID_OK << 16;
1881 return IPS_SUCCESS;
1882 }
1883
1884 /****************************************************************************/
1885 /* Routine Name: ips_free_flash_copperhead */
1886 /* Routine Description: */
1887 /* release the memory resources used to hold the flash image */
1888 /****************************************************************************/
1889 static void
1890 ips_free_flash_copperhead(ips_ha_t * ha)
1891 {
1892 if (ha->flash_data == ips_FlashData)
1893 test_and_clear_bit(0, &ips_FlashDataInUse);
1894 else if (ha->flash_data)
1895 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data,
1896 ha->flash_busaddr);
1897 ha->flash_data = NULL;
1898 }
1899
1900 /****************************************************************************/
1901 /* */
1902 /* Routine Name: ips_usrcmd */
1903 /* */
1904 /* Routine Description: */
1905 /* */
1906 /* Process a user command and make it ready to send */
1907 /* */
1908 /****************************************************************************/
1909 static int
1910 ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1911 {
1912 IPS_SG_LIST sg_list;
1913 uint32_t cmd_busaddr;
1914
1915 METHOD_TRACE("ips_usrcmd", 1);
1916
1917 if ((!scb) || (!pt) || (!ha))
1918 return (0);
1919
1920 /* Save the S/G list pointer so it doesn't get clobbered */
1921 sg_list.list = scb->sg_list.list;
1922 cmd_busaddr = scb->scb_busaddr;
1923 /* copy in the CP */
1924 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1925 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
1926
1927 /* FIX stuff that might be wrong */
1928 scb->sg_list.list = sg_list.list;
1929 scb->scb_busaddr = cmd_busaddr;
1930 scb->bus = scb->scsi_cmd->device->channel;
1931 scb->target_id = scb->scsi_cmd->device->id;
1932 scb->lun = scb->scsi_cmd->device->lun;
1933 scb->sg_len = 0;
1934 scb->data_len = 0;
1935 scb->flags = 0;
1936 scb->op_code = 0;
1937 scb->callback = ipsintr_done;
1938 scb->timeout = ips_cmd_timeout;
1939 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
1940
1941 /* we don't support DCDB/READ/WRITE Scatter Gather */
1942 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
1943 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
1944 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
1945 return (0);
1946
1947 if (pt->CmdBSize) {
1948 scb->data_len = pt->CmdBSize;
1949 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
1950 } else {
1951 scb->data_busaddr = 0L;
1952 }
1953
1954 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1955 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
1956 (unsigned long) &scb->
1957 dcdb -
1958 (unsigned long) scb);
1959
1960 if (pt->CmdBSize) {
1961 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1962 scb->dcdb.buffer_pointer =
1963 cpu_to_le32(scb->data_busaddr);
1964 else
1965 scb->cmd.basic_io.sg_addr =
1966 cpu_to_le32(scb->data_busaddr);
1967 }
1968
1969 /* set timeouts */
1970 if (pt->TimeOut) {
1971 scb->timeout = pt->TimeOut;
1972
1973 if (pt->TimeOut <= 10)
1974 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
1975 else if (pt->TimeOut <= 60)
1976 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
1977 else
1978 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
1979 }
1980
1981 /* assume success */
1982 scb->scsi_cmd->result = DID_OK << 16;
1983
1984 /* success */
1985 return (1);
1986 }
1987
1988 /****************************************************************************/
1989 /* */
1990 /* Routine Name: ips_cleanup_passthru */
1991 /* */
1992 /* Routine Description: */
1993 /* */
1994 /* Cleanup after a passthru command */
1995 /* */
1996 /****************************************************************************/
1997 static void
1998 ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
1999 {
2000 ips_passthru_t *pt;
2001
2002 METHOD_TRACE("ips_cleanup_passthru", 1);
2003
2004 if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(scb->scsi_cmd))) {
2005 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
2006 ips_name, ha->host_num);
2007
2008 return;
2009 }
2010 pt = (ips_passthru_t *) ha->ioctl_data;
2011
2012 /* Copy data back to the user */
2013 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
2014 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2015
2016 pt->BasicStatus = scb->basic_status;
2017 pt->ExtendedStatus = scb->extended_status;
2018 pt->AdapterType = ha->ad_type;
2019
2020 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
2021 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2022 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2023 ips_free_flash_copperhead(ha);
2024
2025 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2026 }
2027
2028 /****************************************************************************/
2029 /* */
2030 /* Routine Name: ips_host_info */
2031 /* */
2032 /* Routine Description: */
2033 /* */
2034 /* The passthru interface for the driver */
2035 /* */
2036 /****************************************************************************/
2037 static int
2038 ips_host_info(ips_ha_t * ha, char *ptr, off_t offset, int len)
2039 {
2040 IPS_INFOSTR info;
2041
2042 METHOD_TRACE("ips_host_info", 1);
2043
2044 info.buffer = ptr;
2045 info.length = len;
2046 info.offset = offset;
2047 info.pos = 0;
2048 info.localpos = 0;
2049
2050 copy_info(&info, "\nIBM ServeRAID General Information:\n\n");
2051
2052 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2053 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2054 copy_info(&info, "\tController Type : %s\n",
2055 ips_adapter_name[ha->ad_type - 1]);
2056 else
2057 copy_info(&info,
2058 "\tController Type : Unknown\n");
2059
2060 if (ha->io_addr)
2061 copy_info(&info,
2062 "\tIO region : 0x%lx (%d bytes)\n",
2063 ha->io_addr, ha->io_len);
2064
2065 if (ha->mem_addr) {
2066 copy_info(&info,
2067 "\tMemory region : 0x%lx (%d bytes)\n",
2068 ha->mem_addr, ha->mem_len);
2069 copy_info(&info,
2070 "\tShared memory address : 0x%lx\n",
2071 ha->mem_ptr);
2072 }
2073
2074 copy_info(&info, "\tIRQ number : %d\n", ha->pcidev->irq);
2075
2076 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2077 /* That keeps everything happy for "text" operations on the proc file. */
2078
2079 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2080 if (ha->nvram->bios_low[3] == 0) {
2081 copy_info(&info,
2082 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2083 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2084 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2085 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2086 ha->nvram->bios_low[2]);
2087
2088 } else {
2089 copy_info(&info,
2090 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2091 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2092 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2093 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2094 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2095 }
2096
2097 }
2098
2099 if (ha->enq->CodeBlkVersion[7] == 0) {
2100 copy_info(&info,
2101 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2102 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2103 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2104 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2105 ha->enq->CodeBlkVersion[6]);
2106 } else {
2107 copy_info(&info,
2108 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2109 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2110 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2111 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2112 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2113 }
2114
2115 if (ha->enq->BootBlkVersion[7] == 0) {
2116 copy_info(&info,
2117 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2118 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2119 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2120 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2121 ha->enq->BootBlkVersion[6]);
2122 } else {
2123 copy_info(&info,
2124 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2125 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2126 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2127 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2128 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2129 }
2130
2131 copy_info(&info, "\tDriver Version : %s%s\n",
2132 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2133
2134 copy_info(&info, "\tDriver Build : %d\n",
2135 IPS_BUILD_IDENT);
2136
2137 copy_info(&info, "\tMax Physical Devices : %d\n",
2138 ha->enq->ucMaxPhysicalDevices);
2139 copy_info(&info, "\tMax Active Commands : %d\n",
2140 ha->max_cmds);
2141 copy_info(&info, "\tCurrent Queued Commands : %d\n",
2142 ha->scb_waitlist.count);
2143 copy_info(&info, "\tCurrent Active Commands : %d\n",
2144 ha->scb_activelist.count - ha->num_ioctl);
2145 copy_info(&info, "\tCurrent Queued PT Commands : %d\n",
2146 ha->copp_waitlist.count);
2147 copy_info(&info, "\tCurrent Active PT Commands : %d\n",
2148 ha->num_ioctl);
2149
2150 copy_info(&info, "\n");
2151
2152 return (info.localpos);
2153 }
2154
2155 /****************************************************************************/
2156 /* */
2157 /* Routine Name: copy_mem_info */
2158 /* */
2159 /* Routine Description: */
2160 /* */
2161 /* Copy data into an IPS_INFOSTR structure */
2162 /* */
2163 /****************************************************************************/
2164 static void
2165 copy_mem_info(IPS_INFOSTR * info, char *data, int len)
2166 {
2167 METHOD_TRACE("copy_mem_info", 1);
2168
2169 if (info->pos + len < info->offset) {
2170 info->pos += len;
2171 return;
2172 }
2173
2174 if (info->pos < info->offset) {
2175 data += (info->offset - info->pos);
2176 len -= (info->offset - info->pos);
2177 info->pos += (info->offset - info->pos);
2178 }
2179
2180 if (info->localpos + len > info->length)
2181 len = info->length - info->localpos;
2182
2183 if (len > 0) {
2184 memcpy(info->buffer + info->localpos, data, len);
2185 info->pos += len;
2186 info->localpos += len;
2187 }
2188 }
2189
2190 /****************************************************************************/
2191 /* */
2192 /* Routine Name: copy_info */
2193 /* */
2194 /* Routine Description: */
2195 /* */
2196 /* printf style wrapper for an info structure */
2197 /* */
2198 /****************************************************************************/
2199 static int
2200 copy_info(IPS_INFOSTR * info, char *fmt, ...)
2201 {
2202 va_list args;
2203 char buf[128];
2204 int len;
2205
2206 METHOD_TRACE("copy_info", 1);
2207
2208 va_start(args, fmt);
2209 len = vsprintf(buf, fmt, args);
2210 va_end(args);
2211
2212 copy_mem_info(info, buf, len);
2213
2214 return (len);
2215 }
2216
2217 /****************************************************************************/
2218 /* */
2219 /* Routine Name: ips_identify_controller */
2220 /* */
2221 /* Routine Description: */
2222 /* */
2223 /* Identify this controller */
2224 /* */
2225 /****************************************************************************/
2226 static void
2227 ips_identify_controller(ips_ha_t * ha)
2228 {
2229 METHOD_TRACE("ips_identify_controller", 1);
2230
2231 switch (ha->pcidev->device) {
2232 case IPS_DEVICEID_COPPERHEAD:
2233 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) {
2234 ha->ad_type = IPS_ADTYPE_SERVERAID;
2235 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) {
2236 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2237 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) {
2238 ha->ad_type = IPS_ADTYPE_NAVAJO;
2239 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2)
2240 && (ha->slot_num == 0)) {
2241 ha->ad_type = IPS_ADTYPE_KIOWA;
2242 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) &&
2243 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) {
2244 if (ha->enq->ucMaxPhysicalDevices == 15)
2245 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2246 else
2247 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2248 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) &&
2249 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) {
2250 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2251 }
2252 break;
2253
2254 case IPS_DEVICEID_MORPHEUS:
2255 switch (ha->pcidev->subsystem_device) {
2256 case IPS_SUBDEVICEID_4L:
2257 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2258 break;
2259
2260 case IPS_SUBDEVICEID_4M:
2261 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2262 break;
2263
2264 case IPS_SUBDEVICEID_4MX:
2265 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2266 break;
2267
2268 case IPS_SUBDEVICEID_4LX:
2269 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2270 break;
2271
2272 case IPS_SUBDEVICEID_5I2:
2273 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2274 break;
2275
2276 case IPS_SUBDEVICEID_5I1:
2277 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2278 break;
2279 }
2280
2281 break;
2282
2283 case IPS_DEVICEID_MARCO:
2284 switch (ha->pcidev->subsystem_device) {
2285 case IPS_SUBDEVICEID_6M:
2286 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2287 break;
2288 case IPS_SUBDEVICEID_6I:
2289 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2290 break;
2291 case IPS_SUBDEVICEID_7k:
2292 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2293 break;
2294 case IPS_SUBDEVICEID_7M:
2295 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2296 break;
2297 }
2298 break;
2299 }
2300 }
2301
2302 /****************************************************************************/
2303 /* */
2304 /* Routine Name: ips_get_bios_version */
2305 /* */
2306 /* Routine Description: */
2307 /* */
2308 /* Get the BIOS revision number */
2309 /* */
2310 /****************************************************************************/
2311 static void
2312 ips_get_bios_version(ips_ha_t * ha, int intr)
2313 {
2314 ips_scb_t *scb;
2315 int ret;
2316 uint8_t major;
2317 uint8_t minor;
2318 uint8_t subminor;
2319 uint8_t *buffer;
2320 char hexDigits[] =
2321 { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
2322 'D', 'E', 'F' };
2323
2324 METHOD_TRACE("ips_get_bios_version", 1);
2325
2326 major = 0;
2327 minor = 0;
2328
2329 strncpy(ha->bios_version, " ?", 8);
2330
2331 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) {
2332 if (IPS_USE_MEMIO(ha)) {
2333 /* Memory Mapped I/O */
2334
2335 /* test 1st byte */
2336 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2337 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2338 udelay(25); /* 25 us */
2339
2340 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2341 return;
2342
2343 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2344 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2345 udelay(25); /* 25 us */
2346
2347 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2348 return;
2349
2350 /* Get Major version */
2351 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2352 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2353 udelay(25); /* 25 us */
2354
2355 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2356
2357 /* Get Minor version */
2358 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2359 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2360 udelay(25); /* 25 us */
2361 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2362
2363 /* Get SubMinor version */
2364 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2365 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2366 udelay(25); /* 25 us */
2367 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2368
2369 } else {
2370 /* Programmed I/O */
2371
2372 /* test 1st byte */
2373 outl(0, ha->io_addr + IPS_REG_FLAP);
2374 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2375 udelay(25); /* 25 us */
2376
2377 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2378 return;
2379
2380 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
2381 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2382 udelay(25); /* 25 us */
2383
2384 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2385 return;
2386
2387 /* Get Major version */
2388 outl(cpu_to_le32(0x1FF), ha->io_addr + IPS_REG_FLAP);
2389 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2390 udelay(25); /* 25 us */
2391
2392 major = inb(ha->io_addr + IPS_REG_FLDP);
2393
2394 /* Get Minor version */
2395 outl(cpu_to_le32(0x1FE), ha->io_addr + IPS_REG_FLAP);
2396 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2397 udelay(25); /* 25 us */
2398
2399 minor = inb(ha->io_addr + IPS_REG_FLDP);
2400
2401 /* Get SubMinor version */
2402 outl(cpu_to_le32(0x1FD), ha->io_addr + IPS_REG_FLAP);
2403 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2404 udelay(25); /* 25 us */
2405
2406 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2407
2408 }
2409 } else {
2410 /* Morpheus Family - Send Command to the card */
2411
2412 buffer = ha->ioctl_data;
2413
2414 memset(buffer, 0, 0x1000);
2415
2416 scb = &ha->scbs[ha->max_cmds - 1];
2417
2418 ips_init_scb(ha, scb);
2419
2420 scb->timeout = ips_cmd_timeout;
2421 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2422
2423 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2424 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2425 scb->cmd.flashfw.type = 1;
2426 scb->cmd.flashfw.direction = 0;
2427 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2428 scb->cmd.flashfw.total_packets = 1;
2429 scb->cmd.flashfw.packet_num = 0;
2430 scb->data_len = 0x1000;
2431 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2432
2433 /* issue the command */
2434 if (((ret =
2435 ips_send_wait(ha, scb, ips_cmd_timeout,
2436 intr)) == IPS_FAILURE)
2437 || (ret == IPS_SUCCESS_IMM)
2438 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2439 /* Error occurred */
2440
2441 return;
2442 }
2443
2444 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2445 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
2446 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
2447 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
2448 } else {
2449 return;
2450 }
2451 }
2452
2453 ha->bios_version[0] = hexDigits[(major & 0xF0) >> 4];
2454 ha->bios_version[1] = '.';
2455 ha->bios_version[2] = hexDigits[major & 0x0F];
2456 ha->bios_version[3] = hexDigits[subminor];
2457 ha->bios_version[4] = '.';
2458 ha->bios_version[5] = hexDigits[(minor & 0xF0) >> 4];
2459 ha->bios_version[6] = hexDigits[minor & 0x0F];
2460 ha->bios_version[7] = 0;
2461 }
2462
2463 /****************************************************************************/
2464 /* */
2465 /* Routine Name: ips_hainit */
2466 /* */
2467 /* Routine Description: */
2468 /* */
2469 /* Initialize the controller */
2470 /* */
2471 /* NOTE: Assumes to be called from with a lock */
2472 /* */
2473 /****************************************************************************/
2474 static int
2475 ips_hainit(ips_ha_t * ha)
2476 {
2477 int i;
2478 struct timeval tv;
2479
2480 METHOD_TRACE("ips_hainit", 1);
2481
2482 if (!ha)
2483 return (0);
2484
2485 if (ha->func.statinit)
2486 (*ha->func.statinit) (ha);
2487
2488 if (ha->func.enableint)
2489 (*ha->func.enableint) (ha);
2490
2491 /* Send FFDC */
2492 ha->reset_count = 1;
2493 do_gettimeofday(&tv);
2494 ha->last_ffdc = tv.tv_sec;
2495 ips_ffdc_reset(ha, IPS_INTR_IORL);
2496
2497 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2498 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2499 "unable to read config from controller.\n");
2500
2501 return (0);
2502 }
2503 /* end if */
2504 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2505 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2506 "unable to read controller status.\n");
2507
2508 return (0);
2509 }
2510
2511 /* Identify this controller */
2512 ips_identify_controller(ha);
2513
2514 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2515 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2516 "unable to read subsystem parameters.\n");
2517
2518 return (0);
2519 }
2520
2521 /* write nvram user page 5 */
2522 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2523 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2524 "unable to write driver info to controller.\n");
2525
2526 return (0);
2527 }
2528
2529 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
2530 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2531 ips_clear_adapter(ha, IPS_INTR_IORL);
2532
2533 /* set limits on SID, LUN, BUS */
2534 ha->ntargets = IPS_MAX_TARGETS + 1;
2535 ha->nlun = 1;
2536 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2537
2538 switch (ha->conf->logical_drive[0].ucStripeSize) {
2539 case 4:
2540 ha->max_xfer = 0x10000;
2541 break;
2542
2543 case 5:
2544 ha->max_xfer = 0x20000;
2545 break;
2546
2547 case 6:
2548 ha->max_xfer = 0x40000;
2549 break;
2550
2551 case 7:
2552 default:
2553 ha->max_xfer = 0x80000;
2554 break;
2555 }
2556
2557 /* setup max concurrent commands */
2558 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2559 /* Use the new method */
2560 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2561 } else {
2562 /* use the old method */
2563 switch (ha->conf->logical_drive[0].ucStripeSize) {
2564 case 4:
2565 ha->max_cmds = 32;
2566 break;
2567
2568 case 5:
2569 ha->max_cmds = 16;
2570 break;
2571
2572 case 6:
2573 ha->max_cmds = 8;
2574 break;
2575
2576 case 7:
2577 default:
2578 ha->max_cmds = 4;
2579 break;
2580 }
2581 }
2582
2583 /* Limit the Active Commands on a Lite Adapter */
2584 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2585 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2586 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2587 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2588 ha->max_cmds = MaxLiteCmds;
2589 }
2590
2591 /* set controller IDs */
2592 ha->ha_id[0] = IPS_ADAPTER_ID;
2593 for (i = 1; i < ha->nbus; i++) {
2594 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2595 ha->dcdb_active[i - 1] = 0;
2596 }
2597
2598 return (1);
2599 }
2600
2601 /****************************************************************************/
2602 /* */
2603 /* Routine Name: ips_next */
2604 /* */
2605 /* Routine Description: */
2606 /* */
2607 /* Take the next command off the queue and send it to the controller */
2608 /* */
2609 /****************************************************************************/
2610 static void
2611 ips_next(ips_ha_t * ha, int intr)
2612 {
2613 ips_scb_t *scb;
2614 struct scsi_cmnd *SC;
2615 struct scsi_cmnd *p;
2616 struct scsi_cmnd *q;
2617 ips_copp_wait_item_t *item;
2618 int ret;
2619 struct Scsi_Host *host;
2620 METHOD_TRACE("ips_next", 1);
2621
2622 if (!ha)
2623 return;
2624 host = ips_sh[ha->host_num];
2625 /*
2626 * Block access to the queue function so
2627 * this command won't time out
2628 */
2629 if (intr == IPS_INTR_ON)
2630 spin_lock(host->host_lock);
2631
2632 if ((ha->subsys->param[3] & 0x300000)
2633 && (ha->scb_activelist.count == 0)) {
2634 struct timeval tv;
2635
2636 do_gettimeofday(&tv);
2637
2638 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) {
2639 ha->last_ffdc = tv.tv_sec;
2640 ips_ffdc_time(ha);
2641 }
2642 }
2643
2644 /*
2645 * Send passthru commands
2646 * These have priority over normal I/O
2647 * but shouldn't affect performance too much
2648 * since we limit the number that can be active
2649 * on the card at any one time
2650 */
2651 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2652 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2653
2654 item = ips_removeq_copp_head(&ha->copp_waitlist);
2655 ha->num_ioctl++;
2656 if (intr == IPS_INTR_ON)
2657 spin_unlock(host->host_lock);
2658 scb->scsi_cmd = item->scsi_cmd;
2659 kfree(item);
2660
2661 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2662
2663 if (intr == IPS_INTR_ON)
2664 spin_lock(host->host_lock);
2665 switch (ret) {
2666 case IPS_FAILURE:
2667 if (scb->scsi_cmd) {
2668 scb->scsi_cmd->result = DID_ERROR << 16;
2669 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2670 }
2671
2672 ips_freescb(ha, scb);
2673 break;
2674 case IPS_SUCCESS_IMM:
2675 if (scb->scsi_cmd) {
2676 scb->scsi_cmd->result = DID_OK << 16;
2677 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2678 }
2679
2680 ips_freescb(ha, scb);
2681 break;
2682 default:
2683 break;
2684 } /* end case */
2685
2686 if (ret != IPS_SUCCESS) {
2687 ha->num_ioctl--;
2688 continue;
2689 }
2690
2691 ret = ips_send_cmd(ha, scb);
2692
2693 if (ret == IPS_SUCCESS)
2694 ips_putq_scb_head(&ha->scb_activelist, scb);
2695 else
2696 ha->num_ioctl--;
2697
2698 switch (ret) {
2699 case IPS_FAILURE:
2700 if (scb->scsi_cmd) {
2701 scb->scsi_cmd->result = DID_ERROR << 16;
2702 }
2703
2704 ips_freescb(ha, scb);
2705 break;
2706 case IPS_SUCCESS_IMM:
2707 ips_freescb(ha, scb);
2708 break;
2709 default:
2710 break;
2711 } /* end case */
2712
2713 }
2714
2715 /*
2716 * Send "Normal" I/O commands
2717 */
2718
2719 p = ha->scb_waitlist.head;
2720 while ((p) && (scb = ips_getscb(ha))) {
2721 if ((scmd_channel(p) > 0)
2722 && (ha->
2723 dcdb_active[scmd_channel(p) -
2724 1] & (1 << scmd_id(p)))) {
2725 ips_freescb(ha, scb);
2726 p = (struct scsi_cmnd *) p->host_scribble;
2727 continue;
2728 }
2729
2730 q = p;
2731 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2732
2733 if (intr == IPS_INTR_ON)
2734 spin_unlock(host->host_lock); /* Unlock HA after command is taken off queue */
2735
2736 SC->result = DID_OK;
2737 SC->host_scribble = NULL;
2738
2739 scb->target_id = SC->device->id;
2740 scb->lun = SC->device->lun;
2741 scb->bus = SC->device->channel;
2742 scb->scsi_cmd = SC;
2743 scb->breakup = 0;
2744 scb->data_len = 0;
2745 scb->callback = ipsintr_done;
2746 scb->timeout = ips_cmd_timeout;
2747 memset(&scb->cmd, 0, 16);
2748
2749 /* copy in the CDB */
2750 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2751
2752 scb->sg_count = scsi_dma_map(SC);
2753 BUG_ON(scb->sg_count < 0);
2754 if (scb->sg_count) {
2755 struct scatterlist *sg;
2756 int i;
2757
2758 scb->flags |= IPS_SCB_MAP_SG;
2759
2760 scsi_for_each_sg(SC, sg, scb->sg_count, i) {
2761 if (ips_fill_scb_sg_single
2762 (ha, sg_dma_address(sg), scb, i,
2763 sg_dma_len(sg)) < 0)
2764 break;
2765 }
2766 scb->dcdb.transfer_length = scb->data_len;
2767 } else {
2768 scb->data_busaddr = 0L;
2769 scb->sg_len = 0;
2770 scb->data_len = 0;
2771 scb->dcdb.transfer_length = 0;
2772 }
2773
2774 scb->dcdb.cmd_attribute =
2775 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2776
2777 /* Allow a WRITE BUFFER Command to Have no Data */
2778 /* This is Used by Tape Flash Utilites */
2779 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) &&
2780 (scb->data_len == 0))
2781 scb->dcdb.cmd_attribute = 0;
2782
2783 if (!(scb->dcdb.cmd_attribute & 0x3))
2784 scb->dcdb.transfer_length = 0;
2785
2786 if (scb->data_len >= IPS_MAX_XFER) {
2787 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2788 scb->dcdb.transfer_length = 0;
2789 }
2790 if (intr == IPS_INTR_ON)
2791 spin_lock(host->host_lock);
2792
2793 ret = ips_send_cmd(ha, scb);
2794
2795 switch (ret) {
2796 case IPS_SUCCESS:
2797 ips_putq_scb_head(&ha->scb_activelist, scb);
2798 break;
2799 case IPS_FAILURE:
2800 if (scb->scsi_cmd) {
2801 scb->scsi_cmd->result = DID_ERROR << 16;
2802 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2803 }
2804
2805 if (scb->bus)
2806 ha->dcdb_active[scb->bus - 1] &=
2807 ~(1 << scb->target_id);
2808
2809 ips_freescb(ha, scb);
2810 break;
2811 case IPS_SUCCESS_IMM:
2812 if (scb->scsi_cmd)
2813 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2814
2815 if (scb->bus)
2816 ha->dcdb_active[scb->bus - 1] &=
2817 ~(1 << scb->target_id);
2818
2819 ips_freescb(ha, scb);
2820 break;
2821 default:
2822 break;
2823 } /* end case */
2824
2825 p = (struct scsi_cmnd *) p->host_scribble;
2826
2827 } /* end while */
2828
2829 if (intr == IPS_INTR_ON)
2830 spin_unlock(host->host_lock);
2831 }
2832
2833 /****************************************************************************/
2834 /* */
2835 /* Routine Name: ips_putq_scb_head */
2836 /* */
2837 /* Routine Description: */
2838 /* */
2839 /* Add an item to the head of the queue */
2840 /* */
2841 /* ASSUMED to be called from within the HA lock */
2842 /* */
2843 /****************************************************************************/
2844 static void
2845 ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2846 {
2847 METHOD_TRACE("ips_putq_scb_head", 1);
2848
2849 if (!item)
2850 return;
2851
2852 item->q_next = queue->head;
2853 queue->head = item;
2854
2855 if (!queue->tail)
2856 queue->tail = item;
2857
2858 queue->count++;
2859 }
2860
2861 /****************************************************************************/
2862 /* */
2863 /* Routine Name: ips_removeq_scb_head */
2864 /* */
2865 /* Routine Description: */
2866 /* */
2867 /* Remove the head of the queue */
2868 /* */
2869 /* ASSUMED to be called from within the HA lock */
2870 /* */
2871 /****************************************************************************/
2872 static ips_scb_t *
2873 ips_removeq_scb_head(ips_scb_queue_t * queue)
2874 {
2875 ips_scb_t *item;
2876
2877 METHOD_TRACE("ips_removeq_scb_head", 1);
2878
2879 item = queue->head;
2880
2881 if (!item) {
2882 return (NULL);
2883 }
2884
2885 queue->head = item->q_next;
2886 item->q_next = NULL;
2887
2888 if (queue->tail == item)
2889 queue->tail = NULL;
2890
2891 queue->count--;
2892
2893 return (item);
2894 }
2895
2896 /****************************************************************************/
2897 /* */
2898 /* Routine Name: ips_removeq_scb */
2899 /* */
2900 /* Routine Description: */
2901 /* */
2902 /* Remove an item from a queue */
2903 /* */
2904 /* ASSUMED to be called from within the HA lock */
2905 /* */
2906 /****************************************************************************/
2907 static ips_scb_t *
2908 ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
2909 {
2910 ips_scb_t *p;
2911
2912 METHOD_TRACE("ips_removeq_scb", 1);
2913
2914 if (!item)
2915 return (NULL);
2916
2917 if (item == queue->head) {
2918 return (ips_removeq_scb_head(queue));
2919 }
2920
2921 p = queue->head;
2922
2923 while ((p) && (item != p->q_next))
2924 p = p->q_next;
2925
2926 if (p) {
2927 /* found a match */
2928 p->q_next = item->q_next;
2929
2930 if (!item->q_next)
2931 queue->tail = p;
2932
2933 item->q_next = NULL;
2934 queue->count--;
2935
2936 return (item);
2937 }
2938
2939 return (NULL);
2940 }
2941
2942 /****************************************************************************/
2943 /* */
2944 /* Routine Name: ips_putq_wait_tail */
2945 /* */
2946 /* Routine Description: */
2947 /* */
2948 /* Add an item to the tail of the queue */
2949 /* */
2950 /* ASSUMED to be called from within the HA lock */
2951 /* */
2952 /****************************************************************************/
2953 static void ips_putq_wait_tail(ips_wait_queue_t *queue, struct scsi_cmnd *item)
2954 {
2955 METHOD_TRACE("ips_putq_wait_tail", 1);
2956
2957 if (!item)
2958 return;
2959
2960 item->host_scribble = NULL;
2961
2962 if (queue->tail)
2963 queue->tail->host_scribble = (char *) item;
2964
2965 queue->tail = item;
2966
2967 if (!queue->head)
2968 queue->head = item;
2969
2970 queue->count++;
2971 }
2972
2973 /****************************************************************************/
2974 /* */
2975 /* Routine Name: ips_removeq_wait_head */
2976 /* */
2977 /* Routine Description: */
2978 /* */
2979 /* Remove the head of the queue */
2980 /* */
2981 /* ASSUMED to be called from within the HA lock */
2982 /* */
2983 /****************************************************************************/
2984 static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_t *queue)
2985 {
2986 struct scsi_cmnd *item;
2987
2988 METHOD_TRACE("ips_removeq_wait_head", 1);
2989
2990 item = queue->head;
2991
2992 if (!item) {
2993 return (NULL);
2994 }
2995
2996 queue->head = (struct scsi_cmnd *) item->host_scribble;
2997 item->host_scribble = NULL;
2998
2999 if (queue->tail == item)
3000 queue->tail = NULL;
3001
3002 queue->count--;
3003
3004 return (item);
3005 }
3006
3007 /****************************************************************************/
3008 /* */
3009 /* Routine Name: ips_removeq_wait */
3010 /* */
3011 /* Routine Description: */
3012 /* */
3013 /* Remove an item from a queue */
3014 /* */
3015 /* ASSUMED to be called from within the HA lock */
3016 /* */
3017 /****************************************************************************/
3018 static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_t *queue,
3019 struct scsi_cmnd *item)
3020 {
3021 struct scsi_cmnd *p;
3022
3023 METHOD_TRACE("ips_removeq_wait", 1);
3024
3025 if (!item)
3026 return (NULL);
3027
3028 if (item == queue->head) {
3029 return (ips_removeq_wait_head(queue));
3030 }
3031
3032 p = queue->head;
3033
3034 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble))
3035 p = (struct scsi_cmnd *) p->host_scribble;
3036
3037 if (p) {
3038 /* found a match */
3039 p->host_scribble = item->host_scribble;
3040
3041 if (!item->host_scribble)
3042 queue->tail = p;
3043
3044 item->host_scribble = NULL;
3045 queue->count--;
3046
3047 return (item);
3048 }
3049
3050 return (NULL);
3051 }
3052
3053 /****************************************************************************/
3054 /* */
3055 /* Routine Name: ips_putq_copp_tail */
3056 /* */
3057 /* Routine Description: */
3058 /* */
3059 /* Add an item to the tail of the queue */
3060 /* */
3061 /* ASSUMED to be called from within the HA lock */
3062 /* */
3063 /****************************************************************************/
3064 static void
3065 ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3066 {
3067 METHOD_TRACE("ips_putq_copp_tail", 1);
3068
3069 if (!item)
3070 return;
3071
3072 item->next = NULL;
3073
3074 if (queue->tail)
3075 queue->tail->next = item;
3076
3077 queue->tail = item;
3078
3079 if (!queue->head)
3080 queue->head = item;
3081
3082 queue->count++;
3083 }
3084
3085 /****************************************************************************/
3086 /* */
3087 /* Routine Name: ips_removeq_copp_head */
3088 /* */
3089 /* Routine Description: */
3090 /* */
3091 /* Remove the head of the queue */
3092 /* */
3093 /* ASSUMED to be called from within the HA lock */
3094 /* */
3095 /****************************************************************************/
3096 static ips_copp_wait_item_t *
3097 ips_removeq_copp_head(ips_copp_queue_t * queue)
3098 {
3099 ips_copp_wait_item_t *item;
3100
3101 METHOD_TRACE("ips_removeq_copp_head", 1);
3102
3103 item = queue->head;
3104
3105 if (!item) {
3106 return (NULL);
3107 }
3108
3109 queue->head = item->next;
3110 item->next = NULL;
3111
3112 if (queue->tail == item)
3113 queue->tail = NULL;
3114
3115 queue->count--;
3116
3117 return (item);
3118 }
3119
3120 /****************************************************************************/
3121 /* */
3122 /* Routine Name: ips_removeq_copp */
3123 /* */
3124 /* Routine Description: */
3125 /* */
3126 /* Remove an item from a queue */
3127 /* */
3128 /* ASSUMED to be called from within the HA lock */
3129 /* */
3130 /****************************************************************************/
3131 static ips_copp_wait_item_t *
3132 ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3133 {
3134 ips_copp_wait_item_t *p;
3135
3136 METHOD_TRACE("ips_removeq_copp", 1);
3137
3138 if (!item)
3139 return (NULL);
3140
3141 if (item == queue->head) {
3142 return (ips_removeq_copp_head(queue));
3143 }
3144
3145 p = queue->head;
3146
3147 while ((p) && (item != p->next))
3148 p = p->next;
3149
3150 if (p) {
3151 /* found a match */
3152 p->next = item->next;
3153
3154 if (!item->next)
3155 queue->tail = p;
3156
3157 item->next = NULL;
3158 queue->count--;
3159
3160 return (item);
3161 }
3162
3163 return (NULL);
3164 }
3165
3166 /****************************************************************************/
3167 /* */
3168 /* Routine Name: ipsintr_blocking */
3169 /* */
3170 /* Routine Description: */
3171 /* */
3172 /* Finalize an interrupt for internal commands */
3173 /* */
3174 /****************************************************************************/
3175 static void
3176 ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3177 {
3178 METHOD_TRACE("ipsintr_blocking", 2);
3179
3180 ips_freescb(ha, scb);
3181 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3182 ha->waitflag = FALSE;
3183
3184 return;
3185 }
3186 }
3187
3188 /****************************************************************************/
3189 /* */
3190 /* Routine Name: ipsintr_done */
3191 /* */
3192 /* Routine Description: */
3193 /* */
3194 /* Finalize an interrupt for non-internal commands */
3195 /* */
3196 /****************************************************************************/
3197 static void
3198 ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3199 {
3200 METHOD_TRACE("ipsintr_done", 2);
3201
3202 if (!scb) {
3203 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3204 "Spurious interrupt; scb NULL.\n");
3205
3206 return;
3207 }
3208
3209 if (scb->scsi_cmd == NULL) {
3210 /* unexpected interrupt */
3211 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3212 "Spurious interrupt; scsi_cmd not set.\n");
3213
3214 return;
3215 }
3216
3217 ips_done(ha, scb);
3218 }
3219
3220 /****************************************************************************/
3221 /* */
3222 /* Routine Name: ips_done */
3223 /* */
3224 /* Routine Description: */
3225 /* */
3226 /* Do housekeeping on completed commands */
3227 /* ASSUMED to be called form within the request lock */
3228 /****************************************************************************/
3229 static void
3230 ips_done(ips_ha_t * ha, ips_scb_t * scb)
3231 {
3232 int ret;
3233
3234 METHOD_TRACE("ips_done", 1);
3235
3236 if (!scb)
3237 return;
3238
3239 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3240 ips_cleanup_passthru(ha, scb);
3241 ha->num_ioctl--;
3242 } else {
3243 /*
3244 * Check to see if this command had too much
3245 * data and had to be broke up. If so, queue
3246 * the rest of the data and continue.
3247 */
3248 if ((scb->breakup) || (scb->sg_break)) {
3249 struct scatterlist *sg;
3250 int i, sg_dma_index, ips_sg_index = 0;
3251
3252 /* we had a data breakup */
3253 scb->data_len = 0;
3254
3255 sg = scsi_sglist(scb->scsi_cmd);
3256
3257 /* Spin forward to last dma chunk */
3258 sg_dma_index = scb->breakup;
3259 for (i = 0; i < scb->breakup; i++)
3260 sg = sg_next(sg);
3261
3262 /* Take care of possible partial on last chunk */
3263 ips_fill_scb_sg_single(ha,
3264 sg_dma_address(sg),
3265 scb, ips_sg_index++,
3266 sg_dma_len(sg));
3267
3268 for (; sg_dma_index < scsi_sg_count(scb->scsi_cmd);
3269 sg_dma_index++, sg = sg_next(sg)) {
3270 if (ips_fill_scb_sg_single
3271 (ha,
3272 sg_dma_address(sg),
3273 scb, ips_sg_index++,
3274 sg_dma_len(sg)) < 0)
3275 break;
3276 }
3277
3278 scb->dcdb.transfer_length = scb->data_len;
3279 scb->dcdb.cmd_attribute |=
3280 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3281
3282 if (!(scb->dcdb.cmd_attribute & 0x3))
3283 scb->dcdb.transfer_length = 0;
3284
3285 if (scb->data_len >= IPS_MAX_XFER) {
3286 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3287 scb->dcdb.transfer_length = 0;
3288 }
3289
3290 ret = ips_send_cmd(ha, scb);
3291
3292 switch (ret) {
3293 case IPS_FAILURE:
3294 if (scb->scsi_cmd) {
3295 scb->scsi_cmd->result = DID_ERROR << 16;
3296 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3297 }
3298
3299 ips_freescb(ha, scb);
3300 break;
3301 case IPS_SUCCESS_IMM:
3302 if (scb->scsi_cmd) {
3303 scb->scsi_cmd->result = DID_ERROR << 16;
3304 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3305 }
3306
3307 ips_freescb(ha, scb);
3308 break;
3309 default:
3310 break;
3311 } /* end case */
3312
3313 return;
3314 }
3315 } /* end if passthru */
3316
3317 if (scb->bus) {
3318 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3319 }
3320
3321 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3322
3323 ips_freescb(ha, scb);
3324 }
3325
3326 /****************************************************************************/
3327 /* */
3328 /* Routine Name: ips_map_status */
3329 /* */
3330 /* Routine Description: */
3331 /* */
3332 /* Map Controller Error codes to Linux Error Codes */
3333 /* */
3334 /****************************************************************************/
3335 static int
3336 ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3337 {
3338 int errcode;
3339 int device_error;
3340 uint32_t transfer_len;
3341 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3342 IPS_SCSI_INQ_DATA inquiryData;
3343
3344 METHOD_TRACE("ips_map_status", 1);
3345
3346 if (scb->bus) {
3347 DEBUG_VAR(2,
3348 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3349 ips_name, ha->host_num,
3350 scb->scsi_cmd->device->channel,
3351 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3352 scb->basic_status, scb->extended_status,
3353 scb->extended_status ==
3354 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3355 scb->extended_status ==
3356 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3357 scb->extended_status ==
3358 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3359 }
3360
3361 /* default driver error */
3362 errcode = DID_ERROR;
3363 device_error = 0;
3364
3365 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3366 case IPS_CMD_TIMEOUT:
3367 errcode = DID_TIME_OUT;
3368 break;
3369
3370 case IPS_INVAL_OPCO:
3371 case IPS_INVAL_CMD_BLK:
3372 case IPS_INVAL_PARM_BLK:
3373 case IPS_LD_ERROR:
3374 case IPS_CMD_CMPLT_WERROR:
3375 break;
3376
3377 case IPS_PHYS_DRV_ERROR:
3378 switch (scb->extended_status) {
3379 case IPS_ERR_SEL_TO:
3380 if (scb->bus)
3381 errcode = DID_NO_CONNECT;
3382
3383 break;
3384
3385 case IPS_ERR_OU_RUN:
3386 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3387 (scb->cmd.dcdb.op_code ==
3388 IPS_CMD_EXTENDED_DCDB_SG)) {
3389 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3390 transfer_len = tapeDCDB->transfer_length;
3391 } else {
3392 transfer_len =
3393 (uint32_t) scb->dcdb.transfer_length;
3394 }
3395
3396 if ((scb->bus) && (transfer_len < scb->data_len)) {
3397 /* Underrun - set default to no error */
3398 errcode = DID_OK;
3399
3400 /* Restrict access to physical DASD */
3401 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3402 ips_scmd_buf_read(scb->scsi_cmd,
3403 &inquiryData, sizeof (inquiryData));
3404 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) {
3405 errcode = DID_TIME_OUT;
3406 break;
3407 }
3408 }
3409 } else
3410 errcode = DID_ERROR;
3411
3412 break;
3413
3414 case IPS_ERR_RECOVERY:
3415 /* don't fail recovered errors */
3416 if (scb->bus)
3417 errcode = DID_OK;
3418
3419 break;
3420
3421 case IPS_ERR_HOST_RESET:
3422 case IPS_ERR_DEV_RESET:
3423 errcode = DID_RESET;
3424 break;
3425
3426 case IPS_ERR_CKCOND:
3427 if (scb->bus) {
3428 if ((scb->cmd.dcdb.op_code ==
3429 IPS_CMD_EXTENDED_DCDB)
3430 || (scb->cmd.dcdb.op_code ==
3431 IPS_CMD_EXTENDED_DCDB_SG)) {
3432 tapeDCDB =
3433 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3434 memcpy(scb->scsi_cmd->sense_buffer,
3435 tapeDCDB->sense_info,
3436 sizeof (scb->scsi_cmd->
3437 sense_buffer));
3438 } else {
3439 memcpy(scb->scsi_cmd->sense_buffer,
3440 scb->dcdb.sense_info,
3441 sizeof (scb->scsi_cmd->
3442 sense_buffer));
3443 }
3444 device_error = 2; /* check condition */
3445 }
3446
3447 errcode = DID_OK;
3448
3449 break;
3450
3451 default:
3452 errcode = DID_ERROR;
3453 break;
3454
3455 } /* end switch */
3456 } /* end switch */
3457
3458 scb->scsi_cmd->result = device_error | (errcode << 16);
3459
3460 return (1);
3461 }
3462
3463 /****************************************************************************/
3464 /* */
3465 /* Routine Name: ips_send_wait */
3466 /* */
3467 /* Routine Description: */
3468 /* */
3469 /* Send a command to the controller and wait for it to return */
3470 /* */
3471 /* The FFDC Time Stamp use this function for the callback, but doesn't */
3472 /* actually need to wait. */
3473 /****************************************************************************/
3474 static int
3475 ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3476 {
3477 int ret;
3478
3479 METHOD_TRACE("ips_send_wait", 1);
3480
3481 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
3482 ha->waitflag = TRUE;
3483 ha->cmd_in_progress = scb->cdb[0];
3484 }
3485 scb->callback = ipsintr_blocking;
3486 ret = ips_send_cmd(ha, scb);
3487
3488 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3489 return (ret);
3490
3491 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
3492 ret = ips_wait(ha, timeout, intr);
3493
3494 return (ret);
3495 }
3496
3497 /****************************************************************************/
3498 /* */
3499 /* Routine Name: ips_scmd_buf_write */
3500 /* */
3501 /* Routine Description: */
3502 /* Write data to struct scsi_cmnd request_buffer at proper offsets */
3503 /****************************************************************************/
3504 static void
3505 ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count)
3506 {
3507 int i;
3508 unsigned int min_cnt, xfer_cnt;
3509 char *cdata = (char *) data;
3510 unsigned char *buffer;
3511 unsigned long flags;
3512 struct scatterlist *sg = scsi_sglist(scmd);
3513
3514 for (i = 0, xfer_cnt = 0;
3515 (i < scsi_sg_count(scmd)) && (xfer_cnt < count); i++) {
3516 min_cnt = min(count - xfer_cnt, sg[i].length);
3517
3518 /* kmap_atomic() ensures addressability of the data buffer.*/
3519 /* local_irq_save() protects the KM_IRQ0 address slot. */
3520 local_irq_save(flags);
3521 buffer = kmap_atomic(sg_page(&sg[i]), KM_IRQ0) + sg[i].offset;
3522 memcpy(buffer, &cdata[xfer_cnt], min_cnt);
3523 kunmap_atomic(buffer - sg[i].offset, KM_IRQ0);
3524 local_irq_restore(flags);
3525
3526 xfer_cnt += min_cnt;
3527 }
3528 }
3529
3530 /****************************************************************************/
3531 /* */
3532 /* Routine Name: ips_scmd_buf_read */
3533 /* */
3534 /* Routine Description: */
3535 /* Copy data from a struct scsi_cmnd to a new, linear buffer */
3536 /****************************************************************************/
3537 static void
3538 ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count)
3539 {
3540 int i;
3541 unsigned int min_cnt, xfer_cnt;
3542 char *cdata = (char *) data;
3543 unsigned char *buffer;
3544 unsigned long flags;
3545 struct scatterlist *sg = scsi_sglist(scmd);
3546
3547 for (i = 0, xfer_cnt = 0;
3548 (i < scsi_sg_count(scmd)) && (xfer_cnt < count); i++) {
3549 min_cnt = min(count - xfer_cnt, sg[i].length);
3550
3551 /* kmap_atomic() ensures addressability of the data buffer.*/
3552 /* local_irq_save() protects the KM_IRQ0 address slot. */
3553 local_irq_save(flags);
3554 buffer = kmap_atomic(sg_page(&sg[i]), KM_IRQ0) + sg[i].offset;
3555 memcpy(&cdata[xfer_cnt], buffer, min_cnt);
3556 kunmap_atomic(buffer - sg[i].offset, KM_IRQ0);
3557 local_irq_restore(flags);
3558
3559 xfer_cnt += min_cnt;
3560 }
3561 }
3562
3563 /****************************************************************************/
3564 /* */
3565 /* Routine Name: ips_send_cmd */
3566 /* */
3567 /* Routine Description: */
3568 /* */
3569 /* Map SCSI commands to ServeRAID commands for logical drives */
3570 /* */
3571 /****************************************************************************/
3572 static int
3573 ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3574 {
3575 int ret;
3576 char *sp;
3577 int device_error;
3578 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3579 int TimeOut;
3580
3581 METHOD_TRACE("ips_send_cmd", 1);
3582
3583 ret = IPS_SUCCESS;
3584
3585 if (!scb->scsi_cmd) {
3586 /* internal command */
3587
3588 if (scb->bus > 0) {
3589 /* Controller commands can't be issued */
3590 /* to real devices -- fail them */
3591 if ((ha->waitflag == TRUE) &&
3592 (ha->cmd_in_progress == scb->cdb[0])) {
3593 ha->waitflag = FALSE;
3594 }
3595
3596 return (1);
3597 }
3598 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3599 /* command to logical bus -- interpret */
3600 ret = IPS_SUCCESS_IMM;
3601
3602 switch (scb->scsi_cmd->cmnd[0]) {
3603 case ALLOW_MEDIUM_REMOVAL:
3604 case REZERO_UNIT:
3605 case ERASE:
3606 case WRITE_FILEMARKS:
3607 case SPACE:
3608 scb->scsi_cmd->result = DID_ERROR << 16;
3609 break;
3610
3611 case START_STOP:
3612 scb->scsi_cmd->result = DID_OK << 16;
3613
3614 case TEST_UNIT_READY:
3615 case INQUIRY:
3616 if (scb->target_id == IPS_ADAPTER_ID) {
3617 /*
3618 * Either we have a TUR
3619 * or we have a SCSI inquiry
3620 */
3621 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3622 scb->scsi_cmd->result = DID_OK << 16;
3623
3624 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3625 IPS_SCSI_INQ_DATA inquiry;
3626
3627 memset(&inquiry, 0,
3628 sizeof (IPS_SCSI_INQ_DATA));
3629
3630 inquiry.DeviceType =
3631 IPS_SCSI_INQ_TYPE_PROCESSOR;
3632 inquiry.DeviceTypeQualifier =
3633 IPS_SCSI_INQ_LU_CONNECTED;
3634 inquiry.Version = IPS_SCSI_INQ_REV2;
3635 inquiry.ResponseDataFormat =
3636 IPS_SCSI_INQ_RD_REV2;
3637 inquiry.AdditionalLength = 31;
3638 inquiry.Flags[0] =
3639 IPS_SCSI_INQ_Address16;
3640 inquiry.Flags[1] =
3641 IPS_SCSI_INQ_WBus16 |
3642 IPS_SCSI_INQ_Sync;
3643 strncpy(inquiry.VendorId, "IBM ",
3644 8);
3645 strncpy(inquiry.ProductId,
3646 "SERVERAID ", 16);
3647 strncpy(inquiry.ProductRevisionLevel,
3648 "1.00", 4);
3649
3650 ips_scmd_buf_write(scb->scsi_cmd,
3651 &inquiry,
3652 sizeof (inquiry));
3653
3654 scb->scsi_cmd->result = DID_OK << 16;
3655 }
3656 } else {
3657 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3658 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3659 scb->cmd.logical_info.reserved = 0;
3660 scb->cmd.logical_info.reserved2 = 0;
3661 scb->data_len = sizeof (IPS_LD_INFO);
3662 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3663 scb->flags = 0;
3664 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3665 ret = IPS_SUCCESS;
3666 }
3667
3668 break;
3669
3670 case REQUEST_SENSE:
3671 ips_reqsen(ha, scb);
3672 scb->scsi_cmd->result = DID_OK << 16;
3673 break;
3674
3675 case READ_6:
3676 case WRITE_6:
3677 if (!scb->sg_len) {
3678 scb->cmd.basic_io.op_code =
3679 (scb->scsi_cmd->cmnd[0] ==
3680 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3681 scb->cmd.basic_io.enhanced_sg = 0;
3682 scb->cmd.basic_io.sg_addr =
3683 cpu_to_le32(scb->data_busaddr);
3684 } else {
3685 scb->cmd.basic_io.op_code =
3686 (scb->scsi_cmd->cmnd[0] ==
3687 READ_6) ? IPS_CMD_READ_SG :
3688 IPS_CMD_WRITE_SG;
3689 scb->cmd.basic_io.enhanced_sg =
3690 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3691 scb->cmd.basic_io.sg_addr =
3692 cpu_to_le32(scb->sg_busaddr);
3693 }
3694
3695 scb->cmd.basic_io.segment_4G = 0;
3696 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3697 scb->cmd.basic_io.log_drv = scb->target_id;
3698 scb->cmd.basic_io.sg_count = scb->sg_len;
3699
3700 if (scb->cmd.basic_io.lba)
3701 scb->cmd.basic_io.lba =
3702 cpu_to_le32(le32_to_cpu
3703 (scb->cmd.basic_io.lba) +
3704 le16_to_cpu(scb->cmd.basic_io.
3705 sector_count));
3706 else
3707 scb->cmd.basic_io.lba =
3708 (((scb->scsi_cmd->
3709 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3710 cmnd[2] << 8) |
3711 (scb->scsi_cmd->cmnd[3]));
3712
3713 scb->cmd.basic_io.sector_count =
3714 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3715
3716 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3717 scb->cmd.basic_io.sector_count =
3718 cpu_to_le16(256);
3719
3720 ret = IPS_SUCCESS;
3721 break;
3722
3723 case READ_10:
3724 case WRITE_10:
3725 if (!scb->sg_len) {
3726 scb->cmd.basic_io.op_code =
3727 (scb->scsi_cmd->cmnd[0] ==
3728 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3729 scb->cmd.basic_io.enhanced_sg = 0;
3730 scb->cmd.basic_io.sg_addr =
3731 cpu_to_le32(scb->data_busaddr);
3732 } else {
3733 scb->cmd.basic_io.op_code =
3734 (scb->scsi_cmd->cmnd[0] ==
3735 READ_10) ? IPS_CMD_READ_SG :
3736 IPS_CMD_WRITE_SG;
3737 scb->cmd.basic_io.enhanced_sg =
3738 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3739 scb->cmd.basic_io.sg_addr =
3740 cpu_to_le32(scb->sg_busaddr);
3741 }
3742
3743 scb->cmd.basic_io.segment_4G = 0;
3744 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3745 scb->cmd.basic_io.log_drv = scb->target_id;
3746 scb->cmd.basic_io.sg_count = scb->sg_len;
3747
3748 if (scb->cmd.basic_io.lba)
3749 scb->cmd.basic_io.lba =
3750 cpu_to_le32(le32_to_cpu
3751 (scb->cmd.basic_io.lba) +
3752 le16_to_cpu(scb->cmd.basic_io.
3753 sector_count));
3754 else
3755 scb->cmd.basic_io.lba =
3756 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3757 scsi_cmd->
3758 cmnd[3]
3759 << 16) |
3760 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3761 scsi_cmd->cmnd[5]);
3762
3763 scb->cmd.basic_io.sector_count =
3764 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3765
3766 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3767 /*
3768 * This is a null condition
3769 * we don't have to do anything
3770 * so just return
3771 */
3772 scb->scsi_cmd->result = DID_OK << 16;
3773 } else
3774 ret = IPS_SUCCESS;
3775
3776 break;
3777
3778 case RESERVE:
3779 case RELEASE:
3780 scb->scsi_cmd->result = DID_OK << 16;
3781 break;
3782
3783 case MODE_SENSE:
3784 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3785 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3786 scb->cmd.basic_io.segment_4G = 0;
3787 scb->cmd.basic_io.enhanced_sg = 0;
3788 scb->data_len = sizeof (*ha->enq);
3789 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3790 ret = IPS_SUCCESS;
3791 break;
3792
3793 case READ_CAPACITY:
3794 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3795 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3796 scb->cmd.logical_info.reserved = 0;
3797 scb->cmd.logical_info.reserved2 = 0;
3798 scb->cmd.logical_info.reserved3 = 0;
3799 scb->data_len = sizeof (IPS_LD_INFO);
3800 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3801 scb->flags = 0;
3802 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3803 ret = IPS_SUCCESS;
3804 break;
3805
3806 case SEND_DIAGNOSTIC:
3807 case REASSIGN_BLOCKS:
3808 case FORMAT_UNIT:
3809 case SEEK_10:
3810 case VERIFY:
3811 case READ_DEFECT_DATA:
3812 case READ_BUFFER:
3813 case WRITE_BUFFER:
3814 scb->scsi_cmd->result = DID_OK << 16;
3815 break;
3816
3817 default:
3818 /* Set the Return Info to appear like the Command was */
3819 /* attempted, a Check Condition occurred, and Sense */
3820 /* Data indicating an Invalid CDB OpCode is returned. */
3821 sp = (char *) scb->scsi_cmd->sense_buffer;
3822
3823 sp[0] = 0x70; /* Error Code */
3824 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
3825 sp[7] = 0x0A; /* Additional Sense Length */
3826 sp[12] = 0x20; /* ASC = Invalid OpCode */
3827 sp[13] = 0x00; /* ASCQ */
3828
3829 device_error = 2; /* Indicate Check Condition */
3830 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3831 break;
3832 } /* end switch */
3833 }
3834 /* end if */
3835 if (ret == IPS_SUCCESS_IMM)
3836 return (ret);
3837
3838 /* setup DCDB */
3839 if (scb->bus > 0) {
3840
3841 /* If we already know the Device is Not there, no need to attempt a Command */
3842 /* This also protects an NT FailOver Controller from getting CDB's sent to it */
3843 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3844 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3845 return (IPS_SUCCESS_IMM);
3846 }
3847
3848 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3849 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3850 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3851 (unsigned long) &scb->
3852 dcdb -
3853 (unsigned long) scb);
3854 scb->cmd.dcdb.reserved = 0;
3855 scb->cmd.dcdb.reserved2 = 0;
3856 scb->cmd.dcdb.reserved3 = 0;
3857 scb->cmd.dcdb.segment_4G = 0;
3858 scb->cmd.dcdb.enhanced_sg = 0;
3859
3860 TimeOut = scb->scsi_cmd->timeout_per_command;
3861
3862 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3863 if (!scb->sg_len) {
3864 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3865 } else {
3866 scb->cmd.dcdb.op_code =
3867 IPS_CMD_EXTENDED_DCDB_SG;
3868 scb->cmd.dcdb.enhanced_sg =
3869 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3870 }
3871
3872 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
3873 tapeDCDB->device_address =
3874 ((scb->bus - 1) << 4) | scb->target_id;
3875 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3876 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
3877
3878 if (TimeOut) {
3879 if (TimeOut < (10 * HZ))
3880 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3881 else if (TimeOut < (60 * HZ))
3882 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3883 else if (TimeOut < (1200 * HZ))
3884 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3885 }
3886
3887 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
3888 tapeDCDB->reserved_for_LUN = 0;
3889 tapeDCDB->transfer_length = scb->data_len;
3890 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
3891 tapeDCDB->buffer_pointer =
3892 cpu_to_le32(scb->sg_busaddr);
3893 else
3894 tapeDCDB->buffer_pointer =
3895 cpu_to_le32(scb->data_busaddr);
3896 tapeDCDB->sg_count = scb->sg_len;
3897 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
3898 tapeDCDB->scsi_status = 0;
3899 tapeDCDB->reserved = 0;
3900 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
3901 scb->scsi_cmd->cmd_len);
3902 } else {
3903 if (!scb->sg_len) {
3904 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
3905 } else {
3906 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
3907 scb->cmd.dcdb.enhanced_sg =
3908 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3909 }
3910
3911 scb->dcdb.device_address =
3912 ((scb->bus - 1) << 4) | scb->target_id;
3913 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3914
3915 if (TimeOut) {
3916 if (TimeOut < (10 * HZ))
3917 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3918 else if (TimeOut < (60 * HZ))
3919 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3920 else if (TimeOut < (1200 * HZ))
3921 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3922 }
3923
3924 scb->dcdb.transfer_length = scb->data_len;
3925 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
3926 scb->dcdb.transfer_length = 0;
3927 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
3928 scb->dcdb.buffer_pointer =
3929 cpu_to_le32(scb->sg_busaddr);
3930 else
3931 scb->dcdb.buffer_pointer =
3932 cpu_to_le32(scb->data_busaddr);
3933 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
3934 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
3935 scb->dcdb.sg_count = scb->sg_len;
3936 scb->dcdb.reserved = 0;
3937 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
3938 scb->scsi_cmd->cmd_len);
3939 scb->dcdb.scsi_status = 0;
3940 scb->dcdb.reserved2[0] = 0;
3941 scb->dcdb.reserved2[1] = 0;
3942 scb->dcdb.reserved2[2] = 0;
3943 }
3944 }
3945
3946 return ((*ha->func.issue) (ha, scb));
3947 }
3948
3949 /****************************************************************************/
3950 /* */
3951 /* Routine Name: ips_chk_status */
3952 /* */
3953 /* Routine Description: */
3954 /* */
3955 /* Check the status of commands to logical drives */
3956 /* Assumed to be called with the HA lock */
3957 /****************************************************************************/
3958 static void
3959 ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
3960 {
3961 ips_scb_t *scb;
3962 ips_stat_t *sp;
3963 uint8_t basic_status;
3964 uint8_t ext_status;
3965 int errcode;
3966 IPS_SCSI_INQ_DATA inquiryData;
3967
3968 METHOD_TRACE("ips_chkstatus", 1);
3969
3970 scb = &ha->scbs[pstatus->fields.command_id];
3971 scb->basic_status = basic_status =
3972 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
3973 scb->extended_status = ext_status = pstatus->fields.extended_status;
3974
3975 sp = &ha->sp;
3976 sp->residue_len = 0;
3977 sp->scb_addr = (void *) scb;
3978
3979 /* Remove the item from the active queue */
3980 ips_removeq_scb(&ha->scb_activelist, scb);
3981
3982 if (!scb->scsi_cmd)
3983 /* internal commands are handled in do_ipsintr */
3984 return;
3985
3986 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
3987 ips_name,
3988 ha->host_num,
3989 scb->cdb[0],
3990 scb->cmd.basic_io.command_id,
3991 scb->bus, scb->target_id, scb->lun);
3992
3993 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
3994 /* passthru - just returns the raw result */
3995 return;
3996
3997 errcode = DID_OK;
3998
3999 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
4000 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
4001
4002 if (scb->bus == 0) {
4003 if ((basic_status & IPS_GSC_STATUS_MASK) ==
4004 IPS_CMD_RECOVERED_ERROR) {
4005 DEBUG_VAR(1,
4006 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
4007 ips_name, ha->host_num,
4008 scb->cmd.basic_io.op_code,
4009 basic_status, ext_status);
4010 }
4011
4012 switch (scb->scsi_cmd->cmnd[0]) {
4013 case ALLOW_MEDIUM_REMOVAL:
4014 case REZERO_UNIT:
4015 case ERASE:
4016 case WRITE_FILEMARKS:
4017 case SPACE:
4018 errcode = DID_ERROR;
4019 break;
4020
4021 case START_STOP:
4022 break;
4023
4024 case TEST_UNIT_READY:
4025 if (!ips_online(ha, scb)) {
4026 errcode = DID_TIME_OUT;
4027 }
4028 break;
4029
4030 case INQUIRY:
4031 if (ips_online(ha, scb)) {
4032 ips_inquiry(ha, scb);
4033 } else {
4034 errcode = DID_TIME_OUT;
4035 }
4036 break;
4037
4038 case REQUEST_SENSE:
4039 ips_reqsen(ha, scb);
4040 break;
4041
4042 case READ_6:
4043 case WRITE_6:
4044 case READ_10:
4045 case WRITE_10:
4046 case RESERVE:
4047 case RELEASE:
4048 break;
4049
4050 case MODE_SENSE:
4051 if (!ips_online(ha, scb)
4052 || !ips_msense(ha, scb)) {
4053 errcode = DID_ERROR;
4054 }
4055 break;
4056
4057 case READ_CAPACITY:
4058 if (ips_online(ha, scb))
4059 ips_rdcap(ha, scb);
4060 else {
4061 errcode = DID_TIME_OUT;
4062 }
4063 break;
4064
4065 case SEND_DIAGNOSTIC:
4066 case REASSIGN_BLOCKS:
4067 break;
4068
4069 case FORMAT_UNIT:
4070 errcode = DID_ERROR;
4071 break;
4072
4073 case SEEK_10:
4074 case VERIFY:
4075 case READ_DEFECT_DATA:
4076 case READ_BUFFER:
4077 case WRITE_BUFFER:
4078 break;
4079
4080 default:
4081 errcode = DID_ERROR;
4082 } /* end switch */
4083
4084 scb->scsi_cmd->result = errcode << 16;
4085 } else { /* bus == 0 */
4086 /* restrict access to physical drives */
4087 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
4088 ips_scmd_buf_read(scb->scsi_cmd,
4089 &inquiryData, sizeof (inquiryData));
4090 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK)
4091 scb->scsi_cmd->result = DID_TIME_OUT << 16;
4092 }
4093 } /* else */
4094 } else { /* recovered error / success */
4095 if (scb->bus == 0) {
4096 DEBUG_VAR(1,
4097 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
4098 ips_name, ha->host_num,
4099 scb->cmd.basic_io.op_code, basic_status,
4100 ext_status);
4101 }
4102
4103 ips_map_status(ha, scb, sp);
4104 } /* else */
4105 }
4106
4107 /****************************************************************************/
4108 /* */
4109 /* Routine Name: ips_online */
4110 /* */
4111 /* Routine Description: */
4112 /* */
4113 /* Determine if a logical drive is online */
4114 /* */
4115 /****************************************************************************/
4116 static int
4117 ips_online(ips_ha_t * ha, ips_scb_t * scb)
4118 {
4119 METHOD_TRACE("ips_online", 1);
4120
4121 if (scb->target_id >= IPS_MAX_LD)
4122 return (0);
4123
4124 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
4125 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4126 return (0);
4127 }
4128
4129 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4130 IPS_LD_OFFLINE
4131 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4132 IPS_LD_FREE
4133 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4134 IPS_LD_CRS
4135 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4136 IPS_LD_SYS)
4137 return (1);
4138 else
4139 return (0);
4140 }
4141
4142 /****************************************************************************/
4143 /* */
4144 /* Routine Name: ips_inquiry */
4145 /* */
4146 /* Routine Description: */
4147 /* */
4148 /* Simulate an inquiry command to a logical drive */
4149 /* */
4150 /****************************************************************************/
4151 static int
4152 ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4153 {
4154 IPS_SCSI_INQ_DATA inquiry;
4155
4156 METHOD_TRACE("ips_inquiry", 1);
4157
4158 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4159
4160 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4161 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4162 inquiry.Version = IPS_SCSI_INQ_REV2;
4163 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4164 inquiry.AdditionalLength = 31;
4165 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4166 inquiry.Flags[1] =
4167 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4168 strncpy(inquiry.VendorId, "IBM ", 8);
4169 strncpy(inquiry.ProductId, "SERVERAID ", 16);
4170 strncpy(inquiry.ProductRevisionLevel, "1.00", 4);
4171
4172 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4173
4174 return (1);
4175 }
4176
4177 /****************************************************************************/
4178 /* */
4179 /* Routine Name: ips_rdcap */
4180 /* */
4181 /* Routine Description: */
4182 /* */
4183 /* Simulate a read capacity command to a logical drive */
4184 /* */
4185 /****************************************************************************/
4186 static int
4187 ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4188 {
4189 IPS_SCSI_CAPACITY cap;
4190
4191 METHOD_TRACE("ips_rdcap", 1);
4192
4193 if (scsi_bufflen(scb->scsi_cmd) < 8)
4194 return (0);
4195
4196 cap.lba =
4197 cpu_to_be32(le32_to_cpu
4198 (ha->logical_drive_info->
4199 drive_info[scb->target_id].sector_count) - 1);
4200 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4201
4202 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4203
4204 return (1);
4205 }
4206
4207 /****************************************************************************/
4208 /* */
4209 /* Routine Name: ips_msense */
4210 /* */
4211 /* Routine Description: */
4212 /* */
4213 /* Simulate a mode sense command to a logical drive */
4214 /* */
4215 /****************************************************************************/
4216 static int
4217 ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4218 {
4219 uint16_t heads;
4220 uint16_t sectors;
4221 uint32_t cylinders;
4222 IPS_SCSI_MODE_PAGE_DATA mdata;
4223
4224 METHOD_TRACE("ips_msense", 1);
4225
4226 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4227 (ha->enq->ucMiscFlag & 0x8) == 0) {
4228 heads = IPS_NORM_HEADS;
4229 sectors = IPS_NORM_SECTORS;
4230 } else {
4231 heads = IPS_COMP_HEADS;
4232 sectors = IPS_COMP_SECTORS;
4233 }
4234
4235 cylinders =
4236 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4237 1) / (heads * sectors);
4238
4239 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4240
4241 mdata.hdr.BlockDescLength = 8;
4242
4243 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4244 case 0x03: /* page 3 */
4245 mdata.pdata.pg3.PageCode = 3;
4246 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4247 mdata.hdr.DataLength =
4248 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4249 mdata.pdata.pg3.TracksPerZone = 0;
4250 mdata.pdata.pg3.AltSectorsPerZone = 0;
4251 mdata.pdata.pg3.AltTracksPerZone = 0;
4252 mdata.pdata.pg3.AltTracksPerVolume = 0;
4253 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4254 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4255 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4256 mdata.pdata.pg3.TrackSkew = 0;
4257 mdata.pdata.pg3.CylinderSkew = 0;
4258 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4259 break;
4260
4261 case 0x4:
4262 mdata.pdata.pg4.PageCode = 4;
4263 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4264 mdata.hdr.DataLength =
4265 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4266 mdata.pdata.pg4.CylindersHigh =
4267 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4268 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4269 mdata.pdata.pg4.Heads = heads;
4270 mdata.pdata.pg4.WritePrecompHigh = 0;
4271 mdata.pdata.pg4.WritePrecompLow = 0;
4272 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4273 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4274 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4275 mdata.pdata.pg4.LandingZoneHigh = 0;
4276 mdata.pdata.pg4.LandingZoneLow = 0;
4277 mdata.pdata.pg4.flags = 0;
4278 mdata.pdata.pg4.RotationalOffset = 0;
4279 mdata.pdata.pg4.MediumRotationRate = 0;
4280 break;
4281 case 0x8:
4282 mdata.pdata.pg8.PageCode = 8;
4283 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4284 mdata.hdr.DataLength =
4285 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4286 /* everything else is left set to 0 */
4287 break;
4288
4289 default:
4290 return (0);
4291 } /* end switch */
4292
4293 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4294
4295 return (1);
4296 }
4297
4298 /****************************************************************************/
4299 /* */
4300 /* Routine Name: ips_reqsen */
4301 /* */
4302 /* Routine Description: */
4303 /* */
4304 /* Simulate a request sense command to a logical drive */
4305 /* */
4306 /****************************************************************************/
4307 static int
4308 ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4309 {
4310 IPS_SCSI_REQSEN reqsen;
4311
4312 METHOD_TRACE("ips_reqsen", 1);
4313
4314 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4315
4316 reqsen.ResponseCode =
4317 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4318 reqsen.AdditionalLength = 10;
4319 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4320 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4321
4322 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4323
4324 return (1);
4325 }
4326
4327 /****************************************************************************/
4328 /* */
4329 /* Routine Name: ips_free */
4330 /* */
4331 /* Routine Description: */
4332 /* */
4333 /* Free any allocated space for this controller */
4334 /* */
4335 /****************************************************************************/
4336 static void
4337 ips_free(ips_ha_t * ha)
4338 {
4339
4340 METHOD_TRACE("ips_free", 1);
4341
4342 if (ha) {
4343 if (ha->enq) {
4344 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ),
4345 ha->enq, ha->enq_busaddr);
4346 ha->enq = NULL;
4347 }
4348
4349 kfree(ha->conf);
4350 ha->conf = NULL;
4351
4352 if (ha->adapt) {
4353 pci_free_consistent(ha->pcidev,
4354 sizeof (IPS_ADAPTER) +
4355 sizeof (IPS_IO_CMD), ha->adapt,
4356 ha->adapt->hw_status_start);
4357 ha->adapt = NULL;
4358 }
4359
4360 if (ha->logical_drive_info) {
4361 pci_free_consistent(ha->pcidev,
4362 sizeof (IPS_LD_INFO),
4363 ha->logical_drive_info,
4364 ha->logical_drive_info_dma_addr);
4365 ha->logical_drive_info = NULL;
4366 }
4367
4368 kfree(ha->nvram);
4369 ha->nvram = NULL;
4370
4371 kfree(ha->subsys);
4372 ha->subsys = NULL;
4373
4374 if (ha->ioctl_data) {
4375 pci_free_consistent(ha->pcidev, ha->ioctl_len,
4376 ha->ioctl_data, ha->ioctl_busaddr);
4377 ha->ioctl_data = NULL;
4378 ha->ioctl_datasize = 0;
4379 ha->ioctl_len = 0;
4380 }
4381 ips_deallocatescbs(ha, ha->max_cmds);
4382
4383 /* free memory mapped (if applicable) */
4384 if (ha->mem_ptr) {
4385 iounmap(ha->ioremap_ptr);
4386 ha->ioremap_ptr = NULL;
4387 ha->mem_ptr = NULL;
4388 }
4389
4390 ha->mem_addr = 0;
4391
4392 }
4393 }
4394
4395 /****************************************************************************/
4396 /* */
4397 /* Routine Name: ips_deallocatescbs */
4398 /* */
4399 /* Routine Description: */
4400 /* */
4401 /* Free the command blocks */
4402 /* */
4403 /****************************************************************************/
4404 static int
4405 ips_deallocatescbs(ips_ha_t * ha, int cmds)
4406 {
4407 if (ha->scbs) {
4408 pci_free_consistent(ha->pcidev,
4409 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4410 ha->scbs->sg_list.list,
4411 ha->scbs->sg_busaddr);
4412 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds,
4413 ha->scbs, ha->scbs->scb_busaddr);
4414 ha->scbs = NULL;
4415 } /* end if */
4416 return 1;
4417 }
4418
4419 /****************************************************************************/
4420 /* */
4421 /* Routine Name: ips_allocatescbs */
4422 /* */
4423 /* Routine Description: */
4424 /* */
4425 /* Allocate the command blocks */
4426 /* */
4427 /****************************************************************************/
4428 static int
4429 ips_allocatescbs(ips_ha_t * ha)
4430 {
4431 ips_scb_t *scb_p;
4432 IPS_SG_LIST ips_sg;
4433 int i;
4434 dma_addr_t command_dma, sg_dma;
4435
4436 METHOD_TRACE("ips_allocatescbs", 1);
4437
4438 /* Allocate memory for the SCBs */
4439 ha->scbs =
4440 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t),
4441 &command_dma);
4442 if (ha->scbs == NULL)
4443 return 0;
4444 ips_sg.list =
4445 pci_alloc_consistent(ha->pcidev,
4446 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG *
4447 ha->max_cmds, &sg_dma);
4448 if (ips_sg.list == NULL) {
4449 pci_free_consistent(ha->pcidev,
4450 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4451 command_dma);
4452 return 0;
4453 }
4454
4455 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4456
4457 for (i = 0; i < ha->max_cmds; i++) {
4458 scb_p = &ha->scbs[i];
4459 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4460 /* set up S/G list */
4461 if (IPS_USE_ENH_SGLIST(ha)) {
4462 scb_p->sg_list.enh_list =
4463 ips_sg.enh_list + i * IPS_MAX_SG;
4464 scb_p->sg_busaddr =
4465 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4466 } else {
4467 scb_p->sg_list.std_list =
4468 ips_sg.std_list + i * IPS_MAX_SG;
4469 scb_p->sg_busaddr =
4470 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4471 }
4472
4473 /* add to the free list */
4474 if (i < ha->max_cmds - 1) {
4475 scb_p->q_next = ha->scb_freelist;
4476 ha->scb_freelist = scb_p;
4477 }
4478 }
4479
4480 /* success */
4481 return (1);
4482 }
4483
4484 /****************************************************************************/
4485 /* */
4486 /* Routine Name: ips_init_scb */
4487 /* */
4488 /* Routine Description: */
4489 /* */
4490 /* Initialize a CCB to default values */
4491 /* */
4492 /****************************************************************************/
4493 static void
4494 ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4495 {
4496 IPS_SG_LIST sg_list;
4497 uint32_t cmd_busaddr, sg_busaddr;
4498 METHOD_TRACE("ips_init_scb", 1);
4499
4500 if (scb == NULL)
4501 return;
4502
4503 sg_list.list = scb->sg_list.list;
4504 cmd_busaddr = scb->scb_busaddr;
4505 sg_busaddr = scb->sg_busaddr;
4506 /* zero fill */
4507 memset(scb, 0, sizeof (ips_scb_t));
4508 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4509
4510 /* Initialize dummy command bucket */
4511 ha->dummy->op_code = 0xFF;
4512 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4513 + sizeof (IPS_ADAPTER));
4514 ha->dummy->command_id = IPS_MAX_CMDS;
4515
4516 /* set bus address of scb */
4517 scb->scb_busaddr = cmd_busaddr;
4518 scb->sg_busaddr = sg_busaddr;
4519 scb->sg_list.list = sg_list.list;
4520
4521 /* Neptune Fix */
4522 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4523 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4524 + sizeof (IPS_ADAPTER));
4525 }
4526
4527 /****************************************************************************/
4528 /* */
4529 /* Routine Name: ips_get_scb */
4530 /* */
4531 /* Routine Description: */
4532 /* */
4533 /* Initialize a CCB to default values */
4534 /* */
4535 /* ASSUMED to be callled from within a lock */
4536 /* */
4537 /****************************************************************************/
4538 static ips_scb_t *
4539 ips_getscb(ips_ha_t * ha)
4540 {
4541 ips_scb_t *scb;
4542
4543 METHOD_TRACE("ips_getscb", 1);
4544
4545 if ((scb = ha->scb_freelist) == NULL) {
4546
4547 return (NULL);
4548 }
4549
4550 ha->scb_freelist = scb->q_next;
4551 scb->flags = 0;
4552 scb->q_next = NULL;
4553
4554 ips_init_scb(ha, scb);
4555
4556 return (scb);
4557 }
4558
4559 /****************************************************************************/
4560 /* */
4561 /* Routine Name: ips_free_scb */
4562 /* */
4563 /* Routine Description: */
4564 /* */
4565 /* Return an unused CCB back to the free list */
4566 /* */
4567 /* ASSUMED to be called from within a lock */
4568 /* */
4569 /****************************************************************************/
4570 static void
4571 ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4572 {
4573
4574 METHOD_TRACE("ips_freescb", 1);
4575 if (scb->flags & IPS_SCB_MAP_SG)
4576 scsi_dma_unmap(scb->scsi_cmd);
4577 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4578 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len,
4579 IPS_DMA_DIR(scb));
4580
4581 /* check to make sure this is not our "special" scb */
4582 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4583 scb->q_next = ha->scb_freelist;
4584 ha->scb_freelist = scb;
4585 }
4586 }
4587
4588 /****************************************************************************/
4589 /* */
4590 /* Routine Name: ips_isinit_copperhead */
4591 /* */
4592 /* Routine Description: */
4593 /* */
4594 /* Is controller initialized ? */
4595 /* */
4596 /****************************************************************************/
4597 static int
4598 ips_isinit_copperhead(ips_ha_t * ha)
4599 {
4600 uint8_t scpr;
4601 uint8_t isr;
4602
4603 METHOD_TRACE("ips_isinit_copperhead", 1);
4604
4605 isr = inb(ha->io_addr + IPS_REG_HISR);
4606 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4607
4608 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4609 return (0);
4610 else
4611 return (1);
4612 }
4613
4614 /****************************************************************************/
4615 /* */
4616 /* Routine Name: ips_isinit_copperhead_memio */
4617 /* */
4618 /* Routine Description: */
4619 /* */
4620 /* Is controller initialized ? */
4621 /* */
4622 /****************************************************************************/
4623 static int
4624 ips_isinit_copperhead_memio(ips_ha_t * ha)
4625 {
4626 uint8_t isr = 0;
4627 uint8_t scpr;
4628
4629 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4630
4631 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4632 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4633
4634 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4635 return (0);
4636 else
4637 return (1);
4638 }
4639
4640 /****************************************************************************/
4641 /* */
4642 /* Routine Name: ips_isinit_morpheus */
4643 /* */
4644 /* Routine Description: */
4645 /* */
4646 /* Is controller initialized ? */
4647 /* */
4648 /****************************************************************************/
4649 static int
4650 ips_isinit_morpheus(ips_ha_t * ha)
4651 {
4652 uint32_t post;
4653 uint32_t bits;
4654
4655 METHOD_TRACE("ips_is_init_morpheus", 1);
4656
4657 if (ips_isintr_morpheus(ha))
4658 ips_flush_and_reset(ha);
4659
4660 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4661 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4662
4663 if (post == 0)
4664 return (0);
4665 else if (bits & 0x3)
4666 return (0);
4667 else
4668 return (1);
4669 }
4670
4671 /****************************************************************************/
4672 /* */
4673 /* Routine Name: ips_flush_and_reset */
4674 /* */
4675 /* Routine Description: */
4676 /* */
4677 /* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */
4678 /* state ( was trying to INIT and an interrupt was already pending ) ... */
4679 /* */
4680 /****************************************************************************/
4681 static void
4682 ips_flush_and_reset(ips_ha_t *ha)
4683 {
4684 ips_scb_t *scb;
4685 int ret;
4686 int time;
4687 int done;
4688 dma_addr_t command_dma;
4689
4690 /* Create a usuable SCB */
4691 scb = pci_alloc_consistent(ha->pcidev, sizeof(ips_scb_t), &command_dma);
4692 if (scb) {
4693 memset(scb, 0, sizeof(ips_scb_t));
4694 ips_init_scb(ha, scb);
4695 scb->scb_busaddr = command_dma;
4696
4697 scb->timeout = ips_cmd_timeout;
4698 scb->cdb[0] = IPS_CMD_FLUSH;
4699
4700 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
4701 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */
4702 scb->cmd.flush_cache.state = IPS_NORM_STATE;
4703 scb->cmd.flush_cache.reserved = 0;
4704 scb->cmd.flush_cache.reserved2 = 0;
4705 scb->cmd.flush_cache.reserved3 = 0;
4706 scb->cmd.flush_cache.reserved4 = 0;
4707
4708 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */
4709
4710 if (ret == IPS_SUCCESS) {
4711 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */
4712 done = 0;
4713
4714 while ((time > 0) && (!done)) {
4715 done = ips_poll_for_flush_complete(ha);
4716 /* This may look evil, but it's only done during extremely rare start-up conditions ! */
4717 udelay(1000);
4718 time--;
4719 }
4720 }
4721 }
4722
4723 /* Now RESET and INIT the adapter */
4724 (*ha->func.reset) (ha);
4725
4726 pci_free_consistent(ha->pcidev, sizeof(ips_scb_t), scb, command_dma);
4727 return;
4728 }
4729
4730 /****************************************************************************/
4731 /* */
4732 /* Routine Name: ips_poll_for_flush_complete */
4733 /* */
4734 /* Routine Description: */
4735 /* */
4736 /* Poll for the Flush Command issued by ips_flush_and_reset() to complete */
4737 /* All other responses are just taken off the queue and ignored */
4738 /* */
4739 /****************************************************************************/
4740 static int
4741 ips_poll_for_flush_complete(ips_ha_t * ha)
4742 {
4743 IPS_STATUS cstatus;
4744
4745 while (TRUE) {
4746 cstatus.value = (*ha->func.statupd) (ha);
4747
4748 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */
4749 break;
4750
4751 /* Success is when we see the Flush Command ID */
4752 if (cstatus.fields.command_id == IPS_MAX_CMDS)
4753 return 1;
4754 }
4755
4756 return 0;
4757 }
4758
4759 /****************************************************************************/
4760 /* */
4761 /* Routine Name: ips_enable_int_copperhead */
4762 /* */
4763 /* Routine Description: */
4764 /* Turn on interrupts */
4765 /* */
4766 /****************************************************************************/
4767 static void
4768 ips_enable_int_copperhead(ips_ha_t * ha)
4769 {
4770 METHOD_TRACE("ips_enable_int_copperhead", 1);
4771
4772 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4773 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4774 }
4775
4776 /****************************************************************************/
4777 /* */
4778 /* Routine Name: ips_enable_int_copperhead_memio */
4779 /* */
4780 /* Routine Description: */
4781 /* Turn on interrupts */
4782 /* */
4783 /****************************************************************************/
4784 static void
4785 ips_enable_int_copperhead_memio(ips_ha_t * ha)
4786 {
4787 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4788
4789 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4790 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4791 }
4792
4793 /****************************************************************************/
4794 /* */
4795 /* Routine Name: ips_enable_int_morpheus */
4796 /* */
4797 /* Routine Description: */
4798 /* Turn on interrupts */
4799 /* */
4800 /****************************************************************************/
4801 static void
4802 ips_enable_int_morpheus(ips_ha_t * ha)
4803 {
4804 uint32_t Oimr;
4805
4806 METHOD_TRACE("ips_enable_int_morpheus", 1);
4807
4808 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4809 Oimr &= ~0x08;
4810 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4811 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4812 }
4813
4814 /****************************************************************************/
4815 /* */
4816 /* Routine Name: ips_init_copperhead */
4817 /* */
4818 /* Routine Description: */
4819 /* */
4820 /* Initialize a copperhead controller */
4821 /* */
4822 /****************************************************************************/
4823 static int
4824 ips_init_copperhead(ips_ha_t * ha)
4825 {
4826 uint8_t Isr;
4827 uint8_t Cbsp;
4828 uint8_t PostByte[IPS_MAX_POST_BYTES];
4829 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4830 int i, j;
4831
4832 METHOD_TRACE("ips_init_copperhead", 1);
4833
4834 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4835 for (j = 0; j < 45; j++) {
4836 Isr = inb(ha->io_addr + IPS_REG_HISR);
4837 if (Isr & IPS_BIT_GHI)
4838 break;
4839
4840 /* Delay for 1 Second */
4841 MDELAY(IPS_ONE_SEC);
4842 }
4843
4844 if (j >= 45)
4845 /* error occurred */
4846 return (0);
4847
4848 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4849 outb(Isr, ha->io_addr + IPS_REG_HISR);
4850 }
4851
4852 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4853 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4854 "reset controller fails (post status %x %x).\n",
4855 PostByte[0], PostByte[1]);
4856
4857 return (0);
4858 }
4859
4860 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4861 for (j = 0; j < 240; j++) {
4862 Isr = inb(ha->io_addr + IPS_REG_HISR);
4863 if (Isr & IPS_BIT_GHI)
4864 break;
4865
4866 /* Delay for 1 Second */
4867 MDELAY(IPS_ONE_SEC);
4868 }
4869
4870 if (j >= 240)
4871 /* error occurred */
4872 return (0);
4873
4874 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4875 outb(Isr, ha->io_addr + IPS_REG_HISR);
4876 }
4877
4878 for (i = 0; i < 240; i++) {
4879 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4880
4881 if ((Cbsp & IPS_BIT_OP) == 0)
4882 break;
4883
4884 /* Delay for 1 Second */
4885 MDELAY(IPS_ONE_SEC);
4886 }
4887
4888 if (i >= 240)
4889 /* reset failed */
4890 return (0);
4891
4892 /* setup CCCR */
4893 outl(cpu_to_le32(0x1010), ha->io_addr + IPS_REG_CCCR);
4894
4895 /* Enable busmastering */
4896 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4897
4898 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4899 /* fix for anaconda64 */
4900 outl(0, ha->io_addr + IPS_REG_NDAE);
4901
4902 /* Enable interrupts */
4903 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4904
4905 return (1);
4906 }
4907
4908 /****************************************************************************/
4909 /* */
4910 /* Routine Name: ips_init_copperhead_memio */
4911 /* */
4912 /* Routine Description: */
4913 /* */
4914 /* Initialize a copperhead controller with memory mapped I/O */
4915 /* */
4916 /****************************************************************************/
4917 static int
4918 ips_init_copperhead_memio(ips_ha_t * ha)
4919 {
4920 uint8_t Isr = 0;
4921 uint8_t Cbsp;
4922 uint8_t PostByte[IPS_MAX_POST_BYTES];
4923 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4924 int i, j;
4925
4926 METHOD_TRACE("ips_init_copperhead_memio", 1);
4927
4928 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4929 for (j = 0; j < 45; j++) {
4930 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4931 if (Isr & IPS_BIT_GHI)
4932 break;
4933
4934 /* Delay for 1 Second */
4935 MDELAY(IPS_ONE_SEC);
4936 }
4937
4938 if (j >= 45)
4939 /* error occurred */
4940 return (0);
4941
4942 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4943 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4944 }
4945
4946 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4947 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4948 "reset controller fails (post status %x %x).\n",
4949 PostByte[0], PostByte[1]);
4950
4951 return (0);
4952 }
4953
4954 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4955 for (j = 0; j < 240; j++) {
4956 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4957 if (Isr & IPS_BIT_GHI)
4958 break;
4959
4960 /* Delay for 1 Second */
4961 MDELAY(IPS_ONE_SEC);
4962 }
4963
4964 if (j >= 240)
4965 /* error occurred */
4966 return (0);
4967
4968 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4969 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4970 }
4971
4972 for (i = 0; i < 240; i++) {
4973 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
4974
4975 if ((Cbsp & IPS_BIT_OP) == 0)
4976 break;
4977
4978 /* Delay for 1 Second */
4979 MDELAY(IPS_ONE_SEC);
4980 }
4981
4982 if (i >= 240)
4983 /* error occurred */
4984 return (0);
4985
4986 /* setup CCCR */
4987 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
4988
4989 /* Enable busmastering */
4990 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4991
4992 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4993 /* fix for anaconda64 */
4994 writel(0, ha->mem_ptr + IPS_REG_NDAE);
4995
4996 /* Enable interrupts */
4997 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4998
4999 /* if we get here then everything went OK */
5000 return (1);
5001 }
5002
5003 /****************************************************************************/
5004 /* */
5005 /* Routine Name: ips_init_morpheus */
5006 /* */
5007 /* Routine Description: */
5008 /* */
5009 /* Initialize a morpheus controller */
5010 /* */
5011 /****************************************************************************/
5012 static int
5013 ips_init_morpheus(ips_ha_t * ha)
5014 {
5015 uint32_t Post;
5016 uint32_t Config;
5017 uint32_t Isr;
5018 uint32_t Oimr;
5019 int i;
5020
5021 METHOD_TRACE("ips_init_morpheus", 1);
5022
5023 /* Wait up to 45 secs for Post */
5024 for (i = 0; i < 45; i++) {
5025 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5026
5027 if (Isr & IPS_BIT_I960_MSG0I)
5028 break;
5029
5030 /* Delay for 1 Second */
5031 MDELAY(IPS_ONE_SEC);
5032 }
5033
5034 if (i >= 45) {
5035 /* error occurred */
5036 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5037 "timeout waiting for post.\n");
5038
5039 return (0);
5040 }
5041
5042 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5043
5044 if (Post == 0x4F00) { /* If Flashing the Battery PIC */
5045 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5046 "Flashing Battery PIC, Please wait ...\n");
5047
5048 /* Clear the interrupt bit */
5049 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5050 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5051
5052 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
5053 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5054 if (Post != 0x4F00)
5055 break;
5056 /* Delay for 1 Second */
5057 MDELAY(IPS_ONE_SEC);
5058 }
5059
5060 if (i >= 120) {
5061 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5062 "timeout waiting for Battery PIC Flash\n");
5063 return (0);
5064 }
5065
5066 }
5067
5068 /* Clear the interrupt bit */
5069 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5070 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5071
5072 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
5073 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5074 "reset controller fails (post status %x).\n", Post);
5075
5076 return (0);
5077 }
5078
5079 /* Wait up to 240 secs for config bytes */
5080 for (i = 0; i < 240; i++) {
5081 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5082
5083 if (Isr & IPS_BIT_I960_MSG1I)
5084 break;
5085
5086 /* Delay for 1 Second */
5087 MDELAY(IPS_ONE_SEC);
5088 }
5089
5090 if (i >= 240) {
5091 /* error occurred */
5092 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5093 "timeout waiting for config.\n");
5094
5095 return (0);
5096 }
5097
5098 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
5099
5100 /* Clear interrupt bit */
5101 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
5102 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5103
5104 /* Turn on the interrupts */
5105 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
5106 Oimr &= ~0x8;
5107 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
5108
5109 /* if we get here then everything went OK */
5110
5111 /* Since we did a RESET, an EraseStripeLock may be needed */
5112 if (Post == 0xEF10) {
5113 if ((Config == 0x000F) || (Config == 0x0009))
5114 ha->requires_esl = 1;
5115 }
5116
5117 return (1);
5118 }
5119
5120 /****************************************************************************/
5121 /* */
5122 /* Routine Name: ips_reset_copperhead */
5123 /* */
5124 /* Routine Description: */
5125 /* */
5126 /* Reset the controller */
5127 /* */
5128 /****************************************************************************/
5129 static int
5130 ips_reset_copperhead(ips_ha_t * ha)
5131 {
5132 int reset_counter;
5133
5134 METHOD_TRACE("ips_reset_copperhead", 1);
5135
5136 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5137 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq);
5138
5139 reset_counter = 0;
5140
5141 while (reset_counter < 2) {
5142 reset_counter++;
5143
5144 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5145
5146 /* Delay for 1 Second */
5147 MDELAY(IPS_ONE_SEC);
5148
5149 outb(0, ha->io_addr + IPS_REG_SCPR);
5150
5151 /* Delay for 1 Second */
5152 MDELAY(IPS_ONE_SEC);
5153
5154 if ((*ha->func.init) (ha))
5155 break;
5156 else if (reset_counter >= 2) {
5157
5158 return (0);
5159 }
5160 }
5161
5162 return (1);
5163 }
5164
5165 /****************************************************************************/
5166 /* */
5167 /* Routine Name: ips_reset_copperhead_memio */
5168 /* */
5169 /* Routine Description: */
5170 /* */
5171 /* Reset the controller */
5172 /* */
5173 /****************************************************************************/
5174 static int
5175 ips_reset_copperhead_memio(ips_ha_t * ha)
5176 {
5177 int reset_counter;
5178
5179 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5180
5181 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5182 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5183
5184 reset_counter = 0;
5185
5186 while (reset_counter < 2) {
5187 reset_counter++;
5188
5189 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5190
5191 /* Delay for 1 Second */
5192 MDELAY(IPS_ONE_SEC);
5193
5194 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5195
5196 /* Delay for 1 Second */
5197 MDELAY(IPS_ONE_SEC);
5198
5199 if ((*ha->func.init) (ha))
5200 break;
5201 else if (reset_counter >= 2) {
5202
5203 return (0);
5204 }
5205 }
5206
5207 return (1);
5208 }
5209
5210 /****************************************************************************/
5211 /* */
5212 /* Routine Name: ips_reset_morpheus */
5213 /* */
5214 /* Routine Description: */
5215 /* */
5216 /* Reset the controller */
5217 /* */
5218 /****************************************************************************/
5219 static int
5220 ips_reset_morpheus(ips_ha_t * ha)
5221 {
5222 int reset_counter;
5223 uint8_t junk;
5224
5225 METHOD_TRACE("ips_reset_morpheus", 1);
5226
5227 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5228 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5229
5230 reset_counter = 0;
5231
5232 while (reset_counter < 2) {
5233 reset_counter++;
5234
5235 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5236
5237 /* Delay for 5 Seconds */
5238 MDELAY(5 * IPS_ONE_SEC);
5239
5240 /* Do a PCI config read to wait for adapter */
5241 pci_read_config_byte(ha->pcidev, 4, &junk);
5242
5243 if ((*ha->func.init) (ha))
5244 break;
5245 else if (reset_counter >= 2) {
5246
5247 return (0);
5248 }
5249 }
5250
5251 return (1);
5252 }
5253
5254 /****************************************************************************/
5255 /* */
5256 /* Routine Name: ips_statinit */
5257 /* */
5258 /* Routine Description: */
5259 /* */
5260 /* Initialize the status queues on the controller */
5261 /* */
5262 /****************************************************************************/
5263 static void
5264 ips_statinit(ips_ha_t * ha)
5265 {
5266 uint32_t phys_status_start;
5267
5268 METHOD_TRACE("ips_statinit", 1);
5269
5270 ha->adapt->p_status_start = ha->adapt->status;
5271 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5272 ha->adapt->p_status_tail = ha->adapt->status;
5273
5274 phys_status_start = ha->adapt->hw_status_start;
5275 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQSR);
5276 outl(cpu_to_le32(phys_status_start + IPS_STATUS_Q_SIZE),
5277 ha->io_addr + IPS_REG_SQER);
5278 outl(cpu_to_le32(phys_status_start + IPS_STATUS_SIZE),
5279 ha->io_addr + IPS_REG_SQHR);
5280 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQTR);
5281
5282 ha->adapt->hw_status_tail = phys_status_start;
5283 }
5284
5285 /****************************************************************************/
5286 /* */
5287 /* Routine Name: ips_statinit_memio */
5288 /* */
5289 /* Routine Description: */
5290 /* */
5291 /* Initialize the status queues on the controller */
5292 /* */
5293 /****************************************************************************/
5294 static void
5295 ips_statinit_memio(ips_ha_t * ha)
5296 {
5297 uint32_t phys_status_start;
5298
5299 METHOD_TRACE("ips_statinit_memio", 1);
5300
5301 ha->adapt->p_status_start = ha->adapt->status;
5302 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5303 ha->adapt->p_status_tail = ha->adapt->status;
5304
5305 phys_status_start = ha->adapt->hw_status_start;
5306 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5307 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5308 ha->mem_ptr + IPS_REG_SQER);
5309 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5310 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5311
5312 ha->adapt->hw_status_tail = phys_status_start;
5313 }
5314
5315 /****************************************************************************/
5316 /* */
5317 /* Routine Name: ips_statupd_copperhead */
5318 /* */
5319 /* Routine Description: */
5320 /* */
5321 /* Remove an element from the status queue */
5322 /* */
5323 /****************************************************************************/
5324 static uint32_t
5325 ips_statupd_copperhead(ips_ha_t * ha)
5326 {
5327 METHOD_TRACE("ips_statupd_copperhead", 1);
5328
5329 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5330 ha->adapt->p_status_tail++;
5331 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5332 } else {
5333 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5334 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5335 }
5336
5337 outl(cpu_to_le32(ha->adapt->hw_status_tail),
5338 ha->io_addr + IPS_REG_SQTR);
5339
5340 return (ha->adapt->p_status_tail->value);
5341 }
5342
5343 /****************************************************************************/
5344 /* */
5345 /* Routine Name: ips_statupd_copperhead_memio */
5346 /* */
5347 /* Routine Description: */
5348 /* */
5349 /* Remove an element from the status queue */
5350 /* */
5351 /****************************************************************************/
5352 static uint32_t
5353 ips_statupd_copperhead_memio(ips_ha_t * ha)
5354 {
5355 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5356
5357 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5358 ha->adapt->p_status_tail++;
5359 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5360 } else {
5361 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5362 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5363 }
5364
5365 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5366
5367 return (ha->adapt->p_status_tail->value);
5368 }
5369
5370 /****************************************************************************/
5371 /* */
5372 /* Routine Name: ips_statupd_morpheus */
5373 /* */
5374 /* Routine Description: */
5375 /* */
5376 /* Remove an element from the status queue */
5377 /* */
5378 /****************************************************************************/
5379 static uint32_t
5380 ips_statupd_morpheus(ips_ha_t * ha)
5381 {
5382 uint32_t val;
5383
5384 METHOD_TRACE("ips_statupd_morpheus", 1);
5385
5386 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5387
5388 return (val);
5389 }
5390
5391 /****************************************************************************/
5392 /* */
5393 /* Routine Name: ips_issue_copperhead */
5394 /* */
5395 /* Routine Description: */
5396 /* */
5397 /* Send a command down to the controller */
5398 /* */
5399 /****************************************************************************/
5400 static int
5401 ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5402 {
5403 uint32_t TimeOut;
5404 uint32_t val;
5405
5406 METHOD_TRACE("ips_issue_copperhead", 1);
5407
5408 if (scb->scsi_cmd) {
5409 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5410 ips_name,
5411 ha->host_num,
5412 scb->cdb[0],
5413 scb->cmd.basic_io.command_id,
5414 scb->bus, scb->target_id, scb->lun);
5415 } else {
5416 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5417 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5418 }
5419
5420 TimeOut = 0;
5421
5422 while ((val =
5423 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5424 udelay(1000);
5425
5426 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5427 if (!(val & IPS_BIT_START_STOP))
5428 break;
5429
5430 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5431 "ips_issue val [0x%x].\n", val);
5432 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5433 "ips_issue semaphore chk timeout.\n");
5434
5435 return (IPS_FAILURE);
5436 } /* end if */
5437 } /* end while */
5438
5439 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_CCSAR);
5440 outw(cpu_to_le32(IPS_BIT_START_CMD), ha->io_addr + IPS_REG_CCCR);
5441
5442 return (IPS_SUCCESS);
5443 }
5444
5445 /****************************************************************************/
5446 /* */
5447 /* Routine Name: ips_issue_copperhead_memio */
5448 /* */
5449 /* Routine Description: */
5450 /* */
5451 /* Send a command down to the controller */
5452 /* */
5453 /****************************************************************************/
5454 static int
5455 ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5456 {
5457 uint32_t TimeOut;
5458 uint32_t val;
5459
5460 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5461
5462 if (scb->scsi_cmd) {
5463 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5464 ips_name,
5465 ha->host_num,
5466 scb->cdb[0],
5467 scb->cmd.basic_io.command_id,
5468 scb->bus, scb->target_id, scb->lun);
5469 } else {
5470 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5471 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5472 }
5473
5474 TimeOut = 0;
5475
5476 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5477 udelay(1000);
5478
5479 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5480 if (!(val & IPS_BIT_START_STOP))
5481 break;
5482
5483 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5484 "ips_issue val [0x%x].\n", val);
5485 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5486 "ips_issue semaphore chk timeout.\n");
5487
5488 return (IPS_FAILURE);
5489 } /* end if */
5490 } /* end while */
5491
5492 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5493 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5494
5495 return (IPS_SUCCESS);
5496 }
5497
5498 /****************************************************************************/
5499 /* */
5500 /* Routine Name: ips_issue_i2o */
5501 /* */
5502 /* Routine Description: */
5503 /* */
5504 /* Send a command down to the controller */
5505 /* */
5506 /****************************************************************************/
5507 static int
5508 ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5509 {
5510
5511 METHOD_TRACE("ips_issue_i2o", 1);
5512
5513 if (scb->scsi_cmd) {
5514 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5515 ips_name,
5516 ha->host_num,
5517 scb->cdb[0],
5518 scb->cmd.basic_io.command_id,
5519 scb->bus, scb->target_id, scb->lun);
5520 } else {
5521 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5522 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5523 }
5524
5525 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_I2O_INMSGQ);
5526
5527 return (IPS_SUCCESS);
5528 }
5529
5530 /****************************************************************************/
5531 /* */
5532 /* Routine Name: ips_issue_i2o_memio */
5533 /* */
5534 /* Routine Description: */
5535 /* */
5536 /* Send a command down to the controller */
5537 /* */
5538 /****************************************************************************/
5539 static int
5540 ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5541 {
5542
5543 METHOD_TRACE("ips_issue_i2o_memio", 1);
5544
5545 if (scb->scsi_cmd) {
5546 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5547 ips_name,
5548 ha->host_num,
5549 scb->cdb[0],
5550 scb->cmd.basic_io.command_id,
5551 scb->bus, scb->target_id, scb->lun);
5552 } else {
5553 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5554 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5555 }
5556
5557 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5558
5559 return (IPS_SUCCESS);
5560 }
5561
5562 /****************************************************************************/
5563 /* */
5564 /* Routine Name: ips_isintr_copperhead */
5565 /* */
5566 /* Routine Description: */
5567 /* */
5568 /* Test to see if an interrupt is for us */
5569 /* */
5570 /****************************************************************************/
5571 static int
5572 ips_isintr_copperhead(ips_ha_t * ha)
5573 {
5574 uint8_t Isr;
5575
5576 METHOD_TRACE("ips_isintr_copperhead", 2);
5577
5578 Isr = inb(ha->io_addr + IPS_REG_HISR);
5579
5580 if (Isr == 0xFF)
5581 /* ?!?! Nothing really there */
5582 return (0);
5583
5584 if (Isr & IPS_BIT_SCE)
5585 return (1);
5586 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5587 /* status queue overflow or GHI */
5588 /* just clear the interrupt */
5589 outb(Isr, ha->io_addr + IPS_REG_HISR);
5590 }
5591
5592 return (0);
5593 }
5594
5595 /****************************************************************************/
5596 /* */
5597 /* Routine Name: ips_isintr_copperhead_memio */
5598 /* */
5599 /* Routine Description: */
5600 /* */
5601 /* Test to see if an interrupt is for us */
5602 /* */
5603 /****************************************************************************/
5604 static int
5605 ips_isintr_copperhead_memio(ips_ha_t * ha)
5606 {
5607 uint8_t Isr;
5608
5609 METHOD_TRACE("ips_isintr_memio", 2);
5610
5611 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5612
5613 if (Isr == 0xFF)
5614 /* ?!?! Nothing really there */
5615 return (0);
5616
5617 if (Isr & IPS_BIT_SCE)
5618 return (1);
5619 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5620 /* status queue overflow or GHI */
5621 /* just clear the interrupt */
5622 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5623 }
5624
5625 return (0);
5626 }
5627
5628 /****************************************************************************/
5629 /* */
5630 /* Routine Name: ips_isintr_morpheus */
5631 /* */
5632 /* Routine Description: */
5633 /* */
5634 /* Test to see if an interrupt is for us */
5635 /* */
5636 /****************************************************************************/
5637 static int
5638 ips_isintr_morpheus(ips_ha_t * ha)
5639 {
5640 uint32_t Isr;
5641
5642 METHOD_TRACE("ips_isintr_morpheus", 2);
5643
5644 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5645
5646 if (Isr & IPS_BIT_I2O_OPQI)
5647 return (1);
5648 else
5649 return (0);
5650 }
5651
5652 /****************************************************************************/
5653 /* */
5654 /* Routine Name: ips_wait */
5655 /* */
5656 /* Routine Description: */
5657 /* */
5658 /* Wait for a command to complete */
5659 /* */
5660 /****************************************************************************/
5661 static int
5662 ips_wait(ips_ha_t * ha, int time, int intr)
5663 {
5664 int ret;
5665 int done;
5666
5667 METHOD_TRACE("ips_wait", 1);
5668
5669 ret = IPS_FAILURE;
5670 done = FALSE;
5671
5672 time *= IPS_ONE_SEC; /* convert seconds */
5673
5674 while ((time > 0) && (!done)) {
5675 if (intr == IPS_INTR_ON) {
5676 if (ha->waitflag == FALSE) {
5677 ret = IPS_SUCCESS;
5678 done = TRUE;
5679 break;
5680 }
5681 } else if (intr == IPS_INTR_IORL) {
5682 if (ha->waitflag == FALSE) {
5683 /*
5684 * controller generated an interrupt to
5685 * acknowledge completion of the command
5686 * and ips_intr() has serviced the interrupt.
5687 */
5688 ret = IPS_SUCCESS;
5689 done = TRUE;
5690 break;
5691 }
5692
5693 /*
5694 * NOTE: we already have the io_request_lock so
5695 * even if we get an interrupt it won't get serviced
5696 * until after we finish.
5697 */
5698
5699 (*ha->func.intr) (ha);
5700 }
5701
5702 /* This looks like a very evil loop, but it only does this during start-up */
5703 udelay(1000);
5704 time--;
5705 }
5706
5707 return (ret);
5708 }
5709
5710 /****************************************************************************/
5711 /* */
5712 /* Routine Name: ips_write_driver_status */
5713 /* */
5714 /* Routine Description: */
5715 /* */
5716 /* Write OS/Driver version to Page 5 of the nvram on the controller */
5717 /* */
5718 /****************************************************************************/
5719 static int
5720 ips_write_driver_status(ips_ha_t * ha, int intr)
5721 {
5722 METHOD_TRACE("ips_write_driver_status", 1);
5723
5724 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5725 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5726 "unable to read NVRAM page 5.\n");
5727
5728 return (0);
5729 }
5730
5731 /* check to make sure the page has a valid */
5732 /* signature */
5733 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5734 DEBUG_VAR(1,
5735 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5736 ips_name, ha->host_num, ha->nvram->signature);
5737 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5738 }
5739
5740 DEBUG_VAR(2,
5741 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5742 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5743 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5744 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5745 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5746 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5747 ha->nvram->bios_low[3]);
5748
5749 ips_get_bios_version(ha, intr);
5750
5751 /* change values (as needed) */
5752 ha->nvram->operating_system = IPS_OS_LINUX;
5753 ha->nvram->adapter_type = ha->ad_type;
5754 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5755 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5756 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5757 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5758
5759 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */
5760
5761 /* now update the page */
5762 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5763 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5764 "unable to write NVRAM page 5.\n");
5765
5766 return (0);
5767 }
5768
5769 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
5770 ha->slot_num = ha->nvram->adapter_slot;
5771
5772 return (1);
5773 }
5774
5775 /****************************************************************************/
5776 /* */
5777 /* Routine Name: ips_read_adapter_status */
5778 /* */
5779 /* Routine Description: */
5780 /* */
5781 /* Do an Inquiry command to the adapter */
5782 /* */
5783 /****************************************************************************/
5784 static int
5785 ips_read_adapter_status(ips_ha_t * ha, int intr)
5786 {
5787 ips_scb_t *scb;
5788 int ret;
5789
5790 METHOD_TRACE("ips_read_adapter_status", 1);
5791
5792 scb = &ha->scbs[ha->max_cmds - 1];
5793
5794 ips_init_scb(ha, scb);
5795
5796 scb->timeout = ips_cmd_timeout;
5797 scb->cdb[0] = IPS_CMD_ENQUIRY;
5798
5799 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5800 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5801 scb->cmd.basic_io.sg_count = 0;
5802 scb->cmd.basic_io.lba = 0;
5803 scb->cmd.basic_io.sector_count = 0;
5804 scb->cmd.basic_io.log_drv = 0;
5805 scb->data_len = sizeof (*ha->enq);
5806 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5807
5808 /* send command */
5809 if (((ret =
5810 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5811 || (ret == IPS_SUCCESS_IMM)
5812 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5813 return (0);
5814
5815 return (1);
5816 }
5817
5818 /****************************************************************************/
5819 /* */
5820 /* Routine Name: ips_read_subsystem_parameters */
5821 /* */
5822 /* Routine Description: */
5823 /* */
5824 /* Read subsystem parameters from the adapter */
5825 /* */
5826 /****************************************************************************/
5827 static int
5828 ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5829 {
5830 ips_scb_t *scb;
5831 int ret;
5832
5833 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5834
5835 scb = &ha->scbs[ha->max_cmds - 1];
5836
5837 ips_init_scb(ha, scb);
5838
5839 scb->timeout = ips_cmd_timeout;
5840 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5841
5842 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5843 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5844 scb->cmd.basic_io.sg_count = 0;
5845 scb->cmd.basic_io.lba = 0;
5846 scb->cmd.basic_io.sector_count = 0;
5847 scb->cmd.basic_io.log_drv = 0;
5848 scb->data_len = sizeof (*ha->subsys);
5849 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5850
5851 /* send command */
5852 if (((ret =
5853 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5854 || (ret == IPS_SUCCESS_IMM)
5855 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5856 return (0);
5857
5858 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5859 return (1);
5860 }
5861
5862 /****************************************************************************/
5863 /* */
5864 /* Routine Name: ips_read_config */
5865 /* */
5866 /* Routine Description: */
5867 /* */
5868 /* Read the configuration on the adapter */
5869 /* */
5870 /****************************************************************************/
5871 static int
5872 ips_read_config(ips_ha_t * ha, int intr)
5873 {
5874 ips_scb_t *scb;
5875 int i;
5876 int ret;
5877
5878 METHOD_TRACE("ips_read_config", 1);
5879
5880 /* set defaults for initiator IDs */
5881 for (i = 0; i < 4; i++)
5882 ha->conf->init_id[i] = 7;
5883
5884 scb = &ha->scbs[ha->max_cmds - 1];
5885
5886 ips_init_scb(ha, scb);
5887
5888 scb->timeout = ips_cmd_timeout;
5889 scb->cdb[0] = IPS_CMD_READ_CONF;
5890
5891 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5892 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5893 scb->data_len = sizeof (*ha->conf);
5894 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5895
5896 /* send command */
5897 if (((ret =
5898 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5899 || (ret == IPS_SUCCESS_IMM)
5900 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5901
5902 memset(ha->conf, 0, sizeof (IPS_CONF));
5903
5904 /* reset initiator IDs */
5905 for (i = 0; i < 4; i++)
5906 ha->conf->init_id[i] = 7;
5907
5908 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
5909 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5910 IPS_CMD_CMPLT_WERROR)
5911 return (1);
5912
5913 return (0);
5914 }
5915
5916 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5917 return (1);
5918 }
5919
5920 /****************************************************************************/
5921 /* */
5922 /* Routine Name: ips_readwrite_page5 */
5923 /* */
5924 /* Routine Description: */
5925 /* */
5926 /* Read nvram page 5 from the adapter */
5927 /* */
5928 /****************************************************************************/
5929 static int
5930 ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5931 {
5932 ips_scb_t *scb;
5933 int ret;
5934
5935 METHOD_TRACE("ips_readwrite_page5", 1);
5936
5937 scb = &ha->scbs[ha->max_cmds - 1];
5938
5939 ips_init_scb(ha, scb);
5940
5941 scb->timeout = ips_cmd_timeout;
5942 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5943
5944 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5945 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5946 scb->cmd.nvram.page = 5;
5947 scb->cmd.nvram.write = write;
5948 scb->cmd.nvram.reserved = 0;
5949 scb->cmd.nvram.reserved2 = 0;
5950 scb->data_len = sizeof (*ha->nvram);
5951 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5952 if (write)
5953 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
5954
5955 /* issue the command */
5956 if (((ret =
5957 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5958 || (ret == IPS_SUCCESS_IMM)
5959 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5960
5961 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
5962
5963 return (0);
5964 }
5965 if (!write)
5966 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
5967 return (1);
5968 }
5969
5970 /****************************************************************************/
5971 /* */
5972 /* Routine Name: ips_clear_adapter */
5973 /* */
5974 /* Routine Description: */
5975 /* */
5976 /* Clear the stripe lock tables */
5977 /* */
5978 /****************************************************************************/
5979 static int
5980 ips_clear_adapter(ips_ha_t * ha, int intr)
5981 {
5982 ips_scb_t *scb;
5983 int ret;
5984
5985 METHOD_TRACE("ips_clear_adapter", 1);
5986
5987 scb = &ha->scbs[ha->max_cmds - 1];
5988
5989 ips_init_scb(ha, scb);
5990
5991 scb->timeout = ips_reset_timeout;
5992 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
5993
5994 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
5995 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
5996 scb->cmd.config_sync.channel = 0;
5997 scb->cmd.config_sync.source_target = IPS_POCL;
5998 scb->cmd.config_sync.reserved = 0;
5999 scb->cmd.config_sync.reserved2 = 0;
6000 scb->cmd.config_sync.reserved3 = 0;
6001
6002 /* issue command */
6003 if (((ret =
6004 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
6005 || (ret == IPS_SUCCESS_IMM)
6006 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
6007 return (0);
6008
6009 /* send unlock stripe command */
6010 ips_init_scb(ha, scb);
6011
6012 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
6013 scb->timeout = ips_reset_timeout;
6014
6015 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
6016 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
6017 scb->cmd.unlock_stripe.log_drv = 0;
6018 scb->cmd.unlock_stripe.control = IPS_CSL;
6019 scb->cmd.unlock_stripe.reserved = 0;
6020 scb->cmd.unlock_stripe.reserved2 = 0;
6021 scb->cmd.unlock_stripe.reserved3 = 0;
6022
6023 /* issue command */
6024 if (((ret =
6025 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6026 || (ret == IPS_SUCCESS_IMM)
6027 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
6028 return (0);
6029
6030 return (1);
6031 }
6032
6033 /****************************************************************************/
6034 /* */
6035 /* Routine Name: ips_ffdc_reset */
6036 /* */
6037 /* Routine Description: */
6038 /* */
6039 /* FFDC: write reset info */
6040 /* */
6041 /****************************************************************************/
6042 static void
6043 ips_ffdc_reset(ips_ha_t * ha, int intr)
6044 {
6045 ips_scb_t *scb;
6046
6047 METHOD_TRACE("ips_ffdc_reset", 1);
6048
6049 scb = &ha->scbs[ha->max_cmds - 1];
6050
6051 ips_init_scb(ha, scb);
6052
6053 scb->timeout = ips_cmd_timeout;
6054 scb->cdb[0] = IPS_CMD_FFDC;
6055 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6056 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6057 scb->cmd.ffdc.reset_count = ha->reset_count;
6058 scb->cmd.ffdc.reset_type = 0x80;
6059
6060 /* convert time to what the card wants */
6061 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6062
6063 /* issue command */
6064 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
6065 }
6066
6067 /****************************************************************************/
6068 /* */
6069 /* Routine Name: ips_ffdc_time */
6070 /* */
6071 /* Routine Description: */
6072 /* */
6073 /* FFDC: write time info */
6074 /* */
6075 /****************************************************************************/
6076 static void
6077 ips_ffdc_time(ips_ha_t * ha)
6078 {
6079 ips_scb_t *scb;
6080
6081 METHOD_TRACE("ips_ffdc_time", 1);
6082
6083 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
6084
6085 scb = &ha->scbs[ha->max_cmds - 1];
6086
6087 ips_init_scb(ha, scb);
6088
6089 scb->timeout = ips_cmd_timeout;
6090 scb->cdb[0] = IPS_CMD_FFDC;
6091 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6092 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6093 scb->cmd.ffdc.reset_count = 0;
6094 scb->cmd.ffdc.reset_type = 0;
6095
6096 /* convert time to what the card wants */
6097 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6098
6099 /* issue command */
6100 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
6101 }
6102
6103 /****************************************************************************/
6104 /* */
6105 /* Routine Name: ips_fix_ffdc_time */
6106 /* */
6107 /* Routine Description: */
6108 /* Adjust time_t to what the card wants */
6109 /* */
6110 /****************************************************************************/
6111 static void
6112 ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time)
6113 {
6114 long days;
6115 long rem;
6116 int i;
6117 int year;
6118 int yleap;
6119 int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR };
6120 int month_lengths[12][2] = { {31, 31},
6121 {28, 29},
6122 {31, 31},
6123 {30, 30},
6124 {31, 31},
6125 {30, 30},
6126 {31, 31},
6127 {31, 31},
6128 {30, 30},
6129 {31, 31},
6130 {30, 30},
6131 {31, 31}
6132 };
6133
6134 METHOD_TRACE("ips_fix_ffdc_time", 1);
6135
6136 days = current_time / IPS_SECS_DAY;
6137 rem = current_time % IPS_SECS_DAY;
6138
6139 scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR);
6140 rem = rem % IPS_SECS_HOUR;
6141 scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN);
6142 scb->cmd.ffdc.second = (rem % IPS_SECS_MIN);
6143
6144 year = IPS_EPOCH_YEAR;
6145 while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) {
6146 int newy;
6147
6148 newy = year + (days / IPS_DAYS_NORMAL_YEAR);
6149 if (days < 0)
6150 --newy;
6151 days -= (newy - year) * IPS_DAYS_NORMAL_YEAR +
6152 IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) -
6153 IPS_NUM_LEAP_YEARS_THROUGH(year - 1);
6154 year = newy;
6155 }
6156
6157 scb->cmd.ffdc.yearH = year / 100;
6158 scb->cmd.ffdc.yearL = year % 100;
6159
6160 for (i = 0; days >= month_lengths[i][yleap]; ++i)
6161 days -= month_lengths[i][yleap];
6162
6163 scb->cmd.ffdc.month = i + 1;
6164 scb->cmd.ffdc.day = days + 1;
6165 }
6166
6167 /****************************************************************************
6168 * BIOS Flash Routines *
6169 ****************************************************************************/
6170
6171 /****************************************************************************/
6172 /* */
6173 /* Routine Name: ips_erase_bios */
6174 /* */
6175 /* Routine Description: */
6176 /* Erase the BIOS on the adapter */
6177 /* */
6178 /****************************************************************************/
6179 static int
6180 ips_erase_bios(ips_ha_t * ha)
6181 {
6182 int timeout;
6183 uint8_t status = 0;
6184
6185 METHOD_TRACE("ips_erase_bios", 1);
6186
6187 status = 0;
6188
6189 /* Clear the status register */
6190 outl(0, ha->io_addr + IPS_REG_FLAP);
6191 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6192 udelay(25); /* 25 us */
6193
6194 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6195 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6196 udelay(25); /* 25 us */
6197
6198 /* Erase Setup */
6199 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6200 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6201 udelay(25); /* 25 us */
6202
6203 /* Erase Confirm */
6204 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6205 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6206 udelay(25); /* 25 us */
6207
6208 /* Erase Status */
6209 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6210 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6211 udelay(25); /* 25 us */
6212
6213 timeout = 80000; /* 80 seconds */
6214
6215 while (timeout > 0) {
6216 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6217 outl(0, ha->io_addr + IPS_REG_FLAP);
6218 udelay(25); /* 25 us */
6219 }
6220
6221 status = inb(ha->io_addr + IPS_REG_FLDP);
6222
6223 if (status & 0x80)
6224 break;
6225
6226 MDELAY(1);
6227 timeout--;
6228 }
6229
6230 /* check for timeout */
6231 if (timeout <= 0) {
6232 /* timeout */
6233
6234 /* try to suspend the erase */
6235 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6236 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6237 udelay(25); /* 25 us */
6238
6239 /* wait for 10 seconds */
6240 timeout = 10000;
6241 while (timeout > 0) {
6242 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6243 outl(0, ha->io_addr + IPS_REG_FLAP);
6244 udelay(25); /* 25 us */
6245 }
6246
6247 status = inb(ha->io_addr + IPS_REG_FLDP);
6248
6249 if (status & 0xC0)
6250 break;
6251
6252 MDELAY(1);
6253 timeout--;
6254 }
6255
6256 return (1);
6257 }
6258
6259 /* check for valid VPP */
6260 if (status & 0x08)
6261 /* VPP failure */
6262 return (1);
6263
6264 /* check for successful flash */
6265 if (status & 0x30)
6266 /* sequence error */
6267 return (1);
6268
6269 /* Otherwise, we were successful */
6270 /* clear status */
6271 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6272 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6273 udelay(25); /* 25 us */
6274
6275 /* enable reads */
6276 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6277 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6278 udelay(25); /* 25 us */
6279
6280 return (0);
6281 }
6282
6283 /****************************************************************************/
6284 /* */
6285 /* Routine Name: ips_erase_bios_memio */
6286 /* */
6287 /* Routine Description: */
6288 /* Erase the BIOS on the adapter */
6289 /* */
6290 /****************************************************************************/
6291 static int
6292 ips_erase_bios_memio(ips_ha_t * ha)
6293 {
6294 int timeout;
6295 uint8_t status;
6296
6297 METHOD_TRACE("ips_erase_bios_memio", 1);
6298
6299 status = 0;
6300
6301 /* Clear the status register */
6302 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6303 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6304 udelay(25); /* 25 us */
6305
6306 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6307 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6308 udelay(25); /* 25 us */
6309
6310 /* Erase Setup */
6311 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6312 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6313 udelay(25); /* 25 us */
6314
6315 /* Erase Confirm */
6316 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6317 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6318 udelay(25); /* 25 us */
6319
6320 /* Erase Status */
6321 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6322 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6323 udelay(25); /* 25 us */
6324
6325 timeout = 80000; /* 80 seconds */
6326
6327 while (timeout > 0) {
6328 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6329 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6330 udelay(25); /* 25 us */
6331 }
6332
6333 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6334
6335 if (status & 0x80)
6336 break;
6337
6338 MDELAY(1);
6339 timeout--;
6340 }
6341
6342 /* check for timeout */
6343 if (timeout <= 0) {
6344 /* timeout */
6345
6346 /* try to suspend the erase */
6347 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6348 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6349 udelay(25); /* 25 us */
6350
6351 /* wait for 10 seconds */
6352 timeout = 10000;
6353 while (timeout > 0) {
6354 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6355 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6356 udelay(25); /* 25 us */
6357 }
6358
6359 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6360
6361 if (status & 0xC0)
6362 break;
6363
6364 MDELAY(1);
6365 timeout--;
6366 }
6367
6368 return (1);
6369 }
6370
6371 /* check for valid VPP */
6372 if (status & 0x08)
6373 /* VPP failure */
6374 return (1);
6375
6376 /* check for successful flash */
6377 if (status & 0x30)
6378 /* sequence error */
6379 return (1);
6380
6381 /* Otherwise, we were successful */
6382 /* clear status */
6383 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6384 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6385 udelay(25); /* 25 us */
6386
6387 /* enable reads */
6388 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6389 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6390 udelay(25); /* 25 us */
6391
6392 return (0);
6393 }
6394
6395 /****************************************************************************/
6396 /* */
6397 /* Routine Name: ips_program_bios */
6398 /* */
6399 /* Routine Description: */
6400 /* Program the BIOS on the adapter */
6401 /* */
6402 /****************************************************************************/
6403 static int
6404 ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6405 uint32_t offset)
6406 {
6407 int i;
6408 int timeout;
6409 uint8_t status = 0;
6410
6411 METHOD_TRACE("ips_program_bios", 1);
6412
6413 status = 0;
6414
6415 for (i = 0; i < buffersize; i++) {
6416 /* write a byte */
6417 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6418 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6419 udelay(25); /* 25 us */
6420
6421 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6422 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6423 udelay(25); /* 25 us */
6424
6425 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6426 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6427 udelay(25); /* 25 us */
6428
6429 /* wait up to one second */
6430 timeout = 1000;
6431 while (timeout > 0) {
6432 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6433 outl(0, ha->io_addr + IPS_REG_FLAP);
6434 udelay(25); /* 25 us */
6435 }
6436
6437 status = inb(ha->io_addr + IPS_REG_FLDP);
6438
6439 if (status & 0x80)
6440 break;
6441
6442 MDELAY(1);
6443 timeout--;
6444 }
6445
6446 if (timeout == 0) {
6447 /* timeout error */
6448 outl(0, ha->io_addr + IPS_REG_FLAP);
6449 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6450 udelay(25); /* 25 us */
6451
6452 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6453 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6454 udelay(25); /* 25 us */
6455
6456 return (1);
6457 }
6458
6459 /* check the status */
6460 if (status & 0x18) {
6461 /* programming error */
6462 outl(0, ha->io_addr + IPS_REG_FLAP);
6463 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6464 udelay(25); /* 25 us */
6465
6466 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6467 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6468 udelay(25); /* 25 us */
6469
6470 return (1);
6471 }
6472 } /* end for */
6473
6474 /* Enable reading */
6475 outl(0, ha->io_addr + IPS_REG_FLAP);
6476 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6477 udelay(25); /* 25 us */
6478
6479 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6480 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6481 udelay(25); /* 25 us */
6482
6483 return (0);
6484 }
6485
6486 /****************************************************************************/
6487 /* */
6488 /* Routine Name: ips_program_bios_memio */
6489 /* */
6490 /* Routine Description: */
6491 /* Program the BIOS on the adapter */
6492 /* */
6493 /****************************************************************************/
6494 static int
6495 ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6496 uint32_t offset)
6497 {
6498 int i;
6499 int timeout;
6500 uint8_t status = 0;
6501
6502 METHOD_TRACE("ips_program_bios_memio", 1);
6503
6504 status = 0;
6505
6506 for (i = 0; i < buffersize; i++) {
6507 /* write a byte */
6508 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6509 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6510 udelay(25); /* 25 us */
6511
6512 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6513 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6514 udelay(25); /* 25 us */
6515
6516 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6517 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6518 udelay(25); /* 25 us */
6519
6520 /* wait up to one second */
6521 timeout = 1000;
6522 while (timeout > 0) {
6523 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6524 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6525 udelay(25); /* 25 us */
6526 }
6527
6528 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6529
6530 if (status & 0x80)
6531 break;
6532
6533 MDELAY(1);
6534 timeout--;
6535 }
6536
6537 if (timeout == 0) {
6538 /* timeout error */
6539 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6540 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6541 udelay(25); /* 25 us */
6542
6543 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6544 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6545 udelay(25); /* 25 us */
6546
6547 return (1);
6548 }
6549
6550 /* check the status */
6551 if (status & 0x18) {
6552 /* programming error */
6553 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6554 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6555 udelay(25); /* 25 us */
6556
6557 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6558 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6559 udelay(25); /* 25 us */
6560
6561 return (1);
6562 }
6563 } /* end for */
6564
6565 /* Enable reading */
6566 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6567 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6568 udelay(25); /* 25 us */
6569
6570 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6571 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6572 udelay(25); /* 25 us */
6573
6574 return (0);
6575 }
6576
6577 /****************************************************************************/
6578 /* */
6579 /* Routine Name: ips_verify_bios */
6580 /* */
6581 /* Routine Description: */
6582 /* Verify the BIOS on the adapter */
6583 /* */
6584 /****************************************************************************/
6585 static int
6586 ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6587 uint32_t offset)
6588 {
6589 uint8_t checksum;
6590 int i;
6591
6592 METHOD_TRACE("ips_verify_bios", 1);
6593
6594 /* test 1st byte */
6595 outl(0, ha->io_addr + IPS_REG_FLAP);
6596 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6597 udelay(25); /* 25 us */
6598
6599 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6600 return (1);
6601
6602 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
6603 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6604 udelay(25); /* 25 us */
6605 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6606 return (1);
6607
6608 checksum = 0xff;
6609 for (i = 2; i < buffersize; i++) {
6610
6611 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6612 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6613 udelay(25); /* 25 us */
6614
6615 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6616 }
6617
6618 if (checksum != 0)
6619 /* failure */
6620 return (1);
6621 else
6622 /* success */
6623 return (0);
6624 }
6625
6626 /****************************************************************************/
6627 /* */
6628 /* Routine Name: ips_verify_bios_memio */
6629 /* */
6630 /* Routine Description: */
6631 /* Verify the BIOS on the adapter */
6632 /* */
6633 /****************************************************************************/
6634 static int
6635 ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6636 uint32_t offset)
6637 {
6638 uint8_t checksum;
6639 int i;
6640
6641 METHOD_TRACE("ips_verify_bios_memio", 1);
6642
6643 /* test 1st byte */
6644 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6645 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6646 udelay(25); /* 25 us */
6647
6648 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6649 return (1);
6650
6651 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6652 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6653 udelay(25); /* 25 us */
6654 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6655 return (1);
6656
6657 checksum = 0xff;
6658 for (i = 2; i < buffersize; i++) {
6659
6660 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6661 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6662 udelay(25); /* 25 us */
6663
6664 checksum =
6665 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6666 }
6667
6668 if (checksum != 0)
6669 /* failure */
6670 return (1);
6671 else
6672 /* success */
6673 return (0);
6674 }
6675
6676 /****************************************************************************/
6677 /* */
6678 /* Routine Name: ips_abort_init */
6679 /* */
6680 /* Routine Description: */
6681 /* cleanup routine for a failed adapter initialization */
6682 /****************************************************************************/
6683 static int
6684 ips_abort_init(ips_ha_t * ha, int index)
6685 {
6686 ha->active = 0;
6687 ips_free(ha);
6688 ips_ha[index] = NULL;
6689 ips_sh[index] = NULL;
6690 return -1;
6691 }
6692
6693 /****************************************************************************/
6694 /* */
6695 /* Routine Name: ips_shift_controllers */
6696 /* */
6697 /* Routine Description: */
6698 /* helper function for ordering adapters */
6699 /****************************************************************************/
6700 static void
6701 ips_shift_controllers(int lowindex, int highindex)
6702 {
6703 ips_ha_t *ha_sav = ips_ha[highindex];
6704 struct Scsi_Host *sh_sav = ips_sh[highindex];
6705 int i;
6706
6707 for (i = highindex; i > lowindex; i--) {
6708 ips_ha[i] = ips_ha[i - 1];
6709 ips_sh[i] = ips_sh[i - 1];
6710 ips_ha[i]->host_num = i;
6711 }
6712 ha_sav->host_num = lowindex;
6713 ips_ha[lowindex] = ha_sav;
6714 ips_sh[lowindex] = sh_sav;
6715 }
6716
6717 /****************************************************************************/
6718 /* */
6719 /* Routine Name: ips_order_controllers */
6720 /* */
6721 /* Routine Description: */
6722 /* place controllers is the "proper" boot order */
6723 /****************************************************************************/
6724 static void
6725 ips_order_controllers(void)
6726 {
6727 int i, j, tmp, position = 0;
6728 IPS_NVRAM_P5 *nvram;
6729 if (!ips_ha[0])
6730 return;
6731 nvram = ips_ha[0]->nvram;
6732
6733 if (nvram->adapter_order[0]) {
6734 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6735 for (j = position; j < ips_num_controllers; j++) {
6736 switch (ips_ha[j]->ad_type) {
6737 case IPS_ADTYPE_SERVERAID6M:
6738 case IPS_ADTYPE_SERVERAID7M:
6739 if (nvram->adapter_order[i] == 'M') {
6740 ips_shift_controllers(position,
6741 j);
6742 position++;
6743 }
6744 break;
6745 case IPS_ADTYPE_SERVERAID4L:
6746 case IPS_ADTYPE_SERVERAID4M:
6747 case IPS_ADTYPE_SERVERAID4MX:
6748 case IPS_ADTYPE_SERVERAID4LX:
6749 if (nvram->adapter_order[i] == 'N') {
6750 ips_shift_controllers(position,
6751 j);
6752 position++;
6753 }
6754 break;
6755 case IPS_ADTYPE_SERVERAID6I:
6756 case IPS_ADTYPE_SERVERAID5I2:
6757 case IPS_ADTYPE_SERVERAID5I1:
6758 case IPS_ADTYPE_SERVERAID7k:
6759 if (nvram->adapter_order[i] == 'S') {
6760 ips_shift_controllers(position,
6761 j);
6762 position++;
6763 }
6764 break;
6765 case IPS_ADTYPE_SERVERAID:
6766 case IPS_ADTYPE_SERVERAID2:
6767 case IPS_ADTYPE_NAVAJO:
6768 case IPS_ADTYPE_KIOWA:
6769 case IPS_ADTYPE_SERVERAID3L:
6770 case IPS_ADTYPE_SERVERAID3:
6771 case IPS_ADTYPE_SERVERAID4H:
6772 if (nvram->adapter_order[i] == 'A') {
6773 ips_shift_controllers(position,
6774 j);
6775 position++;
6776 }
6777 break;
6778 default:
6779 break;
6780 }
6781 }
6782 }
6783 /* if adapter_order[0], then ordering is complete */
6784 return;
6785 }
6786 /* old bios, use older ordering */
6787 tmp = 0;
6788 for (i = position; i < ips_num_controllers; i++) {
6789 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6790 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6791 ips_shift_controllers(position, i);
6792 position++;
6793 tmp = 1;
6794 }
6795 }
6796 /* if there were no 5I cards, then don't do any extra ordering */
6797 if (!tmp)
6798 return;
6799 for (i = position; i < ips_num_controllers; i++) {
6800 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6801 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6802 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6803 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6804 ips_shift_controllers(position, i);
6805 position++;
6806 }
6807 }
6808
6809 return;
6810 }
6811
6812 /****************************************************************************/
6813 /* */
6814 /* Routine Name: ips_register_scsi */
6815 /* */
6816 /* Routine Description: */
6817 /* perform any registration and setup with the scsi layer */
6818 /****************************************************************************/
6819 static int
6820 ips_register_scsi(int index)
6821 {
6822 struct Scsi_Host *sh;
6823 ips_ha_t *ha, *oldha = ips_ha[index];
6824 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
6825 if (!sh) {
6826 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
6827 "Unable to register controller with SCSI subsystem\n");
6828 return -1;
6829 }
6830 ha = IPS_HA(sh);
6831 memcpy(ha, oldha, sizeof (ips_ha_t));
6832 free_irq(oldha->pcidev->irq, oldha);
6833 /* Install the interrupt handler with the new ha */
6834 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
6835 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6836 "Unable to install interrupt handler\n");
6837 goto err_out_sh;
6838 }
6839
6840 kfree(oldha);
6841
6842 /* Store away needed values for later use */
6843 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
6844 sh->sg_tablesize = sh->hostt->sg_tablesize;
6845 sh->can_queue = sh->hostt->can_queue;
6846 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
6847 sh->unchecked_isa_dma = sh->hostt->unchecked_isa_dma;
6848 sh->use_clustering = sh->hostt->use_clustering;
6849 sh->max_sectors = 128;
6850
6851 sh->max_id = ha->ntargets;
6852 sh->max_lun = ha->nlun;
6853 sh->max_channel = ha->nbus - 1;
6854 sh->can_queue = ha->max_cmds - 1;
6855
6856 if (scsi_add_host(sh, &ha->pcidev->dev))
6857 goto err_out;
6858
6859 ips_sh[index] = sh;
6860 ips_ha[index] = ha;
6861
6862 scsi_scan_host(sh);
6863
6864 return 0;
6865
6866 err_out:
6867 free_irq(ha->pcidev->irq, ha);
6868 err_out_sh:
6869 scsi_host_put(sh);
6870 return -1;
6871 }
6872
6873 /*---------------------------------------------------------------------------*/
6874 /* Routine Name: ips_remove_device */
6875 /* */
6876 /* Routine Description: */
6877 /* Remove one Adapter ( Hot Plugging ) */
6878 /*---------------------------------------------------------------------------*/
6879 static void __devexit
6880 ips_remove_device(struct pci_dev *pci_dev)
6881 {
6882 struct Scsi_Host *sh = pci_get_drvdata(pci_dev);
6883
6884 pci_set_drvdata(pci_dev, NULL);
6885
6886 ips_release(sh);
6887
6888 pci_release_regions(pci_dev);
6889 pci_disable_device(pci_dev);
6890 }
6891
6892 /****************************************************************************/
6893 /* */
6894 /* Routine Name: ips_module_init */
6895 /* */
6896 /* Routine Description: */
6897 /* function called on module load */
6898 /****************************************************************************/
6899 static int __init
6900 ips_module_init(void)
6901 {
6902 if (pci_register_driver(&ips_pci_driver) < 0)
6903 return -ENODEV;
6904 ips_driver_template.module = THIS_MODULE;
6905 ips_order_controllers();
6906 if (!ips_detect(&ips_driver_template)) {
6907 pci_unregister_driver(&ips_pci_driver);
6908 return -ENODEV;
6909 }
6910 register_reboot_notifier(&ips_notifier);
6911 return 0;
6912 }
6913
6914 /****************************************************************************/
6915 /* */
6916 /* Routine Name: ips_module_exit */
6917 /* */
6918 /* Routine Description: */
6919 /* function called on module unload */
6920 /****************************************************************************/
6921 static void __exit
6922 ips_module_exit(void)
6923 {
6924 pci_unregister_driver(&ips_pci_driver);
6925 unregister_reboot_notifier(&ips_notifier);
6926 }
6927
6928 module_init(ips_module_init);
6929 module_exit(ips_module_exit);
6930
6931 /*---------------------------------------------------------------------------*/
6932 /* Routine Name: ips_insert_device */
6933 /* */
6934 /* Routine Description: */
6935 /* Add One Adapter ( Hot Plug ) */
6936 /* */
6937 /* Return Value: */
6938 /* 0 if Successful, else non-zero */
6939 /*---------------------------------------------------------------------------*/
6940 static int __devinit
6941 ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
6942 {
6943 int index = -1;
6944 int rc;
6945
6946 METHOD_TRACE("ips_insert_device", 1);
6947 rc = pci_enable_device(pci_dev);
6948 if (rc)
6949 return rc;
6950
6951 rc = pci_request_regions(pci_dev, "ips");
6952 if (rc)
6953 goto err_out;
6954
6955 rc = ips_init_phase1(pci_dev, &index);
6956 if (rc == SUCCESS)
6957 rc = ips_init_phase2(index);
6958
6959 if (ips_hotplug)
6960 if (ips_register_scsi(index)) {
6961 ips_free(ips_ha[index]);
6962 rc = -1;
6963 }
6964
6965 if (rc == SUCCESS)
6966 ips_num_controllers++;
6967
6968 ips_next_controller = ips_num_controllers;
6969
6970 if (rc < 0) {
6971 rc = -ENODEV;
6972 goto err_out_regions;
6973 }
6974
6975 pci_set_drvdata(pci_dev, ips_sh[index]);
6976 return 0;
6977
6978 err_out_regions:
6979 pci_release_regions(pci_dev);
6980 err_out:
6981 pci_disable_device(pci_dev);
6982 return rc;
6983 }
6984
6985 /*---------------------------------------------------------------------------*/
6986 /* Routine Name: ips_init_phase1 */
6987 /* */
6988 /* Routine Description: */
6989 /* Adapter Initialization */
6990 /* */
6991 /* Return Value: */
6992 /* 0 if Successful, else non-zero */
6993 /*---------------------------------------------------------------------------*/
6994 static int
6995 ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
6996 {
6997 ips_ha_t *ha;
6998 uint32_t io_addr;
6999 uint32_t mem_addr;
7000 uint32_t io_len;
7001 uint32_t mem_len;
7002 uint8_t bus;
7003 uint8_t func;
7004 int j;
7005 int index;
7006 dma_addr_t dma_address;
7007 char __iomem *ioremap_ptr;
7008 char __iomem *mem_ptr;
7009 uint32_t IsDead;
7010
7011 METHOD_TRACE("ips_init_phase1", 1);
7012 index = IPS_MAX_ADAPTERS;
7013 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
7014 if (ips_ha[j] == NULL) {
7015 index = j;
7016 break;
7017 }
7018 }
7019
7020 if (index >= IPS_MAX_ADAPTERS)
7021 return -1;
7022
7023 /* stuff that we get in dev */
7024 bus = pci_dev->bus->number;
7025 func = pci_dev->devfn;
7026
7027 /* Init MEM/IO addresses to 0 */
7028 mem_addr = 0;
7029 io_addr = 0;
7030 mem_len = 0;
7031 io_len = 0;
7032
7033 for (j = 0; j < 2; j++) {
7034 if (!pci_resource_start(pci_dev, j))
7035 break;
7036
7037 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
7038 io_addr = pci_resource_start(pci_dev, j);
7039 io_len = pci_resource_len(pci_dev, j);
7040 } else {
7041 mem_addr = pci_resource_start(pci_dev, j);
7042 mem_len = pci_resource_len(pci_dev, j);
7043 }
7044 }
7045
7046 /* setup memory mapped area (if applicable) */
7047 if (mem_addr) {
7048 uint32_t base;
7049 uint32_t offs;
7050
7051 base = mem_addr & PAGE_MASK;
7052 offs = mem_addr - base;
7053 ioremap_ptr = ioremap(base, PAGE_SIZE);
7054 if (!ioremap_ptr)
7055 return -1;
7056 mem_ptr = ioremap_ptr + offs;
7057 } else {
7058 ioremap_ptr = NULL;
7059 mem_ptr = NULL;
7060 }
7061
7062 /* found a controller */
7063 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL);
7064 if (ha == NULL) {
7065 IPS_PRINTK(KERN_WARNING, pci_dev,
7066 "Unable to allocate temporary ha struct\n");
7067 return -1;
7068 }
7069
7070 ips_sh[index] = NULL;
7071 ips_ha[index] = ha;
7072 ha->active = 1;
7073
7074 /* Store info in HA structure */
7075 ha->io_addr = io_addr;
7076 ha->io_len = io_len;
7077 ha->mem_addr = mem_addr;
7078 ha->mem_len = mem_len;
7079 ha->mem_ptr = mem_ptr;
7080 ha->ioremap_ptr = ioremap_ptr;
7081 ha->host_num = (uint32_t) index;
7082 ha->slot_num = PCI_SLOT(pci_dev->devfn);
7083 ha->pcidev = pci_dev;
7084
7085 /*
7086 * Set the pci_dev's dma_mask. Not all adapters support 64bit
7087 * addressing so don't enable it if the adapter can't support
7088 * it! Also, don't use 64bit addressing if dma addresses
7089 * are guaranteed to be < 4G.
7090 */
7091 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) &&
7092 !pci_set_dma_mask(ha->pcidev, DMA_64BIT_MASK)) {
7093 (ha)->flags |= IPS_HA_ENH_SG;
7094 } else {
7095 if (pci_set_dma_mask(ha->pcidev, DMA_32BIT_MASK) != 0) {
7096 printk(KERN_WARNING "Unable to set DMA Mask\n");
7097 return ips_abort_init(ha, index);
7098 }
7099 }
7100 if(ips_cd_boot && !ips_FlashData){
7101 ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7,
7102 &ips_flashbusaddr);
7103 }
7104
7105 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ),
7106 &ha->enq_busaddr);
7107 if (!ha->enq) {
7108 IPS_PRINTK(KERN_WARNING, pci_dev,
7109 "Unable to allocate host inquiry structure\n");
7110 return ips_abort_init(ha, index);
7111 }
7112
7113 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) +
7114 sizeof (IPS_IO_CMD), &dma_address);
7115 if (!ha->adapt) {
7116 IPS_PRINTK(KERN_WARNING, pci_dev,
7117 "Unable to allocate host adapt & dummy structures\n");
7118 return ips_abort_init(ha, index);
7119 }
7120 ha->adapt->hw_status_start = dma_address;
7121 ha->dummy = (void *) (ha->adapt + 1);
7122
7123
7124
7125 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address);
7126 if (!ha->logical_drive_info) {
7127 IPS_PRINTK(KERN_WARNING, pci_dev,
7128 "Unable to allocate logical drive info structure\n");
7129 return ips_abort_init(ha, index);
7130 }
7131 ha->logical_drive_info_dma_addr = dma_address;
7132
7133
7134 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
7135
7136 if (!ha->conf) {
7137 IPS_PRINTK(KERN_WARNING, pci_dev,
7138 "Unable to allocate host conf structure\n");
7139 return ips_abort_init(ha, index);
7140 }
7141
7142 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
7143
7144 if (!ha->nvram) {
7145 IPS_PRINTK(KERN_WARNING, pci_dev,
7146 "Unable to allocate host NVRAM structure\n");
7147 return ips_abort_init(ha, index);
7148 }
7149
7150 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
7151
7152 if (!ha->subsys) {
7153 IPS_PRINTK(KERN_WARNING, pci_dev,
7154 "Unable to allocate host subsystem structure\n");
7155 return ips_abort_init(ha, index);
7156 }
7157
7158 /* the ioctl buffer is now used during adapter initialization, so its
7159 * successful allocation is now required */
7160 if (ips_ioctlsize < PAGE_SIZE)
7161 ips_ioctlsize = PAGE_SIZE;
7162
7163 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize,
7164 &ha->ioctl_busaddr);
7165 ha->ioctl_len = ips_ioctlsize;
7166 if (!ha->ioctl_data) {
7167 IPS_PRINTK(KERN_WARNING, pci_dev,
7168 "Unable to allocate IOCTL data\n");
7169 return ips_abort_init(ha, index);
7170 }
7171
7172 /*
7173 * Setup Functions
7174 */
7175 ips_setup_funclist(ha);
7176
7177 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7178 /* If Morpheus appears dead, reset it */
7179 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7180 if (IsDead == 0xDEADBEEF) {
7181 ips_reset_morpheus(ha);
7182 }
7183 }
7184
7185 /*
7186 * Initialize the card if it isn't already
7187 */
7188
7189 if (!(*ha->func.isinit) (ha)) {
7190 if (!(*ha->func.init) (ha)) {
7191 /*
7192 * Initialization failed
7193 */
7194 IPS_PRINTK(KERN_WARNING, pci_dev,
7195 "Unable to initialize controller\n");
7196 return ips_abort_init(ha, index);
7197 }
7198 }
7199
7200 *indexPtr = index;
7201 return SUCCESS;
7202 }
7203
7204 /*---------------------------------------------------------------------------*/
7205 /* Routine Name: ips_init_phase2 */
7206 /* */
7207 /* Routine Description: */
7208 /* Adapter Initialization Phase 2 */
7209 /* */
7210 /* Return Value: */
7211 /* 0 if Successful, else non-zero */
7212 /*---------------------------------------------------------------------------*/
7213 static int
7214 ips_init_phase2(int index)
7215 {
7216 ips_ha_t *ha;
7217
7218 ha = ips_ha[index];
7219
7220 METHOD_TRACE("ips_init_phase2", 1);
7221 if (!ha->active) {
7222 ips_ha[index] = NULL;
7223 return -1;
7224 }
7225
7226 /* Install the interrupt handler */
7227 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
7228 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7229 "Unable to install interrupt handler\n");
7230 return ips_abort_init(ha, index);
7231 }
7232
7233 /*
7234 * Allocate a temporary SCB for initialization
7235 */
7236 ha->max_cmds = 1;
7237 if (!ips_allocatescbs(ha)) {
7238 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7239 "Unable to allocate a CCB\n");
7240 free_irq(ha->pcidev->irq, ha);
7241 return ips_abort_init(ha, index);
7242 }
7243
7244 if (!ips_hainit(ha)) {
7245 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7246 "Unable to initialize controller\n");
7247 free_irq(ha->pcidev->irq, ha);
7248 return ips_abort_init(ha, index);
7249 }
7250 /* Free the temporary SCB */
7251 ips_deallocatescbs(ha, 1);
7252
7253 /* allocate CCBs */
7254 if (!ips_allocatescbs(ha)) {
7255 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7256 "Unable to allocate CCBs\n");
7257 free_irq(ha->pcidev->irq, ha);
7258 return ips_abort_init(ha, index);
7259 }
7260
7261 return SUCCESS;
7262 }
7263
7264 MODULE_LICENSE("GPL");
7265 MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7266 MODULE_VERSION(IPS_VER_STRING);
7267
7268
7269 /*
7270 * Overrides for Emacs so that we almost follow Linus's tabbing style.
7271 * Emacs will notice this stuff at the end of the file and automatically
7272 * adjust the settings for this buffer only. This must remain at the end
7273 * of the file.
7274 * ---------------------------------------------------------------------------
7275 * Local variables:
7276 * c-indent-level: 2
7277 * c-brace-imaginary-offset: 0
7278 * c-brace-offset: -2
7279 * c-argdecl-indent: 2
7280 * c-label-offset: -2
7281 * c-continued-statement-offset: 2
7282 * c-continued-brace-offset: 0
7283 * indent-tabs-mode: nil
7284 * tab-width: 8
7285 * End:
7286 */
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