]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/scsi/lpfc/lpfc_hw.h
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'efi-urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi into...
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / lpfc / lpfc_hw.h
1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2017 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Limited and/or its subsidiaries. *
6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
7 * EMULEX and SLI are trademarks of Emulex. *
8 * www.broadcom.com *
9 * *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
22
23 #define FDMI_DID 0xfffffaU
24 #define NameServer_DID 0xfffffcU
25 #define SCR_DID 0xfffffdU
26 #define Fabric_DID 0xfffffeU
27 #define Bcast_DID 0xffffffU
28 #define Mask_DID 0xffffffU
29 #define CT_DID_MASK 0xffff00U
30 #define Fabric_DID_MASK 0xfff000U
31 #define WELL_KNOWN_DID_MASK 0xfffff0U
32
33 #define PT2PT_LocalID 1
34 #define PT2PT_RemoteID 2
35
36 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
37 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
38 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */
39 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
40
41 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
42 0 */
43
44 #define FCELSSIZE 1024 /* maximum ELS transfer size */
45
46 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
47 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
48 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
49
50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
58 #define SLI2_IOCB_CMD_R3_ENTRIES 0
59 #define SLI2_IOCB_RSP_R3_ENTRIES 0
60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62
63 #define SLI2_IOCB_CMD_SIZE 32
64 #define SLI2_IOCB_RSP_SIZE 32
65 #define SLI3_IOCB_CMD_SIZE 128
66 #define SLI3_IOCB_RSP_SIZE 64
67
68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
70
71 /* vendor ID used in SCSI netlink calls */
72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73
74 #define FW_REV_STR_SIZE 32
75 /* Common Transport structures and definitions */
76
77 union CtRevisionId {
78 /* Structure is in Big Endian format */
79 struct {
80 uint32_t Revision:8;
81 uint32_t InId:24;
82 } bits;
83 uint32_t word;
84 };
85
86 union CtCommandResponse {
87 /* Structure is in Big Endian format */
88 struct {
89 uint32_t CmdRsp:16;
90 uint32_t Size:16;
91 } bits;
92 uint32_t word;
93 };
94
95 /* FC4 Feature bits for RFF_ID */
96 #define FC4_FEATURE_TARGET 0x1
97 #define FC4_FEATURE_INIT 0x2
98 #define FC4_FEATURE_NVME_DISC 0x4
99
100 struct lpfc_sli_ct_request {
101 /* Structure is in Big Endian format */
102 union CtRevisionId RevisionId;
103 uint8_t FsType;
104 uint8_t FsSubType;
105 uint8_t Options;
106 uint8_t Rsrvd1;
107 union CtCommandResponse CommandResponse;
108 uint8_t Rsrvd2;
109 uint8_t ReasonCode;
110 uint8_t Explanation;
111 uint8_t VendorUnique;
112 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */
113
114 union {
115 uint32_t PortID;
116 struct gid {
117 uint8_t PortType; /* for GID_PT requests */
118 uint8_t DomainScope;
119 uint8_t AreaScope;
120 uint8_t Fc4Type; /* for GID_FT requests */
121 } gid;
122 struct gid_ff {
123 uint8_t Flags;
124 uint8_t DomainScope;
125 uint8_t AreaScope;
126 uint8_t rsvd1;
127 uint8_t rsvd2;
128 uint8_t rsvd3;
129 uint8_t Fc4FBits;
130 uint8_t Fc4Type;
131 } gid_ff;
132 struct rft {
133 uint32_t PortId; /* For RFT_ID requests */
134
135 #ifdef __BIG_ENDIAN_BITFIELD
136 uint32_t rsvd0:16;
137 uint32_t rsvd1:7;
138 uint32_t fcpReg:1; /* Type 8 */
139 uint32_t rsvd2:2;
140 uint32_t ipReg:1; /* Type 5 */
141 uint32_t rsvd3:5;
142 #else /* __LITTLE_ENDIAN_BITFIELD */
143 uint32_t rsvd0:16;
144 uint32_t fcpReg:1; /* Type 8 */
145 uint32_t rsvd1:7;
146 uint32_t rsvd3:5;
147 uint32_t ipReg:1; /* Type 5 */
148 uint32_t rsvd2:2;
149 #endif
150
151 uint32_t rsvd[7];
152 } rft;
153 struct rnn {
154 uint32_t PortId; /* For RNN_ID requests */
155 uint8_t wwnn[8];
156 } rnn;
157 struct rsnn { /* For RSNN_ID requests */
158 uint8_t wwnn[8];
159 uint8_t len;
160 uint8_t symbname[255];
161 } rsnn;
162 struct da_id { /* For DA_ID requests */
163 uint32_t port_id;
164 } da_id;
165 struct rspn { /* For RSPN_ID requests */
166 uint32_t PortId;
167 uint8_t len;
168 uint8_t symbname[255];
169 } rspn;
170 struct gff {
171 uint32_t PortId;
172 } gff;
173 struct gff_acc {
174 uint8_t fbits[128];
175 } gff_acc;
176 struct gft {
177 uint32_t PortId;
178 } gft;
179 struct gft_acc {
180 uint32_t fc4_types[8];
181 } gft_acc;
182 #define FCP_TYPE_FEATURE_OFFSET 7
183 struct rff {
184 uint32_t PortId;
185 uint8_t reserved[2];
186 uint8_t fbits;
187 uint8_t type_code; /* type=8 for FCP */
188 } rff;
189 } un;
190 };
191
192 #define LPFC_MAX_CT_SIZE (60 * 4096)
193
194 #define SLI_CT_REVISION 1
195 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
196 sizeof(struct gid))
197 #define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
198 sizeof(struct gid_ff))
199 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
200 sizeof(struct gff))
201 #define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
202 sizeof(struct gft))
203 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
204 sizeof(struct rft))
205 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
206 sizeof(struct rff))
207 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
208 sizeof(struct rnn))
209 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
210 sizeof(struct rsnn))
211 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
212 sizeof(struct da_id))
213 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
214 sizeof(struct rspn))
215
216 /*
217 * FsType Definitions
218 */
219
220 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
221 #define SLI_CT_TIME_SERVICE 0xFB
222 #define SLI_CT_DIRECTORY_SERVICE 0xFC
223 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
224
225 /*
226 * Directory Service Subtypes
227 */
228
229 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
230
231 /*
232 * Response Codes
233 */
234
235 #define SLI_CT_RESPONSE_FS_RJT 0x8001
236 #define SLI_CT_RESPONSE_FS_ACC 0x8002
237
238 /*
239 * Reason Codes
240 */
241
242 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
243 #define SLI_CT_INVALID_COMMAND 0x01
244 #define SLI_CT_INVALID_VERSION 0x02
245 #define SLI_CT_LOGICAL_ERROR 0x03
246 #define SLI_CT_INVALID_IU_SIZE 0x04
247 #define SLI_CT_LOGICAL_BUSY 0x05
248 #define SLI_CT_PROTOCOL_ERROR 0x07
249 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
250 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
251 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
252 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
253 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
254 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
255 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
256 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
257 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
258 #define SLI_CT_VENDOR_UNIQUE 0xff
259
260 /*
261 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
262 */
263
264 #define SLI_CT_NO_PORT_ID 0x01
265 #define SLI_CT_NO_PORT_NAME 0x02
266 #define SLI_CT_NO_NODE_NAME 0x03
267 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
268 #define SLI_CT_NO_IP_ADDRESS 0x05
269 #define SLI_CT_NO_IPA 0x06
270 #define SLI_CT_NO_FC4_TYPES 0x07
271 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
272 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
273 #define SLI_CT_NO_PORT_TYPE 0x0A
274 #define SLI_CT_ACCESS_DENIED 0x10
275 #define SLI_CT_INVALID_PORT_ID 0x11
276 #define SLI_CT_DATABASE_EMPTY 0x12
277
278 /*
279 * Name Server Command Codes
280 */
281
282 #define SLI_CTNS_GA_NXT 0x0100
283 #define SLI_CTNS_GPN_ID 0x0112
284 #define SLI_CTNS_GNN_ID 0x0113
285 #define SLI_CTNS_GCS_ID 0x0114
286 #define SLI_CTNS_GFT_ID 0x0117
287 #define SLI_CTNS_GSPN_ID 0x0118
288 #define SLI_CTNS_GPT_ID 0x011A
289 #define SLI_CTNS_GFF_ID 0x011F
290 #define SLI_CTNS_GID_PN 0x0121
291 #define SLI_CTNS_GID_NN 0x0131
292 #define SLI_CTNS_GIP_NN 0x0135
293 #define SLI_CTNS_GIPA_NN 0x0136
294 #define SLI_CTNS_GSNN_NN 0x0139
295 #define SLI_CTNS_GNN_IP 0x0153
296 #define SLI_CTNS_GIPA_IP 0x0156
297 #define SLI_CTNS_GID_FT 0x0171
298 #define SLI_CTNS_GID_FF 0x01F1
299 #define SLI_CTNS_GID_PT 0x01A1
300 #define SLI_CTNS_RPN_ID 0x0212
301 #define SLI_CTNS_RNN_ID 0x0213
302 #define SLI_CTNS_RCS_ID 0x0214
303 #define SLI_CTNS_RFT_ID 0x0217
304 #define SLI_CTNS_RSPN_ID 0x0218
305 #define SLI_CTNS_RPT_ID 0x021A
306 #define SLI_CTNS_RFF_ID 0x021F
307 #define SLI_CTNS_RIP_NN 0x0235
308 #define SLI_CTNS_RIPA_NN 0x0236
309 #define SLI_CTNS_RSNN_NN 0x0239
310 #define SLI_CTNS_DA_ID 0x0300
311
312 /*
313 * Port Types
314 */
315
316 #define SLI_CTPT_N_PORT 0x01
317 #define SLI_CTPT_NL_PORT 0x02
318 #define SLI_CTPT_FNL_PORT 0x03
319 #define SLI_CTPT_IP 0x04
320 #define SLI_CTPT_FCP 0x08
321 #define SLI_CTPT_NVME 0x28
322 #define SLI_CTPT_NX_PORT 0x7F
323 #define SLI_CTPT_F_PORT 0x81
324 #define SLI_CTPT_FL_PORT 0x82
325 #define SLI_CTPT_E_PORT 0x84
326
327 #define SLI_CT_LAST_ENTRY 0x80000000
328
329 /* Fibre Channel Service Parameter definitions */
330
331 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
332 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
333 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
334 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
335
336 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
337 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
338 #define FC_PH3 0x20 /* FC-PH-3 version */
339
340 #define FF_FRAME_SIZE 2048
341
342 struct lpfc_name {
343 union {
344 struct {
345 #ifdef __BIG_ENDIAN_BITFIELD
346 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
347 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
348 8:11 of IEEE ext */
349 #else /* __LITTLE_ENDIAN_BITFIELD */
350 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
351 8:11 of IEEE ext */
352 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
353 #endif
354
355 #define NAME_IEEE 0x1 /* IEEE name - nameType */
356 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
357 #define NAME_FC_TYPE 0x3 /* FC native name type */
358 #define NAME_IP_TYPE 0x4 /* IP address */
359 #define NAME_CCITT_TYPE 0xC
360 #define NAME_CCITT_GR_TYPE 0xE
361 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
362 extended Lsb */
363 uint8_t IEEE[6]; /* FC IEEE address */
364 } s;
365 uint8_t wwn[8];
366 uint64_t name;
367 } u;
368 };
369
370 struct csp {
371 uint8_t fcphHigh; /* FC Word 0, byte 0 */
372 uint8_t fcphLow;
373 uint8_t bbCreditMsb;
374 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */
375
376 /*
377 * Word 1 Bit 31 in common service parameter is overloaded.
378 * Word 1 Bit 31 in FLOGI request is multiple NPort request
379 * Word 1 Bit 31 in FLOGI response is clean address bit
380 */
381 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
382 /*
383 * Word 1 Bit 30 in common service parameter is overloaded.
384 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
385 * Word 1 Bit 30 in PLOGI request is random offset
386 */
387 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
388 /*
389 * Word 1 Bit 29 in common service parameter is overloaded.
390 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
391 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
392 */
393 #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
394 #ifdef __BIG_ENDIAN_BITFIELD
395 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
396 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
397 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
398 uint16_t fPort:1; /* FC Word 1, bit 28 */
399 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
400 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
401 uint16_t multicast:1; /* FC Word 1, bit 25 */
402 uint16_t broadcast:1; /* FC Word 1, bit 24 */
403
404 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
405 uint16_t simplex:1; /* FC Word 1, bit 22 */
406 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
407 uint16_t dhd:1; /* FC Word 1, bit 18 */
408 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
409 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
410 #else /* __LITTLE_ENDIAN_BITFIELD */
411 uint16_t broadcast:1; /* FC Word 1, bit 24 */
412 uint16_t multicast:1; /* FC Word 1, bit 25 */
413 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
414 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
415 uint16_t fPort:1; /* FC Word 1, bit 28 */
416 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
417 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
418 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
419
420 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
421 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
422 uint16_t dhd:1; /* FC Word 1, bit 18 */
423 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
424 uint16_t simplex:1; /* FC Word 1, bit 22 */
425 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
426 #endif
427
428 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
429 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
430 union {
431 struct {
432 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
433
434 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
435 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
436
437 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
438 } nPort;
439 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
440 } w2;
441
442 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
443 };
444
445 struct class_parms {
446 #ifdef __BIG_ENDIAN_BITFIELD
447 uint8_t classValid:1; /* FC Word 0, bit 31 */
448 uint8_t intermix:1; /* FC Word 0, bit 30 */
449 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
450 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
451 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
452 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
453 #else /* __LITTLE_ENDIAN_BITFIELD */
454 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
455 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
456 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
457 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
458 uint8_t intermix:1; /* FC Word 0, bit 30 */
459 uint8_t classValid:1; /* FC Word 0, bit 31 */
460
461 #endif
462
463 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
464
465 #ifdef __BIG_ENDIAN_BITFIELD
466 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
467 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
468 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
469 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
470 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
471 #else /* __LITTLE_ENDIAN_BITFIELD */
472 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
473 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
474 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
475 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
476 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
477 #endif
478
479 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
480
481 #ifdef __BIG_ENDIAN_BITFIELD
482 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
483 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
484 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
485 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
486 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
487 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
488 #else /* __LITTLE_ENDIAN_BITFIELD */
489 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
490 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
491 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
492 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
493 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
494 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
495 #endif
496
497 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
498 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
499 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
500
501 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
502 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
503 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
504 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
505
506 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
507 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
508 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
509 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
510 };
511
512 struct serv_parm { /* Structure is in Big Endian format */
513 struct csp cmn;
514 struct lpfc_name portName;
515 struct lpfc_name nodeName;
516 struct class_parms cls1;
517 struct class_parms cls2;
518 struct class_parms cls3;
519 struct class_parms cls4;
520 union {
521 uint8_t vendorVersion[16];
522 struct {
523 uint32_t vid;
524 #define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */
525 uint32_t flags;
526 #define LPFC_VV_SUPPRESS_RSP 1
527 } vv;
528 } un;
529 };
530
531 /*
532 * Virtual Fabric Tagging Header
533 */
534 struct fc_vft_header {
535 uint32_t word0;
536 #define fc_vft_hdr_r_ctl_SHIFT 24
537 #define fc_vft_hdr_r_ctl_MASK 0xFF
538 #define fc_vft_hdr_r_ctl_WORD word0
539 #define fc_vft_hdr_ver_SHIFT 22
540 #define fc_vft_hdr_ver_MASK 0x3
541 #define fc_vft_hdr_ver_WORD word0
542 #define fc_vft_hdr_type_SHIFT 18
543 #define fc_vft_hdr_type_MASK 0xF
544 #define fc_vft_hdr_type_WORD word0
545 #define fc_vft_hdr_e_SHIFT 16
546 #define fc_vft_hdr_e_MASK 0x1
547 #define fc_vft_hdr_e_WORD word0
548 #define fc_vft_hdr_priority_SHIFT 13
549 #define fc_vft_hdr_priority_MASK 0x7
550 #define fc_vft_hdr_priority_WORD word0
551 #define fc_vft_hdr_vf_id_SHIFT 1
552 #define fc_vft_hdr_vf_id_MASK 0xFFF
553 #define fc_vft_hdr_vf_id_WORD word0
554 uint32_t word1;
555 #define fc_vft_hdr_hopct_SHIFT 24
556 #define fc_vft_hdr_hopct_MASK 0xFF
557 #define fc_vft_hdr_hopct_WORD word1
558 };
559
560 /*
561 * Extended Link Service LS_COMMAND codes (Payload Word 0)
562 */
563 #ifdef __BIG_ENDIAN_BITFIELD
564 #define ELS_CMD_MASK 0xffff0000
565 #define ELS_RSP_MASK 0xff000000
566 #define ELS_CMD_LS_RJT 0x01000000
567 #define ELS_CMD_ACC 0x02000000
568 #define ELS_CMD_PLOGI 0x03000000
569 #define ELS_CMD_FLOGI 0x04000000
570 #define ELS_CMD_LOGO 0x05000000
571 #define ELS_CMD_ABTX 0x06000000
572 #define ELS_CMD_RCS 0x07000000
573 #define ELS_CMD_RES 0x08000000
574 #define ELS_CMD_RSS 0x09000000
575 #define ELS_CMD_RSI 0x0A000000
576 #define ELS_CMD_ESTS 0x0B000000
577 #define ELS_CMD_ESTC 0x0C000000
578 #define ELS_CMD_ADVC 0x0D000000
579 #define ELS_CMD_RTV 0x0E000000
580 #define ELS_CMD_RLS 0x0F000000
581 #define ELS_CMD_ECHO 0x10000000
582 #define ELS_CMD_TEST 0x11000000
583 #define ELS_CMD_RRQ 0x12000000
584 #define ELS_CMD_REC 0x13000000
585 #define ELS_CMD_RDP 0x18000000
586 #define ELS_CMD_PRLI 0x20100014
587 #define ELS_CMD_NVMEPRLI 0x20140018
588 #define ELS_CMD_PRLO 0x21100014
589 #define ELS_CMD_PRLO_ACC 0x02100014
590 #define ELS_CMD_PDISC 0x50000000
591 #define ELS_CMD_FDISC 0x51000000
592 #define ELS_CMD_ADISC 0x52000000
593 #define ELS_CMD_FARP 0x54000000
594 #define ELS_CMD_FARPR 0x55000000
595 #define ELS_CMD_RPS 0x56000000
596 #define ELS_CMD_RPL 0x57000000
597 #define ELS_CMD_FAN 0x60000000
598 #define ELS_CMD_RSCN 0x61040000
599 #define ELS_CMD_SCR 0x62000000
600 #define ELS_CMD_RNID 0x78000000
601 #define ELS_CMD_LIRR 0x7A000000
602 #define ELS_CMD_LCB 0x81000000
603 #else /* __LITTLE_ENDIAN_BITFIELD */
604 #define ELS_CMD_MASK 0xffff
605 #define ELS_RSP_MASK 0xff
606 #define ELS_CMD_LS_RJT 0x01
607 #define ELS_CMD_ACC 0x02
608 #define ELS_CMD_PLOGI 0x03
609 #define ELS_CMD_FLOGI 0x04
610 #define ELS_CMD_LOGO 0x05
611 #define ELS_CMD_ABTX 0x06
612 #define ELS_CMD_RCS 0x07
613 #define ELS_CMD_RES 0x08
614 #define ELS_CMD_RSS 0x09
615 #define ELS_CMD_RSI 0x0A
616 #define ELS_CMD_ESTS 0x0B
617 #define ELS_CMD_ESTC 0x0C
618 #define ELS_CMD_ADVC 0x0D
619 #define ELS_CMD_RTV 0x0E
620 #define ELS_CMD_RLS 0x0F
621 #define ELS_CMD_ECHO 0x10
622 #define ELS_CMD_TEST 0x11
623 #define ELS_CMD_RRQ 0x12
624 #define ELS_CMD_REC 0x13
625 #define ELS_CMD_RDP 0x18
626 #define ELS_CMD_PRLI 0x14001020
627 #define ELS_CMD_NVMEPRLI 0x18001420
628 #define ELS_CMD_PRLO 0x14001021
629 #define ELS_CMD_PRLO_ACC 0x14001002
630 #define ELS_CMD_PDISC 0x50
631 #define ELS_CMD_FDISC 0x51
632 #define ELS_CMD_ADISC 0x52
633 #define ELS_CMD_FARP 0x54
634 #define ELS_CMD_FARPR 0x55
635 #define ELS_CMD_RPS 0x56
636 #define ELS_CMD_RPL 0x57
637 #define ELS_CMD_FAN 0x60
638 #define ELS_CMD_RSCN 0x0461
639 #define ELS_CMD_SCR 0x62
640 #define ELS_CMD_RNID 0x78
641 #define ELS_CMD_LIRR 0x7A
642 #define ELS_CMD_LCB 0x81
643 #endif
644
645 /*
646 * LS_RJT Payload Definition
647 */
648
649 struct ls_rjt { /* Structure is in Big Endian format */
650 union {
651 uint32_t lsRjtError;
652 struct {
653 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
654
655 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
656 /* LS_RJT reason codes */
657 #define LSRJT_INVALID_CMD 0x01
658 #define LSRJT_LOGICAL_ERR 0x03
659 #define LSRJT_LOGICAL_BSY 0x05
660 #define LSRJT_PROTOCOL_ERR 0x07
661 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
662 #define LSRJT_CMD_UNSUPPORTED 0x0B
663 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
664
665 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
666 /* LS_RJT reason explanation */
667 #define LSEXP_NOTHING_MORE 0x00
668 #define LSEXP_SPARM_OPTIONS 0x01
669 #define LSEXP_SPARM_ICTL 0x03
670 #define LSEXP_SPARM_RCTL 0x05
671 #define LSEXP_SPARM_RCV_SIZE 0x07
672 #define LSEXP_SPARM_CONCUR_SEQ 0x09
673 #define LSEXP_SPARM_CREDIT 0x0B
674 #define LSEXP_INVALID_PNAME 0x0D
675 #define LSEXP_INVALID_NNAME 0x0E
676 #define LSEXP_INVALID_CSP 0x0F
677 #define LSEXP_INVALID_ASSOC_HDR 0x11
678 #define LSEXP_ASSOC_HDR_REQ 0x13
679 #define LSEXP_INVALID_O_SID 0x15
680 #define LSEXP_INVALID_OX_RX 0x17
681 #define LSEXP_CMD_IN_PROGRESS 0x19
682 #define LSEXP_PORT_LOGIN_REQ 0x1E
683 #define LSEXP_INVALID_NPORT_ID 0x1F
684 #define LSEXP_INVALID_SEQ_ID 0x21
685 #define LSEXP_INVALID_XCHG 0x23
686 #define LSEXP_INACTIVE_XCHG 0x25
687 #define LSEXP_RQ_REQUIRED 0x27
688 #define LSEXP_OUT_OF_RESOURCE 0x29
689 #define LSEXP_CANT_GIVE_DATA 0x2A
690 #define LSEXP_REQ_UNSUPPORTED 0x2C
691 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
692 } b;
693 } un;
694 };
695
696 /*
697 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
698 */
699
700 typedef struct _LOGO { /* Structure is in Big Endian format */
701 union {
702 uint32_t nPortId32; /* Access nPortId as a word */
703 struct {
704 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
705 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
706 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
707 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
708 } b;
709 } un;
710 struct lpfc_name portName; /* N_port name field */
711 } LOGO;
712
713 /*
714 * FCP Login (PRLI Request / ACC) Payload Definition
715 */
716
717 #define PRLX_PAGE_LEN 0x10
718 #define TPRLO_PAGE_LEN 0x14
719
720 typedef struct _PRLI { /* Structure is in Big Endian format */
721 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
722
723 #define PRLI_FCP_TYPE 0x08
724 #define PRLI_NVME_TYPE 0x28
725 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
726
727 #ifdef __BIG_ENDIAN_BITFIELD
728 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
729 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
730 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
731
732 /* ACC = imagePairEstablished */
733 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
734 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
735 #else /* __LITTLE_ENDIAN_BITFIELD */
736 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
737 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
738 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
739 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
740 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
741 /* ACC = imagePairEstablished */
742 #endif
743
744 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
745 #define PRLI_NO_RESOURCES 0x2
746 #define PRLI_INIT_INCOMPLETE 0x3
747 #define PRLI_NO_SUCH_PA 0x4
748 #define PRLI_PREDEF_CONFIG 0x5
749 #define PRLI_PARTIAL_SUCCESS 0x6
750 #define PRLI_INVALID_PAGE_CNT 0x7
751 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
752
753 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
754
755 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
756
757 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
758 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
759
760 #ifdef __BIG_ENDIAN_BITFIELD
761 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
762 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
763 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
764 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
765 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
766 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
767 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
768 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
769 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
770 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
771 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
772 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
773 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
774 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
775 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
776 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
777 #else /* __LITTLE_ENDIAN_BITFIELD */
778 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
779 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
780 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
781 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
782 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
783 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
784 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
785 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
786 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
787 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
788 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
789 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
790 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
791 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
792 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
793 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
794 #endif
795 } PRLI;
796
797 /*
798 * FCP Logout (PRLO Request / ACC) Payload Definition
799 */
800
801 typedef struct _PRLO { /* Structure is in Big Endian format */
802 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
803
804 #define PRLO_FCP_TYPE 0x08
805 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
806
807 #ifdef __BIG_ENDIAN_BITFIELD
808 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
809 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
810 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
811 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
812 #else /* __LITTLE_ENDIAN_BITFIELD */
813 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
814 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
815 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
816 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
817 #endif
818
819 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
820 #define PRLO_NO_SUCH_IMAGE 0x4
821 #define PRLO_INVALID_PAGE_CNT 0x7
822
823 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
824
825 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
826
827 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
828
829 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
830 } PRLO;
831
832 typedef struct _ADISC { /* Structure is in Big Endian format */
833 uint32_t hardAL_PA;
834 struct lpfc_name portName;
835 struct lpfc_name nodeName;
836 uint32_t DID;
837 } ADISC;
838
839 typedef struct _FARP { /* Structure is in Big Endian format */
840 uint32_t Mflags:8;
841 uint32_t Odid:24;
842 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
843 action */
844 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
845 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
846 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
847 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
848 supported */
849 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
850 supported */
851 uint32_t Rflags:8;
852 uint32_t Rdid:24;
853 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
854 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
855 struct lpfc_name OportName;
856 struct lpfc_name OnodeName;
857 struct lpfc_name RportName;
858 struct lpfc_name RnodeName;
859 uint8_t Oipaddr[16];
860 uint8_t Ripaddr[16];
861 } FARP;
862
863 typedef struct _FAN { /* Structure is in Big Endian format */
864 uint32_t Fdid;
865 struct lpfc_name FportName;
866 struct lpfc_name FnodeName;
867 } FAN;
868
869 typedef struct _SCR { /* Structure is in Big Endian format */
870 uint8_t resvd1;
871 uint8_t resvd2;
872 uint8_t resvd3;
873 uint8_t Function;
874 #define SCR_FUNC_FABRIC 0x01
875 #define SCR_FUNC_NPORT 0x02
876 #define SCR_FUNC_FULL 0x03
877 #define SCR_CLEAR 0xff
878 } SCR;
879
880 typedef struct _RNID_TOP_DISC {
881 struct lpfc_name portName;
882 uint8_t resvd[8];
883 uint32_t unitType;
884 #define RNID_HBA 0x7
885 #define RNID_HOST 0xa
886 #define RNID_DRIVER 0xd
887 uint32_t physPort;
888 uint32_t attachedNodes;
889 uint16_t ipVersion;
890 #define RNID_IPV4 0x1
891 #define RNID_IPV6 0x2
892 uint16_t UDPport;
893 uint8_t ipAddr[16];
894 uint16_t resvd1;
895 uint16_t flags;
896 #define RNID_TD_SUPPORT 0x1
897 #define RNID_LP_VALID 0x2
898 } RNID_TOP_DISC;
899
900 typedef struct _RNID { /* Structure is in Big Endian format */
901 uint8_t Format;
902 #define RNID_TOPOLOGY_DISC 0xdf
903 uint8_t CommonLen;
904 uint8_t resvd1;
905 uint8_t SpecificLen;
906 struct lpfc_name portName;
907 struct lpfc_name nodeName;
908 union {
909 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
910 } un;
911 } RNID;
912
913 typedef struct _RPS { /* Structure is in Big Endian format */
914 union {
915 uint32_t portNum;
916 struct lpfc_name portName;
917 } un;
918 } RPS;
919
920 typedef struct _RPS_RSP { /* Structure is in Big Endian format */
921 uint16_t rsvd1;
922 uint16_t portStatus;
923 uint32_t linkFailureCnt;
924 uint32_t lossSyncCnt;
925 uint32_t lossSignalCnt;
926 uint32_t primSeqErrCnt;
927 uint32_t invalidXmitWord;
928 uint32_t crcCnt;
929 } RPS_RSP;
930
931 struct RLS { /* Structure is in Big Endian format */
932 uint32_t rls;
933 #define rls_rsvd_SHIFT 24
934 #define rls_rsvd_MASK 0x000000ff
935 #define rls_rsvd_WORD rls
936 #define rls_did_SHIFT 0
937 #define rls_did_MASK 0x00ffffff
938 #define rls_did_WORD rls
939 };
940
941 struct RLS_RSP { /* Structure is in Big Endian format */
942 uint32_t linkFailureCnt;
943 uint32_t lossSyncCnt;
944 uint32_t lossSignalCnt;
945 uint32_t primSeqErrCnt;
946 uint32_t invalidXmitWord;
947 uint32_t crcCnt;
948 };
949
950 struct RRQ { /* Structure is in Big Endian format */
951 uint32_t rrq;
952 #define rrq_rsvd_SHIFT 24
953 #define rrq_rsvd_MASK 0x000000ff
954 #define rrq_rsvd_WORD rrq
955 #define rrq_did_SHIFT 0
956 #define rrq_did_MASK 0x00ffffff
957 #define rrq_did_WORD rrq
958 uint32_t rrq_exchg;
959 #define rrq_oxid_SHIFT 16
960 #define rrq_oxid_MASK 0xffff
961 #define rrq_oxid_WORD rrq_exchg
962 #define rrq_rxid_SHIFT 0
963 #define rrq_rxid_MASK 0xffff
964 #define rrq_rxid_WORD rrq_exchg
965 };
966
967 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
968 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
969
970 struct RTV_RSP { /* Structure is in Big Endian format */
971 uint32_t ratov;
972 uint32_t edtov;
973 uint32_t qtov;
974 #define qtov_rsvd0_SHIFT 28
975 #define qtov_rsvd0_MASK 0x0000000f
976 #define qtov_rsvd0_WORD qtov /* reserved */
977 #define qtov_edtovres_SHIFT 27
978 #define qtov_edtovres_MASK 0x00000001
979 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
980 #define qtov__rsvd1_SHIFT 19
981 #define qtov_rsvd1_MASK 0x0000003f
982 #define qtov_rsvd1_WORD qtov /* reserved */
983 #define qtov_rttov_SHIFT 18
984 #define qtov_rttov_MASK 0x00000001
985 #define qtov_rttov_WORD qtov /* R_T_TOV value */
986 #define qtov_rsvd2_SHIFT 0
987 #define qtov_rsvd2_MASK 0x0003ffff
988 #define qtov_rsvd2_WORD qtov /* reserved */
989 };
990
991
992 typedef struct _RPL { /* Structure is in Big Endian format */
993 uint32_t maxsize;
994 uint32_t index;
995 } RPL;
996
997 typedef struct _PORT_NUM_BLK {
998 uint32_t portNum;
999 uint32_t portID;
1000 struct lpfc_name portName;
1001 } PORT_NUM_BLK;
1002
1003 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
1004 uint32_t listLen;
1005 uint32_t index;
1006 PORT_NUM_BLK port_num_blk;
1007 } RPL_RSP;
1008
1009 /* This is used for RSCN command */
1010 typedef struct _D_ID { /* Structure is in Big Endian format */
1011 union {
1012 uint32_t word;
1013 struct {
1014 #ifdef __BIG_ENDIAN_BITFIELD
1015 uint8_t resv;
1016 uint8_t domain;
1017 uint8_t area;
1018 uint8_t id;
1019 #else /* __LITTLE_ENDIAN_BITFIELD */
1020 uint8_t id;
1021 uint8_t area;
1022 uint8_t domain;
1023 uint8_t resv;
1024 #endif
1025 } b;
1026 } un;
1027 } D_ID;
1028
1029 #define RSCN_ADDRESS_FORMAT_PORT 0x0
1030 #define RSCN_ADDRESS_FORMAT_AREA 0x1
1031 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
1032 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
1033 #define RSCN_ADDRESS_FORMAT_MASK 0x3
1034
1035 /*
1036 * Structure to define all ELS Payload types
1037 */
1038
1039 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
1040 uint8_t elsCode; /* FC Word 0, bit 24:31 */
1041 uint8_t elsByte1;
1042 uint8_t elsByte2;
1043 uint8_t elsByte3;
1044 union {
1045 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
1046 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
1047 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
1048 PRLI prli; /* Payload for PRLI/ACC */
1049 PRLO prlo; /* Payload for PRLO/ACC */
1050 ADISC adisc; /* Payload for ADISC/ACC */
1051 FARP farp; /* Payload for FARP/ACC */
1052 FAN fan; /* Payload for FAN */
1053 SCR scr; /* Payload for SCR/ACC */
1054 RNID rnid; /* Payload for RNID */
1055 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
1056 } un;
1057 } ELS_PKT;
1058
1059 /*
1060 * Link Cable Beacon (LCB) ELS Frame
1061 */
1062
1063 struct fc_lcb_request_frame {
1064 uint32_t lcb_command; /* ELS command opcode (0x81) */
1065 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1066 #define LPFC_LCB_ON 0x1
1067 #define LPFC_LCB_OFF 0x2
1068 uint8_t reserved[3];
1069
1070 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1071 #define LPFC_LCB_GREEN 0x1
1072 #define LPFC_LCB_AMBER 0x2
1073 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1074 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1075 };
1076
1077 /*
1078 * Link Cable Beacon (LCB) ELS Response Frame
1079 */
1080 struct fc_lcb_res_frame {
1081 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */
1082 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1083 uint8_t reserved[3];
1084 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1085 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1086 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1087 };
1088
1089 /*
1090 * Read Diagnostic Parameters (RDP) ELS frame.
1091 */
1092 #define SFF_PG0_IDENT_SFP 0x3
1093
1094 #define SFP_FLAG_PT_OPTICAL 0x0
1095 #define SFP_FLAG_PT_SWLASER 0x01
1096 #define SFP_FLAG_PT_LWLASER_LC1310 0x02
1097 #define SFP_FLAG_PT_LWLASER_LL1550 0x03
1098 #define SFP_FLAG_PT_MASK 0x0F
1099 #define SFP_FLAG_PT_SHIFT 0
1100
1101 #define SFP_FLAG_IS_OPTICAL_PORT 0x01
1102 #define SFP_FLAG_IS_OPTICAL_MASK 0x010
1103 #define SFP_FLAG_IS_OPTICAL_SHIFT 4
1104
1105 #define SFP_FLAG_IS_DESC_VALID 0x01
1106 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020
1107 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5
1108
1109 #define SFP_FLAG_CT_UNKNOWN 0x0
1110 #define SFP_FLAG_CT_SFP_PLUS 0x01
1111 #define SFP_FLAG_CT_MASK 0x3C
1112 #define SFP_FLAG_CT_SHIFT 6
1113
1114 struct fc_rdp_port_name_info {
1115 uint8_t wwnn[8];
1116 uint8_t wwpn[8];
1117 };
1118
1119
1120 /*
1121 * Link Error Status Block Structure (FC-FS-3) for RDP
1122 * This similar to RPS ELS
1123 */
1124 struct fc_link_status {
1125 uint32_t link_failure_cnt;
1126 uint32_t loss_of_synch_cnt;
1127 uint32_t loss_of_signal_cnt;
1128 uint32_t primitive_seq_proto_err;
1129 uint32_t invalid_trans_word;
1130 uint32_t invalid_crc_cnt;
1131
1132 };
1133
1134 #define RDP_PORT_NAMES_DESC_TAG 0x00010003
1135 struct fc_rdp_port_name_desc {
1136 uint32_t tag; /* 0001 0003h */
1137 uint32_t length; /* set to size of payload struct */
1138 struct fc_rdp_port_name_info port_names;
1139 };
1140
1141
1142 struct fc_rdp_fec_info {
1143 uint32_t CorrectedBlocks;
1144 uint32_t UncorrectableBlocks;
1145 };
1146
1147 #define RDP_FEC_DESC_TAG 0x00010005
1148 struct fc_fec_rdp_desc {
1149 uint32_t tag;
1150 uint32_t length;
1151 struct fc_rdp_fec_info info;
1152 };
1153
1154 struct fc_rdp_link_error_status_payload_info {
1155 struct fc_link_status link_status; /* 24 bytes */
1156 uint32_t port_type; /* bits 31-30 only */
1157 };
1158
1159 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
1160 struct fc_rdp_link_error_status_desc {
1161 uint32_t tag; /* 0001 0002h */
1162 uint32_t length; /* set to size of payload struct */
1163 struct fc_rdp_link_error_status_payload_info info;
1164 };
1165
1166 #define VN_PT_PHY_UNKNOWN 0x00
1167 #define VN_PT_PHY_PF_PORT 0x01
1168 #define VN_PT_PHY_ETH_MAC 0x10
1169 #define VN_PT_PHY_SHIFT 30
1170
1171 #define RDP_PS_1GB 0x8000
1172 #define RDP_PS_2GB 0x4000
1173 #define RDP_PS_4GB 0x2000
1174 #define RDP_PS_10GB 0x1000
1175 #define RDP_PS_8GB 0x0800
1176 #define RDP_PS_16GB 0x0400
1177 #define RDP_PS_32GB 0x0200
1178
1179 #define RDP_CAP_USER_CONFIGURED 0x0002
1180 #define RDP_CAP_UNKNOWN 0x0001
1181 #define RDP_PS_UNKNOWN 0x0002
1182 #define RDP_PS_NOT_ESTABLISHED 0x0001
1183
1184 struct fc_rdp_port_speed {
1185 uint16_t capabilities;
1186 uint16_t speed;
1187 };
1188
1189 struct fc_rdp_port_speed_info {
1190 struct fc_rdp_port_speed port_speed;
1191 };
1192
1193 #define RDP_PORT_SPEED_DESC_TAG 0x00010001
1194 struct fc_rdp_port_speed_desc {
1195 uint32_t tag; /* 00010001h */
1196 uint32_t length; /* set to size of payload struct */
1197 struct fc_rdp_port_speed_info info;
1198 };
1199
1200 #define RDP_NPORT_ID_SIZE 4
1201 #define RDP_N_PORT_DESC_TAG 0x00000003
1202 struct fc_rdp_nport_desc {
1203 uint32_t tag; /* 0000 0003h, big endian */
1204 uint32_t length; /* size of RDP_N_PORT_ID struct */
1205 uint32_t nport_id : 12;
1206 uint32_t reserved : 8;
1207 };
1208
1209
1210 struct fc_rdp_link_service_info {
1211 uint32_t els_req; /* Request payload word 0 value.*/
1212 };
1213
1214 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001
1215 struct fc_rdp_link_service_desc {
1216 uint32_t tag; /* Descriptor tag 1 */
1217 uint32_t length; /* set to size of payload struct. */
1218 struct fc_rdp_link_service_info payload;
1219 /* must be ELS req Word 0(0x18) */
1220 };
1221
1222 struct fc_rdp_sfp_info {
1223 uint16_t temperature;
1224 uint16_t vcc;
1225 uint16_t tx_bias;
1226 uint16_t tx_power;
1227 uint16_t rx_power;
1228 uint16_t flags;
1229 };
1230
1231 #define RDP_SFP_DESC_TAG 0x00010000
1232 struct fc_rdp_sfp_desc {
1233 uint32_t tag;
1234 uint32_t length; /* set to size of sfp_info struct */
1235 struct fc_rdp_sfp_info sfp_info;
1236 };
1237
1238 /* Buffer Credit Descriptor */
1239 struct fc_rdp_bbc_info {
1240 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */
1241 uint32_t attached_port_bbc;
1242 uint32_t rtt; /* Round trip time */
1243 };
1244 #define RDP_BBC_DESC_TAG 0x00010006
1245 struct fc_rdp_bbc_desc {
1246 uint32_t tag;
1247 uint32_t length;
1248 struct fc_rdp_bbc_info bbc_info;
1249 };
1250
1251 /* Optical Element Type Transgression Flags */
1252 #define RDP_OET_LOW_WARNING 0x1
1253 #define RDP_OET_HIGH_WARNING 0x2
1254 #define RDP_OET_LOW_ALARM 0x4
1255 #define RDP_OET_HIGH_ALARM 0x8
1256
1257 #define RDP_OED_TEMPERATURE 0x1
1258 #define RDP_OED_VOLTAGE 0x2
1259 #define RDP_OED_TXBIAS 0x3
1260 #define RDP_OED_TXPOWER 0x4
1261 #define RDP_OED_RXPOWER 0x5
1262
1263 #define RDP_OED_TYPE_SHIFT 28
1264 /* Optical Element Data descriptor */
1265 struct fc_rdp_oed_info {
1266 uint16_t hi_alarm;
1267 uint16_t lo_alarm;
1268 uint16_t hi_warning;
1269 uint16_t lo_warning;
1270 uint32_t function_flags;
1271 };
1272 #define RDP_OED_DESC_TAG 0x00010007
1273 struct fc_rdp_oed_sfp_desc {
1274 uint32_t tag;
1275 uint32_t length;
1276 struct fc_rdp_oed_info oed_info;
1277 };
1278
1279 /* Optical Product Data descriptor */
1280 struct fc_rdp_opd_sfp_info {
1281 uint8_t vendor_name[16];
1282 uint8_t model_number[16];
1283 uint8_t serial_number[16];
1284 uint8_t revision[4];
1285 uint8_t date[8];
1286 };
1287
1288 #define RDP_OPD_DESC_TAG 0x00010008
1289 struct fc_rdp_opd_sfp_desc {
1290 uint32_t tag;
1291 uint32_t length;
1292 struct fc_rdp_opd_sfp_info opd_info;
1293 };
1294
1295 struct fc_rdp_req_frame {
1296 uint32_t rdp_command; /* ELS command opcode (0x18)*/
1297 uint32_t rdp_des_length; /* RDP Payload Word 1 */
1298 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1299 };
1300
1301
1302 struct fc_rdp_res_frame {
1303 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */
1304 uint32_t length; /* FC Word 1 */
1305 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */
1306 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */
1307 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */
1308 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */
1309 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */
1310 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */
1311 struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/
1312 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/
1313 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/
1314 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/
1315 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/
1316 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/
1317 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/
1318 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/
1319 };
1320
1321
1322 /******** FDMI ********/
1323
1324 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1325 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */
1326
1327 /*
1328 * Registered Port List Format
1329 */
1330 struct lpfc_fdmi_reg_port_list {
1331 uint32_t EntryCnt;
1332 uint32_t pe; /* Variable-length array */
1333 };
1334
1335
1336 /* Definitions for HBA / Port attribute entries */
1337
1338 struct lpfc_fdmi_attr_def { /* Defined in TLV format */
1339 /* Structure is in Big Endian format */
1340 uint32_t AttrType:16;
1341 uint32_t AttrLen:16;
1342 uint32_t AttrValue; /* Marks start of Value (ATTRIBUTE_ENTRY) */
1343 };
1344
1345
1346 /* Attribute Entry */
1347 struct lpfc_fdmi_attr_entry {
1348 union {
1349 uint32_t AttrInt;
1350 uint8_t AttrTypes[32];
1351 uint8_t AttrString[256];
1352 struct lpfc_name AttrWWN;
1353 } un;
1354 };
1355
1356 #define LPFC_FDMI_MAX_AE_SIZE sizeof(struct lpfc_fdmi_attr_entry)
1357
1358 /*
1359 * HBA Attribute Block
1360 */
1361 struct lpfc_fdmi_attr_block {
1362 uint32_t EntryCnt; /* Number of HBA attribute entries */
1363 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */
1364 };
1365
1366 /*
1367 * Port Entry
1368 */
1369 struct lpfc_fdmi_port_entry {
1370 struct lpfc_name PortName;
1371 };
1372
1373 /*
1374 * HBA Identifier
1375 */
1376 struct lpfc_fdmi_hba_ident {
1377 struct lpfc_name PortName;
1378 };
1379
1380 /*
1381 * Register HBA(RHBA)
1382 */
1383 struct lpfc_fdmi_reg_hba {
1384 struct lpfc_fdmi_hba_ident hi;
1385 struct lpfc_fdmi_reg_port_list rpl; /* variable-length array */
1386 /* struct lpfc_fdmi_attr_block ab; */
1387 };
1388
1389 /*
1390 * Register HBA Attributes (RHAT)
1391 */
1392 struct lpfc_fdmi_reg_hbaattr {
1393 struct lpfc_name HBA_PortName;
1394 struct lpfc_fdmi_attr_block ab;
1395 };
1396
1397 /*
1398 * Register Port Attributes (RPA)
1399 */
1400 struct lpfc_fdmi_reg_portattr {
1401 struct lpfc_name PortName;
1402 struct lpfc_fdmi_attr_block ab;
1403 };
1404
1405 /*
1406 * HBA MAnagement Operations Command Codes
1407 */
1408 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1409 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1410 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1411 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1412 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */
1413 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
1414 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
1415 #define SLI_MGMT_RPRT 0x210 /* Register Port */
1416 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1417 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1418 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */
1419 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
1420 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */
1421
1422 #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */
1423
1424 /*
1425 * HBA Attribute Types
1426 */
1427 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */
1428 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */
1429 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */
1430 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */
1431 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */
1432 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */
1433 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */
1434 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1435 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */
1436 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */
1437 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1438 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */
1439 #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */
1440 #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */
1441 #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */
1442 #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */
1443 #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */
1444 #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */
1445
1446 /* Bit mask for all individual HBA attributes */
1447 #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001
1448 #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002
1449 #define LPFC_FDMI_HBA_ATTR_sn 0x00000004
1450 #define LPFC_FDMI_HBA_ATTR_model 0x00000008
1451 #define LPFC_FDMI_HBA_ATTR_description 0x00000010
1452 #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020
1453 #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040
1454 #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080
1455 #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100
1456 #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200
1457 #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400
1458 #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800
1459 #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */
1460 #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000
1461 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000
1462 #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000
1463 #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */
1464 #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000
1465
1466 /* Bit mask for FDMI-1 defined HBA attributes */
1467 #define LPFC_FDMI1_HBA_ATTR 0x000007ff
1468
1469 /* Bit mask for FDMI-2 defined HBA attributes */
1470 /* Skip vendor_info and bios_state */
1471 #define LPFC_FDMI2_HBA_ATTR 0x0002efff
1472
1473 /*
1474 * Port Attrubute Types
1475 */
1476 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */
1477 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */
1478 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */
1479 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */
1480 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */
1481 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */
1482 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */
1483 #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */
1484 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */
1485 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */
1486 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */
1487 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */
1488 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */
1489 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */
1490 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */
1491 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */
1492 #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */
1493 #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */
1494 #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */
1495 #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */
1496 #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */
1497 #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */
1498 #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */
1499
1500 /* Bit mask for all individual PORT attributes */
1501 #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001
1502 #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002
1503 #define LPFC_FDMI_PORT_ATTR_speed 0x00000004
1504 #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008
1505 #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010
1506 #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020
1507 #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040
1508 #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080
1509 #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100
1510 #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200
1511 #define LPFC_FDMI_PORT_ATTR_class 0x00000400
1512 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800
1513 #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000
1514 #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000
1515 #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000
1516 #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000
1517 #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */
1518 #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */
1519 #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */
1520 #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */
1521 #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */
1522 #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */
1523 #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */
1524
1525 /* Bit mask for FDMI-1 defined PORT attributes */
1526 #define LPFC_FDMI1_PORT_ATTR 0x0000003f
1527
1528 /* Bit mask for FDMI-2 defined PORT attributes */
1529 #define LPFC_FDMI2_PORT_ATTR 0x0000ffff
1530
1531 /* Bit mask for Smart SAN defined PORT attributes */
1532 #define LPFC_FDMI2_SMART_ATTR 0x007fffff
1533
1534 /* Defines for PORT port state attribute */
1535 #define LPFC_FDMI_PORTSTATE_UNKNOWN 1
1536 #define LPFC_FDMI_PORTSTATE_ONLINE 2
1537
1538 /* Defines for PORT port type attribute */
1539 #define LPFC_FDMI_PORTTYPE_UNKNOWN 0
1540 #define LPFC_FDMI_PORTTYPE_NPORT 1
1541 #define LPFC_FDMI_PORTTYPE_NLPORT 2
1542
1543 /*
1544 * Begin HBA configuration parameters.
1545 * The PCI configuration register BAR assignments are:
1546 * BAR0, offset 0x10 - SLIM base memory address
1547 * BAR1, offset 0x14 - SLIM base memory high address
1548 * BAR2, offset 0x18 - REGISTER base memory address
1549 * BAR3, offset 0x1c - REGISTER base memory high address
1550 * BAR4, offset 0x20 - BIU I/O registers
1551 * BAR5, offset 0x24 - REGISTER base io high address
1552 */
1553
1554 /* Number of rings currently used and available. */
1555 #define MAX_SLI3_CONFIGURED_RINGS 3
1556 #define MAX_SLI3_RINGS 4
1557
1558 /* IOCB / Mailbox is owned by FireFly */
1559 #define OWN_CHIP 1
1560
1561 /* IOCB / Mailbox is owned by Host */
1562 #define OWN_HOST 0
1563
1564 /* Number of 4-byte words in an IOCB. */
1565 #define IOCB_WORD_SZ 8
1566
1567 /* network headers for Dfctl field */
1568 #define FC_NET_HDR 0x20
1569
1570 /* Start FireFly Register definitions */
1571 #define PCI_VENDOR_ID_EMULEX 0x10df
1572 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1573 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1574 #define PCI_DEVICE_ID_BALIUS 0xe131
1575 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1576 #define PCI_DEVICE_ID_LANCER_FC 0xe200
1577 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1578 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1579 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1580 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
1581 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1582 #define PCI_DEVICE_ID_SAT_MID 0xf015
1583 #define PCI_DEVICE_ID_RFLY 0xf095
1584 #define PCI_DEVICE_ID_PFLY 0xf098
1585 #define PCI_DEVICE_ID_LP101 0xf0a1
1586 #define PCI_DEVICE_ID_TFLY 0xf0a5
1587 #define PCI_DEVICE_ID_BSMB 0xf0d1
1588 #define PCI_DEVICE_ID_BMID 0xf0d5
1589 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1590 #define PCI_DEVICE_ID_ZMID 0xf0e5
1591 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1592 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1593 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1594 #define PCI_DEVICE_ID_SAT 0xf100
1595 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1596 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1597 #define PCI_DEVICE_ID_FALCON 0xf180
1598 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1599 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1600 #define PCI_DEVICE_ID_CENTAUR 0xf900
1601 #define PCI_DEVICE_ID_PEGASUS 0xf980
1602 #define PCI_DEVICE_ID_THOR 0xfa00
1603 #define PCI_DEVICE_ID_VIPER 0xfb00
1604 #define PCI_DEVICE_ID_LP10000S 0xfc00
1605 #define PCI_DEVICE_ID_LP11000S 0xfc10
1606 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1607 #define PCI_DEVICE_ID_SAT_S 0xfc40
1608 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1609 #define PCI_DEVICE_ID_HELIOS 0xfd00
1610 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1611 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1612 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1613 #define PCI_DEVICE_ID_HORNET 0xfe05
1614 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1615 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1616 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1617 #define PCI_DEVICE_ID_TIGERSHARK 0x0704
1618 #define PCI_DEVICE_ID_TOMCAT 0x0714
1619 #define PCI_DEVICE_ID_SKYHAWK 0x0724
1620 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1621
1622 #define JEDEC_ID_ADDRESS 0x0080001c
1623 #define FIREFLY_JEDEC_ID 0x1ACC
1624 #define SUPERFLY_JEDEC_ID 0x0020
1625 #define DRAGONFLY_JEDEC_ID 0x0021
1626 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1627 #define CENTAUR_2G_JEDEC_ID 0x0026
1628 #define CENTAUR_1G_JEDEC_ID 0x0028
1629 #define PEGASUS_ORION_JEDEC_ID 0x0036
1630 #define PEGASUS_JEDEC_ID 0x0038
1631 #define THOR_JEDEC_ID 0x0012
1632 #define HELIOS_JEDEC_ID 0x0364
1633 #define ZEPHYR_JEDEC_ID 0x0577
1634 #define VIPER_JEDEC_ID 0x4838
1635 #define SATURN_JEDEC_ID 0x1004
1636 #define HORNET_JDEC_ID 0x2057706D
1637
1638 #define JEDEC_ID_MASK 0x0FFFF000
1639 #define JEDEC_ID_SHIFT 12
1640 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1641
1642 typedef struct { /* FireFly BIU registers */
1643 uint32_t hostAtt; /* See definitions for Host Attention
1644 register */
1645 uint32_t chipAtt; /* See definitions for Chip Attention
1646 register */
1647 uint32_t hostStatus; /* See definitions for Host Status register */
1648 uint32_t hostControl; /* See definitions for Host Control register */
1649 uint32_t buiConfig; /* See definitions for BIU configuration
1650 register */
1651 } FF_REGS;
1652
1653 /* IO Register size in bytes */
1654 #define FF_REG_AREA_SIZE 256
1655
1656 /* Host Attention Register */
1657
1658 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1659
1660 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1661 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1662 #define HA_R0ATT 0x00000008 /* Bit 3 */
1663 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1664 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1665 #define HA_R1ATT 0x00000080 /* Bit 7 */
1666 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1667 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1668 #define HA_R2ATT 0x00000800 /* Bit 11 */
1669 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1670 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1671 #define HA_R3ATT 0x00008000 /* Bit 15 */
1672 #define HA_LATT 0x20000000 /* Bit 29 */
1673 #define HA_MBATT 0x40000000 /* Bit 30 */
1674 #define HA_ERATT 0x80000000 /* Bit 31 */
1675
1676 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1677 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1678 #define HA_RXATT 0x00000008 /* Bit 3 */
1679 #define HA_RXMASK 0x0000000f
1680
1681 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1682 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1683 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1684 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1685
1686 #define HA_R0_POS 3
1687 #define HA_R1_POS 7
1688 #define HA_R2_POS 11
1689 #define HA_R3_POS 15
1690 #define HA_LE_POS 29
1691 #define HA_MB_POS 30
1692 #define HA_ER_POS 31
1693 /* Chip Attention Register */
1694
1695 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1696
1697 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1698 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1699 #define CA_R0ATT 0x00000008 /* Bit 3 */
1700 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1701 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1702 #define CA_R1ATT 0x00000080 /* Bit 7 */
1703 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1704 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1705 #define CA_R2ATT 0x00000800 /* Bit 11 */
1706 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1707 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1708 #define CA_R3ATT 0x00008000 /* Bit 15 */
1709 #define CA_MBATT 0x40000000 /* Bit 30 */
1710
1711 /* Host Status Register */
1712
1713 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1714
1715 #define HS_MBRDY 0x00400000 /* Bit 22 */
1716 #define HS_FFRDY 0x00800000 /* Bit 23 */
1717 #define HS_FFER8 0x01000000 /* Bit 24 */
1718 #define HS_FFER7 0x02000000 /* Bit 25 */
1719 #define HS_FFER6 0x04000000 /* Bit 26 */
1720 #define HS_FFER5 0x08000000 /* Bit 27 */
1721 #define HS_FFER4 0x10000000 /* Bit 28 */
1722 #define HS_FFER3 0x20000000 /* Bit 29 */
1723 #define HS_FFER2 0x40000000 /* Bit 30 */
1724 #define HS_FFER1 0x80000000 /* Bit 31 */
1725 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1726 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1727 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
1728 /* Host Control Register */
1729
1730 #define HC_REG_OFFSET 12 /* Byte offset from register base address */
1731
1732 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1733 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1734 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1735 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1736 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1737 #define HC_INITHBI 0x02000000 /* Bit 25 */
1738 #define HC_INITMB 0x04000000 /* Bit 26 */
1739 #define HC_INITFF 0x08000000 /* Bit 27 */
1740 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1741 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1742
1743 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1744 #define MSIX_DFLT_ID 0
1745 #define MSIX_RNG0_ID 0
1746 #define MSIX_RNG1_ID 1
1747 #define MSIX_RNG2_ID 2
1748 #define MSIX_RNG3_ID 3
1749
1750 #define MSIX_LINK_ID 4
1751 #define MSIX_MBOX_ID 5
1752
1753 #define MSIX_SPARE0_ID 6
1754 #define MSIX_SPARE1_ID 7
1755
1756 /* Mailbox Commands */
1757 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1758 #define MBX_LOAD_SM 0x01
1759 #define MBX_READ_NV 0x02
1760 #define MBX_WRITE_NV 0x03
1761 #define MBX_RUN_BIU_DIAG 0x04
1762 #define MBX_INIT_LINK 0x05
1763 #define MBX_DOWN_LINK 0x06
1764 #define MBX_CONFIG_LINK 0x07
1765 #define MBX_CONFIG_RING 0x09
1766 #define MBX_RESET_RING 0x0A
1767 #define MBX_READ_CONFIG 0x0B
1768 #define MBX_READ_RCONFIG 0x0C
1769 #define MBX_READ_SPARM 0x0D
1770 #define MBX_READ_STATUS 0x0E
1771 #define MBX_READ_RPI 0x0F
1772 #define MBX_READ_XRI 0x10
1773 #define MBX_READ_REV 0x11
1774 #define MBX_READ_LNK_STAT 0x12
1775 #define MBX_REG_LOGIN 0x13
1776 #define MBX_UNREG_LOGIN 0x14
1777 #define MBX_CLEAR_LA 0x16
1778 #define MBX_DUMP_MEMORY 0x17
1779 #define MBX_DUMP_CONTEXT 0x18
1780 #define MBX_RUN_DIAGS 0x19
1781 #define MBX_RESTART 0x1A
1782 #define MBX_UPDATE_CFG 0x1B
1783 #define MBX_DOWN_LOAD 0x1C
1784 #define MBX_DEL_LD_ENTRY 0x1D
1785 #define MBX_RUN_PROGRAM 0x1E
1786 #define MBX_SET_MASK 0x20
1787 #define MBX_SET_VARIABLE 0x21
1788 #define MBX_UNREG_D_ID 0x23
1789 #define MBX_KILL_BOARD 0x24
1790 #define MBX_CONFIG_FARP 0x25
1791 #define MBX_BEACON 0x2A
1792 #define MBX_CONFIG_MSI 0x30
1793 #define MBX_HEARTBEAT 0x31
1794 #define MBX_WRITE_VPARMS 0x32
1795 #define MBX_ASYNCEVT_ENABLE 0x33
1796 #define MBX_READ_EVENT_LOG_STATUS 0x37
1797 #define MBX_READ_EVENT_LOG 0x38
1798 #define MBX_WRITE_EVENT_LOG 0x39
1799
1800 #define MBX_PORT_CAPABILITIES 0x3B
1801 #define MBX_PORT_IOV_CONTROL 0x3C
1802
1803 #define MBX_CONFIG_HBQ 0x7C
1804 #define MBX_LOAD_AREA 0x81
1805 #define MBX_RUN_BIU_DIAG64 0x84
1806 #define MBX_CONFIG_PORT 0x88
1807 #define MBX_READ_SPARM64 0x8D
1808 #define MBX_READ_RPI64 0x8F
1809 #define MBX_REG_LOGIN64 0x93
1810 #define MBX_READ_TOPOLOGY 0x95
1811 #define MBX_REG_VPI 0x96
1812 #define MBX_UNREG_VPI 0x97
1813
1814 #define MBX_WRITE_WWN 0x98
1815 #define MBX_SET_DEBUG 0x99
1816 #define MBX_LOAD_EXP_ROM 0x9C
1817 #define MBX_SLI4_CONFIG 0x9B
1818 #define MBX_SLI4_REQ_FTRS 0x9D
1819 #define MBX_MAX_CMDS 0x9E
1820 #define MBX_RESUME_RPI 0x9E
1821 #define MBX_SLI2_CMD_MASK 0x80
1822 #define MBX_REG_VFI 0x9F
1823 #define MBX_REG_FCFI 0xA0
1824 #define MBX_UNREG_VFI 0xA1
1825 #define MBX_UNREG_FCFI 0xA2
1826 #define MBX_INIT_VFI 0xA3
1827 #define MBX_INIT_VPI 0xA4
1828 #define MBX_ACCESS_VDATA 0xA5
1829 #define MBX_REG_FCFI_MRQ 0xAF
1830
1831 #define MBX_AUTH_PORT 0xF8
1832 #define MBX_SECURITY_MGMT 0xF9
1833
1834 /* IOCB Commands */
1835
1836 #define CMD_RCV_SEQUENCE_CX 0x01
1837 #define CMD_XMIT_SEQUENCE_CR 0x02
1838 #define CMD_XMIT_SEQUENCE_CX 0x03
1839 #define CMD_XMIT_BCAST_CN 0x04
1840 #define CMD_XMIT_BCAST_CX 0x05
1841 #define CMD_QUE_RING_BUF_CN 0x06
1842 #define CMD_QUE_XRI_BUF_CX 0x07
1843 #define CMD_IOCB_CONTINUE_CN 0x08
1844 #define CMD_RET_XRI_BUF_CX 0x09
1845 #define CMD_ELS_REQUEST_CR 0x0A
1846 #define CMD_ELS_REQUEST_CX 0x0B
1847 #define CMD_RCV_ELS_REQ_CX 0x0D
1848 #define CMD_ABORT_XRI_CN 0x0E
1849 #define CMD_ABORT_XRI_CX 0x0F
1850 #define CMD_CLOSE_XRI_CN 0x10
1851 #define CMD_CLOSE_XRI_CX 0x11
1852 #define CMD_CREATE_XRI_CR 0x12
1853 #define CMD_CREATE_XRI_CX 0x13
1854 #define CMD_GET_RPI_CN 0x14
1855 #define CMD_XMIT_ELS_RSP_CX 0x15
1856 #define CMD_GET_RPI_CR 0x16
1857 #define CMD_XRI_ABORTED_CX 0x17
1858 #define CMD_FCP_IWRITE_CR 0x18
1859 #define CMD_FCP_IWRITE_CX 0x19
1860 #define CMD_FCP_IREAD_CR 0x1A
1861 #define CMD_FCP_IREAD_CX 0x1B
1862 #define CMD_FCP_ICMND_CR 0x1C
1863 #define CMD_FCP_ICMND_CX 0x1D
1864 #define CMD_FCP_TSEND_CX 0x1F
1865 #define CMD_FCP_TRECEIVE_CX 0x21
1866 #define CMD_FCP_TRSP_CX 0x23
1867 #define CMD_FCP_AUTO_TRSP_CX 0x29
1868
1869 #define CMD_ADAPTER_MSG 0x20
1870 #define CMD_ADAPTER_DUMP 0x22
1871
1872 /* SLI_2 IOCB Command Set */
1873
1874 #define CMD_ASYNC_STATUS 0x7C
1875 #define CMD_RCV_SEQUENCE64_CX 0x81
1876 #define CMD_XMIT_SEQUENCE64_CR 0x82
1877 #define CMD_XMIT_SEQUENCE64_CX 0x83
1878 #define CMD_XMIT_BCAST64_CN 0x84
1879 #define CMD_XMIT_BCAST64_CX 0x85
1880 #define CMD_QUE_RING_BUF64_CN 0x86
1881 #define CMD_QUE_XRI_BUF64_CX 0x87
1882 #define CMD_IOCB_CONTINUE64_CN 0x88
1883 #define CMD_RET_XRI_BUF64_CX 0x89
1884 #define CMD_ELS_REQUEST64_CR 0x8A
1885 #define CMD_ELS_REQUEST64_CX 0x8B
1886 #define CMD_ABORT_MXRI64_CN 0x8C
1887 #define CMD_RCV_ELS_REQ64_CX 0x8D
1888 #define CMD_XMIT_ELS_RSP64_CX 0x95
1889 #define CMD_XMIT_BLS_RSP64_CX 0x97
1890 #define CMD_FCP_IWRITE64_CR 0x98
1891 #define CMD_FCP_IWRITE64_CX 0x99
1892 #define CMD_FCP_IREAD64_CR 0x9A
1893 #define CMD_FCP_IREAD64_CX 0x9B
1894 #define CMD_FCP_ICMND64_CR 0x9C
1895 #define CMD_FCP_ICMND64_CX 0x9D
1896 #define CMD_FCP_TSEND64_CX 0x9F
1897 #define CMD_FCP_TRECEIVE64_CX 0xA1
1898 #define CMD_FCP_TRSP64_CX 0xA3
1899
1900 #define CMD_QUE_XRI64_CX 0xB3
1901 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
1902 #define CMD_IOCB_RCV_ELS64_CX 0xB7
1903 #define CMD_IOCB_RET_XRI64_CX 0xB9
1904 #define CMD_IOCB_RCV_CONT64_CX 0xBB
1905
1906 #define CMD_GEN_REQUEST64_CR 0xC2
1907 #define CMD_GEN_REQUEST64_CX 0xC3
1908
1909 /* Unhandled SLI-3 Commands */
1910 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1911 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1912 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1913 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1914 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1915 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1916 #define CMD_IOCB_RET_HBQE64_CN 0xCA
1917 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1918 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1919 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1920 #define CMD_IOCB_LOGENTRY_CN 0x94
1921 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1922
1923 /* Data Security SLI Commands */
1924 #define DSSCMD_IWRITE64_CR 0xF8
1925 #define DSSCMD_IWRITE64_CX 0xF9
1926 #define DSSCMD_IREAD64_CR 0xFA
1927 #define DSSCMD_IREAD64_CX 0xFB
1928
1929 #define CMD_MAX_IOCB_CMD 0xFB
1930 #define CMD_IOCB_MASK 0xff
1931
1932 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1933 iocb */
1934 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1935 /*
1936 * Define Status
1937 */
1938 #define MBX_SUCCESS 0
1939 #define MBXERR_NUM_RINGS 1
1940 #define MBXERR_NUM_IOCBS 2
1941 #define MBXERR_IOCBS_EXCEEDED 3
1942 #define MBXERR_BAD_RING_NUMBER 4
1943 #define MBXERR_MASK_ENTRIES_RANGE 5
1944 #define MBXERR_MASKS_EXCEEDED 6
1945 #define MBXERR_BAD_PROFILE 7
1946 #define MBXERR_BAD_DEF_CLASS 8
1947 #define MBXERR_BAD_MAX_RESPONDER 9
1948 #define MBXERR_BAD_MAX_ORIGINATOR 10
1949 #define MBXERR_RPI_REGISTERED 11
1950 #define MBXERR_RPI_FULL 12
1951 #define MBXERR_NO_RESOURCES 13
1952 #define MBXERR_BAD_RCV_LENGTH 14
1953 #define MBXERR_DMA_ERROR 15
1954 #define MBXERR_ERROR 16
1955 #define MBXERR_LINK_DOWN 0x33
1956 #define MBXERR_SEC_NO_PERMISSION 0xF02
1957 #define MBX_NOT_FINISHED 255
1958
1959 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1960 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1961
1962 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1963
1964 /*
1965 * return code Fail
1966 */
1967 #define FAILURE 1
1968
1969 /*
1970 * Begin Structure Definitions for Mailbox Commands
1971 */
1972
1973 typedef struct {
1974 #ifdef __BIG_ENDIAN_BITFIELD
1975 uint8_t tval;
1976 uint8_t tmask;
1977 uint8_t rval;
1978 uint8_t rmask;
1979 #else /* __LITTLE_ENDIAN_BITFIELD */
1980 uint8_t rmask;
1981 uint8_t rval;
1982 uint8_t tmask;
1983 uint8_t tval;
1984 #endif
1985 } RR_REG;
1986
1987 struct ulp_bde {
1988 uint32_t bdeAddress;
1989 #ifdef __BIG_ENDIAN_BITFIELD
1990 uint32_t bdeReserved:4;
1991 uint32_t bdeAddrHigh:4;
1992 uint32_t bdeSize:24;
1993 #else /* __LITTLE_ENDIAN_BITFIELD */
1994 uint32_t bdeSize:24;
1995 uint32_t bdeAddrHigh:4;
1996 uint32_t bdeReserved:4;
1997 #endif
1998 };
1999
2000 typedef struct ULP_BDL { /* SLI-2 */
2001 #ifdef __BIG_ENDIAN_BITFIELD
2002 uint32_t bdeFlags:8; /* BDL Flags */
2003 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
2004 #else /* __LITTLE_ENDIAN_BITFIELD */
2005 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
2006 uint32_t bdeFlags:8; /* BDL Flags */
2007 #endif
2008
2009 uint32_t addrLow; /* Address 0:31 */
2010 uint32_t addrHigh; /* Address 32:63 */
2011 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
2012 } ULP_BDL;
2013
2014 /*
2015 * BlockGuard Definitions
2016 */
2017
2018 enum lpfc_protgrp_type {
2019 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
2020 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
2021 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
2022 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
2023 };
2024
2025 /* PDE Descriptors */
2026 #define LPFC_PDE5_DESCRIPTOR 0x85
2027 #define LPFC_PDE6_DESCRIPTOR 0x86
2028 #define LPFC_PDE7_DESCRIPTOR 0x87
2029
2030 /* BlockGuard Opcodes */
2031 #define BG_OP_IN_NODIF_OUT_CRC 0x0
2032 #define BG_OP_IN_CRC_OUT_NODIF 0x1
2033 #define BG_OP_IN_NODIF_OUT_CSUM 0x2
2034 #define BG_OP_IN_CSUM_OUT_NODIF 0x3
2035 #define BG_OP_IN_CRC_OUT_CRC 0x4
2036 #define BG_OP_IN_CSUM_OUT_CSUM 0x5
2037 #define BG_OP_IN_CRC_OUT_CSUM 0x6
2038 #define BG_OP_IN_CSUM_OUT_CRC 0x7
2039 #define BG_OP_RAW_MODE 0x8
2040
2041 struct lpfc_pde5 {
2042 uint32_t word0;
2043 #define pde5_type_SHIFT 24
2044 #define pde5_type_MASK 0x000000ff
2045 #define pde5_type_WORD word0
2046 #define pde5_rsvd0_SHIFT 0
2047 #define pde5_rsvd0_MASK 0x00ffffff
2048 #define pde5_rsvd0_WORD word0
2049 uint32_t reftag; /* Reference Tag Value */
2050 uint32_t reftagtr; /* Reference Tag Translation Value */
2051 };
2052
2053 struct lpfc_pde6 {
2054 uint32_t word0;
2055 #define pde6_type_SHIFT 24
2056 #define pde6_type_MASK 0x000000ff
2057 #define pde6_type_WORD word0
2058 #define pde6_rsvd0_SHIFT 0
2059 #define pde6_rsvd0_MASK 0x00ffffff
2060 #define pde6_rsvd0_WORD word0
2061 uint32_t word1;
2062 #define pde6_rsvd1_SHIFT 26
2063 #define pde6_rsvd1_MASK 0x0000003f
2064 #define pde6_rsvd1_WORD word1
2065 #define pde6_na_SHIFT 25
2066 #define pde6_na_MASK 0x00000001
2067 #define pde6_na_WORD word1
2068 #define pde6_rsvd2_SHIFT 16
2069 #define pde6_rsvd2_MASK 0x000001FF
2070 #define pde6_rsvd2_WORD word1
2071 #define pde6_apptagtr_SHIFT 0
2072 #define pde6_apptagtr_MASK 0x0000ffff
2073 #define pde6_apptagtr_WORD word1
2074 uint32_t word2;
2075 #define pde6_optx_SHIFT 28
2076 #define pde6_optx_MASK 0x0000000f
2077 #define pde6_optx_WORD word2
2078 #define pde6_oprx_SHIFT 24
2079 #define pde6_oprx_MASK 0x0000000f
2080 #define pde6_oprx_WORD word2
2081 #define pde6_nr_SHIFT 23
2082 #define pde6_nr_MASK 0x00000001
2083 #define pde6_nr_WORD word2
2084 #define pde6_ce_SHIFT 22
2085 #define pde6_ce_MASK 0x00000001
2086 #define pde6_ce_WORD word2
2087 #define pde6_re_SHIFT 21
2088 #define pde6_re_MASK 0x00000001
2089 #define pde6_re_WORD word2
2090 #define pde6_ae_SHIFT 20
2091 #define pde6_ae_MASK 0x00000001
2092 #define pde6_ae_WORD word2
2093 #define pde6_ai_SHIFT 19
2094 #define pde6_ai_MASK 0x00000001
2095 #define pde6_ai_WORD word2
2096 #define pde6_bs_SHIFT 16
2097 #define pde6_bs_MASK 0x00000007
2098 #define pde6_bs_WORD word2
2099 #define pde6_apptagval_SHIFT 0
2100 #define pde6_apptagval_MASK 0x0000ffff
2101 #define pde6_apptagval_WORD word2
2102 };
2103
2104 struct lpfc_pde7 {
2105 uint32_t word0;
2106 #define pde7_type_SHIFT 24
2107 #define pde7_type_MASK 0x000000ff
2108 #define pde7_type_WORD word0
2109 #define pde7_rsvd0_SHIFT 0
2110 #define pde7_rsvd0_MASK 0x00ffffff
2111 #define pde7_rsvd0_WORD word0
2112 uint32_t addrHigh;
2113 uint32_t addrLow;
2114 };
2115
2116 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
2117
2118 typedef struct {
2119 #ifdef __BIG_ENDIAN_BITFIELD
2120 uint32_t rsvd2:25;
2121 uint32_t acknowledgment:1;
2122 uint32_t version:1;
2123 uint32_t erase_or_prog:1;
2124 uint32_t update_flash:1;
2125 uint32_t update_ram:1;
2126 uint32_t method:1;
2127 uint32_t load_cmplt:1;
2128 #else /* __LITTLE_ENDIAN_BITFIELD */
2129 uint32_t load_cmplt:1;
2130 uint32_t method:1;
2131 uint32_t update_ram:1;
2132 uint32_t update_flash:1;
2133 uint32_t erase_or_prog:1;
2134 uint32_t version:1;
2135 uint32_t acknowledgment:1;
2136 uint32_t rsvd2:25;
2137 #endif
2138
2139 uint32_t dl_to_adr_low;
2140 uint32_t dl_to_adr_high;
2141 uint32_t dl_len;
2142 union {
2143 uint32_t dl_from_mbx_offset;
2144 struct ulp_bde dl_from_bde;
2145 struct ulp_bde64 dl_from_bde64;
2146 } un;
2147
2148 } LOAD_SM_VAR;
2149
2150 /* Structure for MB Command READ_NVPARM (02) */
2151
2152 typedef struct {
2153 uint32_t rsvd1[3]; /* Read as all one's */
2154 uint32_t rsvd2; /* Read as all zero's */
2155 uint32_t portname[2]; /* N_PORT name */
2156 uint32_t nodename[2]; /* NODE name */
2157
2158 #ifdef __BIG_ENDIAN_BITFIELD
2159 uint32_t pref_DID:24;
2160 uint32_t hardAL_PA:8;
2161 #else /* __LITTLE_ENDIAN_BITFIELD */
2162 uint32_t hardAL_PA:8;
2163 uint32_t pref_DID:24;
2164 #endif
2165
2166 uint32_t rsvd3[21]; /* Read as all one's */
2167 } READ_NV_VAR;
2168
2169 /* Structure for MB Command WRITE_NVPARMS (03) */
2170
2171 typedef struct {
2172 uint32_t rsvd1[3]; /* Must be all one's */
2173 uint32_t rsvd2; /* Must be all zero's */
2174 uint32_t portname[2]; /* N_PORT name */
2175 uint32_t nodename[2]; /* NODE name */
2176
2177 #ifdef __BIG_ENDIAN_BITFIELD
2178 uint32_t pref_DID:24;
2179 uint32_t hardAL_PA:8;
2180 #else /* __LITTLE_ENDIAN_BITFIELD */
2181 uint32_t hardAL_PA:8;
2182 uint32_t pref_DID:24;
2183 #endif
2184
2185 uint32_t rsvd3[21]; /* Must be all one's */
2186 } WRITE_NV_VAR;
2187
2188 /* Structure for MB Command RUN_BIU_DIAG (04) */
2189 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2190
2191 typedef struct {
2192 uint32_t rsvd1;
2193 union {
2194 struct {
2195 struct ulp_bde xmit_bde;
2196 struct ulp_bde rcv_bde;
2197 } s1;
2198 struct {
2199 struct ulp_bde64 xmit_bde64;
2200 struct ulp_bde64 rcv_bde64;
2201 } s2;
2202 } un;
2203 } BIU_DIAG_VAR;
2204
2205 /* Structure for MB command READ_EVENT_LOG (0x38) */
2206 struct READ_EVENT_LOG_VAR {
2207 uint32_t word1;
2208 #define lpfc_event_log_SHIFT 29
2209 #define lpfc_event_log_MASK 0x00000001
2210 #define lpfc_event_log_WORD word1
2211 #define USE_MAILBOX_RESPONSE 1
2212 uint32_t offset;
2213 struct ulp_bde64 rcv_bde64;
2214 };
2215
2216 /* Structure for MB Command INIT_LINK (05) */
2217
2218 typedef struct {
2219 #ifdef __BIG_ENDIAN_BITFIELD
2220 uint32_t rsvd1:24;
2221 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2222 #else /* __LITTLE_ENDIAN_BITFIELD */
2223 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2224 uint32_t rsvd1:24;
2225 #endif
2226
2227 #ifdef __BIG_ENDIAN_BITFIELD
2228 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2229 uint8_t rsvd2;
2230 uint16_t link_flags;
2231 #else /* __LITTLE_ENDIAN_BITFIELD */
2232 uint16_t link_flags;
2233 uint8_t rsvd2;
2234 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2235 #endif
2236
2237 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
2238 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
2239 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
2240 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
2241 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
2242 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
2243 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
2244
2245 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
2246 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
2247 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
2248
2249 uint32_t link_speed;
2250 #define LINK_SPEED_AUTO 0x0 /* Auto selection */
2251 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
2252 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
2253 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
2254 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
2255 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
2256 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
2257 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */
2258
2259 } INIT_LINK_VAR;
2260
2261 /* Structure for MB Command DOWN_LINK (06) */
2262
2263 typedef struct {
2264 uint32_t rsvd1;
2265 } DOWN_LINK_VAR;
2266
2267 /* Structure for MB Command CONFIG_LINK (07) */
2268
2269 typedef struct {
2270 #ifdef __BIG_ENDIAN_BITFIELD
2271 uint32_t cr:1;
2272 uint32_t ci:1;
2273 uint32_t cr_delay:6;
2274 uint32_t cr_count:8;
2275 uint32_t rsvd1:8;
2276 uint32_t MaxBBC:8;
2277 #else /* __LITTLE_ENDIAN_BITFIELD */
2278 uint32_t MaxBBC:8;
2279 uint32_t rsvd1:8;
2280 uint32_t cr_count:8;
2281 uint32_t cr_delay:6;
2282 uint32_t ci:1;
2283 uint32_t cr:1;
2284 #endif
2285
2286 uint32_t myId;
2287 uint32_t rsvd2;
2288 uint32_t edtov;
2289 uint32_t arbtov;
2290 uint32_t ratov;
2291 uint32_t rttov;
2292 uint32_t altov;
2293 uint32_t crtov;
2294 uint32_t citov;
2295 #ifdef __BIG_ENDIAN_BITFIELD
2296 uint32_t rrq_enable:1;
2297 uint32_t rrq_immed:1;
2298 uint32_t rsvd4:29;
2299 uint32_t ack0_enable:1;
2300 #else /* __LITTLE_ENDIAN_BITFIELD */
2301 uint32_t ack0_enable:1;
2302 uint32_t rsvd4:29;
2303 uint32_t rrq_immed:1;
2304 uint32_t rrq_enable:1;
2305 #endif
2306 } CONFIG_LINK;
2307
2308 /* Structure for MB Command PART_SLIM (08)
2309 * will be removed since SLI1 is no longer supported!
2310 */
2311 typedef struct {
2312 #ifdef __BIG_ENDIAN_BITFIELD
2313 uint16_t offCiocb;
2314 uint16_t numCiocb;
2315 uint16_t offRiocb;
2316 uint16_t numRiocb;
2317 #else /* __LITTLE_ENDIAN_BITFIELD */
2318 uint16_t numCiocb;
2319 uint16_t offCiocb;
2320 uint16_t numRiocb;
2321 uint16_t offRiocb;
2322 #endif
2323 } RING_DEF;
2324
2325 typedef struct {
2326 #ifdef __BIG_ENDIAN_BITFIELD
2327 uint32_t unused1:24;
2328 uint32_t numRing:8;
2329 #else /* __LITTLE_ENDIAN_BITFIELD */
2330 uint32_t numRing:8;
2331 uint32_t unused1:24;
2332 #endif
2333
2334 RING_DEF ringdef[4];
2335 uint32_t hbainit;
2336 } PART_SLIM_VAR;
2337
2338 /* Structure for MB Command CONFIG_RING (09) */
2339
2340 typedef struct {
2341 #ifdef __BIG_ENDIAN_BITFIELD
2342 uint32_t unused2:6;
2343 uint32_t recvSeq:1;
2344 uint32_t recvNotify:1;
2345 uint32_t numMask:8;
2346 uint32_t profile:8;
2347 uint32_t unused1:4;
2348 uint32_t ring:4;
2349 #else /* __LITTLE_ENDIAN_BITFIELD */
2350 uint32_t ring:4;
2351 uint32_t unused1:4;
2352 uint32_t profile:8;
2353 uint32_t numMask:8;
2354 uint32_t recvNotify:1;
2355 uint32_t recvSeq:1;
2356 uint32_t unused2:6;
2357 #endif
2358
2359 #ifdef __BIG_ENDIAN_BITFIELD
2360 uint16_t maxRespXchg;
2361 uint16_t maxOrigXchg;
2362 #else /* __LITTLE_ENDIAN_BITFIELD */
2363 uint16_t maxOrigXchg;
2364 uint16_t maxRespXchg;
2365 #endif
2366
2367 RR_REG rrRegs[6];
2368 } CONFIG_RING_VAR;
2369
2370 /* Structure for MB Command RESET_RING (10) */
2371
2372 typedef struct {
2373 uint32_t ring_no;
2374 } RESET_RING_VAR;
2375
2376 /* Structure for MB Command READ_CONFIG (11) */
2377
2378 typedef struct {
2379 #ifdef __BIG_ENDIAN_BITFIELD
2380 uint32_t cr:1;
2381 uint32_t ci:1;
2382 uint32_t cr_delay:6;
2383 uint32_t cr_count:8;
2384 uint32_t InitBBC:8;
2385 uint32_t MaxBBC:8;
2386 #else /* __LITTLE_ENDIAN_BITFIELD */
2387 uint32_t MaxBBC:8;
2388 uint32_t InitBBC:8;
2389 uint32_t cr_count:8;
2390 uint32_t cr_delay:6;
2391 uint32_t ci:1;
2392 uint32_t cr:1;
2393 #endif
2394
2395 #ifdef __BIG_ENDIAN_BITFIELD
2396 uint32_t topology:8;
2397 uint32_t myDid:24;
2398 #else /* __LITTLE_ENDIAN_BITFIELD */
2399 uint32_t myDid:24;
2400 uint32_t topology:8;
2401 #endif
2402
2403 /* Defines for topology (defined previously) */
2404 #ifdef __BIG_ENDIAN_BITFIELD
2405 uint32_t AR:1;
2406 uint32_t IR:1;
2407 uint32_t rsvd1:29;
2408 uint32_t ack0:1;
2409 #else /* __LITTLE_ENDIAN_BITFIELD */
2410 uint32_t ack0:1;
2411 uint32_t rsvd1:29;
2412 uint32_t IR:1;
2413 uint32_t AR:1;
2414 #endif
2415
2416 uint32_t edtov;
2417 uint32_t arbtov;
2418 uint32_t ratov;
2419 uint32_t rttov;
2420 uint32_t altov;
2421 uint32_t lmt;
2422 #define LMT_RESERVED 0x000 /* Not used */
2423 #define LMT_1Gb 0x004
2424 #define LMT_2Gb 0x008
2425 #define LMT_4Gb 0x040
2426 #define LMT_8Gb 0x080
2427 #define LMT_10Gb 0x100
2428 #define LMT_16Gb 0x200
2429 #define LMT_32Gb 0x400
2430 uint32_t rsvd2;
2431 uint32_t rsvd3;
2432 uint32_t max_xri;
2433 uint32_t max_iocb;
2434 uint32_t max_rpi;
2435 uint32_t avail_xri;
2436 uint32_t avail_iocb;
2437 uint32_t avail_rpi;
2438 uint32_t max_vpi;
2439 uint32_t rsvd4;
2440 uint32_t rsvd5;
2441 uint32_t avail_vpi;
2442 } READ_CONFIG_VAR;
2443
2444 /* Structure for MB Command READ_RCONFIG (12) */
2445
2446 typedef struct {
2447 #ifdef __BIG_ENDIAN_BITFIELD
2448 uint32_t rsvd2:7;
2449 uint32_t recvNotify:1;
2450 uint32_t numMask:8;
2451 uint32_t profile:8;
2452 uint32_t rsvd1:4;
2453 uint32_t ring:4;
2454 #else /* __LITTLE_ENDIAN_BITFIELD */
2455 uint32_t ring:4;
2456 uint32_t rsvd1:4;
2457 uint32_t profile:8;
2458 uint32_t numMask:8;
2459 uint32_t recvNotify:1;
2460 uint32_t rsvd2:7;
2461 #endif
2462
2463 #ifdef __BIG_ENDIAN_BITFIELD
2464 uint16_t maxResp;
2465 uint16_t maxOrig;
2466 #else /* __LITTLE_ENDIAN_BITFIELD */
2467 uint16_t maxOrig;
2468 uint16_t maxResp;
2469 #endif
2470
2471 RR_REG rrRegs[6];
2472
2473 #ifdef __BIG_ENDIAN_BITFIELD
2474 uint16_t cmdRingOffset;
2475 uint16_t cmdEntryCnt;
2476 uint16_t rspRingOffset;
2477 uint16_t rspEntryCnt;
2478 uint16_t nextCmdOffset;
2479 uint16_t rsvd3;
2480 uint16_t nextRspOffset;
2481 uint16_t rsvd4;
2482 #else /* __LITTLE_ENDIAN_BITFIELD */
2483 uint16_t cmdEntryCnt;
2484 uint16_t cmdRingOffset;
2485 uint16_t rspEntryCnt;
2486 uint16_t rspRingOffset;
2487 uint16_t rsvd3;
2488 uint16_t nextCmdOffset;
2489 uint16_t rsvd4;
2490 uint16_t nextRspOffset;
2491 #endif
2492 } READ_RCONF_VAR;
2493
2494 /* Structure for MB Command READ_SPARM (13) */
2495 /* Structure for MB Command READ_SPARM64 (0x8D) */
2496
2497 typedef struct {
2498 uint32_t rsvd1;
2499 uint32_t rsvd2;
2500 union {
2501 struct ulp_bde sp; /* This BDE points to struct serv_parm
2502 structure */
2503 struct ulp_bde64 sp64;
2504 } un;
2505 #ifdef __BIG_ENDIAN_BITFIELD
2506 uint16_t rsvd3;
2507 uint16_t vpi;
2508 #else /* __LITTLE_ENDIAN_BITFIELD */
2509 uint16_t vpi;
2510 uint16_t rsvd3;
2511 #endif
2512 } READ_SPARM_VAR;
2513
2514 /* Structure for MB Command READ_STATUS (14) */
2515
2516 typedef struct {
2517 #ifdef __BIG_ENDIAN_BITFIELD
2518 uint32_t rsvd1:31;
2519 uint32_t clrCounters:1;
2520 uint16_t activeXriCnt;
2521 uint16_t activeRpiCnt;
2522 #else /* __LITTLE_ENDIAN_BITFIELD */
2523 uint32_t clrCounters:1;
2524 uint32_t rsvd1:31;
2525 uint16_t activeRpiCnt;
2526 uint16_t activeXriCnt;
2527 #endif
2528
2529 uint32_t xmitByteCnt;
2530 uint32_t rcvByteCnt;
2531 uint32_t xmitFrameCnt;
2532 uint32_t rcvFrameCnt;
2533 uint32_t xmitSeqCnt;
2534 uint32_t rcvSeqCnt;
2535 uint32_t totalOrigExchanges;
2536 uint32_t totalRespExchanges;
2537 uint32_t rcvPbsyCnt;
2538 uint32_t rcvFbsyCnt;
2539 } READ_STATUS_VAR;
2540
2541 /* Structure for MB Command READ_RPI (15) */
2542 /* Structure for MB Command READ_RPI64 (0x8F) */
2543
2544 typedef struct {
2545 #ifdef __BIG_ENDIAN_BITFIELD
2546 uint16_t nextRpi;
2547 uint16_t reqRpi;
2548 uint32_t rsvd2:8;
2549 uint32_t DID:24;
2550 #else /* __LITTLE_ENDIAN_BITFIELD */
2551 uint16_t reqRpi;
2552 uint16_t nextRpi;
2553 uint32_t DID:24;
2554 uint32_t rsvd2:8;
2555 #endif
2556
2557 union {
2558 struct ulp_bde sp;
2559 struct ulp_bde64 sp64;
2560 } un;
2561
2562 } READ_RPI_VAR;
2563
2564 /* Structure for MB Command READ_XRI (16) */
2565
2566 typedef struct {
2567 #ifdef __BIG_ENDIAN_BITFIELD
2568 uint16_t nextXri;
2569 uint16_t reqXri;
2570 uint16_t rsvd1;
2571 uint16_t rpi;
2572 uint32_t rsvd2:8;
2573 uint32_t DID:24;
2574 uint32_t rsvd3:8;
2575 uint32_t SID:24;
2576 uint32_t rsvd4;
2577 uint8_t seqId;
2578 uint8_t rsvd5;
2579 uint16_t seqCount;
2580 uint16_t oxId;
2581 uint16_t rxId;
2582 uint32_t rsvd6:30;
2583 uint32_t si:1;
2584 uint32_t exchOrig:1;
2585 #else /* __LITTLE_ENDIAN_BITFIELD */
2586 uint16_t reqXri;
2587 uint16_t nextXri;
2588 uint16_t rpi;
2589 uint16_t rsvd1;
2590 uint32_t DID:24;
2591 uint32_t rsvd2:8;
2592 uint32_t SID:24;
2593 uint32_t rsvd3:8;
2594 uint32_t rsvd4;
2595 uint16_t seqCount;
2596 uint8_t rsvd5;
2597 uint8_t seqId;
2598 uint16_t rxId;
2599 uint16_t oxId;
2600 uint32_t exchOrig:1;
2601 uint32_t si:1;
2602 uint32_t rsvd6:30;
2603 #endif
2604 } READ_XRI_VAR;
2605
2606 /* Structure for MB Command READ_REV (17) */
2607
2608 typedef struct {
2609 #ifdef __BIG_ENDIAN_BITFIELD
2610 uint32_t cv:1;
2611 uint32_t rr:1;
2612 uint32_t rsvd2:2;
2613 uint32_t v3req:1;
2614 uint32_t v3rsp:1;
2615 uint32_t rsvd1:25;
2616 uint32_t rv:1;
2617 #else /* __LITTLE_ENDIAN_BITFIELD */
2618 uint32_t rv:1;
2619 uint32_t rsvd1:25;
2620 uint32_t v3rsp:1;
2621 uint32_t v3req:1;
2622 uint32_t rsvd2:2;
2623 uint32_t rr:1;
2624 uint32_t cv:1;
2625 #endif
2626
2627 uint32_t biuRev;
2628 uint32_t smRev;
2629 union {
2630 uint32_t smFwRev;
2631 struct {
2632 #ifdef __BIG_ENDIAN_BITFIELD
2633 uint8_t ProgType;
2634 uint8_t ProgId;
2635 uint16_t ProgVer:4;
2636 uint16_t ProgRev:4;
2637 uint16_t ProgFixLvl:2;
2638 uint16_t ProgDistType:2;
2639 uint16_t DistCnt:4;
2640 #else /* __LITTLE_ENDIAN_BITFIELD */
2641 uint16_t DistCnt:4;
2642 uint16_t ProgDistType:2;
2643 uint16_t ProgFixLvl:2;
2644 uint16_t ProgRev:4;
2645 uint16_t ProgVer:4;
2646 uint8_t ProgId;
2647 uint8_t ProgType;
2648 #endif
2649
2650 } b;
2651 } un;
2652 uint32_t endecRev;
2653 #ifdef __BIG_ENDIAN_BITFIELD
2654 uint8_t feaLevelHigh;
2655 uint8_t feaLevelLow;
2656 uint8_t fcphHigh;
2657 uint8_t fcphLow;
2658 #else /* __LITTLE_ENDIAN_BITFIELD */
2659 uint8_t fcphLow;
2660 uint8_t fcphHigh;
2661 uint8_t feaLevelLow;
2662 uint8_t feaLevelHigh;
2663 #endif
2664
2665 uint32_t postKernRev;
2666 uint32_t opFwRev;
2667 uint8_t opFwName[16];
2668 uint32_t sli1FwRev;
2669 uint8_t sli1FwName[16];
2670 uint32_t sli2FwRev;
2671 uint8_t sli2FwName[16];
2672 uint32_t sli3Feat;
2673 uint32_t RandomData[6];
2674 } READ_REV_VAR;
2675
2676 /* Structure for MB Command READ_LINK_STAT (18) */
2677
2678 typedef struct {
2679 uint32_t word0;
2680
2681 #define lpfc_read_link_stat_rec_SHIFT 0
2682 #define lpfc_read_link_stat_rec_MASK 0x1
2683 #define lpfc_read_link_stat_rec_WORD word0
2684
2685 #define lpfc_read_link_stat_gec_SHIFT 1
2686 #define lpfc_read_link_stat_gec_MASK 0x1
2687 #define lpfc_read_link_stat_gec_WORD word0
2688
2689 #define lpfc_read_link_stat_w02oftow23of_SHIFT 2
2690 #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF
2691 #define lpfc_read_link_stat_w02oftow23of_WORD word0
2692
2693 #define lpfc_read_link_stat_rsvd_SHIFT 24
2694 #define lpfc_read_link_stat_rsvd_MASK 0x1F
2695 #define lpfc_read_link_stat_rsvd_WORD word0
2696
2697 #define lpfc_read_link_stat_gec2_SHIFT 29
2698 #define lpfc_read_link_stat_gec2_MASK 0x1
2699 #define lpfc_read_link_stat_gec2_WORD word0
2700
2701 #define lpfc_read_link_stat_clrc_SHIFT 30
2702 #define lpfc_read_link_stat_clrc_MASK 0x1
2703 #define lpfc_read_link_stat_clrc_WORD word0
2704
2705 #define lpfc_read_link_stat_clof_SHIFT 31
2706 #define lpfc_read_link_stat_clof_MASK 0x1
2707 #define lpfc_read_link_stat_clof_WORD word0
2708
2709 uint32_t linkFailureCnt;
2710 uint32_t lossSyncCnt;
2711 uint32_t lossSignalCnt;
2712 uint32_t primSeqErrCnt;
2713 uint32_t invalidXmitWord;
2714 uint32_t crcCnt;
2715 uint32_t primSeqTimeout;
2716 uint32_t elasticOverrun;
2717 uint32_t arbTimeout;
2718 uint32_t advRecBufCredit;
2719 uint32_t curRecBufCredit;
2720 uint32_t advTransBufCredit;
2721 uint32_t curTransBufCredit;
2722 uint32_t recEofCount;
2723 uint32_t recEofdtiCount;
2724 uint32_t recEofniCount;
2725 uint32_t recSofcount;
2726 uint32_t rsvd1;
2727 uint32_t rsvd2;
2728 uint32_t recDrpXriCount;
2729 uint32_t fecCorrBlkCount;
2730 uint32_t fecUncorrBlkCount;
2731 } READ_LNK_VAR;
2732
2733 /* Structure for MB Command REG_LOGIN (19) */
2734 /* Structure for MB Command REG_LOGIN64 (0x93) */
2735
2736 typedef struct {
2737 #ifdef __BIG_ENDIAN_BITFIELD
2738 uint16_t rsvd1;
2739 uint16_t rpi;
2740 uint32_t rsvd2:8;
2741 uint32_t did:24;
2742 #else /* __LITTLE_ENDIAN_BITFIELD */
2743 uint16_t rpi;
2744 uint16_t rsvd1;
2745 uint32_t did:24;
2746 uint32_t rsvd2:8;
2747 #endif
2748
2749 union {
2750 struct ulp_bde sp;
2751 struct ulp_bde64 sp64;
2752 } un;
2753
2754 #ifdef __BIG_ENDIAN_BITFIELD
2755 uint16_t rsvd6;
2756 uint16_t vpi;
2757 #else /* __LITTLE_ENDIAN_BITFIELD */
2758 uint16_t vpi;
2759 uint16_t rsvd6;
2760 #endif
2761
2762 } REG_LOGIN_VAR;
2763
2764 /* Word 30 contents for REG_LOGIN */
2765 typedef union {
2766 struct {
2767 #ifdef __BIG_ENDIAN_BITFIELD
2768 uint16_t rsvd1:12;
2769 uint16_t wd30_class:4;
2770 uint16_t xri;
2771 #else /* __LITTLE_ENDIAN_BITFIELD */
2772 uint16_t xri;
2773 uint16_t wd30_class:4;
2774 uint16_t rsvd1:12;
2775 #endif
2776 } f;
2777 uint32_t word;
2778 } REG_WD30;
2779
2780 /* Structure for MB Command UNREG_LOGIN (20) */
2781
2782 typedef struct {
2783 #ifdef __BIG_ENDIAN_BITFIELD
2784 uint16_t rsvd1;
2785 uint16_t rpi;
2786 uint32_t rsvd2;
2787 uint32_t rsvd3;
2788 uint32_t rsvd4;
2789 uint32_t rsvd5;
2790 uint16_t rsvd6;
2791 uint16_t vpi;
2792 #else /* __LITTLE_ENDIAN_BITFIELD */
2793 uint16_t rpi;
2794 uint16_t rsvd1;
2795 uint32_t rsvd2;
2796 uint32_t rsvd3;
2797 uint32_t rsvd4;
2798 uint32_t rsvd5;
2799 uint16_t vpi;
2800 uint16_t rsvd6;
2801 #endif
2802 } UNREG_LOGIN_VAR;
2803
2804 /* Structure for MB Command REG_VPI (0x96) */
2805 typedef struct {
2806 #ifdef __BIG_ENDIAN_BITFIELD
2807 uint32_t rsvd1;
2808 uint32_t rsvd2:7;
2809 uint32_t upd:1;
2810 uint32_t sid:24;
2811 uint32_t wwn[2];
2812 uint32_t rsvd5;
2813 uint16_t vfi;
2814 uint16_t vpi;
2815 #else /* __LITTLE_ENDIAN */
2816 uint32_t rsvd1;
2817 uint32_t sid:24;
2818 uint32_t upd:1;
2819 uint32_t rsvd2:7;
2820 uint32_t wwn[2];
2821 uint32_t rsvd5;
2822 uint16_t vpi;
2823 uint16_t vfi;
2824 #endif
2825 } REG_VPI_VAR;
2826
2827 /* Structure for MB Command UNREG_VPI (0x97) */
2828 typedef struct {
2829 uint32_t rsvd1;
2830 #ifdef __BIG_ENDIAN_BITFIELD
2831 uint16_t rsvd2;
2832 uint16_t sli4_vpi;
2833 #else /* __LITTLE_ENDIAN */
2834 uint16_t sli4_vpi;
2835 uint16_t rsvd2;
2836 #endif
2837 uint32_t rsvd3;
2838 uint32_t rsvd4;
2839 uint32_t rsvd5;
2840 #ifdef __BIG_ENDIAN_BITFIELD
2841 uint16_t rsvd6;
2842 uint16_t vpi;
2843 #else /* __LITTLE_ENDIAN */
2844 uint16_t vpi;
2845 uint16_t rsvd6;
2846 #endif
2847 } UNREG_VPI_VAR;
2848
2849 /* Structure for MB Command UNREG_D_ID (0x23) */
2850
2851 typedef struct {
2852 uint32_t did;
2853 uint32_t rsvd2;
2854 uint32_t rsvd3;
2855 uint32_t rsvd4;
2856 uint32_t rsvd5;
2857 #ifdef __BIG_ENDIAN_BITFIELD
2858 uint16_t rsvd6;
2859 uint16_t vpi;
2860 #else
2861 uint16_t vpi;
2862 uint16_t rsvd6;
2863 #endif
2864 } UNREG_D_ID_VAR;
2865
2866 /* Structure for MB Command READ_TOPOLOGY (0x95) */
2867 struct lpfc_mbx_read_top {
2868 uint32_t eventTag; /* Event tag */
2869 uint32_t word2;
2870 #define lpfc_mbx_read_top_fa_SHIFT 12
2871 #define lpfc_mbx_read_top_fa_MASK 0x00000001
2872 #define lpfc_mbx_read_top_fa_WORD word2
2873 #define lpfc_mbx_read_top_mm_SHIFT 11
2874 #define lpfc_mbx_read_top_mm_MASK 0x00000001
2875 #define lpfc_mbx_read_top_mm_WORD word2
2876 #define lpfc_mbx_read_top_pb_SHIFT 9
2877 #define lpfc_mbx_read_top_pb_MASK 0X00000001
2878 #define lpfc_mbx_read_top_pb_WORD word2
2879 #define lpfc_mbx_read_top_il_SHIFT 8
2880 #define lpfc_mbx_read_top_il_MASK 0x00000001
2881 #define lpfc_mbx_read_top_il_WORD word2
2882 #define lpfc_mbx_read_top_att_type_SHIFT 0
2883 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2884 #define lpfc_mbx_read_top_att_type_WORD word2
2885 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
2886 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */
2887 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
2888 uint32_t word3;
2889 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2890 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2891 #define lpfc_mbx_read_top_alpa_granted_WORD word3
2892 #define lpfc_mbx_read_top_lip_alps_SHIFT 16
2893 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2894 #define lpfc_mbx_read_top_lip_alps_WORD word3
2895 #define lpfc_mbx_read_top_lip_type_SHIFT 8
2896 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2897 #define lpfc_mbx_read_top_lip_type_WORD word3
2898 #define lpfc_mbx_read_top_topology_SHIFT 0
2899 #define lpfc_mbx_read_top_topology_MASK 0x000000FF
2900 #define lpfc_mbx_read_top_topology_WORD word3
2901 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2902 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2903 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
2904 /* store the LILP AL_PA position map into */
2905 struct ulp_bde64 lilpBde64;
2906 #define LPFC_ALPA_MAP_SIZE 128
2907 uint32_t word7;
2908 #define lpfc_mbx_read_top_ld_lu_SHIFT 31
2909 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2910 #define lpfc_mbx_read_top_ld_lu_WORD word7
2911 #define lpfc_mbx_read_top_ld_tf_SHIFT 30
2912 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2913 #define lpfc_mbx_read_top_ld_tf_WORD word7
2914 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2915 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2916 #define lpfc_mbx_read_top_ld_link_spd_WORD word7
2917 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2918 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2919 #define lpfc_mbx_read_top_ld_nl_port_WORD word7
2920 #define lpfc_mbx_read_top_ld_tx_SHIFT 2
2921 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2922 #define lpfc_mbx_read_top_ld_tx_WORD word7
2923 #define lpfc_mbx_read_top_ld_rx_SHIFT 0
2924 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2925 #define lpfc_mbx_read_top_ld_rx_WORD word7
2926 uint32_t word8;
2927 #define lpfc_mbx_read_top_lu_SHIFT 31
2928 #define lpfc_mbx_read_top_lu_MASK 0x00000001
2929 #define lpfc_mbx_read_top_lu_WORD word8
2930 #define lpfc_mbx_read_top_tf_SHIFT 30
2931 #define lpfc_mbx_read_top_tf_MASK 0x00000001
2932 #define lpfc_mbx_read_top_tf_WORD word8
2933 #define lpfc_mbx_read_top_link_spd_SHIFT 8
2934 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2935 #define lpfc_mbx_read_top_link_spd_WORD word8
2936 #define lpfc_mbx_read_top_nl_port_SHIFT 4
2937 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2938 #define lpfc_mbx_read_top_nl_port_WORD word8
2939 #define lpfc_mbx_read_top_tx_SHIFT 2
2940 #define lpfc_mbx_read_top_tx_MASK 0x00000003
2941 #define lpfc_mbx_read_top_tx_WORD word8
2942 #define lpfc_mbx_read_top_rx_SHIFT 0
2943 #define lpfc_mbx_read_top_rx_MASK 0x00000003
2944 #define lpfc_mbx_read_top_rx_WORD word8
2945 #define LPFC_LINK_SPEED_UNKNOWN 0x0
2946 #define LPFC_LINK_SPEED_1GHZ 0x04
2947 #define LPFC_LINK_SPEED_2GHZ 0x08
2948 #define LPFC_LINK_SPEED_4GHZ 0x10
2949 #define LPFC_LINK_SPEED_8GHZ 0x20
2950 #define LPFC_LINK_SPEED_10GHZ 0x40
2951 #define LPFC_LINK_SPEED_16GHZ 0x80
2952 #define LPFC_LINK_SPEED_32GHZ 0x90
2953 };
2954
2955 /* Structure for MB Command CLEAR_LA (22) */
2956
2957 typedef struct {
2958 uint32_t eventTag; /* Event tag */
2959 uint32_t rsvd1;
2960 } CLEAR_LA_VAR;
2961
2962 /* Structure for MB Command DUMP */
2963
2964 typedef struct {
2965 #ifdef __BIG_ENDIAN_BITFIELD
2966 uint32_t rsvd:25;
2967 uint32_t ra:1;
2968 uint32_t co:1;
2969 uint32_t cv:1;
2970 uint32_t type:4;
2971 uint32_t entry_index:16;
2972 uint32_t region_id:16;
2973 #else /* __LITTLE_ENDIAN_BITFIELD */
2974 uint32_t type:4;
2975 uint32_t cv:1;
2976 uint32_t co:1;
2977 uint32_t ra:1;
2978 uint32_t rsvd:25;
2979 uint32_t region_id:16;
2980 uint32_t entry_index:16;
2981 #endif
2982
2983 uint32_t sli4_length;
2984 uint32_t word_cnt;
2985 uint32_t resp_offset;
2986 } DUMP_VAR;
2987
2988 #define DMP_MEM_REG 0x1
2989 #define DMP_NV_PARAMS 0x2
2990 #define DMP_LMSD 0x3 /* Link Module Serial Data */
2991 #define DMP_WELL_KNOWN 0x4
2992
2993 #define DMP_REGION_VPD 0xe
2994 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2995 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2996 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2997
2998 #define DMP_REGION_VPORT 0x16 /* VPort info region */
2999 #define DMP_VPORT_REGION_SIZE 0x200
3000 #define DMP_MBOX_OFFSET_WORD 0x5
3001
3002 #define DMP_REGION_23 0x17 /* fcoe param and port state region */
3003 #define DMP_RGN23_SIZE 0x400
3004
3005 #define WAKE_UP_PARMS_REGION_ID 4
3006 #define WAKE_UP_PARMS_WORD_SIZE 15
3007
3008 struct vport_rec {
3009 uint8_t wwpn[8];
3010 uint8_t wwnn[8];
3011 };
3012
3013 #define VPORT_INFO_SIG 0x32324752
3014 #define VPORT_INFO_REV_MASK 0xff
3015 #define VPORT_INFO_REV 0x1
3016 #define MAX_STATIC_VPORT_COUNT 16
3017 struct static_vport_info {
3018 uint32_t signature;
3019 uint32_t rev;
3020 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
3021 uint32_t resvd[66];
3022 };
3023
3024 /* Option rom version structure */
3025 struct prog_id {
3026 #ifdef __BIG_ENDIAN_BITFIELD
3027 uint8_t type;
3028 uint8_t id;
3029 uint32_t ver:4; /* Major Version */
3030 uint32_t rev:4; /* Revision */
3031 uint32_t lev:2; /* Level */
3032 uint32_t dist:2; /* Dist Type */
3033 uint32_t num:4; /* number after dist type */
3034 #else /* __LITTLE_ENDIAN_BITFIELD */
3035 uint32_t num:4; /* number after dist type */
3036 uint32_t dist:2; /* Dist Type */
3037 uint32_t lev:2; /* Level */
3038 uint32_t rev:4; /* Revision */
3039 uint32_t ver:4; /* Major Version */
3040 uint8_t id;
3041 uint8_t type;
3042 #endif
3043 };
3044
3045 /* Structure for MB Command UPDATE_CFG (0x1B) */
3046
3047 struct update_cfg_var {
3048 #ifdef __BIG_ENDIAN_BITFIELD
3049 uint32_t rsvd2:16;
3050 uint32_t type:8;
3051 uint32_t rsvd:1;
3052 uint32_t ra:1;
3053 uint32_t co:1;
3054 uint32_t cv:1;
3055 uint32_t req:4;
3056 uint32_t entry_length:16;
3057 uint32_t region_id:16;
3058 #else /* __LITTLE_ENDIAN_BITFIELD */
3059 uint32_t req:4;
3060 uint32_t cv:1;
3061 uint32_t co:1;
3062 uint32_t ra:1;
3063 uint32_t rsvd:1;
3064 uint32_t type:8;
3065 uint32_t rsvd2:16;
3066 uint32_t region_id:16;
3067 uint32_t entry_length:16;
3068 #endif
3069
3070 uint32_t resp_info;
3071 uint32_t byte_cnt;
3072 uint32_t data_offset;
3073 };
3074
3075 struct hbq_mask {
3076 #ifdef __BIG_ENDIAN_BITFIELD
3077 uint8_t tmatch;
3078 uint8_t tmask;
3079 uint8_t rctlmatch;
3080 uint8_t rctlmask;
3081 #else /* __LITTLE_ENDIAN */
3082 uint8_t rctlmask;
3083 uint8_t rctlmatch;
3084 uint8_t tmask;
3085 uint8_t tmatch;
3086 #endif
3087 };
3088
3089
3090 /* Structure for MB Command CONFIG_HBQ (7c) */
3091
3092 struct config_hbq_var {
3093 #ifdef __BIG_ENDIAN_BITFIELD
3094 uint32_t rsvd1 :7;
3095 uint32_t recvNotify :1; /* Receive Notification */
3096 uint32_t numMask :8; /* # Mask Entries */
3097 uint32_t profile :8; /* Selection Profile */
3098 uint32_t rsvd2 :8;
3099 #else /* __LITTLE_ENDIAN */
3100 uint32_t rsvd2 :8;
3101 uint32_t profile :8; /* Selection Profile */
3102 uint32_t numMask :8; /* # Mask Entries */
3103 uint32_t recvNotify :1; /* Receive Notification */
3104 uint32_t rsvd1 :7;
3105 #endif
3106
3107 #ifdef __BIG_ENDIAN_BITFIELD
3108 uint32_t hbqId :16;
3109 uint32_t rsvd3 :12;
3110 uint32_t ringMask :4;
3111 #else /* __LITTLE_ENDIAN */
3112 uint32_t ringMask :4;
3113 uint32_t rsvd3 :12;
3114 uint32_t hbqId :16;
3115 #endif
3116
3117 #ifdef __BIG_ENDIAN_BITFIELD
3118 uint32_t entry_count :16;
3119 uint32_t rsvd4 :8;
3120 uint32_t headerLen :8;
3121 #else /* __LITTLE_ENDIAN */
3122 uint32_t headerLen :8;
3123 uint32_t rsvd4 :8;
3124 uint32_t entry_count :16;
3125 #endif
3126
3127 uint32_t hbqaddrLow;
3128 uint32_t hbqaddrHigh;
3129
3130 #ifdef __BIG_ENDIAN_BITFIELD
3131 uint32_t rsvd5 :31;
3132 uint32_t logEntry :1;
3133 #else /* __LITTLE_ENDIAN */
3134 uint32_t logEntry :1;
3135 uint32_t rsvd5 :31;
3136 #endif
3137
3138 uint32_t rsvd6; /* w7 */
3139 uint32_t rsvd7; /* w8 */
3140 uint32_t rsvd8; /* w9 */
3141
3142 struct hbq_mask hbqMasks[6];
3143
3144
3145 union {
3146 uint32_t allprofiles[12];
3147
3148 struct {
3149 #ifdef __BIG_ENDIAN_BITFIELD
3150 uint32_t seqlenoff :16;
3151 uint32_t maxlen :16;
3152 #else /* __LITTLE_ENDIAN */
3153 uint32_t maxlen :16;
3154 uint32_t seqlenoff :16;
3155 #endif
3156 #ifdef __BIG_ENDIAN_BITFIELD
3157 uint32_t rsvd1 :28;
3158 uint32_t seqlenbcnt :4;
3159 #else /* __LITTLE_ENDIAN */
3160 uint32_t seqlenbcnt :4;
3161 uint32_t rsvd1 :28;
3162 #endif
3163 uint32_t rsvd[10];
3164 } profile2;
3165
3166 struct {
3167 #ifdef __BIG_ENDIAN_BITFIELD
3168 uint32_t seqlenoff :16;
3169 uint32_t maxlen :16;
3170 #else /* __LITTLE_ENDIAN */
3171 uint32_t maxlen :16;
3172 uint32_t seqlenoff :16;
3173 #endif
3174 #ifdef __BIG_ENDIAN_BITFIELD
3175 uint32_t cmdcodeoff :28;
3176 uint32_t rsvd1 :12;
3177 uint32_t seqlenbcnt :4;
3178 #else /* __LITTLE_ENDIAN */
3179 uint32_t seqlenbcnt :4;
3180 uint32_t rsvd1 :12;
3181 uint32_t cmdcodeoff :28;
3182 #endif
3183 uint32_t cmdmatch[8];
3184
3185 uint32_t rsvd[2];
3186 } profile3;
3187
3188 struct {
3189 #ifdef __BIG_ENDIAN_BITFIELD
3190 uint32_t seqlenoff :16;
3191 uint32_t maxlen :16;
3192 #else /* __LITTLE_ENDIAN */
3193 uint32_t maxlen :16;
3194 uint32_t seqlenoff :16;
3195 #endif
3196 #ifdef __BIG_ENDIAN_BITFIELD
3197 uint32_t cmdcodeoff :28;
3198 uint32_t rsvd1 :12;
3199 uint32_t seqlenbcnt :4;
3200 #else /* __LITTLE_ENDIAN */
3201 uint32_t seqlenbcnt :4;
3202 uint32_t rsvd1 :12;
3203 uint32_t cmdcodeoff :28;
3204 #endif
3205 uint32_t cmdmatch[8];
3206
3207 uint32_t rsvd[2];
3208 } profile5;
3209
3210 } profiles;
3211
3212 };
3213
3214
3215
3216 /* Structure for MB Command CONFIG_PORT (0x88) */
3217 typedef struct {
3218 #ifdef __BIG_ENDIAN_BITFIELD
3219 uint32_t cBE : 1;
3220 uint32_t cET : 1;
3221 uint32_t cHpcb : 1;
3222 uint32_t cMA : 1;
3223 uint32_t sli_mode : 4;
3224 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3225 * config block */
3226 #else /* __LITTLE_ENDIAN */
3227 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3228 * config block */
3229 uint32_t sli_mode : 4;
3230 uint32_t cMA : 1;
3231 uint32_t cHpcb : 1;
3232 uint32_t cET : 1;
3233 uint32_t cBE : 1;
3234 #endif
3235
3236 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
3237 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
3238 uint32_t hbainit[5];
3239 #ifdef __BIG_ENDIAN_BITFIELD
3240 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3241 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3242 #else /* __LITTLE_ENDIAN */
3243 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3244 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3245 #endif
3246
3247 #ifdef __BIG_ENDIAN_BITFIELD
3248 uint32_t rsvd1 : 19; /* Reserved */
3249 uint32_t cdss : 1; /* Configure Data Security SLI */
3250 uint32_t casabt : 1; /* Configure async abts status notice */
3251 uint32_t rsvd2 : 2; /* Reserved */
3252 uint32_t cbg : 1; /* Configure BlockGuard */
3253 uint32_t cmv : 1; /* Configure Max VPIs */
3254 uint32_t ccrp : 1; /* Config Command Ring Polling */
3255 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3256 uint32_t chbs : 1; /* Cofigure Host Backing store */
3257 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3258 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3259 uint32_t cmx : 1; /* Configure Max XRIs */
3260 uint32_t cmr : 1; /* Configure Max RPIs */
3261 #else /* __LITTLE_ENDIAN */
3262 uint32_t cmr : 1; /* Configure Max RPIs */
3263 uint32_t cmx : 1; /* Configure Max XRIs */
3264 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3265 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3266 uint32_t chbs : 1; /* Cofigure Host Backing store */
3267 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3268 uint32_t ccrp : 1; /* Config Command Ring Polling */
3269 uint32_t cmv : 1; /* Configure Max VPIs */
3270 uint32_t cbg : 1; /* Configure BlockGuard */
3271 uint32_t rsvd2 : 2; /* Reserved */
3272 uint32_t casabt : 1; /* Configure async abts status notice */
3273 uint32_t cdss : 1; /* Configure Data Security SLI */
3274 uint32_t rsvd1 : 19; /* Reserved */
3275 #endif
3276 #ifdef __BIG_ENDIAN_BITFIELD
3277 uint32_t rsvd3 : 19; /* Reserved */
3278 uint32_t gdss : 1; /* Configure Data Security SLI */
3279 uint32_t gasabt : 1; /* Grant async abts status notice */
3280 uint32_t rsvd4 : 2; /* Reserved */
3281 uint32_t gbg : 1; /* Grant BlockGuard */
3282 uint32_t gmv : 1; /* Grant Max VPIs */
3283 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3284 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3285 uint32_t ghbs : 1; /* Grant Host Backing Store */
3286 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3287 uint32_t gerbm : 1; /* Grant ERBM Request */
3288 uint32_t gmx : 1; /* Grant Max XRIs */
3289 uint32_t gmr : 1; /* Grant Max RPIs */
3290 #else /* __LITTLE_ENDIAN */
3291 uint32_t gmr : 1; /* Grant Max RPIs */
3292 uint32_t gmx : 1; /* Grant Max XRIs */
3293 uint32_t gerbm : 1; /* Grant ERBM Request */
3294 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3295 uint32_t ghbs : 1; /* Grant Host Backing Store */
3296 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3297 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3298 uint32_t gmv : 1; /* Grant Max VPIs */
3299 uint32_t gbg : 1; /* Grant BlockGuard */
3300 uint32_t rsvd4 : 2; /* Reserved */
3301 uint32_t gasabt : 1; /* Grant async abts status notice */
3302 uint32_t gdss : 1; /* Configure Data Security SLI */
3303 uint32_t rsvd3 : 19; /* Reserved */
3304 #endif
3305
3306 #ifdef __BIG_ENDIAN_BITFIELD
3307 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3308 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3309 #else /* __LITTLE_ENDIAN */
3310 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3311 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3312 #endif
3313
3314 #ifdef __BIG_ENDIAN_BITFIELD
3315 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3316 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3317 #else /* __LITTLE_ENDIAN */
3318 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3319 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3320 #endif
3321
3322 uint32_t rsvd6; /* Reserved */
3323
3324 #ifdef __BIG_ENDIAN_BITFIELD
3325 uint32_t fips_rev : 3; /* FIPS Spec Revision */
3326 uint32_t fips_level : 4; /* FIPS Level */
3327 uint32_t sec_err : 9; /* security crypto error */
3328 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3329 #else /* __LITTLE_ENDIAN */
3330 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3331 uint32_t sec_err : 9; /* security crypto error */
3332 uint32_t fips_level : 4; /* FIPS Level */
3333 uint32_t fips_rev : 3; /* FIPS Spec Revision */
3334 #endif
3335
3336 } CONFIG_PORT_VAR;
3337
3338 /* Structure for MB Command CONFIG_MSI (0x30) */
3339 struct config_msi_var {
3340 #ifdef __BIG_ENDIAN_BITFIELD
3341 uint32_t dfltMsgNum:8; /* Default message number */
3342 uint32_t rsvd1:11; /* Reserved */
3343 uint32_t NID:5; /* Number of secondary attention IDs */
3344 uint32_t rsvd2:5; /* Reserved */
3345 uint32_t dfltPresent:1; /* Default message number present */
3346 uint32_t addFlag:1; /* Add association flag */
3347 uint32_t reportFlag:1; /* Report association flag */
3348 #else /* __LITTLE_ENDIAN_BITFIELD */
3349 uint32_t reportFlag:1; /* Report association flag */
3350 uint32_t addFlag:1; /* Add association flag */
3351 uint32_t dfltPresent:1; /* Default message number present */
3352 uint32_t rsvd2:5; /* Reserved */
3353 uint32_t NID:5; /* Number of secondary attention IDs */
3354 uint32_t rsvd1:11; /* Reserved */
3355 uint32_t dfltMsgNum:8; /* Default message number */
3356 #endif
3357 uint32_t attentionConditions[2];
3358 uint8_t attentionId[16];
3359 uint8_t messageNumberByHA[64];
3360 uint8_t messageNumberByID[16];
3361 uint32_t autoClearHA[2];
3362 #ifdef __BIG_ENDIAN_BITFIELD
3363 uint32_t rsvd3:16;
3364 uint32_t autoClearID:16;
3365 #else /* __LITTLE_ENDIAN_BITFIELD */
3366 uint32_t autoClearID:16;
3367 uint32_t rsvd3:16;
3368 #endif
3369 uint32_t rsvd4;
3370 };
3371
3372 /* SLI-2 Port Control Block */
3373
3374 /* SLIM POINTER */
3375 #define SLIMOFF 0x30 /* WORD */
3376
3377 typedef struct _SLI2_RDSC {
3378 uint32_t cmdEntries;
3379 uint32_t cmdAddrLow;
3380 uint32_t cmdAddrHigh;
3381
3382 uint32_t rspEntries;
3383 uint32_t rspAddrLow;
3384 uint32_t rspAddrHigh;
3385 } SLI2_RDSC;
3386
3387 typedef struct _PCB {
3388 #ifdef __BIG_ENDIAN_BITFIELD
3389 uint32_t type:8;
3390 #define TYPE_NATIVE_SLI2 0x01
3391 uint32_t feature:8;
3392 #define FEATURE_INITIAL_SLI2 0x01
3393 uint32_t rsvd:12;
3394 uint32_t maxRing:4;
3395 #else /* __LITTLE_ENDIAN_BITFIELD */
3396 uint32_t maxRing:4;
3397 uint32_t rsvd:12;
3398 uint32_t feature:8;
3399 #define FEATURE_INITIAL_SLI2 0x01
3400 uint32_t type:8;
3401 #define TYPE_NATIVE_SLI2 0x01
3402 #endif
3403
3404 uint32_t mailBoxSize;
3405 uint32_t mbAddrLow;
3406 uint32_t mbAddrHigh;
3407
3408 uint32_t hgpAddrLow;
3409 uint32_t hgpAddrHigh;
3410
3411 uint32_t pgpAddrLow;
3412 uint32_t pgpAddrHigh;
3413 SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3414 } PCB_t;
3415
3416 /* NEW_FEATURE */
3417 typedef struct {
3418 #ifdef __BIG_ENDIAN_BITFIELD
3419 uint32_t rsvd0:27;
3420 uint32_t discardFarp:1;
3421 uint32_t IPEnable:1;
3422 uint32_t nodeName:1;
3423 uint32_t portName:1;
3424 uint32_t filterEnable:1;
3425 #else /* __LITTLE_ENDIAN_BITFIELD */
3426 uint32_t filterEnable:1;
3427 uint32_t portName:1;
3428 uint32_t nodeName:1;
3429 uint32_t IPEnable:1;
3430 uint32_t discardFarp:1;
3431 uint32_t rsvd:27;
3432 #endif
3433
3434 uint8_t portname[8]; /* Used to be struct lpfc_name */
3435 uint8_t nodename[8];
3436 uint32_t rsvd1;
3437 uint32_t rsvd2;
3438 uint32_t rsvd3;
3439 uint32_t IPAddress;
3440 } CONFIG_FARP_VAR;
3441
3442 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3443
3444 typedef struct {
3445 #ifdef __BIG_ENDIAN_BITFIELD
3446 uint32_t rsvd:30;
3447 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3448 #else /* __LITTLE_ENDIAN */
3449 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3450 uint32_t rsvd:30;
3451 #endif
3452 } ASYNCEVT_ENABLE_VAR;
3453
3454 /* Union of all Mailbox Command types */
3455 #define MAILBOX_CMD_WSIZE 32
3456 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3457 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3458 #define MAILBOX_EXT_WSIZE 512
3459 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3460 #define MAILBOX_HBA_EXT_OFFSET 0x100
3461 /* max mbox xmit size is a page size for sysfs IO operations */
3462 #define MAILBOX_SYSFS_MAX 4096
3463
3464 typedef union {
3465 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3466 * feature/max ring number
3467 */
3468 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3469 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3470 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
3471 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3472 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
3473 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
3474 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3475 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
3476 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3477 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3478 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3479 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3480 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3481 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
3482 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3483 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3484 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3485 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
3486 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3487 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
3488 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
3489 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3490 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3491 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3492 * NEW_FEATURE
3493 */
3494 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3495 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3496 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3497 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3498 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3499 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3500 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3501 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3502 * (READ_EVENT_LOG)
3503 */
3504 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
3505 } MAILVARIANTS;
3506
3507 /*
3508 * SLI-2 specific structures
3509 */
3510
3511 struct lpfc_hgp {
3512 __le32 cmdPutInx;
3513 __le32 rspGetInx;
3514 };
3515
3516 struct lpfc_pgp {
3517 __le32 cmdGetInx;
3518 __le32 rspPutInx;
3519 };
3520
3521 struct sli2_desc {
3522 uint32_t unused1[16];
3523 struct lpfc_hgp host[MAX_SLI3_RINGS];
3524 struct lpfc_pgp port[MAX_SLI3_RINGS];
3525 };
3526
3527 struct sli3_desc {
3528 struct lpfc_hgp host[MAX_SLI3_RINGS];
3529 uint32_t reserved[8];
3530 uint32_t hbq_put[16];
3531 };
3532
3533 struct sli3_pgp {
3534 struct lpfc_pgp port[MAX_SLI3_RINGS];
3535 uint32_t hbq_get[16];
3536 };
3537
3538 union sli_var {
3539 struct sli2_desc s2;
3540 struct sli3_desc s3;
3541 struct sli3_pgp s3_pgp;
3542 };
3543
3544 typedef struct {
3545 #ifdef __BIG_ENDIAN_BITFIELD
3546 uint16_t mbxStatus;
3547 uint8_t mbxCommand;
3548 uint8_t mbxReserved:6;
3549 uint8_t mbxHc:1;
3550 uint8_t mbxOwner:1; /* Low order bit first word */
3551 #else /* __LITTLE_ENDIAN_BITFIELD */
3552 uint8_t mbxOwner:1; /* Low order bit first word */
3553 uint8_t mbxHc:1;
3554 uint8_t mbxReserved:6;
3555 uint8_t mbxCommand;
3556 uint16_t mbxStatus;
3557 #endif
3558
3559 MAILVARIANTS un;
3560 union sli_var us;
3561 } MAILBOX_t;
3562
3563 /*
3564 * Begin Structure Definitions for IOCB Commands
3565 */
3566
3567 typedef struct {
3568 #ifdef __BIG_ENDIAN_BITFIELD
3569 uint8_t statAction;
3570 uint8_t statRsn;
3571 uint8_t statBaExp;
3572 uint8_t statLocalError;
3573 #else /* __LITTLE_ENDIAN_BITFIELD */
3574 uint8_t statLocalError;
3575 uint8_t statBaExp;
3576 uint8_t statRsn;
3577 uint8_t statAction;
3578 #endif
3579 /* statRsn P/F_RJT reason codes */
3580 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3581 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3582 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3583 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3584 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3585 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3586 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3587 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3588 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3589 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3590 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3591 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3592 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3593 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3594 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3595 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
3596 #define RJT_XCHG_ERR 0x11 /* Exchange error */
3597 #define RJT_PROT_ERR 0x12 /* Protocol error */
3598 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3599 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3600 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3601 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3602 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3603 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3604 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3605 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3606
3607 #define IOERR_SUCCESS 0x00 /* statLocalError */
3608 #define IOERR_MISSING_CONTINUE 0x01
3609 #define IOERR_SEQUENCE_TIMEOUT 0x02
3610 #define IOERR_INTERNAL_ERROR 0x03
3611 #define IOERR_INVALID_RPI 0x04
3612 #define IOERR_NO_XRI 0x05
3613 #define IOERR_ILLEGAL_COMMAND 0x06
3614 #define IOERR_XCHG_DROPPED 0x07
3615 #define IOERR_ILLEGAL_FIELD 0x08
3616 #define IOERR_BAD_CONTINUE 0x09
3617 #define IOERR_TOO_MANY_BUFFERS 0x0A
3618 #define IOERR_RCV_BUFFER_WAITING 0x0B
3619 #define IOERR_NO_CONNECTION 0x0C
3620 #define IOERR_TX_DMA_FAILED 0x0D
3621 #define IOERR_RX_DMA_FAILED 0x0E
3622 #define IOERR_ILLEGAL_FRAME 0x0F
3623 #define IOERR_EXTRA_DATA 0x10
3624 #define IOERR_NO_RESOURCES 0x11
3625 #define IOERR_RESERVED 0x12
3626 #define IOERR_ILLEGAL_LENGTH 0x13
3627 #define IOERR_UNSUPPORTED_FEATURE 0x14
3628 #define IOERR_ABORT_IN_PROGRESS 0x15
3629 #define IOERR_ABORT_REQUESTED 0x16
3630 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3631 #define IOERR_LOOP_OPEN_FAILURE 0x18
3632 #define IOERR_RING_RESET 0x19
3633 #define IOERR_LINK_DOWN 0x1A
3634 #define IOERR_CORRUPTED_DATA 0x1B
3635 #define IOERR_CORRUPTED_RPI 0x1C
3636 #define IOERR_OUT_OF_ORDER_DATA 0x1D
3637 #define IOERR_OUT_OF_ORDER_ACK 0x1E
3638 #define IOERR_DUP_FRAME 0x1F
3639 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3640 #define IOERR_BAD_HOST_ADDRESS 0x21
3641 #define IOERR_RCV_HDRBUF_WAITING 0x22
3642 #define IOERR_MISSING_HDR_BUFFER 0x23
3643 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3644 #define IOERR_ABORTMULT_REQUESTED 0x25
3645 #define IOERR_BUFFER_SHORTAGE 0x28
3646 #define IOERR_DEFAULT 0x29
3647 #define IOERR_CNT 0x2A
3648 #define IOERR_SLER_FAILURE 0x46
3649 #define IOERR_SLER_CMD_RCV_FAILURE 0x47
3650 #define IOERR_SLER_REC_RJT_ERR 0x48
3651 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3652 #define IOERR_SLER_SRR_RJT_ERR 0x4A
3653 #define IOERR_SLER_RRQ_RJT_ERR 0x4C
3654 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3655 #define IOERR_SLER_ABTS_ERR 0x4E
3656 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3657 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3658 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3659 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3660 #define IOERR_DRVR_MASK 0x100
3661 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3662 #define IOERR_SLI_BRESET 0x102
3663 #define IOERR_SLI_ABORTED 0x103
3664 #define IOERR_PARAM_MASK 0x1ff
3665 } PARM_ERR;
3666
3667 typedef union {
3668 struct {
3669 #ifdef __BIG_ENDIAN_BITFIELD
3670 uint8_t Rctl; /* R_CTL field */
3671 uint8_t Type; /* TYPE field */
3672 uint8_t Dfctl; /* DF_CTL field */
3673 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3674 #else /* __LITTLE_ENDIAN_BITFIELD */
3675 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3676 uint8_t Dfctl; /* DF_CTL field */
3677 uint8_t Type; /* TYPE field */
3678 uint8_t Rctl; /* R_CTL field */
3679 #endif
3680
3681 #define BC 0x02 /* Broadcast Received - Fctl */
3682 #define SI 0x04 /* Sequence Initiative */
3683 #define LA 0x08 /* Ignore Link Attention state */
3684 #define LS 0x80 /* Last Sequence */
3685 } hcsw;
3686 uint32_t reserved;
3687 } WORD5;
3688
3689 /* IOCB Command template for a generic response */
3690 typedef struct {
3691 uint32_t reserved[4];
3692 PARM_ERR perr;
3693 } GENERIC_RSP;
3694
3695 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3696 typedef struct {
3697 struct ulp_bde xrsqbde[2];
3698 uint32_t xrsqRo; /* Starting Relative Offset */
3699 WORD5 w5; /* Header control/status word */
3700 } XR_SEQ_FIELDS;
3701
3702 /* IOCB Command template for ELS_REQUEST */
3703 typedef struct {
3704 struct ulp_bde elsReq;
3705 struct ulp_bde elsRsp;
3706
3707 #ifdef __BIG_ENDIAN_BITFIELD
3708 uint32_t word4Rsvd:7;
3709 uint32_t fl:1;
3710 uint32_t myID:24;
3711 uint32_t word5Rsvd:8;
3712 uint32_t remoteID:24;
3713 #else /* __LITTLE_ENDIAN_BITFIELD */
3714 uint32_t myID:24;
3715 uint32_t fl:1;
3716 uint32_t word4Rsvd:7;
3717 uint32_t remoteID:24;
3718 uint32_t word5Rsvd:8;
3719 #endif
3720 } ELS_REQUEST;
3721
3722 /* IOCB Command template for RCV_ELS_REQ */
3723 typedef struct {
3724 struct ulp_bde elsReq[2];
3725 uint32_t parmRo;
3726
3727 #ifdef __BIG_ENDIAN_BITFIELD
3728 uint32_t word5Rsvd:8;
3729 uint32_t remoteID:24;
3730 #else /* __LITTLE_ENDIAN_BITFIELD */
3731 uint32_t remoteID:24;
3732 uint32_t word5Rsvd:8;
3733 #endif
3734 } RCV_ELS_REQ;
3735
3736 /* IOCB Command template for ABORT / CLOSE_XRI */
3737 typedef struct {
3738 uint32_t rsvd[3];
3739 uint32_t abortType;
3740 #define ABORT_TYPE_ABTX 0x00000000
3741 #define ABORT_TYPE_ABTS 0x00000001
3742 uint32_t parm;
3743 #ifdef __BIG_ENDIAN_BITFIELD
3744 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3745 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3746 #else /* __LITTLE_ENDIAN_BITFIELD */
3747 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3748 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3749 #endif
3750 } AC_XRI;
3751
3752 /* IOCB Command template for ABORT_MXRI64 */
3753 typedef struct {
3754 uint32_t rsvd[3];
3755 uint32_t abortType;
3756 uint32_t parm;
3757 uint32_t iotag32;
3758 } A_MXRI64;
3759
3760 /* IOCB Command template for GET_RPI */
3761 typedef struct {
3762 uint32_t rsvd[4];
3763 uint32_t parmRo;
3764 #ifdef __BIG_ENDIAN_BITFIELD
3765 uint32_t word5Rsvd:8;
3766 uint32_t remoteID:24;
3767 #else /* __LITTLE_ENDIAN_BITFIELD */
3768 uint32_t remoteID:24;
3769 uint32_t word5Rsvd:8;
3770 #endif
3771 } GET_RPI;
3772
3773 /* IOCB Command template for all FCP Initiator commands */
3774 typedef struct {
3775 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3776 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3777 uint32_t fcpi_parm;
3778 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3779 } FCPI_FIELDS;
3780
3781 /* IOCB Command template for all FCP Target commands */
3782 typedef struct {
3783 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3784 uint32_t fcpt_Offset;
3785 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3786 } FCPT_FIELDS;
3787
3788 /* SLI-2 IOCB structure definitions */
3789
3790 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3791 typedef struct {
3792 ULP_BDL bdl;
3793 uint32_t xrsqRo; /* Starting Relative Offset */
3794 WORD5 w5; /* Header control/status word */
3795 } XMT_SEQ_FIELDS64;
3796
3797 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3798 #define xmit_els_remoteID xrsqRo
3799
3800 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3801 typedef struct {
3802 struct ulp_bde64 rcvBde;
3803 uint32_t rsvd1;
3804 uint32_t xrsqRo; /* Starting Relative Offset */
3805 WORD5 w5; /* Header control/status word */
3806 } RCV_SEQ_FIELDS64;
3807
3808 /* IOCB Command template for ELS_REQUEST64 */
3809 typedef struct {
3810 ULP_BDL bdl;
3811 #ifdef __BIG_ENDIAN_BITFIELD
3812 uint32_t word4Rsvd:7;
3813 uint32_t fl:1;
3814 uint32_t myID:24;
3815 uint32_t word5Rsvd:8;
3816 uint32_t remoteID:24;
3817 #else /* __LITTLE_ENDIAN_BITFIELD */
3818 uint32_t myID:24;
3819 uint32_t fl:1;
3820 uint32_t word4Rsvd:7;
3821 uint32_t remoteID:24;
3822 uint32_t word5Rsvd:8;
3823 #endif
3824 } ELS_REQUEST64;
3825
3826 /* IOCB Command template for GEN_REQUEST64 */
3827 typedef struct {
3828 ULP_BDL bdl;
3829 uint32_t xrsqRo; /* Starting Relative Offset */
3830 WORD5 w5; /* Header control/status word */
3831 } GEN_REQUEST64;
3832
3833 /* IOCB Command template for RCV_ELS_REQ64 */
3834 typedef struct {
3835 struct ulp_bde64 elsReq;
3836 uint32_t rcvd1;
3837 uint32_t parmRo;
3838
3839 #ifdef __BIG_ENDIAN_BITFIELD
3840 uint32_t word5Rsvd:8;
3841 uint32_t remoteID:24;
3842 #else /* __LITTLE_ENDIAN_BITFIELD */
3843 uint32_t remoteID:24;
3844 uint32_t word5Rsvd:8;
3845 #endif
3846 } RCV_ELS_REQ64;
3847
3848 /* IOCB Command template for RCV_SEQ64 */
3849 struct rcv_seq64 {
3850 struct ulp_bde64 elsReq;
3851 uint32_t hbq_1;
3852 uint32_t parmRo;
3853 #ifdef __BIG_ENDIAN_BITFIELD
3854 uint32_t rctl:8;
3855 uint32_t type:8;
3856 uint32_t dfctl:8;
3857 uint32_t ls:1;
3858 uint32_t fs:1;
3859 uint32_t rsvd2:3;
3860 uint32_t si:1;
3861 uint32_t bc:1;
3862 uint32_t rsvd3:1;
3863 #else /* __LITTLE_ENDIAN_BITFIELD */
3864 uint32_t rsvd3:1;
3865 uint32_t bc:1;
3866 uint32_t si:1;
3867 uint32_t rsvd2:3;
3868 uint32_t fs:1;
3869 uint32_t ls:1;
3870 uint32_t dfctl:8;
3871 uint32_t type:8;
3872 uint32_t rctl:8;
3873 #endif
3874 };
3875
3876 /* IOCB Command template for all 64 bit FCP Initiator commands */
3877 typedef struct {
3878 ULP_BDL bdl;
3879 uint32_t fcpi_parm;
3880 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3881 } FCPI_FIELDS64;
3882
3883 /* IOCB Command template for all 64 bit FCP Target commands */
3884 typedef struct {
3885 ULP_BDL bdl;
3886 uint32_t fcpt_Offset;
3887 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3888 } FCPT_FIELDS64;
3889
3890 /* IOCB Command template for Async Status iocb commands */
3891 typedef struct {
3892 uint32_t rsvd[4];
3893 uint32_t param;
3894 #ifdef __BIG_ENDIAN_BITFIELD
3895 uint16_t evt_code; /* High order bits word 5 */
3896 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3897 #else /* __LITTLE_ENDIAN_BITFIELD */
3898 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3899 uint16_t evt_code; /* Low order bits word 5 */
3900 #endif
3901 } ASYNCSTAT_FIELDS;
3902 #define ASYNC_TEMP_WARN 0x100
3903 #define ASYNC_TEMP_SAFE 0x101
3904 #define ASYNC_STATUS_CN 0x102
3905
3906 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3907 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3908
3909 struct rcv_sli3 {
3910 #ifdef __BIG_ENDIAN_BITFIELD
3911 uint16_t ox_id;
3912 uint16_t seq_cnt;
3913
3914 uint16_t vpi;
3915 uint16_t word9Rsvd;
3916 #else /* __LITTLE_ENDIAN */
3917 uint16_t seq_cnt;
3918 uint16_t ox_id;
3919
3920 uint16_t word9Rsvd;
3921 uint16_t vpi;
3922 #endif
3923 uint32_t word10Rsvd;
3924 uint32_t acc_len; /* accumulated length */
3925 struct ulp_bde64 bde2;
3926 };
3927
3928 /* Structure used for a single HBQ entry */
3929 struct lpfc_hbq_entry {
3930 struct ulp_bde64 bde;
3931 uint32_t buffer_tag;
3932 };
3933
3934 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3935 typedef struct {
3936 struct lpfc_hbq_entry buff;
3937 uint32_t rsvd;
3938 uint32_t rsvd1;
3939 } QUE_XRI64_CX_FIELDS;
3940
3941 struct que_xri64cx_ext_fields {
3942 uint32_t iotag64_low;
3943 uint32_t iotag64_high;
3944 uint32_t ebde_count;
3945 uint32_t rsvd;
3946 struct lpfc_hbq_entry buff[5];
3947 };
3948
3949 struct sli3_bg_fields {
3950 uint32_t filler[6]; /* word 8-13 in IOCB */
3951 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3952 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3953 #define BGS_BIDIR_BG_PROF_MASK 0xff000000
3954 #define BGS_BIDIR_BG_PROF_SHIFT 24
3955 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3956 #define BGS_BIDIR_ERR_COND_SHIFT 16
3957 #define BGS_BG_PROFILE_MASK 0x0000ff00
3958 #define BGS_BG_PROFILE_SHIFT 8
3959 #define BGS_INVALID_PROF_MASK 0x00000020
3960 #define BGS_INVALID_PROF_SHIFT 5
3961 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3962 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3963 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3964 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3965 #define BGS_REFTAG_ERR_MASK 0x00000004
3966 #define BGS_REFTAG_ERR_SHIFT 2
3967 #define BGS_APPTAG_ERR_MASK 0x00000002
3968 #define BGS_APPTAG_ERR_SHIFT 1
3969 #define BGS_GUARD_ERR_MASK 0x00000001
3970 #define BGS_GUARD_ERR_SHIFT 0
3971 uint32_t bgstat; /* word 15 - BlockGuard Status */
3972 };
3973
3974 static inline uint32_t
3975 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3976 {
3977 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
3978 BGS_BIDIR_BG_PROF_SHIFT;
3979 }
3980
3981 static inline uint32_t
3982 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3983 {
3984 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3985 BGS_BIDIR_ERR_COND_SHIFT;
3986 }
3987
3988 static inline uint32_t
3989 lpfc_bgs_get_bg_prof(uint32_t bgstat)
3990 {
3991 return (bgstat & BGS_BG_PROFILE_MASK) >>
3992 BGS_BG_PROFILE_SHIFT;
3993 }
3994
3995 static inline uint32_t
3996 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3997 {
3998 return (bgstat & BGS_INVALID_PROF_MASK) >>
3999 BGS_INVALID_PROF_SHIFT;
4000 }
4001
4002 static inline uint32_t
4003 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
4004 {
4005 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
4006 BGS_UNINIT_DIF_BLOCK_SHIFT;
4007 }
4008
4009 static inline uint32_t
4010 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
4011 {
4012 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
4013 BGS_HI_WATER_MARK_PRESENT_SHIFT;
4014 }
4015
4016 static inline uint32_t
4017 lpfc_bgs_get_reftag_err(uint32_t bgstat)
4018 {
4019 return (bgstat & BGS_REFTAG_ERR_MASK) >>
4020 BGS_REFTAG_ERR_SHIFT;
4021 }
4022
4023 static inline uint32_t
4024 lpfc_bgs_get_apptag_err(uint32_t bgstat)
4025 {
4026 return (bgstat & BGS_APPTAG_ERR_MASK) >>
4027 BGS_APPTAG_ERR_SHIFT;
4028 }
4029
4030 static inline uint32_t
4031 lpfc_bgs_get_guard_err(uint32_t bgstat)
4032 {
4033 return (bgstat & BGS_GUARD_ERR_MASK) >>
4034 BGS_GUARD_ERR_SHIFT;
4035 }
4036
4037 #define LPFC_EXT_DATA_BDE_COUNT 3
4038 struct fcp_irw_ext {
4039 uint32_t io_tag64_low;
4040 uint32_t io_tag64_high;
4041 #ifdef __BIG_ENDIAN_BITFIELD
4042 uint8_t reserved1;
4043 uint8_t reserved2;
4044 uint8_t reserved3;
4045 uint8_t ebde_count;
4046 #else /* __LITTLE_ENDIAN */
4047 uint8_t ebde_count;
4048 uint8_t reserved3;
4049 uint8_t reserved2;
4050 uint8_t reserved1;
4051 #endif
4052 uint32_t reserved4;
4053 struct ulp_bde64 rbde; /* response bde */
4054 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
4055 uint8_t icd[32]; /* immediate command data (32 bytes) */
4056 };
4057
4058 typedef struct _IOCB { /* IOCB structure */
4059 union {
4060 GENERIC_RSP grsp; /* Generic response */
4061 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
4062 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
4063 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
4064 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
4065 A_MXRI64 amxri; /* abort multiple xri command overlay */
4066 GET_RPI getrpi; /* GET_RPI template */
4067 FCPI_FIELDS fcpi; /* FCP Initiator template */
4068 FCPT_FIELDS fcpt; /* FCP target template */
4069
4070 /* SLI-2 structures */
4071
4072 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
4073 * bde_64s */
4074 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
4075 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
4076 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
4077 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
4078 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
4079 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
4080 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
4081 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
4082 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
4083 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
4084 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
4085 } un;
4086 union {
4087 struct {
4088 #ifdef __BIG_ENDIAN_BITFIELD
4089 uint16_t ulpContext; /* High order bits word 6 */
4090 uint16_t ulpIoTag; /* Low order bits word 6 */
4091 #else /* __LITTLE_ENDIAN_BITFIELD */
4092 uint16_t ulpIoTag; /* Low order bits word 6 */
4093 uint16_t ulpContext; /* High order bits word 6 */
4094 #endif
4095 } t1;
4096 struct {
4097 #ifdef __BIG_ENDIAN_BITFIELD
4098 uint16_t ulpContext; /* High order bits word 6 */
4099 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4100 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4101 #else /* __LITTLE_ENDIAN_BITFIELD */
4102 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4103 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4104 uint16_t ulpContext; /* High order bits word 6 */
4105 #endif
4106 } t2;
4107 } un1;
4108 #define ulpContext un1.t1.ulpContext
4109 #define ulpIoTag un1.t1.ulpIoTag
4110 #define ulpIoTag0 un1.t2.ulpIoTag0
4111
4112 #ifdef __BIG_ENDIAN_BITFIELD
4113 uint32_t ulpTimeout:8;
4114 uint32_t ulpXS:1;
4115 uint32_t ulpFCP2Rcvy:1;
4116 uint32_t ulpPU:2;
4117 uint32_t ulpIr:1;
4118 uint32_t ulpClass:3;
4119 uint32_t ulpCommand:8;
4120 uint32_t ulpStatus:4;
4121 uint32_t ulpBdeCount:2;
4122 uint32_t ulpLe:1;
4123 uint32_t ulpOwner:1; /* Low order bit word 7 */
4124 #else /* __LITTLE_ENDIAN_BITFIELD */
4125 uint32_t ulpOwner:1; /* Low order bit word 7 */
4126 uint32_t ulpLe:1;
4127 uint32_t ulpBdeCount:2;
4128 uint32_t ulpStatus:4;
4129 uint32_t ulpCommand:8;
4130 uint32_t ulpClass:3;
4131 uint32_t ulpIr:1;
4132 uint32_t ulpPU:2;
4133 uint32_t ulpFCP2Rcvy:1;
4134 uint32_t ulpXS:1;
4135 uint32_t ulpTimeout:8;
4136 #endif
4137
4138 union {
4139 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
4140
4141 /* words 8-31 used for que_xri_cx iocb */
4142 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4143 struct fcp_irw_ext fcp_ext;
4144 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
4145
4146 /* words 8-15 for BlockGuard */
4147 struct sli3_bg_fields sli3_bg;
4148 } unsli3;
4149
4150 #define ulpCt_h ulpXS
4151 #define ulpCt_l ulpFCP2Rcvy
4152
4153 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
4154 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
4155 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
4156 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
4157 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
4158 #define PARM_NPIV_DID 3
4159 #define CLASS1 0 /* Class 1 */
4160 #define CLASS2 1 /* Class 2 */
4161 #define CLASS3 2 /* Class 3 */
4162 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
4163
4164 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
4165 #define IOSTAT_FCP_RSP_ERROR 0x1
4166 #define IOSTAT_REMOTE_STOP 0x2
4167 #define IOSTAT_LOCAL_REJECT 0x3
4168 #define IOSTAT_NPORT_RJT 0x4
4169 #define IOSTAT_FABRIC_RJT 0x5
4170 #define IOSTAT_NPORT_BSY 0x6
4171 #define IOSTAT_FABRIC_BSY 0x7
4172 #define IOSTAT_INTERMED_RSP 0x8
4173 #define IOSTAT_LS_RJT 0x9
4174 #define IOSTAT_BA_RJT 0xA
4175 #define IOSTAT_RSVD1 0xB
4176 #define IOSTAT_RSVD2 0xC
4177 #define IOSTAT_RSVD3 0xD
4178 #define IOSTAT_RSVD4 0xE
4179 #define IOSTAT_NEED_BUFFER 0xF
4180 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
4181 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
4182 #define IOSTAT_CNT 0x11
4183
4184 } IOCB_t;
4185
4186
4187 #define SLI1_SLIM_SIZE (4 * 1024)
4188
4189 /* Up to 498 IOCBs will fit into 16k
4190 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
4191 */
4192 #define SLI2_SLIM_SIZE (64 * 1024)
4193
4194 /* Maximum IOCBs that will fit in SLI2 slim */
4195 #define MAX_SLI2_IOCB 498
4196 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4197 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4198 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4199
4200 /* HBQ entries are 4 words each = 4k */
4201 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
4202 lpfc_sli_hbq_count())
4203
4204 struct lpfc_sli2_slim {
4205 MAILBOX_t mbx;
4206 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
4207 PCB_t pcb;
4208 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4209 };
4210
4211 /*
4212 * This function checks PCI device to allow special handling for LC HBAs.
4213 *
4214 * Parameters:
4215 * device : struct pci_dev 's device field
4216 *
4217 * return 1 => TRUE
4218 * 0 => FALSE
4219 */
4220 static inline int
4221 lpfc_is_LC_HBA(unsigned short device)
4222 {
4223 if ((device == PCI_DEVICE_ID_TFLY) ||
4224 (device == PCI_DEVICE_ID_PFLY) ||
4225 (device == PCI_DEVICE_ID_LP101) ||
4226 (device == PCI_DEVICE_ID_BMID) ||
4227 (device == PCI_DEVICE_ID_BSMB) ||
4228 (device == PCI_DEVICE_ID_ZMID) ||
4229 (device == PCI_DEVICE_ID_ZSMB) ||
4230 (device == PCI_DEVICE_ID_SAT_MID) ||
4231 (device == PCI_DEVICE_ID_SAT_SMB) ||
4232 (device == PCI_DEVICE_ID_RFLY))
4233 return 1;
4234 else
4235 return 0;
4236 }
4237
4238 /*
4239 * Determine if an IOCB failed because of a link event or firmware reset.
4240 */
4241
4242 static inline int
4243 lpfc_error_lost_link(IOCB_t *iocbp)
4244 {
4245 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
4246 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
4247 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
4248 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
4249 }
4250
4251 #define MENLO_TRANSPORT_TYPE 0xfe
4252 #define MENLO_CONTEXT 0
4253 #define MENLO_PU 3
4254 #define MENLO_TIMEOUT 30
4255 #define SETVAR_MLOMNT 0x103107
4256 #define SETVAR_MLORST 0x103007
4257
4258 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
Ubuntu Artful kernel mirror