drivers/scsi/lpfc/lpfc_hw.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2004-2007 Emulex.  All rights reserved.           *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *******************************************************************/
  20
  21 #define FDMI_DID        0xfffffaU
  22 #define NameServer_DID  0xfffffcU
  23 #define SCR_DID         0xfffffdU
  24 #define Fabric_DID      0xfffffeU
  25 #define Bcast_DID       0xffffffU
  26 #define Mask_DID        0xffffffU
  27 #define CT_DID_MASK     0xffff00U
  28 #define Fabric_DID_MASK 0xfff000U
  29 #define WELL_KNOWN_DID_MASK 0xfffff0U
  30
  31 #define PT2PT_LocalID   1
  32 #define PT2PT_RemoteID  2
  33
  34 #define FF_DEF_EDTOV          2000      /* Default E_D_TOV (2000ms) */
  35 #define FF_DEF_ALTOV            15      /* Default AL_TIME (15ms) */
  36 #define FF_DEF_RATOV             2      /* Default RA_TOV (2s) */
  37 #define FF_DEF_ARBTOV         1900      /* Default ARB_TOV (1900ms) */
  38
  39 #define LPFC_BUF_RING0        64        /* Number of buffers to post to RING
  40                                            0 */
  41
  42 #define FCELSSIZE             1024      /* maximum ELS transfer size */
  43
  44 #define LPFC_FCP_RING            0      /* ring 0 for FCP initiator commands */
  45 #define LPFC_EXTRA_RING          1      /* ring 1 for other protocols */
  46 #define LPFC_ELS_RING            2      /* ring 2 for ELS commands */
  47 #define LPFC_FCP_NEXT_RING       3
  48
  49 #define SLI2_IOCB_CMD_R0_ENTRIES    172 /* SLI-2 FCP command ring entries */
  50 #define SLI2_IOCB_RSP_R0_ENTRIES    134 /* SLI-2 FCP response ring entries */
  51 #define SLI2_IOCB_CMD_R1_ENTRIES      4 /* SLI-2 extra command ring entries */
  52 #define SLI2_IOCB_RSP_R1_ENTRIES      4 /* SLI-2 extra response ring entries */
  53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
  54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
  55 #define SLI2_IOCB_CMD_R2_ENTRIES     20 /* SLI-2 ELS command ring entries */
  56 #define SLI2_IOCB_RSP_R2_ENTRIES     20 /* SLI-2 ELS response ring entries */
  57 #define SLI2_IOCB_CMD_R3_ENTRIES      0
  58 #define SLI2_IOCB_RSP_R3_ENTRIES      0
  59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
  60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
  61
  62 /* Common Transport structures and definitions */
  63
  64 union CtRevisionId {
  65         /* Structure is in Big Endian format */
  66         struct {
  67                 uint32_t Revision:8;
  68                 uint32_t InId:24;
  69         } bits;
  70         uint32_t word;
  71 };
  72
  73 union CtCommandResponse {
  74         /* Structure is in Big Endian format */
  75         struct {
  76                 uint32_t CmdRsp:16;
  77                 uint32_t Size:16;
  78         } bits;
  79         uint32_t word;
  80 };
  81
  82 struct lpfc_sli_ct_request {
  83         /* Structure is in Big Endian format */
  84         union CtRevisionId RevisionId;
  85         uint8_t FsType;
  86         uint8_t FsSubType;
  87         uint8_t Options;
  88         uint8_t Rsrvd1;
  89         union CtCommandResponse CommandResponse;
  90         uint8_t Rsrvd2;
  91         uint8_t ReasonCode;
  92         uint8_t Explanation;
  93         uint8_t VendorUnique;
  94
  95         union {
  96                 uint32_t PortID;
  97                 struct gid {
  98                         uint8_t PortType;       /* for GID_PT requests */
  99                         uint8_t DomainScope;
 100                         uint8_t AreaScope;
 101                         uint8_t Fc4Type;        /* for GID_FT requests */
 102                 } gid;
 103                 struct rft {
 104                         uint32_t PortId;        /* For RFT_ID requests */
 105
 106 #ifdef __BIG_ENDIAN_BITFIELD
 107                         uint32_t rsvd0:16;
 108                         uint32_t rsvd1:7;
 109                         uint32_t fcpReg:1;      /* Type 8 */
 110                         uint32_t rsvd2:2;
 111                         uint32_t ipReg:1;       /* Type 5 */
 112                         uint32_t rsvd3:5;
 113 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 114                         uint32_t rsvd0:16;
 115                         uint32_t fcpReg:1;      /* Type 8 */
 116                         uint32_t rsvd1:7;
 117                         uint32_t rsvd3:5;
 118                         uint32_t ipReg:1;       /* Type 5 */
 119                         uint32_t rsvd2:2;
 120 #endif
 121
 122                         uint32_t rsvd[7];
 123                 } rft;
 124                 struct rff {
 125                         uint32_t PortId;
 126                         uint8_t reserved[2];
 127 #ifdef __BIG_ENDIAN_BITFIELD
 128                         uint8_t feature_res:6;
 129                         uint8_t feature_init:1;
 130                         uint8_t feature_tgt:1;
 131 #else  /*  __LITTLE_ENDIAN_BITFIELD */
 132                         uint8_t feature_tgt:1;
 133                         uint8_t feature_init:1;
 134                         uint8_t feature_res:6;
 135 #endif
 136                         uint8_t type_code;     /* type=8 for FCP */
 137                 } rff;
 138                 struct rnn {
 139                         uint32_t PortId;        /* For RNN_ID requests */
 140                         uint8_t wwnn[8];
 141                 } rnn;
 142                 struct rsnn {   /* For RSNN_ID requests */
 143                         uint8_t wwnn[8];
 144                         uint8_t len;
 145                         uint8_t symbname[255];
 146                 } rsnn;
 147         } un;
 148 };
 149
 150 #define  SLI_CT_REVISION        1
 151 #define  GID_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 260)
 152 #define  RFT_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 228)
 153 #define  RFF_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 235)
 154 #define  RNN_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 252)
 155 #define  RSNN_REQUEST_SZ        (sizeof(struct lpfc_sli_ct_request))
 156
 157 /*
 158  * FsType Definitions
 159  */
 160
 161 #define  SLI_CT_MANAGEMENT_SERVICE        0xFA
 162 #define  SLI_CT_TIME_SERVICE              0xFB
 163 #define  SLI_CT_DIRECTORY_SERVICE         0xFC
 164 #define  SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
 165
 166 /*
 167  * Directory Service Subtypes
 168  */
 169
 170 #define  SLI_CT_DIRECTORY_NAME_SERVER     0x02
 171
 172 /*
 173  * Response Codes
 174  */
 175
 176 #define  SLI_CT_RESPONSE_FS_RJT           0x8001
 177 #define  SLI_CT_RESPONSE_FS_ACC           0x8002
 178
 179 /*
 180  * Reason Codes
 181  */
 182
 183 #define  SLI_CT_NO_ADDITIONAL_EXPL        0x0
 184 #define  SLI_CT_INVALID_COMMAND           0x01
 185 #define  SLI_CT_INVALID_VERSION           0x02
 186 #define  SLI_CT_LOGICAL_ERROR             0x03
 187 #define  SLI_CT_INVALID_IU_SIZE           0x04
 188 #define  SLI_CT_LOGICAL_BUSY              0x05
 189 #define  SLI_CT_PROTOCOL_ERROR            0x07
 190 #define  SLI_CT_UNABLE_TO_PERFORM_REQ     0x09
 191 #define  SLI_CT_REQ_NOT_SUPPORTED         0x0b
 192 #define  SLI_CT_HBA_INFO_NOT_REGISTERED   0x10
 193 #define  SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE  0x11
 194 #define  SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN      0x12
 195 #define  SLI_CT_HBA_ATTR_NOT_PRESENT      0x13
 196 #define  SLI_CT_PORT_INFO_NOT_REGISTERED  0x20
 197 #define  SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
 198 #define  SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN     0x22
 199 #define  SLI_CT_VENDOR_UNIQUE             0xff
 200
 201 /*
 202  * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
 203  */
 204
 205 #define  SLI_CT_NO_PORT_ID                0x01
 206 #define  SLI_CT_NO_PORT_NAME              0x02
 207 #define  SLI_CT_NO_NODE_NAME              0x03
 208 #define  SLI_CT_NO_CLASS_OF_SERVICE       0x04
 209 #define  SLI_CT_NO_IP_ADDRESS             0x05
 210 #define  SLI_CT_NO_IPA                    0x06
 211 #define  SLI_CT_NO_FC4_TYPES              0x07
 212 #define  SLI_CT_NO_SYMBOLIC_PORT_NAME     0x08
 213 #define  SLI_CT_NO_SYMBOLIC_NODE_NAME     0x09
 214 #define  SLI_CT_NO_PORT_TYPE              0x0A
 215 #define  SLI_CT_ACCESS_DENIED             0x10
 216 #define  SLI_CT_INVALID_PORT_ID           0x11
 217 #define  SLI_CT_DATABASE_EMPTY            0x12
 218
 219 /*
 220  * Name Server Command Codes
 221  */
 222
 223 #define  SLI_CTNS_GA_NXT      0x0100
 224 #define  SLI_CTNS_GPN_ID      0x0112
 225 #define  SLI_CTNS_GNN_ID      0x0113
 226 #define  SLI_CTNS_GCS_ID      0x0114
 227 #define  SLI_CTNS_GFT_ID      0x0117
 228 #define  SLI_CTNS_GSPN_ID     0x0118
 229 #define  SLI_CTNS_GPT_ID      0x011A
 230 #define  SLI_CTNS_GID_PN      0x0121
 231 #define  SLI_CTNS_GID_NN      0x0131
 232 #define  SLI_CTNS_GIP_NN      0x0135
 233 #define  SLI_CTNS_GIPA_NN     0x0136
 234 #define  SLI_CTNS_GSNN_NN     0x0139
 235 #define  SLI_CTNS_GNN_IP      0x0153
 236 #define  SLI_CTNS_GIPA_IP     0x0156
 237 #define  SLI_CTNS_GID_FT      0x0171
 238 #define  SLI_CTNS_GID_PT      0x01A1
 239 #define  SLI_CTNS_RPN_ID      0x0212
 240 #define  SLI_CTNS_RNN_ID      0x0213
 241 #define  SLI_CTNS_RCS_ID      0x0214
 242 #define  SLI_CTNS_RFT_ID      0x0217
 243 #define  SLI_CTNS_RFF_ID      0x021F
 244 #define  SLI_CTNS_RSPN_ID     0x0218
 245 #define  SLI_CTNS_RPT_ID      0x021A
 246 #define  SLI_CTNS_RIP_NN      0x0235
 247 #define  SLI_CTNS_RIPA_NN     0x0236
 248 #define  SLI_CTNS_RSNN_NN     0x0239
 249 #define  SLI_CTNS_DA_ID       0x0300
 250
 251 /*
 252  * Port Types
 253  */
 254
 255 #define  SLI_CTPT_N_PORT      0x01
 256 #define  SLI_CTPT_NL_PORT     0x02
 257 #define  SLI_CTPT_FNL_PORT    0x03
 258 #define  SLI_CTPT_IP          0x04
 259 #define  SLI_CTPT_FCP         0x08
 260 #define  SLI_CTPT_NX_PORT     0x7F
 261 #define  SLI_CTPT_F_PORT      0x81
 262 #define  SLI_CTPT_FL_PORT     0x82
 263 #define  SLI_CTPT_E_PORT      0x84
 264
 265 #define SLI_CT_LAST_ENTRY     0x80000000
 266
 267 /* Fibre Channel Service Parameter definitions */
 268
 269 #define FC_PH_4_0   6           /* FC-PH version 4.0 */
 270 #define FC_PH_4_1   7           /* FC-PH version 4.1 */
 271 #define FC_PH_4_2   8           /* FC-PH version 4.2 */
 272 #define FC_PH_4_3   9           /* FC-PH version 4.3 */
 273
 274 #define FC_PH_LOW   8           /* Lowest supported FC-PH version */
 275 #define FC_PH_HIGH  9           /* Highest supported FC-PH version */
 276 #define FC_PH3   0x20           /* FC-PH-3 version */
 277
 278 #define FF_FRAME_SIZE     2048
 279
 280 struct lpfc_name {
 281         union {
 282                 struct {
 283 #ifdef __BIG_ENDIAN_BITFIELD
 284                         uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 285                         uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 286                                                    8:11 of IEEE ext */
 287 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 288                         uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 289                                                    8:11 of IEEE ext */
 290                         uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 291 #endif
 292
 293 #define NAME_IEEE           0x1 /* IEEE name - nameType */
 294 #define NAME_IEEE_EXT       0x2 /* IEEE extended name */
 295 #define NAME_FC_TYPE        0x3 /* FC native name type */
 296 #define NAME_IP_TYPE        0x4 /* IP address */
 297 #define NAME_CCITT_TYPE     0xC
 298 #define NAME_CCITT_GR_TYPE  0xE
 299                         uint8_t IEEEextLsb;     /* FC Word 0, bit 16:23, IEEE
 300                                                    extended Lsb */
 301                         uint8_t IEEE[6];        /* FC IEEE address */
 302                 } s;
 303                 uint8_t wwn[8];
 304         } u;
 305 };
 306
 307 struct csp {
 308         uint8_t fcphHigh;       /* FC Word 0, byte 0 */
 309         uint8_t fcphLow;
 310         uint8_t bbCreditMsb;
 311         uint8_t bbCreditlsb;    /* FC Word 0, byte 3 */
 312
 313 #ifdef __BIG_ENDIAN_BITFIELD
 314         uint16_t increasingOffset:1;    /* FC Word 1, bit 31 */
 315         uint16_t response_multiple_Nport:1;     /* FC Word 1, bit 29 */
 316         uint16_t fPort:1;       /* FC Word 1, bit 28 */
 317         uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 318         uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 319         uint16_t multicast:1;   /* FC Word 1, bit 25 */
 320         uint16_t broadcast:1;   /* FC Word 1, bit 24 */
 321
 322         uint16_t huntgroup:1;   /* FC Word 1, bit 23 */
 323         uint16_t simplex:1;     /* FC Word 1, bit 22 */
 324         uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 325         uint16_t dhd:1;         /* FC Word 1, bit 18 */
 326         uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 327         uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 328 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 329         uint16_t broadcast:1;   /* FC Word 1, bit 24 */
 330         uint16_t multicast:1;   /* FC Word 1, bit 25 */
 331         uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 332         uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 333         uint16_t fPort:1;       /* FC Word 1, bit 28 */
 334         uint16_t word1Reserved2:1;      /* FC Word 1, bit 29 */
 335         uint16_t randomOffset:1;        /* FC Word 1, bit 30 */
 336         uint16_t increasingOffset:1;    /* FC Word 1, bit 31 */
 337
 338         uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 339         uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 340         uint16_t dhd:1;         /* FC Word 1, bit 18 */
 341         uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 342         uint16_t simplex:1;     /* FC Word 1, bit 22 */
 343         uint16_t huntgroup:1;   /* FC Word 1, bit 23 */
 344 #endif
 345
 346         uint8_t bbRcvSizeMsb;   /* Upper nibble is reserved */
 347         uint8_t bbRcvSizeLsb;   /* FC Word 1, byte 3 */
 348         union {
 349                 struct {
 350                         uint8_t word2Reserved1; /* FC Word 2 byte 0 */
 351
 352                         uint8_t totalConcurrSeq;        /* FC Word 2 byte 1 */
 353                         uint8_t roByCategoryMsb;        /* FC Word 2 byte 2 */
 354
 355                         uint8_t roByCategoryLsb;        /* FC Word 2 byte 3 */
 356                 } nPort;
 357                 uint32_t r_a_tov;       /* R_A_TOV must be in B.E. format */
 358         } w2;
 359
 360         uint32_t e_d_tov;       /* E_D_TOV must be in B.E. format */
 361 };
 362
 363 struct class_parms {
 364 #ifdef __BIG_ENDIAN_BITFIELD
 365         uint8_t classValid:1;   /* FC Word 0, bit 31 */
 366         uint8_t intermix:1;     /* FC Word 0, bit 30 */
 367         uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 368         uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 369         uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 370         uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 371 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 372         uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 373         uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 374         uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 375         uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 376         uint8_t intermix:1;     /* FC Word 0, bit 30 */
 377         uint8_t classValid:1;   /* FC Word 0, bit 31 */
 378
 379 #endif
 380
 381         uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
 382
 383 #ifdef __BIG_ENDIAN_BITFIELD
 384         uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 385         uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 386         uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 387         uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 388         uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 389 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 390         uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 391         uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 392         uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 393         uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 394         uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 395 #endif
 396
 397         uint8_t word0Reserved4; /* FC Word 0, bit  0: 7 */
 398
 399 #ifdef __BIG_ENDIAN_BITFIELD
 400         uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 401         uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 402         uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 403         uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 404         uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 405         uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 406 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 407         uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 408         uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 409         uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 410         uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 411         uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 412         uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 413 #endif
 414
 415         uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
 416         uint8_t rcvDataSizeMsb; /* FC Word 1, bit  8:15 */
 417         uint8_t rcvDataSizeLsb; /* FC Word 1, bit  0: 7 */
 418
 419         uint8_t concurrentSeqMsb;       /* FC Word 2, bit 24:31 */
 420         uint8_t concurrentSeqLsb;       /* FC Word 2, bit 16:23 */
 421         uint8_t EeCreditSeqMsb; /* FC Word 2, bit  8:15 */
 422         uint8_t EeCreditSeqLsb; /* FC Word 2, bit  0: 7 */
 423
 424         uint8_t openSeqPerXchgMsb;      /* FC Word 3, bit 24:31 */
 425         uint8_t openSeqPerXchgLsb;      /* FC Word 3, bit 16:23 */
 426         uint8_t word3Reserved1; /* Fc Word 3, bit  8:15 */
 427         uint8_t word3Reserved2; /* Fc Word 3, bit  0: 7 */
 428 };
 429
 430 struct serv_parm {      /* Structure is in Big Endian format */
 431         struct csp cmn;
 432         struct lpfc_name portName;
 433         struct lpfc_name nodeName;
 434         struct class_parms cls1;
 435         struct class_parms cls2;
 436         struct class_parms cls3;
 437         struct class_parms cls4;
 438         uint8_t vendorVersion[16];
 439 };
 440
 441 /*
 442  *  Extended Link Service LS_COMMAND codes (Payload Word 0)
 443  */
 444 #ifdef __BIG_ENDIAN_BITFIELD
 445 #define ELS_CMD_MASK      0xffff0000
 446 #define ELS_RSP_MASK      0xff000000
 447 #define ELS_CMD_LS_RJT    0x01000000
 448 #define ELS_CMD_ACC       0x02000000
 449 #define ELS_CMD_PLOGI     0x03000000
 450 #define ELS_CMD_FLOGI     0x04000000
 451 #define ELS_CMD_LOGO      0x05000000
 452 #define ELS_CMD_ABTX      0x06000000
 453 #define ELS_CMD_RCS       0x07000000
 454 #define ELS_CMD_RES       0x08000000
 455 #define ELS_CMD_RSS       0x09000000
 456 #define ELS_CMD_RSI       0x0A000000
 457 #define ELS_CMD_ESTS      0x0B000000
 458 #define ELS_CMD_ESTC      0x0C000000
 459 #define ELS_CMD_ADVC      0x0D000000
 460 #define ELS_CMD_RTV       0x0E000000
 461 #define ELS_CMD_RLS       0x0F000000
 462 #define ELS_CMD_ECHO      0x10000000
 463 #define ELS_CMD_TEST      0x11000000
 464 #define ELS_CMD_RRQ       0x12000000
 465 #define ELS_CMD_PRLI      0x20100014
 466 #define ELS_CMD_PRLO      0x21100014
 467 #define ELS_CMD_PRLO_ACC  0x02100014
 468 #define ELS_CMD_PDISC     0x50000000
 469 #define ELS_CMD_FDISC     0x51000000
 470 #define ELS_CMD_ADISC     0x52000000
 471 #define ELS_CMD_FARP      0x54000000
 472 #define ELS_CMD_FARPR     0x55000000
 473 #define ELS_CMD_RPS       0x56000000
 474 #define ELS_CMD_RPL       0x57000000
 475 #define ELS_CMD_FAN       0x60000000
 476 #define ELS_CMD_RSCN      0x61040000
 477 #define ELS_CMD_SCR       0x62000000
 478 #define ELS_CMD_RNID      0x78000000
 479 #define ELS_CMD_LIRR      0x7A000000
 480 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 481 #define ELS_CMD_MASK      0xffff
 482 #define ELS_RSP_MASK      0xff
 483 #define ELS_CMD_LS_RJT    0x01
 484 #define ELS_CMD_ACC       0x02
 485 #define ELS_CMD_PLOGI     0x03
 486 #define ELS_CMD_FLOGI     0x04
 487 #define ELS_CMD_LOGO      0x05
 488 #define ELS_CMD_ABTX      0x06
 489 #define ELS_CMD_RCS       0x07
 490 #define ELS_CMD_RES       0x08
 491 #define ELS_CMD_RSS       0x09
 492 #define ELS_CMD_RSI       0x0A
 493 #define ELS_CMD_ESTS      0x0B
 494 #define ELS_CMD_ESTC      0x0C
 495 #define ELS_CMD_ADVC      0x0D
 496 #define ELS_CMD_RTV       0x0E
 497 #define ELS_CMD_RLS       0x0F
 498 #define ELS_CMD_ECHO      0x10
 499 #define ELS_CMD_TEST      0x11
 500 #define ELS_CMD_RRQ       0x12
 501 #define ELS_CMD_PRLI      0x14001020
 502 #define ELS_CMD_PRLO      0x14001021
 503 #define ELS_CMD_PRLO_ACC  0x14001002
 504 #define ELS_CMD_PDISC     0x50
 505 #define ELS_CMD_FDISC     0x51
 506 #define ELS_CMD_ADISC     0x52
 507 #define ELS_CMD_FARP      0x54
 508 #define ELS_CMD_FARPR     0x55
 509 #define ELS_CMD_RPS       0x56
 510 #define ELS_CMD_RPL       0x57
 511 #define ELS_CMD_FAN       0x60
 512 #define ELS_CMD_RSCN      0x0461
 513 #define ELS_CMD_SCR       0x62
 514 #define ELS_CMD_RNID      0x78
 515 #define ELS_CMD_LIRR      0x7A
 516 #endif
 517
 518 /*
 519  *  LS_RJT Payload Definition
 520  */
 521
 522 struct ls_rjt { /* Structure is in Big Endian format */
 523         union {
 524                 uint32_t lsRjtError;
 525                 struct {
 526                         uint8_t lsRjtRsvd0;     /* FC Word 0, bit 24:31 */
 527
 528                         uint8_t lsRjtRsnCode;   /* FC Word 0, bit 16:23 */
 529                         /* LS_RJT reason codes */
 530 #define LSRJT_INVALID_CMD     0x01
 531 #define LSRJT_LOGICAL_ERR     0x03
 532 #define LSRJT_LOGICAL_BSY     0x05
 533 #define LSRJT_PROTOCOL_ERR    0x07
 534 #define LSRJT_UNABLE_TPC      0x09      /* Unable to perform command */
 535 #define LSRJT_CMD_UNSUPPORTED 0x0B
 536 #define LSRJT_VENDOR_UNIQUE   0xFF      /* See Byte 3 */
 537
 538                         uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
 539                         /* LS_RJT reason explanation */
 540 #define LSEXP_NOTHING_MORE      0x00
 541 #define LSEXP_SPARM_OPTIONS     0x01
 542 #define LSEXP_SPARM_ICTL        0x03
 543 #define LSEXP_SPARM_RCTL        0x05
 544 #define LSEXP_SPARM_RCV_SIZE    0x07
 545 #define LSEXP_SPARM_CONCUR_SEQ  0x09
 546 #define LSEXP_SPARM_CREDIT      0x0B
 547 #define LSEXP_INVALID_PNAME     0x0D
 548 #define LSEXP_INVALID_NNAME     0x0E
 549 #define LSEXP_INVALID_CSP       0x0F
 550 #define LSEXP_INVALID_ASSOC_HDR 0x11
 551 #define LSEXP_ASSOC_HDR_REQ     0x13
 552 #define LSEXP_INVALID_O_SID     0x15
 553 #define LSEXP_INVALID_OX_RX     0x17
 554 #define LSEXP_CMD_IN_PROGRESS   0x19
 555 #define LSEXP_INVALID_NPORT_ID  0x1F
 556 #define LSEXP_INVALID_SEQ_ID    0x21
 557 #define LSEXP_INVALID_XCHG      0x23
 558 #define LSEXP_INACTIVE_XCHG     0x25
 559 #define LSEXP_RQ_REQUIRED       0x27
 560 #define LSEXP_OUT_OF_RESOURCE   0x29
 561 #define LSEXP_CANT_GIVE_DATA    0x2A
 562 #define LSEXP_REQ_UNSUPPORTED   0x2C
 563                         uint8_t vendorUnique;   /* FC Word 0, bit  0: 7 */
 564                 } b;
 565         } un;
 566 };
 567
 568 /*
 569  *  N_Port Login (FLOGO/PLOGO Request) Payload Definition
 570  */
 571
 572 typedef struct _LOGO {          /* Structure is in Big Endian format */
 573         union {
 574                 uint32_t nPortId32;     /* Access nPortId as a word */
 575                 struct {
 576                         uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
 577                         uint8_t nPortIdByte0;   /* N_port  ID bit 16:23 */
 578                         uint8_t nPortIdByte1;   /* N_port  ID bit  8:15 */
 579                         uint8_t nPortIdByte2;   /* N_port  ID bit  0: 7 */
 580                 } b;
 581         } un;
 582         struct lpfc_name portName;      /* N_port name field */
 583 } LOGO;
 584
 585 /*
 586  *  FCP Login (PRLI Request / ACC) Payload Definition
 587  */
 588
 589 #define PRLX_PAGE_LEN   0x10
 590 #define TPRLO_PAGE_LEN  0x14
 591
 592 typedef struct _PRLI {          /* Structure is in Big Endian format */
 593         uint8_t prliType;       /* FC Parm Word 0, bit 24:31 */
 594
 595 #define PRLI_FCP_TYPE 0x08
 596         uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 597
 598 #ifdef __BIG_ENDIAN_BITFIELD
 599         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 600         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 601         uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 602
 603         /*    ACC = imagePairEstablished */
 604         uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 605         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 606 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 607         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 608         uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 609         uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 610         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 611         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 612         /*    ACC = imagePairEstablished */
 613 #endif
 614
 615 #define PRLI_REQ_EXECUTED     0x1       /* acceptRspCode */
 616 #define PRLI_NO_RESOURCES     0x2
 617 #define PRLI_INIT_INCOMPLETE  0x3
 618 #define PRLI_NO_SUCH_PA       0x4
 619 #define PRLI_PREDEF_CONFIG    0x5
 620 #define PRLI_PARTIAL_SUCCESS  0x6
 621 #define PRLI_INVALID_PAGE_CNT 0x7
 622         uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 623
 624         uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 625
 626         uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 627
 628         uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
 629         uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
 630
 631 #ifdef __BIG_ENDIAN_BITFIELD
 632         uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 633         uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 634         uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 635         uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 636         uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 637         uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 638         uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 639         uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 640         uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 641         uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 642         uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 643         uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 644         uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 645         uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 646         uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 647         uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 648 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 649         uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 650         uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 651         uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 652         uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 653         uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 654         uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 655         uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 656         uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 657         uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 658         uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 659         uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 660         uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 661         uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 662         uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 663         uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 664         uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 665 #endif
 666 } PRLI;
 667
 668 /*
 669  *  FCP Logout (PRLO Request / ACC) Payload Definition
 670  */
 671
 672 typedef struct _PRLO {          /* Structure is in Big Endian format */
 673         uint8_t prloType;       /* FC Parm Word 0, bit 24:31 */
 674
 675 #define PRLO_FCP_TYPE  0x08
 676         uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 677
 678 #ifdef __BIG_ENDIAN_BITFIELD
 679         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 680         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 681         uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 682         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 683 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 684         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 685         uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 686         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 687         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 688 #endif
 689
 690 #define PRLO_REQ_EXECUTED     0x1       /* acceptRspCode */
 691 #define PRLO_NO_SUCH_IMAGE    0x4
 692 #define PRLO_INVALID_PAGE_CNT 0x7
 693
 694         uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 695
 696         uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 697
 698         uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 699
 700         uint32_t word3Reserved1;        /* FC Parm Word 3, bit 0:31 */
 701 } PRLO;
 702
 703 typedef struct _ADISC {         /* Structure is in Big Endian format */
 704         uint32_t hardAL_PA;
 705         struct lpfc_name portName;
 706         struct lpfc_name nodeName;
 707         uint32_t DID;
 708 } ADISC;
 709
 710 typedef struct _FARP {          /* Structure is in Big Endian format */
 711         uint32_t Mflags:8;
 712         uint32_t Odid:24;
 713 #define FARP_NO_ACTION          0       /* FARP information enclosed, no
 714                                            action */
 715 #define FARP_MATCH_PORT         0x1     /* Match on Responder Port Name */
 716 #define FARP_MATCH_NODE         0x2     /* Match on Responder Node Name */
 717 #define FARP_MATCH_IP           0x4     /* Match on IP address, not supported */
 718 #define FARP_MATCH_IPV4         0x5     /* Match on IPV4 address, not
 719                                            supported */
 720 #define FARP_MATCH_IPV6         0x6     /* Match on IPV6 address, not
 721                                            supported */
 722         uint32_t Rflags:8;
 723         uint32_t Rdid:24;
 724 #define FARP_REQUEST_PLOGI      0x1     /* Request for PLOGI */
 725 #define FARP_REQUEST_FARPR      0x2     /* Request for FARP Response */
 726         struct lpfc_name OportName;
 727         struct lpfc_name OnodeName;
 728         struct lpfc_name RportName;
 729         struct lpfc_name RnodeName;
 730         uint8_t Oipaddr[16];
 731         uint8_t Ripaddr[16];
 732 } FARP;
 733
 734 typedef struct _FAN {           /* Structure is in Big Endian format */
 735         uint32_t Fdid;
 736         struct lpfc_name FportName;
 737         struct lpfc_name FnodeName;
 738 } FAN;
 739
 740 typedef struct _SCR {           /* Structure is in Big Endian format */
 741         uint8_t resvd1;
 742         uint8_t resvd2;
 743         uint8_t resvd3;
 744         uint8_t Function;
 745 #define  SCR_FUNC_FABRIC     0x01
 746 #define  SCR_FUNC_NPORT      0x02
 747 #define  SCR_FUNC_FULL       0x03
 748 #define  SCR_CLEAR           0xff
 749 } SCR;
 750
 751 typedef struct _RNID_TOP_DISC {
 752         struct lpfc_name portName;
 753         uint8_t resvd[8];
 754         uint32_t unitType;
 755 #define RNID_HBA            0x7
 756 #define RNID_HOST           0xa
 757 #define RNID_DRIVER         0xd
 758         uint32_t physPort;
 759         uint32_t attachedNodes;
 760         uint16_t ipVersion;
 761 #define RNID_IPV4           0x1
 762 #define RNID_IPV6           0x2
 763         uint16_t UDPport;
 764         uint8_t ipAddr[16];
 765         uint16_t resvd1;
 766         uint16_t flags;
 767 #define RNID_TD_SUPPORT     0x1
 768 #define RNID_LP_VALID       0x2
 769 } RNID_TOP_DISC;
 770
 771 typedef struct _RNID {          /* Structure is in Big Endian format */
 772         uint8_t Format;
 773 #define RNID_TOPOLOGY_DISC  0xdf
 774         uint8_t CommonLen;
 775         uint8_t resvd1;
 776         uint8_t SpecificLen;
 777         struct lpfc_name portName;
 778         struct lpfc_name nodeName;
 779         union {
 780                 RNID_TOP_DISC topologyDisc;     /* topology disc (0xdf) */
 781         } un;
 782 } RNID;
 783
 784 typedef struct  _RPS {          /* Structure is in Big Endian format */
 785         union {
 786                 uint32_t portNum;
 787                 struct lpfc_name portName;
 788         } un;
 789 } RPS;
 790
 791 typedef struct  _RPS_RSP {      /* Structure is in Big Endian format */
 792         uint16_t rsvd1;
 793         uint16_t portStatus;
 794         uint32_t linkFailureCnt;
 795         uint32_t lossSyncCnt;
 796         uint32_t lossSignalCnt;
 797         uint32_t primSeqErrCnt;
 798         uint32_t invalidXmitWord;
 799         uint32_t crcCnt;
 800 } RPS_RSP;
 801
 802 typedef struct  _RPL {          /* Structure is in Big Endian format */
 803         uint32_t maxsize;
 804         uint32_t index;
 805 } RPL;
 806
 807 typedef struct  _PORT_NUM_BLK {
 808         uint32_t portNum;
 809         uint32_t portID;
 810         struct lpfc_name portName;
 811 } PORT_NUM_BLK;
 812
 813 typedef struct  _RPL_RSP {      /* Structure is in Big Endian format */
 814         uint32_t listLen;
 815         uint32_t index;
 816         PORT_NUM_BLK port_num_blk;
 817 } RPL_RSP;
 818
 819 /* This is used for RSCN command */
 820 typedef struct _D_ID {          /* Structure is in Big Endian format */
 821         union {
 822                 uint32_t word;
 823                 struct {
 824 #ifdef __BIG_ENDIAN_BITFIELD
 825                         uint8_t resv;
 826                         uint8_t domain;
 827                         uint8_t area;
 828                         uint8_t id;
 829 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 830                         uint8_t id;
 831                         uint8_t area;
 832                         uint8_t domain;
 833                         uint8_t resv;
 834 #endif
 835                 } b;
 836         } un;
 837 } D_ID;
 838
 839 /*
 840  *  Structure to define all ELS Payload types
 841  */
 842
 843 typedef struct _ELS_PKT {       /* Structure is in Big Endian format */
 844         uint8_t elsCode;        /* FC Word 0, bit 24:31 */
 845         uint8_t elsByte1;
 846         uint8_t elsByte2;
 847         uint8_t elsByte3;
 848         union {
 849                 struct ls_rjt lsRjt;    /* Payload for LS_RJT ELS response */
 850                 struct serv_parm logi;  /* Payload for PLOGI/FLOGI/PDISC/ACC */
 851                 LOGO logo;      /* Payload for PLOGO/FLOGO/ACC */
 852                 PRLI prli;      /* Payload for PRLI/ACC */
 853                 PRLO prlo;      /* Payload for PRLO/ACC */
 854                 ADISC adisc;    /* Payload for ADISC/ACC */
 855                 FARP farp;      /* Payload for FARP/ACC */
 856                 FAN fan;        /* Payload for FAN */
 857                 SCR scr;        /* Payload for SCR/ACC */
 858                 RNID rnid;      /* Payload for RNID */
 859                 uint8_t pad[128 - 4];   /* Pad out to payload of 128 bytes */
 860         } un;
 861 } ELS_PKT;
 862
 863 /*
 864  * FDMI
 865  * HBA MAnagement Operations Command Codes
 866  */
 867 #define  SLI_MGMT_GRHL     0x100        /* Get registered HBA list */
 868 #define  SLI_MGMT_GHAT     0x101        /* Get HBA attributes */
 869 #define  SLI_MGMT_GRPL     0x102        /* Get registered Port list */
 870 #define  SLI_MGMT_GPAT     0x110        /* Get Port attributes */
 871 #define  SLI_MGMT_RHBA     0x200        /* Register HBA */
 872 #define  SLI_MGMT_RHAT     0x201        /* Register HBA atttributes */
 873 #define  SLI_MGMT_RPRT     0x210        /* Register Port */
 874 #define  SLI_MGMT_RPA      0x211        /* Register Port attributes */
 875 #define  SLI_MGMT_DHBA     0x300        /* De-register HBA */
 876 #define  SLI_MGMT_DPRT     0x310        /* De-register Port */
 877
 878 /*
 879  * Management Service Subtypes
 880  */
 881 #define  SLI_CT_FDMI_Subtypes     0x10
 882
 883 /*
 884  * HBA Management Service Reject Code
 885  */
 886 #define  REJECT_CODE             0x9    /* Unable to perform command request */
 887
 888 /*
 889  * HBA Management Service Reject Reason Code
 890  * Please refer to the Reason Codes above
 891  */
 892
 893 /*
 894  * HBA Attribute Types
 895  */
 896 #define  NODE_NAME               0x1
 897 #define  MANUFACTURER            0x2
 898 #define  SERIAL_NUMBER           0x3
 899 #define  MODEL                   0x4
 900 #define  MODEL_DESCRIPTION       0x5
 901 #define  HARDWARE_VERSION        0x6
 902 #define  DRIVER_VERSION          0x7
 903 #define  OPTION_ROM_VERSION      0x8
 904 #define  FIRMWARE_VERSION        0x9
 905 #define  OS_NAME_VERSION         0xa
 906 #define  MAX_CT_PAYLOAD_LEN      0xb
 907
 908 /*
 909  * Port Attrubute Types
 910  */
 911 #define  SUPPORTED_FC4_TYPES     0x1
 912 #define  SUPPORTED_SPEED         0x2
 913 #define  PORT_SPEED              0x3
 914 #define  MAX_FRAME_SIZE          0x4
 915 #define  OS_DEVICE_NAME          0x5
 916 #define  HOST_NAME               0x6
 917
 918 union AttributesDef {
 919         /* Structure is in Big Endian format */
 920         struct {
 921                 uint32_t AttrType:16;
 922                 uint32_t AttrLen:16;
 923         } bits;
 924         uint32_t word;
 925 };
 926
 927
 928 /*
 929  * HBA Attribute Entry (8 - 260 bytes)
 930  */
 931 typedef struct {
 932         union AttributesDef ad;
 933         union {
 934                 uint32_t VendorSpecific;
 935                 uint8_t Manufacturer[64];
 936                 uint8_t SerialNumber[64];
 937                 uint8_t Model[256];
 938                 uint8_t ModelDescription[256];
 939                 uint8_t HardwareVersion[256];
 940                 uint8_t DriverVersion[256];
 941                 uint8_t OptionROMVersion[256];
 942                 uint8_t FirmwareVersion[256];
 943                 struct lpfc_name NodeName;
 944                 uint8_t SupportFC4Types[32];
 945                 uint32_t SupportSpeed;
 946                 uint32_t PortSpeed;
 947                 uint32_t MaxFrameSize;
 948                 uint8_t OsDeviceName[256];
 949                 uint8_t OsNameVersion[256];
 950                 uint32_t MaxCTPayloadLen;
 951                 uint8_t HostName[256];
 952         } un;
 953 } ATTRIBUTE_ENTRY;
 954
 955 /*
 956  * HBA Attribute Block
 957  */
 958 typedef struct {
 959         uint32_t EntryCnt;      /* Number of HBA attribute entries */
 960         ATTRIBUTE_ENTRY Entry;  /* Variable-length array */
 961 } ATTRIBUTE_BLOCK;
 962
 963 /*
 964  * Port Entry
 965  */
 966 typedef struct {
 967         struct lpfc_name PortName;
 968 } PORT_ENTRY;
 969
 970 /*
 971  * HBA Identifier
 972  */
 973 typedef struct {
 974         struct lpfc_name PortName;
 975 } HBA_IDENTIFIER;
 976
 977 /*
 978  * Registered Port List Format
 979  */
 980 typedef struct {
 981         uint32_t EntryCnt;
 982         PORT_ENTRY pe;          /* Variable-length array */
 983 } REG_PORT_LIST;
 984
 985 /*
 986  * Register HBA(RHBA)
 987  */
 988 typedef struct {
 989         HBA_IDENTIFIER hi;
 990         REG_PORT_LIST rpl;      /* variable-length array */
 991 /* ATTRIBUTE_BLOCK   ab; */
 992 } REG_HBA;
 993
 994 /*
 995  * Register HBA Attributes (RHAT)
 996  */
 997 typedef struct {
 998         struct lpfc_name HBA_PortName;
 999         ATTRIBUTE_BLOCK ab;
1000 } REG_HBA_ATTRIBUTE;
1001
1002 /*
1003  * Register Port Attributes (RPA)
1004  */
1005 typedef struct {
1006         struct lpfc_name PortName;
1007         ATTRIBUTE_BLOCK ab;
1008 } REG_PORT_ATTRIBUTE;
1009
1010 /*
1011  * Get Registered HBA List (GRHL) Accept Payload Format
1012  */
1013 typedef struct {
1014         uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1015         struct lpfc_name HBA_PortName;  /* Variable-length array */
1016 } GRHL_ACC_PAYLOAD;
1017
1018 /*
1019  * Get Registered Port List (GRPL) Accept Payload Format
1020  */
1021 typedef struct {
1022         uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1023         PORT_ENTRY Reg_Port_Entry[1];   /* Variable-length array */
1024 } GRPL_ACC_PAYLOAD;
1025
1026 /*
1027  * Get Port Attributes (GPAT) Accept Payload Format
1028  */
1029
1030 typedef struct {
1031         ATTRIBUTE_BLOCK pab;
1032 } GPAT_ACC_PAYLOAD;
1033
1034
1035 /*
1036  *  Begin HBA configuration parameters.
1037  *  The PCI configuration register BAR assignments are:
1038  *  BAR0, offset 0x10 - SLIM base memory address
1039  *  BAR1, offset 0x14 - SLIM base memory high address
1040  *  BAR2, offset 0x18 - REGISTER base memory address
1041  *  BAR3, offset 0x1c - REGISTER base memory high address
1042  *  BAR4, offset 0x20 - BIU I/O registers
1043  *  BAR5, offset 0x24 - REGISTER base io high address
1044  */
1045
1046 /* Number of rings currently used and available. */
1047 #define MAX_CONFIGURED_RINGS     3
1048 #define MAX_RINGS                4
1049
1050 /* IOCB / Mailbox is owned by FireFly */
1051 #define OWN_CHIP        1
1052
1053 /* IOCB / Mailbox is owned by Host */
1054 #define OWN_HOST        0
1055
1056 /* Number of 4-byte words in an IOCB. */
1057 #define IOCB_WORD_SZ    8
1058
1059 /* defines for type field in fc header */
1060 #define FC_ELS_DATA     0x1
1061 #define FC_LLC_SNAP     0x5
1062 #define FC_FCP_DATA     0x8
1063 #define FC_COMMON_TRANSPORT_ULP 0x20
1064
1065 /* defines for rctl field in fc header */
1066 #define FC_DEV_DATA     0x0
1067 #define FC_UNSOL_CTL    0x2
1068 #define FC_SOL_CTL      0x3
1069 #define FC_UNSOL_DATA   0x4
1070 #define FC_FCP_CMND     0x6
1071 #define FC_ELS_REQ      0x22
1072 #define FC_ELS_RSP      0x23
1073
1074 /* network headers for Dfctl field */
1075 #define FC_NET_HDR      0x20
1076
1077 /* Start FireFly Register definitions */
1078 #define PCI_VENDOR_ID_EMULEX        0x10df
1079 #define PCI_DEVICE_ID_FIREFLY       0x1ae5
1080 #define PCI_DEVICE_ID_SAT_SMB       0xf011
1081 #define PCI_DEVICE_ID_SAT_MID       0xf015
1082 #define PCI_DEVICE_ID_RFLY          0xf095
1083 #define PCI_DEVICE_ID_PFLY          0xf098
1084 #define PCI_DEVICE_ID_LP101         0xf0a1
1085 #define PCI_DEVICE_ID_TFLY          0xf0a5
1086 #define PCI_DEVICE_ID_BSMB          0xf0d1
1087 #define PCI_DEVICE_ID_BMID          0xf0d5
1088 #define PCI_DEVICE_ID_ZSMB          0xf0e1
1089 #define PCI_DEVICE_ID_ZMID          0xf0e5
1090 #define PCI_DEVICE_ID_NEPTUNE       0xf0f5
1091 #define PCI_DEVICE_ID_NEPTUNE_SCSP  0xf0f6
1092 #define PCI_DEVICE_ID_NEPTUNE_DCSP  0xf0f7
1093 #define PCI_DEVICE_ID_SAT           0xf100
1094 #define PCI_DEVICE_ID_SAT_SCSP      0xf111
1095 #define PCI_DEVICE_ID_SAT_DCSP      0xf112
1096 #define PCI_DEVICE_ID_SUPERFLY      0xf700
1097 #define PCI_DEVICE_ID_DRAGONFLY     0xf800
1098 #define PCI_DEVICE_ID_CENTAUR       0xf900
1099 #define PCI_DEVICE_ID_PEGASUS       0xf980
1100 #define PCI_DEVICE_ID_THOR          0xfa00
1101 #define PCI_DEVICE_ID_VIPER         0xfb00
1102 #define PCI_DEVICE_ID_LP10000S      0xfc00
1103 #define PCI_DEVICE_ID_LP11000S      0xfc10
1104 #define PCI_DEVICE_ID_LPE11000S     0xfc20
1105 #define PCI_DEVICE_ID_SAT_S         0xfc40
1106 #define PCI_DEVICE_ID_HELIOS        0xfd00
1107 #define PCI_DEVICE_ID_HELIOS_SCSP   0xfd11
1108 #define PCI_DEVICE_ID_HELIOS_DCSP   0xfd12
1109 #define PCI_DEVICE_ID_ZEPHYR        0xfe00
1110 #define PCI_DEVICE_ID_ZEPHYR_SCSP   0xfe11
1111 #define PCI_DEVICE_ID_ZEPHYR_DCSP   0xfe12
1112
1113 #define JEDEC_ID_ADDRESS            0x0080001c
1114 #define FIREFLY_JEDEC_ID            0x1ACC
1115 #define SUPERFLY_JEDEC_ID           0x0020
1116 #define DRAGONFLY_JEDEC_ID          0x0021
1117 #define DRAGONFLY_V2_JEDEC_ID       0x0025
1118 #define CENTAUR_2G_JEDEC_ID         0x0026
1119 #define CENTAUR_1G_JEDEC_ID         0x0028
1120 #define PEGASUS_ORION_JEDEC_ID      0x0036
1121 #define PEGASUS_JEDEC_ID            0x0038
1122 #define THOR_JEDEC_ID               0x0012
1123 #define HELIOS_JEDEC_ID             0x0364
1124 #define ZEPHYR_JEDEC_ID             0x0577
1125 #define VIPER_JEDEC_ID              0x4838
1126 #define SATURN_JEDEC_ID             0x1004
1127
1128 #define JEDEC_ID_MASK               0x0FFFF000
1129 #define JEDEC_ID_SHIFT              12
1130 #define FC_JEDEC_ID(id)             ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1131
1132 typedef struct {                /* FireFly BIU registers */
1133         uint32_t hostAtt;       /* See definitions for Host Attention
1134                                    register */
1135         uint32_t chipAtt;       /* See definitions for Chip Attention
1136                                    register */
1137         uint32_t hostStatus;    /* See definitions for Host Status register */
1138         uint32_t hostControl;   /* See definitions for Host Control register */
1139         uint32_t buiConfig;     /* See definitions for BIU configuration
1140                                    register */
1141 } FF_REGS;
1142
1143 /* IO Register size in bytes */
1144 #define FF_REG_AREA_SIZE       256
1145
1146 /* Host Attention Register */
1147
1148 #define HA_REG_OFFSET  0        /* Byte offset from register base address */
1149
1150 #define HA_R0RE_REQ    0x00000001       /* Bit  0 */
1151 #define HA_R0CE_RSP    0x00000002       /* Bit  1 */
1152 #define HA_R0ATT       0x00000008       /* Bit  3 */
1153 #define HA_R1RE_REQ    0x00000010       /* Bit  4 */
1154 #define HA_R1CE_RSP    0x00000020       /* Bit  5 */
1155 #define HA_R1ATT       0x00000080       /* Bit  7 */
1156 #define HA_R2RE_REQ    0x00000100       /* Bit  8 */
1157 #define HA_R2CE_RSP    0x00000200       /* Bit  9 */
1158 #define HA_R2ATT       0x00000800       /* Bit 11 */
1159 #define HA_R3RE_REQ    0x00001000       /* Bit 12 */
1160 #define HA_R3CE_RSP    0x00002000       /* Bit 13 */
1161 #define HA_R3ATT       0x00008000       /* Bit 15 */
1162 #define HA_LATT        0x20000000       /* Bit 29 */
1163 #define HA_MBATT       0x40000000       /* Bit 30 */
1164 #define HA_ERATT       0x80000000       /* Bit 31 */
1165
1166 #define HA_RXRE_REQ    0x00000001       /* Bit  0 */
1167 #define HA_RXCE_RSP    0x00000002       /* Bit  1 */
1168 #define HA_RXATT       0x00000008       /* Bit  3 */
1169 #define HA_RXMASK      0x0000000f
1170
1171 /* Chip Attention Register */
1172
1173 #define CA_REG_OFFSET  4        /* Byte offset from register base address */
1174
1175 #define CA_R0CE_REQ    0x00000001       /* Bit  0 */
1176 #define CA_R0RE_RSP    0x00000002       /* Bit  1 */
1177 #define CA_R0ATT       0x00000008       /* Bit  3 */
1178 #define CA_R1CE_REQ    0x00000010       /* Bit  4 */
1179 #define CA_R1RE_RSP    0x00000020       /* Bit  5 */
1180 #define CA_R1ATT       0x00000080       /* Bit  7 */
1181 #define CA_R2CE_REQ    0x00000100       /* Bit  8 */
1182 #define CA_R2RE_RSP    0x00000200       /* Bit  9 */
1183 #define CA_R2ATT       0x00000800       /* Bit 11 */
1184 #define CA_R3CE_REQ    0x00001000       /* Bit 12 */
1185 #define CA_R3RE_RSP    0x00002000       /* Bit 13 */
1186 #define CA_R3ATT       0x00008000       /* Bit 15 */
1187 #define CA_MBATT       0x40000000       /* Bit 30 */
1188
1189 /* Host Status Register */
1190
1191 #define HS_REG_OFFSET  8        /* Byte offset from register base address */
1192
1193 #define HS_MBRDY       0x00400000       /* Bit 22 */
1194 #define HS_FFRDY       0x00800000       /* Bit 23 */
1195 #define HS_FFER8       0x01000000       /* Bit 24 */
1196 #define HS_FFER7       0x02000000       /* Bit 25 */
1197 #define HS_FFER6       0x04000000       /* Bit 26 */
1198 #define HS_FFER5       0x08000000       /* Bit 27 */
1199 #define HS_FFER4       0x10000000       /* Bit 28 */
1200 #define HS_FFER3       0x20000000       /* Bit 29 */
1201 #define HS_FFER2       0x40000000       /* Bit 30 */
1202 #define HS_FFER1       0x80000000       /* Bit 31 */
1203 #define HS_FFERM       0xFF000000       /* Mask for error bits 31:24 */
1204
1205 /* Host Control Register */
1206
1207 #define HC_REG_OFFSET  12       /* Word offset from register base address */
1208
1209 #define HC_MBINT_ENA   0x00000001       /* Bit  0 */
1210 #define HC_R0INT_ENA   0x00000002       /* Bit  1 */
1211 #define HC_R1INT_ENA   0x00000004       /* Bit  2 */
1212 #define HC_R2INT_ENA   0x00000008       /* Bit  3 */
1213 #define HC_R3INT_ENA   0x00000010       /* Bit  4 */
1214 #define HC_INITHBI     0x02000000       /* Bit 25 */
1215 #define HC_INITMB      0x04000000       /* Bit 26 */
1216 #define HC_INITFF      0x08000000       /* Bit 27 */
1217 #define HC_LAINT_ENA   0x20000000       /* Bit 29 */
1218 #define HC_ERINT_ENA   0x80000000       /* Bit 31 */
1219
1220 /* Mailbox Commands */
1221 #define MBX_SHUTDOWN        0x00        /* terminate testing */
1222 #define MBX_LOAD_SM         0x01
1223 #define MBX_READ_NV         0x02
1224 #define MBX_WRITE_NV        0x03
1225 #define MBX_RUN_BIU_DIAG    0x04
1226 #define MBX_INIT_LINK       0x05
1227 #define MBX_DOWN_LINK       0x06
1228 #define MBX_CONFIG_LINK     0x07
1229 #define MBX_CONFIG_RING     0x09
1230 #define MBX_RESET_RING      0x0A
1231 #define MBX_READ_CONFIG     0x0B
1232 #define MBX_READ_RCONFIG    0x0C
1233 #define MBX_READ_SPARM      0x0D
1234 #define MBX_READ_STATUS     0x0E
1235 #define MBX_READ_RPI        0x0F
1236 #define MBX_READ_XRI        0x10
1237 #define MBX_READ_REV        0x11
1238 #define MBX_READ_LNK_STAT   0x12
1239 #define MBX_REG_LOGIN       0x13
1240 #define MBX_UNREG_LOGIN     0x14
1241 #define MBX_READ_LA         0x15
1242 #define MBX_CLEAR_LA        0x16
1243 #define MBX_DUMP_MEMORY     0x17
1244 #define MBX_DUMP_CONTEXT    0x18
1245 #define MBX_RUN_DIAGS       0x19
1246 #define MBX_RESTART         0x1A
1247 #define MBX_UPDATE_CFG      0x1B
1248 #define MBX_DOWN_LOAD       0x1C
1249 #define MBX_DEL_LD_ENTRY    0x1D
1250 #define MBX_RUN_PROGRAM     0x1E
1251 #define MBX_SET_MASK        0x20
1252 #define MBX_SET_SLIM        0x21
1253 #define MBX_UNREG_D_ID      0x23
1254 #define MBX_KILL_BOARD      0x24
1255 #define MBX_CONFIG_FARP     0x25
1256 #define MBX_BEACON          0x2A
1257
1258 #define MBX_LOAD_AREA       0x81
1259 #define MBX_RUN_BIU_DIAG64  0x84
1260 #define MBX_CONFIG_PORT     0x88
1261 #define MBX_READ_SPARM64    0x8D
1262 #define MBX_READ_RPI64      0x8F
1263 #define MBX_REG_LOGIN64     0x93
1264 #define MBX_READ_LA64       0x95
1265
1266 #define MBX_FLASH_WR_ULA    0x98
1267 #define MBX_SET_DEBUG       0x99
1268 #define MBX_LOAD_EXP_ROM    0x9C
1269
1270 #define MBX_MAX_CMDS        0x9D
1271 #define MBX_SLI2_CMD_MASK   0x80
1272
1273 /* IOCB Commands */
1274
1275 #define CMD_RCV_SEQUENCE_CX     0x01
1276 #define CMD_XMIT_SEQUENCE_CR    0x02
1277 #define CMD_XMIT_SEQUENCE_CX    0x03
1278 #define CMD_XMIT_BCAST_CN       0x04
1279 #define CMD_XMIT_BCAST_CX       0x05
1280 #define CMD_QUE_RING_BUF_CN     0x06
1281 #define CMD_QUE_XRI_BUF_CX      0x07
1282 #define CMD_IOCB_CONTINUE_CN    0x08
1283 #define CMD_RET_XRI_BUF_CX      0x09
1284 #define CMD_ELS_REQUEST_CR      0x0A
1285 #define CMD_ELS_REQUEST_CX      0x0B
1286 #define CMD_RCV_ELS_REQ_CX      0x0D
1287 #define CMD_ABORT_XRI_CN        0x0E
1288 #define CMD_ABORT_XRI_CX        0x0F
1289 #define CMD_CLOSE_XRI_CN        0x10
1290 #define CMD_CLOSE_XRI_CX        0x11
1291 #define CMD_CREATE_XRI_CR       0x12
1292 #define CMD_CREATE_XRI_CX       0x13
1293 #define CMD_GET_RPI_CN          0x14
1294 #define CMD_XMIT_ELS_RSP_CX     0x15
1295 #define CMD_GET_RPI_CR          0x16
1296 #define CMD_XRI_ABORTED_CX      0x17
1297 #define CMD_FCP_IWRITE_CR       0x18
1298 #define CMD_FCP_IWRITE_CX       0x19
1299 #define CMD_FCP_IREAD_CR        0x1A
1300 #define CMD_FCP_IREAD_CX        0x1B
1301 #define CMD_FCP_ICMND_CR        0x1C
1302 #define CMD_FCP_ICMND_CX        0x1D
1303 #define CMD_FCP_TSEND_CX        0x1F
1304 #define CMD_FCP_TRECEIVE_CX     0x21
1305 #define CMD_FCP_TRSP_CX         0x23
1306 #define CMD_FCP_AUTO_TRSP_CX    0x29
1307
1308 #define CMD_ADAPTER_MSG         0x20
1309 #define CMD_ADAPTER_DUMP        0x22
1310
1311 /*  SLI_2 IOCB Command Set */
1312
1313 #define CMD_RCV_SEQUENCE64_CX   0x81
1314 #define CMD_XMIT_SEQUENCE64_CR  0x82
1315 #define CMD_XMIT_SEQUENCE64_CX  0x83
1316 #define CMD_XMIT_BCAST64_CN     0x84
1317 #define CMD_XMIT_BCAST64_CX     0x85
1318 #define CMD_QUE_RING_BUF64_CN   0x86
1319 #define CMD_QUE_XRI_BUF64_CX    0x87
1320 #define CMD_IOCB_CONTINUE64_CN  0x88
1321 #define CMD_RET_XRI_BUF64_CX    0x89
1322 #define CMD_ELS_REQUEST64_CR    0x8A
1323 #define CMD_ELS_REQUEST64_CX    0x8B
1324 #define CMD_ABORT_MXRI64_CN     0x8C
1325 #define CMD_RCV_ELS_REQ64_CX    0x8D
1326 #define CMD_XMIT_ELS_RSP64_CX   0x95
1327 #define CMD_FCP_IWRITE64_CR     0x98
1328 #define CMD_FCP_IWRITE64_CX     0x99
1329 #define CMD_FCP_IREAD64_CR      0x9A
1330 #define CMD_FCP_IREAD64_CX      0x9B
1331 #define CMD_FCP_ICMND64_CR      0x9C
1332 #define CMD_FCP_ICMND64_CX      0x9D
1333 #define CMD_FCP_TSEND64_CX      0x9F
1334 #define CMD_FCP_TRECEIVE64_CX   0xA1
1335 #define CMD_FCP_TRSP64_CX       0xA3
1336
1337 #define CMD_GEN_REQUEST64_CR    0xC2
1338 #define CMD_GEN_REQUEST64_CX    0xC3
1339
1340 #define CMD_MAX_IOCB_CMD        0xE6
1341 #define CMD_IOCB_MASK           0xff
1342
1343 #define MAX_MSG_DATA            28      /* max msg data in CMD_ADAPTER_MSG
1344                                            iocb */
1345 #define LPFC_MAX_ADPTMSG         32     /* max msg data */
1346 /*
1347  *  Define Status
1348  */
1349 #define MBX_SUCCESS                 0
1350 #define MBXERR_NUM_RINGS            1
1351 #define MBXERR_NUM_IOCBS            2
1352 #define MBXERR_IOCBS_EXCEEDED       3
1353 #define MBXERR_BAD_RING_NUMBER      4
1354 #define MBXERR_MASK_ENTRIES_RANGE   5
1355 #define MBXERR_MASKS_EXCEEDED       6
1356 #define MBXERR_BAD_PROFILE          7
1357 #define MBXERR_BAD_DEF_CLASS        8
1358 #define MBXERR_BAD_MAX_RESPONDER    9
1359 #define MBXERR_BAD_MAX_ORIGINATOR   10
1360 #define MBXERR_RPI_REGISTERED       11
1361 #define MBXERR_RPI_FULL             12
1362 #define MBXERR_NO_RESOURCES         13
1363 #define MBXERR_BAD_RCV_LENGTH       14
1364 #define MBXERR_DMA_ERROR            15
1365 #define MBXERR_ERROR                16
1366 #define MBX_NOT_FINISHED           255
1367
1368 #define MBX_BUSY                   0xffffff /* Attempted cmd to busy Mailbox */
1369 #define MBX_TIMEOUT                0xfffffe /* time-out expired waiting for */
1370
1371 /*
1372  *    Begin Structure Definitions for Mailbox Commands
1373  */
1374
1375 typedef struct {
1376 #ifdef __BIG_ENDIAN_BITFIELD
1377         uint8_t tval;
1378         uint8_t tmask;
1379         uint8_t rval;
1380         uint8_t rmask;
1381 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1382         uint8_t rmask;
1383         uint8_t rval;
1384         uint8_t tmask;
1385         uint8_t tval;
1386 #endif
1387 } RR_REG;
1388
1389 struct ulp_bde {
1390         uint32_t bdeAddress;
1391 #ifdef __BIG_ENDIAN_BITFIELD
1392         uint32_t bdeReserved:4;
1393         uint32_t bdeAddrHigh:4;
1394         uint32_t bdeSize:24;
1395 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1396         uint32_t bdeSize:24;
1397         uint32_t bdeAddrHigh:4;
1398         uint32_t bdeReserved:4;
1399 #endif
1400 };
1401
1402 struct ulp_bde64 {      /* SLI-2 */
1403         union ULP_BDE_TUS {
1404                 uint32_t w;
1405                 struct {
1406 #ifdef __BIG_ENDIAN_BITFIELD
1407                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
1408                                                    VALUE !! */
1409                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
1410 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1411                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
1412                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
1413                                                    VALUE !! */
1414 #endif
1415
1416 #define BUFF_USE_RSVD       0x01        /* bdeFlags */
1417 #define BUFF_USE_INTRPT     0x02        /* Not Implemented with LP6000 */
1418 #define BUFF_USE_CMND       0x04        /* Optional, 1=cmd/rsp 0=data buffer */
1419 #define BUFF_USE_RCV        0x08        /*  "" "", 1=rcv buffer, 0=xmit
1420                                             buffer */
1421 #define BUFF_TYPE_32BIT     0x10        /*  "" "", 1=32 bit addr 0=64 bit
1422                                             addr */
1423 #define BUFF_TYPE_SPECIAL   0x20        /* Not Implemented with LP6000  */
1424 #define BUFF_TYPE_BDL       0x40        /* Optional,  may be set in BDL */
1425 #define BUFF_TYPE_INVALID   0x80        /*  ""  "" */
1426                 } f;
1427         } tus;
1428         uint32_t addrLow;
1429         uint32_t addrHigh;
1430 };
1431 #define BDE64_SIZE_WORD 0
1432 #define BPL64_SIZE_WORD 0x40
1433
1434 typedef struct ULP_BDL {        /* SLI-2 */
1435 #ifdef __BIG_ENDIAN_BITFIELD
1436         uint32_t bdeFlags:8;    /* BDL Flags */
1437         uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
1438 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1439         uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
1440         uint32_t bdeFlags:8;    /* BDL Flags */
1441 #endif
1442
1443         uint32_t addrLow;       /* Address 0:31 */
1444         uint32_t addrHigh;      /* Address 32:63 */
1445         uint32_t ulpIoTag32;    /* Can be used for 32 bit I/O Tag */
1446 } ULP_BDL;
1447
1448 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1449
1450 typedef struct {
1451 #ifdef __BIG_ENDIAN_BITFIELD
1452         uint32_t rsvd2:25;
1453         uint32_t acknowledgment:1;
1454         uint32_t version:1;
1455         uint32_t erase_or_prog:1;
1456         uint32_t update_flash:1;
1457         uint32_t update_ram:1;
1458         uint32_t method:1;
1459         uint32_t load_cmplt:1;
1460 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1461         uint32_t load_cmplt:1;
1462         uint32_t method:1;
1463         uint32_t update_ram:1;
1464         uint32_t update_flash:1;
1465         uint32_t erase_or_prog:1;
1466         uint32_t version:1;
1467         uint32_t acknowledgment:1;
1468         uint32_t rsvd2:25;
1469 #endif
1470
1471         uint32_t dl_to_adr_low;
1472         uint32_t dl_to_adr_high;
1473         uint32_t dl_len;
1474         union {
1475                 uint32_t dl_from_mbx_offset;
1476                 struct ulp_bde dl_from_bde;
1477                 struct ulp_bde64 dl_from_bde64;
1478         } un;
1479
1480 } LOAD_SM_VAR;
1481
1482 /* Structure for MB Command READ_NVPARM (02) */
1483
1484 typedef struct {
1485         uint32_t rsvd1[3];      /* Read as all one's */
1486         uint32_t rsvd2;         /* Read as all zero's */
1487         uint32_t portname[2];   /* N_PORT name */
1488         uint32_t nodename[2];   /* NODE name */
1489
1490 #ifdef __BIG_ENDIAN_BITFIELD
1491         uint32_t pref_DID:24;
1492         uint32_t hardAL_PA:8;
1493 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1494         uint32_t hardAL_PA:8;
1495         uint32_t pref_DID:24;
1496 #endif
1497
1498         uint32_t rsvd3[21];     /* Read as all one's */
1499 } READ_NV_VAR;
1500
1501 /* Structure for MB Command WRITE_NVPARMS (03) */
1502
1503 typedef struct {
1504         uint32_t rsvd1[3];      /* Must be all one's */
1505         uint32_t rsvd2;         /* Must be all zero's */
1506         uint32_t portname[2];   /* N_PORT name */
1507         uint32_t nodename[2];   /* NODE name */
1508
1509 #ifdef __BIG_ENDIAN_BITFIELD
1510         uint32_t pref_DID:24;
1511         uint32_t hardAL_PA:8;
1512 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1513         uint32_t hardAL_PA:8;
1514         uint32_t pref_DID:24;
1515 #endif
1516
1517         uint32_t rsvd3[21];     /* Must be all one's */
1518 } WRITE_NV_VAR;
1519
1520 /* Structure for MB Command RUN_BIU_DIAG (04) */
1521 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1522
1523 typedef struct {
1524         uint32_t rsvd1;
1525         union {
1526                 struct {
1527                         struct ulp_bde xmit_bde;
1528                         struct ulp_bde rcv_bde;
1529                 } s1;
1530                 struct {
1531                         struct ulp_bde64 xmit_bde64;
1532                         struct ulp_bde64 rcv_bde64;
1533                 } s2;
1534         } un;
1535 } BIU_DIAG_VAR;
1536
1537 /* Structure for MB Command INIT_LINK (05) */
1538
1539 typedef struct {
1540 #ifdef __BIG_ENDIAN_BITFIELD
1541         uint32_t rsvd1:24;
1542         uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1543 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1544         uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1545         uint32_t rsvd1:24;
1546 #endif
1547
1548 #ifdef __BIG_ENDIAN_BITFIELD
1549         uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
1550         uint8_t rsvd2;
1551         uint16_t link_flags;
1552 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1553         uint16_t link_flags;
1554         uint8_t rsvd2;
1555         uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
1556 #endif
1557
1558 #define FLAGS_LOCAL_LB               0x01 /* link_flags (=1) ENDEC loopback */
1559 #define FLAGS_TOPOLOGY_MODE_LOOP_PT  0x00 /* Attempt loop then pt-pt */
1560 #define FLAGS_TOPOLOGY_MODE_PT_PT    0x02 /* Attempt pt-pt only */
1561 #define FLAGS_TOPOLOGY_MODE_LOOP     0x04 /* Attempt loop only */
1562 #define FLAGS_TOPOLOGY_MODE_PT_LOOP  0x06 /* Attempt pt-pt then loop */
1563 #define FLAGS_LIRP_LILP              0x80 /* LIRP / LILP is disabled */
1564
1565 #define FLAGS_TOPOLOGY_FAILOVER      0x0400     /* Bit 10 */
1566 #define FLAGS_LINK_SPEED             0x0800     /* Bit 11 */
1567 #define FLAGS_IMED_ABORT             0x04000    /* Bit 14 */
1568
1569         uint32_t link_speed;
1570 #define LINK_SPEED_AUTO 0       /* Auto selection */
1571 #define LINK_SPEED_1G   1       /* 1 Gigabaud */
1572 #define LINK_SPEED_2G   2       /* 2 Gigabaud */
1573 #define LINK_SPEED_4G   4       /* 4 Gigabaud */
1574 #define LINK_SPEED_8G   8       /* 8 Gigabaud */
1575 #define LINK_SPEED_10G   16      /* 10 Gigabaud */
1576
1577 } INIT_LINK_VAR;
1578
1579 /* Structure for MB Command DOWN_LINK (06) */
1580
1581 typedef struct {
1582         uint32_t rsvd1;
1583 } DOWN_LINK_VAR;
1584
1585 /* Structure for MB Command CONFIG_LINK (07) */
1586
1587 typedef struct {
1588 #ifdef __BIG_ENDIAN_BITFIELD
1589         uint32_t cr:1;
1590         uint32_t ci:1;
1591         uint32_t cr_delay:6;
1592         uint32_t cr_count:8;
1593         uint32_t rsvd1:8;
1594         uint32_t MaxBBC:8;
1595 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1596         uint32_t MaxBBC:8;
1597         uint32_t rsvd1:8;
1598         uint32_t cr_count:8;
1599         uint32_t cr_delay:6;
1600         uint32_t ci:1;
1601         uint32_t cr:1;
1602 #endif
1603
1604         uint32_t myId;
1605         uint32_t rsvd2;
1606         uint32_t edtov;
1607         uint32_t arbtov;
1608         uint32_t ratov;
1609         uint32_t rttov;
1610         uint32_t altov;
1611         uint32_t crtov;
1612         uint32_t citov;
1613 #ifdef __BIG_ENDIAN_BITFIELD
1614         uint32_t rrq_enable:1;
1615         uint32_t rrq_immed:1;
1616         uint32_t rsvd4:29;
1617         uint32_t ack0_enable:1;
1618 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1619         uint32_t ack0_enable:1;
1620         uint32_t rsvd4:29;
1621         uint32_t rrq_immed:1;
1622         uint32_t rrq_enable:1;
1623 #endif
1624 } CONFIG_LINK;
1625
1626 /* Structure for MB Command PART_SLIM (08)
1627  * will be removed since SLI1 is no longer supported!
1628  */
1629 typedef struct {
1630 #ifdef __BIG_ENDIAN_BITFIELD
1631         uint16_t offCiocb;
1632         uint16_t numCiocb;
1633         uint16_t offRiocb;
1634         uint16_t numRiocb;
1635 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1636         uint16_t numCiocb;
1637         uint16_t offCiocb;
1638         uint16_t numRiocb;
1639         uint16_t offRiocb;
1640 #endif
1641 } RING_DEF;
1642
1643 typedef struct {
1644 #ifdef __BIG_ENDIAN_BITFIELD
1645         uint32_t unused1:24;
1646         uint32_t numRing:8;
1647 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1648         uint32_t numRing:8;
1649         uint32_t unused1:24;
1650 #endif
1651
1652         RING_DEF ringdef[4];
1653         uint32_t hbainit;
1654 } PART_SLIM_VAR;
1655
1656 /* Structure for MB Command CONFIG_RING (09) */
1657
1658 typedef struct {
1659 #ifdef __BIG_ENDIAN_BITFIELD
1660         uint32_t unused2:6;
1661         uint32_t recvSeq:1;
1662         uint32_t recvNotify:1;
1663         uint32_t numMask:8;
1664         uint32_t profile:8;
1665         uint32_t unused1:4;
1666         uint32_t ring:4;
1667 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1668         uint32_t ring:4;
1669         uint32_t unused1:4;
1670         uint32_t profile:8;
1671         uint32_t numMask:8;
1672         uint32_t recvNotify:1;
1673         uint32_t recvSeq:1;
1674         uint32_t unused2:6;
1675 #endif
1676
1677 #ifdef __BIG_ENDIAN_BITFIELD
1678         uint16_t maxRespXchg;
1679         uint16_t maxOrigXchg;
1680 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1681         uint16_t maxOrigXchg;
1682         uint16_t maxRespXchg;
1683 #endif
1684
1685         RR_REG rrRegs[6];
1686 } CONFIG_RING_VAR;
1687
1688 /* Structure for MB Command RESET_RING (10) */
1689
1690 typedef struct {
1691         uint32_t ring_no;
1692 } RESET_RING_VAR;
1693
1694 /* Structure for MB Command READ_CONFIG (11) */
1695
1696 typedef struct {
1697 #ifdef __BIG_ENDIAN_BITFIELD
1698         uint32_t cr:1;
1699         uint32_t ci:1;
1700         uint32_t cr_delay:6;
1701         uint32_t cr_count:8;
1702         uint32_t InitBBC:8;
1703         uint32_t MaxBBC:8;
1704 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1705         uint32_t MaxBBC:8;
1706         uint32_t InitBBC:8;
1707         uint32_t cr_count:8;
1708         uint32_t cr_delay:6;
1709         uint32_t ci:1;
1710         uint32_t cr:1;
1711 #endif
1712
1713 #ifdef __BIG_ENDIAN_BITFIELD
1714         uint32_t topology:8;
1715         uint32_t myDid:24;
1716 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1717         uint32_t myDid:24;
1718         uint32_t topology:8;
1719 #endif
1720
1721         /* Defines for topology (defined previously) */
1722 #ifdef __BIG_ENDIAN_BITFIELD
1723         uint32_t AR:1;
1724         uint32_t IR:1;
1725         uint32_t rsvd1:29;
1726         uint32_t ack0:1;
1727 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1728         uint32_t ack0:1;
1729         uint32_t rsvd1:29;
1730         uint32_t IR:1;
1731         uint32_t AR:1;
1732 #endif
1733
1734         uint32_t edtov;
1735         uint32_t arbtov;
1736         uint32_t ratov;
1737         uint32_t rttov;
1738         uint32_t altov;
1739         uint32_t lmt;
1740 #define LMT_RESERVED  0x000    /* Not used */
1741 #define LMT_1Gb       0x004
1742 #define LMT_2Gb       0x008
1743 #define LMT_4Gb       0x040
1744 #define LMT_8Gb       0x080
1745 #define LMT_10Gb      0x100
1746
1747
1748         uint32_t rsvd2;
1749         uint32_t rsvd3;
1750         uint32_t max_xri;
1751         uint32_t max_iocb;
1752         uint32_t max_rpi;
1753         uint32_t avail_xri;
1754         uint32_t avail_iocb;
1755         uint32_t avail_rpi;
1756         uint32_t default_rpi;
1757 } READ_CONFIG_VAR;
1758
1759 /* Structure for MB Command READ_RCONFIG (12) */
1760
1761 typedef struct {
1762 #ifdef __BIG_ENDIAN_BITFIELD
1763         uint32_t rsvd2:7;
1764         uint32_t recvNotify:1;
1765         uint32_t numMask:8;
1766         uint32_t profile:8;
1767         uint32_t rsvd1:4;
1768         uint32_t ring:4;
1769 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1770         uint32_t ring:4;
1771         uint32_t rsvd1:4;
1772         uint32_t profile:8;
1773         uint32_t numMask:8;
1774         uint32_t recvNotify:1;
1775         uint32_t rsvd2:7;
1776 #endif
1777
1778 #ifdef __BIG_ENDIAN_BITFIELD
1779         uint16_t maxResp;
1780         uint16_t maxOrig;
1781 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1782         uint16_t maxOrig;
1783         uint16_t maxResp;
1784 #endif
1785
1786         RR_REG rrRegs[6];
1787
1788 #ifdef __BIG_ENDIAN_BITFIELD
1789         uint16_t cmdRingOffset;
1790         uint16_t cmdEntryCnt;
1791         uint16_t rspRingOffset;
1792         uint16_t rspEntryCnt;
1793         uint16_t nextCmdOffset;
1794         uint16_t rsvd3;
1795         uint16_t nextRspOffset;
1796         uint16_t rsvd4;
1797 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1798         uint16_t cmdEntryCnt;
1799         uint16_t cmdRingOffset;
1800         uint16_t rspEntryCnt;
1801         uint16_t rspRingOffset;
1802         uint16_t rsvd3;
1803         uint16_t nextCmdOffset;
1804         uint16_t rsvd4;
1805         uint16_t nextRspOffset;
1806 #endif
1807 } READ_RCONF_VAR;
1808
1809 /* Structure for MB Command READ_SPARM (13) */
1810 /* Structure for MB Command READ_SPARM64 (0x8D) */
1811
1812 typedef struct {
1813         uint32_t rsvd1;
1814         uint32_t rsvd2;
1815         union {
1816                 struct ulp_bde sp; /* This BDE points to struct serv_parm
1817                                       structure */
1818                 struct ulp_bde64 sp64;
1819         } un;
1820 } READ_SPARM_VAR;
1821
1822 /* Structure for MB Command READ_STATUS (14) */
1823
1824 typedef struct {
1825 #ifdef __BIG_ENDIAN_BITFIELD
1826         uint32_t rsvd1:31;
1827         uint32_t clrCounters:1;
1828         uint16_t activeXriCnt;
1829         uint16_t activeRpiCnt;
1830 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1831         uint32_t clrCounters:1;
1832         uint32_t rsvd1:31;
1833         uint16_t activeRpiCnt;
1834         uint16_t activeXriCnt;
1835 #endif
1836
1837         uint32_t xmitByteCnt;
1838         uint32_t rcvByteCnt;
1839         uint32_t xmitFrameCnt;
1840         uint32_t rcvFrameCnt;
1841         uint32_t xmitSeqCnt;
1842         uint32_t rcvSeqCnt;
1843         uint32_t totalOrigExchanges;
1844         uint32_t totalRespExchanges;
1845         uint32_t rcvPbsyCnt;
1846         uint32_t rcvFbsyCnt;
1847 } READ_STATUS_VAR;
1848
1849 /* Structure for MB Command READ_RPI (15) */
1850 /* Structure for MB Command READ_RPI64 (0x8F) */
1851
1852 typedef struct {
1853 #ifdef __BIG_ENDIAN_BITFIELD
1854         uint16_t nextRpi;
1855         uint16_t reqRpi;
1856         uint32_t rsvd2:8;
1857         uint32_t DID:24;
1858 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1859         uint16_t reqRpi;
1860         uint16_t nextRpi;
1861         uint32_t DID:24;
1862         uint32_t rsvd2:8;
1863 #endif
1864
1865         union {
1866                 struct ulp_bde sp;
1867                 struct ulp_bde64 sp64;
1868         } un;
1869
1870 } READ_RPI_VAR;
1871
1872 /* Structure for MB Command READ_XRI (16) */
1873
1874 typedef struct {
1875 #ifdef __BIG_ENDIAN_BITFIELD
1876         uint16_t nextXri;
1877         uint16_t reqXri;
1878         uint16_t rsvd1;
1879         uint16_t rpi;
1880         uint32_t rsvd2:8;
1881         uint32_t DID:24;
1882         uint32_t rsvd3:8;
1883         uint32_t SID:24;
1884         uint32_t rsvd4;
1885         uint8_t seqId;
1886         uint8_t rsvd5;
1887         uint16_t seqCount;
1888         uint16_t oxId;
1889         uint16_t rxId;
1890         uint32_t rsvd6:30;
1891         uint32_t si:1;
1892         uint32_t exchOrig:1;
1893 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1894         uint16_t reqXri;
1895         uint16_t nextXri;
1896         uint16_t rpi;
1897         uint16_t rsvd1;
1898         uint32_t DID:24;
1899         uint32_t rsvd2:8;
1900         uint32_t SID:24;
1901         uint32_t rsvd3:8;
1902         uint32_t rsvd4;
1903         uint16_t seqCount;
1904         uint8_t rsvd5;
1905         uint8_t seqId;
1906         uint16_t rxId;
1907         uint16_t oxId;
1908         uint32_t exchOrig:1;
1909         uint32_t si:1;
1910         uint32_t rsvd6:30;
1911 #endif
1912 } READ_XRI_VAR;
1913
1914 /* Structure for MB Command READ_REV (17) */
1915
1916 typedef struct {
1917 #ifdef __BIG_ENDIAN_BITFIELD
1918         uint32_t cv:1;
1919         uint32_t rr:1;
1920         uint32_t rsvd1:29;
1921         uint32_t rv:1;
1922 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1923         uint32_t rv:1;
1924         uint32_t rsvd1:29;
1925         uint32_t rr:1;
1926         uint32_t cv:1;
1927 #endif
1928
1929         uint32_t biuRev;
1930         uint32_t smRev;
1931         union {
1932                 uint32_t smFwRev;
1933                 struct {
1934 #ifdef __BIG_ENDIAN_BITFIELD
1935                         uint8_t ProgType;
1936                         uint8_t ProgId;
1937                         uint16_t ProgVer:4;
1938                         uint16_t ProgRev:4;
1939                         uint16_t ProgFixLvl:2;
1940                         uint16_t ProgDistType:2;
1941                         uint16_t DistCnt:4;
1942 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1943                         uint16_t DistCnt:4;
1944                         uint16_t ProgDistType:2;
1945                         uint16_t ProgFixLvl:2;
1946                         uint16_t ProgRev:4;
1947                         uint16_t ProgVer:4;
1948                         uint8_t ProgId;
1949                         uint8_t ProgType;
1950 #endif
1951
1952                 } b;
1953         } un;
1954         uint32_t endecRev;
1955 #ifdef __BIG_ENDIAN_BITFIELD
1956         uint8_t feaLevelHigh;
1957         uint8_t feaLevelLow;
1958         uint8_t fcphHigh;
1959         uint8_t fcphLow;
1960 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1961         uint8_t fcphLow;
1962         uint8_t fcphHigh;
1963         uint8_t feaLevelLow;
1964         uint8_t feaLevelHigh;
1965 #endif
1966
1967         uint32_t postKernRev;
1968         uint32_t opFwRev;
1969         uint8_t opFwName[16];
1970         uint32_t sli1FwRev;
1971         uint8_t sli1FwName[16];
1972         uint32_t sli2FwRev;
1973         uint8_t sli2FwName[16];
1974         uint32_t rsvd2;
1975         uint32_t RandomData[7];
1976 } READ_REV_VAR;
1977
1978 /* Structure for MB Command READ_LINK_STAT (18) */
1979
1980 typedef struct {
1981         uint32_t rsvd1;
1982         uint32_t linkFailureCnt;
1983         uint32_t lossSyncCnt;
1984
1985         uint32_t lossSignalCnt;
1986         uint32_t primSeqErrCnt;
1987         uint32_t invalidXmitWord;
1988         uint32_t crcCnt;
1989         uint32_t primSeqTimeout;
1990         uint32_t elasticOverrun;
1991         uint32_t arbTimeout;
1992 } READ_LNK_VAR;
1993
1994 /* Structure for MB Command REG_LOGIN (19) */
1995 /* Structure for MB Command REG_LOGIN64 (0x93) */
1996
1997 typedef struct {
1998 #ifdef __BIG_ENDIAN_BITFIELD
1999         uint16_t rsvd1;
2000         uint16_t rpi;
2001         uint32_t rsvd2:8;
2002         uint32_t did:24;
2003 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2004         uint16_t rpi;
2005         uint16_t rsvd1;
2006         uint32_t did:24;
2007         uint32_t rsvd2:8;
2008 #endif
2009
2010         union {
2011                 struct ulp_bde sp;
2012                 struct ulp_bde64 sp64;
2013         } un;
2014
2015 } REG_LOGIN_VAR;
2016
2017 /* Word 30 contents for REG_LOGIN */
2018 typedef union {
2019         struct {
2020 #ifdef __BIG_ENDIAN_BITFIELD
2021                 uint16_t rsvd1:12;
2022                 uint16_t wd30_class:4;
2023                 uint16_t xri;
2024 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2025                 uint16_t xri;
2026                 uint16_t wd30_class:4;
2027                 uint16_t rsvd1:12;
2028 #endif
2029         } f;
2030         uint32_t word;
2031 } REG_WD30;
2032
2033 /* Structure for MB Command UNREG_LOGIN (20) */
2034
2035 typedef struct {
2036 #ifdef __BIG_ENDIAN_BITFIELD
2037         uint16_t rsvd1;
2038         uint16_t rpi;
2039 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2040         uint16_t rpi;
2041         uint16_t rsvd1;
2042 #endif
2043 } UNREG_LOGIN_VAR;
2044
2045 /* Structure for MB Command UNREG_D_ID (0x23) */
2046
2047 typedef struct {
2048         uint32_t did;
2049 } UNREG_D_ID_VAR;
2050
2051 /* Structure for MB Command READ_LA (21) */
2052 /* Structure for MB Command READ_LA64 (0x95) */
2053
2054 typedef struct {
2055         uint32_t eventTag;      /* Event tag */
2056 #ifdef __BIG_ENDIAN_BITFIELD
2057         uint32_t rsvd1:22;
2058         uint32_t pb:1;
2059         uint32_t il:1;
2060         uint32_t attType:8;
2061 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2062         uint32_t attType:8;
2063         uint32_t il:1;
2064         uint32_t pb:1;
2065         uint32_t rsvd1:22;
2066 #endif
2067
2068 #define AT_RESERVED    0x00     /* Reserved - attType */
2069 #define AT_LINK_UP     0x01     /* Link is up */
2070 #define AT_LINK_DOWN   0x02     /* Link is down */
2071
2072 #ifdef __BIG_ENDIAN_BITFIELD
2073         uint8_t granted_AL_PA;
2074         uint8_t lipAlPs;
2075         uint8_t lipType;
2076         uint8_t topology;
2077 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2078         uint8_t topology;
2079         uint8_t lipType;
2080         uint8_t lipAlPs;
2081         uint8_t granted_AL_PA;
2082 #endif
2083
2084 #define TOPOLOGY_PT_PT 0x01     /* Topology is pt-pt / pt-fabric */
2085 #define TOPOLOGY_LOOP  0x02     /* Topology is FC-AL */
2086
2087         union {
2088                 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer
2089                                            to */
2090                 /* store the LILP AL_PA position map into */
2091                 struct ulp_bde64 lilpBde64;
2092         } un;
2093
2094 #ifdef __BIG_ENDIAN_BITFIELD
2095         uint32_t Dlu:1;
2096         uint32_t Dtf:1;
2097         uint32_t Drsvd2:14;
2098         uint32_t DlnkSpeed:8;
2099         uint32_t DnlPort:4;
2100         uint32_t Dtx:2;
2101         uint32_t Drx:2;
2102 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2103         uint32_t Drx:2;
2104         uint32_t Dtx:2;
2105         uint32_t DnlPort:4;
2106         uint32_t DlnkSpeed:8;
2107         uint32_t Drsvd2:14;
2108         uint32_t Dtf:1;
2109         uint32_t Dlu:1;
2110 #endif
2111
2112 #ifdef __BIG_ENDIAN_BITFIELD
2113         uint32_t Ulu:1;
2114         uint32_t Utf:1;
2115         uint32_t Ursvd2:14;
2116         uint32_t UlnkSpeed:8;
2117         uint32_t UnlPort:4;
2118         uint32_t Utx:2;
2119         uint32_t Urx:2;
2120 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2121         uint32_t Urx:2;
2122         uint32_t Utx:2;
2123         uint32_t UnlPort:4;
2124         uint32_t UlnkSpeed:8;
2125         uint32_t Ursvd2:14;
2126         uint32_t Utf:1;
2127         uint32_t Ulu:1;
2128 #endif
2129
2130 #define LA_UNKNW_LINK  0x0    /* lnkSpeed */
2131 #define LA_1GHZ_LINK   0x04   /* lnkSpeed */
2132 #define LA_2GHZ_LINK   0x08   /* lnkSpeed */
2133 #define LA_4GHZ_LINK   0x10   /* lnkSpeed */
2134 #define LA_8GHZ_LINK   0x20   /* lnkSpeed */
2135 #define LA_10GHZ_LINK  0x40   /* lnkSpeed */
2136
2137 } READ_LA_VAR;
2138
2139 /* Structure for MB Command CLEAR_LA (22) */
2140
2141 typedef struct {
2142         uint32_t eventTag;      /* Event tag */
2143         uint32_t rsvd1;
2144 } CLEAR_LA_VAR;
2145
2146 /* Structure for MB Command DUMP */
2147
2148 typedef struct {
2149 #ifdef __BIG_ENDIAN_BITFIELD
2150         uint32_t rsvd:25;
2151         uint32_t ra:1;
2152         uint32_t co:1;
2153         uint32_t cv:1;
2154         uint32_t type:4;
2155         uint32_t entry_index:16;
2156         uint32_t region_id:16;
2157 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2158         uint32_t type:4;
2159         uint32_t cv:1;
2160         uint32_t co:1;
2161         uint32_t ra:1;
2162         uint32_t rsvd:25;
2163         uint32_t region_id:16;
2164         uint32_t entry_index:16;
2165 #endif
2166
2167         uint32_t rsvd1;
2168         uint32_t word_cnt;
2169         uint32_t resp_offset;
2170 } DUMP_VAR;
2171
2172 #define  DMP_MEM_REG             0x1
2173 #define  DMP_NV_PARAMS           0x2
2174
2175 #define  DMP_REGION_VPD          0xe
2176 #define  DMP_VPD_SIZE            0x400  /* maximum amount of VPD */
2177 #define  DMP_RSP_OFFSET          0x14   /* word 5 contains first word of rsp */
2178 #define  DMP_RSP_SIZE            0x6C   /* maximum of 27 words of rsp data */
2179
2180
2181 /* Structure for MB Command CONFIG_PORT (0x88) */
2182 typedef struct {
2183         uint32_t pcbLen;
2184         uint32_t pcbLow;       /* bit 31:0  of memory based port config block */
2185         uint32_t pcbHigh;      /* bit 63:32 of memory based port config block */
2186         uint32_t hbainit[5];
2187 } CONFIG_PORT_VAR;
2188
2189 /* SLI-2 Port Control Block */
2190
2191 /* SLIM POINTER */
2192 #define SLIMOFF 0x30            /* WORD */
2193
2194 typedef struct _SLI2_RDSC {
2195         uint32_t cmdEntries;
2196         uint32_t cmdAddrLow;
2197         uint32_t cmdAddrHigh;
2198
2199         uint32_t rspEntries;
2200         uint32_t rspAddrLow;
2201         uint32_t rspAddrHigh;
2202 } SLI2_RDSC;
2203
2204 typedef struct _PCB {
2205 #ifdef __BIG_ENDIAN_BITFIELD
2206         uint32_t type:8;
2207 #define TYPE_NATIVE_SLI2       0x01;
2208         uint32_t feature:8;
2209 #define FEATURE_INITIAL_SLI2   0x01;
2210         uint32_t rsvd:12;
2211         uint32_t maxRing:4;
2212 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2213         uint32_t maxRing:4;
2214         uint32_t rsvd:12;
2215         uint32_t feature:8;
2216 #define FEATURE_INITIAL_SLI2   0x01;
2217         uint32_t type:8;
2218 #define TYPE_NATIVE_SLI2       0x01;
2219 #endif
2220
2221         uint32_t mailBoxSize;
2222         uint32_t mbAddrLow;
2223         uint32_t mbAddrHigh;
2224
2225         uint32_t hgpAddrLow;
2226         uint32_t hgpAddrHigh;
2227
2228         uint32_t pgpAddrLow;
2229         uint32_t pgpAddrHigh;
2230         SLI2_RDSC rdsc[MAX_RINGS];
2231 } PCB_t;
2232
2233 /* NEW_FEATURE */
2234 typedef struct {
2235 #ifdef __BIG_ENDIAN_BITFIELD
2236         uint32_t rsvd0:27;
2237         uint32_t discardFarp:1;
2238         uint32_t IPEnable:1;
2239         uint32_t nodeName:1;
2240         uint32_t portName:1;
2241         uint32_t filterEnable:1;
2242 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2243         uint32_t filterEnable:1;
2244         uint32_t portName:1;
2245         uint32_t nodeName:1;
2246         uint32_t IPEnable:1;
2247         uint32_t discardFarp:1;
2248         uint32_t rsvd:27;
2249 #endif
2250
2251         uint8_t portname[8];    /* Used to be struct lpfc_name */
2252         uint8_t nodename[8];
2253         uint32_t rsvd1;
2254         uint32_t rsvd2;
2255         uint32_t rsvd3;
2256         uint32_t IPAddress;
2257 } CONFIG_FARP_VAR;
2258
2259 /* Union of all Mailbox Command types */
2260 #define MAILBOX_CMD_WSIZE       32
2261 #define MAILBOX_CMD_SIZE        (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2262
2263 typedef union {
2264         uint32_t varWords[MAILBOX_CMD_WSIZE - 1];
2265         LOAD_SM_VAR varLdSM;    /* cmd =  1 (LOAD_SM)        */
2266         READ_NV_VAR varRDnvp;   /* cmd =  2 (READ_NVPARMS)   */
2267         WRITE_NV_VAR varWTnvp;  /* cmd =  3 (WRITE_NVPARMS)  */
2268         BIU_DIAG_VAR varBIUdiag;        /* cmd =  4 (RUN_BIU_DIAG)   */
2269         INIT_LINK_VAR varInitLnk;       /* cmd =  5 (INIT_LINK)      */
2270         DOWN_LINK_VAR varDwnLnk;        /* cmd =  6 (DOWN_LINK)      */
2271         CONFIG_LINK varCfgLnk;  /* cmd =  7 (CONFIG_LINK)    */
2272         PART_SLIM_VAR varSlim;  /* cmd =  8 (PART_SLIM)      */
2273         CONFIG_RING_VAR varCfgRing;     /* cmd =  9 (CONFIG_RING)    */
2274         RESET_RING_VAR varRstRing;      /* cmd = 10 (RESET_RING)     */
2275         READ_CONFIG_VAR varRdConfig;    /* cmd = 11 (READ_CONFIG)    */
2276         READ_RCONF_VAR varRdRConfig;    /* cmd = 12 (READ_RCONFIG)   */
2277         READ_SPARM_VAR varRdSparm;      /* cmd = 13 (READ_SPARM(64)) */
2278         READ_STATUS_VAR varRdStatus;    /* cmd = 14 (READ_STATUS)    */
2279         READ_RPI_VAR varRdRPI;  /* cmd = 15 (READ_RPI(64))   */
2280         READ_XRI_VAR varRdXRI;  /* cmd = 16 (READ_XRI)       */
2281         READ_REV_VAR varRdRev;  /* cmd = 17 (READ_REV)       */
2282         READ_LNK_VAR varRdLnk;  /* cmd = 18 (READ_LNK_STAT)  */
2283         REG_LOGIN_VAR varRegLogin;      /* cmd = 19 (REG_LOGIN(64))  */
2284         UNREG_LOGIN_VAR varUnregLogin;  /* cmd = 20 (UNREG_LOGIN)    */
2285         READ_LA_VAR varReadLA;  /* cmd = 21 (READ_LA(64))    */
2286         CLEAR_LA_VAR varClearLA;        /* cmd = 22 (CLEAR_LA)       */
2287         DUMP_VAR varDmp;        /* Warm Start DUMP mbx cmd   */
2288         UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID)   */
2289         CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)  NEW_FEATURE */
2290         CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT)  */
2291 } MAILVARIANTS;
2292
2293 /*
2294  * SLI-2 specific structures
2295  */
2296
2297 struct lpfc_hgp {
2298         __le32 cmdPutInx;
2299         __le32 rspGetInx;
2300 };
2301
2302 struct lpfc_pgp {
2303         __le32 cmdGetInx;
2304         __le32 rspPutInx;
2305 };
2306
2307 typedef struct _SLI2_DESC {
2308         struct lpfc_hgp host[MAX_RINGS];
2309         uint32_t unused1[16];
2310         struct lpfc_pgp port[MAX_RINGS];
2311 } SLI2_DESC;
2312
2313 typedef union {
2314         SLI2_DESC s2;
2315 } SLI_VAR;
2316
2317 typedef struct {
2318 #ifdef __BIG_ENDIAN_BITFIELD
2319         uint16_t mbxStatus;
2320         uint8_t mbxCommand;
2321         uint8_t mbxReserved:6;
2322         uint8_t mbxHc:1;
2323         uint8_t mbxOwner:1;     /* Low order bit first word */
2324 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2325         uint8_t mbxOwner:1;     /* Low order bit first word */
2326         uint8_t mbxHc:1;
2327         uint8_t mbxReserved:6;
2328         uint8_t mbxCommand;
2329         uint16_t mbxStatus;
2330 #endif
2331
2332         MAILVARIANTS un;
2333         SLI_VAR us;
2334 } MAILBOX_t;
2335
2336 /*
2337  *    Begin Structure Definitions for IOCB Commands
2338  */
2339
2340 typedef struct {
2341 #ifdef __BIG_ENDIAN_BITFIELD
2342         uint8_t statAction;
2343         uint8_t statRsn;
2344         uint8_t statBaExp;
2345         uint8_t statLocalError;
2346 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2347         uint8_t statLocalError;
2348         uint8_t statBaExp;
2349         uint8_t statRsn;
2350         uint8_t statAction;
2351 #endif
2352         /* statRsn  P/F_RJT reason codes */
2353 #define RJT_BAD_D_ID       0x01 /* Invalid D_ID field */
2354 #define RJT_BAD_S_ID       0x02 /* Invalid S_ID field */
2355 #define RJT_UNAVAIL_TEMP   0x03 /* N_Port unavailable temp. */
2356 #define RJT_UNAVAIL_PERM   0x04 /* N_Port unavailable perm. */
2357 #define RJT_UNSUP_CLASS    0x05 /* Class not supported */
2358 #define RJT_DELIM_ERR      0x06 /* Delimiter usage error */
2359 #define RJT_UNSUP_TYPE     0x07 /* Type not supported */
2360 #define RJT_BAD_CONTROL    0x08 /* Invalid link conrtol */
2361 #define RJT_BAD_RCTL       0x09 /* R_CTL invalid */
2362 #define RJT_BAD_FCTL       0x0A /* F_CTL invalid */
2363 #define RJT_BAD_OXID       0x0B /* OX_ID invalid */
2364 #define RJT_BAD_RXID       0x0C /* RX_ID invalid */
2365 #define RJT_BAD_SEQID      0x0D /* SEQ_ID invalid */
2366 #define RJT_BAD_DFCTL      0x0E /* DF_CTL invalid */
2367 #define RJT_BAD_SEQCNT     0x0F /* SEQ_CNT invalid */
2368 #define RJT_BAD_PARM       0x10 /* Param. field invalid */
2369 #define RJT_XCHG_ERR       0x11 /* Exchange error */
2370 #define RJT_PROT_ERR       0x12 /* Protocol error */
2371 #define RJT_BAD_LENGTH     0x13 /* Invalid Length */
2372 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
2373 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
2374 #define RJT_TOO_MANY_SEQ   0x17 /* Excessive sequences */
2375 #define RJT_XCHG_NOT_STRT  0x18 /* Exchange not started */
2376 #define RJT_UNSUP_SEC_HDR  0x19 /* Security hdr not supported */
2377 #define RJT_UNAVAIL_PATH   0x1A /* Fabric Path not available */
2378 #define RJT_VENDOR_UNIQUE  0xFF /* Vendor unique error */
2379
2380 #define IOERR_SUCCESS                 0x00      /* statLocalError */
2381 #define IOERR_MISSING_CONTINUE        0x01
2382 #define IOERR_SEQUENCE_TIMEOUT        0x02
2383 #define IOERR_INTERNAL_ERROR          0x03
2384 #define IOERR_INVALID_RPI             0x04
2385 #define IOERR_NO_XRI                  0x05
2386 #define IOERR_ILLEGAL_COMMAND         0x06
2387 #define IOERR_XCHG_DROPPED            0x07
2388 #define IOERR_ILLEGAL_FIELD           0x08
2389 #define IOERR_BAD_CONTINUE            0x09
2390 #define IOERR_TOO_MANY_BUFFERS        0x0A
2391 #define IOERR_RCV_BUFFER_WAITING      0x0B
2392 #define IOERR_NO_CONNECTION           0x0C
2393 #define IOERR_TX_DMA_FAILED           0x0D
2394 #define IOERR_RX_DMA_FAILED           0x0E
2395 #define IOERR_ILLEGAL_FRAME           0x0F
2396 #define IOERR_EXTRA_DATA              0x10
2397 #define IOERR_NO_RESOURCES            0x11
2398 #define IOERR_RESERVED                0x12
2399 #define IOERR_ILLEGAL_LENGTH          0x13
2400 #define IOERR_UNSUPPORTED_FEATURE     0x14
2401 #define IOERR_ABORT_IN_PROGRESS       0x15
2402 #define IOERR_ABORT_REQUESTED         0x16
2403 #define IOERR_RECEIVE_BUFFER_TIMEOUT  0x17
2404 #define IOERR_LOOP_OPEN_FAILURE       0x18
2405 #define IOERR_RING_RESET              0x19
2406 #define IOERR_LINK_DOWN               0x1A
2407 #define IOERR_CORRUPTED_DATA          0x1B
2408 #define IOERR_CORRUPTED_RPI           0x1C
2409 #define IOERR_OUT_OF_ORDER_DATA       0x1D
2410 #define IOERR_OUT_OF_ORDER_ACK        0x1E
2411 #define IOERR_DUP_FRAME               0x1F
2412 #define IOERR_LINK_CONTROL_FRAME      0x20      /* ACK_N received */
2413 #define IOERR_BAD_HOST_ADDRESS        0x21
2414 #define IOERR_RCV_HDRBUF_WAITING      0x22
2415 #define IOERR_MISSING_HDR_BUFFER      0x23
2416 #define IOERR_MSEQ_CHAIN_CORRUPTED    0x24
2417 #define IOERR_ABORTMULT_REQUESTED     0x25
2418 #define IOERR_BUFFER_SHORTAGE         0x28
2419 #define IOERR_DEFAULT                 0x29
2420 #define IOERR_CNT                     0x2A
2421
2422 #define IOERR_DRVR_MASK               0x100
2423 #define IOERR_SLI_DOWN                0x101  /* ulpStatus  - Driver defined */
2424 #define IOERR_SLI_BRESET              0x102
2425 #define IOERR_SLI_ABORTED             0x103
2426 } PARM_ERR;
2427
2428 typedef union {
2429         struct {
2430 #ifdef __BIG_ENDIAN_BITFIELD
2431                 uint8_t Rctl;   /* R_CTL field */
2432                 uint8_t Type;   /* TYPE field */
2433                 uint8_t Dfctl;  /* DF_CTL field */
2434                 uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
2435 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2436                 uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
2437                 uint8_t Dfctl;  /* DF_CTL field */
2438                 uint8_t Type;   /* TYPE field */
2439                 uint8_t Rctl;   /* R_CTL field */
2440 #endif
2441
2442 #define BC      0x02            /* Broadcast Received  - Fctl */
2443 #define SI      0x04            /* Sequence Initiative */
2444 #define LA      0x08            /* Ignore Link Attention state */
2445 #define LS      0x80            /* Last Sequence */
2446         } hcsw;
2447         uint32_t reserved;
2448 } WORD5;
2449
2450 /* IOCB Command template for a generic response */
2451 typedef struct {
2452         uint32_t reserved[4];
2453         PARM_ERR perr;
2454 } GENERIC_RSP;
2455
2456 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
2457 typedef struct {
2458         struct ulp_bde xrsqbde[2];
2459         uint32_t xrsqRo;        /* Starting Relative Offset */
2460         WORD5 w5;               /* Header control/status word */
2461 } XR_SEQ_FIELDS;
2462
2463 /* IOCB Command template for ELS_REQUEST */
2464 typedef struct {
2465         struct ulp_bde elsReq;
2466         struct ulp_bde elsRsp;
2467
2468 #ifdef __BIG_ENDIAN_BITFIELD
2469         uint32_t word4Rsvd:7;
2470         uint32_t fl:1;
2471         uint32_t myID:24;
2472         uint32_t word5Rsvd:8;
2473         uint32_t remoteID:24;
2474 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2475         uint32_t myID:24;
2476         uint32_t fl:1;
2477         uint32_t word4Rsvd:7;
2478         uint32_t remoteID:24;
2479         uint32_t word5Rsvd:8;
2480 #endif
2481 } ELS_REQUEST;
2482
2483 /* IOCB Command template for RCV_ELS_REQ */
2484 typedef struct {
2485         struct ulp_bde elsReq[2];
2486         uint32_t parmRo;
2487
2488 #ifdef __BIG_ENDIAN_BITFIELD
2489         uint32_t word5Rsvd:8;
2490         uint32_t remoteID:24;
2491 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2492         uint32_t remoteID:24;
2493         uint32_t word5Rsvd:8;
2494 #endif
2495 } RCV_ELS_REQ;
2496
2497 /* IOCB Command template for ABORT / CLOSE_XRI */
2498 typedef struct {
2499         uint32_t rsvd[3];
2500         uint32_t abortType;
2501 #define ABORT_TYPE_ABTX  0x00000000
2502 #define ABORT_TYPE_ABTS  0x00000001
2503         uint32_t parm;
2504 #ifdef __BIG_ENDIAN_BITFIELD
2505         uint16_t abortContextTag; /* ulpContext from command to abort/close */
2506         uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
2507 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2508         uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
2509         uint16_t abortContextTag; /* ulpContext from command to abort/close */
2510 #endif
2511 } AC_XRI;
2512
2513 /* IOCB Command template for ABORT_MXRI64 */
2514 typedef struct {
2515         uint32_t rsvd[3];
2516         uint32_t abortType;
2517         uint32_t parm;
2518         uint32_t iotag32;
2519 } A_MXRI64;
2520
2521 /* IOCB Command template for GET_RPI */
2522 typedef struct {
2523         uint32_t rsvd[4];
2524         uint32_t parmRo;
2525 #ifdef __BIG_ENDIAN_BITFIELD
2526         uint32_t word5Rsvd:8;
2527         uint32_t remoteID:24;
2528 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2529         uint32_t remoteID:24;
2530         uint32_t word5Rsvd:8;
2531 #endif
2532 } GET_RPI;
2533
2534 /* IOCB Command template for all FCP Initiator commands */
2535 typedef struct {
2536         struct ulp_bde fcpi_cmnd;       /* FCP_CMND payload descriptor */
2537         struct ulp_bde fcpi_rsp;        /* Rcv buffer */
2538         uint32_t fcpi_parm;
2539         uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
2540 } FCPI_FIELDS;
2541
2542 /* IOCB Command template for all FCP Target commands */
2543 typedef struct {
2544         struct ulp_bde fcpt_Buffer[2];  /* FCP_CMND payload descriptor */
2545         uint32_t fcpt_Offset;
2546         uint32_t fcpt_Length;   /* transfer ready for IWRITE */
2547 } FCPT_FIELDS;
2548
2549 /* SLI-2 IOCB structure definitions */
2550
2551 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
2552 typedef struct {
2553         ULP_BDL bdl;
2554         uint32_t xrsqRo;        /* Starting Relative Offset */
2555         WORD5 w5;               /* Header control/status word */
2556 } XMT_SEQ_FIELDS64;
2557
2558 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
2559 typedef struct {
2560         struct ulp_bde64 rcvBde;
2561         uint32_t rsvd1;
2562         uint32_t xrsqRo;        /* Starting Relative Offset */
2563         WORD5 w5;               /* Header control/status word */
2564 } RCV_SEQ_FIELDS64;
2565
2566 /* IOCB Command template for ELS_REQUEST64 */
2567 typedef struct {
2568         ULP_BDL bdl;
2569 #ifdef __BIG_ENDIAN_BITFIELD
2570         uint32_t word4Rsvd:7;
2571         uint32_t fl:1;
2572         uint32_t myID:24;
2573         uint32_t word5Rsvd:8;
2574         uint32_t remoteID:24;
2575 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2576         uint32_t myID:24;
2577         uint32_t fl:1;
2578         uint32_t word4Rsvd:7;
2579         uint32_t remoteID:24;
2580         uint32_t word5Rsvd:8;
2581 #endif
2582 } ELS_REQUEST64;
2583
2584 /* IOCB Command template for GEN_REQUEST64 */
2585 typedef struct {
2586         ULP_BDL bdl;
2587         uint32_t xrsqRo;        /* Starting Relative Offset */
2588         WORD5 w5;               /* Header control/status word */
2589 } GEN_REQUEST64;
2590
2591 /* IOCB Command template for RCV_ELS_REQ64 */
2592 typedef struct {
2593         struct ulp_bde64 elsReq;
2594         uint32_t rcvd1;
2595         uint32_t parmRo;
2596
2597 #ifdef __BIG_ENDIAN_BITFIELD
2598         uint32_t word5Rsvd:8;
2599         uint32_t remoteID:24;
2600 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2601         uint32_t remoteID:24;
2602         uint32_t word5Rsvd:8;
2603 #endif
2604 } RCV_ELS_REQ64;
2605
2606 /* IOCB Command template for all 64 bit FCP Initiator commands */
2607 typedef struct {
2608         ULP_BDL bdl;
2609         uint32_t fcpi_parm;
2610         uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
2611 } FCPI_FIELDS64;
2612
2613 /* IOCB Command template for all 64 bit FCP Target commands */
2614 typedef struct {
2615         ULP_BDL bdl;
2616         uint32_t fcpt_Offset;
2617         uint32_t fcpt_Length;   /* transfer ready for IWRITE */
2618 } FCPT_FIELDS64;
2619
2620 typedef struct _IOCB {  /* IOCB structure */
2621         union {
2622                 GENERIC_RSP grsp;       /* Generic response */
2623                 XR_SEQ_FIELDS xrseq;    /* XMIT / BCAST / RCV_SEQUENCE cmd */
2624                 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
2625                 RCV_ELS_REQ rcvels;     /* RCV_ELS_REQ template */
2626                 AC_XRI acxri;   /* ABORT / CLOSE_XRI template */
2627                 A_MXRI64 amxri; /* abort multiple xri command overlay */
2628                 GET_RPI getrpi; /* GET_RPI template */
2629                 FCPI_FIELDS fcpi;       /* FCP Initiator template */
2630                 FCPT_FIELDS fcpt;       /* FCP target template */
2631
2632                 /* SLI-2 structures */
2633
2634                 struct ulp_bde64 cont64[2];     /* up to 2 64 bit continuation
2635                                            bde_64s */
2636                 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
2637                 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
2638                 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
2639                 XMT_SEQ_FIELDS64 xseq64;        /* XMIT / BCAST cmd */
2640                 FCPI_FIELDS64 fcpi64;   /* FCP 64 bit Initiator template */
2641                 FCPT_FIELDS64 fcpt64;   /* FCP 64 bit target template */
2642
2643                 uint32_t ulpWord[IOCB_WORD_SZ - 2];     /* generic 6 'words' */
2644         } un;
2645         union {
2646                 struct {
2647 #ifdef __BIG_ENDIAN_BITFIELD
2648                         uint16_t ulpContext;    /* High order bits word 6 */
2649                         uint16_t ulpIoTag;      /* Low  order bits word 6 */
2650 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2651                         uint16_t ulpIoTag;      /* Low  order bits word 6 */
2652                         uint16_t ulpContext;    /* High order bits word 6 */
2653 #endif
2654                 } t1;
2655                 struct {
2656 #ifdef __BIG_ENDIAN_BITFIELD
2657                         uint16_t ulpContext;    /* High order bits word 6 */
2658                         uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
2659                         uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
2660 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2661                         uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
2662                         uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
2663                         uint16_t ulpContext;    /* High order bits word 6 */
2664 #endif
2665                 } t2;
2666         } un1;
2667 #define ulpContext un1.t1.ulpContext
2668 #define ulpIoTag   un1.t1.ulpIoTag
2669 #define ulpIoTag0  un1.t2.ulpIoTag0
2670
2671 #ifdef __BIG_ENDIAN_BITFIELD
2672         uint32_t ulpTimeout:8;
2673         uint32_t ulpXS:1;
2674         uint32_t ulpFCP2Rcvy:1;
2675         uint32_t ulpPU:2;
2676         uint32_t ulpIr:1;
2677         uint32_t ulpClass:3;
2678         uint32_t ulpCommand:8;
2679         uint32_t ulpStatus:4;
2680         uint32_t ulpBdeCount:2;
2681         uint32_t ulpLe:1;
2682         uint32_t ulpOwner:1;    /* Low order bit word 7 */
2683 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2684         uint32_t ulpOwner:1;    /* Low order bit word 7 */
2685         uint32_t ulpLe:1;
2686         uint32_t ulpBdeCount:2;
2687         uint32_t ulpStatus:4;
2688         uint32_t ulpCommand:8;
2689         uint32_t ulpClass:3;
2690         uint32_t ulpIr:1;
2691         uint32_t ulpPU:2;
2692         uint32_t ulpFCP2Rcvy:1;
2693         uint32_t ulpXS:1;
2694         uint32_t ulpTimeout:8;
2695 #endif
2696
2697 #define PARM_UNUSED        0    /* PU field (Word 4) not used */
2698 #define PARM_REL_OFF       1    /* PU field (Word 4) = R. O. */
2699 #define PARM_READ_CHECK    2    /* PU field (Word 4) = Data Transfer Length */
2700 #define CLASS1             0    /* Class 1 */
2701 #define CLASS2             1    /* Class 2 */
2702 #define CLASS3             2    /* Class 3 */
2703 #define CLASS_FCP_INTERMIX 7    /* FCP Data->Cls 1, all else->Cls 2 */
2704
2705 #define IOSTAT_SUCCESS         0x0      /* ulpStatus  - HBA defined */
2706 #define IOSTAT_FCP_RSP_ERROR   0x1
2707 #define IOSTAT_REMOTE_STOP     0x2
2708 #define IOSTAT_LOCAL_REJECT    0x3
2709 #define IOSTAT_NPORT_RJT       0x4
2710 #define IOSTAT_FABRIC_RJT      0x5
2711 #define IOSTAT_NPORT_BSY       0x6
2712 #define IOSTAT_FABRIC_BSY      0x7
2713 #define IOSTAT_INTERMED_RSP    0x8
2714 #define IOSTAT_LS_RJT          0x9
2715 #define IOSTAT_BA_RJT          0xA
2716 #define IOSTAT_RSVD1           0xB
2717 #define IOSTAT_RSVD2           0xC
2718 #define IOSTAT_RSVD3           0xD
2719 #define IOSTAT_RSVD4           0xE
2720 #define IOSTAT_RSVD5           0xF
2721 #define IOSTAT_DRIVER_REJECT   0x10   /* ulpStatus  - Driver defined */
2722 #define IOSTAT_DEFAULT         0xF    /* Same as rsvd5 for now */
2723 #define IOSTAT_CNT             0x11
2724
2725 } IOCB_t;
2726
2727
2728 #define SLI1_SLIM_SIZE   (4 * 1024)
2729
2730 /* Up to 498 IOCBs will fit into 16k
2731  * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
2732  */
2733 #define SLI2_SLIM_SIZE   (16 * 1024)
2734
2735 /* Maximum IOCBs that will fit in SLI2 slim */
2736 #define MAX_SLI2_IOCB    498
2737
2738 struct lpfc_sli2_slim {
2739         MAILBOX_t mbx;
2740         PCB_t pcb;
2741         IOCB_t IOCBs[MAX_SLI2_IOCB];
2742 };
2743
2744 /*
2745  * This function checks PCI device to allow special handling for LC HBAs.
2746  *
2747  * Parameters:
2748  * device : struct pci_dev 's device field
2749  *
2750  * return 1 => TRUE
2751  *        0 => FALSE
2752  */
2753 static inline int
2754 lpfc_is_LC_HBA(unsigned short device)
2755 {
2756         if ((device == PCI_DEVICE_ID_TFLY) ||
2757             (device == PCI_DEVICE_ID_PFLY) ||
2758             (device == PCI_DEVICE_ID_LP101) ||
2759             (device == PCI_DEVICE_ID_BMID) ||
2760             (device == PCI_DEVICE_ID_BSMB) ||
2761             (device == PCI_DEVICE_ID_ZMID) ||
2762             (device == PCI_DEVICE_ID_ZSMB) ||
2763             (device == PCI_DEVICE_ID_RFLY))
2764                 return 1;
2765         else
2766                 return 0;
2767 }