]>
git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blob - drivers/scsi/mac53c94.h
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mac53c94.h: definitions for the driver for the 53c94 SCSI bus adaptor
4 * found on Power Macintosh computers, controlling the external SCSI chain.
6 * Copyright (C) 1996 Paul Mackerras.
12 * Registers in the 53C94 controller.
15 struct mac53c94_regs
{
16 unsigned char count_lo
;
18 unsigned char count_mid
;
22 unsigned char command
;
26 unsigned char interrupt
;
28 unsigned char seqstep
;
32 unsigned char config1
;
34 unsigned char clk_factor
;
38 unsigned char config2
;
40 unsigned char config3
;
42 unsigned char config4
;
44 unsigned char count_hi
;
46 unsigned char fifo_res
;
51 * Alternate functions for some registers.
53 #define dest_id status
54 #define sel_timeout interrupt
55 #define sync_period seqstep
56 #define sync_offset flags
59 * Bits in command register.
61 #define CMD_DMA_MODE 0x80
62 #define CMD_MODE_MASK 0x70
63 #define CMD_MODE_INIT 0x10
64 #define CMD_MODE_TARG 0x20
65 #define CMD_MODE_DISC 0x40
70 #define CMD_SCSI_RESET 3
72 #define CMD_XFER_DATA 0x10
73 #define CMD_I_COMPLETE 0x11
74 #define CMD_ACCEPT_MSG 0x12
75 #define CMD_XFER_PAD 0x18
76 #define CMD_SET_ATN 0x1a
77 #define CMD_CLR_ATN 0x1b
79 #define CMD_SEND_MSG 0x20
80 #define CMD_SEND_STATUS 0x21
81 #define CMD_SEND_DATA 0x22
82 #define CMD_DISC_SEQ 0x23
83 #define CMD_TERMINATE 0x24
84 #define CMD_T_COMPLETE 0x25
85 #define CMD_DISCONNECT 0x27
86 #define CMD_RECV_MSG 0x28
87 #define CMD_RECV_CDB 0x29
88 #define CMD_RECV_DATA 0x2a
89 #define CMD_RECV_CMD 0x2b
90 #define CMD_ABORT_DMA 0x04
92 #define CMD_RESELECT 0x40
93 #define CMD_SELECT 0x41
94 #define CMD_SELECT_ATN 0x42
95 #define CMD_SELATN_STOP 0x43
96 #define CMD_ENABLE_SEL 0x44
97 #define CMD_DISABLE_SEL 0x45
98 #define CMD_SEL_ATN3 0x46
99 #define CMD_RESEL_ATN3 0x47
102 * Bits in status register.
104 #define STAT_IRQ 0x80
105 #define STAT_ERROR 0x40
106 #define STAT_PARITY 0x20
107 #define STAT_TC_ZERO 0x10
108 #define STAT_DONE 0x08
109 #define STAT_PHASE 0x07
110 #define STAT_MSG 0x04
115 * Bits in interrupt register.
117 #define INTR_RESET 0x80 /* SCSI bus was reset */
118 #define INTR_ILL_CMD 0x40 /* illegal command */
119 #define INTR_DISCONNECT 0x20 /* we got disconnected */
120 #define INTR_BUS_SERV 0x10 /* bus service requested */
121 #define INTR_DONE 0x08 /* function completed */
122 #define INTR_RESELECTED 0x04 /* we were reselected */
123 #define INTR_SEL_ATN 0x02 /* we were selected, ATN asserted */
124 #define INTR_SELECT 0x01 /* we were selected, ATN negated */
127 * Encoding for the select timeout.
129 #define TIMO_VAL(x) ((x) * 5000 / 7682)
132 * Bits in sequence step register.
135 #define SS_ARB_SEL 0 /* Selection & arbitration complete */
136 #define SS_MSG_SENT 1 /* One message byte sent */
137 #define SS_NOT_CMD 2 /* Not in command phase */
138 #define SS_PHASE_CHG 3 /* Early phase change, cmd bytes lost */
139 #define SS_DONE 4 /* Command was sent OK */
142 * Encoding for sync transfer period.
144 #define SYNCP_MASK 0x1f
149 * Bits in flags register.
151 #define FLAGS_FIFO_LEV 0x1f
152 #define FLAGS_SEQ_STEP 0xe0
155 * Encoding for sync offset.
157 #define SYNCO_MASK 0x0f
158 #define SYNCO_ASS_CTRL 0x30 /* REQ/ACK assertion control */
159 #define SYNCO_NEG_CTRL 0xc0 /* REQ/ACK negation control */
162 * Bits in config1 register.
164 #define CF1_SLOW_CABLE 0x80 /* Slow cable mode */
165 #define CF1_NO_RES_REP 0x40 /* Disable SCSI reset reports */
166 #define CF1_PAR_TEST 0x20 /* Parity test mode enable */
167 #define CF1_PAR_ENABLE 0x10 /* Enable parity checks */
168 #define CF1_TEST 0x08 /* Chip tests */
169 #define CF1_MY_ID 0x07 /* Controller's address on bus */
172 * Encoding for clk_factor register.
175 #define CLKF_VAL(freq) ((((freq) + 4999999) / 5000000) & CLKF_MASK)
178 * Bits in test mode register.
180 #define TEST_TARGET 1 /* target test mode */
181 #define TEST_INITIATOR 2 /* initiator test mode */
182 #define TEST_TRISTATE 4 /* tristate (hi-z) test mode */
185 * Bits in config2 register.
188 #define CF2_FEATURE_EN 0x40 /* enable features / phase latch */
189 #define CF2_BYTECTRL 0x20
190 #define CF2_DREQ_HIZ 0x10
191 #define CF2_SCSI2 0x08
192 #define CF2_PAR_ABORT 0x04 /* bad parity target abort */
193 #define CF2_REG_PARERR 0x02 /* register parity error */
194 #define CF2_DMA_PARERR 0x01 /* DMA parity error */
197 * Bits in the config3 register.
199 #define CF3_ID_MSG_CHK 0x80
200 #define CF3_3B_MSGS 0x40
201 #define CF3_CDB10 0x20
202 #define CF3_FASTSCSI 0x10 /* enable fast SCSI support */
203 #define CF3_FASTCLOCK 0x08
204 #define CF3_SAVERESID 0x04
205 #define CF3_ALT_DMA 0x02
206 #define CF3_THRESH_8 0x01
209 * Bits in the config4 register.
212 #define CF4_TEST 0x02
213 #define CF4_BBTE 0x01
215 #endif /* _MAC53C94_H */