1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux MegaRAID driver for SAS based RAID controllers
5 * Copyright (c) 2003-2013 LSI Corporation
6 * Copyright (c) 2013-2016 Avago Technologies
7 * Copyright (c) 2016-2018 Broadcom Inc.
11 * Authors: Broadcom Inc.
12 * Kashyap Desai <kashyap.desai@broadcom.com>
13 * Sumit Saxena <sumit.saxena@broadcom.com>
15 * Send feedback to: megaraidlinux.pdl@broadcom.com
18 #ifndef LSI_MEGARAID_SAS_H
19 #define LSI_MEGARAID_SAS_H
22 * MegaRAID SAS Driver meta data
24 #define MEGASAS_VERSION "07.710.50.00-rc1"
25 #define MEGASAS_RELDATE "June 28, 2019"
30 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
31 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
32 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
33 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
34 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
35 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
36 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
37 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
38 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
39 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
40 #define PCI_DEVICE_ID_LSI_FURY 0x005f
41 #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce
42 #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf
43 #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052
44 #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053
45 #define PCI_DEVICE_ID_LSI_VENTURA 0x0014
46 #define PCI_DEVICE_ID_LSI_CRUSADER 0x0015
47 #define PCI_DEVICE_ID_LSI_HARPOON 0x0016
48 #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017
49 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B
50 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C
51 #define PCI_DEVICE_ID_LSI_AERO_10E1 0x10e1
52 #define PCI_DEVICE_ID_LSI_AERO_10E2 0x10e2
53 #define PCI_DEVICE_ID_LSI_AERO_10E5 0x10e5
54 #define PCI_DEVICE_ID_LSI_AERO_10E6 0x10e6
55 #define PCI_DEVICE_ID_LSI_AERO_10E0 0x10e0
56 #define PCI_DEVICE_ID_LSI_AERO_10E3 0x10e3
57 #define PCI_DEVICE_ID_LSI_AERO_10E4 0x10e4
58 #define PCI_DEVICE_ID_LSI_AERO_10E7 0x10e7
63 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
64 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
65 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
66 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
67 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
68 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
69 #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B
74 #define MEGARAID_INTRUDER_SSDID1 0x9371
75 #define MEGARAID_INTRUDER_SSDID2 0x9390
76 #define MEGARAID_INTRUDER_SSDID3 0x9370
81 #define MEGARAID_INTEL_RS3DC080_BRANDING \
82 "Intel(R) RAID Controller RS3DC080"
83 #define MEGARAID_INTEL_RS3DC040_BRANDING \
84 "Intel(R) RAID Controller RS3DC040"
85 #define MEGARAID_INTEL_RS3SC008_BRANDING \
86 "Intel(R) RAID Controller RS3SC008"
87 #define MEGARAID_INTEL_RS3MC044_BRANDING \
88 "Intel(R) RAID Controller RS3MC044"
89 #define MEGARAID_INTEL_RS3WC080_BRANDING \
90 "Intel(R) RAID Controller RS3WC080"
91 #define MEGARAID_INTEL_RS3WC040_BRANDING \
92 "Intel(R) RAID Controller RS3WC040"
93 #define MEGARAID_INTEL_RMS3BC160_BRANDING \
94 "Intel(R) Integrated RAID Module RMS3BC160"
97 * =====================================
98 * MegaRAID SAS MFI firmware definitions
99 * =====================================
103 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
104 * protocol between the software and firmware. Commands are issued using
109 * FW posts its state in upper 4 bits of outbound_msg_0 register
111 #define MFI_STATE_MASK 0xF0000000
112 #define MFI_STATE_UNDEFINED 0x00000000
113 #define MFI_STATE_BB_INIT 0x10000000
114 #define MFI_STATE_FW_INIT 0x40000000
115 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
116 #define MFI_STATE_FW_INIT_2 0x70000000
117 #define MFI_STATE_DEVICE_SCAN 0x80000000
118 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
119 #define MFI_STATE_FLUSH_CACHE 0xA0000000
120 #define MFI_STATE_READY 0xB0000000
121 #define MFI_STATE_OPERATIONAL 0xC0000000
122 #define MFI_STATE_FAULT 0xF0000000
123 #define MFI_STATE_FORCE_OCR 0x00000080
124 #define MFI_STATE_DMADONE 0x00000008
125 #define MFI_STATE_CRASH_DUMP_DONE 0x00000004
126 #define MFI_RESET_REQUIRED 0x00000001
127 #define MFI_RESET_ADAPTER 0x00000002
128 #define MEGAMFI_FRAME_SIZE 64
130 #define MFI_STATE_FAULT_CODE 0x0FFF0000
131 #define MFI_STATE_FAULT_SUBCODE 0x0000FF00
133 * During FW init, clear pending cmds & reset state using inbound_msg_0
135 * ABORT : Abort all pending cmds
136 * READY : Move from OPERATIONAL to READY state; discard queue info
137 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
138 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
139 * HOTPLUG : Resume from Hotplug
140 * MFI_STOP_ADP : Send signal to FW to stop processing
141 * MFI_ADP_TRIGGER_SNAP_DUMP: Inform firmware to initiate snap dump
143 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
144 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
145 #define DIAG_WRITE_ENABLE (0x00000080)
146 #define DIAG_RESET_ADAPTER (0x00000004)
148 #define MFI_ADP_RESET 0x00000040
149 #define MFI_INIT_ABORT 0x00000001
150 #define MFI_INIT_READY 0x00000002
151 #define MFI_INIT_MFIMODE 0x00000004
152 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
153 #define MFI_INIT_HOTPLUG 0x00000010
154 #define MFI_STOP_ADP 0x00000020
155 #define MFI_RESET_FLAGS MFI_INIT_READY| \
158 #define MFI_ADP_TRIGGER_SNAP_DUMP 0x00000100
159 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
164 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
165 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
166 #define MFI_FRAME_SGL32 0x0000
167 #define MFI_FRAME_SGL64 0x0002
168 #define MFI_FRAME_SENSE32 0x0000
169 #define MFI_FRAME_SENSE64 0x0004
170 #define MFI_FRAME_DIR_NONE 0x0000
171 #define MFI_FRAME_DIR_WRITE 0x0008
172 #define MFI_FRAME_DIR_READ 0x0010
173 #define MFI_FRAME_DIR_BOTH 0x0018
174 #define MFI_FRAME_IEEE 0x0020
176 /* Driver internal */
177 #define DRV_DCMD_POLLED_MODE 0x1
178 #define DRV_DCMD_SKIP_REFIRE 0x2
181 * Definition for cmd_status
183 #define MFI_CMD_STATUS_POLL_MODE 0xFF
186 * MFI command opcodes
190 MFI_CMD_LD_READ
= 0x1,
191 MFI_CMD_LD_WRITE
= 0x2,
192 MFI_CMD_LD_SCSI_IO
= 0x3,
193 MFI_CMD_PD_SCSI_IO
= 0x4,
199 MFI_CMD_TOOLBOX
= 0xa,
201 MFI_CMD_INVALID
= 0xff
204 #define MR_DCMD_CTRL_GET_INFO 0x01010000
205 #define MR_DCMD_LD_GET_LIST 0x03010000
206 #define MR_DCMD_LD_LIST_QUERY 0x03010100
208 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
209 #define MR_FLUSH_CTRL_CACHE 0x01
210 #define MR_FLUSH_DISK_CACHE 0x02
212 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
213 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
214 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
216 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
217 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
218 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
219 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
221 #define MR_DCMD_CLUSTER 0x08000000
222 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
223 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
224 #define MR_DCMD_PD_LIST_QUERY 0x02010100
226 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
227 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
228 #define MR_DCMD_PD_GET_INFO 0x02020000
233 extern u8
MR_ValidateMapInfo(struct megasas_instance
*instance
, u64 map_id
);
237 * MFI command completion codes
241 MFI_STAT_INVALID_CMD
= 0x01,
242 MFI_STAT_INVALID_DCMD
= 0x02,
243 MFI_STAT_INVALID_PARAMETER
= 0x03,
244 MFI_STAT_INVALID_SEQUENCE_NUMBER
= 0x04,
245 MFI_STAT_ABORT_NOT_POSSIBLE
= 0x05,
246 MFI_STAT_APP_HOST_CODE_NOT_FOUND
= 0x06,
247 MFI_STAT_APP_IN_USE
= 0x07,
248 MFI_STAT_APP_NOT_INITIALIZED
= 0x08,
249 MFI_STAT_ARRAY_INDEX_INVALID
= 0x09,
250 MFI_STAT_ARRAY_ROW_NOT_EMPTY
= 0x0a,
251 MFI_STAT_CONFIG_RESOURCE_CONFLICT
= 0x0b,
252 MFI_STAT_DEVICE_NOT_FOUND
= 0x0c,
253 MFI_STAT_DRIVE_TOO_SMALL
= 0x0d,
254 MFI_STAT_FLASH_ALLOC_FAIL
= 0x0e,
255 MFI_STAT_FLASH_BUSY
= 0x0f,
256 MFI_STAT_FLASH_ERROR
= 0x10,
257 MFI_STAT_FLASH_IMAGE_BAD
= 0x11,
258 MFI_STAT_FLASH_IMAGE_INCOMPLETE
= 0x12,
259 MFI_STAT_FLASH_NOT_OPEN
= 0x13,
260 MFI_STAT_FLASH_NOT_STARTED
= 0x14,
261 MFI_STAT_FLUSH_FAILED
= 0x15,
262 MFI_STAT_HOST_CODE_NOT_FOUNT
= 0x16,
263 MFI_STAT_LD_CC_IN_PROGRESS
= 0x17,
264 MFI_STAT_LD_INIT_IN_PROGRESS
= 0x18,
265 MFI_STAT_LD_LBA_OUT_OF_RANGE
= 0x19,
266 MFI_STAT_LD_MAX_CONFIGURED
= 0x1a,
267 MFI_STAT_LD_NOT_OPTIMAL
= 0x1b,
268 MFI_STAT_LD_RBLD_IN_PROGRESS
= 0x1c,
269 MFI_STAT_LD_RECON_IN_PROGRESS
= 0x1d,
270 MFI_STAT_LD_WRONG_RAID_LEVEL
= 0x1e,
271 MFI_STAT_MAX_SPARES_EXCEEDED
= 0x1f,
272 MFI_STAT_MEMORY_NOT_AVAILABLE
= 0x20,
273 MFI_STAT_MFC_HW_ERROR
= 0x21,
274 MFI_STAT_NO_HW_PRESENT
= 0x22,
275 MFI_STAT_NOT_FOUND
= 0x23,
276 MFI_STAT_NOT_IN_ENCL
= 0x24,
277 MFI_STAT_PD_CLEAR_IN_PROGRESS
= 0x25,
278 MFI_STAT_PD_TYPE_WRONG
= 0x26,
279 MFI_STAT_PR_DISABLED
= 0x27,
280 MFI_STAT_ROW_INDEX_INVALID
= 0x28,
281 MFI_STAT_SAS_CONFIG_INVALID_ACTION
= 0x29,
282 MFI_STAT_SAS_CONFIG_INVALID_DATA
= 0x2a,
283 MFI_STAT_SAS_CONFIG_INVALID_PAGE
= 0x2b,
284 MFI_STAT_SAS_CONFIG_INVALID_TYPE
= 0x2c,
285 MFI_STAT_SCSI_DONE_WITH_ERROR
= 0x2d,
286 MFI_STAT_SCSI_IO_FAILED
= 0x2e,
287 MFI_STAT_SCSI_RESERVATION_CONFLICT
= 0x2f,
288 MFI_STAT_SHUTDOWN_FAILED
= 0x30,
289 MFI_STAT_TIME_NOT_SET
= 0x31,
290 MFI_STAT_WRONG_STATE
= 0x32,
291 MFI_STAT_LD_OFFLINE
= 0x33,
292 MFI_STAT_PEER_NOTIFICATION_REJECTED
= 0x34,
293 MFI_STAT_PEER_NOTIFICATION_FAILED
= 0x35,
294 MFI_STAT_RESERVATION_IN_PROGRESS
= 0x36,
295 MFI_STAT_I2C_ERRORS_DETECTED
= 0x37,
296 MFI_STAT_PCI_ERRORS_DETECTED
= 0x38,
297 MFI_STAT_CONFIG_SEQ_MISMATCH
= 0x67,
299 MFI_STAT_INVALID_STATUS
= 0xFF
303 MFI_EVT_CLASS_DEBUG
= -2,
304 MFI_EVT_CLASS_PROGRESS
= -1,
305 MFI_EVT_CLASS_INFO
= 0,
306 MFI_EVT_CLASS_WARNING
= 1,
307 MFI_EVT_CLASS_CRITICAL
= 2,
308 MFI_EVT_CLASS_FATAL
= 3,
309 MFI_EVT_CLASS_DEAD
= 4
313 * Crash dump related defines
315 #define MAX_CRASH_DUMP_SIZE 512
316 #define CRASH_DMA_BUF_SIZE (1024 * 1024)
318 enum MR_FW_CRASH_DUMP_STATE
{
326 enum _MR_CRASH_BUF_STATUS
{
327 MR_CRASH_BUF_TURN_OFF
= 0,
328 MR_CRASH_BUF_TURN_ON
= 1,
332 * Number of mailbox bytes in DCMD message frame
334 #define MFI_MBOX_SIZE 12
338 MR_EVT_CLASS_DEBUG
= -2,
339 MR_EVT_CLASS_PROGRESS
= -1,
340 MR_EVT_CLASS_INFO
= 0,
341 MR_EVT_CLASS_WARNING
= 1,
342 MR_EVT_CLASS_CRITICAL
= 2,
343 MR_EVT_CLASS_FATAL
= 3,
344 MR_EVT_CLASS_DEAD
= 4,
350 MR_EVT_LOCALE_LD
= 0x0001,
351 MR_EVT_LOCALE_PD
= 0x0002,
352 MR_EVT_LOCALE_ENCL
= 0x0004,
353 MR_EVT_LOCALE_BBU
= 0x0008,
354 MR_EVT_LOCALE_SAS
= 0x0010,
355 MR_EVT_LOCALE_CTRL
= 0x0020,
356 MR_EVT_LOCALE_CONFIG
= 0x0040,
357 MR_EVT_LOCALE_CLUSTER
= 0x0080,
358 MR_EVT_LOCALE_ALL
= 0xffff,
365 MR_EVT_ARGS_CDB_SENSE
,
367 MR_EVT_ARGS_LD_COUNT
,
369 MR_EVT_ARGS_LD_OWNER
,
370 MR_EVT_ARGS_LD_LBA_PD_LBA
,
372 MR_EVT_ARGS_LD_STATE
,
373 MR_EVT_ARGS_LD_STRIP
,
377 MR_EVT_ARGS_PD_LBA_LD
,
379 MR_EVT_ARGS_PD_STATE
,
386 MR_EVT_ARGS_PD_SPARE
,
387 MR_EVT_ARGS_PD_INDEX
,
388 MR_EVT_ARGS_DIAG_PASS
,
389 MR_EVT_ARGS_DIAG_FAIL
,
390 MR_EVT_ARGS_PD_LBA_LBA
,
391 MR_EVT_ARGS_PORT_PHY
,
392 MR_EVT_ARGS_PD_MISSING
,
393 MR_EVT_ARGS_PD_ADDRESS
,
395 MR_EVT_ARGS_CONNECTOR
,
398 MR_EVT_ARGS_PD_PATHINFO
,
399 MR_EVT_ARGS_PD_POWER_STATE
,
404 #define SGE_BUFFER_SIZE 4096
405 #define MEGASAS_CLUSTER_ID_SIZE 16
407 * define constants for device list query options
409 enum MR_PD_QUERY_TYPE
{
410 MR_PD_QUERY_TYPE_ALL
= 0,
411 MR_PD_QUERY_TYPE_STATE
= 1,
412 MR_PD_QUERY_TYPE_POWER_STATE
= 2,
413 MR_PD_QUERY_TYPE_MEDIA_TYPE
= 3,
414 MR_PD_QUERY_TYPE_SPEED
= 4,
415 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST
= 5,
418 enum MR_LD_QUERY_TYPE
{
419 MR_LD_QUERY_TYPE_ALL
= 0,
420 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST
= 1,
421 MR_LD_QUERY_TYPE_USED_TGT_IDS
= 2,
422 MR_LD_QUERY_TYPE_CLUSTER_ACCESS
= 3,
423 MR_LD_QUERY_TYPE_CLUSTER_LOCALE
= 4,
427 #define MR_EVT_CFG_CLEARED 0x0004
428 #define MR_EVT_LD_STATE_CHANGE 0x0051
429 #define MR_EVT_PD_INSERTED 0x005b
430 #define MR_EVT_PD_REMOVED 0x0070
431 #define MR_EVT_LD_CREATED 0x008a
432 #define MR_EVT_LD_DELETED 0x008b
433 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
434 #define MR_EVT_LD_OFFLINE 0x00fc
435 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
436 #define MR_EVT_CTRL_PROP_CHANGED 0x012f
439 MR_PD_STATE_UNCONFIGURED_GOOD
= 0x00,
440 MR_PD_STATE_UNCONFIGURED_BAD
= 0x01,
441 MR_PD_STATE_HOT_SPARE
= 0x02,
442 MR_PD_STATE_OFFLINE
= 0x10,
443 MR_PD_STATE_FAILED
= 0x11,
444 MR_PD_STATE_REBUILD
= 0x14,
445 MR_PD_STATE_ONLINE
= 0x18,
446 MR_PD_STATE_COPYBACK
= 0x20,
447 MR_PD_STATE_SYSTEM
= 0x40,
459 * define the DDF Type bit structure
461 union MR_PD_DDF_TYPE
{
465 #ifndef __BIG_ENDIAN_BITFIELD
494 * defines the progress structure
501 u16 elapsedSecsForLastPercent
;
508 * defines the physical drive progress structure
510 struct MR_PD_PROGRESS
{
512 #ifndef MFI_BIG_ENDIAN
530 union MR_PROGRESS rbld
;
531 union MR_PROGRESS patrol
;
533 union MR_PROGRESS clear
;
534 union MR_PROGRESS erase
;
538 #ifndef MFI_BIG_ENDIAN
555 union MR_PROGRESS reserved
[3];
566 u8 connectedPortBitmap
;
567 u8 connectedPortNumbers
;
574 u32 lastPredFailEventSeqNum
;
577 u8 disabledForRemoval
;
579 union MR_PD_DDF_TYPE state
;
583 #ifndef __BIG_ENDIAN_BITFIELD
586 u8 widePortCapable
:1;
588 u8 widePortCapable
:1;
593 u8 connectorIndex
[2];
607 u8 enclConnectorIndex
;
610 struct MR_PD_PROGRESS progInfo
;
611 u8 badBlockTableFull
;
612 u8 unusableInCurrentConfig
;
617 u16 copyBackPartnerId
;
618 u16 enclPartnerDeviceId
;
620 #ifndef __BIG_ENDIAN_BITFIELD
641 u8 bridgeProductIdentification
[16];
642 u8 bridgeProductRevisionLevel
[4];
647 u8 emulatedBlockSize
;
648 u16 userDataBlockSize
;
652 #ifndef __BIG_ENDIAN_BITFIELD
658 u32 commissionedSpare
:1;
659 u32 emergencySpare
:1;
660 u32 ineligibleForSSCD
:1;
661 u32 ineligibleForLd
:1;
662 u32 useSSEraseType
:1;
664 u32 supportScsiUnmap
:1;
668 u32 supportScsiUnmap
:1;
670 u32 useSSEraseType
:1;
671 u32 ineligibleForLd
:1;
672 u32 ineligibleForSSCD
:1;
673 u32 emergencySpare
:1;
674 u32 commissionedSpare
:1;
683 u64 shieldDiagCompletionTime
;
690 #ifndef __BIG_ENDIAN_BITFIELD
691 u32 bbmErrCountSupported
:1;
695 u32 bbmErrCountSupported
:1;
699 u8 reserved1
[512-428];
703 * Definition of structure used to expose attributes of VD or JBOD
704 * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP
705 * is fired by driver)
707 struct MR_TARGET_PROPERTIES
{
716 * defines the physical drive address structure
718 struct MR_PD_ADDRESS
{
729 u8 enclConnectorIndex
;
734 u8 connectedPortBitmap
;
735 u8 connectedPortNumbers
;
741 * defines the physical drive list structure
746 struct MR_PD_ADDRESS addr
[1];
749 struct megasas_pd_list
{
756 * defines the logical drive reference structure
768 * defines the logical drive list structure
778 } ldList
[MAX_LOGICAL_DRIVES_EXT
];
781 struct MR_LD_TARGETID_LIST
{
785 u8 targetId
[MAX_LOGICAL_DRIVES_EXT
];
788 struct MR_HOST_DEVICE_LIST_ENTRY
{
792 #if defined(__BIG_ENDIAN_BITFIELD)
809 struct MR_HOST_DEVICE_LIST
{
813 struct MR_HOST_DEVICE_LIST_ENTRY host_device_list
[1];
816 #define HOST_DEVICE_LIST_SZ (sizeof(struct MR_HOST_DEVICE_LIST) + \
817 (sizeof(struct MR_HOST_DEVICE_LIST_ENTRY) * \
818 (MEGASAS_MAX_PD + MAX_LOGICAL_DRIVES_EXT - 1)))
822 * SAS controller properties
824 struct megasas_ctrl_prop
{
827 u16 pred_fail_poll_interval
;
828 u16 intr_throttle_count
;
829 u16 intr_throttle_timeouts
;
835 u8 cache_flush_interval
;
841 u8 disable_auto_rebuild
;
842 u8 disable_battery_warn
;
844 u16 ecc_bucket_leak_rate
;
845 u8 restore_hotspare_on_insertion
;
846 u8 expose_encl_devices
;
847 u8 maintainPdFailHistory
;
848 u8 disallowHostRequestReordering
;
851 u8 disableAutoDetectBackplane
;
856 * Add properties that can be controlled by
857 * a bit in the following structure.
860 #if defined(__BIG_ENDIAN_BITFIELD)
863 u32 disableSpinDownHS
:1;
864 u32 allowBootWithPinnedCache
:1;
865 u32 disableOnlineCtrlReset
:1;
866 u32 enableSecretKeyControl
:1;
867 u32 autoEnhancedImport
:1;
868 u32 enableSpinDownUnconfigured
:1;
869 u32 SSDPatrolReadEnabled
:1;
870 u32 SSDSMARTerEnabled
:1;
873 u32 prCorrectUnconfiguredAreas
:1;
874 u32 SMARTerEnabled
:1;
875 u32 copyBackDisabled
:1;
877 u32 copyBackDisabled
:1;
878 u32 SMARTerEnabled
:1;
879 u32 prCorrectUnconfiguredAreas
:1;
882 u32 SSDSMARTerEnabled
:1;
883 u32 SSDPatrolReadEnabled
:1;
884 u32 enableSpinDownUnconfigured
:1;
885 u32 autoEnhancedImport
:1;
886 u32 enableSecretKeyControl
:1;
887 u32 disableOnlineCtrlReset
:1;
888 u32 allowBootWithPinnedCache
:1;
889 u32 disableSpinDownHS
:1;
899 #if defined(__BIG_ENDIAN_BITFIELD)
901 u16 enable_fw_dev_list
:1;
903 u16 enable_snap_dump
:1;
907 u16 enable_snap_dump
:1;
909 u16 enable_fw_dev_list
:1;
912 } on_off_properties2
;
919 * SAS controller information
921 struct megasas_ctrl_info
{
924 * PCI device information
930 __le16 sub_vendor_id
;
931 __le16 sub_device_id
;
934 } __attribute__ ((packed
)) pci
;
937 * Host interface information
951 } __attribute__ ((packed
)) host_interface
;
954 * Device (backend) interface information
967 } __attribute__ ((packed
)) device_interface
;
970 * List of components residing in flash. All str are null terminated
972 __le32 image_check_word
;
973 __le32 image_component_count
;
982 } __attribute__ ((packed
)) image_component
[8];
985 * List of flash components that have been flashed on the card, but
986 * are not in use, pending reset of the adapter. This list will be
987 * empty if a flash operation has not occurred. All stings are null
990 __le32 pending_image_component_count
;
999 } __attribute__ ((packed
)) pending_image_component
[8];
1006 char product_name
[80];
1010 * Other physical/controller/operation information. Indicates the
1011 * presence of the hardware
1021 } __attribute__ ((packed
)) hw_present
;
1023 __le32 current_fw_time
;
1026 * Maximum data transfer sizes
1028 __le16 max_concurrent_cmds
;
1029 __le16 max_sge_count
;
1030 __le32 max_request_size
;
1033 * Logical and physical device counts
1035 __le16 ld_present_count
;
1036 __le16 ld_degraded_count
;
1037 __le16 ld_offline_count
;
1039 __le16 pd_present_count
;
1040 __le16 pd_disk_present_count
;
1041 __le16 pd_disk_pred_failure_count
;
1042 __le16 pd_disk_failed_count
;
1045 * Memory size information
1054 __le16 mem_correctable_error_count
;
1055 __le16 mem_uncorrectable_error_count
;
1058 * Cluster information
1060 u8 cluster_permitted
;
1064 * Additional max data transfer sizes
1066 __le16 max_strips_per_io
;
1069 * Controller capabilities structures
1076 u32 raid_level_1E
:1;
1080 } __attribute__ ((packed
)) raid_levels
;
1089 u32 alarm_control
:1;
1090 u32 cluster_supported
:1;
1092 u32 spanning_allowed
:1;
1093 u32 dedicated_hotspares
:1;
1094 u32 revertible_hotspares
:1;
1095 u32 foreign_config_import
:1;
1096 u32 self_diagnostic
:1;
1097 u32 mixed_redundancy_arr
:1;
1098 u32 global_hot_spares
:1;
1101 } __attribute__ ((packed
)) adapter_operations
;
1108 u32 access_policy
:1;
1109 u32 disk_cache_policy
:1;
1112 } __attribute__ ((packed
)) ld_operations
;
1120 } __attribute__ ((packed
)) stripe_sz_ops
;
1125 u32 force_offline
:1;
1126 u32 force_rebuild
:1;
1129 } __attribute__ ((packed
)) pd_operations
;
1133 u32 ctrl_supports_sas
:1;
1134 u32 ctrl_supports_sata
:1;
1135 u32 allow_mix_in_encl
:1;
1136 u32 allow_mix_in_ld
:1;
1137 u32 allow_sata_in_cluster
:1;
1140 } __attribute__ ((packed
)) pd_mix_support
;
1143 * Define ECC single-bit-error bucket information
1145 u8 ecc_bucket_count
;
1149 * Include the controller properties (changeable items)
1151 struct megasas_ctrl_prop properties
;
1154 * Define FW pkg version (set in envt v'bles on OEM basis)
1156 char package_version
[0x60];
1160 * If adapterOperations.supportMoreThan8Phys is set,
1161 * and deviceInterface.portCount is greater than 8,
1162 * SAS Addrs for first 8 ports shall be populated in
1163 * deviceInterface.portAddr, and the rest shall be
1164 * populated in deviceInterfacePortAddr2.
1166 __le64 deviceInterfacePortAddr2
[8]; /*6a0h */
1167 u8 reserved3
[128]; /*6e0h */
1170 u16 minPdRaidLevel_0
:4;
1171 u16 maxPdRaidLevel_0
:12;
1173 u16 minPdRaidLevel_1
:4;
1174 u16 maxPdRaidLevel_1
:12;
1176 u16 minPdRaidLevel_5
:4;
1177 u16 maxPdRaidLevel_5
:12;
1179 u16 minPdRaidLevel_1E
:4;
1180 u16 maxPdRaidLevel_1E
:12;
1182 u16 minPdRaidLevel_6
:4;
1183 u16 maxPdRaidLevel_6
:12;
1185 u16 minPdRaidLevel_10
:4;
1186 u16 maxPdRaidLevel_10
:12;
1188 u16 minPdRaidLevel_50
:4;
1189 u16 maxPdRaidLevel_50
:12;
1191 u16 minPdRaidLevel_60
:4;
1192 u16 maxPdRaidLevel_60
:12;
1194 u16 minPdRaidLevel_1E_RLQ0
:4;
1195 u16 maxPdRaidLevel_1E_RLQ0
:12;
1197 u16 minPdRaidLevel_1E0_RLQ0
:4;
1198 u16 maxPdRaidLevel_1E0_RLQ0
:12;
1203 __le16 maxPds
; /*780h */
1204 __le16 maxDedHSPs
; /*782h */
1205 __le16 maxGlobalHSP
; /*784h */
1206 __le16 ddfSize
; /*786h */
1207 u8 maxLdsPerArray
; /*788h */
1208 u8 partitionsInDDF
; /*789h */
1209 u8 lockKeyBinding
; /*78ah */
1210 u8 maxPITsPerLd
; /*78bh */
1211 u8 maxViewsPerLd
; /*78ch */
1212 u8 maxTargetId
; /*78dh */
1213 __le16 maxBvlVdSize
; /*78eh */
1215 __le16 maxConfigurableSSCSize
; /*790h */
1216 __le16 currentSSCsize
; /*792h */
1218 char expanderFwVersion
[12]; /*794h */
1220 __le16 PFKTrialTimeRemaining
; /*7A0h */
1222 __le16 cacheMemorySize
; /*7A2h */
1225 #if defined(__BIG_ENDIAN_BITFIELD)
1227 u32 activePassive
:2;
1228 u32 supportConfigAutoBalance
:1;
1230 u32 supportDataLDonSSCArray
:1;
1231 u32 supportPointInTimeProgress
:1;
1232 u32 supportUnevenSpans
:1;
1233 u32 dedicatedHotSparesLimited
:1;
1235 u32 supportEmulatedDrives
:1;
1236 u32 supportResetNow
:1;
1237 u32 realTimeScheduler
:1;
1238 u32 supportSSDPatrolRead
:1;
1239 u32 supportPerfTuning
:1;
1240 u32 disableOnlinePFKChange
:1;
1242 u32 supportBootTimePFKChange
:1;
1243 u32 supportSetLinkSpeed
:1;
1244 u32 supportEmergencySpares
:1;
1245 u32 supportSuspendResumeBGops
:1;
1246 u32 blockSSDWriteCacheChange
:1;
1247 u32 supportShieldState
:1;
1248 u32 supportLdBBMInfo
:1;
1249 u32 supportLdPIType3
:1;
1250 u32 supportLdPIType2
:1;
1251 u32 supportLdPIType1
:1;
1252 u32 supportPIcontroller
:1;
1254 u32 supportPIcontroller
:1;
1255 u32 supportLdPIType1
:1;
1256 u32 supportLdPIType2
:1;
1257 u32 supportLdPIType3
:1;
1258 u32 supportLdBBMInfo
:1;
1259 u32 supportShieldState
:1;
1260 u32 blockSSDWriteCacheChange
:1;
1261 u32 supportSuspendResumeBGops
:1;
1262 u32 supportEmergencySpares
:1;
1263 u32 supportSetLinkSpeed
:1;
1264 u32 supportBootTimePFKChange
:1;
1266 u32 disableOnlinePFKChange
:1;
1267 u32 supportPerfTuning
:1;
1268 u32 supportSSDPatrolRead
:1;
1269 u32 realTimeScheduler
:1;
1271 u32 supportResetNow
:1;
1272 u32 supportEmulatedDrives
:1;
1274 u32 dedicatedHotSparesLimited
:1;
1277 u32 supportUnevenSpans
:1;
1278 u32 supportPointInTimeProgress
:1;
1279 u32 supportDataLDonSSCArray
:1;
1281 u32 supportConfigAutoBalance
:1;
1282 u32 activePassive
:2;
1285 } adapterOperations2
;
1287 u8 driverVersion
[32]; /*7A8h */
1288 u8 maxDAPdCountSpinup60
; /*7C8h */
1289 u8 temperatureROC
; /*7C9h */
1290 u8 temperatureCtrl
; /*7CAh */
1291 u8 reserved4
; /*7CBh */
1292 __le16 maxConfigurablePds
; /*7CCh */
1295 u8 reserved5
[2]; /*0x7CDh */
1298 * HA cluster information
1301 #if defined(__BIG_ENDIAN_BITFIELD)
1304 u32 premiumFeatureMismatch
:1;
1305 u32 ctrlPropIncompatible
:1;
1306 u32 fwVersionMismatch
:1;
1307 u32 hwIncompatible
:1;
1308 u32 peerIsIncompatible
:1;
1309 u32 peerIsPresent
:1;
1311 u32 peerIsPresent
:1;
1312 u32 peerIsIncompatible
:1;
1313 u32 hwIncompatible
:1;
1314 u32 fwVersionMismatch
:1;
1315 u32 ctrlPropIncompatible
:1;
1316 u32 premiumFeatureMismatch
:1;
1322 char clusterId
[MEGASAS_CLUSTER_ID_SIZE
]; /*0x7D4 */
1324 u8 maxVFsSupported
; /*0x7E4*/
1325 u8 numVFsEnabled
; /*0x7E5*/
1326 u8 requestorId
; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
1327 u8 reserved
; /*0x7E7*/
1331 #if defined(__BIG_ENDIAN_BITFIELD)
1333 u32 useSeqNumJbodFP
:1;
1334 u32 supportExtendedSSCSize
:1;
1335 u32 supportDiskCacheSettingForSysPDs
:1;
1336 u32 supportCPLDUpdate
:1;
1337 u32 supportTTYLogCompression
:1;
1338 u32 discardCacheDuringLDDelete
:1;
1339 u32 supportSecurityonJBOD
:1;
1340 u32 supportCacheBypassModes
:1;
1341 u32 supportDisableSESMonitoring
:1;
1342 u32 supportForceFlash
:1;
1343 u32 supportNVDRAM
:1;
1344 u32 supportDrvActivityLEDSetting
:1;
1345 u32 supportAllowedOpsforDrvRemoval
:1;
1346 u32 supportHOQRebuild
:1;
1347 u32 supportForceTo512e
:1;
1348 u32 supportNVCacheErase
:1;
1349 u32 supportDebugQueue
:1;
1350 u32 supportSwZone
:1;
1351 u32 supportCrashDump
:1;
1352 u32 supportMaxExtLDs
:1;
1353 u32 supportT10RebuildAssist
:1;
1354 u32 supportDisableImmediateIO
:1;
1355 u32 supportThermalPollInterval
:1;
1356 u32 supportPersonalityChange
:2;
1358 u32 supportPersonalityChange
:2;
1359 u32 supportThermalPollInterval
:1;
1360 u32 supportDisableImmediateIO
:1;
1361 u32 supportT10RebuildAssist
:1;
1362 u32 supportMaxExtLDs
:1;
1363 u32 supportCrashDump
:1;
1364 u32 supportSwZone
:1;
1365 u32 supportDebugQueue
:1;
1366 u32 supportNVCacheErase
:1;
1367 u32 supportForceTo512e
:1;
1368 u32 supportHOQRebuild
:1;
1369 u32 supportAllowedOpsforDrvRemoval
:1;
1370 u32 supportDrvActivityLEDSetting
:1;
1371 u32 supportNVDRAM
:1;
1372 u32 supportForceFlash
:1;
1373 u32 supportDisableSESMonitoring
:1;
1374 u32 supportCacheBypassModes
:1;
1375 u32 supportSecurityonJBOD
:1;
1376 u32 discardCacheDuringLDDelete
:1;
1377 u32 supportTTYLogCompression
:1;
1378 u32 supportCPLDUpdate
:1;
1379 u32 supportDiskCacheSettingForSysPDs
:1;
1380 u32 supportExtendedSSCSize
:1;
1381 u32 useSeqNumJbodFP
:1;
1384 } adapterOperations3
;
1387 #if defined(__BIG_ENDIAN_BITFIELD)
1389 /* Indicates whether the CPLD image is part of
1390 * the package and stored in flash
1398 /* Null terminated string. Has the version
1399 * information if cpld_in_flash = FALSE
1401 u8 userCodeDefinition
[12];
1402 } cpld
; /* Valid only if upgradableCPLD is TRUE */
1405 #if defined(__BIG_ENDIAN_BITFIELD)
1407 u16 support_nvme_passthru
:1;
1408 u16 support_pl_debug_info
:1;
1409 u16 support_flash_comp_info
:1;
1410 u16 support_host_info
:1;
1411 u16 support_dual_fw_update
:1;
1412 u16 support_ssc_rev3
:1;
1413 u16 fw_swaps_bbu_vpd_info
:1;
1414 u16 support_pd_map_target_id
:1;
1415 u16 support_ses_ctrl_in_multipathcfg
:1;
1416 u16 image_upload_supported
:1;
1417 u16 support_encrypted_mfc
:1;
1418 u16 supported_enc_algo
:1;
1419 u16 support_ibutton_less
:1;
1420 u16 ctrl_info_ext_supported
:1;
1423 u16 ctrl_info_ext_supported
:1;
1424 u16 support_ibutton_less
:1;
1425 u16 supported_enc_algo
:1;
1426 u16 support_encrypted_mfc
:1;
1427 u16 image_upload_supported
:1;
1428 /* FW supports LUN based association and target port based */
1429 u16 support_ses_ctrl_in_multipathcfg
:1;
1430 /* association for the SES device connected in multipath mode */
1431 /* FW defines Jbod target Id within MR_PD_CFG_SEQ */
1432 u16 support_pd_map_target_id
:1;
1433 /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to
1434 * provide the data in little endian order
1436 u16 fw_swaps_bbu_vpd_info
:1;
1437 u16 support_ssc_rev3
:1;
1438 /* FW supports CacheCade 3.0, only one SSCD creation allowed */
1439 u16 support_dual_fw_update
:1;
1440 /* FW supports dual firmware update feature */
1441 u16 support_host_info
:1;
1442 /* FW supports MR_DCMD_CTRL_HOST_INFO_SET/GET */
1443 u16 support_flash_comp_info
:1;
1444 /* FW supports MR_DCMD_CTRL_FLASH_COMP_INFO_GET */
1445 u16 support_pl_debug_info
:1;
1446 /* FW supports retrieval of PL debug information through apps */
1447 u16 support_nvme_passthru
:1;
1448 /* FW supports NVMe passthru commands */
1451 } adapter_operations4
;
1452 u8 pad
[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */
1460 #if defined(__BIG_ENDIAN_BITFIELD)
1462 u32 support_pci_lane_margining
: 1;
1463 u32 support_psoc_update
:1;
1464 u32 support_force_personality_change
:1;
1465 u32 support_fde_type_mix
:1;
1466 u32 support_snap_dump
:1;
1467 u32 support_nvme_tm
:1;
1468 u32 support_oce_only
:1;
1469 u32 support_ext_mfg_vpd
:1;
1471 u32 support_cvhealth_info
:1;
1472 u32 support_profile_change
:2;
1473 u32 mr_config_ext2_supported
:1;
1475 u32 mr_config_ext2_supported
:1;
1476 u32 support_profile_change
:2;
1477 u32 support_cvhealth_info
:1;
1479 u32 support_ext_mfg_vpd
:1;
1480 u32 support_oce_only
:1;
1481 u32 support_nvme_tm
:1;
1482 u32 support_snap_dump
:1;
1483 u32 support_fde_type_mix
:1;
1484 u32 support_force_personality_change
:1;
1485 u32 support_psoc_update
:1;
1486 u32 support_pci_lane_margining
: 1;
1489 } adapter_operations5
;
1491 u32 rsvdForAdptOp
[63];
1495 u8 TaskAbortTO
; /* Timeout value in seconds used by Abort Task TM */
1496 u8 MaxResetTO
; /* Max Supported Reset timeout in seconds. */
1501 * ===============================
1502 * MegaRAID SAS driver definitions
1503 * ===============================
1505 #define MEGASAS_MAX_PD_CHANNELS 2
1506 #define MEGASAS_MAX_LD_CHANNELS 2
1507 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
1508 MEGASAS_MAX_LD_CHANNELS)
1509 #define MEGASAS_MAX_DEV_PER_CHANNEL 128
1510 #define MEGASAS_DEFAULT_INIT_ID -1
1511 #define MEGASAS_MAX_LUN 8
1512 #define MEGASAS_DEFAULT_CMD_PER_LUN 256
1513 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
1514 MEGASAS_MAX_DEV_PER_CHANNEL)
1515 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
1516 MEGASAS_MAX_DEV_PER_CHANNEL)
1518 #define MEGASAS_MAX_SECTORS (2*1024)
1519 #define MEGASAS_MAX_SECTORS_IEEE (2*128)
1520 #define MEGASAS_DBG_LVL 1
1522 #define MEGASAS_FW_BUSY 1
1524 /* Driver's internal Logging levels*/
1525 #define OCR_DEBUG (1 << 0)
1526 #define TM_DEBUG (1 << 1)
1527 #define LD_PD_DEBUG (1 << 2)
1529 #define SCAN_PD_CHANNEL 0x1
1530 #define SCAN_VD_CHANNEL 0x2
1532 #define MEGASAS_KDUMP_QUEUE_DEPTH 100
1533 #define MR_LARGE_IO_MIN_SIZE (32 * 1024)
1534 #define MR_R1_LDIO_PIGGYBACK_DEFAULT 4
1536 enum MR_SCSI_CMD_TYPE
{
1537 READ_WRITE_LDIO
= 0,
1538 NON_READ_WRITE_LDIO
= 1,
1539 READ_WRITE_SYSPDIO
= 2,
1540 NON_READ_WRITE_SYSPDIO
= 3,
1543 enum DCMD_TIMEOUT_ACTION
{
1549 enum FW_BOOT_CONTEXT
{
1556 #define PTHRU_FRAME 1
1559 * When SCSI mid-layer calls driver's reset routine, driver waits for
1560 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1561 * that the driver cannot _actually_ abort or reset pending commands. While
1562 * it is waiting for the commands to complete, it prints a diagnostic message
1563 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1565 #define MEGASAS_RESET_WAIT_TIME 180
1566 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
1567 #define MEGASAS_RESET_NOTICE_INTERVAL 5
1568 #define MEGASAS_IOCTL_CMD 0
1569 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90
1570 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16
1571 #define MEGASAS_DEFAULT_TM_TIMEOUT 50
1573 * FW reports the maximum of number of commands that it can accept (maximum
1574 * commands that can be outstanding) at any time. The driver must report a
1575 * lower number to the mid layer because it can issue a few internal commands
1576 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1579 #define MEGASAS_INT_CMDS 32
1580 #define MEGASAS_SKINNY_INT_CMDS 5
1581 #define MEGASAS_FUSION_INTERNAL_CMDS 8
1582 #define MEGASAS_FUSION_IOCTL_CMDS 3
1583 #define MEGASAS_MFI_IOCTL_CMDS 27
1585 #define MEGASAS_MAX_MSIX_QUEUES 128
1587 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1588 * SGLs based on the size of dma_addr_t
1590 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
1592 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1594 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1595 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1596 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1598 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1599 #define MFI_POLL_TIMEOUT_SECS 60
1600 #define MFI_IO_TIMEOUT_SECS 180
1601 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
1602 #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
1603 #define MEGASAS_SRIOV_MAX_RESET_TRIES_VF 1
1604 #define MEGASAS_ROUTINE_WAIT_TIME_VF 300
1605 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
1606 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1607 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
1608 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1609 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
1611 #define MFI_1068_PCSR_OFFSET 0x84
1612 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1613 #define MFI_1068_FW_READY 0xDDDD0000
1615 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1616 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1617 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
1618 #define MR_MAX_MSIX_REG_ARRAY 16
1619 #define MR_RDPQ_MODE_OFFSET 0X00800000
1621 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16
1622 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF
1623 #define MR_MIN_MAP_SIZE 0x10000
1626 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
1628 #define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET (1 << 24)
1630 #define MR_CAN_HANDLE_64_BIT_DMA_OFFSET (1 << 25)
1631 #define MR_INTR_COALESCING_SUPPORT_OFFSET (1 << 26)
1633 #define MEGASAS_WATCHDOG_THREAD_INTERVAL 1000
1634 #define MEGASAS_WAIT_FOR_NEXT_DMA_MSECS 20
1635 #define MEGASAS_WATCHDOG_WAIT_COUNT 50
1637 enum MR_ADAPTER_TYPE
{
1639 THUNDERBOLT_SERIES
= 2,
1646 * register set for both 1068 and 1078 controllers
1647 * structure extended for 1078 registers
1650 struct megasas_register_set
{
1651 u32 doorbell
; /*0000h*/
1652 u32 fusion_seq_offset
; /*0004h*/
1653 u32 fusion_host_diag
; /*0008h*/
1654 u32 reserved_01
; /*000Ch*/
1656 u32 inbound_msg_0
; /*0010h*/
1657 u32 inbound_msg_1
; /*0014h*/
1658 u32 outbound_msg_0
; /*0018h*/
1659 u32 outbound_msg_1
; /*001Ch*/
1661 u32 inbound_doorbell
; /*0020h*/
1662 u32 inbound_intr_status
; /*0024h*/
1663 u32 inbound_intr_mask
; /*0028h*/
1665 u32 outbound_doorbell
; /*002Ch*/
1666 u32 outbound_intr_status
; /*0030h*/
1667 u32 outbound_intr_mask
; /*0034h*/
1669 u32 reserved_1
[2]; /*0038h*/
1671 u32 inbound_queue_port
; /*0040h*/
1672 u32 outbound_queue_port
; /*0044h*/
1674 u32 reserved_2
[9]; /*0048h*/
1675 u32 reply_post_host_index
; /*006Ch*/
1676 u32 reserved_2_2
[12]; /*0070h*/
1678 u32 outbound_doorbell_clear
; /*00A0h*/
1680 u32 reserved_3
[3]; /*00A4h*/
1682 u32 outbound_scratch_pad_0
; /*00B0h*/
1683 u32 outbound_scratch_pad_1
; /*00B4h*/
1684 u32 outbound_scratch_pad_2
; /*00B8h*/
1685 u32 outbound_scratch_pad_3
; /*00BCh*/
1687 u32 inbound_low_queue_port
; /*00C0h*/
1689 u32 inbound_high_queue_port
; /*00C4h*/
1691 u32 inbound_single_queue_port
; /*00C8h*/
1692 u32 res_6
[11]; /*CCh*/
1695 u32 index_registers
[807]; /*00CCh*/
1696 } __attribute__ ((packed
));
1698 struct megasas_sge32
{
1703 } __attribute__ ((packed
));
1705 struct megasas_sge64
{
1710 } __attribute__ ((packed
));
1712 struct megasas_sge_skinny
{
1720 struct megasas_sge32 sge32
[1];
1721 struct megasas_sge64 sge64
[1];
1722 struct megasas_sge_skinny sge_skinny
[1];
1724 } __attribute__ ((packed
));
1726 struct megasas_header
{
1729 u8 sense_len
; /*01h */
1730 u8 cmd_status
; /*02h */
1731 u8 scsi_status
; /*03h */
1733 u8 target_id
; /*04h */
1735 u8 cdb_len
; /*06h */
1736 u8 sge_count
; /*07h */
1738 __le32 context
; /*08h */
1739 __le32 pad_0
; /*0Ch */
1741 __le16 flags
; /*10h */
1742 __le16 timeout
; /*12h */
1743 __le32 data_xferlen
; /*14h */
1745 } __attribute__ ((packed
));
1747 union megasas_sgl_frame
{
1749 struct megasas_sge32 sge32
[8];
1750 struct megasas_sge64 sge64
[5];
1752 } __attribute__ ((packed
));
1754 typedef union _MFI_CAPABILITIES
{
1756 #if defined(__BIG_ENDIAN_BITFIELD)
1758 u32 support_fw_exposed_dev_list
:1;
1759 u32 support_nvme_passthru
:1;
1760 u32 support_64bit_mode
:1;
1761 u32 support_pd_map_target_id
:1;
1762 u32 support_qd_throttling
:1;
1763 u32 support_fp_rlbypass
:1;
1764 u32 support_vfid_in_ioframe
:1;
1765 u32 support_ext_io_size
:1;
1766 u32 support_ext_queue_depth
:1;
1767 u32 security_protocol_cmds_fw
:1;
1768 u32 support_core_affinity
:1;
1769 u32 support_ndrive_r1_lb
:1;
1770 u32 support_max_255lds
:1;
1771 u32 support_fastpath_wb
:1;
1772 u32 support_additional_msix
:1;
1773 u32 support_fp_remote_lun
:1;
1775 u32 support_fp_remote_lun
:1;
1776 u32 support_additional_msix
:1;
1777 u32 support_fastpath_wb
:1;
1778 u32 support_max_255lds
:1;
1779 u32 support_ndrive_r1_lb
:1;
1780 u32 support_core_affinity
:1;
1781 u32 security_protocol_cmds_fw
:1;
1782 u32 support_ext_queue_depth
:1;
1783 u32 support_ext_io_size
:1;
1784 u32 support_vfid_in_ioframe
:1;
1785 u32 support_fp_rlbypass
:1;
1786 u32 support_qd_throttling
:1;
1787 u32 support_pd_map_target_id
:1;
1788 u32 support_64bit_mode
:1;
1789 u32 support_nvme_passthru
:1;
1790 u32 support_fw_exposed_dev_list
:1;
1797 struct megasas_init_frame
{
1800 u8 reserved_0
; /*01h */
1801 u8 cmd_status
; /*02h */
1803 u8 reserved_1
; /*03h */
1804 MFI_CAPABILITIES driver_operations
; /*04h*/
1806 __le32 context
; /*08h */
1807 __le32 pad_0
; /*0Ch */
1809 __le16 flags
; /*10h */
1810 __le16 replyqueue_mask
; /*12h */
1811 __le32 data_xfer_len
; /*14h */
1813 __le32 queue_info_new_phys_addr_lo
; /*18h */
1814 __le32 queue_info_new_phys_addr_hi
; /*1Ch */
1815 __le32 queue_info_old_phys_addr_lo
; /*20h */
1816 __le32 queue_info_old_phys_addr_hi
; /*24h */
1817 __le32 reserved_4
[2]; /*28h */
1818 __le32 system_info_lo
; /*30h */
1819 __le32 system_info_hi
; /*34h */
1820 __le32 reserved_5
[2]; /*38h */
1822 } __attribute__ ((packed
));
1824 struct megasas_init_queue_info
{
1826 __le32 init_flags
; /*00h */
1827 __le32 reply_queue_entries
; /*04h */
1829 __le32 reply_queue_start_phys_addr_lo
; /*08h */
1830 __le32 reply_queue_start_phys_addr_hi
; /*0Ch */
1831 __le32 producer_index_phys_addr_lo
; /*10h */
1832 __le32 producer_index_phys_addr_hi
; /*14h */
1833 __le32 consumer_index_phys_addr_lo
; /*18h */
1834 __le32 consumer_index_phys_addr_hi
; /*1Ch */
1836 } __attribute__ ((packed
));
1838 struct megasas_io_frame
{
1841 u8 sense_len
; /*01h */
1842 u8 cmd_status
; /*02h */
1843 u8 scsi_status
; /*03h */
1845 u8 target_id
; /*04h */
1846 u8 access_byte
; /*05h */
1847 u8 reserved_0
; /*06h */
1848 u8 sge_count
; /*07h */
1850 __le32 context
; /*08h */
1851 __le32 pad_0
; /*0Ch */
1853 __le16 flags
; /*10h */
1854 __le16 timeout
; /*12h */
1855 __le32 lba_count
; /*14h */
1857 __le32 sense_buf_phys_addr_lo
; /*18h */
1858 __le32 sense_buf_phys_addr_hi
; /*1Ch */
1860 __le32 start_lba_lo
; /*20h */
1861 __le32 start_lba_hi
; /*24h */
1863 union megasas_sgl sgl
; /*28h */
1865 } __attribute__ ((packed
));
1867 struct megasas_pthru_frame
{
1870 u8 sense_len
; /*01h */
1871 u8 cmd_status
; /*02h */
1872 u8 scsi_status
; /*03h */
1874 u8 target_id
; /*04h */
1876 u8 cdb_len
; /*06h */
1877 u8 sge_count
; /*07h */
1879 __le32 context
; /*08h */
1880 __le32 pad_0
; /*0Ch */
1882 __le16 flags
; /*10h */
1883 __le16 timeout
; /*12h */
1884 __le32 data_xfer_len
; /*14h */
1886 __le32 sense_buf_phys_addr_lo
; /*18h */
1887 __le32 sense_buf_phys_addr_hi
; /*1Ch */
1889 u8 cdb
[16]; /*20h */
1890 union megasas_sgl sgl
; /*30h */
1892 } __attribute__ ((packed
));
1894 struct megasas_dcmd_frame
{
1897 u8 reserved_0
; /*01h */
1898 u8 cmd_status
; /*02h */
1899 u8 reserved_1
[4]; /*03h */
1900 u8 sge_count
; /*07h */
1902 __le32 context
; /*08h */
1903 __le32 pad_0
; /*0Ch */
1905 __le16 flags
; /*10h */
1906 __le16 timeout
; /*12h */
1908 __le32 data_xfer_len
; /*14h */
1909 __le32 opcode
; /*18h */
1917 union megasas_sgl sgl
; /*28h */
1919 } __attribute__ ((packed
));
1921 struct megasas_abort_frame
{
1924 u8 reserved_0
; /*01h */
1925 u8 cmd_status
; /*02h */
1927 u8 reserved_1
; /*03h */
1928 __le32 reserved_2
; /*04h */
1930 __le32 context
; /*08h */
1931 __le32 pad_0
; /*0Ch */
1933 __le16 flags
; /*10h */
1934 __le16 reserved_3
; /*12h */
1935 __le32 reserved_4
; /*14h */
1937 __le32 abort_context
; /*18h */
1938 __le32 pad_1
; /*1Ch */
1940 __le32 abort_mfi_phys_addr_lo
; /*20h */
1941 __le32 abort_mfi_phys_addr_hi
; /*24h */
1943 __le32 reserved_5
[6]; /*28h */
1945 } __attribute__ ((packed
));
1947 struct megasas_smp_frame
{
1950 u8 reserved_1
; /*01h */
1951 u8 cmd_status
; /*02h */
1952 u8 connection_status
; /*03h */
1954 u8 reserved_2
[3]; /*04h */
1955 u8 sge_count
; /*07h */
1957 __le32 context
; /*08h */
1958 __le32 pad_0
; /*0Ch */
1960 __le16 flags
; /*10h */
1961 __le16 timeout
; /*12h */
1963 __le32 data_xfer_len
; /*14h */
1964 __le64 sas_addr
; /*18h */
1967 struct megasas_sge32 sge32
[2]; /* [0]: resp [1]: req */
1968 struct megasas_sge64 sge64
[2]; /* [0]: resp [1]: req */
1971 } __attribute__ ((packed
));
1973 struct megasas_stp_frame
{
1976 u8 reserved_1
; /*01h */
1977 u8 cmd_status
; /*02h */
1978 u8 reserved_2
; /*03h */
1980 u8 target_id
; /*04h */
1981 u8 reserved_3
[2]; /*05h */
1982 u8 sge_count
; /*07h */
1984 __le32 context
; /*08h */
1985 __le32 pad_0
; /*0Ch */
1987 __le16 flags
; /*10h */
1988 __le16 timeout
; /*12h */
1990 __le32 data_xfer_len
; /*14h */
1992 __le16 fis
[10]; /*18h */
1996 struct megasas_sge32 sge32
[2]; /* [0]: resp [1]: data */
1997 struct megasas_sge64 sge64
[2]; /* [0]: resp [1]: data */
2000 } __attribute__ ((packed
));
2002 union megasas_frame
{
2004 struct megasas_header hdr
;
2005 struct megasas_init_frame init
;
2006 struct megasas_io_frame io
;
2007 struct megasas_pthru_frame pthru
;
2008 struct megasas_dcmd_frame dcmd
;
2009 struct megasas_abort_frame abort
;
2010 struct megasas_smp_frame smp
;
2011 struct megasas_stp_frame stp
;
2017 * struct MR_PRIV_DEVICE - sdev private hostdata
2018 * @is_tm_capable: firmware managed tm_capable flag
2019 * @tm_busy: TM request is in progress
2021 struct MR_PRIV_DEVICE
{
2024 atomic_t r1_ldio_hint
;
2027 u8 target_reset_tmo
;
2031 union megasas_evt_class_locale
{
2034 #ifndef __BIG_ENDIAN_BITFIELD
2043 } __attribute__ ((packed
)) members
;
2047 } __attribute__ ((packed
));
2049 struct megasas_evt_log_info
{
2050 __le32 newest_seq_num
;
2051 __le32 oldest_seq_num
;
2052 __le32 clear_seq_num
;
2053 __le32 shutdown_seq_num
;
2054 __le32 boot_seq_num
;
2056 } __attribute__ ((packed
));
2058 struct megasas_progress
{
2061 __le16 elapsed_seconds
;
2063 } __attribute__ ((packed
));
2065 struct megasas_evtarg_ld
{
2071 } __attribute__ ((packed
));
2073 struct megasas_evtarg_pd
{
2078 } __attribute__ ((packed
));
2080 struct megasas_evt_detail
{
2085 union megasas_evt_class_locale cl
;
2091 struct megasas_evtarg_pd pd
;
2097 } __attribute__ ((packed
)) cdbSense
;
2099 struct megasas_evtarg_ld ld
;
2102 struct megasas_evtarg_ld ld
;
2104 } __attribute__ ((packed
)) ld_count
;
2108 struct megasas_evtarg_ld ld
;
2109 } __attribute__ ((packed
)) ld_lba
;
2112 struct megasas_evtarg_ld ld
;
2115 } __attribute__ ((packed
)) ld_owner
;
2120 struct megasas_evtarg_ld ld
;
2121 struct megasas_evtarg_pd pd
;
2122 } __attribute__ ((packed
)) ld_lba_pd_lba
;
2125 struct megasas_evtarg_ld ld
;
2126 struct megasas_progress prog
;
2127 } __attribute__ ((packed
)) ld_prog
;
2130 struct megasas_evtarg_ld ld
;
2133 } __attribute__ ((packed
)) ld_state
;
2137 struct megasas_evtarg_ld ld
;
2138 } __attribute__ ((packed
)) ld_strip
;
2140 struct megasas_evtarg_pd pd
;
2143 struct megasas_evtarg_pd pd
;
2145 } __attribute__ ((packed
)) pd_err
;
2149 struct megasas_evtarg_pd pd
;
2150 } __attribute__ ((packed
)) pd_lba
;
2154 struct megasas_evtarg_pd pd
;
2155 struct megasas_evtarg_ld ld
;
2156 } __attribute__ ((packed
)) pd_lba_ld
;
2159 struct megasas_evtarg_pd pd
;
2160 struct megasas_progress prog
;
2161 } __attribute__ ((packed
)) pd_prog
;
2164 struct megasas_evtarg_pd pd
;
2167 } __attribute__ ((packed
)) pd_state
;
2174 } __attribute__ ((packed
)) pci
;
2182 } __attribute__ ((packed
)) time
;
2188 } __attribute__ ((packed
)) ecc
;
2196 char description
[128];
2198 } __attribute__ ((packed
));
2200 struct megasas_aen_event
{
2201 struct delayed_work hotplug_work
;
2202 struct megasas_instance
*instance
;
2205 struct megasas_irq_context
{
2206 struct megasas_instance
*instance
;
2209 struct irq_poll irqpoll
;
2210 bool irq_poll_scheduled
;
2211 bool irq_line_enable
;
2214 struct MR_DRV_SYSTEM_INFO
{
2231 /* JBOD Queue depth definitions */
2232 #define MEGASAS_SATA_QD 32
2233 #define MEGASAS_SAS_QD 64
2234 #define MEGASAS_DEFAULT_PD_QD 64
2235 #define MEGASAS_NVME_QD 32
2237 #define MR_DEFAULT_NVME_PAGE_SIZE 4096
2238 #define MR_DEFAULT_NVME_PAGE_SHIFT 12
2239 #define MR_DEFAULT_NVME_MDTS_KB 128
2240 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF
2242 /*Aero performance parameters*/
2243 #define MR_HIGH_IOPS_QUEUE_COUNT 8
2244 #define MR_DEVICE_HIGH_IOPS_DEPTH 8
2245 #define MR_HIGH_IOPS_BATCH_COUNT 16
2248 MR_BALANCED_PERF_MODE
= 0,
2249 MR_IOPS_PERF_MODE
= 1,
2250 MR_LATENCY_PERF_MODE
= 2,
2253 #define MEGASAS_PERF_MODE_2STR(mode) \
2254 ((mode) == MR_BALANCED_PERF_MODE ? "Balanced" : \
2255 (mode) == MR_IOPS_PERF_MODE ? "IOPS" : \
2256 (mode) == MR_LATENCY_PERF_MODE ? "Latency" : \
2259 struct megasas_instance
{
2261 unsigned int *reply_map
;
2263 dma_addr_t producer_h
;
2265 dma_addr_t consumer_h
;
2266 struct MR_DRV_SYSTEM_INFO
*system_info_buf
;
2267 dma_addr_t system_info_h
;
2268 struct MR_LD_VF_AFFILIATION
*vf_affiliation
;
2269 dma_addr_t vf_affiliation_h
;
2270 struct MR_LD_VF_AFFILIATION_111
*vf_affiliation_111
;
2271 dma_addr_t vf_affiliation_111_h
;
2272 struct MR_CTRL_HB_HOST_MEM
*hb_host_mem
;
2273 dma_addr_t hb_host_mem_h
;
2274 struct MR_PD_INFO
*pd_info
;
2275 dma_addr_t pd_info_h
;
2276 struct MR_TARGET_PROPERTIES
*tgt_prop
;
2277 dma_addr_t tgt_prop_h
;
2279 __le32
*reply_queue
;
2280 dma_addr_t reply_queue_h
;
2282 u32
*crash_dump_buf
;
2283 dma_addr_t crash_dump_h
;
2285 struct MR_PD_LIST
*pd_list_buf
;
2286 dma_addr_t pd_list_buf_h
;
2288 struct megasas_ctrl_info
*ctrl_info_buf
;
2289 dma_addr_t ctrl_info_buf_h
;
2291 struct MR_LD_LIST
*ld_list_buf
;
2292 dma_addr_t ld_list_buf_h
;
2294 struct MR_LD_TARGETID_LIST
*ld_targetid_list_buf
;
2295 dma_addr_t ld_targetid_list_buf_h
;
2297 struct MR_HOST_DEVICE_LIST
*host_device_list_buf
;
2298 dma_addr_t host_device_list_buf_h
;
2300 struct MR_SNAPDUMP_PROPERTIES
*snapdump_prop
;
2301 dma_addr_t snapdump_prop_h
;
2303 void *crash_buf
[MAX_CRASH_DUMP_SIZE
];
2304 unsigned int fw_crash_buffer_size
;
2305 unsigned int fw_crash_state
;
2306 unsigned int fw_crash_buffer_offset
;
2309 u32 crash_dump_fw_support
;
2310 u32 crash_dump_drv_support
;
2311 u32 crash_dump_app_support
;
2312 u32 secure_jbod_support
;
2313 u32 support_morethan256jbod
; /* FW support for more than 256 PD/JBOD */
2314 bool use_seqnum_jbod_fp
; /* Added for PD sequence */
2315 bool smp_affinity_enable
;
2316 spinlock_t crashdump_lock
;
2318 struct megasas_register_set __iomem
*reg_set
;
2319 u32 __iomem
*reply_post_host_index_addr
[MR_MAX_MSIX_REG_ARRAY
];
2320 struct megasas_pd_list pd_list
[MEGASAS_MAX_PD
];
2321 struct megasas_pd_list local_pd_list
[MEGASAS_MAX_PD
];
2322 u8 ld_ids
[MEGASAS_MAX_LD_IDS
];
2332 u32 max_sectors_per_req
;
2333 bool msix_load_balance
;
2334 struct megasas_aen_event
*ev
;
2336 struct megasas_cmd
**cmd_list
;
2337 struct list_head cmd_pool
;
2338 /* used to sync fire the cmd to fw */
2339 spinlock_t mfi_pool_lock
;
2340 /* used to sync fire the cmd to fw */
2341 spinlock_t hba_lock
;
2342 /* used to synch producer, consumer ptrs in dpc */
2343 spinlock_t stream_lock
;
2344 spinlock_t completion_lock
;
2345 struct dma_pool
*frame_dma_pool
;
2346 struct dma_pool
*sense_dma_pool
;
2348 struct megasas_evt_detail
*evt_detail
;
2349 dma_addr_t evt_detail_h
;
2350 struct megasas_cmd
*aen_cmd
;
2351 struct semaphore ioctl_sem
;
2353 struct Scsi_Host
*host
;
2355 wait_queue_head_t int_cmd_wait_q
;
2356 wait_queue_head_t abort_cmd_wait_q
;
2358 struct pci_dev
*pdev
;
2360 u32 fw_support_ieee
;
2361 u32 threshold_reply_count
;
2363 atomic_t fw_outstanding
;
2364 atomic_t ldio_outstanding
;
2365 atomic_t fw_reset_no_pci_access
;
2366 atomic64_t total_io_count
;
2367 atomic64_t high_iops_outstanding
;
2369 struct megasas_instance_template
*instancet
;
2370 struct tasklet_struct isr_tasklet
;
2371 struct work_struct work_init
;
2372 struct delayed_work fw_fault_work
;
2373 struct workqueue_struct
*fw_fault_work_q
;
2374 char fault_handler_work_q_name
[48];
2380 u8 disableOnlineCtrlReset
;
2381 u8 UnevenSpanSupport
;
2384 u8 pd_list_not_supported
;
2385 u16 fw_supported_vd_count
;
2386 u16 fw_supported_pd_count
;
2388 u16 drv_supported_vd_count
;
2389 u16 drv_supported_pd_count
;
2391 atomic_t adprecovery
;
2392 unsigned long last_time
;
2396 struct list_head internal_reset_pending_q
;
2398 /* Ptr to hba specific information */
2400 unsigned int msix_vectors
;
2401 struct megasas_irq_context irq_context
[MEGASAS_MAX_MSIX_QUEUES
];
2404 struct megasas_cmd
*map_update_cmd
;
2405 struct megasas_cmd
*jbod_seq_cmd
;
2408 struct mutex reset_mutex
;
2409 struct timer_list sriov_heartbeat_timer
;
2410 char skip_heartbeat_timer_del
;
2413 char clusterId
[MEGASAS_CLUSTER_ID_SIZE
];
2416 u16 throttlequeuedepth
;
2418 u16 max_chain_frame_sz
;
2422 bool fw_sync_cache_support
;
2425 u16 max_raid_mapsize
;
2426 /* preffered count to send as LDIO irrspective of FP capable.*/
2427 u8 r1_ldio_hint_default
;
2430 bool consistent_mask_64bit
;
2431 bool support_nvme_passthru
;
2434 u8 snapdump_wait_time
;
2435 #ifdef CONFIG_DEBUG_FS
2436 struct dentry
*debugfs_root
;
2437 struct dentry
*raidmap_dump
;
2439 u8 enable_fw_dev_list
;
2440 bool atomic_desc_support
;
2441 bool support_seqnum_jbod_fp
;
2442 bool support_pci_lane_margining
;
2443 u8 low_latency_index_start
;
2447 struct MR_LD_VF_MAP
{
2449 union MR_LD_REF ref
;
2455 struct MR_LD_VF_AFFILIATION
{
2461 struct MR_LD_VF_MAP map
[1];
2464 /* Plasma 1.11 FW backward compatibility structures */
2465 #define IOV_111_OFFSET 0x7CE
2466 #define MAX_VIRTUAL_FUNCTIONS 8
2467 #define MR_LD_ACCESS_HIDDEN 15
2476 struct MR_LD_VF_MAP_111
{
2479 u8 policy
[MAX_VIRTUAL_FUNCTIONS
];
2482 struct MR_LD_VF_AFFILIATION_111
{
2487 struct MR_LD_VF_MAP_111 map
[MAX_LOGICAL_DRIVES
];
2490 struct MR_CTRL_HB_HOST_MEM
{
2492 u32 fwCounter
; /* Firmware heart beat counter */
2494 u32 debugmode
:1; /* 1=Firmware is in debug mode.
2495 Heart beat will not be updated. */
2499 u32 driverCounter
; /* Driver heart beat counter. 0x20 */
2500 u32 reserved_driver
[7];
2506 MEGASAS_HBA_OPERATIONAL
= 0,
2507 MEGASAS_ADPRESET_SM_INFAULT
= 1,
2508 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS
= 2,
2509 MEGASAS_ADPRESET_SM_OPERATIONAL
= 3,
2510 MEGASAS_HW_CRITICAL_ERROR
= 4,
2511 MEGASAS_ADPRESET_SM_POLLING
= 5,
2512 MEGASAS_ADPRESET_INPROG_SIGN
= 0xDEADDEAD,
2515 struct megasas_instance_template
{
2516 void (*fire_cmd
)(struct megasas_instance
*, dma_addr_t
, \
2517 u32
, struct megasas_register_set __iomem
*);
2519 void (*enable_intr
)(struct megasas_instance
*);
2520 void (*disable_intr
)(struct megasas_instance
*);
2522 int (*clear_intr
)(struct megasas_instance
*);
2524 u32 (*read_fw_status_reg
)(struct megasas_instance
*);
2525 int (*adp_reset
)(struct megasas_instance
*, \
2526 struct megasas_register_set __iomem
*);
2527 int (*check_reset
)(struct megasas_instance
*, \
2528 struct megasas_register_set __iomem
*);
2529 irqreturn_t (*service_isr
)(int irq
, void *devp
);
2530 void (*tasklet
)(unsigned long);
2531 u32 (*init_adapter
)(struct megasas_instance
*);
2532 u32 (*build_and_issue_cmd
) (struct megasas_instance
*,
2533 struct scsi_cmnd
*);
2534 void (*issue_dcmd
)(struct megasas_instance
*instance
,
2535 struct megasas_cmd
*cmd
);
2538 #define MEGASAS_IS_LOGICAL(sdev) \
2539 ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
2541 #define MEGASAS_DEV_INDEX(scp) \
2542 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
2545 #define MEGASAS_PD_INDEX(scp) \
2546 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \
2549 struct megasas_cmd
{
2551 union megasas_frame
*frame
;
2552 dma_addr_t frame_phys_addr
;
2554 dma_addr_t sense_phys_addr
;
2560 u8 retry_for_fw_reset
;
2563 struct list_head list
;
2564 struct scsi_cmnd
*scmd
;
2567 struct megasas_instance
*instance
;
2577 #define MAX_MGMT_ADAPTERS 1024
2578 #define MAX_IOCTL_SGE 16
2580 struct megasas_iocpacket
{
2590 struct megasas_header hdr
;
2593 struct iovec sgl
[MAX_IOCTL_SGE
];
2595 } __attribute__ ((packed
));
2597 struct megasas_aen
{
2601 u32 class_locale_word
;
2602 } __attribute__ ((packed
));
2604 #ifdef CONFIG_COMPAT
2605 struct compat_megasas_iocpacket
{
2614 struct megasas_header hdr
;
2616 struct compat_iovec sgl
[MAX_IOCTL_SGE
];
2617 } __attribute__ ((packed
));
2619 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
2622 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
2623 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
2625 struct megasas_mgmt_info
{
2628 struct megasas_instance
*instance
[MAX_MGMT_ADAPTERS
];
2632 enum MEGASAS_OCR_CAUSE
{
2634 SCSIIO_TIMEOUT_OCR
= 1,
2635 MFI_IO_TIMEOUT_OCR
= 2,
2638 enum DCMD_RETURN_STATUS
{
2646 MR_BuildRaidContext(struct megasas_instance
*instance
,
2647 struct IO_REQUEST_INFO
*io_info
,
2648 struct RAID_CONTEXT
*pRAID_Context
,
2649 struct MR_DRV_RAID_MAP_ALL
*map
, u8
**raidLUN
);
2650 u16
MR_TargetIdToLdGet(u32 ldTgtId
, struct MR_DRV_RAID_MAP_ALL
*map
);
2651 struct MR_LD_RAID
*MR_LdRaidGet(u32 ld
, struct MR_DRV_RAID_MAP_ALL
*map
);
2652 u16
MR_ArPdGet(u32 ar
, u32 arm
, struct MR_DRV_RAID_MAP_ALL
*map
);
2653 u16
MR_LdSpanArrayGet(u32 ld
, u32 span
, struct MR_DRV_RAID_MAP_ALL
*map
);
2654 __le16
MR_PdDevHandleGet(u32 pd
, struct MR_DRV_RAID_MAP_ALL
*map
);
2655 u16
MR_GetLDTgtId(u32 ld
, struct MR_DRV_RAID_MAP_ALL
*map
);
2657 __le16
get_updated_dev_handle(struct megasas_instance
*instance
,
2658 struct LD_LOAD_BALANCE_INFO
*lbInfo
,
2659 struct IO_REQUEST_INFO
*in_info
,
2660 struct MR_DRV_RAID_MAP_ALL
*drv_map
);
2661 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL
*map
,
2662 struct LD_LOAD_BALANCE_INFO
*lbInfo
);
2663 int megasas_get_ctrl_info(struct megasas_instance
*instance
);
2666 megasas_sync_pd_seq_num(struct megasas_instance
*instance
, bool pend
);
2667 void megasas_set_dynamic_target_properties(struct scsi_device
*sdev
,
2668 bool is_target_prop
);
2669 int megasas_get_target_prop(struct megasas_instance
*instance
,
2670 struct scsi_device
*sdev
);
2671 void megasas_get_snapdump_properties(struct megasas_instance
*instance
);
2673 int megasas_set_crash_dump_params(struct megasas_instance
*instance
,
2674 u8 crash_buf_state
);
2675 void megasas_free_host_crash_buffer(struct megasas_instance
*instance
);
2677 void megasas_return_cmd_fusion(struct megasas_instance
*instance
,
2678 struct megasas_cmd_fusion
*cmd
);
2679 int megasas_issue_blocked_cmd(struct megasas_instance
*instance
,
2680 struct megasas_cmd
*cmd
, int timeout
);
2681 void __megasas_return_cmd(struct megasas_instance
*instance
,
2682 struct megasas_cmd
*cmd
);
2684 void megasas_return_mfi_mpt_pthr(struct megasas_instance
*instance
,
2685 struct megasas_cmd
*cmd_mfi
, struct megasas_cmd_fusion
*cmd_fusion
);
2686 int megasas_cmd_type(struct scsi_cmnd
*cmd
);
2687 void megasas_setup_jbod_map(struct megasas_instance
*instance
);
2689 void megasas_update_sdev_properties(struct scsi_device
*sdev
);
2690 int megasas_reset_fusion(struct Scsi_Host
*shost
, int reason
);
2691 int megasas_task_abort_fusion(struct scsi_cmnd
*scmd
);
2692 int megasas_reset_target_fusion(struct scsi_cmnd
*scmd
);
2693 u32
mega_mod64(u64 dividend
, u32 divisor
);
2694 int megasas_alloc_fusion_context(struct megasas_instance
*instance
);
2695 void megasas_free_fusion_context(struct megasas_instance
*instance
);
2696 int megasas_fusion_start_watchdog(struct megasas_instance
*instance
);
2697 void megasas_fusion_stop_watchdog(struct megasas_instance
*instance
);
2699 void megasas_set_dma_settings(struct megasas_instance
*instance
,
2700 struct megasas_dcmd_frame
*dcmd
,
2701 dma_addr_t dma_addr
, u32 dma_len
);
2702 int megasas_adp_reset_wait_for_ready(struct megasas_instance
*instance
,
2705 int megasas_irqpoll(struct irq_poll
*irqpoll
, int budget
);
2706 void megasas_dump_fusion_io(struct scsi_cmnd
*scmd
);
2707 #endif /*LSI_MEGARAID_SAS_H */