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scsi: megaraid_sas: remove instance->ctrl_info
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / megaraid / megaraid_sas.h
1 /*
2 * Linux MegaRAID driver for SAS based RAID controllers
3 *
4 * Copyright (c) 2003-2013 LSI Corporation
5 * Copyright (c) 2013-2014 Avago Technologies
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 *
20 * FILE: megaraid_sas.h
21 *
22 * Authors: Avago Technologies
23 * Kashyap Desai <kashyap.desai@avagotech.com>
24 * Sumit Saxena <sumit.saxena@avagotech.com>
25 *
26 * Send feedback to: megaraidlinux.pdl@avagotech.com
27 *
28 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
29 * San Jose, California 95131
30 */
31
32 #ifndef LSI_MEGARAID_SAS_H
33 #define LSI_MEGARAID_SAS_H
34
35 /*
36 * MegaRAID SAS Driver meta data
37 */
38 #define MEGASAS_VERSION "07.702.06.00-rc1"
39 #define MEGASAS_RELDATE "June 21, 2017"
40
41 /*
42 * Device IDs
43 */
44 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
45 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
46 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
47 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
48 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
49 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
50 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
51 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
52 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
53 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
54 #define PCI_DEVICE_ID_LSI_FURY 0x005f
55 #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce
56 #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf
57 #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052
58 #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053
59 #define PCI_DEVICE_ID_LSI_VENTURA 0x0014
60 #define PCI_DEVICE_ID_LSI_CRUSADER 0x0015
61 #define PCI_DEVICE_ID_LSI_HARPOON 0x0016
62 #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017
63 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B
64 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C
65
66 /*
67 * Intel HBA SSDIDs
68 */
69 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
70 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
71 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
72 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
73 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
74 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
75 #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B
76
77 /*
78 * Intruder HBA SSDIDs
79 */
80 #define MEGARAID_INTRUDER_SSDID1 0x9371
81 #define MEGARAID_INTRUDER_SSDID2 0x9390
82 #define MEGARAID_INTRUDER_SSDID3 0x9370
83
84 /*
85 * Intel HBA branding
86 */
87 #define MEGARAID_INTEL_RS3DC080_BRANDING \
88 "Intel(R) RAID Controller RS3DC080"
89 #define MEGARAID_INTEL_RS3DC040_BRANDING \
90 "Intel(R) RAID Controller RS3DC040"
91 #define MEGARAID_INTEL_RS3SC008_BRANDING \
92 "Intel(R) RAID Controller RS3SC008"
93 #define MEGARAID_INTEL_RS3MC044_BRANDING \
94 "Intel(R) RAID Controller RS3MC044"
95 #define MEGARAID_INTEL_RS3WC080_BRANDING \
96 "Intel(R) RAID Controller RS3WC080"
97 #define MEGARAID_INTEL_RS3WC040_BRANDING \
98 "Intel(R) RAID Controller RS3WC040"
99 #define MEGARAID_INTEL_RMS3BC160_BRANDING \
100 "Intel(R) Integrated RAID Module RMS3BC160"
101
102 /*
103 * =====================================
104 * MegaRAID SAS MFI firmware definitions
105 * =====================================
106 */
107
108 /*
109 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
110 * protocol between the software and firmware. Commands are issued using
111 * "message frames"
112 */
113
114 /*
115 * FW posts its state in upper 4 bits of outbound_msg_0 register
116 */
117 #define MFI_STATE_MASK 0xF0000000
118 #define MFI_STATE_UNDEFINED 0x00000000
119 #define MFI_STATE_BB_INIT 0x10000000
120 #define MFI_STATE_FW_INIT 0x40000000
121 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
122 #define MFI_STATE_FW_INIT_2 0x70000000
123 #define MFI_STATE_DEVICE_SCAN 0x80000000
124 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
125 #define MFI_STATE_FLUSH_CACHE 0xA0000000
126 #define MFI_STATE_READY 0xB0000000
127 #define MFI_STATE_OPERATIONAL 0xC0000000
128 #define MFI_STATE_FAULT 0xF0000000
129 #define MFI_STATE_FORCE_OCR 0x00000080
130 #define MFI_STATE_DMADONE 0x00000008
131 #define MFI_STATE_CRASH_DUMP_DONE 0x00000004
132 #define MFI_RESET_REQUIRED 0x00000001
133 #define MFI_RESET_ADAPTER 0x00000002
134 #define MEGAMFI_FRAME_SIZE 64
135
136 /*
137 * During FW init, clear pending cmds & reset state using inbound_msg_0
138 *
139 * ABORT : Abort all pending cmds
140 * READY : Move from OPERATIONAL to READY state; discard queue info
141 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
142 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
143 * HOTPLUG : Resume from Hotplug
144 * MFI_STOP_ADP : Send signal to FW to stop processing
145 */
146 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
147 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
148 #define DIAG_WRITE_ENABLE (0x00000080)
149 #define DIAG_RESET_ADAPTER (0x00000004)
150
151 #define MFI_ADP_RESET 0x00000040
152 #define MFI_INIT_ABORT 0x00000001
153 #define MFI_INIT_READY 0x00000002
154 #define MFI_INIT_MFIMODE 0x00000004
155 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
156 #define MFI_INIT_HOTPLUG 0x00000010
157 #define MFI_STOP_ADP 0x00000020
158 #define MFI_RESET_FLAGS MFI_INIT_READY| \
159 MFI_INIT_MFIMODE| \
160 MFI_INIT_ABORT
161 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
162
163 /*
164 * MFI frame flags
165 */
166 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
167 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
168 #define MFI_FRAME_SGL32 0x0000
169 #define MFI_FRAME_SGL64 0x0002
170 #define MFI_FRAME_SENSE32 0x0000
171 #define MFI_FRAME_SENSE64 0x0004
172 #define MFI_FRAME_DIR_NONE 0x0000
173 #define MFI_FRAME_DIR_WRITE 0x0008
174 #define MFI_FRAME_DIR_READ 0x0010
175 #define MFI_FRAME_DIR_BOTH 0x0018
176 #define MFI_FRAME_IEEE 0x0020
177
178 /* Driver internal */
179 #define DRV_DCMD_POLLED_MODE 0x1
180 #define DRV_DCMD_SKIP_REFIRE 0x2
181
182 /*
183 * Definition for cmd_status
184 */
185 #define MFI_CMD_STATUS_POLL_MODE 0xFF
186
187 /*
188 * MFI command opcodes
189 */
190 #define MFI_CMD_INIT 0x00
191 #define MFI_CMD_LD_READ 0x01
192 #define MFI_CMD_LD_WRITE 0x02
193 #define MFI_CMD_LD_SCSI_IO 0x03
194 #define MFI_CMD_PD_SCSI_IO 0x04
195 #define MFI_CMD_DCMD 0x05
196 #define MFI_CMD_ABORT 0x06
197 #define MFI_CMD_SMP 0x07
198 #define MFI_CMD_STP 0x08
199 #define MFI_CMD_INVALID 0xff
200
201 #define MR_DCMD_CTRL_GET_INFO 0x01010000
202 #define MR_DCMD_LD_GET_LIST 0x03010000
203 #define MR_DCMD_LD_LIST_QUERY 0x03010100
204
205 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
206 #define MR_FLUSH_CTRL_CACHE 0x01
207 #define MR_FLUSH_DISK_CACHE 0x02
208
209 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
210 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
211 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
212
213 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
214 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
215 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
216 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
217
218 #define MR_DCMD_CLUSTER 0x08000000
219 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
220 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
221 #define MR_DCMD_PD_LIST_QUERY 0x02010100
222
223 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
224 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
225 #define MR_DCMD_PD_GET_INFO 0x02020000
226
227 /*
228 * Global functions
229 */
230 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);
231
232
233 /*
234 * MFI command completion codes
235 */
236 enum MFI_STAT {
237 MFI_STAT_OK = 0x00,
238 MFI_STAT_INVALID_CMD = 0x01,
239 MFI_STAT_INVALID_DCMD = 0x02,
240 MFI_STAT_INVALID_PARAMETER = 0x03,
241 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
242 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
243 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
244 MFI_STAT_APP_IN_USE = 0x07,
245 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
246 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
247 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
248 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
249 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
250 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
251 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
252 MFI_STAT_FLASH_BUSY = 0x0f,
253 MFI_STAT_FLASH_ERROR = 0x10,
254 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
255 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
256 MFI_STAT_FLASH_NOT_OPEN = 0x13,
257 MFI_STAT_FLASH_NOT_STARTED = 0x14,
258 MFI_STAT_FLUSH_FAILED = 0x15,
259 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
260 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
261 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
262 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
263 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
264 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
265 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
266 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
267 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
268 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
269 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
270 MFI_STAT_MFC_HW_ERROR = 0x21,
271 MFI_STAT_NO_HW_PRESENT = 0x22,
272 MFI_STAT_NOT_FOUND = 0x23,
273 MFI_STAT_NOT_IN_ENCL = 0x24,
274 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
275 MFI_STAT_PD_TYPE_WRONG = 0x26,
276 MFI_STAT_PR_DISABLED = 0x27,
277 MFI_STAT_ROW_INDEX_INVALID = 0x28,
278 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
279 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
280 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
281 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
282 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
283 MFI_STAT_SCSI_IO_FAILED = 0x2e,
284 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
285 MFI_STAT_SHUTDOWN_FAILED = 0x30,
286 MFI_STAT_TIME_NOT_SET = 0x31,
287 MFI_STAT_WRONG_STATE = 0x32,
288 MFI_STAT_LD_OFFLINE = 0x33,
289 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
290 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
291 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
292 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
293 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
294 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
295
296 MFI_STAT_INVALID_STATUS = 0xFF
297 };
298
299 enum mfi_evt_class {
300 MFI_EVT_CLASS_DEBUG = -2,
301 MFI_EVT_CLASS_PROGRESS = -1,
302 MFI_EVT_CLASS_INFO = 0,
303 MFI_EVT_CLASS_WARNING = 1,
304 MFI_EVT_CLASS_CRITICAL = 2,
305 MFI_EVT_CLASS_FATAL = 3,
306 MFI_EVT_CLASS_DEAD = 4
307 };
308
309 /*
310 * Crash dump related defines
311 */
312 #define MAX_CRASH_DUMP_SIZE 512
313 #define CRASH_DMA_BUF_SIZE (1024 * 1024)
314
315 enum MR_FW_CRASH_DUMP_STATE {
316 UNAVAILABLE = 0,
317 AVAILABLE = 1,
318 COPYING = 2,
319 COPIED = 3,
320 COPY_ERROR = 4,
321 };
322
323 enum _MR_CRASH_BUF_STATUS {
324 MR_CRASH_BUF_TURN_OFF = 0,
325 MR_CRASH_BUF_TURN_ON = 1,
326 };
327
328 /*
329 * Number of mailbox bytes in DCMD message frame
330 */
331 #define MFI_MBOX_SIZE 12
332
333 enum MR_EVT_CLASS {
334
335 MR_EVT_CLASS_DEBUG = -2,
336 MR_EVT_CLASS_PROGRESS = -1,
337 MR_EVT_CLASS_INFO = 0,
338 MR_EVT_CLASS_WARNING = 1,
339 MR_EVT_CLASS_CRITICAL = 2,
340 MR_EVT_CLASS_FATAL = 3,
341 MR_EVT_CLASS_DEAD = 4,
342
343 };
344
345 enum MR_EVT_LOCALE {
346
347 MR_EVT_LOCALE_LD = 0x0001,
348 MR_EVT_LOCALE_PD = 0x0002,
349 MR_EVT_LOCALE_ENCL = 0x0004,
350 MR_EVT_LOCALE_BBU = 0x0008,
351 MR_EVT_LOCALE_SAS = 0x0010,
352 MR_EVT_LOCALE_CTRL = 0x0020,
353 MR_EVT_LOCALE_CONFIG = 0x0040,
354 MR_EVT_LOCALE_CLUSTER = 0x0080,
355 MR_EVT_LOCALE_ALL = 0xffff,
356
357 };
358
359 enum MR_EVT_ARGS {
360
361 MR_EVT_ARGS_NONE,
362 MR_EVT_ARGS_CDB_SENSE,
363 MR_EVT_ARGS_LD,
364 MR_EVT_ARGS_LD_COUNT,
365 MR_EVT_ARGS_LD_LBA,
366 MR_EVT_ARGS_LD_OWNER,
367 MR_EVT_ARGS_LD_LBA_PD_LBA,
368 MR_EVT_ARGS_LD_PROG,
369 MR_EVT_ARGS_LD_STATE,
370 MR_EVT_ARGS_LD_STRIP,
371 MR_EVT_ARGS_PD,
372 MR_EVT_ARGS_PD_ERR,
373 MR_EVT_ARGS_PD_LBA,
374 MR_EVT_ARGS_PD_LBA_LD,
375 MR_EVT_ARGS_PD_PROG,
376 MR_EVT_ARGS_PD_STATE,
377 MR_EVT_ARGS_PCI,
378 MR_EVT_ARGS_RATE,
379 MR_EVT_ARGS_STR,
380 MR_EVT_ARGS_TIME,
381 MR_EVT_ARGS_ECC,
382 MR_EVT_ARGS_LD_PROP,
383 MR_EVT_ARGS_PD_SPARE,
384 MR_EVT_ARGS_PD_INDEX,
385 MR_EVT_ARGS_DIAG_PASS,
386 MR_EVT_ARGS_DIAG_FAIL,
387 MR_EVT_ARGS_PD_LBA_LBA,
388 MR_EVT_ARGS_PORT_PHY,
389 MR_EVT_ARGS_PD_MISSING,
390 MR_EVT_ARGS_PD_ADDRESS,
391 MR_EVT_ARGS_BITMAP,
392 MR_EVT_ARGS_CONNECTOR,
393 MR_EVT_ARGS_PD_PD,
394 MR_EVT_ARGS_PD_FRU,
395 MR_EVT_ARGS_PD_PATHINFO,
396 MR_EVT_ARGS_PD_POWER_STATE,
397 MR_EVT_ARGS_GENERIC,
398 };
399
400
401 #define SGE_BUFFER_SIZE 4096
402 #define MEGASAS_CLUSTER_ID_SIZE 16
403 /*
404 * define constants for device list query options
405 */
406 enum MR_PD_QUERY_TYPE {
407 MR_PD_QUERY_TYPE_ALL = 0,
408 MR_PD_QUERY_TYPE_STATE = 1,
409 MR_PD_QUERY_TYPE_POWER_STATE = 2,
410 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
411 MR_PD_QUERY_TYPE_SPEED = 4,
412 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
413 };
414
415 enum MR_LD_QUERY_TYPE {
416 MR_LD_QUERY_TYPE_ALL = 0,
417 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
418 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2,
419 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,
420 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,
421 };
422
423
424 #define MR_EVT_CFG_CLEARED 0x0004
425 #define MR_EVT_LD_STATE_CHANGE 0x0051
426 #define MR_EVT_PD_INSERTED 0x005b
427 #define MR_EVT_PD_REMOVED 0x0070
428 #define MR_EVT_LD_CREATED 0x008a
429 #define MR_EVT_LD_DELETED 0x008b
430 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
431 #define MR_EVT_LD_OFFLINE 0x00fc
432 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
433 #define MR_EVT_CTRL_PROP_CHANGED 0x012f
434
435 enum MR_PD_STATE {
436 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
437 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
438 MR_PD_STATE_HOT_SPARE = 0x02,
439 MR_PD_STATE_OFFLINE = 0x10,
440 MR_PD_STATE_FAILED = 0x11,
441 MR_PD_STATE_REBUILD = 0x14,
442 MR_PD_STATE_ONLINE = 0x18,
443 MR_PD_STATE_COPYBACK = 0x20,
444 MR_PD_STATE_SYSTEM = 0x40,
445 };
446
447 union MR_PD_REF {
448 struct {
449 u16 deviceId;
450 u16 seqNum;
451 } mrPdRef;
452 u32 ref;
453 };
454
455 /*
456 * define the DDF Type bit structure
457 */
458 union MR_PD_DDF_TYPE {
459 struct {
460 union {
461 struct {
462 #ifndef __BIG_ENDIAN_BITFIELD
463 u16 forcedPDGUID:1;
464 u16 inVD:1;
465 u16 isGlobalSpare:1;
466 u16 isSpare:1;
467 u16 isForeign:1;
468 u16 reserved:7;
469 u16 intf:4;
470 #else
471 u16 intf:4;
472 u16 reserved:7;
473 u16 isForeign:1;
474 u16 isSpare:1;
475 u16 isGlobalSpare:1;
476 u16 inVD:1;
477 u16 forcedPDGUID:1;
478 #endif
479 } pdType;
480 u16 type;
481 };
482 u16 reserved;
483 } ddf;
484 struct {
485 u32 reserved;
486 } nonDisk;
487 u32 type;
488 } __packed;
489
490 /*
491 * defines the progress structure
492 */
493 union MR_PROGRESS {
494 struct {
495 u16 progress;
496 union {
497 u16 elapsedSecs;
498 u16 elapsedSecsForLastPercent;
499 };
500 } mrProgress;
501 u32 w;
502 } __packed;
503
504 /*
505 * defines the physical drive progress structure
506 */
507 struct MR_PD_PROGRESS {
508 struct {
509 #ifndef MFI_BIG_ENDIAN
510 u32 rbld:1;
511 u32 patrol:1;
512 u32 clear:1;
513 u32 copyBack:1;
514 u32 erase:1;
515 u32 locate:1;
516 u32 reserved:26;
517 #else
518 u32 reserved:26;
519 u32 locate:1;
520 u32 erase:1;
521 u32 copyBack:1;
522 u32 clear:1;
523 u32 patrol:1;
524 u32 rbld:1;
525 #endif
526 } active;
527 union MR_PROGRESS rbld;
528 union MR_PROGRESS patrol;
529 union {
530 union MR_PROGRESS clear;
531 union MR_PROGRESS erase;
532 };
533
534 struct {
535 #ifndef MFI_BIG_ENDIAN
536 u32 rbld:1;
537 u32 patrol:1;
538 u32 clear:1;
539 u32 copyBack:1;
540 u32 erase:1;
541 u32 reserved:27;
542 #else
543 u32 reserved:27;
544 u32 erase:1;
545 u32 copyBack:1;
546 u32 clear:1;
547 u32 patrol:1;
548 u32 rbld:1;
549 #endif
550 } pause;
551
552 union MR_PROGRESS reserved[3];
553 } __packed;
554
555 struct MR_PD_INFO {
556 union MR_PD_REF ref;
557 u8 inquiryData[96];
558 u8 vpdPage83[64];
559 u8 notSupported;
560 u8 scsiDevType;
561
562 union {
563 u8 connectedPortBitmap;
564 u8 connectedPortNumbers;
565 };
566
567 u8 deviceSpeed;
568 u32 mediaErrCount;
569 u32 otherErrCount;
570 u32 predFailCount;
571 u32 lastPredFailEventSeqNum;
572
573 u16 fwState;
574 u8 disabledForRemoval;
575 u8 linkSpeed;
576 union MR_PD_DDF_TYPE state;
577
578 struct {
579 u8 count;
580 #ifndef __BIG_ENDIAN_BITFIELD
581 u8 isPathBroken:4;
582 u8 reserved3:3;
583 u8 widePortCapable:1;
584 #else
585 u8 widePortCapable:1;
586 u8 reserved3:3;
587 u8 isPathBroken:4;
588 #endif
589
590 u8 connectorIndex[2];
591 u8 reserved[4];
592 u64 sasAddr[2];
593 u8 reserved2[16];
594 } pathInfo;
595
596 u64 rawSize;
597 u64 nonCoercedSize;
598 u64 coercedSize;
599 u16 enclDeviceId;
600 u8 enclIndex;
601
602 union {
603 u8 slotNumber;
604 u8 enclConnectorIndex;
605 };
606
607 struct MR_PD_PROGRESS progInfo;
608 u8 badBlockTableFull;
609 u8 unusableInCurrentConfig;
610 u8 vpdPage83Ext[64];
611 u8 powerState;
612 u8 enclPosition;
613 u32 allowedOps;
614 u16 copyBackPartnerId;
615 u16 enclPartnerDeviceId;
616 struct {
617 #ifndef __BIG_ENDIAN_BITFIELD
618 u16 fdeCapable:1;
619 u16 fdeEnabled:1;
620 u16 secured:1;
621 u16 locked:1;
622 u16 foreign:1;
623 u16 needsEKM:1;
624 u16 reserved:10;
625 #else
626 u16 reserved:10;
627 u16 needsEKM:1;
628 u16 foreign:1;
629 u16 locked:1;
630 u16 secured:1;
631 u16 fdeEnabled:1;
632 u16 fdeCapable:1;
633 #endif
634 } security;
635 u8 mediaType;
636 u8 notCertified;
637 u8 bridgeVendor[8];
638 u8 bridgeProductIdentification[16];
639 u8 bridgeProductRevisionLevel[4];
640 u8 satBridgeExists;
641
642 u8 interfaceType;
643 u8 temperature;
644 u8 emulatedBlockSize;
645 u16 userDataBlockSize;
646 u16 reserved2;
647
648 struct {
649 #ifndef __BIG_ENDIAN_BITFIELD
650 u32 piType:3;
651 u32 piFormatted:1;
652 u32 piEligible:1;
653 u32 NCQ:1;
654 u32 WCE:1;
655 u32 commissionedSpare:1;
656 u32 emergencySpare:1;
657 u32 ineligibleForSSCD:1;
658 u32 ineligibleForLd:1;
659 u32 useSSEraseType:1;
660 u32 wceUnchanged:1;
661 u32 supportScsiUnmap:1;
662 u32 reserved:18;
663 #else
664 u32 reserved:18;
665 u32 supportScsiUnmap:1;
666 u32 wceUnchanged:1;
667 u32 useSSEraseType:1;
668 u32 ineligibleForLd:1;
669 u32 ineligibleForSSCD:1;
670 u32 emergencySpare:1;
671 u32 commissionedSpare:1;
672 u32 WCE:1;
673 u32 NCQ:1;
674 u32 piEligible:1;
675 u32 piFormatted:1;
676 u32 piType:3;
677 #endif
678 } properties;
679
680 u64 shieldDiagCompletionTime;
681 u8 shieldCounter;
682
683 u8 linkSpeedOther;
684 u8 reserved4[2];
685
686 struct {
687 #ifndef __BIG_ENDIAN_BITFIELD
688 u32 bbmErrCountSupported:1;
689 u32 bbmErrCount:31;
690 #else
691 u32 bbmErrCount:31;
692 u32 bbmErrCountSupported:1;
693 #endif
694 } bbmErr;
695
696 u8 reserved1[512-428];
697 } __packed;
698
699 /*
700 * Definition of structure used to expose attributes of VD or JBOD
701 * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP
702 * is fired by driver)
703 */
704 struct MR_TARGET_PROPERTIES {
705 u32 max_io_size_kb;
706 u32 device_qdepth;
707 u32 sector_size;
708 u8 reserved[500];
709 } __packed;
710
711 /*
712 * defines the physical drive address structure
713 */
714 struct MR_PD_ADDRESS {
715 __le16 deviceId;
716 u16 enclDeviceId;
717
718 union {
719 struct {
720 u8 enclIndex;
721 u8 slotNumber;
722 } mrPdAddress;
723 struct {
724 u8 enclPosition;
725 u8 enclConnectorIndex;
726 } mrEnclAddress;
727 };
728 u8 scsiDevType;
729 union {
730 u8 connectedPortBitmap;
731 u8 connectedPortNumbers;
732 };
733 u64 sasAddr[2];
734 } __packed;
735
736 /*
737 * defines the physical drive list structure
738 */
739 struct MR_PD_LIST {
740 __le32 size;
741 __le32 count;
742 struct MR_PD_ADDRESS addr[1];
743 } __packed;
744
745 struct megasas_pd_list {
746 u16 tid;
747 u8 driveType;
748 u8 driveState;
749 } __packed;
750
751 /*
752 * defines the logical drive reference structure
753 */
754 union MR_LD_REF {
755 struct {
756 u8 targetId;
757 u8 reserved;
758 __le16 seqNum;
759 };
760 __le32 ref;
761 } __packed;
762
763 /*
764 * defines the logical drive list structure
765 */
766 struct MR_LD_LIST {
767 __le32 ldCount;
768 __le32 reserved;
769 struct {
770 union MR_LD_REF ref;
771 u8 state;
772 u8 reserved[3];
773 __le64 size;
774 } ldList[MAX_LOGICAL_DRIVES_EXT];
775 } __packed;
776
777 struct MR_LD_TARGETID_LIST {
778 __le32 size;
779 __le32 count;
780 u8 pad[3];
781 u8 targetId[MAX_LOGICAL_DRIVES_EXT];
782 };
783
784
785 /*
786 * SAS controller properties
787 */
788 struct megasas_ctrl_prop {
789
790 u16 seq_num;
791 u16 pred_fail_poll_interval;
792 u16 intr_throttle_count;
793 u16 intr_throttle_timeouts;
794 u8 rebuild_rate;
795 u8 patrol_read_rate;
796 u8 bgi_rate;
797 u8 cc_rate;
798 u8 recon_rate;
799 u8 cache_flush_interval;
800 u8 spinup_drv_count;
801 u8 spinup_delay;
802 u8 cluster_enable;
803 u8 coercion_mode;
804 u8 alarm_enable;
805 u8 disable_auto_rebuild;
806 u8 disable_battery_warn;
807 u8 ecc_bucket_size;
808 u16 ecc_bucket_leak_rate;
809 u8 restore_hotspare_on_insertion;
810 u8 expose_encl_devices;
811 u8 maintainPdFailHistory;
812 u8 disallowHostRequestReordering;
813 u8 abortCCOnError;
814 u8 loadBalanceMode;
815 u8 disableAutoDetectBackplane;
816
817 u8 snapVDSpace;
818
819 /*
820 * Add properties that can be controlled by
821 * a bit in the following structure.
822 */
823 struct {
824 #if defined(__BIG_ENDIAN_BITFIELD)
825 u32 reserved:18;
826 u32 enableJBOD:1;
827 u32 disableSpinDownHS:1;
828 u32 allowBootWithPinnedCache:1;
829 u32 disableOnlineCtrlReset:1;
830 u32 enableSecretKeyControl:1;
831 u32 autoEnhancedImport:1;
832 u32 enableSpinDownUnconfigured:1;
833 u32 SSDPatrolReadEnabled:1;
834 u32 SSDSMARTerEnabled:1;
835 u32 disableNCQ:1;
836 u32 useFdeOnly:1;
837 u32 prCorrectUnconfiguredAreas:1;
838 u32 SMARTerEnabled:1;
839 u32 copyBackDisabled:1;
840 #else
841 u32 copyBackDisabled:1;
842 u32 SMARTerEnabled:1;
843 u32 prCorrectUnconfiguredAreas:1;
844 u32 useFdeOnly:1;
845 u32 disableNCQ:1;
846 u32 SSDSMARTerEnabled:1;
847 u32 SSDPatrolReadEnabled:1;
848 u32 enableSpinDownUnconfigured:1;
849 u32 autoEnhancedImport:1;
850 u32 enableSecretKeyControl:1;
851 u32 disableOnlineCtrlReset:1;
852 u32 allowBootWithPinnedCache:1;
853 u32 disableSpinDownHS:1;
854 u32 enableJBOD:1;
855 u32 reserved:18;
856 #endif
857 } OnOffProperties;
858 u8 autoSnapVDSpace;
859 u8 viewSpace;
860 __le16 spinDownTime;
861 u8 reserved[24];
862 } __packed;
863
864 /*
865 * SAS controller information
866 */
867 struct megasas_ctrl_info {
868
869 /*
870 * PCI device information
871 */
872 struct {
873
874 __le16 vendor_id;
875 __le16 device_id;
876 __le16 sub_vendor_id;
877 __le16 sub_device_id;
878 u8 reserved[24];
879
880 } __attribute__ ((packed)) pci;
881
882 /*
883 * Host interface information
884 */
885 struct {
886
887 u8 PCIX:1;
888 u8 PCIE:1;
889 u8 iSCSI:1;
890 u8 SAS_3G:1;
891 u8 SRIOV:1;
892 u8 reserved_0:3;
893 u8 reserved_1[6];
894 u8 port_count;
895 u64 port_addr[8];
896
897 } __attribute__ ((packed)) host_interface;
898
899 /*
900 * Device (backend) interface information
901 */
902 struct {
903
904 u8 SPI:1;
905 u8 SAS_3G:1;
906 u8 SATA_1_5G:1;
907 u8 SATA_3G:1;
908 u8 reserved_0:4;
909 u8 reserved_1[6];
910 u8 port_count;
911 u64 port_addr[8];
912
913 } __attribute__ ((packed)) device_interface;
914
915 /*
916 * List of components residing in flash. All str are null terminated
917 */
918 __le32 image_check_word;
919 __le32 image_component_count;
920
921 struct {
922
923 char name[8];
924 char version[32];
925 char build_date[16];
926 char built_time[16];
927
928 } __attribute__ ((packed)) image_component[8];
929
930 /*
931 * List of flash components that have been flashed on the card, but
932 * are not in use, pending reset of the adapter. This list will be
933 * empty if a flash operation has not occurred. All stings are null
934 * terminated
935 */
936 __le32 pending_image_component_count;
937
938 struct {
939
940 char name[8];
941 char version[32];
942 char build_date[16];
943 char build_time[16];
944
945 } __attribute__ ((packed)) pending_image_component[8];
946
947 u8 max_arms;
948 u8 max_spans;
949 u8 max_arrays;
950 u8 max_lds;
951
952 char product_name[80];
953 char serial_no[32];
954
955 /*
956 * Other physical/controller/operation information. Indicates the
957 * presence of the hardware
958 */
959 struct {
960
961 u32 bbu:1;
962 u32 alarm:1;
963 u32 nvram:1;
964 u32 uart:1;
965 u32 reserved:28;
966
967 } __attribute__ ((packed)) hw_present;
968
969 __le32 current_fw_time;
970
971 /*
972 * Maximum data transfer sizes
973 */
974 __le16 max_concurrent_cmds;
975 __le16 max_sge_count;
976 __le32 max_request_size;
977
978 /*
979 * Logical and physical device counts
980 */
981 __le16 ld_present_count;
982 __le16 ld_degraded_count;
983 __le16 ld_offline_count;
984
985 __le16 pd_present_count;
986 __le16 pd_disk_present_count;
987 __le16 pd_disk_pred_failure_count;
988 __le16 pd_disk_failed_count;
989
990 /*
991 * Memory size information
992 */
993 __le16 nvram_size;
994 __le16 memory_size;
995 __le16 flash_size;
996
997 /*
998 * Error counters
999 */
1000 __le16 mem_correctable_error_count;
1001 __le16 mem_uncorrectable_error_count;
1002
1003 /*
1004 * Cluster information
1005 */
1006 u8 cluster_permitted;
1007 u8 cluster_active;
1008
1009 /*
1010 * Additional max data transfer sizes
1011 */
1012 __le16 max_strips_per_io;
1013
1014 /*
1015 * Controller capabilities structures
1016 */
1017 struct {
1018
1019 u32 raid_level_0:1;
1020 u32 raid_level_1:1;
1021 u32 raid_level_5:1;
1022 u32 raid_level_1E:1;
1023 u32 raid_level_6:1;
1024 u32 reserved:27;
1025
1026 } __attribute__ ((packed)) raid_levels;
1027
1028 struct {
1029
1030 u32 rbld_rate:1;
1031 u32 cc_rate:1;
1032 u32 bgi_rate:1;
1033 u32 recon_rate:1;
1034 u32 patrol_rate:1;
1035 u32 alarm_control:1;
1036 u32 cluster_supported:1;
1037 u32 bbu:1;
1038 u32 spanning_allowed:1;
1039 u32 dedicated_hotspares:1;
1040 u32 revertible_hotspares:1;
1041 u32 foreign_config_import:1;
1042 u32 self_diagnostic:1;
1043 u32 mixed_redundancy_arr:1;
1044 u32 global_hot_spares:1;
1045 u32 reserved:17;
1046
1047 } __attribute__ ((packed)) adapter_operations;
1048
1049 struct {
1050
1051 u32 read_policy:1;
1052 u32 write_policy:1;
1053 u32 io_policy:1;
1054 u32 access_policy:1;
1055 u32 disk_cache_policy:1;
1056 u32 reserved:27;
1057
1058 } __attribute__ ((packed)) ld_operations;
1059
1060 struct {
1061
1062 u8 min;
1063 u8 max;
1064 u8 reserved[2];
1065
1066 } __attribute__ ((packed)) stripe_sz_ops;
1067
1068 struct {
1069
1070 u32 force_online:1;
1071 u32 force_offline:1;
1072 u32 force_rebuild:1;
1073 u32 reserved:29;
1074
1075 } __attribute__ ((packed)) pd_operations;
1076
1077 struct {
1078
1079 u32 ctrl_supports_sas:1;
1080 u32 ctrl_supports_sata:1;
1081 u32 allow_mix_in_encl:1;
1082 u32 allow_mix_in_ld:1;
1083 u32 allow_sata_in_cluster:1;
1084 u32 reserved:27;
1085
1086 } __attribute__ ((packed)) pd_mix_support;
1087
1088 /*
1089 * Define ECC single-bit-error bucket information
1090 */
1091 u8 ecc_bucket_count;
1092 u8 reserved_2[11];
1093
1094 /*
1095 * Include the controller properties (changeable items)
1096 */
1097 struct megasas_ctrl_prop properties;
1098
1099 /*
1100 * Define FW pkg version (set in envt v'bles on OEM basis)
1101 */
1102 char package_version[0x60];
1103
1104
1105 /*
1106 * If adapterOperations.supportMoreThan8Phys is set,
1107 * and deviceInterface.portCount is greater than 8,
1108 * SAS Addrs for first 8 ports shall be populated in
1109 * deviceInterface.portAddr, and the rest shall be
1110 * populated in deviceInterfacePortAddr2.
1111 */
1112 __le64 deviceInterfacePortAddr2[8]; /*6a0h */
1113 u8 reserved3[128]; /*6e0h */
1114
1115 struct { /*760h */
1116 u16 minPdRaidLevel_0:4;
1117 u16 maxPdRaidLevel_0:12;
1118
1119 u16 minPdRaidLevel_1:4;
1120 u16 maxPdRaidLevel_1:12;
1121
1122 u16 minPdRaidLevel_5:4;
1123 u16 maxPdRaidLevel_5:12;
1124
1125 u16 minPdRaidLevel_1E:4;
1126 u16 maxPdRaidLevel_1E:12;
1127
1128 u16 minPdRaidLevel_6:4;
1129 u16 maxPdRaidLevel_6:12;
1130
1131 u16 minPdRaidLevel_10:4;
1132 u16 maxPdRaidLevel_10:12;
1133
1134 u16 minPdRaidLevel_50:4;
1135 u16 maxPdRaidLevel_50:12;
1136
1137 u16 minPdRaidLevel_60:4;
1138 u16 maxPdRaidLevel_60:12;
1139
1140 u16 minPdRaidLevel_1E_RLQ0:4;
1141 u16 maxPdRaidLevel_1E_RLQ0:12;
1142
1143 u16 minPdRaidLevel_1E0_RLQ0:4;
1144 u16 maxPdRaidLevel_1E0_RLQ0:12;
1145
1146 u16 reserved[6];
1147 } pdsForRaidLevels;
1148
1149 __le16 maxPds; /*780h */
1150 __le16 maxDedHSPs; /*782h */
1151 __le16 maxGlobalHSP; /*784h */
1152 __le16 ddfSize; /*786h */
1153 u8 maxLdsPerArray; /*788h */
1154 u8 partitionsInDDF; /*789h */
1155 u8 lockKeyBinding; /*78ah */
1156 u8 maxPITsPerLd; /*78bh */
1157 u8 maxViewsPerLd; /*78ch */
1158 u8 maxTargetId; /*78dh */
1159 __le16 maxBvlVdSize; /*78eh */
1160
1161 __le16 maxConfigurableSSCSize; /*790h */
1162 __le16 currentSSCsize; /*792h */
1163
1164 char expanderFwVersion[12]; /*794h */
1165
1166 __le16 PFKTrialTimeRemaining; /*7A0h */
1167
1168 __le16 cacheMemorySize; /*7A2h */
1169
1170 struct { /*7A4h */
1171 #if defined(__BIG_ENDIAN_BITFIELD)
1172 u32 reserved:5;
1173 u32 activePassive:2;
1174 u32 supportConfigAutoBalance:1;
1175 u32 mpio:1;
1176 u32 supportDataLDonSSCArray:1;
1177 u32 supportPointInTimeProgress:1;
1178 u32 supportUnevenSpans:1;
1179 u32 dedicatedHotSparesLimited:1;
1180 u32 headlessMode:1;
1181 u32 supportEmulatedDrives:1;
1182 u32 supportResetNow:1;
1183 u32 realTimeScheduler:1;
1184 u32 supportSSDPatrolRead:1;
1185 u32 supportPerfTuning:1;
1186 u32 disableOnlinePFKChange:1;
1187 u32 supportJBOD:1;
1188 u32 supportBootTimePFKChange:1;
1189 u32 supportSetLinkSpeed:1;
1190 u32 supportEmergencySpares:1;
1191 u32 supportSuspendResumeBGops:1;
1192 u32 blockSSDWriteCacheChange:1;
1193 u32 supportShieldState:1;
1194 u32 supportLdBBMInfo:1;
1195 u32 supportLdPIType3:1;
1196 u32 supportLdPIType2:1;
1197 u32 supportLdPIType1:1;
1198 u32 supportPIcontroller:1;
1199 #else
1200 u32 supportPIcontroller:1;
1201 u32 supportLdPIType1:1;
1202 u32 supportLdPIType2:1;
1203 u32 supportLdPIType3:1;
1204 u32 supportLdBBMInfo:1;
1205 u32 supportShieldState:1;
1206 u32 blockSSDWriteCacheChange:1;
1207 u32 supportSuspendResumeBGops:1;
1208 u32 supportEmergencySpares:1;
1209 u32 supportSetLinkSpeed:1;
1210 u32 supportBootTimePFKChange:1;
1211 u32 supportJBOD:1;
1212 u32 disableOnlinePFKChange:1;
1213 u32 supportPerfTuning:1;
1214 u32 supportSSDPatrolRead:1;
1215 u32 realTimeScheduler:1;
1216
1217 u32 supportResetNow:1;
1218 u32 supportEmulatedDrives:1;
1219 u32 headlessMode:1;
1220 u32 dedicatedHotSparesLimited:1;
1221
1222
1223 u32 supportUnevenSpans:1;
1224 u32 supportPointInTimeProgress:1;
1225 u32 supportDataLDonSSCArray:1;
1226 u32 mpio:1;
1227 u32 supportConfigAutoBalance:1;
1228 u32 activePassive:2;
1229 u32 reserved:5;
1230 #endif
1231 } adapterOperations2;
1232
1233 u8 driverVersion[32]; /*7A8h */
1234 u8 maxDAPdCountSpinup60; /*7C8h */
1235 u8 temperatureROC; /*7C9h */
1236 u8 temperatureCtrl; /*7CAh */
1237 u8 reserved4; /*7CBh */
1238 __le16 maxConfigurablePds; /*7CCh */
1239
1240
1241 u8 reserved5[2]; /*0x7CDh */
1242
1243 /*
1244 * HA cluster information
1245 */
1246 struct {
1247 #if defined(__BIG_ENDIAN_BITFIELD)
1248 u32 reserved:25;
1249 u32 passive:1;
1250 u32 premiumFeatureMismatch:1;
1251 u32 ctrlPropIncompatible:1;
1252 u32 fwVersionMismatch:1;
1253 u32 hwIncompatible:1;
1254 u32 peerIsIncompatible:1;
1255 u32 peerIsPresent:1;
1256 #else
1257 u32 peerIsPresent:1;
1258 u32 peerIsIncompatible:1;
1259 u32 hwIncompatible:1;
1260 u32 fwVersionMismatch:1;
1261 u32 ctrlPropIncompatible:1;
1262 u32 premiumFeatureMismatch:1;
1263 u32 passive:1;
1264 u32 reserved:25;
1265 #endif
1266 } cluster;
1267
1268 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */
1269 struct {
1270 u8 maxVFsSupported; /*0x7E4*/
1271 u8 numVFsEnabled; /*0x7E5*/
1272 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
1273 u8 reserved; /*0x7E7*/
1274 } iov;
1275
1276 struct {
1277 #if defined(__BIG_ENDIAN_BITFIELD)
1278 u32 reserved:7;
1279 u32 useSeqNumJbodFP:1;
1280 u32 supportExtendedSSCSize:1;
1281 u32 supportDiskCacheSettingForSysPDs:1;
1282 u32 supportCPLDUpdate:1;
1283 u32 supportTTYLogCompression:1;
1284 u32 discardCacheDuringLDDelete:1;
1285 u32 supportSecurityonJBOD:1;
1286 u32 supportCacheBypassModes:1;
1287 u32 supportDisableSESMonitoring:1;
1288 u32 supportForceFlash:1;
1289 u32 supportNVDRAM:1;
1290 u32 supportDrvActivityLEDSetting:1;
1291 u32 supportAllowedOpsforDrvRemoval:1;
1292 u32 supportHOQRebuild:1;
1293 u32 supportForceTo512e:1;
1294 u32 supportNVCacheErase:1;
1295 u32 supportDebugQueue:1;
1296 u32 supportSwZone:1;
1297 u32 supportCrashDump:1;
1298 u32 supportMaxExtLDs:1;
1299 u32 supportT10RebuildAssist:1;
1300 u32 supportDisableImmediateIO:1;
1301 u32 supportThermalPollInterval:1;
1302 u32 supportPersonalityChange:2;
1303 #else
1304 u32 supportPersonalityChange:2;
1305 u32 supportThermalPollInterval:1;
1306 u32 supportDisableImmediateIO:1;
1307 u32 supportT10RebuildAssist:1;
1308 u32 supportMaxExtLDs:1;
1309 u32 supportCrashDump:1;
1310 u32 supportSwZone:1;
1311 u32 supportDebugQueue:1;
1312 u32 supportNVCacheErase:1;
1313 u32 supportForceTo512e:1;
1314 u32 supportHOQRebuild:1;
1315 u32 supportAllowedOpsforDrvRemoval:1;
1316 u32 supportDrvActivityLEDSetting:1;
1317 u32 supportNVDRAM:1;
1318 u32 supportForceFlash:1;
1319 u32 supportDisableSESMonitoring:1;
1320 u32 supportCacheBypassModes:1;
1321 u32 supportSecurityonJBOD:1;
1322 u32 discardCacheDuringLDDelete:1;
1323 u32 supportTTYLogCompression:1;
1324 u32 supportCPLDUpdate:1;
1325 u32 supportDiskCacheSettingForSysPDs:1;
1326 u32 supportExtendedSSCSize:1;
1327 u32 useSeqNumJbodFP:1;
1328 u32 reserved:7;
1329 #endif
1330 } adapterOperations3;
1331
1332 struct {
1333 #if defined(__BIG_ENDIAN_BITFIELD)
1334 u8 reserved:7;
1335 /* Indicates whether the CPLD image is part of
1336 * the package and stored in flash
1337 */
1338 u8 cpld_in_flash:1;
1339 #else
1340 u8 cpld_in_flash:1;
1341 u8 reserved:7;
1342 #endif
1343 u8 reserved1[3];
1344 /* Null terminated string. Has the version
1345 * information if cpld_in_flash = FALSE
1346 */
1347 u8 userCodeDefinition[12];
1348 } cpld; /* Valid only if upgradableCPLD is TRUE */
1349
1350 struct {
1351 #if defined(__BIG_ENDIAN_BITFIELD)
1352 u16 reserved:8;
1353 u16 fw_swaps_bbu_vpd_info:1;
1354 u16 support_pd_map_target_id:1;
1355 u16 support_ses_ctrl_in_multipathcfg:1;
1356 u16 image_upload_supported:1;
1357 u16 support_encrypted_mfc:1;
1358 u16 supported_enc_algo:1;
1359 u16 support_ibutton_less:1;
1360 u16 ctrl_info_ext_supported:1;
1361 #else
1362
1363 u16 ctrl_info_ext_supported:1;
1364 u16 support_ibutton_less:1;
1365 u16 supported_enc_algo:1;
1366 u16 support_encrypted_mfc:1;
1367 u16 image_upload_supported:1;
1368 /* FW supports LUN based association and target port based */
1369 u16 support_ses_ctrl_in_multipathcfg:1;
1370 /* association for the SES device connected in multipath mode */
1371 /* FW defines Jbod target Id within MR_PD_CFG_SEQ */
1372 u16 support_pd_map_target_id:1;
1373 /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to
1374 * provide the data in little endian order
1375 */
1376 u16 fw_swaps_bbu_vpd_info:1;
1377 u16 reserved:8;
1378 #endif
1379 } adapter_operations4;
1380 u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */
1381 } __packed;
1382
1383 /*
1384 * ===============================
1385 * MegaRAID SAS driver definitions
1386 * ===============================
1387 */
1388 #define MEGASAS_MAX_PD_CHANNELS 2
1389 #define MEGASAS_MAX_LD_CHANNELS 2
1390 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
1391 MEGASAS_MAX_LD_CHANNELS)
1392 #define MEGASAS_MAX_DEV_PER_CHANNEL 128
1393 #define MEGASAS_DEFAULT_INIT_ID -1
1394 #define MEGASAS_MAX_LUN 8
1395 #define MEGASAS_DEFAULT_CMD_PER_LUN 256
1396 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
1397 MEGASAS_MAX_DEV_PER_CHANNEL)
1398 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
1399 MEGASAS_MAX_DEV_PER_CHANNEL)
1400
1401 #define MEGASAS_MAX_SECTORS (2*1024)
1402 #define MEGASAS_MAX_SECTORS_IEEE (2*128)
1403 #define MEGASAS_DBG_LVL 1
1404
1405 #define MEGASAS_FW_BUSY 1
1406
1407 /* Driver's internal Logging levels*/
1408 #define OCR_LOGS (1 << 0)
1409
1410 #define SCAN_PD_CHANNEL 0x1
1411 #define SCAN_VD_CHANNEL 0x2
1412
1413 #define MEGASAS_KDUMP_QUEUE_DEPTH 100
1414 #define MR_LARGE_IO_MIN_SIZE (32 * 1024)
1415 #define MR_R1_LDIO_PIGGYBACK_DEFAULT 4
1416
1417 enum MR_SCSI_CMD_TYPE {
1418 READ_WRITE_LDIO = 0,
1419 NON_READ_WRITE_LDIO = 1,
1420 READ_WRITE_SYSPDIO = 2,
1421 NON_READ_WRITE_SYSPDIO = 3,
1422 };
1423
1424 enum DCMD_TIMEOUT_ACTION {
1425 INITIATE_OCR = 0,
1426 KILL_ADAPTER = 1,
1427 IGNORE_TIMEOUT = 2,
1428 };
1429
1430 enum FW_BOOT_CONTEXT {
1431 PROBE_CONTEXT = 0,
1432 OCR_CONTEXT = 1,
1433 };
1434
1435 /* Frame Type */
1436 #define IO_FRAME 0
1437 #define PTHRU_FRAME 1
1438
1439 /*
1440 * When SCSI mid-layer calls driver's reset routine, driver waits for
1441 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1442 * that the driver cannot _actually_ abort or reset pending commands. While
1443 * it is waiting for the commands to complete, it prints a diagnostic message
1444 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1445 */
1446 #define MEGASAS_RESET_WAIT_TIME 180
1447 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
1448 #define MEGASAS_RESET_NOTICE_INTERVAL 5
1449 #define MEGASAS_IOCTL_CMD 0
1450 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90
1451 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16
1452 #define MEGASAS_BLOCKED_CMD_TIMEOUT 60
1453 /*
1454 * FW reports the maximum of number of commands that it can accept (maximum
1455 * commands that can be outstanding) at any time. The driver must report a
1456 * lower number to the mid layer because it can issue a few internal commands
1457 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1458 * is shown below
1459 */
1460 #define MEGASAS_INT_CMDS 32
1461 #define MEGASAS_SKINNY_INT_CMDS 5
1462 #define MEGASAS_FUSION_INTERNAL_CMDS 8
1463 #define MEGASAS_FUSION_IOCTL_CMDS 3
1464 #define MEGASAS_MFI_IOCTL_CMDS 27
1465
1466 #define MEGASAS_MAX_MSIX_QUEUES 128
1467 /*
1468 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1469 * SGLs based on the size of dma_addr_t
1470 */
1471 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
1472
1473 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1474
1475 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1476 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1477 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1478
1479 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1480 #define MFI_POLL_TIMEOUT_SECS 60
1481 #define MFI_IO_TIMEOUT_SECS 180
1482 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
1483 #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
1484 #define MEGASAS_ROUTINE_WAIT_TIME_VF 300
1485 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
1486 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1487 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
1488 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1489 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
1490
1491 #define MFI_1068_PCSR_OFFSET 0x84
1492 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1493 #define MFI_1068_FW_READY 0xDDDD0000
1494
1495 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1496 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1497 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
1498 #define MR_MAX_MSIX_REG_ARRAY 16
1499 #define MR_RDPQ_MODE_OFFSET 0X00800000
1500
1501 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16
1502 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF
1503 #define MR_MIN_MAP_SIZE 0x10000
1504 /* 64k */
1505
1506 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
1507
1508 enum MR_ADAPTER_TYPE {
1509 MFI_SERIES = 1,
1510 THUNDERBOLT_SERIES = 2,
1511 INVADER_SERIES = 3,
1512 VENTURA_SERIES = 4,
1513 };
1514
1515 /*
1516 * register set for both 1068 and 1078 controllers
1517 * structure extended for 1078 registers
1518 */
1519
1520 struct megasas_register_set {
1521 u32 doorbell; /*0000h*/
1522 u32 fusion_seq_offset; /*0004h*/
1523 u32 fusion_host_diag; /*0008h*/
1524 u32 reserved_01; /*000Ch*/
1525
1526 u32 inbound_msg_0; /*0010h*/
1527 u32 inbound_msg_1; /*0014h*/
1528 u32 outbound_msg_0; /*0018h*/
1529 u32 outbound_msg_1; /*001Ch*/
1530
1531 u32 inbound_doorbell; /*0020h*/
1532 u32 inbound_intr_status; /*0024h*/
1533 u32 inbound_intr_mask; /*0028h*/
1534
1535 u32 outbound_doorbell; /*002Ch*/
1536 u32 outbound_intr_status; /*0030h*/
1537 u32 outbound_intr_mask; /*0034h*/
1538
1539 u32 reserved_1[2]; /*0038h*/
1540
1541 u32 inbound_queue_port; /*0040h*/
1542 u32 outbound_queue_port; /*0044h*/
1543
1544 u32 reserved_2[9]; /*0048h*/
1545 u32 reply_post_host_index; /*006Ch*/
1546 u32 reserved_2_2[12]; /*0070h*/
1547
1548 u32 outbound_doorbell_clear; /*00A0h*/
1549
1550 u32 reserved_3[3]; /*00A4h*/
1551
1552 u32 outbound_scratch_pad ; /*00B0h*/
1553 u32 outbound_scratch_pad_2; /*00B4h*/
1554 u32 outbound_scratch_pad_3; /*00B8h*/
1555 u32 outbound_scratch_pad_4; /*00BCh*/
1556
1557
1558 u32 inbound_low_queue_port ; /*00C0h*/
1559
1560 u32 inbound_high_queue_port ; /*00C4h*/
1561
1562 u32 inbound_single_queue_port; /*00C8h*/
1563 u32 res_6[11]; /*CCh*/
1564 u32 host_diag;
1565 u32 seq_offset;
1566 u32 index_registers[807]; /*00CCh*/
1567 } __attribute__ ((packed));
1568
1569 struct megasas_sge32 {
1570
1571 __le32 phys_addr;
1572 __le32 length;
1573
1574 } __attribute__ ((packed));
1575
1576 struct megasas_sge64 {
1577
1578 __le64 phys_addr;
1579 __le32 length;
1580
1581 } __attribute__ ((packed));
1582
1583 struct megasas_sge_skinny {
1584 __le64 phys_addr;
1585 __le32 length;
1586 __le32 flag;
1587 } __packed;
1588
1589 union megasas_sgl {
1590
1591 struct megasas_sge32 sge32[1];
1592 struct megasas_sge64 sge64[1];
1593 struct megasas_sge_skinny sge_skinny[1];
1594
1595 } __attribute__ ((packed));
1596
1597 struct megasas_header {
1598
1599 u8 cmd; /*00h */
1600 u8 sense_len; /*01h */
1601 u8 cmd_status; /*02h */
1602 u8 scsi_status; /*03h */
1603
1604 u8 target_id; /*04h */
1605 u8 lun; /*05h */
1606 u8 cdb_len; /*06h */
1607 u8 sge_count; /*07h */
1608
1609 __le32 context; /*08h */
1610 __le32 pad_0; /*0Ch */
1611
1612 __le16 flags; /*10h */
1613 __le16 timeout; /*12h */
1614 __le32 data_xferlen; /*14h */
1615
1616 } __attribute__ ((packed));
1617
1618 union megasas_sgl_frame {
1619
1620 struct megasas_sge32 sge32[8];
1621 struct megasas_sge64 sge64[5];
1622
1623 } __attribute__ ((packed));
1624
1625 typedef union _MFI_CAPABILITIES {
1626 struct {
1627 #if defined(__BIG_ENDIAN_BITFIELD)
1628 u32 reserved:19;
1629 u32 support_pd_map_target_id:1;
1630 u32 support_qd_throttling:1;
1631 u32 support_fp_rlbypass:1;
1632 u32 support_vfid_in_ioframe:1;
1633 u32 support_ext_io_size:1;
1634 u32 support_ext_queue_depth:1;
1635 u32 security_protocol_cmds_fw:1;
1636 u32 support_core_affinity:1;
1637 u32 support_ndrive_r1_lb:1;
1638 u32 support_max_255lds:1;
1639 u32 support_fastpath_wb:1;
1640 u32 support_additional_msix:1;
1641 u32 support_fp_remote_lun:1;
1642 #else
1643 u32 support_fp_remote_lun:1;
1644 u32 support_additional_msix:1;
1645 u32 support_fastpath_wb:1;
1646 u32 support_max_255lds:1;
1647 u32 support_ndrive_r1_lb:1;
1648 u32 support_core_affinity:1;
1649 u32 security_protocol_cmds_fw:1;
1650 u32 support_ext_queue_depth:1;
1651 u32 support_ext_io_size:1;
1652 u32 support_vfid_in_ioframe:1;
1653 u32 support_fp_rlbypass:1;
1654 u32 support_qd_throttling:1;
1655 u32 support_pd_map_target_id:1;
1656 u32 reserved:19;
1657 #endif
1658 } mfi_capabilities;
1659 __le32 reg;
1660 } MFI_CAPABILITIES;
1661
1662 struct megasas_init_frame {
1663
1664 u8 cmd; /*00h */
1665 u8 reserved_0; /*01h */
1666 u8 cmd_status; /*02h */
1667
1668 u8 reserved_1; /*03h */
1669 MFI_CAPABILITIES driver_operations; /*04h*/
1670
1671 __le32 context; /*08h */
1672 __le32 pad_0; /*0Ch */
1673
1674 __le16 flags; /*10h */
1675 __le16 reserved_3; /*12h */
1676 __le32 data_xfer_len; /*14h */
1677
1678 __le32 queue_info_new_phys_addr_lo; /*18h */
1679 __le32 queue_info_new_phys_addr_hi; /*1Ch */
1680 __le32 queue_info_old_phys_addr_lo; /*20h */
1681 __le32 queue_info_old_phys_addr_hi; /*24h */
1682 __le32 reserved_4[2]; /*28h */
1683 __le32 system_info_lo; /*30h */
1684 __le32 system_info_hi; /*34h */
1685 __le32 reserved_5[2]; /*38h */
1686
1687 } __attribute__ ((packed));
1688
1689 struct megasas_init_queue_info {
1690
1691 __le32 init_flags; /*00h */
1692 __le32 reply_queue_entries; /*04h */
1693
1694 __le32 reply_queue_start_phys_addr_lo; /*08h */
1695 __le32 reply_queue_start_phys_addr_hi; /*0Ch */
1696 __le32 producer_index_phys_addr_lo; /*10h */
1697 __le32 producer_index_phys_addr_hi; /*14h */
1698 __le32 consumer_index_phys_addr_lo; /*18h */
1699 __le32 consumer_index_phys_addr_hi; /*1Ch */
1700
1701 } __attribute__ ((packed));
1702
1703 struct megasas_io_frame {
1704
1705 u8 cmd; /*00h */
1706 u8 sense_len; /*01h */
1707 u8 cmd_status; /*02h */
1708 u8 scsi_status; /*03h */
1709
1710 u8 target_id; /*04h */
1711 u8 access_byte; /*05h */
1712 u8 reserved_0; /*06h */
1713 u8 sge_count; /*07h */
1714
1715 __le32 context; /*08h */
1716 __le32 pad_0; /*0Ch */
1717
1718 __le16 flags; /*10h */
1719 __le16 timeout; /*12h */
1720 __le32 lba_count; /*14h */
1721
1722 __le32 sense_buf_phys_addr_lo; /*18h */
1723 __le32 sense_buf_phys_addr_hi; /*1Ch */
1724
1725 __le32 start_lba_lo; /*20h */
1726 __le32 start_lba_hi; /*24h */
1727
1728 union megasas_sgl sgl; /*28h */
1729
1730 } __attribute__ ((packed));
1731
1732 struct megasas_pthru_frame {
1733
1734 u8 cmd; /*00h */
1735 u8 sense_len; /*01h */
1736 u8 cmd_status; /*02h */
1737 u8 scsi_status; /*03h */
1738
1739 u8 target_id; /*04h */
1740 u8 lun; /*05h */
1741 u8 cdb_len; /*06h */
1742 u8 sge_count; /*07h */
1743
1744 __le32 context; /*08h */
1745 __le32 pad_0; /*0Ch */
1746
1747 __le16 flags; /*10h */
1748 __le16 timeout; /*12h */
1749 __le32 data_xfer_len; /*14h */
1750
1751 __le32 sense_buf_phys_addr_lo; /*18h */
1752 __le32 sense_buf_phys_addr_hi; /*1Ch */
1753
1754 u8 cdb[16]; /*20h */
1755 union megasas_sgl sgl; /*30h */
1756
1757 } __attribute__ ((packed));
1758
1759 struct megasas_dcmd_frame {
1760
1761 u8 cmd; /*00h */
1762 u8 reserved_0; /*01h */
1763 u8 cmd_status; /*02h */
1764 u8 reserved_1[4]; /*03h */
1765 u8 sge_count; /*07h */
1766
1767 __le32 context; /*08h */
1768 __le32 pad_0; /*0Ch */
1769
1770 __le16 flags; /*10h */
1771 __le16 timeout; /*12h */
1772
1773 __le32 data_xfer_len; /*14h */
1774 __le32 opcode; /*18h */
1775
1776 union { /*1Ch */
1777 u8 b[12];
1778 __le16 s[6];
1779 __le32 w[3];
1780 } mbox;
1781
1782 union megasas_sgl sgl; /*28h */
1783
1784 } __attribute__ ((packed));
1785
1786 struct megasas_abort_frame {
1787
1788 u8 cmd; /*00h */
1789 u8 reserved_0; /*01h */
1790 u8 cmd_status; /*02h */
1791
1792 u8 reserved_1; /*03h */
1793 __le32 reserved_2; /*04h */
1794
1795 __le32 context; /*08h */
1796 __le32 pad_0; /*0Ch */
1797
1798 __le16 flags; /*10h */
1799 __le16 reserved_3; /*12h */
1800 __le32 reserved_4; /*14h */
1801
1802 __le32 abort_context; /*18h */
1803 __le32 pad_1; /*1Ch */
1804
1805 __le32 abort_mfi_phys_addr_lo; /*20h */
1806 __le32 abort_mfi_phys_addr_hi; /*24h */
1807
1808 __le32 reserved_5[6]; /*28h */
1809
1810 } __attribute__ ((packed));
1811
1812 struct megasas_smp_frame {
1813
1814 u8 cmd; /*00h */
1815 u8 reserved_1; /*01h */
1816 u8 cmd_status; /*02h */
1817 u8 connection_status; /*03h */
1818
1819 u8 reserved_2[3]; /*04h */
1820 u8 sge_count; /*07h */
1821
1822 __le32 context; /*08h */
1823 __le32 pad_0; /*0Ch */
1824
1825 __le16 flags; /*10h */
1826 __le16 timeout; /*12h */
1827
1828 __le32 data_xfer_len; /*14h */
1829 __le64 sas_addr; /*18h */
1830
1831 union {
1832 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1833 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1834 } sgl;
1835
1836 } __attribute__ ((packed));
1837
1838 struct megasas_stp_frame {
1839
1840 u8 cmd; /*00h */
1841 u8 reserved_1; /*01h */
1842 u8 cmd_status; /*02h */
1843 u8 reserved_2; /*03h */
1844
1845 u8 target_id; /*04h */
1846 u8 reserved_3[2]; /*05h */
1847 u8 sge_count; /*07h */
1848
1849 __le32 context; /*08h */
1850 __le32 pad_0; /*0Ch */
1851
1852 __le16 flags; /*10h */
1853 __le16 timeout; /*12h */
1854
1855 __le32 data_xfer_len; /*14h */
1856
1857 __le16 fis[10]; /*18h */
1858 __le32 stp_flags;
1859
1860 union {
1861 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1862 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1863 } sgl;
1864
1865 } __attribute__ ((packed));
1866
1867 union megasas_frame {
1868
1869 struct megasas_header hdr;
1870 struct megasas_init_frame init;
1871 struct megasas_io_frame io;
1872 struct megasas_pthru_frame pthru;
1873 struct megasas_dcmd_frame dcmd;
1874 struct megasas_abort_frame abort;
1875 struct megasas_smp_frame smp;
1876 struct megasas_stp_frame stp;
1877
1878 u8 raw_bytes[64];
1879 };
1880
1881 /**
1882 * struct MR_PRIV_DEVICE - sdev private hostdata
1883 * @is_tm_capable: firmware managed tm_capable flag
1884 * @tm_busy: TM request is in progress
1885 */
1886 struct MR_PRIV_DEVICE {
1887 bool is_tm_capable;
1888 bool tm_busy;
1889 atomic_t r1_ldio_hint;
1890 u8 interface_type;
1891 };
1892 struct megasas_cmd;
1893
1894 union megasas_evt_class_locale {
1895
1896 struct {
1897 #ifndef __BIG_ENDIAN_BITFIELD
1898 u16 locale;
1899 u8 reserved;
1900 s8 class;
1901 #else
1902 s8 class;
1903 u8 reserved;
1904 u16 locale;
1905 #endif
1906 } __attribute__ ((packed)) members;
1907
1908 u32 word;
1909
1910 } __attribute__ ((packed));
1911
1912 struct megasas_evt_log_info {
1913 __le32 newest_seq_num;
1914 __le32 oldest_seq_num;
1915 __le32 clear_seq_num;
1916 __le32 shutdown_seq_num;
1917 __le32 boot_seq_num;
1918
1919 } __attribute__ ((packed));
1920
1921 struct megasas_progress {
1922
1923 __le16 progress;
1924 __le16 elapsed_seconds;
1925
1926 } __attribute__ ((packed));
1927
1928 struct megasas_evtarg_ld {
1929
1930 u16 target_id;
1931 u8 ld_index;
1932 u8 reserved;
1933
1934 } __attribute__ ((packed));
1935
1936 struct megasas_evtarg_pd {
1937 u16 device_id;
1938 u8 encl_index;
1939 u8 slot_number;
1940
1941 } __attribute__ ((packed));
1942
1943 struct megasas_evt_detail {
1944
1945 __le32 seq_num;
1946 __le32 time_stamp;
1947 __le32 code;
1948 union megasas_evt_class_locale cl;
1949 u8 arg_type;
1950 u8 reserved1[15];
1951
1952 union {
1953 struct {
1954 struct megasas_evtarg_pd pd;
1955 u8 cdb_length;
1956 u8 sense_length;
1957 u8 reserved[2];
1958 u8 cdb[16];
1959 u8 sense[64];
1960 } __attribute__ ((packed)) cdbSense;
1961
1962 struct megasas_evtarg_ld ld;
1963
1964 struct {
1965 struct megasas_evtarg_ld ld;
1966 __le64 count;
1967 } __attribute__ ((packed)) ld_count;
1968
1969 struct {
1970 __le64 lba;
1971 struct megasas_evtarg_ld ld;
1972 } __attribute__ ((packed)) ld_lba;
1973
1974 struct {
1975 struct megasas_evtarg_ld ld;
1976 __le32 prevOwner;
1977 __le32 newOwner;
1978 } __attribute__ ((packed)) ld_owner;
1979
1980 struct {
1981 u64 ld_lba;
1982 u64 pd_lba;
1983 struct megasas_evtarg_ld ld;
1984 struct megasas_evtarg_pd pd;
1985 } __attribute__ ((packed)) ld_lba_pd_lba;
1986
1987 struct {
1988 struct megasas_evtarg_ld ld;
1989 struct megasas_progress prog;
1990 } __attribute__ ((packed)) ld_prog;
1991
1992 struct {
1993 struct megasas_evtarg_ld ld;
1994 u32 prev_state;
1995 u32 new_state;
1996 } __attribute__ ((packed)) ld_state;
1997
1998 struct {
1999 u64 strip;
2000 struct megasas_evtarg_ld ld;
2001 } __attribute__ ((packed)) ld_strip;
2002
2003 struct megasas_evtarg_pd pd;
2004
2005 struct {
2006 struct megasas_evtarg_pd pd;
2007 u32 err;
2008 } __attribute__ ((packed)) pd_err;
2009
2010 struct {
2011 u64 lba;
2012 struct megasas_evtarg_pd pd;
2013 } __attribute__ ((packed)) pd_lba;
2014
2015 struct {
2016 u64 lba;
2017 struct megasas_evtarg_pd pd;
2018 struct megasas_evtarg_ld ld;
2019 } __attribute__ ((packed)) pd_lba_ld;
2020
2021 struct {
2022 struct megasas_evtarg_pd pd;
2023 struct megasas_progress prog;
2024 } __attribute__ ((packed)) pd_prog;
2025
2026 struct {
2027 struct megasas_evtarg_pd pd;
2028 u32 prevState;
2029 u32 newState;
2030 } __attribute__ ((packed)) pd_state;
2031
2032 struct {
2033 u16 vendorId;
2034 __le16 deviceId;
2035 u16 subVendorId;
2036 u16 subDeviceId;
2037 } __attribute__ ((packed)) pci;
2038
2039 u32 rate;
2040 char str[96];
2041
2042 struct {
2043 u32 rtc;
2044 u32 elapsedSeconds;
2045 } __attribute__ ((packed)) time;
2046
2047 struct {
2048 u32 ecar;
2049 u32 elog;
2050 char str[64];
2051 } __attribute__ ((packed)) ecc;
2052
2053 u8 b[96];
2054 __le16 s[48];
2055 __le32 w[24];
2056 __le64 d[12];
2057 } args;
2058
2059 char description[128];
2060
2061 } __attribute__ ((packed));
2062
2063 struct megasas_aen_event {
2064 struct delayed_work hotplug_work;
2065 struct megasas_instance *instance;
2066 };
2067
2068 struct megasas_irq_context {
2069 struct megasas_instance *instance;
2070 u32 MSIxIndex;
2071 };
2072
2073 struct MR_DRV_SYSTEM_INFO {
2074 u8 infoVersion;
2075 u8 systemIdLength;
2076 u16 reserved0;
2077 u8 systemId[64];
2078 u8 reserved[1980];
2079 };
2080
2081 enum MR_PD_TYPE {
2082 UNKNOWN_DRIVE = 0,
2083 PARALLEL_SCSI = 1,
2084 SAS_PD = 2,
2085 SATA_PD = 3,
2086 FC_PD = 4,
2087 NVME_PD = 5,
2088 };
2089
2090 /* JBOD Queue depth definitions */
2091 #define MEGASAS_SATA_QD 32
2092 #define MEGASAS_SAS_QD 64
2093 #define MEGASAS_DEFAULT_PD_QD 64
2094 #define MEGASAS_NVME_QD 32
2095
2096 #define MR_DEFAULT_NVME_PAGE_SIZE 4096
2097 #define MR_DEFAULT_NVME_PAGE_SHIFT 12
2098 #define MR_DEFAULT_NVME_MDTS_KB 128
2099 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF
2100
2101 struct megasas_instance {
2102
2103 __le32 *producer;
2104 dma_addr_t producer_h;
2105 __le32 *consumer;
2106 dma_addr_t consumer_h;
2107 struct MR_DRV_SYSTEM_INFO *system_info_buf;
2108 dma_addr_t system_info_h;
2109 struct MR_LD_VF_AFFILIATION *vf_affiliation;
2110 dma_addr_t vf_affiliation_h;
2111 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
2112 dma_addr_t vf_affiliation_111_h;
2113 struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
2114 dma_addr_t hb_host_mem_h;
2115 struct MR_PD_INFO *pd_info;
2116 dma_addr_t pd_info_h;
2117 struct MR_TARGET_PROPERTIES *tgt_prop;
2118 dma_addr_t tgt_prop_h;
2119
2120 __le32 *reply_queue;
2121 dma_addr_t reply_queue_h;
2122
2123 u32 *crash_dump_buf;
2124 dma_addr_t crash_dump_h;
2125
2126 struct MR_PD_LIST *pd_list_buf;
2127 dma_addr_t pd_list_buf_h;
2128
2129 struct megasas_ctrl_info *ctrl_info_buf;
2130 dma_addr_t ctrl_info_buf_h;
2131
2132 struct MR_LD_LIST *ld_list_buf;
2133 dma_addr_t ld_list_buf_h;
2134
2135 struct MR_LD_TARGETID_LIST *ld_targetid_list_buf;
2136 dma_addr_t ld_targetid_list_buf_h;
2137
2138 void *crash_buf[MAX_CRASH_DUMP_SIZE];
2139 unsigned int fw_crash_buffer_size;
2140 unsigned int fw_crash_state;
2141 unsigned int fw_crash_buffer_offset;
2142 u32 drv_buf_index;
2143 u32 drv_buf_alloc;
2144 u32 crash_dump_fw_support;
2145 u32 crash_dump_drv_support;
2146 u32 crash_dump_app_support;
2147 u32 secure_jbod_support;
2148 u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */
2149 bool use_seqnum_jbod_fp; /* Added for PD sequence */
2150 spinlock_t crashdump_lock;
2151
2152 struct megasas_register_set __iomem *reg_set;
2153 u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
2154 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
2155 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD];
2156 u8 ld_ids[MEGASAS_MAX_LD_IDS];
2157 s8 init_id;
2158
2159 u16 max_num_sge;
2160 u16 max_fw_cmds;
2161 u16 max_mpt_cmds;
2162 u16 max_mfi_cmds;
2163 u16 max_scsi_cmds;
2164 u16 ldio_threshold;
2165 u16 cur_can_queue;
2166 u32 max_sectors_per_req;
2167 struct megasas_aen_event *ev;
2168
2169 struct megasas_cmd **cmd_list;
2170 struct list_head cmd_pool;
2171 /* used to sync fire the cmd to fw */
2172 spinlock_t mfi_pool_lock;
2173 /* used to sync fire the cmd to fw */
2174 spinlock_t hba_lock;
2175 /* used to synch producer, consumer ptrs in dpc */
2176 spinlock_t stream_lock;
2177 spinlock_t completion_lock;
2178 struct dma_pool *frame_dma_pool;
2179 struct dma_pool *sense_dma_pool;
2180
2181 struct megasas_evt_detail *evt_detail;
2182 dma_addr_t evt_detail_h;
2183 struct megasas_cmd *aen_cmd;
2184 struct mutex hba_mutex;
2185 struct semaphore ioctl_sem;
2186
2187 struct Scsi_Host *host;
2188
2189 wait_queue_head_t int_cmd_wait_q;
2190 wait_queue_head_t abort_cmd_wait_q;
2191
2192 struct pci_dev *pdev;
2193 u32 unique_id;
2194 u32 fw_support_ieee;
2195
2196 atomic_t fw_outstanding;
2197 atomic_t ldio_outstanding;
2198 atomic_t fw_reset_no_pci_access;
2199 atomic_t ieee_sgl;
2200 atomic_t prp_sgl;
2201 atomic_t sge_holes_type1;
2202 atomic_t sge_holes_type2;
2203 atomic_t sge_holes_type3;
2204
2205 struct megasas_instance_template *instancet;
2206 struct tasklet_struct isr_tasklet;
2207 struct work_struct work_init;
2208 struct work_struct crash_init;
2209
2210 u8 flag;
2211 u8 unload;
2212 u8 flag_ieee;
2213 u8 issuepend_done;
2214 u8 disableOnlineCtrlReset;
2215 u8 UnevenSpanSupport;
2216
2217 u8 supportmax256vd;
2218 u8 pd_list_not_supported;
2219 u16 fw_supported_vd_count;
2220 u16 fw_supported_pd_count;
2221
2222 u16 drv_supported_vd_count;
2223 u16 drv_supported_pd_count;
2224
2225 atomic_t adprecovery;
2226 unsigned long last_time;
2227 u32 mfiStatus;
2228 u32 last_seq_num;
2229
2230 struct list_head internal_reset_pending_q;
2231
2232 /* Ptr to hba specific information */
2233 void *ctrl_context;
2234 unsigned int msix_vectors;
2235 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
2236 u64 map_id;
2237 u64 pd_seq_map_id;
2238 struct megasas_cmd *map_update_cmd;
2239 struct megasas_cmd *jbod_seq_cmd;
2240 unsigned long bar;
2241 long reset_flags;
2242 struct mutex reset_mutex;
2243 struct timer_list sriov_heartbeat_timer;
2244 char skip_heartbeat_timer_del;
2245 u8 requestorId;
2246 char PlasmaFW111;
2247 char clusterId[MEGASAS_CLUSTER_ID_SIZE];
2248 u8 peerIsPresent;
2249 u8 passive;
2250 u16 throttlequeuedepth;
2251 u8 mask_interrupts;
2252 u16 max_chain_frame_sz;
2253 u8 is_imr;
2254 u8 is_rdpq;
2255 bool dev_handle;
2256 bool fw_sync_cache_support;
2257 u32 mfi_frame_size;
2258 bool msix_combined;
2259 u16 max_raid_mapsize;
2260 /* preffered count to send as LDIO irrspective of FP capable.*/
2261 u8 r1_ldio_hint_default;
2262 u32 nvme_page_size;
2263 u8 adapter_type;
2264 };
2265 struct MR_LD_VF_MAP {
2266 u32 size;
2267 union MR_LD_REF ref;
2268 u8 ldVfCount;
2269 u8 reserved[6];
2270 u8 policy[1];
2271 };
2272
2273 struct MR_LD_VF_AFFILIATION {
2274 u32 size;
2275 u8 ldCount;
2276 u8 vfCount;
2277 u8 thisVf;
2278 u8 reserved[9];
2279 struct MR_LD_VF_MAP map[1];
2280 };
2281
2282 /* Plasma 1.11 FW backward compatibility structures */
2283 #define IOV_111_OFFSET 0x7CE
2284 #define MAX_VIRTUAL_FUNCTIONS 8
2285 #define MR_LD_ACCESS_HIDDEN 15
2286
2287 struct IOV_111 {
2288 u8 maxVFsSupported;
2289 u8 numVFsEnabled;
2290 u8 requestorId;
2291 u8 reserved[5];
2292 };
2293
2294 struct MR_LD_VF_MAP_111 {
2295 u8 targetId;
2296 u8 reserved[3];
2297 u8 policy[MAX_VIRTUAL_FUNCTIONS];
2298 };
2299
2300 struct MR_LD_VF_AFFILIATION_111 {
2301 u8 vdCount;
2302 u8 vfCount;
2303 u8 thisVf;
2304 u8 reserved[5];
2305 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
2306 };
2307
2308 struct MR_CTRL_HB_HOST_MEM {
2309 struct {
2310 u32 fwCounter; /* Firmware heart beat counter */
2311 struct {
2312 u32 debugmode:1; /* 1=Firmware is in debug mode.
2313 Heart beat will not be updated. */
2314 u32 reserved:31;
2315 } debug;
2316 u32 reserved_fw[6];
2317 u32 driverCounter; /* Driver heart beat counter. 0x20 */
2318 u32 reserved_driver[7];
2319 } HB;
2320 u8 pad[0x400-0x40];
2321 };
2322
2323 enum {
2324 MEGASAS_HBA_OPERATIONAL = 0,
2325 MEGASAS_ADPRESET_SM_INFAULT = 1,
2326 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
2327 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
2328 MEGASAS_HW_CRITICAL_ERROR = 4,
2329 MEGASAS_ADPRESET_SM_POLLING = 5,
2330 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
2331 };
2332
2333 struct megasas_instance_template {
2334 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
2335 u32, struct megasas_register_set __iomem *);
2336
2337 void (*enable_intr)(struct megasas_instance *);
2338 void (*disable_intr)(struct megasas_instance *);
2339
2340 int (*clear_intr)(struct megasas_register_set __iomem *);
2341
2342 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
2343 int (*adp_reset)(struct megasas_instance *, \
2344 struct megasas_register_set __iomem *);
2345 int (*check_reset)(struct megasas_instance *, \
2346 struct megasas_register_set __iomem *);
2347 irqreturn_t (*service_isr)(int irq, void *devp);
2348 void (*tasklet)(unsigned long);
2349 u32 (*init_adapter)(struct megasas_instance *);
2350 u32 (*build_and_issue_cmd) (struct megasas_instance *,
2351 struct scsi_cmnd *);
2352 void (*issue_dcmd)(struct megasas_instance *instance,
2353 struct megasas_cmd *cmd);
2354 };
2355
2356 #define MEGASAS_IS_LOGICAL(sdev) \
2357 ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
2358
2359 #define MEGASAS_DEV_INDEX(scp) \
2360 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
2361 scp->device->id)
2362
2363 #define MEGASAS_PD_INDEX(scp) \
2364 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \
2365 scp->device->id)
2366
2367 struct megasas_cmd {
2368
2369 union megasas_frame *frame;
2370 dma_addr_t frame_phys_addr;
2371 u8 *sense;
2372 dma_addr_t sense_phys_addr;
2373
2374 u32 index;
2375 u8 sync_cmd;
2376 u8 cmd_status_drv;
2377 u8 abort_aen;
2378 u8 retry_for_fw_reset;
2379
2380
2381 struct list_head list;
2382 struct scsi_cmnd *scmd;
2383 u8 flags;
2384
2385 struct megasas_instance *instance;
2386 union {
2387 struct {
2388 u16 smid;
2389 u16 resvd;
2390 } context;
2391 u32 frame_count;
2392 };
2393 };
2394
2395 #define MAX_MGMT_ADAPTERS 1024
2396 #define MAX_IOCTL_SGE 16
2397
2398 struct megasas_iocpacket {
2399
2400 u16 host_no;
2401 u16 __pad1;
2402 u32 sgl_off;
2403 u32 sge_count;
2404 u32 sense_off;
2405 u32 sense_len;
2406 union {
2407 u8 raw[128];
2408 struct megasas_header hdr;
2409 } frame;
2410
2411 struct iovec sgl[MAX_IOCTL_SGE];
2412
2413 } __attribute__ ((packed));
2414
2415 struct megasas_aen {
2416 u16 host_no;
2417 u16 __pad1;
2418 u32 seq_num;
2419 u32 class_locale_word;
2420 } __attribute__ ((packed));
2421
2422 #ifdef CONFIG_COMPAT
2423 struct compat_megasas_iocpacket {
2424 u16 host_no;
2425 u16 __pad1;
2426 u32 sgl_off;
2427 u32 sge_count;
2428 u32 sense_off;
2429 u32 sense_len;
2430 union {
2431 u8 raw[128];
2432 struct megasas_header hdr;
2433 } frame;
2434 struct compat_iovec sgl[MAX_IOCTL_SGE];
2435 } __attribute__ ((packed));
2436
2437 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
2438 #endif
2439
2440 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
2441 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
2442
2443 struct megasas_mgmt_info {
2444
2445 u16 count;
2446 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
2447 int max_index;
2448 };
2449
2450 enum MEGASAS_OCR_CAUSE {
2451 FW_FAULT_OCR = 0,
2452 SCSIIO_TIMEOUT_OCR = 1,
2453 MFI_IO_TIMEOUT_OCR = 2,
2454 };
2455
2456 enum DCMD_RETURN_STATUS {
2457 DCMD_SUCCESS = 0,
2458 DCMD_TIMEOUT = 1,
2459 DCMD_FAILED = 2,
2460 DCMD_NOT_FIRED = 3,
2461 };
2462
2463 u8
2464 MR_BuildRaidContext(struct megasas_instance *instance,
2465 struct IO_REQUEST_INFO *io_info,
2466 struct RAID_CONTEXT *pRAID_Context,
2467 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
2468 u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
2469 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2470 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
2471 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
2472 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
2473 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2474
2475 __le16 get_updated_dev_handle(struct megasas_instance *instance,
2476 struct LD_LOAD_BALANCE_INFO *lbInfo,
2477 struct IO_REQUEST_INFO *in_info,
2478 struct MR_DRV_RAID_MAP_ALL *drv_map);
2479 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
2480 struct LD_LOAD_BALANCE_INFO *lbInfo);
2481 int megasas_get_ctrl_info(struct megasas_instance *instance);
2482 /* PD sequence */
2483 int
2484 megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
2485 void megasas_set_dynamic_target_properties(struct scsi_device *sdev);
2486 int megasas_set_crash_dump_params(struct megasas_instance *instance,
2487 u8 crash_buf_state);
2488 void megasas_free_host_crash_buffer(struct megasas_instance *instance);
2489 void megasas_fusion_crash_dump_wq(struct work_struct *work);
2490
2491 void megasas_return_cmd_fusion(struct megasas_instance *instance,
2492 struct megasas_cmd_fusion *cmd);
2493 int megasas_issue_blocked_cmd(struct megasas_instance *instance,
2494 struct megasas_cmd *cmd, int timeout);
2495 void __megasas_return_cmd(struct megasas_instance *instance,
2496 struct megasas_cmd *cmd);
2497
2498 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
2499 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
2500 int megasas_cmd_type(struct scsi_cmnd *cmd);
2501 void megasas_setup_jbod_map(struct megasas_instance *instance);
2502
2503 void megasas_update_sdev_properties(struct scsi_device *sdev);
2504 int megasas_reset_fusion(struct Scsi_Host *shost, int reason);
2505 int megasas_task_abort_fusion(struct scsi_cmnd *scmd);
2506 int megasas_reset_target_fusion(struct scsi_cmnd *scmd);
2507 u32 mega_mod64(u64 dividend, u32 divisor);
2508 int megasas_alloc_fusion_context(struct megasas_instance *instance);
2509 void megasas_free_fusion_context(struct megasas_instance *instance);
2510 #endif /*LSI_MEGARAID_SAS_H */
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