2 * Linux MegaRAID driver for SAS based RAID controllers
4 * Copyright (c) 2003-2013 LSI Corporation
5 * Copyright (c) 2013-2014 Avago Technologies
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 * FILE: megaraid_sas.h
22 * Authors: Avago Technologies
23 * Kashyap Desai <kashyap.desai@avagotech.com>
24 * Sumit Saxena <sumit.saxena@avagotech.com>
26 * Send feedback to: megaraidlinux.pdl@avagotech.com
28 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
29 * San Jose, California 95131
32 #ifndef LSI_MEGARAID_SAS_H
33 #define LSI_MEGARAID_SAS_H
36 * MegaRAID SAS Driver meta data
38 #define MEGASAS_VERSION "07.702.06.00-rc1"
39 #define MEGASAS_RELDATE "June 21, 2017"
44 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
45 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
46 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
47 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
48 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
49 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
50 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
51 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
52 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
53 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
54 #define PCI_DEVICE_ID_LSI_FURY 0x005f
55 #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce
56 #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf
57 #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052
58 #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053
59 #define PCI_DEVICE_ID_LSI_VENTURA 0x0014
60 #define PCI_DEVICE_ID_LSI_HARPOON 0x0016
61 #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017
62 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B
63 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C
68 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
69 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
70 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
71 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
72 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
73 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
74 #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B
79 #define MEGARAID_INTRUDER_SSDID1 0x9371
80 #define MEGARAID_INTRUDER_SSDID2 0x9390
81 #define MEGARAID_INTRUDER_SSDID3 0x9370
86 #define MEGARAID_INTEL_RS3DC080_BRANDING \
87 "Intel(R) RAID Controller RS3DC080"
88 #define MEGARAID_INTEL_RS3DC040_BRANDING \
89 "Intel(R) RAID Controller RS3DC040"
90 #define MEGARAID_INTEL_RS3SC008_BRANDING \
91 "Intel(R) RAID Controller RS3SC008"
92 #define MEGARAID_INTEL_RS3MC044_BRANDING \
93 "Intel(R) RAID Controller RS3MC044"
94 #define MEGARAID_INTEL_RS3WC080_BRANDING \
95 "Intel(R) RAID Controller RS3WC080"
96 #define MEGARAID_INTEL_RS3WC040_BRANDING \
97 "Intel(R) RAID Controller RS3WC040"
98 #define MEGARAID_INTEL_RMS3BC160_BRANDING \
99 "Intel(R) Integrated RAID Module RMS3BC160"
102 * =====================================
103 * MegaRAID SAS MFI firmware definitions
104 * =====================================
108 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
109 * protocol between the software and firmware. Commands are issued using
114 * FW posts its state in upper 4 bits of outbound_msg_0 register
116 #define MFI_STATE_MASK 0xF0000000
117 #define MFI_STATE_UNDEFINED 0x00000000
118 #define MFI_STATE_BB_INIT 0x10000000
119 #define MFI_STATE_FW_INIT 0x40000000
120 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
121 #define MFI_STATE_FW_INIT_2 0x70000000
122 #define MFI_STATE_DEVICE_SCAN 0x80000000
123 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
124 #define MFI_STATE_FLUSH_CACHE 0xA0000000
125 #define MFI_STATE_READY 0xB0000000
126 #define MFI_STATE_OPERATIONAL 0xC0000000
127 #define MFI_STATE_FAULT 0xF0000000
128 #define MFI_STATE_FORCE_OCR 0x00000080
129 #define MFI_STATE_DMADONE 0x00000008
130 #define MFI_STATE_CRASH_DUMP_DONE 0x00000004
131 #define MFI_RESET_REQUIRED 0x00000001
132 #define MFI_RESET_ADAPTER 0x00000002
133 #define MEGAMFI_FRAME_SIZE 64
136 * During FW init, clear pending cmds & reset state using inbound_msg_0
138 * ABORT : Abort all pending cmds
139 * READY : Move from OPERATIONAL to READY state; discard queue info
140 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
141 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
142 * HOTPLUG : Resume from Hotplug
143 * MFI_STOP_ADP : Send signal to FW to stop processing
145 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
146 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
147 #define DIAG_WRITE_ENABLE (0x00000080)
148 #define DIAG_RESET_ADAPTER (0x00000004)
150 #define MFI_ADP_RESET 0x00000040
151 #define MFI_INIT_ABORT 0x00000001
152 #define MFI_INIT_READY 0x00000002
153 #define MFI_INIT_MFIMODE 0x00000004
154 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
155 #define MFI_INIT_HOTPLUG 0x00000010
156 #define MFI_STOP_ADP 0x00000020
157 #define MFI_RESET_FLAGS MFI_INIT_READY| \
160 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
165 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
166 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
167 #define MFI_FRAME_SGL32 0x0000
168 #define MFI_FRAME_SGL64 0x0002
169 #define MFI_FRAME_SENSE32 0x0000
170 #define MFI_FRAME_SENSE64 0x0004
171 #define MFI_FRAME_DIR_NONE 0x0000
172 #define MFI_FRAME_DIR_WRITE 0x0008
173 #define MFI_FRAME_DIR_READ 0x0010
174 #define MFI_FRAME_DIR_BOTH 0x0018
175 #define MFI_FRAME_IEEE 0x0020
177 /* Driver internal */
178 #define DRV_DCMD_POLLED_MODE 0x1
179 #define DRV_DCMD_SKIP_REFIRE 0x2
182 * Definition for cmd_status
184 #define MFI_CMD_STATUS_POLL_MODE 0xFF
187 * MFI command opcodes
189 #define MFI_CMD_INIT 0x00
190 #define MFI_CMD_LD_READ 0x01
191 #define MFI_CMD_LD_WRITE 0x02
192 #define MFI_CMD_LD_SCSI_IO 0x03
193 #define MFI_CMD_PD_SCSI_IO 0x04
194 #define MFI_CMD_DCMD 0x05
195 #define MFI_CMD_ABORT 0x06
196 #define MFI_CMD_SMP 0x07
197 #define MFI_CMD_STP 0x08
198 #define MFI_CMD_INVALID 0xff
200 #define MR_DCMD_CTRL_GET_INFO 0x01010000
201 #define MR_DCMD_LD_GET_LIST 0x03010000
202 #define MR_DCMD_LD_LIST_QUERY 0x03010100
204 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
205 #define MR_FLUSH_CTRL_CACHE 0x01
206 #define MR_FLUSH_DISK_CACHE 0x02
208 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
209 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
210 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
212 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
213 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
214 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
215 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
217 #define MR_DCMD_CLUSTER 0x08000000
218 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
219 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
220 #define MR_DCMD_PD_LIST_QUERY 0x02010100
222 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
223 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
224 #define MR_DCMD_PD_GET_INFO 0x02020000
229 extern u8
MR_ValidateMapInfo(struct megasas_instance
*instance
);
233 * MFI command completion codes
237 MFI_STAT_INVALID_CMD
= 0x01,
238 MFI_STAT_INVALID_DCMD
= 0x02,
239 MFI_STAT_INVALID_PARAMETER
= 0x03,
240 MFI_STAT_INVALID_SEQUENCE_NUMBER
= 0x04,
241 MFI_STAT_ABORT_NOT_POSSIBLE
= 0x05,
242 MFI_STAT_APP_HOST_CODE_NOT_FOUND
= 0x06,
243 MFI_STAT_APP_IN_USE
= 0x07,
244 MFI_STAT_APP_NOT_INITIALIZED
= 0x08,
245 MFI_STAT_ARRAY_INDEX_INVALID
= 0x09,
246 MFI_STAT_ARRAY_ROW_NOT_EMPTY
= 0x0a,
247 MFI_STAT_CONFIG_RESOURCE_CONFLICT
= 0x0b,
248 MFI_STAT_DEVICE_NOT_FOUND
= 0x0c,
249 MFI_STAT_DRIVE_TOO_SMALL
= 0x0d,
250 MFI_STAT_FLASH_ALLOC_FAIL
= 0x0e,
251 MFI_STAT_FLASH_BUSY
= 0x0f,
252 MFI_STAT_FLASH_ERROR
= 0x10,
253 MFI_STAT_FLASH_IMAGE_BAD
= 0x11,
254 MFI_STAT_FLASH_IMAGE_INCOMPLETE
= 0x12,
255 MFI_STAT_FLASH_NOT_OPEN
= 0x13,
256 MFI_STAT_FLASH_NOT_STARTED
= 0x14,
257 MFI_STAT_FLUSH_FAILED
= 0x15,
258 MFI_STAT_HOST_CODE_NOT_FOUNT
= 0x16,
259 MFI_STAT_LD_CC_IN_PROGRESS
= 0x17,
260 MFI_STAT_LD_INIT_IN_PROGRESS
= 0x18,
261 MFI_STAT_LD_LBA_OUT_OF_RANGE
= 0x19,
262 MFI_STAT_LD_MAX_CONFIGURED
= 0x1a,
263 MFI_STAT_LD_NOT_OPTIMAL
= 0x1b,
264 MFI_STAT_LD_RBLD_IN_PROGRESS
= 0x1c,
265 MFI_STAT_LD_RECON_IN_PROGRESS
= 0x1d,
266 MFI_STAT_LD_WRONG_RAID_LEVEL
= 0x1e,
267 MFI_STAT_MAX_SPARES_EXCEEDED
= 0x1f,
268 MFI_STAT_MEMORY_NOT_AVAILABLE
= 0x20,
269 MFI_STAT_MFC_HW_ERROR
= 0x21,
270 MFI_STAT_NO_HW_PRESENT
= 0x22,
271 MFI_STAT_NOT_FOUND
= 0x23,
272 MFI_STAT_NOT_IN_ENCL
= 0x24,
273 MFI_STAT_PD_CLEAR_IN_PROGRESS
= 0x25,
274 MFI_STAT_PD_TYPE_WRONG
= 0x26,
275 MFI_STAT_PR_DISABLED
= 0x27,
276 MFI_STAT_ROW_INDEX_INVALID
= 0x28,
277 MFI_STAT_SAS_CONFIG_INVALID_ACTION
= 0x29,
278 MFI_STAT_SAS_CONFIG_INVALID_DATA
= 0x2a,
279 MFI_STAT_SAS_CONFIG_INVALID_PAGE
= 0x2b,
280 MFI_STAT_SAS_CONFIG_INVALID_TYPE
= 0x2c,
281 MFI_STAT_SCSI_DONE_WITH_ERROR
= 0x2d,
282 MFI_STAT_SCSI_IO_FAILED
= 0x2e,
283 MFI_STAT_SCSI_RESERVATION_CONFLICT
= 0x2f,
284 MFI_STAT_SHUTDOWN_FAILED
= 0x30,
285 MFI_STAT_TIME_NOT_SET
= 0x31,
286 MFI_STAT_WRONG_STATE
= 0x32,
287 MFI_STAT_LD_OFFLINE
= 0x33,
288 MFI_STAT_PEER_NOTIFICATION_REJECTED
= 0x34,
289 MFI_STAT_PEER_NOTIFICATION_FAILED
= 0x35,
290 MFI_STAT_RESERVATION_IN_PROGRESS
= 0x36,
291 MFI_STAT_I2C_ERRORS_DETECTED
= 0x37,
292 MFI_STAT_PCI_ERRORS_DETECTED
= 0x38,
293 MFI_STAT_CONFIG_SEQ_MISMATCH
= 0x67,
295 MFI_STAT_INVALID_STATUS
= 0xFF
299 MFI_EVT_CLASS_DEBUG
= -2,
300 MFI_EVT_CLASS_PROGRESS
= -1,
301 MFI_EVT_CLASS_INFO
= 0,
302 MFI_EVT_CLASS_WARNING
= 1,
303 MFI_EVT_CLASS_CRITICAL
= 2,
304 MFI_EVT_CLASS_FATAL
= 3,
305 MFI_EVT_CLASS_DEAD
= 4
309 * Crash dump related defines
311 #define MAX_CRASH_DUMP_SIZE 512
312 #define CRASH_DMA_BUF_SIZE (1024 * 1024)
314 enum MR_FW_CRASH_DUMP_STATE
{
322 enum _MR_CRASH_BUF_STATUS
{
323 MR_CRASH_BUF_TURN_OFF
= 0,
324 MR_CRASH_BUF_TURN_ON
= 1,
328 * Number of mailbox bytes in DCMD message frame
330 #define MFI_MBOX_SIZE 12
334 MR_EVT_CLASS_DEBUG
= -2,
335 MR_EVT_CLASS_PROGRESS
= -1,
336 MR_EVT_CLASS_INFO
= 0,
337 MR_EVT_CLASS_WARNING
= 1,
338 MR_EVT_CLASS_CRITICAL
= 2,
339 MR_EVT_CLASS_FATAL
= 3,
340 MR_EVT_CLASS_DEAD
= 4,
346 MR_EVT_LOCALE_LD
= 0x0001,
347 MR_EVT_LOCALE_PD
= 0x0002,
348 MR_EVT_LOCALE_ENCL
= 0x0004,
349 MR_EVT_LOCALE_BBU
= 0x0008,
350 MR_EVT_LOCALE_SAS
= 0x0010,
351 MR_EVT_LOCALE_CTRL
= 0x0020,
352 MR_EVT_LOCALE_CONFIG
= 0x0040,
353 MR_EVT_LOCALE_CLUSTER
= 0x0080,
354 MR_EVT_LOCALE_ALL
= 0xffff,
361 MR_EVT_ARGS_CDB_SENSE
,
363 MR_EVT_ARGS_LD_COUNT
,
365 MR_EVT_ARGS_LD_OWNER
,
366 MR_EVT_ARGS_LD_LBA_PD_LBA
,
368 MR_EVT_ARGS_LD_STATE
,
369 MR_EVT_ARGS_LD_STRIP
,
373 MR_EVT_ARGS_PD_LBA_LD
,
375 MR_EVT_ARGS_PD_STATE
,
382 MR_EVT_ARGS_PD_SPARE
,
383 MR_EVT_ARGS_PD_INDEX
,
384 MR_EVT_ARGS_DIAG_PASS
,
385 MR_EVT_ARGS_DIAG_FAIL
,
386 MR_EVT_ARGS_PD_LBA_LBA
,
387 MR_EVT_ARGS_PORT_PHY
,
388 MR_EVT_ARGS_PD_MISSING
,
389 MR_EVT_ARGS_PD_ADDRESS
,
391 MR_EVT_ARGS_CONNECTOR
,
394 MR_EVT_ARGS_PD_PATHINFO
,
395 MR_EVT_ARGS_PD_POWER_STATE
,
400 #define SGE_BUFFER_SIZE 4096
401 #define MEGASAS_CLUSTER_ID_SIZE 16
403 * define constants for device list query options
405 enum MR_PD_QUERY_TYPE
{
406 MR_PD_QUERY_TYPE_ALL
= 0,
407 MR_PD_QUERY_TYPE_STATE
= 1,
408 MR_PD_QUERY_TYPE_POWER_STATE
= 2,
409 MR_PD_QUERY_TYPE_MEDIA_TYPE
= 3,
410 MR_PD_QUERY_TYPE_SPEED
= 4,
411 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST
= 5,
414 enum MR_LD_QUERY_TYPE
{
415 MR_LD_QUERY_TYPE_ALL
= 0,
416 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST
= 1,
417 MR_LD_QUERY_TYPE_USED_TGT_IDS
= 2,
418 MR_LD_QUERY_TYPE_CLUSTER_ACCESS
= 3,
419 MR_LD_QUERY_TYPE_CLUSTER_LOCALE
= 4,
423 #define MR_EVT_CFG_CLEARED 0x0004
424 #define MR_EVT_LD_STATE_CHANGE 0x0051
425 #define MR_EVT_PD_INSERTED 0x005b
426 #define MR_EVT_PD_REMOVED 0x0070
427 #define MR_EVT_LD_CREATED 0x008a
428 #define MR_EVT_LD_DELETED 0x008b
429 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
430 #define MR_EVT_LD_OFFLINE 0x00fc
431 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
432 #define MR_EVT_CTRL_PROP_CHANGED 0x012f
435 MR_PD_STATE_UNCONFIGURED_GOOD
= 0x00,
436 MR_PD_STATE_UNCONFIGURED_BAD
= 0x01,
437 MR_PD_STATE_HOT_SPARE
= 0x02,
438 MR_PD_STATE_OFFLINE
= 0x10,
439 MR_PD_STATE_FAILED
= 0x11,
440 MR_PD_STATE_REBUILD
= 0x14,
441 MR_PD_STATE_ONLINE
= 0x18,
442 MR_PD_STATE_COPYBACK
= 0x20,
443 MR_PD_STATE_SYSTEM
= 0x40,
455 * define the DDF Type bit structure
457 union MR_PD_DDF_TYPE
{
461 #ifndef __BIG_ENDIAN_BITFIELD
490 * defines the progress structure
497 u16 elapsedSecsForLastPercent
;
504 * defines the physical drive progress structure
506 struct MR_PD_PROGRESS
{
508 #ifndef MFI_BIG_ENDIAN
526 union MR_PROGRESS rbld
;
527 union MR_PROGRESS patrol
;
529 union MR_PROGRESS clear
;
530 union MR_PROGRESS erase
;
534 #ifndef MFI_BIG_ENDIAN
551 union MR_PROGRESS reserved
[3];
562 u8 connectedPortBitmap
;
563 u8 connectedPortNumbers
;
570 u32 lastPredFailEventSeqNum
;
573 u8 disabledForRemoval
;
575 union MR_PD_DDF_TYPE state
;
579 #ifndef __BIG_ENDIAN_BITFIELD
582 u8 widePortCapable
:1;
584 u8 widePortCapable
:1;
589 u8 connectorIndex
[2];
603 u8 enclConnectorIndex
;
606 struct MR_PD_PROGRESS progInfo
;
607 u8 badBlockTableFull
;
608 u8 unusableInCurrentConfig
;
613 u16 copyBackPartnerId
;
614 u16 enclPartnerDeviceId
;
616 #ifndef __BIG_ENDIAN_BITFIELD
637 u8 bridgeProductIdentification
[16];
638 u8 bridgeProductRevisionLevel
[4];
643 u8 emulatedBlockSize
;
644 u16 userDataBlockSize
;
648 #ifndef __BIG_ENDIAN_BITFIELD
654 u32 commissionedSpare
:1;
655 u32 emergencySpare
:1;
656 u32 ineligibleForSSCD
:1;
657 u32 ineligibleForLd
:1;
658 u32 useSSEraseType
:1;
660 u32 supportScsiUnmap
:1;
664 u32 supportScsiUnmap
:1;
666 u32 useSSEraseType
:1;
667 u32 ineligibleForLd
:1;
668 u32 ineligibleForSSCD
:1;
669 u32 emergencySpare
:1;
670 u32 commissionedSpare
:1;
679 u64 shieldDiagCompletionTime
;
686 #ifndef __BIG_ENDIAN_BITFIELD
687 u32 bbmErrCountSupported
:1;
691 u32 bbmErrCountSupported
:1;
695 u8 reserved1
[512-428];
699 * Definition of structure used to expose attributes of VD or JBOD
700 * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP
701 * is fired by driver)
703 struct MR_TARGET_PROPERTIES
{
711 * defines the physical drive address structure
713 struct MR_PD_ADDRESS
{
724 u8 enclConnectorIndex
;
729 u8 connectedPortBitmap
;
730 u8 connectedPortNumbers
;
736 * defines the physical drive list structure
741 struct MR_PD_ADDRESS addr
[1];
744 struct megasas_pd_list
{
751 * defines the logical drive reference structure
763 * defines the logical drive list structure
773 } ldList
[MAX_LOGICAL_DRIVES_EXT
];
776 struct MR_LD_TARGETID_LIST
{
780 u8 targetId
[MAX_LOGICAL_DRIVES_EXT
];
785 * SAS controller properties
787 struct megasas_ctrl_prop
{
790 u16 pred_fail_poll_interval
;
791 u16 intr_throttle_count
;
792 u16 intr_throttle_timeouts
;
798 u8 cache_flush_interval
;
804 u8 disable_auto_rebuild
;
805 u8 disable_battery_warn
;
807 u16 ecc_bucket_leak_rate
;
808 u8 restore_hotspare_on_insertion
;
809 u8 expose_encl_devices
;
810 u8 maintainPdFailHistory
;
811 u8 disallowHostRequestReordering
;
814 u8 disableAutoDetectBackplane
;
819 * Add properties that can be controlled by
820 * a bit in the following structure.
823 #if defined(__BIG_ENDIAN_BITFIELD)
826 u32 disableSpinDownHS
:1;
827 u32 allowBootWithPinnedCache
:1;
828 u32 disableOnlineCtrlReset
:1;
829 u32 enableSecretKeyControl
:1;
830 u32 autoEnhancedImport
:1;
831 u32 enableSpinDownUnconfigured
:1;
832 u32 SSDPatrolReadEnabled
:1;
833 u32 SSDSMARTerEnabled
:1;
836 u32 prCorrectUnconfiguredAreas
:1;
837 u32 SMARTerEnabled
:1;
838 u32 copyBackDisabled
:1;
840 u32 copyBackDisabled
:1;
841 u32 SMARTerEnabled
:1;
842 u32 prCorrectUnconfiguredAreas
:1;
845 u32 SSDSMARTerEnabled
:1;
846 u32 SSDPatrolReadEnabled
:1;
847 u32 enableSpinDownUnconfigured
:1;
848 u32 autoEnhancedImport
:1;
849 u32 enableSecretKeyControl
:1;
850 u32 disableOnlineCtrlReset
:1;
851 u32 allowBootWithPinnedCache
:1;
852 u32 disableSpinDownHS
:1;
864 * SAS controller information
866 struct megasas_ctrl_info
{
869 * PCI device information
875 __le16 sub_vendor_id
;
876 __le16 sub_device_id
;
879 } __attribute__ ((packed
)) pci
;
882 * Host interface information
896 } __attribute__ ((packed
)) host_interface
;
899 * Device (backend) interface information
912 } __attribute__ ((packed
)) device_interface
;
915 * List of components residing in flash. All str are null terminated
917 __le32 image_check_word
;
918 __le32 image_component_count
;
927 } __attribute__ ((packed
)) image_component
[8];
930 * List of flash components that have been flashed on the card, but
931 * are not in use, pending reset of the adapter. This list will be
932 * empty if a flash operation has not occurred. All stings are null
935 __le32 pending_image_component_count
;
944 } __attribute__ ((packed
)) pending_image_component
[8];
951 char product_name
[80];
955 * Other physical/controller/operation information. Indicates the
956 * presence of the hardware
966 } __attribute__ ((packed
)) hw_present
;
968 __le32 current_fw_time
;
971 * Maximum data transfer sizes
973 __le16 max_concurrent_cmds
;
974 __le16 max_sge_count
;
975 __le32 max_request_size
;
978 * Logical and physical device counts
980 __le16 ld_present_count
;
981 __le16 ld_degraded_count
;
982 __le16 ld_offline_count
;
984 __le16 pd_present_count
;
985 __le16 pd_disk_present_count
;
986 __le16 pd_disk_pred_failure_count
;
987 __le16 pd_disk_failed_count
;
990 * Memory size information
999 __le16 mem_correctable_error_count
;
1000 __le16 mem_uncorrectable_error_count
;
1003 * Cluster information
1005 u8 cluster_permitted
;
1009 * Additional max data transfer sizes
1011 __le16 max_strips_per_io
;
1014 * Controller capabilities structures
1021 u32 raid_level_1E
:1;
1025 } __attribute__ ((packed
)) raid_levels
;
1034 u32 alarm_control
:1;
1035 u32 cluster_supported
:1;
1037 u32 spanning_allowed
:1;
1038 u32 dedicated_hotspares
:1;
1039 u32 revertible_hotspares
:1;
1040 u32 foreign_config_import
:1;
1041 u32 self_diagnostic
:1;
1042 u32 mixed_redundancy_arr
:1;
1043 u32 global_hot_spares
:1;
1046 } __attribute__ ((packed
)) adapter_operations
;
1053 u32 access_policy
:1;
1054 u32 disk_cache_policy
:1;
1057 } __attribute__ ((packed
)) ld_operations
;
1065 } __attribute__ ((packed
)) stripe_sz_ops
;
1070 u32 force_offline
:1;
1071 u32 force_rebuild
:1;
1074 } __attribute__ ((packed
)) pd_operations
;
1078 u32 ctrl_supports_sas
:1;
1079 u32 ctrl_supports_sata
:1;
1080 u32 allow_mix_in_encl
:1;
1081 u32 allow_mix_in_ld
:1;
1082 u32 allow_sata_in_cluster
:1;
1085 } __attribute__ ((packed
)) pd_mix_support
;
1088 * Define ECC single-bit-error bucket information
1090 u8 ecc_bucket_count
;
1094 * Include the controller properties (changeable items)
1096 struct megasas_ctrl_prop properties
;
1099 * Define FW pkg version (set in envt v'bles on OEM basis)
1101 char package_version
[0x60];
1105 * If adapterOperations.supportMoreThan8Phys is set,
1106 * and deviceInterface.portCount is greater than 8,
1107 * SAS Addrs for first 8 ports shall be populated in
1108 * deviceInterface.portAddr, and the rest shall be
1109 * populated in deviceInterfacePortAddr2.
1111 __le64 deviceInterfacePortAddr2
[8]; /*6a0h */
1112 u8 reserved3
[128]; /*6e0h */
1115 u16 minPdRaidLevel_0
:4;
1116 u16 maxPdRaidLevel_0
:12;
1118 u16 minPdRaidLevel_1
:4;
1119 u16 maxPdRaidLevel_1
:12;
1121 u16 minPdRaidLevel_5
:4;
1122 u16 maxPdRaidLevel_5
:12;
1124 u16 minPdRaidLevel_1E
:4;
1125 u16 maxPdRaidLevel_1E
:12;
1127 u16 minPdRaidLevel_6
:4;
1128 u16 maxPdRaidLevel_6
:12;
1130 u16 minPdRaidLevel_10
:4;
1131 u16 maxPdRaidLevel_10
:12;
1133 u16 minPdRaidLevel_50
:4;
1134 u16 maxPdRaidLevel_50
:12;
1136 u16 minPdRaidLevel_60
:4;
1137 u16 maxPdRaidLevel_60
:12;
1139 u16 minPdRaidLevel_1E_RLQ0
:4;
1140 u16 maxPdRaidLevel_1E_RLQ0
:12;
1142 u16 minPdRaidLevel_1E0_RLQ0
:4;
1143 u16 maxPdRaidLevel_1E0_RLQ0
:12;
1148 __le16 maxPds
; /*780h */
1149 __le16 maxDedHSPs
; /*782h */
1150 __le16 maxGlobalHSP
; /*784h */
1151 __le16 ddfSize
; /*786h */
1152 u8 maxLdsPerArray
; /*788h */
1153 u8 partitionsInDDF
; /*789h */
1154 u8 lockKeyBinding
; /*78ah */
1155 u8 maxPITsPerLd
; /*78bh */
1156 u8 maxViewsPerLd
; /*78ch */
1157 u8 maxTargetId
; /*78dh */
1158 __le16 maxBvlVdSize
; /*78eh */
1160 __le16 maxConfigurableSSCSize
; /*790h */
1161 __le16 currentSSCsize
; /*792h */
1163 char expanderFwVersion
[12]; /*794h */
1165 __le16 PFKTrialTimeRemaining
; /*7A0h */
1167 __le16 cacheMemorySize
; /*7A2h */
1170 #if defined(__BIG_ENDIAN_BITFIELD)
1172 u32 activePassive
:2;
1173 u32 supportConfigAutoBalance
:1;
1175 u32 supportDataLDonSSCArray
:1;
1176 u32 supportPointInTimeProgress
:1;
1177 u32 supportUnevenSpans
:1;
1178 u32 dedicatedHotSparesLimited
:1;
1180 u32 supportEmulatedDrives
:1;
1181 u32 supportResetNow
:1;
1182 u32 realTimeScheduler
:1;
1183 u32 supportSSDPatrolRead
:1;
1184 u32 supportPerfTuning
:1;
1185 u32 disableOnlinePFKChange
:1;
1187 u32 supportBootTimePFKChange
:1;
1188 u32 supportSetLinkSpeed
:1;
1189 u32 supportEmergencySpares
:1;
1190 u32 supportSuspendResumeBGops
:1;
1191 u32 blockSSDWriteCacheChange
:1;
1192 u32 supportShieldState
:1;
1193 u32 supportLdBBMInfo
:1;
1194 u32 supportLdPIType3
:1;
1195 u32 supportLdPIType2
:1;
1196 u32 supportLdPIType1
:1;
1197 u32 supportPIcontroller
:1;
1199 u32 supportPIcontroller
:1;
1200 u32 supportLdPIType1
:1;
1201 u32 supportLdPIType2
:1;
1202 u32 supportLdPIType3
:1;
1203 u32 supportLdBBMInfo
:1;
1204 u32 supportShieldState
:1;
1205 u32 blockSSDWriteCacheChange
:1;
1206 u32 supportSuspendResumeBGops
:1;
1207 u32 supportEmergencySpares
:1;
1208 u32 supportSetLinkSpeed
:1;
1209 u32 supportBootTimePFKChange
:1;
1211 u32 disableOnlinePFKChange
:1;
1212 u32 supportPerfTuning
:1;
1213 u32 supportSSDPatrolRead
:1;
1214 u32 realTimeScheduler
:1;
1216 u32 supportResetNow
:1;
1217 u32 supportEmulatedDrives
:1;
1219 u32 dedicatedHotSparesLimited
:1;
1222 u32 supportUnevenSpans
:1;
1223 u32 supportPointInTimeProgress
:1;
1224 u32 supportDataLDonSSCArray
:1;
1226 u32 supportConfigAutoBalance
:1;
1227 u32 activePassive
:2;
1230 } adapterOperations2
;
1232 u8 driverVersion
[32]; /*7A8h */
1233 u8 maxDAPdCountSpinup60
; /*7C8h */
1234 u8 temperatureROC
; /*7C9h */
1235 u8 temperatureCtrl
; /*7CAh */
1236 u8 reserved4
; /*7CBh */
1237 __le16 maxConfigurablePds
; /*7CCh */
1240 u8 reserved5
[2]; /*0x7CDh */
1243 * HA cluster information
1246 #if defined(__BIG_ENDIAN_BITFIELD)
1249 u32 premiumFeatureMismatch
:1;
1250 u32 ctrlPropIncompatible
:1;
1251 u32 fwVersionMismatch
:1;
1252 u32 hwIncompatible
:1;
1253 u32 peerIsIncompatible
:1;
1254 u32 peerIsPresent
:1;
1256 u32 peerIsPresent
:1;
1257 u32 peerIsIncompatible
:1;
1258 u32 hwIncompatible
:1;
1259 u32 fwVersionMismatch
:1;
1260 u32 ctrlPropIncompatible
:1;
1261 u32 premiumFeatureMismatch
:1;
1267 char clusterId
[MEGASAS_CLUSTER_ID_SIZE
]; /*0x7D4 */
1269 u8 maxVFsSupported
; /*0x7E4*/
1270 u8 numVFsEnabled
; /*0x7E5*/
1271 u8 requestorId
; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
1272 u8 reserved
; /*0x7E7*/
1276 #if defined(__BIG_ENDIAN_BITFIELD)
1278 u32 useSeqNumJbodFP
:1;
1279 u32 supportExtendedSSCSize
:1;
1280 u32 supportDiskCacheSettingForSysPDs
:1;
1281 u32 supportCPLDUpdate
:1;
1282 u32 supportTTYLogCompression
:1;
1283 u32 discardCacheDuringLDDelete
:1;
1284 u32 supportSecurityonJBOD
:1;
1285 u32 supportCacheBypassModes
:1;
1286 u32 supportDisableSESMonitoring
:1;
1287 u32 supportForceFlash
:1;
1288 u32 supportNVDRAM
:1;
1289 u32 supportDrvActivityLEDSetting
:1;
1290 u32 supportAllowedOpsforDrvRemoval
:1;
1291 u32 supportHOQRebuild
:1;
1292 u32 supportForceTo512e
:1;
1293 u32 supportNVCacheErase
:1;
1294 u32 supportDebugQueue
:1;
1295 u32 supportSwZone
:1;
1296 u32 supportCrashDump
:1;
1297 u32 supportMaxExtLDs
:1;
1298 u32 supportT10RebuildAssist
:1;
1299 u32 supportDisableImmediateIO
:1;
1300 u32 supportThermalPollInterval
:1;
1301 u32 supportPersonalityChange
:2;
1303 u32 supportPersonalityChange
:2;
1304 u32 supportThermalPollInterval
:1;
1305 u32 supportDisableImmediateIO
:1;
1306 u32 supportT10RebuildAssist
:1;
1307 u32 supportMaxExtLDs
:1;
1308 u32 supportCrashDump
:1;
1309 u32 supportSwZone
:1;
1310 u32 supportDebugQueue
:1;
1311 u32 supportNVCacheErase
:1;
1312 u32 supportForceTo512e
:1;
1313 u32 supportHOQRebuild
:1;
1314 u32 supportAllowedOpsforDrvRemoval
:1;
1315 u32 supportDrvActivityLEDSetting
:1;
1316 u32 supportNVDRAM
:1;
1317 u32 supportForceFlash
:1;
1318 u32 supportDisableSESMonitoring
:1;
1319 u32 supportCacheBypassModes
:1;
1320 u32 supportSecurityonJBOD
:1;
1321 u32 discardCacheDuringLDDelete
:1;
1322 u32 supportTTYLogCompression
:1;
1323 u32 supportCPLDUpdate
:1;
1324 u32 supportDiskCacheSettingForSysPDs
:1;
1325 u32 supportExtendedSSCSize
:1;
1326 u32 useSeqNumJbodFP
:1;
1329 } adapterOperations3
;
1332 #if defined(__BIG_ENDIAN_BITFIELD)
1334 /* Indicates whether the CPLD image is part of
1335 * the package and stored in flash
1343 /* Null terminated string. Has the version
1344 * information if cpld_in_flash = FALSE
1346 u8 userCodeDefinition
[12];
1347 } cpld
; /* Valid only if upgradableCPLD is TRUE */
1350 #if defined(__BIG_ENDIAN_BITFIELD)
1352 u16 fw_swaps_bbu_vpd_info
:1;
1353 u16 support_pd_map_target_id
:1;
1354 u16 support_ses_ctrl_in_multipathcfg
:1;
1355 u16 image_upload_supported
:1;
1356 u16 support_encrypted_mfc
:1;
1357 u16 supported_enc_algo
:1;
1358 u16 support_ibutton_less
:1;
1359 u16 ctrl_info_ext_supported
:1;
1362 u16 ctrl_info_ext_supported
:1;
1363 u16 support_ibutton_less
:1;
1364 u16 supported_enc_algo
:1;
1365 u16 support_encrypted_mfc
:1;
1366 u16 image_upload_supported
:1;
1367 /* FW supports LUN based association and target port based */
1368 u16 support_ses_ctrl_in_multipathcfg
:1;
1369 /* association for the SES device connected in multipath mode */
1370 /* FW defines Jbod target Id within MR_PD_CFG_SEQ */
1371 u16 support_pd_map_target_id
:1;
1372 /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to
1373 * provide the data in little endian order
1375 u16 fw_swaps_bbu_vpd_info
:1;
1378 } adapter_operations4
;
1379 u8 pad
[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */
1383 * ===============================
1384 * MegaRAID SAS driver definitions
1385 * ===============================
1387 #define MEGASAS_MAX_PD_CHANNELS 2
1388 #define MEGASAS_MAX_LD_CHANNELS 2
1389 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
1390 MEGASAS_MAX_LD_CHANNELS)
1391 #define MEGASAS_MAX_DEV_PER_CHANNEL 128
1392 #define MEGASAS_DEFAULT_INIT_ID -1
1393 #define MEGASAS_MAX_LUN 8
1394 #define MEGASAS_DEFAULT_CMD_PER_LUN 256
1395 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
1396 MEGASAS_MAX_DEV_PER_CHANNEL)
1397 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
1398 MEGASAS_MAX_DEV_PER_CHANNEL)
1400 #define MEGASAS_MAX_SECTORS (2*1024)
1401 #define MEGASAS_MAX_SECTORS_IEEE (2*128)
1402 #define MEGASAS_DBG_LVL 1
1404 #define MEGASAS_FW_BUSY 1
1406 /* Driver's internal Logging levels*/
1407 #define OCR_LOGS (1 << 0)
1409 #define SCAN_PD_CHANNEL 0x1
1410 #define SCAN_VD_CHANNEL 0x2
1412 #define MEGASAS_KDUMP_QUEUE_DEPTH 100
1413 #define MR_LARGE_IO_MIN_SIZE (32 * 1024)
1414 #define MR_R1_LDIO_PIGGYBACK_DEFAULT 4
1416 enum MR_SCSI_CMD_TYPE
{
1417 READ_WRITE_LDIO
= 0,
1418 NON_READ_WRITE_LDIO
= 1,
1419 READ_WRITE_SYSPDIO
= 2,
1420 NON_READ_WRITE_SYSPDIO
= 3,
1423 enum DCMD_TIMEOUT_ACTION
{
1429 enum FW_BOOT_CONTEXT
{
1436 #define PTHRU_FRAME 1
1439 * When SCSI mid-layer calls driver's reset routine, driver waits for
1440 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1441 * that the driver cannot _actually_ abort or reset pending commands. While
1442 * it is waiting for the commands to complete, it prints a diagnostic message
1443 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1445 #define MEGASAS_RESET_WAIT_TIME 180
1446 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
1447 #define MEGASAS_RESET_NOTICE_INTERVAL 5
1448 #define MEGASAS_IOCTL_CMD 0
1449 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90
1450 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16
1451 #define MEGASAS_BLOCKED_CMD_TIMEOUT 60
1453 * FW reports the maximum of number of commands that it can accept (maximum
1454 * commands that can be outstanding) at any time. The driver must report a
1455 * lower number to the mid layer because it can issue a few internal commands
1456 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1459 #define MEGASAS_INT_CMDS 32
1460 #define MEGASAS_SKINNY_INT_CMDS 5
1461 #define MEGASAS_FUSION_INTERNAL_CMDS 8
1462 #define MEGASAS_FUSION_IOCTL_CMDS 3
1463 #define MEGASAS_MFI_IOCTL_CMDS 27
1465 #define MEGASAS_MAX_MSIX_QUEUES 128
1467 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1468 * SGLs based on the size of dma_addr_t
1470 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
1472 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1474 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1475 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1476 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1478 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1479 #define MFI_POLL_TIMEOUT_SECS 60
1480 #define MFI_IO_TIMEOUT_SECS 180
1481 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
1482 #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
1483 #define MEGASAS_ROUTINE_WAIT_TIME_VF 300
1484 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
1485 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1486 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
1487 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1488 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
1490 #define MFI_1068_PCSR_OFFSET 0x84
1491 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1492 #define MFI_1068_FW_READY 0xDDDD0000
1494 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1495 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1496 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
1497 #define MR_MAX_MSIX_REG_ARRAY 16
1498 #define MR_RDPQ_MODE_OFFSET 0X00800000
1500 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16
1501 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF
1502 #define MR_MIN_MAP_SIZE 0x10000
1505 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
1508 * register set for both 1068 and 1078 controllers
1509 * structure extended for 1078 registers
1512 struct megasas_register_set
{
1513 u32 doorbell
; /*0000h*/
1514 u32 fusion_seq_offset
; /*0004h*/
1515 u32 fusion_host_diag
; /*0008h*/
1516 u32 reserved_01
; /*000Ch*/
1518 u32 inbound_msg_0
; /*0010h*/
1519 u32 inbound_msg_1
; /*0014h*/
1520 u32 outbound_msg_0
; /*0018h*/
1521 u32 outbound_msg_1
; /*001Ch*/
1523 u32 inbound_doorbell
; /*0020h*/
1524 u32 inbound_intr_status
; /*0024h*/
1525 u32 inbound_intr_mask
; /*0028h*/
1527 u32 outbound_doorbell
; /*002Ch*/
1528 u32 outbound_intr_status
; /*0030h*/
1529 u32 outbound_intr_mask
; /*0034h*/
1531 u32 reserved_1
[2]; /*0038h*/
1533 u32 inbound_queue_port
; /*0040h*/
1534 u32 outbound_queue_port
; /*0044h*/
1536 u32 reserved_2
[9]; /*0048h*/
1537 u32 reply_post_host_index
; /*006Ch*/
1538 u32 reserved_2_2
[12]; /*0070h*/
1540 u32 outbound_doorbell_clear
; /*00A0h*/
1542 u32 reserved_3
[3]; /*00A4h*/
1544 u32 outbound_scratch_pad
; /*00B0h*/
1545 u32 outbound_scratch_pad_2
; /*00B4h*/
1546 u32 outbound_scratch_pad_3
; /*00B8h*/
1547 u32 outbound_scratch_pad_4
; /*00BCh*/
1550 u32 inbound_low_queue_port
; /*00C0h*/
1552 u32 inbound_high_queue_port
; /*00C4h*/
1554 u32 inbound_single_queue_port
; /*00C8h*/
1555 u32 res_6
[11]; /*CCh*/
1558 u32 index_registers
[807]; /*00CCh*/
1559 } __attribute__ ((packed
));
1561 struct megasas_sge32
{
1566 } __attribute__ ((packed
));
1568 struct megasas_sge64
{
1573 } __attribute__ ((packed
));
1575 struct megasas_sge_skinny
{
1583 struct megasas_sge32 sge32
[1];
1584 struct megasas_sge64 sge64
[1];
1585 struct megasas_sge_skinny sge_skinny
[1];
1587 } __attribute__ ((packed
));
1589 struct megasas_header
{
1592 u8 sense_len
; /*01h */
1593 u8 cmd_status
; /*02h */
1594 u8 scsi_status
; /*03h */
1596 u8 target_id
; /*04h */
1598 u8 cdb_len
; /*06h */
1599 u8 sge_count
; /*07h */
1601 __le32 context
; /*08h */
1602 __le32 pad_0
; /*0Ch */
1604 __le16 flags
; /*10h */
1605 __le16 timeout
; /*12h */
1606 __le32 data_xferlen
; /*14h */
1608 } __attribute__ ((packed
));
1610 union megasas_sgl_frame
{
1612 struct megasas_sge32 sge32
[8];
1613 struct megasas_sge64 sge64
[5];
1615 } __attribute__ ((packed
));
1617 typedef union _MFI_CAPABILITIES
{
1619 #if defined(__BIG_ENDIAN_BITFIELD)
1621 u32 support_pd_map_target_id
:1;
1622 u32 support_qd_throttling
:1;
1623 u32 support_fp_rlbypass
:1;
1624 u32 support_vfid_in_ioframe
:1;
1625 u32 support_ext_io_size
:1;
1626 u32 support_ext_queue_depth
:1;
1627 u32 security_protocol_cmds_fw
:1;
1628 u32 support_core_affinity
:1;
1629 u32 support_ndrive_r1_lb
:1;
1630 u32 support_max_255lds
:1;
1631 u32 support_fastpath_wb
:1;
1632 u32 support_additional_msix
:1;
1633 u32 support_fp_remote_lun
:1;
1635 u32 support_fp_remote_lun
:1;
1636 u32 support_additional_msix
:1;
1637 u32 support_fastpath_wb
:1;
1638 u32 support_max_255lds
:1;
1639 u32 support_ndrive_r1_lb
:1;
1640 u32 support_core_affinity
:1;
1641 u32 security_protocol_cmds_fw
:1;
1642 u32 support_ext_queue_depth
:1;
1643 u32 support_ext_io_size
:1;
1644 u32 support_vfid_in_ioframe
:1;
1645 u32 support_fp_rlbypass
:1;
1646 u32 support_qd_throttling
:1;
1647 u32 support_pd_map_target_id
:1;
1654 struct megasas_init_frame
{
1657 u8 reserved_0
; /*01h */
1658 u8 cmd_status
; /*02h */
1660 u8 reserved_1
; /*03h */
1661 MFI_CAPABILITIES driver_operations
; /*04h*/
1663 __le32 context
; /*08h */
1664 __le32 pad_0
; /*0Ch */
1666 __le16 flags
; /*10h */
1667 __le16 reserved_3
; /*12h */
1668 __le32 data_xfer_len
; /*14h */
1670 __le32 queue_info_new_phys_addr_lo
; /*18h */
1671 __le32 queue_info_new_phys_addr_hi
; /*1Ch */
1672 __le32 queue_info_old_phys_addr_lo
; /*20h */
1673 __le32 queue_info_old_phys_addr_hi
; /*24h */
1674 __le32 reserved_4
[2]; /*28h */
1675 __le32 system_info_lo
; /*30h */
1676 __le32 system_info_hi
; /*34h */
1677 __le32 reserved_5
[2]; /*38h */
1679 } __attribute__ ((packed
));
1681 struct megasas_init_queue_info
{
1683 __le32 init_flags
; /*00h */
1684 __le32 reply_queue_entries
; /*04h */
1686 __le32 reply_queue_start_phys_addr_lo
; /*08h */
1687 __le32 reply_queue_start_phys_addr_hi
; /*0Ch */
1688 __le32 producer_index_phys_addr_lo
; /*10h */
1689 __le32 producer_index_phys_addr_hi
; /*14h */
1690 __le32 consumer_index_phys_addr_lo
; /*18h */
1691 __le32 consumer_index_phys_addr_hi
; /*1Ch */
1693 } __attribute__ ((packed
));
1695 struct megasas_io_frame
{
1698 u8 sense_len
; /*01h */
1699 u8 cmd_status
; /*02h */
1700 u8 scsi_status
; /*03h */
1702 u8 target_id
; /*04h */
1703 u8 access_byte
; /*05h */
1704 u8 reserved_0
; /*06h */
1705 u8 sge_count
; /*07h */
1707 __le32 context
; /*08h */
1708 __le32 pad_0
; /*0Ch */
1710 __le16 flags
; /*10h */
1711 __le16 timeout
; /*12h */
1712 __le32 lba_count
; /*14h */
1714 __le32 sense_buf_phys_addr_lo
; /*18h */
1715 __le32 sense_buf_phys_addr_hi
; /*1Ch */
1717 __le32 start_lba_lo
; /*20h */
1718 __le32 start_lba_hi
; /*24h */
1720 union megasas_sgl sgl
; /*28h */
1722 } __attribute__ ((packed
));
1724 struct megasas_pthru_frame
{
1727 u8 sense_len
; /*01h */
1728 u8 cmd_status
; /*02h */
1729 u8 scsi_status
; /*03h */
1731 u8 target_id
; /*04h */
1733 u8 cdb_len
; /*06h */
1734 u8 sge_count
; /*07h */
1736 __le32 context
; /*08h */
1737 __le32 pad_0
; /*0Ch */
1739 __le16 flags
; /*10h */
1740 __le16 timeout
; /*12h */
1741 __le32 data_xfer_len
; /*14h */
1743 __le32 sense_buf_phys_addr_lo
; /*18h */
1744 __le32 sense_buf_phys_addr_hi
; /*1Ch */
1746 u8 cdb
[16]; /*20h */
1747 union megasas_sgl sgl
; /*30h */
1749 } __attribute__ ((packed
));
1751 struct megasas_dcmd_frame
{
1754 u8 reserved_0
; /*01h */
1755 u8 cmd_status
; /*02h */
1756 u8 reserved_1
[4]; /*03h */
1757 u8 sge_count
; /*07h */
1759 __le32 context
; /*08h */
1760 __le32 pad_0
; /*0Ch */
1762 __le16 flags
; /*10h */
1763 __le16 timeout
; /*12h */
1765 __le32 data_xfer_len
; /*14h */
1766 __le32 opcode
; /*18h */
1774 union megasas_sgl sgl
; /*28h */
1776 } __attribute__ ((packed
));
1778 struct megasas_abort_frame
{
1781 u8 reserved_0
; /*01h */
1782 u8 cmd_status
; /*02h */
1784 u8 reserved_1
; /*03h */
1785 __le32 reserved_2
; /*04h */
1787 __le32 context
; /*08h */
1788 __le32 pad_0
; /*0Ch */
1790 __le16 flags
; /*10h */
1791 __le16 reserved_3
; /*12h */
1792 __le32 reserved_4
; /*14h */
1794 __le32 abort_context
; /*18h */
1795 __le32 pad_1
; /*1Ch */
1797 __le32 abort_mfi_phys_addr_lo
; /*20h */
1798 __le32 abort_mfi_phys_addr_hi
; /*24h */
1800 __le32 reserved_5
[6]; /*28h */
1802 } __attribute__ ((packed
));
1804 struct megasas_smp_frame
{
1807 u8 reserved_1
; /*01h */
1808 u8 cmd_status
; /*02h */
1809 u8 connection_status
; /*03h */
1811 u8 reserved_2
[3]; /*04h */
1812 u8 sge_count
; /*07h */
1814 __le32 context
; /*08h */
1815 __le32 pad_0
; /*0Ch */
1817 __le16 flags
; /*10h */
1818 __le16 timeout
; /*12h */
1820 __le32 data_xfer_len
; /*14h */
1821 __le64 sas_addr
; /*18h */
1824 struct megasas_sge32 sge32
[2]; /* [0]: resp [1]: req */
1825 struct megasas_sge64 sge64
[2]; /* [0]: resp [1]: req */
1828 } __attribute__ ((packed
));
1830 struct megasas_stp_frame
{
1833 u8 reserved_1
; /*01h */
1834 u8 cmd_status
; /*02h */
1835 u8 reserved_2
; /*03h */
1837 u8 target_id
; /*04h */
1838 u8 reserved_3
[2]; /*05h */
1839 u8 sge_count
; /*07h */
1841 __le32 context
; /*08h */
1842 __le32 pad_0
; /*0Ch */
1844 __le16 flags
; /*10h */
1845 __le16 timeout
; /*12h */
1847 __le32 data_xfer_len
; /*14h */
1849 __le16 fis
[10]; /*18h */
1853 struct megasas_sge32 sge32
[2]; /* [0]: resp [1]: data */
1854 struct megasas_sge64 sge64
[2]; /* [0]: resp [1]: data */
1857 } __attribute__ ((packed
));
1859 union megasas_frame
{
1861 struct megasas_header hdr
;
1862 struct megasas_init_frame init
;
1863 struct megasas_io_frame io
;
1864 struct megasas_pthru_frame pthru
;
1865 struct megasas_dcmd_frame dcmd
;
1866 struct megasas_abort_frame abort
;
1867 struct megasas_smp_frame smp
;
1868 struct megasas_stp_frame stp
;
1874 * struct MR_PRIV_DEVICE - sdev private hostdata
1875 * @is_tm_capable: firmware managed tm_capable flag
1876 * @tm_busy: TM request is in progress
1878 struct MR_PRIV_DEVICE
{
1881 atomic_t r1_ldio_hint
;
1886 union megasas_evt_class_locale
{
1889 #ifndef __BIG_ENDIAN_BITFIELD
1898 } __attribute__ ((packed
)) members
;
1902 } __attribute__ ((packed
));
1904 struct megasas_evt_log_info
{
1905 __le32 newest_seq_num
;
1906 __le32 oldest_seq_num
;
1907 __le32 clear_seq_num
;
1908 __le32 shutdown_seq_num
;
1909 __le32 boot_seq_num
;
1911 } __attribute__ ((packed
));
1913 struct megasas_progress
{
1916 __le16 elapsed_seconds
;
1918 } __attribute__ ((packed
));
1920 struct megasas_evtarg_ld
{
1926 } __attribute__ ((packed
));
1928 struct megasas_evtarg_pd
{
1933 } __attribute__ ((packed
));
1935 struct megasas_evt_detail
{
1940 union megasas_evt_class_locale cl
;
1946 struct megasas_evtarg_pd pd
;
1952 } __attribute__ ((packed
)) cdbSense
;
1954 struct megasas_evtarg_ld ld
;
1957 struct megasas_evtarg_ld ld
;
1959 } __attribute__ ((packed
)) ld_count
;
1963 struct megasas_evtarg_ld ld
;
1964 } __attribute__ ((packed
)) ld_lba
;
1967 struct megasas_evtarg_ld ld
;
1970 } __attribute__ ((packed
)) ld_owner
;
1975 struct megasas_evtarg_ld ld
;
1976 struct megasas_evtarg_pd pd
;
1977 } __attribute__ ((packed
)) ld_lba_pd_lba
;
1980 struct megasas_evtarg_ld ld
;
1981 struct megasas_progress prog
;
1982 } __attribute__ ((packed
)) ld_prog
;
1985 struct megasas_evtarg_ld ld
;
1988 } __attribute__ ((packed
)) ld_state
;
1992 struct megasas_evtarg_ld ld
;
1993 } __attribute__ ((packed
)) ld_strip
;
1995 struct megasas_evtarg_pd pd
;
1998 struct megasas_evtarg_pd pd
;
2000 } __attribute__ ((packed
)) pd_err
;
2004 struct megasas_evtarg_pd pd
;
2005 } __attribute__ ((packed
)) pd_lba
;
2009 struct megasas_evtarg_pd pd
;
2010 struct megasas_evtarg_ld ld
;
2011 } __attribute__ ((packed
)) pd_lba_ld
;
2014 struct megasas_evtarg_pd pd
;
2015 struct megasas_progress prog
;
2016 } __attribute__ ((packed
)) pd_prog
;
2019 struct megasas_evtarg_pd pd
;
2022 } __attribute__ ((packed
)) pd_state
;
2029 } __attribute__ ((packed
)) pci
;
2037 } __attribute__ ((packed
)) time
;
2043 } __attribute__ ((packed
)) ecc
;
2051 char description
[128];
2053 } __attribute__ ((packed
));
2055 struct megasas_aen_event
{
2056 struct delayed_work hotplug_work
;
2057 struct megasas_instance
*instance
;
2060 struct megasas_irq_context
{
2061 struct megasas_instance
*instance
;
2065 struct MR_DRV_SYSTEM_INFO
{
2082 /* JBOD Queue depth definitions */
2083 #define MEGASAS_SATA_QD 32
2084 #define MEGASAS_SAS_QD 64
2085 #define MEGASAS_DEFAULT_PD_QD 64
2086 #define MEGASAS_NVME_QD 32
2088 #define MR_DEFAULT_NVME_PAGE_SIZE 4096
2089 #define MR_DEFAULT_NVME_PAGE_SHIFT 12
2090 #define MR_DEFAULT_NVME_MDTS_KB 128
2091 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF
2093 struct megasas_instance
{
2096 dma_addr_t producer_h
;
2098 dma_addr_t consumer_h
;
2099 struct MR_DRV_SYSTEM_INFO
*system_info_buf
;
2100 dma_addr_t system_info_h
;
2101 struct MR_LD_VF_AFFILIATION
*vf_affiliation
;
2102 dma_addr_t vf_affiliation_h
;
2103 struct MR_LD_VF_AFFILIATION_111
*vf_affiliation_111
;
2104 dma_addr_t vf_affiliation_111_h
;
2105 struct MR_CTRL_HB_HOST_MEM
*hb_host_mem
;
2106 dma_addr_t hb_host_mem_h
;
2107 struct MR_PD_INFO
*pd_info
;
2108 dma_addr_t pd_info_h
;
2109 struct MR_TARGET_PROPERTIES
*tgt_prop
;
2110 dma_addr_t tgt_prop_h
;
2112 __le32
*reply_queue
;
2113 dma_addr_t reply_queue_h
;
2115 u32
*crash_dump_buf
;
2116 dma_addr_t crash_dump_h
;
2117 void *crash_buf
[MAX_CRASH_DUMP_SIZE
];
2118 unsigned int fw_crash_buffer_size
;
2119 unsigned int fw_crash_state
;
2120 unsigned int fw_crash_buffer_offset
;
2123 u32 crash_dump_fw_support
;
2124 u32 crash_dump_drv_support
;
2125 u32 crash_dump_app_support
;
2126 u32 secure_jbod_support
;
2127 u32 support_morethan256jbod
; /* FW support for more than 256 PD/JBOD */
2128 bool use_seqnum_jbod_fp
; /* Added for PD sequence */
2129 spinlock_t crashdump_lock
;
2131 struct megasas_register_set __iomem
*reg_set
;
2132 u32 __iomem
*reply_post_host_index_addr
[MR_MAX_MSIX_REG_ARRAY
];
2133 struct megasas_pd_list pd_list
[MEGASAS_MAX_PD
];
2134 struct megasas_pd_list local_pd_list
[MEGASAS_MAX_PD
];
2135 u8 ld_ids
[MEGASAS_MAX_LD_IDS
];
2145 u32 max_sectors_per_req
;
2146 struct megasas_aen_event
*ev
;
2148 struct megasas_cmd
**cmd_list
;
2149 struct list_head cmd_pool
;
2150 /* used to sync fire the cmd to fw */
2151 spinlock_t mfi_pool_lock
;
2152 /* used to sync fire the cmd to fw */
2153 spinlock_t hba_lock
;
2154 /* used to synch producer, consumer ptrs in dpc */
2155 spinlock_t stream_lock
;
2156 spinlock_t completion_lock
;
2157 struct dma_pool
*frame_dma_pool
;
2158 struct dma_pool
*sense_dma_pool
;
2160 struct megasas_evt_detail
*evt_detail
;
2161 dma_addr_t evt_detail_h
;
2162 struct megasas_cmd
*aen_cmd
;
2163 struct mutex hba_mutex
;
2164 struct semaphore ioctl_sem
;
2166 struct Scsi_Host
*host
;
2168 wait_queue_head_t int_cmd_wait_q
;
2169 wait_queue_head_t abort_cmd_wait_q
;
2171 struct pci_dev
*pdev
;
2173 u32 fw_support_ieee
;
2175 atomic_t fw_outstanding
;
2176 atomic_t ldio_outstanding
;
2177 atomic_t fw_reset_no_pci_access
;
2180 atomic_t sge_holes_type1
;
2181 atomic_t sge_holes_type2
;
2182 atomic_t sge_holes_type3
;
2184 struct megasas_instance_template
*instancet
;
2185 struct tasklet_struct isr_tasklet
;
2186 struct work_struct work_init
;
2187 struct work_struct crash_init
;
2193 u8 disableOnlineCtrlReset
;
2194 u8 UnevenSpanSupport
;
2197 u8 pd_list_not_supported
;
2198 u16 fw_supported_vd_count
;
2199 u16 fw_supported_pd_count
;
2201 u16 drv_supported_vd_count
;
2202 u16 drv_supported_pd_count
;
2204 atomic_t adprecovery
;
2205 unsigned long last_time
;
2209 struct list_head internal_reset_pending_q
;
2211 /* Ptr to hba specific information */
2213 u32 ctrl_context_pages
;
2214 struct megasas_ctrl_info
*ctrl_info
;
2215 unsigned int msix_vectors
;
2216 struct megasas_irq_context irq_context
[MEGASAS_MAX_MSIX_QUEUES
];
2219 struct megasas_cmd
*map_update_cmd
;
2220 struct megasas_cmd
*jbod_seq_cmd
;
2223 struct mutex reset_mutex
;
2224 struct timer_list sriov_heartbeat_timer
;
2225 char skip_heartbeat_timer_del
;
2228 char clusterId
[MEGASAS_CLUSTER_ID_SIZE
];
2231 u16 throttlequeuedepth
;
2233 u16 max_chain_frame_sz
;
2237 bool fw_sync_cache_support
;
2241 u16 max_raid_mapsize
;
2242 /* preffered count to send as LDIO irrspective of FP capable.*/
2243 u8 r1_ldio_hint_default
;
2246 struct MR_LD_VF_MAP
{
2248 union MR_LD_REF ref
;
2254 struct MR_LD_VF_AFFILIATION
{
2260 struct MR_LD_VF_MAP map
[1];
2263 /* Plasma 1.11 FW backward compatibility structures */
2264 #define IOV_111_OFFSET 0x7CE
2265 #define MAX_VIRTUAL_FUNCTIONS 8
2266 #define MR_LD_ACCESS_HIDDEN 15
2275 struct MR_LD_VF_MAP_111
{
2278 u8 policy
[MAX_VIRTUAL_FUNCTIONS
];
2281 struct MR_LD_VF_AFFILIATION_111
{
2286 struct MR_LD_VF_MAP_111 map
[MAX_LOGICAL_DRIVES
];
2289 struct MR_CTRL_HB_HOST_MEM
{
2291 u32 fwCounter
; /* Firmware heart beat counter */
2293 u32 debugmode
:1; /* 1=Firmware is in debug mode.
2294 Heart beat will not be updated. */
2298 u32 driverCounter
; /* Driver heart beat counter. 0x20 */
2299 u32 reserved_driver
[7];
2305 MEGASAS_HBA_OPERATIONAL
= 0,
2306 MEGASAS_ADPRESET_SM_INFAULT
= 1,
2307 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS
= 2,
2308 MEGASAS_ADPRESET_SM_OPERATIONAL
= 3,
2309 MEGASAS_HW_CRITICAL_ERROR
= 4,
2310 MEGASAS_ADPRESET_SM_POLLING
= 5,
2311 MEGASAS_ADPRESET_INPROG_SIGN
= 0xDEADDEAD,
2314 struct megasas_instance_template
{
2315 void (*fire_cmd
)(struct megasas_instance
*, dma_addr_t
, \
2316 u32
, struct megasas_register_set __iomem
*);
2318 void (*enable_intr
)(struct megasas_instance
*);
2319 void (*disable_intr
)(struct megasas_instance
*);
2321 int (*clear_intr
)(struct megasas_register_set __iomem
*);
2323 u32 (*read_fw_status_reg
)(struct megasas_register_set __iomem
*);
2324 int (*adp_reset
)(struct megasas_instance
*, \
2325 struct megasas_register_set __iomem
*);
2326 int (*check_reset
)(struct megasas_instance
*, \
2327 struct megasas_register_set __iomem
*);
2328 irqreturn_t (*service_isr
)(int irq
, void *devp
);
2329 void (*tasklet
)(unsigned long);
2330 u32 (*init_adapter
)(struct megasas_instance
*);
2331 u32 (*build_and_issue_cmd
) (struct megasas_instance
*,
2332 struct scsi_cmnd
*);
2333 void (*issue_dcmd
)(struct megasas_instance
*instance
,
2334 struct megasas_cmd
*cmd
);
2337 #define MEGASAS_IS_LOGICAL(sdev) \
2338 ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
2340 #define MEGASAS_DEV_INDEX(scp) \
2341 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
2344 #define MEGASAS_PD_INDEX(scp) \
2345 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \
2348 struct megasas_cmd
{
2350 union megasas_frame
*frame
;
2351 dma_addr_t frame_phys_addr
;
2353 dma_addr_t sense_phys_addr
;
2359 u8 retry_for_fw_reset
;
2362 struct list_head list
;
2363 struct scsi_cmnd
*scmd
;
2366 struct megasas_instance
*instance
;
2376 #define MAX_MGMT_ADAPTERS 1024
2377 #define MAX_IOCTL_SGE 16
2379 struct megasas_iocpacket
{
2389 struct megasas_header hdr
;
2392 struct iovec sgl
[MAX_IOCTL_SGE
];
2394 } __attribute__ ((packed
));
2396 struct megasas_aen
{
2400 u32 class_locale_word
;
2401 } __attribute__ ((packed
));
2403 #ifdef CONFIG_COMPAT
2404 struct compat_megasas_iocpacket
{
2413 struct megasas_header hdr
;
2415 struct compat_iovec sgl
[MAX_IOCTL_SGE
];
2416 } __attribute__ ((packed
));
2418 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
2421 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
2422 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
2424 struct megasas_mgmt_info
{
2427 struct megasas_instance
*instance
[MAX_MGMT_ADAPTERS
];
2431 enum MEGASAS_OCR_CAUSE
{
2433 SCSIIO_TIMEOUT_OCR
= 1,
2434 MFI_IO_TIMEOUT_OCR
= 2,
2437 enum DCMD_RETURN_STATUS
{
2445 MR_BuildRaidContext(struct megasas_instance
*instance
,
2446 struct IO_REQUEST_INFO
*io_info
,
2447 struct RAID_CONTEXT
*pRAID_Context
,
2448 struct MR_DRV_RAID_MAP_ALL
*map
, u8
**raidLUN
);
2449 u16
MR_TargetIdToLdGet(u32 ldTgtId
, struct MR_DRV_RAID_MAP_ALL
*map
);
2450 struct MR_LD_RAID
*MR_LdRaidGet(u32 ld
, struct MR_DRV_RAID_MAP_ALL
*map
);
2451 u16
MR_ArPdGet(u32 ar
, u32 arm
, struct MR_DRV_RAID_MAP_ALL
*map
);
2452 u16
MR_LdSpanArrayGet(u32 ld
, u32 span
, struct MR_DRV_RAID_MAP_ALL
*map
);
2453 __le16
MR_PdDevHandleGet(u32 pd
, struct MR_DRV_RAID_MAP_ALL
*map
);
2454 u16
MR_GetLDTgtId(u32 ld
, struct MR_DRV_RAID_MAP_ALL
*map
);
2456 __le16
get_updated_dev_handle(struct megasas_instance
*instance
,
2457 struct LD_LOAD_BALANCE_INFO
*lbInfo
,
2458 struct IO_REQUEST_INFO
*in_info
,
2459 struct MR_DRV_RAID_MAP_ALL
*drv_map
);
2460 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL
*map
,
2461 struct LD_LOAD_BALANCE_INFO
*lbInfo
);
2462 int megasas_get_ctrl_info(struct megasas_instance
*instance
);
2465 megasas_sync_pd_seq_num(struct megasas_instance
*instance
, bool pend
);
2466 void megasas_set_dynamic_target_properties(struct scsi_device
*sdev
);
2467 int megasas_set_crash_dump_params(struct megasas_instance
*instance
,
2468 u8 crash_buf_state
);
2469 void megasas_free_host_crash_buffer(struct megasas_instance
*instance
);
2470 void megasas_fusion_crash_dump_wq(struct work_struct
*work
);
2472 void megasas_return_cmd_fusion(struct megasas_instance
*instance
,
2473 struct megasas_cmd_fusion
*cmd
);
2474 int megasas_issue_blocked_cmd(struct megasas_instance
*instance
,
2475 struct megasas_cmd
*cmd
, int timeout
);
2476 void __megasas_return_cmd(struct megasas_instance
*instance
,
2477 struct megasas_cmd
*cmd
);
2479 void megasas_return_mfi_mpt_pthr(struct megasas_instance
*instance
,
2480 struct megasas_cmd
*cmd_mfi
, struct megasas_cmd_fusion
*cmd_fusion
);
2481 int megasas_cmd_type(struct scsi_cmnd
*cmd
);
2482 void megasas_setup_jbod_map(struct megasas_instance
*instance
);
2484 void megasas_update_sdev_properties(struct scsi_device
*sdev
);
2485 int megasas_reset_fusion(struct Scsi_Host
*shost
, int reason
);
2486 int megasas_task_abort_fusion(struct scsi_cmnd
*scmd
);
2487 int megasas_reset_target_fusion(struct scsi_cmnd
*scmd
);
2488 u32
mega_mod64(u64 dividend
, u32 divisor
);
2489 int megasas_alloc_fusion_context(struct megasas_instance
*instance
);
2490 void megasas_free_fusion_context(struct megasas_instance
*instance
);
2491 #endif /*LSI_MEGARAID_SAS_H */