drivers/scsi/mpi3mr/mpi/mpi30_ioc.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *  Copyright 2016-2021 Broadcom Inc. All rights reserved.
   4  *
   5  */
   6 #ifndef MPI30_IOC_H
   7 #define MPI30_IOC_H     1
   8 struct mpi3_ioc_init_request {
   9         __le16                   host_tag;
  10         u8                       ioc_use_only02;
  11         u8                       function;
  12         __le16                   ioc_use_only04;
  13         u8                       ioc_use_only06;
  14         u8                       msg_flags;
  15         __le16                   change_count;
  16         __le16                   reserved0a;
  17         union mpi3_version_union    mpi_version;
  18         __le64                   time_stamp;
  19         u8                       reserved18;
  20         u8                       who_init;
  21         __le16                   reserved1a;
  22         __le16                   reply_free_queue_depth;
  23         __le16                   reserved1e;
  24         __le64                   reply_free_queue_address;
  25         __le32                   reserved28;
  26         __le16                   sense_buffer_free_queue_depth;
  27         __le16                   sense_buffer_length;
  28         __le64                   sense_buffer_free_queue_address;
  29         __le64                   driver_information_address;
  30 };
  31
  32 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK          (0x03)
  33 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED      (0x00)
  34 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED     (0x01)
  35 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE        (0x02)
  36 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH          (0x03)
  37 #define MPI3_WHOINIT_NOT_INITIALIZED                     (0x00)
  38 #define MPI3_WHOINIT_ROM_BIOS                            (0x02)
  39 #define MPI3_WHOINIT_HOST_DRIVER                         (0x03)
  40 #define MPI3_WHOINIT_MANUFACTURER                        (0x04)
  41 struct mpi3_driver_info_layout {
  42         __le32             information_length;
  43         u8                 driver_signature[12];
  44         u8                 os_name[16];
  45         u8                 os_version[12];
  46         u8                 driver_name[20];
  47         u8                 driver_version[32];
  48         u8                 driver_release_date[20];
  49         __le32             driver_capabilities;
  50 };
  51
  52 struct mpi3_ioc_facts_request {
  53         __le16                 host_tag;
  54         u8                     ioc_use_only02;
  55         u8                     function;
  56         __le16                 ioc_use_only04;
  57         u8                     ioc_use_only06;
  58         u8                     msg_flags;
  59         __le16                 change_count;
  60         __le16                 reserved0a;
  61         __le32                 reserved0c;
  62         union mpi3_sge_union      sgl;
  63 };
  64
  65 struct mpi3_ioc_facts_data {
  66         __le16                     ioc_facts_data_length;
  67         __le16                     reserved02;
  68         union mpi3_version_union      mpi_version;
  69         struct mpi3_comp_image_version fw_version;
  70         __le32                     ioc_capabilities;
  71         u8                         ioc_number;
  72         u8                         who_init;
  73         __le16                     max_msix_vectors;
  74         __le16                     max_outstanding_requests;
  75         __le16                     product_id;
  76         __le16                     ioc_request_frame_size;
  77         __le16                     reply_frame_size;
  78         __le16                     ioc_exceptions;
  79         __le16                     max_persistent_id;
  80         u8                         sge_modifier_mask;
  81         u8                         sge_modifier_value;
  82         u8                         sge_modifier_shift;
  83         u8                         protocol_flags;
  84         __le16                     max_sas_initiators;
  85         __le16                     max_data_length;
  86         __le16                     max_sas_expanders;
  87         __le16                     max_enclosures;
  88         __le16                     min_dev_handle;
  89         __le16                     max_dev_handle;
  90         __le16                     max_pcie_switches;
  91         __le16                     max_nvme;
  92         __le16                     reserved38;
  93         __le16                     max_vds;
  94         __le16                     max_host_pds;
  95         __le16                     max_adv_host_pds;
  96         __le16                     max_raid_pds;
  97         __le16                     max_posted_cmd_buffers;
  98         __le32                     flags;
  99         __le16                     max_operational_request_queues;
 100         __le16                     max_operational_reply_queues;
 101         __le16                     shutdown_timeout;
 102         __le16                     reserved4e;
 103         __le32                     diag_trace_size;
 104         __le32                     diag_fw_size;
 105         __le32                     diag_driver_size;
 106         u8                         max_host_pd_ns_count;
 107         u8                         max_adv_host_pd_ns_count;
 108         u8                         max_raidpd_ns_count;
 109         u8                         max_devices_per_throttle_group;
 110         __le16                     io_throttle_data_length;
 111         __le16                     max_io_throttle_group;
 112         __le16                     io_throttle_low;
 113         __le16                     io_throttle_high;
 114 };
 115 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK          (0x80000000)
 116 #define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC               (0x00000000)
 117 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC           (0x80000000)
 118 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK            (0x00000600)
 119 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0x00000000)
 120 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO  (0x00000200)
 121 #define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_CAPABLE       (0x00000100)
 122 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_ENABLED       (0x00000080)
 123 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_ENABLED          (0x00000040)
 124 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_ENABLED      (0x00000020)
 125 #define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_ENABLED     (0x00000010)
 126 #define MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE                 (0x00000008)
 127 #define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED            (0x00000002)
 128 #define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED      (0x00000001)
 129 #define MPI3_IOCFACTS_PID_TYPE_MASK                           (0xf000)
 130 #define MPI3_IOCFACTS_PID_TYPE_SHIFT                          (12)
 131 #define MPI3_IOCFACTS_PID_PRODUCT_MASK                        (0x0f00)
 132 #define MPI3_IOCFACTS_PID_PRODUCT_SHIFT                       (8)
 133 #define MPI3_IOCFACTS_PID_FAMILY_MASK                         (0x00ff)
 134 #define MPI3_IOCFACTS_PID_FAMILY_SHIFT                        (0)
 135 #define MPI3_IOCFACTS_EXCEPT_SECURITY_REKEY                   (0x2000)
 136 #define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED                     (0x1000)
 137 #define MPI3_IOCFACTS_EXCEPT_SAFE_MODE                        (0x0800)
 138 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK                (0x0700)
 139 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE                (0x0000)
 140 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT      (0x0100)
 141 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT        (0x0200)
 142 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_MGMT  (0x0300)
 143 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB       (0x0400)
 144 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB         (0x0500)
 145 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_OOB   (0x0600)
 146 #define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED                    (0x0080)
 147 #define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE           (0x0040)
 148 #define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL           (0x0020)
 149 #define MPI3_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL                 (0x0010)
 150 #define MPI3_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL             (0x0008)
 151 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK                    (0x0001)
 152 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY                 (0x0000)
 153 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY               (0x0001)
 154 #define MPI3_IOCFACTS_PROTOCOL_SAS                            (0x0010)
 155 #define MPI3_IOCFACTS_PROTOCOL_SATA                           (0x0008)
 156 #define MPI3_IOCFACTS_PROTOCOL_NVME                           (0x0004)
 157 #define MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR                 (0x0002)
 158 #define MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET                    (0x0001)
 159 #define MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED            (0x0000)
 160 #define MPI3_IOCFACTS_FLAGS_SIGNED_NVDATA_REQUIRED            (0x00010000)
 161 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK            (0x0000ff00)
 162 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT           (8)
 163 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK          (0x00000030)
 164 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED   (0x00000000)
 165 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS   (0x00000010)
 166 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE      (0x00000020)
 167 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK                  (0x0000000f)
 168 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA                  (0x00000000)
 169 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR              (0x00000002)
 170 #define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED    (0x0000)
 171 struct mpi3_mgmt_passthrough_request {
 172         __le16                 host_tag;
 173         u8                     ioc_use_only02;
 174         u8                     function;
 175         __le16                 ioc_use_only04;
 176         u8                     ioc_use_only06;
 177         u8                     msg_flags;
 178         __le16                 change_count;
 179         __le16                 reserved0a;
 180         __le32                 reserved0c[5];
 181         union mpi3_sge_union      command_sgl;
 182         union mpi3_sge_union      response_sgl;
 183 };
 184
 185 struct mpi3_create_request_queue_request {
 186         __le16             host_tag;
 187         u8                 ioc_use_only02;
 188         u8                 function;
 189         __le16             ioc_use_only04;
 190         u8                 ioc_use_only06;
 191         u8                 msg_flags;
 192         __le16             change_count;
 193         u8                 flags;
 194         u8                 burst;
 195         __le16             size;
 196         __le16             queue_id;
 197         __le16             reply_queue_id;
 198         __le16             reserved12;
 199         __le32             reserved14;
 200         __le64             base_address;
 201 };
 202
 203 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK          (0x80)
 204 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED     (0x80)
 205 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS    (0x00)
 206 #define MPI3_CREATE_REQUEST_QUEUE_SIZE_MINIMUM                  (2)
 207 struct mpi3_delete_request_queue_request {
 208         __le16             host_tag;
 209         u8                 ioc_use_only02;
 210         u8                 function;
 211         __le16             ioc_use_only04;
 212         u8                 ioc_use_only06;
 213         u8                 msg_flags;
 214         __le16             change_count;
 215         __le16             queue_id;
 216 };
 217
 218 struct mpi3_create_reply_queue_request {
 219         __le16             host_tag;
 220         u8                 ioc_use_only02;
 221         u8                 function;
 222         __le16             ioc_use_only04;
 223         u8                 ioc_use_only06;
 224         u8                 msg_flags;
 225         __le16             change_count;
 226         u8                 flags;
 227         u8                 reserved0b;
 228         __le16             size;
 229         __le16             queue_id;
 230         __le16             msix_index;
 231         __le16             reserved12;
 232         __le32             reserved14;
 233         __le64             base_address;
 234 };
 235
 236 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_MASK            (0x80)
 237 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SEGMENTED       (0x80)
 238 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS      (0x00)
 239 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_COALESCE_DISABLE          (0x02)
 240 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK           (0x01)
 241 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE        (0x00)
 242 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE         (0x01)
 243 #define MPI3_CREATE_REPLY_QUEUE_SIZE_MINIMUM                    (2)
 244 struct mpi3_delete_reply_queue_request {
 245         __le16             host_tag;
 246         u8                 ioc_use_only02;
 247         u8                 function;
 248         __le16             ioc_use_only04;
 249         u8                 ioc_use_only06;
 250         u8                 msg_flags;
 251         __le16             change_count;
 252         __le16             queue_id;
 253 };
 254
 255 struct mpi3_port_enable_request {
 256         __le16             host_tag;
 257         u8                 ioc_use_only02;
 258         u8                 function;
 259         __le16             ioc_use_only04;
 260         u8                 ioc_use_only06;
 261         u8                 msg_flags;
 262         __le16             change_count;
 263         __le16             reserved0a;
 264 };
 265
 266 #define MPI3_EVENT_LOG_DATA                         (0x01)
 267 #define MPI3_EVENT_CHANGE                           (0x02)
 268 #define MPI3_EVENT_GPIO_INTERRUPT                   (0x04)
 269 #define MPI3_EVENT_CABLE_MGMT                       (0x06)
 270 #define MPI3_EVENT_DEVICE_ADDED                     (0x07)
 271 #define MPI3_EVENT_DEVICE_INFO_CHANGED              (0x08)
 272 #define MPI3_EVENT_PREPARE_FOR_RESET                (0x09)
 273 #define MPI3_EVENT_COMP_IMAGE_ACT_START             (0x0a)
 274 #define MPI3_EVENT_ENCL_DEVICE_ADDED                (0x0b)
 275 #define MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE        (0x0c)
 276 #define MPI3_EVENT_DEVICE_STATUS_CHANGE             (0x0d)
 277 #define MPI3_EVENT_ENERGY_PACK_CHANGE               (0x0e)
 278 #define MPI3_EVENT_SAS_DISCOVERY                    (0x11)
 279 #define MPI3_EVENT_SAS_BROADCAST_PRIMITIVE          (0x12)
 280 #define MPI3_EVENT_SAS_NOTIFY_PRIMITIVE             (0x13)
 281 #define MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE    (0x14)
 282 #define MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW          (0x15)
 283 #define MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST         (0x16)
 284 #define MPI3_EVENT_SAS_PHY_COUNTER                  (0x18)
 285 #define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR       (0x19)
 286 #define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST        (0x20)
 287 #define MPI3_EVENT_PCIE_ENUMERATION                 (0x22)
 288 #define MPI3_EVENT_PCIE_ERROR_THRESHOLD             (0x23)
 289 #define MPI3_EVENT_HARD_RESET_RECEIVED              (0x40)
 290 #define MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE  (0x50)
 291 #define MPI3_EVENT_MIN_PRODUCT_SPECIFIC             (0x60)
 292 #define MPI3_EVENT_MAX_PRODUCT_SPECIFIC             (0x7f)
 293 #define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS           (4)
 294 struct mpi3_event_notification_request {
 295         __le16             host_tag;
 296         u8                 ioc_use_only02;
 297         u8                 function;
 298         __le16             ioc_use_only04;
 299         u8                 ioc_use_only06;
 300         u8                 msg_flags;
 301         __le16             change_count;
 302         __le16             reserved0a;
 303         __le16             sas_broadcast_primitive_masks;
 304         __le16             sas_notify_primitive_masks;
 305         __le32             event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
 306 };
 307
 308 struct mpi3_event_notification_reply {
 309         __le16             host_tag;
 310         u8                 ioc_use_only02;
 311         u8                 function;
 312         __le16             ioc_use_only04;
 313         u8                 ioc_use_only06;
 314         u8                 msg_flags;
 315         __le16             ioc_use_only08;
 316         __le16             ioc_status;
 317         __le32             ioc_log_info;
 318         u8                 event_data_length;
 319         u8                 event;
 320         __le16             ioc_change_count;
 321         __le32             event_context;
 322         __le32             event_data[1];
 323 };
 324
 325 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK                        (0x01)
 326 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED                    (0x01)
 327 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_NOT_REQUIRED                (0x00)
 328 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_MASK          (0x02)
 329 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_ORIGINAL      (0x00)
 330 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_REPLAY        (0x02)
 331 struct mpi3_event_data_gpio_interrupt {
 332         u8                 gpio_num;
 333         u8                 reserved01[3];
 334 };
 335 struct mpi3_event_data_cable_management {
 336         __le32             active_cable_power_requirement;
 337         u8                 status;
 338         u8                 receptacle_id;
 339         __le16             reserved06;
 340 };
 341
 342 #define MPI3_EVENT_CABLE_MGMT_ACT_CABLE_PWR_INVALID     (0xffffffff)
 343 #define MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER        (0x00)
 344 #define MPI3_EVENT_CABLE_MGMT_STATUS_PRESENT                   (0x01)
 345 #define MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED                  (0x02)
 346 struct mpi3_event_ack_request {
 347         __le16             host_tag;
 348         u8                 ioc_use_only02;
 349         u8                 function;
 350         __le16             ioc_use_only04;
 351         u8                 ioc_use_only06;
 352         u8                 msg_flags;
 353         __le16             change_count;
 354         __le16             reserved0a;
 355         u8                 event;
 356         u8                 reserved0d[3];
 357         __le32             event_context;
 358 };
 359
 360 struct mpi3_event_data_prepare_for_reset {
 361         u8                 reason_code;
 362         u8                 reserved01;
 363         __le16             reserved02;
 364 };
 365
 366 #define MPI3_EVENT_PREPARE_RESET_RC_START                (0x01)
 367 #define MPI3_EVENT_PREPARE_RESET_RC_ABORT                (0x02)
 368 struct mpi3_event_data_comp_image_activation {
 369         __le32            reserved00;
 370 };
 371
 372 struct mpi3_event_data_device_status_change {
 373         __le16             task_tag;
 374         u8                 reason_code;
 375         u8                 io_unit_port;
 376         __le16             parent_dev_handle;
 377         __le16             dev_handle;
 378         __le64             wwid;
 379         u8                 lun[8];
 380 };
 381
 382 #define MPI3_EVENT_DEV_STAT_RC_MOVED                                (0x01)
 383 #define MPI3_EVENT_DEV_STAT_RC_HIDDEN                               (0x02)
 384 #define MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN                           (0x03)
 385 #define MPI3_EVENT_DEV_STAT_RC_ASYNC_NOTIFICATION                   (0x04)
 386 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT                (0x20)
 387 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP                 (0x21)
 388 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_STRT                  (0x22)
 389 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_CMP                   (0x23)
 390 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT              (0x24)
 391 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP               (0x25)
 392 #define MPI3_EVENT_DEV_STAT_RC_PCIE_HOT_RESET_FAILED                (0x30)
 393 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_STRT           (0x40)
 394 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_CMP            (0x41)
 395 #define MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING                    (0x50)
 396 struct mpi3_event_data_energy_pack_change {
 397         __le32             reserved00;
 398         __le16             shutdown_timeout;
 399         __le16             reserved06;
 400 };
 401
 402 struct mpi3_event_data_sas_discovery {
 403         u8                 flags;
 404         u8                 reason_code;
 405         u8                 io_unit_port;
 406         u8                 reserved03;
 407         __le32             discovery_status;
 408 };
 409
 410 #define MPI3_EVENT_SAS_DISC_FLAGS_DEVICE_CHANGE                 (0x02)
 411 #define MPI3_EVENT_SAS_DISC_FLAGS_IN_PROGRESS                   (0x01)
 412 #define MPI3_EVENT_SAS_DISC_RC_STARTED                          (0x01)
 413 #define MPI3_EVENT_SAS_DISC_RC_COMPLETED                        (0x02)
 414 #define MPI3_SAS_DISC_STATUS_MAX_ENCLOSURES_EXCEED            (0x80000000)
 415 #define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED             (0x40000000)
 416 #define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED               (0x20000000)
 417 #define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
 418 #define MPI3_SAS_DISC_STATUS_INVALID_CEI                      (0x00010000)
 419 #define MPI3_SAS_DISC_STATUS_FECEI_MISMATCH                   (0x00008000)
 420 #define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT         (0x00004000)
 421 #define MPI3_SAS_DISC_STATUS_NECEI_MISMATCH                   (0x00002000)
 422 #define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS                   (0x00001000)
 423 #define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE            (0x00000800)
 424 #define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN                (0x00000400)
 425 #define MPI3_SAS_DISC_STATUS_TABLE_TO_SUBTRACTIVE_LINK        (0x00000200)
 426 #define MPI3_SAS_DISC_STATUS_UNSUPPORTED_DEVICE               (0x00000100)
 427 #define MPI3_SAS_DISC_STATUS_TABLE_LINK                       (0x00000080)
 428 #define MPI3_SAS_DISC_STATUS_SUBTRACTIVE_LINK                 (0x00000040)
 429 #define MPI3_SAS_DISC_STATUS_SMP_CRC_ERROR                    (0x00000020)
 430 #define MPI3_SAS_DISC_STATUS_SMP_FUNCTION_FAILED              (0x00000010)
 431 #define MPI3_SAS_DISC_STATUS_SMP_TIMEOUT                      (0x00000008)
 432 #define MPI3_SAS_DISC_STATUS_MULTIPLE_PORTS                   (0x00000004)
 433 #define MPI3_SAS_DISC_STATUS_INVALID_SAS_ADDRESS              (0x00000002)
 434 #define MPI3_SAS_DISC_STATUS_LOOP_DETECTED                    (0x00000001)
 435 struct mpi3_event_data_sas_broadcast_primitive {
 436         u8                 phy_num;
 437         u8                 io_unit_port;
 438         u8                 port_width;
 439         u8                 primitive;
 440 };
 441
 442 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE                 (0x01)
 443 #define MPI3_EVENT_BROADCAST_PRIMITIVE_SES                    (0x02)
 444 #define MPI3_EVENT_BROADCAST_PRIMITIVE_EXPANDER               (0x03)
 445 #define MPI3_EVENT_BROADCAST_PRIMITIVE_ASYNCHRONOUS_EVENT     (0x04)
 446 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED3              (0x05)
 447 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED4              (0x06)
 448 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE0_RESERVED       (0x07)
 449 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE1_RESERVED       (0x08)
 450 struct mpi3_event_data_sas_notify_primitive {
 451         u8                 phy_num;
 452         u8                 io_unit_port;
 453         u8                 reserved02;
 454         u8                 primitive;
 455 };
 456
 457 #define MPI3_EVENT_NOTIFY_PRIMITIVE_ENABLE_SPINUP         (0x01)
 458 #define MPI3_EVENT_NOTIFY_PRIMITIVE_POWER_LOSS_EXPECTED   (0x02)
 459 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED1             (0x03)
 460 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED2             (0x04)
 461 #ifndef MPI3_EVENT_SAS_TOPO_PHY_COUNT
 462 #define MPI3_EVENT_SAS_TOPO_PHY_COUNT           (1)
 463 #endif
 464 struct mpi3_event_sas_topo_phy_entry {
 465         __le16             attached_dev_handle;
 466         u8                 link_rate;
 467         u8                 status;
 468 };
 469
 470 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_MASK                 (0xf0)
 471 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_SHIFT                (4)
 472 #define MPI3_EVENT_SAS_TOPO_LR_PREV_MASK                    (0x0f)
 473 #define MPI3_EVENT_SAS_TOPO_LR_PREV_SHIFT                   (0)
 474 #define MPI3_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE            (0x00)
 475 #define MPI3_EVENT_SAS_TOPO_LR_PHY_DISABLED                 (0x01)
 476 #define MPI3_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED           (0x02)
 477 #define MPI3_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE            (0x03)
 478 #define MPI3_EVENT_SAS_TOPO_LR_PORT_SELECTOR                (0x04)
 479 #define MPI3_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS        (0x05)
 480 #define MPI3_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY              (0x06)
 481 #define MPI3_EVENT_SAS_TOPO_LR_RATE_6_0                     (0x0a)
 482 #define MPI3_EVENT_SAS_TOPO_LR_RATE_12_0                    (0x0b)
 483 #define MPI3_EVENT_SAS_TOPO_LR_RATE_22_5                    (0x0c)
 484 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_MASK                 (0xc0)
 485 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_SHIFT                (6)
 486 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_ACCESSIBLE           (0x00)
 487 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_NO_EXIST             (0x40)
 488 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_VACANT               (0x80)
 489 #define MPI3_EVENT_SAS_TOPO_PHY_RC_MASK                     (0x0f)
 490 #define MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING      (0x02)
 491 #define MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED              (0x03)
 492 #define MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE                (0x04)
 493 #define MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING     (0x05)
 494 #define MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING               (0x06)
 495 struct mpi3_event_data_sas_topology_change_list {
 496         __le16                             enclosure_handle;
 497         __le16                             expander_dev_handle;
 498         u8                                 num_phys;
 499         u8                                 reserved05[3];
 500         u8                                 num_entries;
 501         u8                                 start_phy_num;
 502         u8                                 exp_status;
 503         u8                                 io_unit_port;
 504         struct mpi3_event_sas_topo_phy_entry   phy_entry[MPI3_EVENT_SAS_TOPO_PHY_COUNT];
 505 };
 506
 507 #define MPI3_EVENT_SAS_TOPO_ES_NO_EXPANDER              (0x00)
 508 #define MPI3_EVENT_SAS_TOPO_ES_NOT_RESPONDING           (0x02)
 509 #define MPI3_EVENT_SAS_TOPO_ES_RESPONDING               (0x03)
 510 #define MPI3_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING     (0x04)
 511 struct mpi3_event_data_sas_phy_counter {
 512         __le64             time_stamp;
 513         __le32             reserved08;
 514         u8                 phy_event_code;
 515         u8                 phy_num;
 516         __le16             reserved0e;
 517         __le32             phy_event_info;
 518         u8                 counter_type;
 519         u8                 threshold_window;
 520         u8                 time_units;
 521         u8                 reserved17;
 522         __le32             event_threshold;
 523         __le16             threshold_flags;
 524         __le16             reserved1e;
 525 };
 526
 527 struct mpi3_event_data_sas_device_disc_err {
 528         __le16             dev_handle;
 529         u8                 reason_code;
 530         u8                 io_unit_port;
 531         __le32             reserved04;
 532         __le64             sas_address;
 533 };
 534
 535 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_FAILED          (0x01)
 536 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_TIMEOUT         (0x02)
 537 struct mpi3_event_data_pcie_enumeration {
 538         u8                 flags;
 539         u8                 reason_code;
 540         u8                 io_unit_port;
 541         u8                 reserved03;
 542         __le32             enumeration_status;
 543 };
 544
 545 #define MPI3_EVENT_PCIE_ENUM_FLAGS_DEVICE_CHANGE            (0x02)
 546 #define MPI3_EVENT_PCIE_ENUM_FLAGS_IN_PROGRESS              (0x01)
 547 #define MPI3_EVENT_PCIE_ENUM_RC_STARTED                     (0x01)
 548 #define MPI3_EVENT_PCIE_ENUM_RC_COMPLETED                   (0x02)
 549 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCH_DEPTH_EXCEED     (0x80000000)
 550 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED         (0x40000000)
 551 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED          (0x20000000)
 552 #define MPI3_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED         (0x10000000)
 553 #ifndef MPI3_EVENT_PCIE_TOPO_PORT_COUNT
 554 #define MPI3_EVENT_PCIE_TOPO_PORT_COUNT         (1)
 555 #endif
 556 struct mpi3_event_pcie_topo_port_entry {
 557         __le16             attached_dev_handle;
 558         u8                 port_status;
 559         u8                 reserved03;
 560         u8                 current_port_info;
 561         u8                 reserved05;
 562         u8                 previous_port_info;
 563         u8                 reserved07;
 564 };
 565
 566 #define MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING          (0x02)
 567 #define MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED            (0x03)
 568 #define MPI3_EVENT_PCIE_TOPO_PS_NO_CHANGE               (0x04)
 569 #define MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING    (0x05)
 570 #define MPI3_EVENT_PCIE_TOPO_PS_RESPONDING              (0x06)
 571 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_MASK              (0xf0)
 572 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN           (0x00)
 573 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_1                 (0x10)
 574 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_2                 (0x20)
 575 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_4                 (0x30)
 576 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_8                 (0x40)
 577 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_16                (0x50)
 578 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK               (0x0f)
 579 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN            (0x00)
 580 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_DISABLED           (0x01)
 581 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_2_5                (0x02)
 582 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_5_0                (0x03)
 583 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_8_0                (0x04)
 584 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_16_0               (0x05)
 585 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_32_0               (0x06)
 586 struct mpi3_event_data_pcie_topology_change_list {
 587         __le16                                 enclosure_handle;
 588         __le16                                 switch_dev_handle;
 589         u8                                     num_ports;
 590         u8                                     reserved05[3];
 591         u8                                     num_entries;
 592         u8                                     start_port_num;
 593         u8                                     switch_status;
 594         u8                                     io_unit_port;
 595         __le32                                 reserved0c;
 596         struct mpi3_event_pcie_topo_port_entry     port_entry[MPI3_EVENT_PCIE_TOPO_PORT_COUNT];
 597 };
 598
 599 #define MPI3_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH          (0x00)
 600 #define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING          (0x02)
 601 #define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING              (0x03)
 602 #define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING    (0x04)
 603 struct mpi3_event_data_pcie_error_threshold {
 604         __le64                                 timestamp;
 605         u8                                     reason_code;
 606         u8                                     port;
 607         __le16                                 switch_dev_handle;
 608         u8                                     error;
 609         u8                                     action;
 610         __le16                                 threshold_count;
 611         __le16                                 attached_dev_handle;
 612         __le16                                 reserved12;
 613 };
 614
 615 #define MPI3_EVENT_PCI_ERROR_RC_THRESHOLD_EXCEEDED          (0x00)
 616 #define MPI3_EVENT_PCI_ERROR_RC_ESCALATION                  (0x01)
 617 struct mpi3_event_data_sas_init_dev_status_change {
 618         u8                 reason_code;
 619         u8                 io_unit_port;
 620         __le16             dev_handle;
 621         __le32             reserved04;
 622         __le64             sas_address;
 623 };
 624
 625 #define MPI3_EVENT_SAS_INIT_RC_ADDED                (0x01)
 626 #define MPI3_EVENT_SAS_INIT_RC_NOT_RESPONDING       (0x02)
 627 struct mpi3_event_data_sas_init_table_overflow {
 628         __le16             max_init;
 629         __le16             current_init;
 630         __le32             reserved04;
 631         __le64             sas_address;
 632 };
 633
 634 struct mpi3_event_data_hard_reset_received {
 635         u8                 reserved00;
 636         u8                 io_unit_port;
 637         __le16             reserved02;
 638 };
 639
 640 struct mpi3_event_data_diag_buffer_status_change {
 641         u8                 type;
 642         u8                 reason_code;
 643         __le16             reserved02;
 644         __le32             reserved04;
 645 };
 646
 647 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RELEASED             (0x01)
 648 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_PAUSED               (0x02)
 649 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RESUMED              (0x03)
 650 #define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT   (0x0200)
 651 #define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT       (0x0100)
 652 #define MPI3_PEL_LOCALE_FLAGS_PCIE                      (0x0080)
 653 #define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION             (0x0040)
 654 #define MPI3_PEL_LOCALE_FLAGS_CONTROLER                 (0x0020)
 655 #define MPI3_PEL_LOCALE_FLAGS_SAS                       (0x0010)
 656 #define MPI3_PEL_LOCALE_FLAGS_EPACK                     (0x0008)
 657 #define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE                 (0x0004)
 658 #define MPI3_PEL_LOCALE_FLAGS_PD                        (0x0002)
 659 #define MPI3_PEL_LOCALE_FLAGS_VD                        (0x0001)
 660 #define MPI3_PEL_CLASS_DEBUG                            (0x00)
 661 #define MPI3_PEL_CLASS_PROGRESS                         (0x01)
 662 #define MPI3_PEL_CLASS_INFORMATIONAL                    (0x02)
 663 #define MPI3_PEL_CLASS_WARNING                          (0x03)
 664 #define MPI3_PEL_CLASS_CRITICAL                         (0x04)
 665 #define MPI3_PEL_CLASS_FATAL                            (0x05)
 666 #define MPI3_PEL_CLASS_FAULT                            (0x06)
 667 #define MPI3_PEL_CLEARTYPE_CLEAR                        (0x00)
 668 #define MPI3_PEL_WAITTIME_INFINITE_WAIT                 (0x00)
 669 #define MPI3_PEL_ACTION_GET_SEQNUM                      (0x01)
 670 #define MPI3_PEL_ACTION_MARK_CLEAR                      (0x02)
 671 #define MPI3_PEL_ACTION_GET_LOG                         (0x03)
 672 #define MPI3_PEL_ACTION_GET_COUNT                       (0x04)
 673 #define MPI3_PEL_ACTION_WAIT                            (0x05)
 674 #define MPI3_PEL_ACTION_ABORT                           (0x06)
 675 #define MPI3_PEL_ACTION_GET_PRINT_STRINGS               (0x07)
 676 #define MPI3_PEL_ACTION_ACKNOWLEDGE                     (0x08)
 677 #define MPI3_PEL_STATUS_SUCCESS                         (0x00)
 678 #define MPI3_PEL_STATUS_NOT_FOUND                       (0x01)
 679 #define MPI3_PEL_STATUS_ABORTED                         (0x02)
 680 #define MPI3_PEL_STATUS_NOT_READY                       (0x03)
 681 struct mpi3_pel_seq {
 682         __le32                             newest;
 683         __le32                             oldest;
 684         __le32                             clear;
 685         __le32                             shutdown;
 686         __le32                             boot;
 687         __le32                             last_acknowledged;
 688 };
 689
 690 struct mpi3_pel_entry {
 691         __le64                             time_stamp;
 692         __le32                             sequence_number;
 693         __le16                             log_code;
 694         __le16                             arg_type;
 695         __le16                             locale;
 696         u8                                 class;
 697         u8                                 flags;
 698         u8                                 ext_num;
 699         u8                                 num_exts;
 700         u8                                 arg_data_size;
 701         u8                                 fixed_format_strings_size;
 702         __le32                             reserved18[2];
 703         __le32                             pel_info[24];
 704 };
 705
 706 #define MPI3_PEL_FLAGS_COMPLETE_RESET_NEEDED                  (0x02)
 707 #define MPI3_PEL_FLAGS_ACK_NEEDED                             (0x01)
 708 struct mpi3_pel_list {
 709         __le32                             log_count;
 710         __le32                             reserved04;
 711         struct mpi3_pel_entry                  entry[1];
 712 };
 713
 714 struct mpi3_pel_arg_map {
 715         u8                                 arg_type;
 716         u8                                 length;
 717         __le16                             start_location;
 718 };
 719
 720 #define MPI3_PEL_ARG_MAP_ARG_TYPE_APPEND_STRING                (0x00)
 721 #define MPI3_PEL_ARG_MAP_ARG_TYPE_INTEGER                      (0x01)
 722 #define MPI3_PEL_ARG_MAP_ARG_TYPE_STRING                       (0x02)
 723 #define MPI3_PEL_ARG_MAP_ARG_TYPE_BIT_FIELD                    (0x03)
 724 struct mpi3_pel_print_string {
 725         __le16                             log_code;
 726         __le16                             string_length;
 727         u8                                 num_arg_map;
 728         u8                                 reserved05[3];
 729         struct mpi3_pel_arg_map                arg_map[1];
 730 };
 731
 732 struct mpi3_pel_print_string_list {
 733         __le32                             num_print_strings;
 734         __le32                             residual_bytes_remain;
 735         __le32                             reserved08[2];
 736         struct mpi3_pel_print_string           print_string[1];
 737 };
 738
 739 #ifndef MPI3_PEL_ACTION_SPECIFIC_MAX
 740 #define MPI3_PEL_ACTION_SPECIFIC_MAX               (1)
 741 #endif
 742 struct mpi3_pel_request {
 743         __le16                             host_tag;
 744         u8                                 ioc_use_only02;
 745         u8                                 function;
 746         __le16                             ioc_use_only04;
 747         u8                                 ioc_use_only06;
 748         u8                                 msg_flags;
 749         __le16                             change_count;
 750         u8                                 action;
 751         u8                                 reserved0b;
 752         __le32                             action_specific[MPI3_PEL_ACTION_SPECIFIC_MAX];
 753 };
 754
 755 struct mpi3_pel_req_action_get_sequence_numbers {
 756         __le16                             host_tag;
 757         u8                                 ioc_use_only02;
 758         u8                                 function;
 759         __le16                             ioc_use_only04;
 760         u8                                 ioc_use_only06;
 761         u8                                 msg_flags;
 762         __le16                             change_count;
 763         u8                                 action;
 764         u8                                 reserved0b;
 765         __le32                             reserved0c[5];
 766         union mpi3_sge_union                  sgl;
 767 };
 768
 769 struct mpi3_pel_req_action_clear_log_marker {
 770         __le16                             host_tag;
 771         u8                                 ioc_use_only02;
 772         u8                                 function;
 773         __le16                             ioc_use_only04;
 774         u8                                 ioc_use_only06;
 775         u8                                 msg_flags;
 776         __le16                             change_count;
 777         u8                                 action;
 778         u8                                 reserved0b;
 779         u8                                 clear_type;
 780         u8                                 reserved0d[3];
 781 };
 782
 783 struct mpi3_pel_req_action_get_log {
 784         __le16                             host_tag;
 785         u8                                 ioc_use_only02;
 786         u8                                 function;
 787         __le16                             ioc_use_only04;
 788         u8                                 ioc_use_only06;
 789         u8                                 msg_flags;
 790         __le16                             change_count;
 791         u8                                 action;
 792         u8                                 reserved0b;
 793         __le32                             starting_sequence_number;
 794         __le16                             locale;
 795         u8                                 class;
 796         u8                                 reserved13;
 797         __le32                             reserved14[3];
 798         union mpi3_sge_union                  sgl;
 799 };
 800
 801 struct mpi3_pel_req_action_get_count {
 802         __le16                             host_tag;
 803         u8                                 ioc_use_only02;
 804         u8                                 function;
 805         __le16                             ioc_use_only04;
 806         u8                                 ioc_use_only06;
 807         u8                                 msg_flags;
 808         __le16                             change_count;
 809         u8                                 action;
 810         u8                                 reserved0b;
 811         __le32                             starting_sequence_number;
 812         __le16                             locale;
 813         u8                                 class;
 814         u8                                 reserved13;
 815         __le32                             reserved14[3];
 816         union mpi3_sge_union                  sgl;
 817 };
 818
 819 struct mpi3_pel_req_action_wait {
 820         __le16                             host_tag;
 821         u8                                 ioc_use_only02;
 822         u8                                 function;
 823         __le16                             ioc_use_only04;
 824         u8                                 ioc_use_only06;
 825         u8                                 msg_flags;
 826         __le16                             change_count;
 827         u8                                 action;
 828         u8                                 reserved0b;
 829         __le32                             starting_sequence_number;
 830         __le16                             locale;
 831         u8                                 class;
 832         u8                                 reserved13;
 833         __le16                             wait_time;
 834         __le16                             reserved16;
 835         __le32                             reserved18[2];
 836 };
 837
 838 struct mpi3_pel_req_action_abort {
 839         __le16                             host_tag;
 840         u8                                 ioc_use_only02;
 841         u8                                 function;
 842         __le16                             ioc_use_only04;
 843         u8                                 ioc_use_only06;
 844         u8                                 msg_flags;
 845         __le16                             change_count;
 846         u8                                 action;
 847         u8                                 reserved0b;
 848         __le32                             reserved0c;
 849         __le16                             abort_host_tag;
 850         __le16                             reserved12;
 851         __le32                             reserved14;
 852 };
 853
 854 struct mpi3_pel_req_action_get_print_strings {
 855         __le16                             host_tag;
 856         u8                                 ioc_use_only02;
 857         u8                                 function;
 858         __le16                             ioc_use_only04;
 859         u8                                 ioc_use_only06;
 860         u8                                 msg_flags;
 861         __le16                             change_count;
 862         u8                                 action;
 863         u8                                 reserved0b;
 864         __le32                             reserved0c;
 865         __le16                             start_log_code;
 866         __le16                             reserved12;
 867         __le32                             reserved14[3];
 868         union mpi3_sge_union                  sgl;
 869 };
 870
 871 struct mpi3_pel_req_action_acknowledge {
 872         __le16                             host_tag;
 873         u8                                 ioc_use_only02;
 874         u8                                 function;
 875         __le16                             ioc_use_only04;
 876         u8                                 ioc_use_only06;
 877         u8                                 msg_flags;
 878         __le16                             change_count;
 879         u8                                 action;
 880         u8                                 reserved0b;
 881         __le32                             sequence_number;
 882         __le32                             reserved10;
 883 };
 884
 885 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK                     (0x03)
 886 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE              (0x00)
 887 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP              (0x01)
 888 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT      (0x02)
 889 struct mpi3_pel_reply {
 890         __le16                             host_tag;
 891         u8                                 ioc_use_only02;
 892         u8                                 function;
 893         __le16                             ioc_use_only04;
 894         u8                                 ioc_use_only06;
 895         u8                                 msg_flags;
 896         __le16                             ioc_use_only08;
 897         __le16                             ioc_status;
 898         __le32                             ioc_log_info;
 899         u8                                 action;
 900         u8                                 reserved11;
 901         __le16                             reserved12;
 902         __le16                             pe_log_status;
 903         __le16                             reserved16;
 904         __le32                             transfer_length;
 905 };
 906
 907 struct mpi3_ci_download_request {
 908         __le16                             host_tag;
 909         u8                                 ioc_use_only02;
 910         u8                                 function;
 911         __le16                             ioc_use_only04;
 912         u8                                 ioc_use_only06;
 913         u8                                 msg_flags;
 914         __le16                             change_count;
 915         u8                                 action;
 916         u8                                 reserved0b;
 917         __le32                             signature1;
 918         __le32                             total_image_size;
 919         __le32                             image_offset;
 920         __le32                             segment_size;
 921         __le32                             reserved1c;
 922         union mpi3_sge_union                  sgl;
 923 };
 924
 925 #define MPI3_CI_DOWNLOAD_MSGFLAGS_LAST_SEGMENT                 (0x80)
 926 #define MPI3_CI_DOWNLOAD_MSGFLAGS_FORCE_FMC_ENABLE             (0x40)
 927 #define MPI3_CI_DOWNLOAD_MSGFLAGS_SIGNED_NVDATA                (0x20)
 928 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MASK       (0x03)
 929 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_FAST       (0x00)
 930 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MEDIUM     (0x01)
 931 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SLOW       (0x02)
 932 #define MPI3_CI_DOWNLOAD_ACTION_DOWNLOAD                       (0x01)
 933 #define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION              (0x02)
 934 #define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION             (0x03)
 935 #define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS                     (0x04)
 936 #define MPI3_CI_DOWNLOAD_ACTION_CANCEL_OFFLINE_ACTIVATION      (0x05)
 937 struct mpi3_ci_download_reply {
 938         __le16                             host_tag;
 939         u8                                 ioc_use_only02;
 940         u8                                 function;
 941         __le16                             ioc_use_only04;
 942         u8                                 ioc_use_only06;
 943         u8                                 msg_flags;
 944         __le16                             ioc_use_only08;
 945         __le16                             ioc_status;
 946         __le32                             ioc_log_info;
 947         u8                                 flags;
 948         u8                                 cache_dirty;
 949         u8                                 pending_count;
 950         u8                                 reserved13;
 951 };
 952
 953 #define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS                  (0x80)
 954 #define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED           (0x20)
 955 #define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING                    (0x10)
 956 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK                (0x0e)
 957 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED          (0x00)
 958 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_AWAITING            (0x02)
 959 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_ONLINE_PENDING      (0x04)
 960 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_OFFLINE_PENDING     (0x06)
 961 #define MPI3_CI_DOWNLOAD_FLAGS_COMPATIBLE                            (0x01)
 962 struct mpi3_ci_upload_request {
 963         __le16                             host_tag;
 964         u8                                 ioc_use_only02;
 965         u8                                 function;
 966         __le16                             ioc_use_only04;
 967         u8                                 ioc_use_only06;
 968         u8                                 msg_flags;
 969         __le16                             change_count;
 970         __le16                             reserved0a;
 971         __le32                             signature1;
 972         __le32                             reserved10;
 973         __le32                             image_offset;
 974         __le32                             segment_size;
 975         __le32                             reserved1c;
 976         union mpi3_sge_union                  sgl;
 977 };
 978
 979 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_MASK                        (0x01)
 980 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY                     (0x00)
 981 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SECONDARY                   (0x01)
 982 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_MASK                          (0x02)
 983 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_FLASH                         (0x00)
 984 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_EXECUTABLE                    (0x02)
 985 #define MPI3_CTRL_OP_FORCE_FULL_DISCOVERY                            (0x01)
 986 #define MPI3_CTRL_OP_LOOKUP_MAPPING                                  (0x02)
 987 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP                                (0x04)
 988 #define MPI3_CTRL_OP_GET_TIMESTAMP                                   (0x05)
 989 #define MPI3_CTRL_OP_GET_IOC_CHANGE_COUNT                            (0x06)
 990 #define MPI3_CTRL_OP_CHANGE_PROFILE                                  (0x07)
 991 #define MPI3_CTRL_OP_REMOVE_DEVICE                                   (0x10)
 992 #define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION                     (0x11)
 993 #define MPI3_CTRL_OP_HIDDEN_ACK                                      (0x12)
 994 #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS                           (0x13)
 995 #define MPI3_CTRL_OP_SEND_SAS_PRIMITIVE                              (0x20)
 996 #define MPI3_CTRL_OP_SAS_PHY_CONTROL                                 (0x21)
 997 #define MPI3_CTRL_OP_READ_INTERNAL_BUS                               (0x23)
 998 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS                              (0x24)
 999 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL                               (0x30)
1000 #define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX       (0x00)
1001 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX        (0x00)
1002 #define MPI3_CTRL_OP_CHANGE_PROFILE_PARAM8_PROFILE_ID_INDEX          (0x00)
1003 #define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX           (0x00)
1004 #define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX      (0x00)
1005 #define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX              (0x00)
1006 #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS_PARAM16_DEVHANDLE_INDEX   (0x00)
1007 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PHY_INDEX                  (0x00)
1008 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PRIMSEQ_INDEX              (0x01)
1009 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM32_PRIMITIVE_INDEX           (0x00)
1010 #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_ACTION_INDEX             (0x00)
1011 #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_PHY_INDEX                (0x01)
1012 #define MPI3_CTRL_OP_READ_INTERNAL_BUS_PARAM64_ADDRESS_INDEX         (0x00)
1013 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM64_ADDRESS_INDEX        (0x00)
1014 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM32_VALUE_INDEX          (0x00)
1015 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_ACTION_INDEX           (0x00)
1016 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_LINK_INDEX             (0x01)
1017 #define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS                         (0x01)
1018 #define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT                       (0x02)
1019 #define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME                      (0x03)
1020 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTENT_ID                        (0x04)
1021 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM16_DEVH_INDEX             (0)
1022 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM64_WWID_INDEX             (0)
1023 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM16_SLOTNUM_INDEX          (0)
1024 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM64_ENCLOSURELID_INDEX     (0)
1025 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM16_DEVH_INDEX           (0)
1026 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM64_DEVNAME_INDEX        (0)
1027 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_DEVH_INDEX            (0)
1028 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX   (1)
1029 #define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX                      (0)
1030 #define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX                 (0)
1031 #define MPI3_CTRL_GET_IOC_CHANGE_COUNT_VALUE16_CHANGECOUNT_INDEX        (0)
1032 #define MPI3_CTRL_READ_INTERNAL_BUS_VALUE32_VALUE_INDEX                 (0)
1033 #define MPI3_CTRL_PRIMFLAGS_SINGLE                                   (0x01)
1034 #define MPI3_CTRL_PRIMFLAGS_TRIPLE                                   (0x03)
1035 #define MPI3_CTRL_PRIMFLAGS_REDUNDANT                                (0x06)
1036 #define MPI3_CTRL_ACTION_NOP                                         (0x00)
1037 #define MPI3_CTRL_ACTION_LINK_RESET                                  (0x01)
1038 #define MPI3_CTRL_ACTION_HARD_RESET                                  (0x02)
1039 #define MPI3_CTRL_ACTION_CLEAR_ERROR_LOG                             (0x05)
1040 struct mpi3_iounit_control_request {
1041         __le16                             host_tag;
1042         u8                                 ioc_use_only02;
1043         u8                                 function;
1044         __le16                             ioc_use_only04;
1045         u8                                 ioc_use_only06;
1046         u8                                 msg_flags;
1047         __le16                             change_count;
1048         u8                                 reserved0a;
1049         u8                                 operation;
1050         __le32                             reserved0c;
1051         __le64                             param64[2];
1052         __le32                             param32[4];
1053         __le16                             param16[4];
1054         u8                                 param8[8];
1055 };
1056
1057 struct mpi3_iounit_control_reply {
1058         __le16                             host_tag;
1059         u8                                 ioc_use_only02;
1060         u8                                 function;
1061         __le16                             ioc_use_only04;
1062         u8                                 ioc_use_only06;
1063         u8                                 msg_flags;
1064         __le16                             ioc_use_only08;
1065         __le16                             ioc_status;
1066         __le32                             ioc_log_info;
1067         __le64                             value64[2];
1068         __le32                             value32[4];
1069         __le16                             value16[4];
1070         u8                                 value8[8];
1071 };
1072 #endif