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HID: sony: Remove the size check for the Dualshock 4 HID Descriptor
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / mpt2sas / mpi / mpi2_cnfg.h
1 /*
2 * Copyright (c) 2000-2014 LSI Corporation.
3 *
4 *
5 * Name: mpi2_cnfg.h
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
8 *
9 * mpi2_cnfg.h Version: 02.00.29
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
18 * Added Manufacturing Page 11.
19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
20 * define.
21 * 06-26-07 02.00.02 Adding generic structure for product-specific
22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
23 * Rework of BIOS Page 2 configuration page.
24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
25 * forms.
26 * Added configuration pages IOC Page 8 and Driver
27 * Persistent Mapping Page 0.
28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
30 * RAID Physical Disk Pages 0 and 1, RAID Configuration
31 * Page 0).
32 * Added new value for AccessStatus field of SAS Device
33 * Page 0 (_SATA_NEEDS_INITIALIZATION).
34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
37 * NVDATA.
38 * Modified IOC Page 7 to use masks and added field for
39 * SASBroadcastPrimitiveMasks.
40 * Added MPI2_CONFIG_PAGE_BIOS_4.
41 * Added MPI2_CONFIG_PAGE_LOG_0.
42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
43 * Added SAS Device IDs.
44 * Updated Integrated RAID configuration pages including
45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
46 * Page 0.
47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
50 * Added missing MaxNumRoutedSasAddresses field to
51 * MPI2_CONFIG_PAGE_EXPANDER_0.
52 * Added SAS Port Page 0.
53 * Modified structure layout for
54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
58 * to 0x000000FF.
59 * Added two new values for the Physical Disk Coercion Size
60 * bits in the Flags field of Manufacturing Page 4.
61 * Added product-specific Manufacturing pages 16 to 31.
62 * Modified Flags bits for controlling write cache on SATA
63 * drives in IO Unit Page 1.
64 * Added new bit to AdditionalControlFlags of SAS IO Unit
65 * Page 1 to control Invalid Topology Correction.
66 * Added additional defines for RAID Volume Page 0
67 * VolumeStatusFlags field.
68 * Modified meaning of RAID Volume Page 0 VolumeSettings
69 * define for auto-configure of hot-swap drives.
70 * Added SupportedPhysDisks field to RAID Volume Page 1 and
71 * added related defines.
72 * Added PhysDiskAttributes field (and related defines) to
73 * RAID Physical Disk Page 0.
74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
75 * Added three new DiscoveryStatus bits for SAS IO Unit
76 * Page 0 and SAS Expander Page 0.
77 * Removed multiplexing information from SAS IO Unit pages.
78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
79 * Removed Zone Address Resolved bit from PhyInfo and from
80 * Expander Page 0 Flags field.
81 * Added two new AccessStatus values to SAS Device Page 0
82 * for indicating routing problems. Added 3 reserved words
83 * to this page.
84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
85 * Inserted missing reserved field into structure for IOC
86 * Page 6.
87 * Added more pending task bits to RAID Volume Page 0
88 * VolumeStatusFlags defines.
89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
91 * and SAS Expander Page 0 to flag a downstream initiator
92 * when in simplified routing mode.
93 * Removed SATA Init Failure defines for DiscoveryStatus
94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
96 * Added PortGroups, DmaGroup, and ControlGroup fields to
97 * SAS Device Page 0.
98 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
99 * Unit Page 6.
100 * Added expander reduced functionality data to SAS
101 * Expander Page 0.
102 * Added SAS PHY Page 2 and SAS PHY Page 3.
103 * 07-30-09 02.00.12 Added IO Unit Page 7.
104 * Added new device ids.
105 * Added SAS IO Unit Page 5.
106 * Added partial and slumber power management capable flags
107 * to SAS Device Page 0 Flags field.
108 * Added PhyInfo defines for power condition.
109 * Added Ethernet configuration pages.
110 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
111 * Added SAS PHY Page 4 structure and defines.
112 * 02-10-10 02.00.14 Modified the comments for the configuration page
113 * structures that contain an array of data. The host
114 * should use the "count" field in the page data (e.g. the
115 * NumPhys field) to determine the number of valid elements
116 * in the array.
117 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
118 * Added PowerManagementCapabilities to IO Unit Page 7.
119 * Added PortWidthModGroup field to
120 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
121 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
122 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
123 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
124 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
125 * define.
126 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
127 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
128 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
129 * defines.
130 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
131 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
132 * the Pinout field.
133 * Added BoardTemperature and BoardTemperatureUnits fields
134 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
135 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
136 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
137 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
138 * Added IO Unit Page 8, IO Unit Page 9,
139 * and IO Unit Page 10.
140 * Added SASNotifyPrimitiveMasks field to
141 * MPI2_CONFIG_PAGE_IOC_7.
142 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec).
143 * 05-25-11 02.00.20 Cleaned up a few comments.
144 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities
145 * for PCIe link as obsolete.
146 * Added SpinupFlags field containing a Disable Spin-up
147 * bit to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of
148 * SAS IO Unit Page 4.
149 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
150 * Added UEFIVersion field to BIOS Page 1 and defined new
151 * BiosOptions bits.
152 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
153 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
154 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
155 * obsolete for MPI v2.5 and later.
156 * Added some defines for 12G SAS speeds.
157 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
158 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
159 * match the specification.
160 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
161 * MPI2_CONFIG_PAGE_MAN_7.
162 * Added EnclosureLevel and ConnectorName fields to
163 * MPI2_CONFIG_PAGE_SAS_DEV_0.
164 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
165 * MPI2_CONFIG_PAGE_SAS_DEV_0.
166 * Added EnclosureLevel field to
167 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
168 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
169 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
170 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of
171 * MPI2_CONFIG_PAGE_BIOS_1.
172 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and
173 * more defines for the BiosOptions field.
174 * --------------------------------------------------------------------------
175 */
176
177 #ifndef MPI2_CNFG_H
178 #define MPI2_CNFG_H
179
180 /*****************************************************************************
181 * Configuration Page Header and defines
182 *****************************************************************************/
183
184 /* Config Page Header */
185 typedef struct _MPI2_CONFIG_PAGE_HEADER
186 {
187 U8 PageVersion; /* 0x00 */
188 U8 PageLength; /* 0x01 */
189 U8 PageNumber; /* 0x02 */
190 U8 PageType; /* 0x03 */
191 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
192 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
193
194 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
195 {
196 MPI2_CONFIG_PAGE_HEADER Struct;
197 U8 Bytes[4];
198 U16 Word16[2];
199 U32 Word32;
200 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
201 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
202
203 /* Extended Config Page Header */
204 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
205 {
206 U8 PageVersion; /* 0x00 */
207 U8 Reserved1; /* 0x01 */
208 U8 PageNumber; /* 0x02 */
209 U8 PageType; /* 0x03 */
210 U16 ExtPageLength; /* 0x04 */
211 U8 ExtPageType; /* 0x06 */
212 U8 Reserved2; /* 0x07 */
213 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
214 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
215 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
216
217 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
218 {
219 MPI2_CONFIG_PAGE_HEADER Struct;
220 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
221 U8 Bytes[8];
222 U16 Word16[4];
223 U32 Word32[2];
224 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
225 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
226
227
228 /* PageType field values */
229 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
230 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
231 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
232 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
233
234 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
235 #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
236 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
237 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
238 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
239 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
240 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
241 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
242
243 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
244
245
246 /* ExtPageType field values */
247 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
248 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
249 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
250 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
251 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
252 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
253 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
254 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
255 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
256 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
257 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
258
259
260 /*****************************************************************************
261 * PageAddress defines
262 *****************************************************************************/
263
264 /* RAID Volume PageAddress format */
265 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
266 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
267 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
268
269 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
270
271
272 /* RAID Physical Disk PageAddress format */
273 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
274 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
275 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
276 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
277
278 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
279 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
280
281
282 /* SAS Expander PageAddress format */
283 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
284 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
285 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
286 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
287
288 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
289 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
290 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
291
292
293 /* SAS Device PageAddress format */
294 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
295 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
296 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
297
298 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
299
300
301 /* SAS PHY PageAddress format */
302 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
303 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
304 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
305
306 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
307 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
308
309
310 /* SAS Port PageAddress format */
311 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
312 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
313 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
314
315 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
316
317
318 /* SAS Enclosure PageAddress format */
319 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
320 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
321 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
322
323 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
324
325
326 /* RAID Configuration PageAddress format */
327 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
328 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
329 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
330 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
331
332 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
333
334
335 /* Driver Persistent Mapping PageAddress format */
336 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
337 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
338
339 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
340 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
341 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
342
343
344 /* Ethernet PageAddress format */
345 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
346 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
347
348 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
349
350
351
352 /****************************************************************************
353 * Configuration messages
354 ****************************************************************************/
355
356 /* Configuration Request Message */
357 typedef struct _MPI2_CONFIG_REQUEST
358 {
359 U8 Action; /* 0x00 */
360 U8 SGLFlags; /* 0x01 */
361 U8 ChainOffset; /* 0x02 */
362 U8 Function; /* 0x03 */
363 U16 ExtPageLength; /* 0x04 */
364 U8 ExtPageType; /* 0x06 */
365 U8 MsgFlags; /* 0x07 */
366 U8 VP_ID; /* 0x08 */
367 U8 VF_ID; /* 0x09 */
368 U16 Reserved1; /* 0x0A */
369 U8 Reserved2; /* 0x0C */
370 U8 ProxyVF_ID; /* 0x0D */
371 U16 Reserved4; /* 0x0E */
372 U32 Reserved3; /* 0x10 */
373 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
374 U32 PageAddress; /* 0x18 */
375 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
376 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
377 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
378
379 /* values for the Action field */
380 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
381 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
382 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
383 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
384 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
385 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
386 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
387 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
388
389 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
390
391
392 /* Config Reply Message */
393 typedef struct _MPI2_CONFIG_REPLY
394 {
395 U8 Action; /* 0x00 */
396 U8 SGLFlags; /* 0x01 */
397 U8 MsgLength; /* 0x02 */
398 U8 Function; /* 0x03 */
399 U16 ExtPageLength; /* 0x04 */
400 U8 ExtPageType; /* 0x06 */
401 U8 MsgFlags; /* 0x07 */
402 U8 VP_ID; /* 0x08 */
403 U8 VF_ID; /* 0x09 */
404 U16 Reserved1; /* 0x0A */
405 U16 Reserved2; /* 0x0C */
406 U16 IOCStatus; /* 0x0E */
407 U32 IOCLogInfo; /* 0x10 */
408 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
409 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
410 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
411
412
413
414 /*****************************************************************************
415 *
416 * C o n f i g u r a t i o n P a g e s
417 *
418 *****************************************************************************/
419
420 /****************************************************************************
421 * Manufacturing Config pages
422 ****************************************************************************/
423
424 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
425
426 /* SAS */
427 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
428 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
429 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
430 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
431 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
432 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
433 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
434
435 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
436
437 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
438 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
439 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
440 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
441 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
442 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
443 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
444 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
445 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
446
447
448
449
450 /* Manufacturing Page 0 */
451
452 typedef struct _MPI2_CONFIG_PAGE_MAN_0
453 {
454 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
455 U8 ChipName[16]; /* 0x04 */
456 U8 ChipRevision[8]; /* 0x14 */
457 U8 BoardName[16]; /* 0x1C */
458 U8 BoardAssembly[16]; /* 0x2C */
459 U8 BoardTracerNumber[16]; /* 0x3C */
460 } MPI2_CONFIG_PAGE_MAN_0,
461 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
462 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
463
464 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
465
466
467 /* Manufacturing Page 1 */
468
469 typedef struct _MPI2_CONFIG_PAGE_MAN_1
470 {
471 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
472 U8 VPD[256]; /* 0x04 */
473 } MPI2_CONFIG_PAGE_MAN_1,
474 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
475 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
476
477 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
478
479
480 typedef struct _MPI2_CHIP_REVISION_ID
481 {
482 U16 DeviceID; /* 0x00 */
483 U8 PCIRevisionID; /* 0x02 */
484 U8 Reserved; /* 0x03 */
485 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
486 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
487
488
489 /* Manufacturing Page 2 */
490
491 /*
492 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
493 * one and check Header.PageLength at runtime.
494 */
495 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
496 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
497 #endif
498
499 typedef struct _MPI2_CONFIG_PAGE_MAN_2
500 {
501 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
502 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
503 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
504 } MPI2_CONFIG_PAGE_MAN_2,
505 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
506 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
507
508 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
509
510
511 /* Manufacturing Page 3 */
512
513 /*
514 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
515 * one and check Header.PageLength at runtime.
516 */
517 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
518 #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
519 #endif
520
521 typedef struct _MPI2_CONFIG_PAGE_MAN_3
522 {
523 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
524 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
525 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
526 } MPI2_CONFIG_PAGE_MAN_3,
527 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
528 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
529
530 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
531
532
533 /* Manufacturing Page 4 */
534
535 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
536 {
537 U8 PowerSaveFlags; /* 0x00 */
538 U8 InternalOperationsSleepTime; /* 0x01 */
539 U8 InternalOperationsRunTime; /* 0x02 */
540 U8 HostIdleTime; /* 0x03 */
541 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
542 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
543 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
544
545 /* defines for the PowerSaveFlags field */
546 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
547 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
548 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
549 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
550
551 typedef struct _MPI2_CONFIG_PAGE_MAN_4
552 {
553 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
554 U32 Reserved1; /* 0x04 */
555 U32 Flags; /* 0x08 */
556 U8 InquirySize; /* 0x0C */
557 U8 Reserved2; /* 0x0D */
558 U16 Reserved3; /* 0x0E */
559 U8 InquiryData[56]; /* 0x10 */
560 U32 RAID0VolumeSettings; /* 0x48 */
561 U32 RAID1EVolumeSettings; /* 0x4C */
562 U32 RAID1VolumeSettings; /* 0x50 */
563 U32 RAID10VolumeSettings; /* 0x54 */
564 U32 Reserved4; /* 0x58 */
565 U32 Reserved5; /* 0x5C */
566 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
567 U8 MaxOCEDisks; /* 0x64 */
568 U8 ResyncRate; /* 0x65 */
569 U16 DataScrubDuration; /* 0x66 */
570 U8 MaxHotSpares; /* 0x68 */
571 U8 MaxPhysDisksPerVol; /* 0x69 */
572 U8 MaxPhysDisks; /* 0x6A */
573 U8 MaxVolumes; /* 0x6B */
574 } MPI2_CONFIG_PAGE_MAN_4,
575 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
576 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
577
578 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
579
580 /* Manufacturing Page 4 Flags field */
581 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
582 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
583
584 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
585 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
586 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
587
588 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
589 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
590 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
591 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
592 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
593
594 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
595 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
596 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
597 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
598
599 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
600 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
601 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
602 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
603 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
604 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
605 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
606 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
607
608
609 /* Manufacturing Page 5 */
610
611 /*
612 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
613 * one and check the value returned for NumPhys at runtime.
614 */
615 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
616 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
617 #endif
618
619 typedef struct _MPI2_MANUFACTURING5_ENTRY
620 {
621 U64 WWID; /* 0x00 */
622 U64 DeviceName; /* 0x08 */
623 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
624 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
625
626 typedef struct _MPI2_CONFIG_PAGE_MAN_5
627 {
628 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
629 U8 NumPhys; /* 0x04 */
630 U8 Reserved1; /* 0x05 */
631 U16 Reserved2; /* 0x06 */
632 U32 Reserved3; /* 0x08 */
633 U32 Reserved4; /* 0x0C */
634 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
635 } MPI2_CONFIG_PAGE_MAN_5,
636 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
637 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
638
639 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
640
641
642 /* Manufacturing Page 6 */
643
644 typedef struct _MPI2_CONFIG_PAGE_MAN_6
645 {
646 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
647 U32 ProductSpecificInfo;/* 0x04 */
648 } MPI2_CONFIG_PAGE_MAN_6,
649 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
650 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
651
652 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
653
654
655 /* Manufacturing Page 7 */
656
657 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
658 {
659 U32 Pinout; /* 0x00 */
660 U8 Connector[16]; /* 0x04 */
661 U8 Location; /* 0x14 */
662 U8 ReceptacleID; /* 0x15 */
663 U16 Slot; /* 0x16 */
664 U32 Reserved2; /* 0x18 */
665 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
666 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
667
668 /* defines for the Pinout field */
669 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
670 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
671
672 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
673 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
674 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
675 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
676 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
677 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
678 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
679 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
680 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
681 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
682 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
683 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
684 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
685 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
686 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
687
688 /* defines for the Location field */
689 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
690 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
691 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
692 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
693 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
694 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
695 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
696
697 /*
698 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
699 * one and check the value returned for NumPhys at runtime.
700 */
701 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
702 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
703 #endif
704
705 typedef struct _MPI2_CONFIG_PAGE_MAN_7
706 {
707 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
708 U32 Reserved1; /* 0x04 */
709 U32 Reserved2; /* 0x08 */
710 U32 Flags; /* 0x0C */
711 U8 EnclosureName[16]; /* 0x10 */
712 U8 NumPhys; /* 0x20 */
713 U8 Reserved3; /* 0x21 */
714 U16 Reserved4; /* 0x22 */
715 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
716 } MPI2_CONFIG_PAGE_MAN_7,
717 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
718 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
719
720 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
721
722 /* defines for the Flags field */
723 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008)
724 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002)
725 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
726
727
728 /*
729 * Generic structure to use for product-specific manufacturing pages
730 * (currently Manufacturing Page 8 through Manufacturing Page 31).
731 */
732
733 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
734 {
735 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
736 U32 ProductSpecificInfo;/* 0x04 */
737 } MPI2_CONFIG_PAGE_MAN_PS,
738 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
739 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
740
741 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
742 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
743 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
744 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
745 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
746 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
747 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
748 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
749 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
750 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
751 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
752 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
753 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
754 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
755 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
756 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
757 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
758 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
759 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
760 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
761 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
762 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
763 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
764 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
765
766
767 /****************************************************************************
768 * IO Unit Config Pages
769 ****************************************************************************/
770
771 /* IO Unit Page 0 */
772
773 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
774 {
775 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
776 U64 UniqueValue; /* 0x04 */
777 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
778 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
779 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
780 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
781
782 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
783
784
785 /* IO Unit Page 1 */
786
787 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
788 {
789 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
790 U32 Flags; /* 0x04 */
791 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
792 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
793
794 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
795
796 /* IO Unit Page 1 Flags defines */
797 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000)
798 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
799 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
800 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
801 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
802 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
803 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
804 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
805 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
806 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
807 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
808
809
810 /* IO Unit Page 3 */
811
812 /*
813 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
814 * one and check the value returned for GPIOCount at runtime.
815 */
816 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
817 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
818 #endif
819
820 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
821 {
822 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
823 U8 GPIOCount; /* 0x04 */
824 U8 Reserved1; /* 0x05 */
825 U16 Reserved2; /* 0x06 */
826 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
827 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
828 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
829
830 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
831
832 /* defines for IO Unit Page 3 GPIOVal field */
833 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
834 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
835 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
836 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
837
838
839 /* IO Unit Page 5 */
840
841 /*
842 * Upper layer code (drivers, utilities, etc.) should leave this define set to
843 * one and check the value returned for NumDmaEngines at runtime.
844 */
845 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
846 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
847 #endif
848
849 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
850 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
851 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
852 U64 RaidAcceleratorBufferSize; /* 0x0C */
853 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
854 U8 RAControlSize; /* 0x1C */
855 U8 NumDmaEngines; /* 0x1D */
856 U8 RAMinControlSize; /* 0x1E */
857 U8 RAMaxControlSize; /* 0x1F */
858 U32 Reserved1; /* 0x20 */
859 U32 Reserved2; /* 0x24 */
860 U32 Reserved3; /* 0x28 */
861 U32 DmaEngineCapabilities
862 [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
863 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
864 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
865
866 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
867
868 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
869 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000)
870 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
871
872 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
873 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
874 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
875 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
876
877
878 /* IO Unit Page 6 */
879
880 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
881 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
882 U16 Flags; /* 0x04 */
883 U8 RAHostControlSize; /* 0x06 */
884 U8 Reserved0; /* 0x07 */
885 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
886 U32 Reserved1; /* 0x10 */
887 U32 Reserved2; /* 0x14 */
888 U32 Reserved3; /* 0x18 */
889 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
890 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
891
892 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
893
894 /* defines for IO Unit Page 6 Flags field */
895 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
896
897
898 /* IO Unit Page 7 */
899
900 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
901 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
902 U16 Reserved1; /* 0x04 */
903 U8 PCIeWidth; /* 0x06 */
904 U8 PCIeSpeed; /* 0x07 */
905 U32 ProcessorState; /* 0x08 */
906 U32 PowerManagementCapabilities; /* 0x0C */
907 U16 IOCTemperature; /* 0x10 */
908 U8 IOCTemperatureUnits; /* 0x12 */
909 U8 IOCSpeed; /* 0x13 */
910 U16 BoardTemperature; /* 0x14 */
911 U8 BoardTemperatureUnits; /* 0x16 */
912 U8 Reserved3; /* 0x17 */
913 U32 Reserved4; /* 0x18 */
914 U32 Reserved5; /* 0x1C */
915 U32 Reserved6; /* 0x20 */
916 U32 Reserved7; /* 0x24 */
917 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
918 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
919
920 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x04)
921
922 /* defines for IO Unit Page 7 PCIeWidth field */
923 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
924 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
925 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
926 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
927
928 /* defines for IO Unit Page 7 PCIeSpeed field */
929 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
930 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
931 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
932
933 /* defines for IO Unit Page 7 ProcessorState field */
934 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
935 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
936
937 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
938 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
939 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
940
941 /* defines for IO Unit Page 7 PowerManagementCapabilities field */
942 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
943 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
944 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
945 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /* obsolete */
946 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /* obsolete */
947
948 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
949 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
950 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
951 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
952
953 /* defines for IO Unit Page 7 IOCSpeed field */
954 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
955 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
956 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
957 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
958
959 /* defines for IO Unit Page 7 BoardTemperatureUnits field */
960 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
961 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
962 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
963
964 /* IO Unit Page 8 */
965
966 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4)
967
968 typedef struct _MPI2_IOUNIT8_SENSOR {
969 U16 Flags; /* 0x00 */
970 U16 Reserved1; /* 0x02 */
971 U16
972 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */
973 U32 Reserved2; /* 0x0C */
974 U32 Reserved3; /* 0x10 */
975 U32 Reserved4; /* 0x14 */
976 } MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR,
977 Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t;
978
979 /* defines for IO Unit Page 8 Sensor Flags field */
980 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
981 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
982 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
983 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
984
985 /*
986 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
987 * one and check the value returned for NumSensors at runtime.
988 */
989 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
990 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1)
991 #endif
992
993 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
994 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
995 U32 Reserved1; /* 0x04 */
996 U32 Reserved2; /* 0x08 */
997 U8 NumSensors; /* 0x0C */
998 U8 PollingInterval; /* 0x0D */
999 U16 Reserved3; /* 0x0E */
1000 MPI2_IOUNIT8_SENSOR
1001 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */
1002 } MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1003 Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t;
1004
1005 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
1006
1007
1008 /* IO Unit Page 9 */
1009
1010 typedef struct _MPI2_IOUNIT9_SENSOR {
1011 U16 CurrentTemperature; /* 0x00 */
1012 U16 Reserved1; /* 0x02 */
1013 U8 Flags; /* 0x04 */
1014 U8 Reserved2; /* 0x05 */
1015 U16 Reserved3; /* 0x06 */
1016 U32 Reserved4; /* 0x08 */
1017 U32 Reserved5; /* 0x0C */
1018 } MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR,
1019 Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t;
1020
1021 /* defines for IO Unit Page 9 Sensor Flags field */
1022 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
1023
1024 /*
1025 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1026 * one and check the value returned for NumSensors at runtime.
1027 */
1028 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1029 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1)
1030 #endif
1031
1032 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1033 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1034 U32 Reserved1; /* 0x04 */
1035 U32 Reserved2; /* 0x08 */
1036 U8 NumSensors; /* 0x0C */
1037 U8 Reserved4; /* 0x0D */
1038 U16 Reserved3; /* 0x0E */
1039 MPI2_IOUNIT9_SENSOR
1040 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */
1041 } MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1042 Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t;
1043
1044 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
1045
1046
1047 /* IO Unit Page 10 */
1048
1049 typedef struct _MPI2_IOUNIT10_FUNCTION {
1050 U8 CreditPercent; /* 0x00 */
1051 U8 Reserved1; /* 0x01 */
1052 U16 Reserved2; /* 0x02 */
1053 } MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION,
1054 Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t;
1055
1056 /*
1057 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1058 * one and check the value returned for NumFunctions at runtime.
1059 */
1060 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1061 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1)
1062 #endif
1063
1064 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1065 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1066 U8 NumFunctions; /* 0x04 */
1067 U8 Reserved1; /* 0x05 */
1068 U16 Reserved2; /* 0x06 */
1069 U32 Reserved3; /* 0x08 */
1070 U32 Reserved4; /* 0x0C */
1071 MPI2_IOUNIT10_FUNCTION
1072 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/* 0x10 */
1073 } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1074 Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t;
1075
1076 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
1077
1078
1079
1080 /****************************************************************************
1081 * IOC Config Pages
1082 ****************************************************************************/
1083
1084 /* IOC Page 0 */
1085
1086 typedef struct _MPI2_CONFIG_PAGE_IOC_0
1087 {
1088 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1089 U32 Reserved1; /* 0x04 */
1090 U32 Reserved2; /* 0x08 */
1091 U16 VendorID; /* 0x0C */
1092 U16 DeviceID; /* 0x0E */
1093 U8 RevisionID; /* 0x10 */
1094 U8 Reserved3; /* 0x11 */
1095 U16 Reserved4; /* 0x12 */
1096 U32 ClassCode; /* 0x14 */
1097 U16 SubsystemVendorID; /* 0x18 */
1098 U16 SubsystemID; /* 0x1A */
1099 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
1100 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
1101
1102 #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
1103
1104
1105 /* IOC Page 1 */
1106
1107 typedef struct _MPI2_CONFIG_PAGE_IOC_1
1108 {
1109 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1110 U32 Flags; /* 0x04 */
1111 U32 CoalescingTimeout; /* 0x08 */
1112 U8 CoalescingDepth; /* 0x0C */
1113 U8 PCISlotNum; /* 0x0D */
1114 U8 PCIBusNum; /* 0x0E */
1115 U8 PCIDomainSegment; /* 0x0F */
1116 U32 Reserved1; /* 0x10 */
1117 U32 Reserved2; /* 0x14 */
1118 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
1119 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
1120
1121 #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1122
1123 /* defines for IOC Page 1 Flags field */
1124 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1125
1126 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1127 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1128 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1129
1130 /* IOC Page 6 */
1131
1132 typedef struct _MPI2_CONFIG_PAGE_IOC_6
1133 {
1134 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1135 U32 CapabilitiesFlags; /* 0x04 */
1136 U8 MaxDrivesRAID0; /* 0x08 */
1137 U8 MaxDrivesRAID1; /* 0x09 */
1138 U8 MaxDrivesRAID1E; /* 0x0A */
1139 U8 MaxDrivesRAID10; /* 0x0B */
1140 U8 MinDrivesRAID0; /* 0x0C */
1141 U8 MinDrivesRAID1; /* 0x0D */
1142 U8 MinDrivesRAID1E; /* 0x0E */
1143 U8 MinDrivesRAID10; /* 0x0F */
1144 U32 Reserved1; /* 0x10 */
1145 U8 MaxGlobalHotSpares; /* 0x14 */
1146 U8 MaxPhysDisks; /* 0x15 */
1147 U8 MaxVolumes; /* 0x16 */
1148 U8 MaxConfigs; /* 0x17 */
1149 U8 MaxOCEDisks; /* 0x18 */
1150 U8 Reserved2; /* 0x19 */
1151 U16 Reserved3; /* 0x1A */
1152 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
1153 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
1154 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
1155 U32 Reserved4; /* 0x28 */
1156 U32 Reserved5; /* 0x2C */
1157 U16 DefaultMetadataSize; /* 0x30 */
1158 U16 Reserved6; /* 0x32 */
1159 U16 MaxBadBlockTableEntries; /* 0x34 */
1160 U16 Reserved7; /* 0x36 */
1161 U32 IRNvsramVersion; /* 0x38 */
1162 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
1163 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
1164
1165 #define MPI2_IOCPAGE6_PAGEVERSION (0x05)
1166
1167 /* defines for IOC Page 6 CapabilitiesFlags */
1168 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020)
1169 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1170 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1171 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1172 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1173 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1174
1175
1176 /* IOC Page 7 */
1177
1178 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1179
1180 typedef struct _MPI2_CONFIG_PAGE_IOC_7
1181 {
1182 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1183 U32 Reserved1; /* 0x04 */
1184 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1185 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
1186 U16 SASNotifyPrimitiveMasks; /* 0x1A */
1187 U32 Reserved3; /* 0x1C */
1188 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1189 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1190
1191 #define MPI2_IOCPAGE7_PAGEVERSION (0x02)
1192
1193
1194 /* IOC Page 8 */
1195
1196 typedef struct _MPI2_CONFIG_PAGE_IOC_8
1197 {
1198 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1199 U8 NumDevsPerEnclosure; /* 0x04 */
1200 U8 Reserved1; /* 0x05 */
1201 U16 Reserved2; /* 0x06 */
1202 U16 MaxPersistentEntries; /* 0x08 */
1203 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
1204 U16 Flags; /* 0x0C */
1205 U16 Reserved3; /* 0x0E */
1206 U16 IRVolumeMappingFlags; /* 0x10 */
1207 U16 Reserved4; /* 0x12 */
1208 U32 Reserved5; /* 0x14 */
1209 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1210 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1211
1212 #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1213
1214 /* defines for IOC Page 8 Flags field */
1215 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1216 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1217
1218 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1219 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1220 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1221
1222 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1223 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1224
1225 /* defines for IOC Page 8 IRVolumeMappingFlags */
1226 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1227 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1228 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1229
1230
1231 /****************************************************************************
1232 * BIOS Config Pages
1233 ****************************************************************************/
1234
1235 /* BIOS Page 1 */
1236
1237 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1238 {
1239 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1240 U32 BiosOptions; /* 0x04 */
1241 U32 IOCSettings; /* 0x08 */
1242 U8 SSUTimeout; /* 0x0C */
1243 U8 Reserved1; /* 0x0D */
1244 U16 Reserved2; /* 0x0E */
1245 U32 DeviceSettings; /* 0x10 */
1246 U16 NumberOfDevices; /* 0x14 */
1247 U16 UEFIVersion; /* 0x16 */
1248 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
1249 U16 IOTimeoutSequential; /* 0x1A */
1250 U16 IOTimeoutOther; /* 0x1C */
1251 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
1252 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1253 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1254
1255 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07)
1256
1257 /* values for BIOS Page 1 BiosOptions field */
1258 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800)
1259 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000)
1260 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800)
1261 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000)
1262 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800)
1263 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000)
1264
1265 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400)
1266
1267 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300)
1268 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000)
1269 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100)
1270 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200)
1271 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300)
1272
1273 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0)
1274 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000)
1275
1276 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006)
1277 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000)
1278 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002)
1279 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004)
1280
1281 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1282
1283 /* values for BIOS Page 1 IOCSettings field */
1284 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1285 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1286 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1287
1288 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1289 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1290 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1291 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1292
1293 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1294 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1295 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1296 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1297 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1298
1299 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1300
1301 /* values for BIOS Page 1 DeviceSettings field */
1302 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1303 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1304 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1305 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1306 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1307
1308 /* defines for BIOS Page 1 UEFIVersion field */
1309 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00)
1310 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8)
1311 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF)
1312 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0)
1313
1314
1315
1316 /* BIOS Page 2 */
1317
1318 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1319 {
1320 U32 Reserved1; /* 0x00 */
1321 U32 Reserved2; /* 0x04 */
1322 U32 Reserved3; /* 0x08 */
1323 U32 Reserved4; /* 0x0C */
1324 U32 Reserved5; /* 0x10 */
1325 U32 Reserved6; /* 0x14 */
1326 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1327 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1328 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1329
1330 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1331 {
1332 U64 SASAddress; /* 0x00 */
1333 U8 LUN[8]; /* 0x08 */
1334 U32 Reserved1; /* 0x10 */
1335 U32 Reserved2; /* 0x14 */
1336 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1337 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1338
1339 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1340 {
1341 U64 EnclosureLogicalID; /* 0x00 */
1342 U32 Reserved1; /* 0x08 */
1343 U32 Reserved2; /* 0x0C */
1344 U16 SlotNumber; /* 0x10 */
1345 U16 Reserved3; /* 0x12 */
1346 U32 Reserved4; /* 0x14 */
1347 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1348 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1349 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1350
1351 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1352 {
1353 U64 DeviceName; /* 0x00 */
1354 U8 LUN[8]; /* 0x08 */
1355 U32 Reserved1; /* 0x10 */
1356 U32 Reserved2; /* 0x14 */
1357 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1358 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1359
1360 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1361 {
1362 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1363 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1364 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1365 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1366 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1367 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1368
1369 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1370 {
1371 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1372 U32 Reserved1; /* 0x04 */
1373 U32 Reserved2; /* 0x08 */
1374 U32 Reserved3; /* 0x0C */
1375 U32 Reserved4; /* 0x10 */
1376 U32 Reserved5; /* 0x14 */
1377 U32 Reserved6; /* 0x18 */
1378 U8 ReqBootDeviceForm; /* 0x1C */
1379 U8 Reserved7; /* 0x1D */
1380 U16 Reserved8; /* 0x1E */
1381 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1382 U8 ReqAltBootDeviceForm; /* 0x38 */
1383 U8 Reserved9; /* 0x39 */
1384 U16 Reserved10; /* 0x3A */
1385 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1386 U8 CurrentBootDeviceForm; /* 0x58 */
1387 U8 Reserved11; /* 0x59 */
1388 U16 Reserved12; /* 0x5A */
1389 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1390 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1391 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1392
1393 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1394
1395 /* values for BIOS Page 2 BootDeviceForm fields */
1396 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1397 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1398 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1399 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1400 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1401
1402
1403 /* BIOS Page 3 */
1404
1405 typedef struct _MPI2_ADAPTER_INFO
1406 {
1407 U8 PciBusNumber; /* 0x00 */
1408 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1409 U16 AdapterFlags; /* 0x02 */
1410 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1411 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1412
1413 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1414 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1415
1416 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1417 {
1418 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1419 U32 GlobalFlags; /* 0x04 */
1420 U32 BiosVersion; /* 0x08 */
1421 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1422 U32 Reserved1; /* 0x1C */
1423 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1424 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1425
1426 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1427
1428 /* values for BIOS Page 3 GlobalFlags */
1429 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1430 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1431 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1432
1433 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1434 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1435 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1436 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1437
1438
1439 /* BIOS Page 4 */
1440
1441 /*
1442 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1443 * one and check the value returned for NumPhys at runtime.
1444 */
1445 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1446 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1447 #endif
1448
1449 typedef struct _MPI2_BIOS4_ENTRY
1450 {
1451 U64 ReassignmentWWID; /* 0x00 */
1452 U64 ReassignmentDeviceName; /* 0x08 */
1453 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1454 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1455
1456 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1457 {
1458 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1459 U8 NumPhys; /* 0x04 */
1460 U8 Reserved1; /* 0x05 */
1461 U16 Reserved2; /* 0x06 */
1462 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1463 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1464 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1465
1466 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1467
1468
1469 /****************************************************************************
1470 * RAID Volume Config Pages
1471 ****************************************************************************/
1472
1473 /* RAID Volume Page 0 */
1474
1475 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1476 {
1477 U8 RAIDSetNum; /* 0x00 */
1478 U8 PhysDiskMap; /* 0x01 */
1479 U8 PhysDiskNum; /* 0x02 */
1480 U8 Reserved; /* 0x03 */
1481 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1482 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1483
1484 /* defines for the PhysDiskMap field */
1485 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1486 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1487
1488 typedef struct _MPI2_RAIDVOL0_SETTINGS
1489 {
1490 U16 Settings; /* 0x00 */
1491 U8 HotSparePool; /* 0x01 */
1492 U8 Reserved; /* 0x02 */
1493 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1494 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1495
1496 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1497 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1498 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1499 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1500 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1501 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1502 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1503 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1504 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1505
1506 /* RAID Volume Page 0 VolumeSettings defines */
1507 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1508 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1509
1510 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1511 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1512 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1513 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1514
1515 /*
1516 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1517 * one and check the value returned for NumPhysDisks at runtime.
1518 */
1519 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1520 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1521 #endif
1522
1523 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1524 {
1525 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1526 U16 DevHandle; /* 0x04 */
1527 U8 VolumeState; /* 0x06 */
1528 U8 VolumeType; /* 0x07 */
1529 U32 VolumeStatusFlags; /* 0x08 */
1530 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1531 U64 MaxLBA; /* 0x10 */
1532 U32 StripeSize; /* 0x18 */
1533 U16 BlockSize; /* 0x1C */
1534 U16 Reserved1; /* 0x1E */
1535 U8 SupportedPhysDisks; /* 0x20 */
1536 U8 ResyncRate; /* 0x21 */
1537 U16 DataScrubDuration; /* 0x22 */
1538 U8 NumPhysDisks; /* 0x24 */
1539 U8 Reserved2; /* 0x25 */
1540 U8 Reserved3; /* 0x26 */
1541 U8 InactiveStatus; /* 0x27 */
1542 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1543 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1544 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1545
1546 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1547
1548 /* values for RAID VolumeState */
1549 #define MPI2_RAID_VOL_STATE_MISSING (0x00)
1550 #define MPI2_RAID_VOL_STATE_FAILED (0x01)
1551 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1552 #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1553 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1554 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1555
1556 /* values for RAID VolumeType */
1557 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1558 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1559 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1560 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1561 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1562
1563 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1564 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1565 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1566 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1567 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1568 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1569 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1570 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1571 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1572 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1573 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1574 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1575 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1576 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1577 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1578 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1579 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1580 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1581 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1582 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1583
1584 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1585 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1586 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1587 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1588 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1589
1590 /* values for RAID Volume Page 0 InactiveStatus field */
1591 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1592 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1593 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1594 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1595 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1596 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1597 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1598
1599
1600 /* RAID Volume Page 1 */
1601
1602 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1603 {
1604 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1605 U16 DevHandle; /* 0x04 */
1606 U16 Reserved0; /* 0x06 */
1607 U8 GUID[24]; /* 0x08 */
1608 U8 Name[16]; /* 0x20 */
1609 U64 WWID; /* 0x30 */
1610 U32 Reserved1; /* 0x38 */
1611 U32 Reserved2; /* 0x3C */
1612 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1613 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1614
1615 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1616
1617
1618 /****************************************************************************
1619 * RAID Physical Disk Config Pages
1620 ****************************************************************************/
1621
1622 /* RAID Physical Disk Page 0 */
1623
1624 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1625 {
1626 U16 Reserved1; /* 0x00 */
1627 U8 HotSparePool; /* 0x02 */
1628 U8 Reserved2; /* 0x03 */
1629 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1630 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1631
1632 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1633
1634 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1635 {
1636 U8 VendorID[8]; /* 0x00 */
1637 U8 ProductID[16]; /* 0x08 */
1638 U8 ProductRevLevel[4]; /* 0x18 */
1639 U8 SerialNum[32]; /* 0x1C */
1640 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1641 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1642 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1643
1644 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1645 {
1646 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1647 U16 DevHandle; /* 0x04 */
1648 U8 Reserved1; /* 0x06 */
1649 U8 PhysDiskNum; /* 0x07 */
1650 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1651 U32 Reserved2; /* 0x0C */
1652 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1653 U32 Reserved3; /* 0x4C */
1654 U8 PhysDiskState; /* 0x50 */
1655 U8 OfflineReason; /* 0x51 */
1656 U8 IncompatibleReason; /* 0x52 */
1657 U8 PhysDiskAttributes; /* 0x53 */
1658 U32 PhysDiskStatusFlags; /* 0x54 */
1659 U64 DeviceMaxLBA; /* 0x58 */
1660 U64 HostMaxLBA; /* 0x60 */
1661 U64 CoercedMaxLBA; /* 0x68 */
1662 U16 BlockSize; /* 0x70 */
1663 U16 Reserved5; /* 0x72 */
1664 U32 Reserved6; /* 0x74 */
1665 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1666 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1667 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1668
1669 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1670
1671 /* PhysDiskState defines */
1672 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1673 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1674 #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1675 #define MPI2_RAID_PD_STATE_ONLINE (0x03)
1676 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1677 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1678 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1679 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1680
1681 /* OfflineReason defines */
1682 #define MPI2_PHYSDISK0_ONLINE (0x00)
1683 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1684 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1685 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1686 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1687 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1688 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1689
1690 /* IncompatibleReason defines */
1691 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1692 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1693 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1694 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1695 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1696 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1697 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1698 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1699
1700 /* PhysDiskAttributes defines */
1701 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
1702 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1703 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1704
1705 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1706 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1707 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1708
1709 /* PhysDiskStatusFlags defines */
1710 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1711 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1712 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1713 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1714 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1715 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1716 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1717 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1718
1719
1720 /* RAID Physical Disk Page 1 */
1721
1722 /*
1723 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1724 * one and check the value returned for NumPhysDiskPaths at runtime.
1725 */
1726 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1727 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1728 #endif
1729
1730 typedef struct _MPI2_RAIDPHYSDISK1_PATH
1731 {
1732 U16 DevHandle; /* 0x00 */
1733 U16 Reserved1; /* 0x02 */
1734 U64 WWID; /* 0x04 */
1735 U64 OwnerWWID; /* 0x0C */
1736 U8 OwnerIdentifier; /* 0x14 */
1737 U8 Reserved2; /* 0x15 */
1738 U16 Flags; /* 0x16 */
1739 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1740 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1741
1742 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1743 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1744 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1745 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1746
1747 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1748 {
1749 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1750 U8 NumPhysDiskPaths; /* 0x04 */
1751 U8 PhysDiskNum; /* 0x05 */
1752 U16 Reserved1; /* 0x06 */
1753 U32 Reserved2; /* 0x08 */
1754 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1755 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1756 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1757 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1758
1759 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1760
1761
1762 /****************************************************************************
1763 * values for fields used by several types of SAS Config Pages
1764 ****************************************************************************/
1765
1766 /* values for NegotiatedLinkRates fields */
1767 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1768 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1769 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1770 /* link rates used for Negotiated Physical and Logical Link Rate */
1771 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1772 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1773 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1774 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1775 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1776 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1777 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
1778 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1779 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1780 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1781
1782
1783 /* values for AttachedPhyInfo fields */
1784 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1785 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1786 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1787
1788 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1789 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1790 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1791 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1792 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1793 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1794 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1795 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1796 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1797 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1798
1799
1800 /* values for PhyInfo fields */
1801 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1802
1803 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1804 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
1805 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1806 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1807 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1808
1809 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1810 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1811 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1812 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1813 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1814 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1815
1816 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1817 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1818 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1819 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1820 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1821 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1822 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1823 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1824 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1825 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1826
1827 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1828 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1829 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1830 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1831
1832 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1833 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1834
1835 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1836 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1837 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1838 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1839
1840
1841 /* values for SAS ProgrammedLinkRate fields */
1842 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1843 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1844 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1845 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1846 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1847 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0)
1848 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1849 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1850 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1851 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1852 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1853
1854
1855 /* values for SAS HwLinkRate fields */
1856 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1857 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1858 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1859 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1860 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0)
1861 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1862 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1863 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1864 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1865
1866
1867
1868 /****************************************************************************
1869 * SAS IO Unit Config Pages
1870 ****************************************************************************/
1871
1872 /* SAS IO Unit Page 0 */
1873
1874 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1875 {
1876 U8 Port; /* 0x00 */
1877 U8 PortFlags; /* 0x01 */
1878 U8 PhyFlags; /* 0x02 */
1879 U8 NegotiatedLinkRate; /* 0x03 */
1880 U32 ControllerPhyDeviceInfo;/* 0x04 */
1881 U16 AttachedDevHandle; /* 0x08 */
1882 U16 ControllerDevHandle; /* 0x0A */
1883 U32 DiscoveryStatus; /* 0x0C */
1884 U32 Reserved; /* 0x10 */
1885 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1886 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1887
1888 /*
1889 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1890 * one and check the value returned for NumPhys at runtime.
1891 */
1892 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1893 #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1894 #endif
1895
1896 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1897 {
1898 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1899 U32 Reserved1; /* 0x08 */
1900 U8 NumPhys; /* 0x0C */
1901 U8 Reserved2; /* 0x0D */
1902 U16 Reserved3; /* 0x0E */
1903 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1904 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1905 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1906 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1907
1908 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1909
1910 /* values for SAS IO Unit Page 0 PortFlags */
1911 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1912 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1913
1914 /* values for SAS IO Unit Page 0 PhyFlags */
1915 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1916 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1917
1918 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1919
1920 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1921
1922 /* values for SAS IO Unit Page 0 DiscoveryStatus */
1923 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1924 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1925 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1926 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1927 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1928 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1929 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1930 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1931 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1932 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1933 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1934 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1935 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1936 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1937 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1938 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1939 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1940 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1941 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1942 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1943
1944
1945 /* SAS IO Unit Page 1 */
1946
1947 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1948 {
1949 U8 Port; /* 0x00 */
1950 U8 PortFlags; /* 0x01 */
1951 U8 PhyFlags; /* 0x02 */
1952 U8 MaxMinLinkRate; /* 0x03 */
1953 U32 ControllerPhyDeviceInfo; /* 0x04 */
1954 U16 MaxTargetPortConnectTime; /* 0x08 */
1955 U16 Reserved1; /* 0x0A */
1956 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1957 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1958
1959 /*
1960 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1961 * one and check the value returned for NumPhys at runtime.
1962 */
1963 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1964 #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1965 #endif
1966
1967 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1968 {
1969 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1970 U16 ControlFlags; /* 0x08 */
1971 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1972 U16 AdditionalControlFlags; /* 0x0C */
1973 U16 SASWideMaxQueueDepth; /* 0x0E */
1974 U8 NumPhys; /* 0x10 */
1975 U8 SATAMaxQDepth; /* 0x11 */
1976 U8 ReportDeviceMissingDelay; /* 0x12 */
1977 U8 IODeviceMissingDelay; /* 0x13 */
1978 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1979 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
1980 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1981 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1982
1983 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1984
1985 /* values for SAS IO Unit Page 1 ControlFlags */
1986 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1987 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1988 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1989 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1990
1991 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1992 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1993 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1994 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1995 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1996
1997 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1998 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1999 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2000 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2001 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
2002 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2003 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2004 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2005
2006 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
2007 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
2008 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
2009 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
2010 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
2011 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
2012 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
2013 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
2014 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
2015
2016 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2017 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
2018 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
2019
2020 /* values for SAS IO Unit Page 1 PortFlags */
2021 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2022
2023 /* values for SAS IO Unit Page 1 PhyFlags */
2024 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
2025 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
2026
2027 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
2028 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
2029 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
2030 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
2031 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
2032 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
2033 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
2034 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
2035 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
2036
2037 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2038
2039
2040 /* SAS IO Unit Page 4 */
2041
2042 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
2043 {
2044 U8 MaxTargetSpinup; /* 0x00 */
2045 U8 SpinupDelay; /* 0x01 */
2046 U8 SpinupFlags; /* 0x02 */
2047 U8 Reserved1; /* 0x03 */
2048 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2049 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
2050
2051 /* defines for SAS IO Unit Page 4 SpinupFlags */
2052 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01)
2053
2054 /*
2055 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2056 * one and check the value returned for NumPhys at runtime.
2057 */
2058 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2059 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
2060 #endif
2061
2062 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
2063 {
2064 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2065 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
2066 U32 Reserved1; /* 0x18 */
2067 U32 Reserved2; /* 0x1C */
2068 U32 Reserved3; /* 0x20 */
2069 U8 BootDeviceWaitTime; /* 0x24 */
2070 U8 Reserved4; /* 0x25 */
2071 U16 Reserved5; /* 0x26 */
2072 U8 NumPhys; /* 0x28 */
2073 U8 PEInitialSpinupDelay; /* 0x29 */
2074 U8 PEReplyDelay; /* 0x2A */
2075 U8 Flags; /* 0x2B */
2076 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
2077 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
2078 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2079 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
2080
2081 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
2082
2083 /* defines for Flags field */
2084 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
2085
2086 /* defines for PHY field */
2087 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
2088
2089
2090 /* SAS IO Unit Page 5 */
2091
2092 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2093 U8 ControlFlags; /* 0x00 */
2094 U8 PortWidthModGroup; /* 0x01 */
2095 U16 InactivityTimerExponent; /* 0x02 */
2096 U8 SATAPartialTimeout; /* 0x04 */
2097 U8 Reserved2; /* 0x05 */
2098 U8 SATASlumberTimeout; /* 0x06 */
2099 U8 Reserved3; /* 0x07 */
2100 U8 SASPartialTimeout; /* 0x08 */
2101 U8 Reserved4; /* 0x09 */
2102 U8 SASSlumberTimeout; /* 0x0A */
2103 U8 Reserved5; /* 0x0B */
2104 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2105 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2106 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
2107
2108 /* defines for ControlFlags field */
2109 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
2110 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
2111 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
2112 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
2113
2114 /* defines for PortWidthModeGroup field */
2115 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
2116
2117 /* defines for InactivityTimerExponent field */
2118 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
2119 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
2120 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
2121 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
2122 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
2123 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
2124 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
2125 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
2126
2127 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
2128 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
2129 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
2130 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
2131 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
2132 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
2133 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
2134 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
2135
2136 /*
2137 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2138 * one and check the value returned for NumPhys at runtime.
2139 */
2140 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2141 #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
2142 #endif
2143
2144 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2145 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2146 U8 NumPhys; /* 0x08 */
2147 U8 Reserved1; /* 0x09 */
2148 U16 Reserved2; /* 0x0A */
2149 U32 Reserved3; /* 0x0C */
2150 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings
2151 [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
2152 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2153 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2154 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
2155
2156 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2157
2158
2159 /* SAS IO Unit Page 6 */
2160
2161 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2162 U8 CurrentStatus; /* 0x00 */
2163 U8 CurrentModulation; /* 0x01 */
2164 U8 CurrentUtilization; /* 0x02 */
2165 U8 Reserved1; /* 0x03 */
2166 U32 Reserved2; /* 0x04 */
2167 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2168 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2169 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2170 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2171
2172 /* defines for CurrentStatus field */
2173 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2174 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2175 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2176 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2177 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2178 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2179 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2180 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2181
2182 /* defines for CurrentModulation field */
2183 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2184 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2185 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2186 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2187
2188 /*
2189 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2190 * one and check the value returned for NumGroups at runtime.
2191 */
2192 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2193 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2194 #endif
2195
2196 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2197 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2198 U32 Reserved1; /* 0x08 */
2199 U32 Reserved2; /* 0x0C */
2200 U8 NumGroups; /* 0x10 */
2201 U8 Reserved3; /* 0x11 */
2202 U16 Reserved4; /* 0x12 */
2203 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2204 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2205 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2206 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2207 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2208
2209 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2210
2211
2212 /* SAS IO Unit Page 7 */
2213
2214 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2215 U8 Flags; /* 0x00 */
2216 U8 Reserved1; /* 0x01 */
2217 U16 Reserved2; /* 0x02 */
2218 U8 Threshold75Pct; /* 0x04 */
2219 U8 Threshold50Pct; /* 0x05 */
2220 U8 Threshold25Pct; /* 0x06 */
2221 U8 Reserved3; /* 0x07 */
2222 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2223 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2224 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2225 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2226
2227 /* defines for Flags field */
2228 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2229
2230
2231 /*
2232 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2233 * one and check the value returned for NumGroups at runtime.
2234 */
2235 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2236 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2237 #endif
2238
2239 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2240 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2241 U8 SamplingInterval; /* 0x08 */
2242 U8 WindowLength; /* 0x09 */
2243 U16 Reserved1; /* 0x0A */
2244 U32 Reserved2; /* 0x0C */
2245 U32 Reserved3; /* 0x10 */
2246 U8 NumGroups; /* 0x14 */
2247 U8 Reserved4; /* 0x15 */
2248 U16 Reserved5; /* 0x16 */
2249 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2250 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2251 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2252 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2253 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2254
2255 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2256
2257
2258 /* SAS IO Unit Page 8 */
2259
2260 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2261 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2262 U32 Reserved1; /* 0x08 */
2263 U32 PowerManagementCapabilities;/* 0x0C */
2264 U32 Reserved2; /* 0x10 */
2265 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2266 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2267 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2268
2269 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2270
2271 /* defines for PowerManagementCapabilities field */
2272 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
2273 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
2274 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
2275 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
2276 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
2277 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
2278 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
2279 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
2280 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
2281 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
2282
2283
2284
2285 /* SAS IO Unit Page 16 */
2286
2287 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 {
2288 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2289 U64 TimeStamp; /* 0x08 */
2290 U32 Reserved1; /* 0x10 */
2291 U32 Reserved2; /* 0x14 */
2292 U32 FastPathPendedRequests; /* 0x18 */
2293 U32 FastPathUnPendedRequests; /* 0x1C */
2294 U32 FastPathHostRequestStarts; /* 0x20 */
2295 U32 FastPathFirmwareRequestStarts; /* 0x24 */
2296 U32 FastPathHostCompletions; /* 0x28 */
2297 U32 FastPathFirmwareCompletions; /* 0x2C */
2298 U32 NonFastPathRequestStarts; /* 0x30 */
2299 U32 NonFastPathHostCompletions; /* 0x30 */
2300 } MPI2_CONFIG_PAGE_SASIOUNIT16,
2301 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2302 Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t;
2303
2304 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00)
2305
2306
2307 /****************************************************************************
2308 * SAS Expander Config Pages
2309 ****************************************************************************/
2310
2311 /* SAS Expander Page 0 */
2312
2313 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2314 {
2315 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2316 U8 PhysicalPort; /* 0x08 */
2317 U8 ReportGenLength; /* 0x09 */
2318 U16 EnclosureHandle; /* 0x0A */
2319 U64 SASAddress; /* 0x0C */
2320 U32 DiscoveryStatus; /* 0x14 */
2321 U16 DevHandle; /* 0x18 */
2322 U16 ParentDevHandle; /* 0x1A */
2323 U16 ExpanderChangeCount; /* 0x1C */
2324 U16 ExpanderRouteIndexes; /* 0x1E */
2325 U8 NumPhys; /* 0x20 */
2326 U8 SASLevel; /* 0x21 */
2327 U16 Flags; /* 0x22 */
2328 U16 STPBusInactivityTimeLimit; /* 0x24 */
2329 U16 STPMaxConnectTimeLimit; /* 0x26 */
2330 U16 STP_SMP_NexusLossTime; /* 0x28 */
2331 U16 MaxNumRoutedSasAddresses; /* 0x2A */
2332 U64 ActiveZoneManagerSASAddress;/* 0x2C */
2333 U16 ZoneLockInactivityLimit; /* 0x34 */
2334 U16 Reserved1; /* 0x36 */
2335 U8 TimeToReducedFunc; /* 0x38 */
2336 U8 InitialTimeToReducedFunc; /* 0x39 */
2337 U8 MaxReducedFuncTime; /* 0x3A */
2338 U8 Reserved2; /* 0x3B */
2339 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2340 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
2341
2342 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2343
2344 /* values for SAS Expander Page 0 DiscoveryStatus field */
2345 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2346 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2347 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2348 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2349 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2350 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2351 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2352 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2353 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2354 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2355 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2356 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2357 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2358 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2359 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2360 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2361 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2362 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2363 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2364 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2365
2366 /* values for SAS Expander Page 0 Flags field */
2367 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2368 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2369 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2370 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2371 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2372 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2373 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2374 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2375 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2376 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2377 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2378
2379
2380 /* SAS Expander Page 1 */
2381
2382 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2383 {
2384 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2385 U8 PhysicalPort; /* 0x08 */
2386 U8 Reserved1; /* 0x09 */
2387 U16 Reserved2; /* 0x0A */
2388 U8 NumPhys; /* 0x0C */
2389 U8 Phy; /* 0x0D */
2390 U16 NumTableEntriesProgrammed; /* 0x0E */
2391 U8 ProgrammedLinkRate; /* 0x10 */
2392 U8 HwLinkRate; /* 0x11 */
2393 U16 AttachedDevHandle; /* 0x12 */
2394 U32 PhyInfo; /* 0x14 */
2395 U32 AttachedDeviceInfo; /* 0x18 */
2396 U16 ExpanderDevHandle; /* 0x1C */
2397 U8 ChangeCount; /* 0x1E */
2398 U8 NegotiatedLinkRate; /* 0x1F */
2399 U8 PhyIdentifier; /* 0x20 */
2400 U8 AttachedPhyIdentifier; /* 0x21 */
2401 U8 Reserved3; /* 0x22 */
2402 U8 DiscoveryInfo; /* 0x23 */
2403 U32 AttachedPhyInfo; /* 0x24 */
2404 U8 ZoneGroup; /* 0x28 */
2405 U8 SelfConfigStatus; /* 0x29 */
2406 U16 Reserved4; /* 0x2A */
2407 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2408 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2409
2410 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2411
2412 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2413
2414 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2415
2416 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2417
2418 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2419
2420 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2421
2422 /* values for SAS Expander Page 1 DiscoveryInfo field */
2423 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2424 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2425 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2426
2427 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2428
2429 /****************************************************************************
2430 * SAS Device Config Pages
2431 ****************************************************************************/
2432
2433 /* SAS Device Page 0 */
2434
2435 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2436 {
2437 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2438 U16 Slot; /* 0x08 */
2439 U16 EnclosureHandle; /* 0x0A */
2440 U64 SASAddress; /* 0x0C */
2441 U16 ParentDevHandle; /* 0x14 */
2442 U8 PhyNum; /* 0x16 */
2443 U8 AccessStatus; /* 0x17 */
2444 U16 DevHandle; /* 0x18 */
2445 U8 AttachedPhyIdentifier; /* 0x1A */
2446 U8 ZoneGroup; /* 0x1B */
2447 U32 DeviceInfo; /* 0x1C */
2448 U16 Flags; /* 0x20 */
2449 U8 PhysicalPort; /* 0x22 */
2450 U8 MaxPortConnections; /* 0x23 */
2451 U64 DeviceName; /* 0x24 */
2452 U8 PortGroups; /* 0x2C */
2453 U8 DmaGroup; /* 0x2D */
2454 U8 ControlGroup; /* 0x2E */
2455 U8 EnclosureLevel; /* 0x2F */
2456 U8 ConnectorName[4]; /* 0x30 */
2457 U32 Reserved3; /* 0x34 */
2458 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2459 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2460
2461 #define MPI2_SASDEVICE0_PAGEVERSION (0x09)
2462
2463 /* values for SAS Device Page 0 AccessStatus field */
2464 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2465 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2466 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2467 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2468 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2469 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2470 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2471 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2472 /* specific values for SATA Init failures */
2473 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2474 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2475 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2476 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2477 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2478 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2479 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2480 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2481 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2482 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2483 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2484
2485 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2486
2487 /* values for SAS Device Page 0 Flags field */
2488 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
2489 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2490 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2491 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2492 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2493 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2494 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2495 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2496 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2497 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2498 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2499 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002)
2500 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2501
2502
2503 /* SAS Device Page 1 */
2504
2505 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2506 {
2507 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2508 U32 Reserved1; /* 0x08 */
2509 U64 SASAddress; /* 0x0C */
2510 U32 Reserved2; /* 0x14 */
2511 U16 DevHandle; /* 0x18 */
2512 U16 Reserved3; /* 0x1A */
2513 U8 InitialRegDeviceFIS[20];/* 0x1C */
2514 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2515 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2516
2517 #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2518
2519
2520 /****************************************************************************
2521 * SAS PHY Config Pages
2522 ****************************************************************************/
2523
2524 /* SAS PHY Page 0 */
2525
2526 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2527 {
2528 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2529 U16 OwnerDevHandle; /* 0x08 */
2530 U16 Reserved1; /* 0x0A */
2531 U16 AttachedDevHandle; /* 0x0C */
2532 U8 AttachedPhyIdentifier; /* 0x0E */
2533 U8 Reserved2; /* 0x0F */
2534 U32 AttachedPhyInfo; /* 0x10 */
2535 U8 ProgrammedLinkRate; /* 0x14 */
2536 U8 HwLinkRate; /* 0x15 */
2537 U8 ChangeCount; /* 0x16 */
2538 U8 Flags; /* 0x17 */
2539 U32 PhyInfo; /* 0x18 */
2540 U8 NegotiatedLinkRate; /* 0x1C */
2541 U8 Reserved3; /* 0x1D */
2542 U16 Reserved4; /* 0x1E */
2543 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2544 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2545
2546 #define MPI2_SASPHY0_PAGEVERSION (0x03)
2547
2548 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2549
2550 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2551
2552 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2553
2554 /* values for SAS PHY Page 0 Flags field */
2555 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2556
2557 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2558
2559 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2560
2561
2562 /* SAS PHY Page 1 */
2563
2564 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2565 {
2566 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2567 U32 Reserved1; /* 0x08 */
2568 U32 InvalidDwordCount; /* 0x0C */
2569 U32 RunningDisparityErrorCount; /* 0x10 */
2570 U32 LossDwordSynchCount; /* 0x14 */
2571 U32 PhyResetProblemCount; /* 0x18 */
2572 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2573 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2574
2575 #define MPI2_SASPHY1_PAGEVERSION (0x01)
2576
2577
2578 /* SAS PHY Page 2 */
2579
2580 typedef struct _MPI2_SASPHY2_PHY_EVENT {
2581 U8 PhyEventCode; /* 0x00 */
2582 U8 Reserved1; /* 0x01 */
2583 U16 Reserved2; /* 0x02 */
2584 U32 PhyEventInfo; /* 0x04 */
2585 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2586 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2587
2588 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2589
2590
2591 /*
2592 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2593 * one and check the value returned for NumPhyEvents at runtime.
2594 */
2595 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2596 #define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2597 #endif
2598
2599 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2600 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2601 U32 Reserved1; /* 0x08 */
2602 U8 NumPhyEvents; /* 0x0C */
2603 U8 Reserved2; /* 0x0D */
2604 U16 Reserved3; /* 0x0E */
2605 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX];
2606 /* 0x10 */
2607 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2608 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2609
2610 #define MPI2_SASPHY2_PAGEVERSION (0x00)
2611
2612
2613 /* SAS PHY Page 3 */
2614
2615 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2616 U8 PhyEventCode; /* 0x00 */
2617 U8 Reserved1; /* 0x01 */
2618 U16 Reserved2; /* 0x02 */
2619 U8 CounterType; /* 0x04 */
2620 U8 ThresholdWindow; /* 0x05 */
2621 U8 TimeUnits; /* 0x06 */
2622 U8 Reserved3; /* 0x07 */
2623 U32 EventThreshold; /* 0x08 */
2624 U16 ThresholdFlags; /* 0x0C */
2625 U16 Reserved4; /* 0x0E */
2626 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2627 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2628
2629 /* values for PhyEventCode field */
2630 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2631 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2632 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2633 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2634 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2635 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2636 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2637 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2638 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2639 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2640 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2641 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2642 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2643 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2644 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2645 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2646 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2647 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2648 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2649 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2650 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2651 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2652 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2653 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2654 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2655 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2656 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2657 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2658 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2659 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2660 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2661 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2662 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2663 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2664 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2665 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2666 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2667
2668 /* values for the CounterType field */
2669 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2670 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2671 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2672
2673 /* values for the TimeUnits field */
2674 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2675 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2676 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2677 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2678
2679 /* values for the ThresholdFlags field */
2680 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2681 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2682
2683 /*
2684 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2685 * one and check the value returned for NumPhyEvents at runtime.
2686 */
2687 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2688 #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2689 #endif
2690
2691 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2692 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2693 U32 Reserved1; /* 0x08 */
2694 U8 NumPhyEvents; /* 0x0C */
2695 U8 Reserved2; /* 0x0D */
2696 U16 Reserved3; /* 0x0E */
2697 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig
2698 [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2699 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2700 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2701
2702 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2703
2704
2705 /* SAS PHY Page 4 */
2706
2707 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
2708 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2709 U16 Reserved1; /* 0x08 */
2710 U8 Reserved2; /* 0x0A */
2711 U8 Flags; /* 0x0B */
2712 U8 InitialFrame[28]; /* 0x0C */
2713 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2714 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2715
2716 #define MPI2_SASPHY4_PAGEVERSION (0x00)
2717
2718 /* values for the Flags field */
2719 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2720 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2721
2722
2723
2724
2725 /****************************************************************************
2726 * SAS Port Config Pages
2727 ****************************************************************************/
2728
2729 /* SAS Port Page 0 */
2730
2731 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2732 {
2733 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2734 U8 PortNumber; /* 0x08 */
2735 U8 PhysicalPort; /* 0x09 */
2736 U8 PortWidth; /* 0x0A */
2737 U8 PhysicalPortWidth; /* 0x0B */
2738 U8 ZoneGroup; /* 0x0C */
2739 U8 Reserved1; /* 0x0D */
2740 U16 Reserved2; /* 0x0E */
2741 U64 SASAddress; /* 0x10 */
2742 U32 DeviceInfo; /* 0x18 */
2743 U32 Reserved3; /* 0x1C */
2744 U32 Reserved4; /* 0x20 */
2745 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2746 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2747
2748 #define MPI2_SASPORT0_PAGEVERSION (0x00)
2749
2750 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2751
2752
2753 /****************************************************************************
2754 * SAS Enclosure Config Pages
2755 ****************************************************************************/
2756
2757 /* SAS Enclosure Page 0 */
2758
2759 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2760 {
2761 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2762 U32 Reserved1; /* 0x08 */
2763 U64 EnclosureLogicalID; /* 0x0C */
2764 U16 Flags; /* 0x14 */
2765 U16 EnclosureHandle; /* 0x16 */
2766 U16 NumSlots; /* 0x18 */
2767 U16 StartSlot; /* 0x1A */
2768 U8 Reserved2; /* 0x1C */
2769 U8 EnclosureLevel; /* 0x1D */
2770 U16 SEPDevHandle; /* 0x1E */
2771 U32 Reserved3; /* 0x20 */
2772 U32 Reserved4; /* 0x24 */
2773 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2774 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2775 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2776
2777 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04)
2778
2779 /* values for SAS Enclosure Page 0 Flags field */
2780 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
2781 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2782 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2783 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2784 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2785 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2786 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2787 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2788
2789
2790 /****************************************************************************
2791 * Log Config Page
2792 ****************************************************************************/
2793
2794 /* Log Page 0 */
2795
2796 /*
2797 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2798 * one and check the value returned for NumLogEntries at runtime.
2799 */
2800 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2801 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2802 #endif
2803
2804 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2805
2806 typedef struct _MPI2_LOG_0_ENTRY
2807 {
2808 U64 TimeStamp; /* 0x00 */
2809 U32 Reserved1; /* 0x08 */
2810 U16 LogSequence; /* 0x0C */
2811 U16 LogEntryQualifier; /* 0x0E */
2812 U8 VP_ID; /* 0x10 */
2813 U8 VF_ID; /* 0x11 */
2814 U16 Reserved2; /* 0x12 */
2815 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2816 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2817 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2818
2819 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2820 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2821 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2822 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2823 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2824 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2825
2826 typedef struct _MPI2_CONFIG_PAGE_LOG_0
2827 {
2828 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2829 U32 Reserved1; /* 0x08 */
2830 U32 Reserved2; /* 0x0C */
2831 U16 NumLogEntries; /* 0x10 */
2832 U16 Reserved3; /* 0x12 */
2833 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2834 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2835 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2836
2837 #define MPI2_LOG_0_PAGEVERSION (0x02)
2838
2839
2840 /****************************************************************************
2841 * RAID Config Page
2842 ****************************************************************************/
2843
2844 /* RAID Page 0 */
2845
2846 /*
2847 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2848 * one and check the value returned for NumElements at runtime.
2849 */
2850 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2851 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2852 #endif
2853
2854 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2855 {
2856 U16 ElementFlags; /* 0x00 */
2857 U16 VolDevHandle; /* 0x02 */
2858 U8 HotSparePool; /* 0x04 */
2859 U8 PhysDiskNum; /* 0x05 */
2860 U16 PhysDiskDevHandle; /* 0x06 */
2861 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2862 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2863 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2864
2865 /* values for the ElementFlags field */
2866 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2867 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2868 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2869 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2870 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2871
2872
2873 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2874 {
2875 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2876 U8 NumHotSpares; /* 0x08 */
2877 U8 NumPhysDisks; /* 0x09 */
2878 U8 NumVolumes; /* 0x0A */
2879 U8 ConfigNum; /* 0x0B */
2880 U32 Flags; /* 0x0C */
2881 U8 ConfigGUID[24]; /* 0x10 */
2882 U32 Reserved1; /* 0x28 */
2883 U8 NumElements; /* 0x2C */
2884 U8 Reserved2; /* 0x2D */
2885 U16 Reserved3; /* 0x2E */
2886 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2887 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2888 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2889 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2890
2891 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2892
2893 /* values for RAID Configuration Page 0 Flags field */
2894 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2895
2896
2897 /****************************************************************************
2898 * Driver Persistent Mapping Config Pages
2899 ****************************************************************************/
2900
2901 /* Driver Persistent Mapping Page 0 */
2902
2903 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2904 {
2905 U64 PhysicalIdentifier; /* 0x00 */
2906 U16 MappingInformation; /* 0x08 */
2907 U16 DeviceIndex; /* 0x0A */
2908 U32 PhysicalBitsMapping; /* 0x0C */
2909 U32 Reserved1; /* 0x10 */
2910 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2911 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2912 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2913
2914 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2915 {
2916 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2917 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2918 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2919 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2920 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2921
2922 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2923
2924 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
2925 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2926 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2927 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2928
2929
2930 /****************************************************************************
2931 * Ethernet Config Pages
2932 ****************************************************************************/
2933
2934 /* Ethernet Page 0 */
2935
2936 /* IP address (union of IPv4 and IPv6) */
2937 typedef union _MPI2_ETHERNET_IP_ADDR {
2938 U32 IPv4Addr;
2939 U32 IPv6Addr[4];
2940 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2941 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2942
2943 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
2944
2945 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
2946 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2947 U8 NumInterfaces; /* 0x08 */
2948 U8 Reserved0; /* 0x09 */
2949 U16 Reserved1; /* 0x0A */
2950 U32 Status; /* 0x0C */
2951 U8 MediaState; /* 0x10 */
2952 U8 Reserved2; /* 0x11 */
2953 U16 Reserved3; /* 0x12 */
2954 U8 MacAddress[6]; /* 0x14 */
2955 U8 Reserved4; /* 0x1A */
2956 U8 Reserved5; /* 0x1B */
2957 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
2958 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
2959 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
2960 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
2961 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
2962 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
2963 U8 HostName
2964 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2965 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2966 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2967
2968 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
2969
2970 /* values for Ethernet Page 0 Status field */
2971 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
2972 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
2973 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
2974 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
2975 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
2976 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
2977 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
2978 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
2979 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
2980 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
2981 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
2982 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
2983
2984 /* values for Ethernet Page 0 MediaState field */
2985 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
2986 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
2987 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
2988
2989 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
2990 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
2991 #define MPI2_ETHPG0_MS_10MBIT (0x01)
2992 #define MPI2_ETHPG0_MS_100MBIT (0x02)
2993 #define MPI2_ETHPG0_MS_1GBIT (0x03)
2994
2995
2996 /* Ethernet Page 1 */
2997
2998 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
2999 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3000 U32 Reserved0; /* 0x08 */
3001 U32 Flags; /* 0x0C */
3002 U8 MediaState; /* 0x10 */
3003 U8 Reserved1; /* 0x11 */
3004 U16 Reserved2; /* 0x12 */
3005 U8 MacAddress[6]; /* 0x14 */
3006 U8 Reserved3; /* 0x1A */
3007 U8 Reserved4; /* 0x1B */
3008 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
3009 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
3010 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
3011 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
3012 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
3013 U32 Reserved5; /* 0x6C */
3014 U32 Reserved6; /* 0x70 */
3015 U32 Reserved7; /* 0x74 */
3016 U32 Reserved8; /* 0x78 */
3017 U8 HostName
3018 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
3019 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3020 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
3021
3022 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
3023
3024 /* values for Ethernet Page 1 Flags field */
3025 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
3026 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
3027 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
3028 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
3029 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
3030 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
3031 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
3032 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
3033 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
3034
3035 /* values for Ethernet Page 1 MediaState field */
3036 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
3037 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
3038 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
3039
3040 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
3041 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
3042 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
3043 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
3044 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
3045
3046
3047 /****************************************************************************
3048 * Extended Manufacturing Config Pages
3049 ****************************************************************************/
3050
3051 /*
3052 * Generic structure to use for product-specific extended manufacturing pages
3053 * (currently Extended Manufacturing Page 40 through Extended Manufacturing
3054 * Page 60).
3055 */
3056
3057 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
3058 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3059 U32 ProductSpecificInfo; /* 0x08 */
3060 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
3061 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3062 Mpi2ExtManufacturingPagePS_t,
3063 MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
3064
3065 /* PageVersion should be provided by product-specific code */
3066
3067 #endif
3068
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