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1 /*
2 * Copyright 2000-2015 Avago Technologies. All rights reserved.
3 *
4 *
5 * Name: mpi2_ioc.h
6 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
7 * Creation Date: October 11, 2006
8 *
9 * mpi2_ioc.h Version: 02.00.27
10 *
11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
12 * prefix are for use only on MPI v2.5 products, and must not be used
13 * with MPI v2.0 products. Unless otherwise noted, names beginning with
14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
15 *
16 * Version History
17 * ---------------
18 *
19 * Date Version Description
20 * -------- -------- ------------------------------------------------------
21 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
22 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
23 * MaxTargets.
24 * Added TotalImageSize field to FWDownload Request.
25 * Added reserved words to FWUpload Request.
26 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
27 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
28 * request and replaced it with
29 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
30 * Replaced the MinReplyQueueDepth field of the IOCFacts
31 * reply with MaxReplyDescriptorPostQueueDepth.
32 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
33 * depth for the Reply Descriptor Post Queue.
34 * Added SASAddress field to Initiator Device Table
35 * Overflow Event data.
36 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
37 * for SAS Initiator Device Status Change Event data.
38 * Modified Reason Code defines for SAS Topology Change
39 * List Event data, including adding a bit for PHY Vacant
40 * status, and adding a mask for the Reason Code.
41 * Added define for
42 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
43 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
44 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
45 * the IOCFacts Reply.
46 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
47 * Moved MPI2_VERSION_UNION to mpi2.h.
48 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
49 * instead of enables, and added SASBroadcastPrimitiveMasks
50 * field.
51 * Added Log Entry Added Event and related structure.
52 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
53 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
54 * Added MaxVolumes and MaxPersistentEntries fields to
55 * IOCFacts reply.
56 * Added ProtocalFlags and IOCCapabilities fields to
57 * MPI2_FW_IMAGE_HEADER.
58 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
59 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
60 * a U16 (from a U32).
61 * Removed extra 's' from EventMasks name.
62 * 06-27-08 02.00.08 Fixed an offset in a comment.
63 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
64 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
65 * renamed MinReplyFrameSize to ReplyFrameSize.
66 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
67 * Added two new RAIDOperation values for Integrated RAID
68 * Operations Status Event data.
69 * Added four new IR Configuration Change List Event data
70 * ReasonCode values.
71 * Added two new ReasonCode defines for SAS Device Status
72 * Change Event data.
73 * Added three new DiscoveryStatus bits for the SAS
74 * Discovery event data.
75 * Added Multiplexing Status Change bit to the PhyStatus
76 * field of the SAS Topology Change List event data.
77 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
78 * BootFlags are now product-specific.
79 * Added defines for the indivdual signature bytes
80 * for MPI2_INIT_IMAGE_FOOTER.
81 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
82 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
83 * define.
84 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
85 * define.
86 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
87 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
88 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
89 * Added two new reason codes for SAS Device Status Change
90 * Event.
91 * Added new event: SAS PHY Counter.
92 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
93 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
94 * Added new product id family for 2208.
95 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
96 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
97 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
98 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
99 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
100 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
101 * Added Host Based Discovery Phy Event data.
102 * Added defines for ProductID Product field
103 * (MPI2_FW_HEADER_PID_).
104 * Modified values for SAS ProductID Family
105 * (MPI2_FW_HEADER_PID_FAMILY_).
106 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
107 * Added PowerManagementControl Request structures and
108 * defines.
109 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
110 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
111 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
112 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added
113 * SASNotifyPrimitiveMasks field to
114 * MPI2_EVENT_NOTIFICATION_REQUEST.
115 * Added Temperature Threshold Event.
116 * Added Host Message Event.
117 * Added Send Host Message request and reply.
118 * 05-25-11 02.00.18 For Extended Image Header, added
119 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
120 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
121 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
122 * 08-24-11 02.00.19 Added PhysicalPort field to
123 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
124 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
125 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5.
126 * 03-29-12 02.00.21 Added a product specific range to event values.
127 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
128 * Added ElapsedSeconds field to
129 * MPI2_EVENT_DATA_IR_OPERATION_STATUS.
130 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
131 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
132 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
133 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
134 * Added Encrypted Hash Extended Image.
135 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS.
136 * 11-18-14 02.00.25 Updated copyright information.
137 * 03-16-15 02.00.26 Updated for MPI v2.6.
138 * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and
139 * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT.
140 * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and
141 * MPI26_FW_HEADER_PID_FAMILY_3516_SAS.
142 * Added MPI26_CTRL_OP_SHUTDOWN.
143 * 08-25-15 02.00.27 Added IC ARCH Class based signature defines
144 * --------------------------------------------------------------------------
145 */
146
147 #ifndef MPI2_IOC_H
148 #define MPI2_IOC_H
149
150 /*****************************************************************************
151 *
152 * IOC Messages
153 *
154 *****************************************************************************/
155
156 /****************************************************************************
157 * IOCInit message
158 ****************************************************************************/
159
160 /*IOCInit Request message */
161 typedef struct _MPI2_IOC_INIT_REQUEST {
162 U8 WhoInit; /*0x00 */
163 U8 Reserved1; /*0x01 */
164 U8 ChainOffset; /*0x02 */
165 U8 Function; /*0x03 */
166 U16 Reserved2; /*0x04 */
167 U8 Reserved3; /*0x06 */
168 U8 MsgFlags; /*0x07 */
169 U8 VP_ID; /*0x08 */
170 U8 VF_ID; /*0x09 */
171 U16 Reserved4; /*0x0A */
172 U16 MsgVersion; /*0x0C */
173 U16 HeaderVersion; /*0x0E */
174 U32 Reserved5; /*0x10 */
175 U16 ConfigurationFlags; /* 0x14 */
176 U8 HostPageSize; /*0x16 */
177 U8 HostMSIxVectors; /*0x17 */
178 U16 Reserved8; /*0x18 */
179 U16 SystemRequestFrameSize; /*0x1A */
180 U16 ReplyDescriptorPostQueueDepth; /*0x1C */
181 U16 ReplyFreeQueueDepth; /*0x1E */
182 U32 SenseBufferAddressHigh; /*0x20 */
183 U32 SystemReplyAddressHigh; /*0x24 */
184 U64 SystemRequestFrameBaseAddress; /*0x28 */
185 U64 ReplyDescriptorPostQueueAddress; /*0x30 */
186 U64 ReplyFreeQueueAddress; /*0x38 */
187 U64 TimeStamp; /*0x40 */
188 } MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST,
189 Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t;
190
191 /*WhoInit values */
192 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
193 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
194 #define MPI2_WHOINIT_ROM_BIOS (0x02)
195 #define MPI2_WHOINIT_PCI_PEER (0x03)
196 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
197 #define MPI2_WHOINIT_MANUFACTURER (0x05)
198
199 /* MsgFlags */
200 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
201
202
203 /*MsgVersion */
204 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
205 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
206 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
207 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
208
209 /*HeaderVersion */
210 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
211 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
212 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
213 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
214
215 /*minimum depth for a Reply Descriptor Post Queue */
216 #define MPI2_RDPQ_DEPTH_MIN (16)
217
218 /* Reply Descriptor Post Queue Array Entry */
219 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
220 U64 RDPQBaseAddress; /* 0x00 */
221 U32 Reserved1; /* 0x08 */
222 U32 Reserved2; /* 0x0C */
223 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
224 *PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
225 Mpi2IOCInitRDPQArrayEntry, *pMpi2IOCInitRDPQArrayEntry;
226
227
228 /*IOCInit Reply message */
229 typedef struct _MPI2_IOC_INIT_REPLY {
230 U8 WhoInit; /*0x00 */
231 U8 Reserved1; /*0x01 */
232 U8 MsgLength; /*0x02 */
233 U8 Function; /*0x03 */
234 U16 Reserved2; /*0x04 */
235 U8 Reserved3; /*0x06 */
236 U8 MsgFlags; /*0x07 */
237 U8 VP_ID; /*0x08 */
238 U8 VF_ID; /*0x09 */
239 U16 Reserved4; /*0x0A */
240 U16 Reserved5; /*0x0C */
241 U16 IOCStatus; /*0x0E */
242 U32 IOCLogInfo; /*0x10 */
243 } MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY,
244 Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t;
245
246 /****************************************************************************
247 * IOCFacts message
248 ****************************************************************************/
249
250 /*IOCFacts Request message */
251 typedef struct _MPI2_IOC_FACTS_REQUEST {
252 U16 Reserved1; /*0x00 */
253 U8 ChainOffset; /*0x02 */
254 U8 Function; /*0x03 */
255 U16 Reserved2; /*0x04 */
256 U8 Reserved3; /*0x06 */
257 U8 MsgFlags; /*0x07 */
258 U8 VP_ID; /*0x08 */
259 U8 VF_ID; /*0x09 */
260 U16 Reserved4; /*0x0A */
261 } MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST,
262 Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t;
263
264 /*IOCFacts Reply message */
265 typedef struct _MPI2_IOC_FACTS_REPLY {
266 U16 MsgVersion; /*0x00 */
267 U8 MsgLength; /*0x02 */
268 U8 Function; /*0x03 */
269 U16 HeaderVersion; /*0x04 */
270 U8 IOCNumber; /*0x06 */
271 U8 MsgFlags; /*0x07 */
272 U8 VP_ID; /*0x08 */
273 U8 VF_ID; /*0x09 */
274 U16 Reserved1; /*0x0A */
275 U16 IOCExceptions; /*0x0C */
276 U16 IOCStatus; /*0x0E */
277 U32 IOCLogInfo; /*0x10 */
278 U8 MaxChainDepth; /*0x14 */
279 U8 WhoInit; /*0x15 */
280 U8 NumberOfPorts; /*0x16 */
281 U8 MaxMSIxVectors; /*0x17 */
282 U16 RequestCredit; /*0x18 */
283 U16 ProductID; /*0x1A */
284 U32 IOCCapabilities; /*0x1C */
285 MPI2_VERSION_UNION FWVersion; /*0x20 */
286 U16 IOCRequestFrameSize; /*0x24 */
287 U16 IOCMaxChainSegmentSize; /*0x26 */
288 U16 MaxInitiators; /*0x28 */
289 U16 MaxTargets; /*0x2A */
290 U16 MaxSasExpanders; /*0x2C */
291 U16 MaxEnclosures; /*0x2E */
292 U16 ProtocolFlags; /*0x30 */
293 U16 HighPriorityCredit; /*0x32 */
294 U16 MaxReplyDescriptorPostQueueDepth; /*0x34 */
295 U8 ReplyFrameSize; /*0x36 */
296 U8 MaxVolumes; /*0x37 */
297 U16 MaxDevHandle; /*0x38 */
298 U16 MaxPersistentEntries; /*0x3A */
299 U16 MinDevHandle; /*0x3C */
300 U8 CurrentHostPageSize; /* 0x3E */
301 U8 Reserved4; /* 0x3F */
302 } MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY,
303 Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t;
304
305 /*MsgVersion */
306 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
307 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
308 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
309 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
310
311 /*HeaderVersion */
312 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
313 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
314 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
315 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
316
317 /*IOCExceptions */
318 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200)
319 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
320
321 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
322 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
323 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
324 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
325 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
326
327 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
328 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
329 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
330 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
331 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
332
333 /*defines for WhoInit field are after the IOCInit Request */
334
335 /*ProductID field uses MPI2_FW_HEADER_PID_ */
336
337 /*IOCCapabilities */
338 #define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000)
339 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000)
340 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000)
341 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
342 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
343 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
344 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
345 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
346 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
347 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
348 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
349 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
350 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
351 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
352 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
353 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
354
355 /*ProtocolFlags */
356 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
357 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
358
359 /****************************************************************************
360 * PortFacts message
361 ****************************************************************************/
362
363 /*PortFacts Request message */
364 typedef struct _MPI2_PORT_FACTS_REQUEST {
365 U16 Reserved1; /*0x00 */
366 U8 ChainOffset; /*0x02 */
367 U8 Function; /*0x03 */
368 U16 Reserved2; /*0x04 */
369 U8 PortNumber; /*0x06 */
370 U8 MsgFlags; /*0x07 */
371 U8 VP_ID; /*0x08 */
372 U8 VF_ID; /*0x09 */
373 U16 Reserved3; /*0x0A */
374 } MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST,
375 Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t;
376
377 /*PortFacts Reply message */
378 typedef struct _MPI2_PORT_FACTS_REPLY {
379 U16 Reserved1; /*0x00 */
380 U8 MsgLength; /*0x02 */
381 U8 Function; /*0x03 */
382 U16 Reserved2; /*0x04 */
383 U8 PortNumber; /*0x06 */
384 U8 MsgFlags; /*0x07 */
385 U8 VP_ID; /*0x08 */
386 U8 VF_ID; /*0x09 */
387 U16 Reserved3; /*0x0A */
388 U16 Reserved4; /*0x0C */
389 U16 IOCStatus; /*0x0E */
390 U32 IOCLogInfo; /*0x10 */
391 U8 Reserved5; /*0x14 */
392 U8 PortType; /*0x15 */
393 U16 Reserved6; /*0x16 */
394 U16 MaxPostedCmdBuffers; /*0x18 */
395 U16 Reserved7; /*0x1A */
396 } MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY,
397 Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t;
398
399 /*PortType values */
400 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
401 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
402 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
403 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
404 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
405
406 /****************************************************************************
407 * PortEnable message
408 ****************************************************************************/
409
410 /*PortEnable Request message */
411 typedef struct _MPI2_PORT_ENABLE_REQUEST {
412 U16 Reserved1; /*0x00 */
413 U8 ChainOffset; /*0x02 */
414 U8 Function; /*0x03 */
415 U8 Reserved2; /*0x04 */
416 U8 PortFlags; /*0x05 */
417 U8 Reserved3; /*0x06 */
418 U8 MsgFlags; /*0x07 */
419 U8 VP_ID; /*0x08 */
420 U8 VF_ID; /*0x09 */
421 U16 Reserved4; /*0x0A */
422 } MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST,
423 Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t;
424
425 /*PortEnable Reply message */
426 typedef struct _MPI2_PORT_ENABLE_REPLY {
427 U16 Reserved1; /*0x00 */
428 U8 MsgLength; /*0x02 */
429 U8 Function; /*0x03 */
430 U8 Reserved2; /*0x04 */
431 U8 PortFlags; /*0x05 */
432 U8 Reserved3; /*0x06 */
433 U8 MsgFlags; /*0x07 */
434 U8 VP_ID; /*0x08 */
435 U8 VF_ID; /*0x09 */
436 U16 Reserved4; /*0x0A */
437 U16 Reserved5; /*0x0C */
438 U16 IOCStatus; /*0x0E */
439 U32 IOCLogInfo; /*0x10 */
440 } MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY,
441 Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t;
442
443 /****************************************************************************
444 * EventNotification message
445 ****************************************************************************/
446
447 /*EventNotification Request message */
448 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
449
450 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST {
451 U16 Reserved1; /*0x00 */
452 U8 ChainOffset; /*0x02 */
453 U8 Function; /*0x03 */
454 U16 Reserved2; /*0x04 */
455 U8 Reserved3; /*0x06 */
456 U8 MsgFlags; /*0x07 */
457 U8 VP_ID; /*0x08 */
458 U8 VF_ID; /*0x09 */
459 U16 Reserved4; /*0x0A */
460 U32 Reserved5; /*0x0C */
461 U32 Reserved6; /*0x10 */
462 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; /*0x14 */
463 U16 SASBroadcastPrimitiveMasks; /*0x24 */
464 U16 SASNotifyPrimitiveMasks; /*0x26 */
465 U32 Reserved8; /*0x28 */
466 } MPI2_EVENT_NOTIFICATION_REQUEST,
467 *PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
468 Mpi2EventNotificationRequest_t,
469 *pMpi2EventNotificationRequest_t;
470
471 /*EventNotification Reply message */
472 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {
473 U16 EventDataLength; /*0x00 */
474 U8 MsgLength; /*0x02 */
475 U8 Function; /*0x03 */
476 U16 Reserved1; /*0x04 */
477 U8 AckRequired; /*0x06 */
478 U8 MsgFlags; /*0x07 */
479 U8 VP_ID; /*0x08 */
480 U8 VF_ID; /*0x09 */
481 U16 Reserved2; /*0x0A */
482 U16 Reserved3; /*0x0C */
483 U16 IOCStatus; /*0x0E */
484 U32 IOCLogInfo; /*0x10 */
485 U16 Event; /*0x14 */
486 U16 Reserved4; /*0x16 */
487 U32 EventContext; /*0x18 */
488 U32 EventData[1]; /*0x1C */
489 } MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY,
490 Mpi2EventNotificationReply_t,
491 *pMpi2EventNotificationReply_t;
492
493 /*AckRequired */
494 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
495 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
496
497 /*Event */
498 #define MPI2_EVENT_LOG_DATA (0x0001)
499 #define MPI2_EVENT_STATE_CHANGE (0x0002)
500 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
501 #define MPI2_EVENT_EVENT_CHANGE (0x000A)
502 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /*obsolete */
503 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
504 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
505 #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
506 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
507 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
508 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
509 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
510 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
511 #define MPI2_EVENT_IR_VOLUME (0x001E)
512 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
513 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
514 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
515 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
516 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
517 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
518 #define MPI2_EVENT_SAS_QUIESCE (0x0025)
519 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
520 #define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
521 #define MPI2_EVENT_HOST_MESSAGE (0x0028)
522 #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029)
523 #define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034)
524 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
525 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
526
527 /*Log Entry Added Event data */
528
529 /*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
530 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
531
532 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED {
533 U64 TimeStamp; /*0x00 */
534 U32 Reserved1; /*0x08 */
535 U16 LogSequence; /*0x0C */
536 U16 LogEntryQualifier; /*0x0E */
537 U8 VP_ID; /*0x10 */
538 U8 VF_ID; /*0x11 */
539 U16 Reserved2; /*0x12 */
540 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH]; /*0x14 */
541 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
542 *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
543 Mpi2EventDataLogEntryAdded_t,
544 *pMpi2EventDataLogEntryAdded_t;
545
546 /*GPIO Interrupt Event data */
547
548 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
549 U8 GPIONum; /*0x00 */
550 U8 Reserved1; /*0x01 */
551 U16 Reserved2; /*0x02 */
552 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
553 *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
554 Mpi2EventDataGpioInterrupt_t,
555 *pMpi2EventDataGpioInterrupt_t;
556
557 /*Temperature Threshold Event data */
558
559 typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
560 U16 Status; /*0x00 */
561 U8 SensorNum; /*0x02 */
562 U8 Reserved1; /*0x03 */
563 U16 CurrentTemperature; /*0x04 */
564 U16 Reserved2; /*0x06 */
565 U32 Reserved3; /*0x08 */
566 U32 Reserved4; /*0x0C */
567 } MPI2_EVENT_DATA_TEMPERATURE,
568 *PTR_MPI2_EVENT_DATA_TEMPERATURE,
569 Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t;
570
571 /*Temperature Threshold Event data Status bits */
572 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008)
573 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004)
574 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002)
575 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001)
576
577 /*Host Message Event data */
578
579 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
580 U8 SourceVF_ID; /*0x00 */
581 U8 Reserved1; /*0x01 */
582 U16 Reserved2; /*0x02 */
583 U32 Reserved3; /*0x04 */
584 U32 HostData[1]; /*0x08 */
585 } MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
586 Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t;
587
588 /*Power Performance Change Event data */
589
590 typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE {
591 U8 CurrentPowerMode; /*0x00 */
592 U8 PreviousPowerMode; /*0x01 */
593 U16 Reserved1; /*0x02 */
594 } MPI2_EVENT_DATA_POWER_PERF_CHANGE,
595 *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
596 Mpi2EventDataPowerPerfChange_t,
597 *pMpi2EventDataPowerPerfChange_t;
598
599 /*defines for CurrentPowerMode and PreviousPowerMode fields */
600 #define MPI2_EVENT_PM_INIT_MASK (0xC0)
601 #define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00)
602 #define MPI2_EVENT_PM_INIT_HOST (0x40)
603 #define MPI2_EVENT_PM_INIT_IO_UNIT (0x80)
604 #define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0)
605
606 #define MPI2_EVENT_PM_MODE_MASK (0x07)
607 #define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00)
608 #define MPI2_EVENT_PM_MODE_UNKNOWN (0x01)
609 #define MPI2_EVENT_PM_MODE_FULL_POWER (0x04)
610 #define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05)
611 #define MPI2_EVENT_PM_MODE_STANDBY (0x06)
612
613 /* Active Cable Exception Event data */
614
615 typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT {
616 U32 ActiveCablePowerRequirement; /* 0x00 */
617 U8 ReasonCode; /* 0x04 */
618 U8 ReceptacleID; /* 0x05 */
619 U16 Reserved1; /* 0x06 */
620 } MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
621 *PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
622 Mpi26EventDataActiveCableExcept_t,
623 *pMpi26EventDataActiveCableExcept_t;
624
625 /* defines for ReasonCode field */
626 #define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
627 #define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01)
628 #define MPI26_EVENT_ACTIVE_CABLE_DEGRADED (0x02)
629
630 /*Hard Reset Received Event data */
631
632 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED {
633 U8 Reserved1; /*0x00 */
634 U8 Port; /*0x01 */
635 U16 Reserved2; /*0x02 */
636 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
637 *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
638 Mpi2EventDataHardResetReceived_t,
639 *pMpi2EventDataHardResetReceived_t;
640
641 /*Task Set Full Event data */
642 /* this event is obsolete */
643
644 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL {
645 U16 DevHandle; /*0x00 */
646 U16 CurrentDepth; /*0x02 */
647 } MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
648 Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t;
649
650 /*SAS Device Status Change Event data */
651
652 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE {
653 U16 TaskTag; /*0x00 */
654 U8 ReasonCode; /*0x02 */
655 U8 PhysicalPort; /*0x03 */
656 U8 ASC; /*0x04 */
657 U8 ASCQ; /*0x05 */
658 U16 DevHandle; /*0x06 */
659 U32 Reserved2; /*0x08 */
660 U64 SASAddress; /*0x0C */
661 U8 LUN[8]; /*0x14 */
662 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
663 *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
664 Mpi2EventDataSasDeviceStatusChange_t,
665 *pMpi2EventDataSasDeviceStatusChange_t;
666
667 /*SAS Device Status Change Event data ReasonCode values */
668 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
669 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
670 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
671 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
672 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
673 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
674 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
675 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
676 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
677 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
678 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
679 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
680 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
681
682 /*Integrated RAID Operation Status Event data */
683
684 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS {
685 U16 VolDevHandle; /*0x00 */
686 U16 Reserved1; /*0x02 */
687 U8 RAIDOperation; /*0x04 */
688 U8 PercentComplete; /*0x05 */
689 U16 Reserved2; /*0x06 */
690 U32 ElapsedSeconds; /*0x08 */
691 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
692 *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
693 Mpi2EventDataIrOperationStatus_t,
694 *pMpi2EventDataIrOperationStatus_t;
695
696 /*Integrated RAID Operation Status Event data RAIDOperation values */
697 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
698 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
699 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
700 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
701 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
702
703 /*Integrated RAID Volume Event data */
704
705 typedef struct _MPI2_EVENT_DATA_IR_VOLUME {
706 U16 VolDevHandle; /*0x00 */
707 U8 ReasonCode; /*0x02 */
708 U8 Reserved1; /*0x03 */
709 U32 NewValue; /*0x04 */
710 U32 PreviousValue; /*0x08 */
711 } MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME,
712 Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t;
713
714 /*Integrated RAID Volume Event data ReasonCode values */
715 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
716 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
717 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
718
719 /*Integrated RAID Physical Disk Event data */
720
721 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK {
722 U16 Reserved1; /*0x00 */
723 U8 ReasonCode; /*0x02 */
724 U8 PhysDiskNum; /*0x03 */
725 U16 PhysDiskDevHandle; /*0x04 */
726 U16 Reserved2; /*0x06 */
727 U16 Slot; /*0x08 */
728 U16 EnclosureHandle; /*0x0A */
729 U32 NewValue; /*0x0C */
730 U32 PreviousValue; /*0x10 */
731 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
732 *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
733 Mpi2EventDataIrPhysicalDisk_t,
734 *pMpi2EventDataIrPhysicalDisk_t;
735
736 /*Integrated RAID Physical Disk Event data ReasonCode values */
737 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
738 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
739 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
740
741 /*Integrated RAID Configuration Change List Event data */
742
743 /*
744 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
745 *one and check NumElements at runtime.
746 */
747 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
748 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
749 #endif
750
751 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT {
752 U16 ElementFlags; /*0x00 */
753 U16 VolDevHandle; /*0x02 */
754 U8 ReasonCode; /*0x04 */
755 U8 PhysDiskNum; /*0x05 */
756 U16 PhysDiskDevHandle; /*0x06 */
757 } MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
758 Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t;
759
760 /*IR Configuration Change List Event data ElementFlags values */
761 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
762 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
763 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
764 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
765
766 /*IR Configuration Change List Event data ReasonCode values */
767 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
768 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
769 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
770 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
771 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
772 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
773 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
774 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
775 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
776
777 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST {
778 U8 NumElements; /*0x00 */
779 U8 Reserved1; /*0x01 */
780 U8 Reserved2; /*0x02 */
781 U8 ConfigNum; /*0x03 */
782 U32 Flags; /*0x04 */
783 MPI2_EVENT_IR_CONFIG_ELEMENT
784 ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];/*0x08 */
785 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
786 *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
787 Mpi2EventDataIrConfigChangeList_t,
788 *pMpi2EventDataIrConfigChangeList_t;
789
790 /*IR Configuration Change List Event data Flags values */
791 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
792
793 /*SAS Discovery Event data */
794
795 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY {
796 U8 Flags; /*0x00 */
797 U8 ReasonCode; /*0x01 */
798 U8 PhysicalPort; /*0x02 */
799 U8 Reserved1; /*0x03 */
800 U32 DiscoveryStatus; /*0x04 */
801 } MPI2_EVENT_DATA_SAS_DISCOVERY,
802 *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
803 Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t;
804
805 /*SAS Discovery Event data Flags values */
806 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
807 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
808
809 /*SAS Discovery Event data ReasonCode values */
810 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
811 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
812
813 /*SAS Discovery Event data DiscoveryStatus values */
814 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
815 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
816 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
817 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
818 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
819 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
820 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
821 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
822 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
823 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
824 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
825 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
826 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
827 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
828 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
829 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
830 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
831 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
832 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
833 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
834
835 /*SAS Broadcast Primitive Event data */
836
837 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE {
838 U8 PhyNum; /*0x00 */
839 U8 Port; /*0x01 */
840 U8 PortWidth; /*0x02 */
841 U8 Primitive; /*0x03 */
842 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
843 *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
844 Mpi2EventDataSasBroadcastPrimitive_t,
845 *pMpi2EventDataSasBroadcastPrimitive_t;
846
847 /*defines for the Primitive field */
848 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
849 #define MPI2_EVENT_PRIMITIVE_SES (0x02)
850 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
851 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
852 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
853 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
854 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
855 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
856
857 /*SAS Notify Primitive Event data */
858
859 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
860 U8 PhyNum; /*0x00 */
861 U8 Port; /*0x01 */
862 U8 Reserved1; /*0x02 */
863 U8 Primitive; /*0x03 */
864 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
865 *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
866 Mpi2EventDataSasNotifyPrimitive_t,
867 *pMpi2EventDataSasNotifyPrimitive_t;
868
869 /*defines for the Primitive field */
870 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01)
871 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02)
872 #define MPI2_EVENT_NOTIFY_RESERVED1 (0x03)
873 #define MPI2_EVENT_NOTIFY_RESERVED2 (0x04)
874
875 /*SAS Initiator Device Status Change Event data */
876
877 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE {
878 U8 ReasonCode; /*0x00 */
879 U8 PhysicalPort; /*0x01 */
880 U16 DevHandle; /*0x02 */
881 U64 SASAddress; /*0x04 */
882 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
883 *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
884 Mpi2EventDataSasInitDevStatusChange_t,
885 *pMpi2EventDataSasInitDevStatusChange_t;
886
887 /*SAS Initiator Device Status Change event ReasonCode values */
888 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
889 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
890
891 /*SAS Initiator Device Table Overflow Event data */
892
893 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW {
894 U16 MaxInit; /*0x00 */
895 U16 CurrentInit; /*0x02 */
896 U64 SASAddress; /*0x04 */
897 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
898 *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
899 Mpi2EventDataSasInitTableOverflow_t,
900 *pMpi2EventDataSasInitTableOverflow_t;
901
902 /*SAS Topology Change List Event data */
903
904 /*
905 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
906 *one and check NumEntries at runtime.
907 */
908 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
909 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
910 #endif
911
912 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY {
913 U16 AttachedDevHandle; /*0x00 */
914 U8 LinkRate; /*0x02 */
915 U8 PhyStatus; /*0x03 */
916 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
917 Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t;
918
919 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST {
920 U16 EnclosureHandle; /*0x00 */
921 U16 ExpanderDevHandle; /*0x02 */
922 U8 NumPhys; /*0x04 */
923 U8 Reserved1; /*0x05 */
924 U16 Reserved2; /*0x06 */
925 U8 NumEntries; /*0x08 */
926 U8 StartPhyNum; /*0x09 */
927 U8 ExpStatus; /*0x0A */
928 U8 PhysicalPort; /*0x0B */
929 MPI2_EVENT_SAS_TOPO_PHY_ENTRY
930 PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /*0x0C */
931 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
932 *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
933 Mpi2EventDataSasTopologyChangeList_t,
934 *pMpi2EventDataSasTopologyChangeList_t;
935
936 /*values for the ExpStatus field */
937 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
938 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
939 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
940 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
941 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
942
943 /*defines for the LinkRate field */
944 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
945 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
946 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
947 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
948
949 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
950 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
951 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
952 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
953 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
954 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
955 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
956 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
957 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
958 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
959 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B)
960
961 /*values for the PhyStatus field */
962 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
963 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
964 /*values for the PhyStatus ReasonCode sub-field */
965 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
966 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
967 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
968 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
969 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
970 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
971
972 /*SAS Enclosure Device Status Change Event data */
973
974 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE {
975 U16 EnclosureHandle; /*0x00 */
976 U8 ReasonCode; /*0x02 */
977 U8 PhysicalPort; /*0x03 */
978 U64 EnclosureLogicalID; /*0x04 */
979 U16 NumSlots; /*0x0C */
980 U16 StartSlot; /*0x0E */
981 U32 PhyBits; /*0x10 */
982 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
983 *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
984 Mpi2EventDataSasEnclDevStatusChange_t,
985 *pMpi2EventDataSasEnclDevStatusChange_t;
986
987 /*SAS Enclosure Device Status Change event ReasonCode values */
988 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
989 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
990
991 /*SAS PHY Counter Event data */
992
993 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
994 U64 TimeStamp; /*0x00 */
995 U32 Reserved1; /*0x08 */
996 U8 PhyEventCode; /*0x0C */
997 U8 PhyNum; /*0x0D */
998 U16 Reserved2; /*0x0E */
999 U32 PhyEventInfo; /*0x10 */
1000 U8 CounterType; /*0x14 */
1001 U8 ThresholdWindow; /*0x15 */
1002 U8 TimeUnits; /*0x16 */
1003 U8 Reserved3; /*0x17 */
1004 U32 EventThreshold; /*0x18 */
1005 U16 ThresholdFlags; /*0x1C */
1006 U16 Reserved4; /*0x1E */
1007 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1008 *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1009 Mpi2EventDataSasPhyCounter_t,
1010 *pMpi2EventDataSasPhyCounter_t;
1011
1012 /*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h
1013 *for the PhyEventCode field */
1014
1015 /*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h
1016 *for the CounterType field */
1017
1018 /*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h
1019 *for the TimeUnits field */
1020
1021 /*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h
1022 *for the ThresholdFlags field */
1023
1024 /*SAS Quiesce Event data */
1025
1026 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
1027 U8 ReasonCode; /*0x00 */
1028 U8 Reserved1; /*0x01 */
1029 U16 Reserved2; /*0x02 */
1030 U32 Reserved3; /*0x04 */
1031 } MPI2_EVENT_DATA_SAS_QUIESCE,
1032 *PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1033 Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t;
1034
1035 /*SAS Quiesce Event data ReasonCode values */
1036 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
1037 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
1038
1039 /*Host Based Discovery Phy Event data */
1040
1041 typedef struct _MPI2_EVENT_HBD_PHY_SAS {
1042 U8 Flags; /*0x00 */
1043 U8 NegotiatedLinkRate; /*0x01 */
1044 U8 PhyNum; /*0x02 */
1045 U8 PhysicalPort; /*0x03 */
1046 U32 Reserved1; /*0x04 */
1047 U8 InitialFrame[28]; /*0x08 */
1048 } MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS,
1049 Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t;
1050
1051 /*values for the Flags field */
1052 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
1053 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
1054
1055 /*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h
1056 *for the NegotiatedLinkRate field */
1057
1058 typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1059 MPI2_EVENT_HBD_PHY_SAS Sas;
1060 } MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1061 Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t;
1062
1063 typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1064 U8 DescriptorType; /*0x00 */
1065 U8 Reserved1; /*0x01 */
1066 U16 Reserved2; /*0x02 */
1067 U32 Reserved3; /*0x04 */
1068 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /*0x08 */
1069 } MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY,
1070 Mpi2EventDataHbdPhy_t,
1071 *pMpi2EventDataMpi2EventDataHbdPhy_t;
1072
1073 /*values for the DescriptorType field */
1074 #define MPI2_EVENT_HBD_DT_SAS (0x01)
1075
1076 /****************************************************************************
1077 * EventAck message
1078 ****************************************************************************/
1079
1080 /*EventAck Request message */
1081 typedef struct _MPI2_EVENT_ACK_REQUEST {
1082 U16 Reserved1; /*0x00 */
1083 U8 ChainOffset; /*0x02 */
1084 U8 Function; /*0x03 */
1085 U16 Reserved2; /*0x04 */
1086 U8 Reserved3; /*0x06 */
1087 U8 MsgFlags; /*0x07 */
1088 U8 VP_ID; /*0x08 */
1089 U8 VF_ID; /*0x09 */
1090 U16 Reserved4; /*0x0A */
1091 U16 Event; /*0x0C */
1092 U16 Reserved5; /*0x0E */
1093 U32 EventContext; /*0x10 */
1094 } MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST,
1095 Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t;
1096
1097 /*EventAck Reply message */
1098 typedef struct _MPI2_EVENT_ACK_REPLY {
1099 U16 Reserved1; /*0x00 */
1100 U8 MsgLength; /*0x02 */
1101 U8 Function; /*0x03 */
1102 U16 Reserved2; /*0x04 */
1103 U8 Reserved3; /*0x06 */
1104 U8 MsgFlags; /*0x07 */
1105 U8 VP_ID; /*0x08 */
1106 U8 VF_ID; /*0x09 */
1107 U16 Reserved4; /*0x0A */
1108 U16 Reserved5; /*0x0C */
1109 U16 IOCStatus; /*0x0E */
1110 U32 IOCLogInfo; /*0x10 */
1111 } MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY,
1112 Mpi2EventAckReply_t, *pMpi2EventAckReply_t;
1113
1114 /****************************************************************************
1115 * SendHostMessage message
1116 ****************************************************************************/
1117
1118 /*SendHostMessage Request message */
1119 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1120 U16 HostDataLength; /*0x00 */
1121 U8 ChainOffset; /*0x02 */
1122 U8 Function; /*0x03 */
1123 U16 Reserved1; /*0x04 */
1124 U8 Reserved2; /*0x06 */
1125 U8 MsgFlags; /*0x07 */
1126 U8 VP_ID; /*0x08 */
1127 U8 VF_ID; /*0x09 */
1128 U16 Reserved3; /*0x0A */
1129 U8 Reserved4; /*0x0C */
1130 U8 DestVF_ID; /*0x0D */
1131 U16 Reserved5; /*0x0E */
1132 U32 Reserved6; /*0x10 */
1133 U32 Reserved7; /*0x14 */
1134 U32 Reserved8; /*0x18 */
1135 U32 Reserved9; /*0x1C */
1136 U32 Reserved10; /*0x20 */
1137 U32 HostData[1]; /*0x24 */
1138 } MPI2_SEND_HOST_MESSAGE_REQUEST,
1139 *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1140 Mpi2SendHostMessageRequest_t,
1141 *pMpi2SendHostMessageRequest_t;
1142
1143 /*SendHostMessage Reply message */
1144 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1145 U16 HostDataLength; /*0x00 */
1146 U8 MsgLength; /*0x02 */
1147 U8 Function; /*0x03 */
1148 U16 Reserved1; /*0x04 */
1149 U8 Reserved2; /*0x06 */
1150 U8 MsgFlags; /*0x07 */
1151 U8 VP_ID; /*0x08 */
1152 U8 VF_ID; /*0x09 */
1153 U16 Reserved3; /*0x0A */
1154 U16 Reserved4; /*0x0C */
1155 U16 IOCStatus; /*0x0E */
1156 U32 IOCLogInfo; /*0x10 */
1157 } MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1158 Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t;
1159
1160 /****************************************************************************
1161 * FWDownload message
1162 ****************************************************************************/
1163
1164 /*MPI v2.0 FWDownload Request message */
1165 typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
1166 U8 ImageType; /*0x00 */
1167 U8 Reserved1; /*0x01 */
1168 U8 ChainOffset; /*0x02 */
1169 U8 Function; /*0x03 */
1170 U16 Reserved2; /*0x04 */
1171 U8 Reserved3; /*0x06 */
1172 U8 MsgFlags; /*0x07 */
1173 U8 VP_ID; /*0x08 */
1174 U8 VF_ID; /*0x09 */
1175 U16 Reserved4; /*0x0A */
1176 U32 TotalImageSize; /*0x0C */
1177 U32 Reserved5; /*0x10 */
1178 MPI2_MPI_SGE_UNION SGL; /*0x14 */
1179 } MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST,
1180 Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest;
1181
1182 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1183
1184 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1185 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1186 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1187 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1188 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1189 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1190 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1191 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1192 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C)
1193 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1194
1195 /*MPI v2.0 FWDownload TransactionContext Element */
1196 typedef struct _MPI2_FW_DOWNLOAD_TCSGE {
1197 U8 Reserved1; /*0x00 */
1198 U8 ContextSize; /*0x01 */
1199 U8 DetailsLength; /*0x02 */
1200 U8 Flags; /*0x03 */
1201 U32 Reserved2; /*0x04 */
1202 U32 ImageOffset; /*0x08 */
1203 U32 ImageSize; /*0x0C */
1204 } MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE,
1205 Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t;
1206
1207 /*MPI v2.5 FWDownload Request message */
1208 typedef struct _MPI25_FW_DOWNLOAD_REQUEST {
1209 U8 ImageType; /*0x00 */
1210 U8 Reserved1; /*0x01 */
1211 U8 ChainOffset; /*0x02 */
1212 U8 Function; /*0x03 */
1213 U16 Reserved2; /*0x04 */
1214 U8 Reserved3; /*0x06 */
1215 U8 MsgFlags; /*0x07 */
1216 U8 VP_ID; /*0x08 */
1217 U8 VF_ID; /*0x09 */
1218 U16 Reserved4; /*0x0A */
1219 U32 TotalImageSize; /*0x0C */
1220 U32 Reserved5; /*0x10 */
1221 U32 Reserved6; /*0x14 */
1222 U32 ImageOffset; /*0x18 */
1223 U32 ImageSize; /*0x1C */
1224 MPI25_SGE_IO_UNION SGL; /*0x20 */
1225 } MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST,
1226 Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest;
1227
1228 /*FWDownload Reply message */
1229 typedef struct _MPI2_FW_DOWNLOAD_REPLY {
1230 U8 ImageType; /*0x00 */
1231 U8 Reserved1; /*0x01 */
1232 U8 MsgLength; /*0x02 */
1233 U8 Function; /*0x03 */
1234 U16 Reserved2; /*0x04 */
1235 U8 Reserved3; /*0x06 */
1236 U8 MsgFlags; /*0x07 */
1237 U8 VP_ID; /*0x08 */
1238 U8 VF_ID; /*0x09 */
1239 U16 Reserved4; /*0x0A */
1240 U16 Reserved5; /*0x0C */
1241 U16 IOCStatus; /*0x0E */
1242 U32 IOCLogInfo; /*0x10 */
1243 } MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY,
1244 Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t;
1245
1246 /****************************************************************************
1247 * FWUpload message
1248 ****************************************************************************/
1249
1250 /*MPI v2.0 FWUpload Request message */
1251 typedef struct _MPI2_FW_UPLOAD_REQUEST {
1252 U8 ImageType; /*0x00 */
1253 U8 Reserved1; /*0x01 */
1254 U8 ChainOffset; /*0x02 */
1255 U8 Function; /*0x03 */
1256 U16 Reserved2; /*0x04 */
1257 U8 Reserved3; /*0x06 */
1258 U8 MsgFlags; /*0x07 */
1259 U8 VP_ID; /*0x08 */
1260 U8 VF_ID; /*0x09 */
1261 U16 Reserved4; /*0x0A */
1262 U32 Reserved5; /*0x0C */
1263 U32 Reserved6; /*0x10 */
1264 MPI2_MPI_SGE_UNION SGL; /*0x14 */
1265 } MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST,
1266 Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t;
1267
1268 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1269 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1270 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1271 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1272 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1273 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1274 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1275 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1276 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1277 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1278 #define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D)
1279
1280 /*MPI v2.0 FWUpload TransactionContext Element */
1281 typedef struct _MPI2_FW_UPLOAD_TCSGE {
1282 U8 Reserved1; /*0x00 */
1283 U8 ContextSize; /*0x01 */
1284 U8 DetailsLength; /*0x02 */
1285 U8 Flags; /*0x03 */
1286 U32 Reserved2; /*0x04 */
1287 U32 ImageOffset; /*0x08 */
1288 U32 ImageSize; /*0x0C */
1289 } MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE,
1290 Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t;
1291
1292 /*MPI v2.5 FWUpload Request message */
1293 typedef struct _MPI25_FW_UPLOAD_REQUEST {
1294 U8 ImageType; /*0x00 */
1295 U8 Reserved1; /*0x01 */
1296 U8 ChainOffset; /*0x02 */
1297 U8 Function; /*0x03 */
1298 U16 Reserved2; /*0x04 */
1299 U8 Reserved3; /*0x06 */
1300 U8 MsgFlags; /*0x07 */
1301 U8 VP_ID; /*0x08 */
1302 U8 VF_ID; /*0x09 */
1303 U16 Reserved4; /*0x0A */
1304 U32 Reserved5; /*0x0C */
1305 U32 Reserved6; /*0x10 */
1306 U32 Reserved7; /*0x14 */
1307 U32 ImageOffset; /*0x18 */
1308 U32 ImageSize; /*0x1C */
1309 MPI25_SGE_IO_UNION SGL; /*0x20 */
1310 } MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST,
1311 Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t;
1312
1313 /*FWUpload Reply message */
1314 typedef struct _MPI2_FW_UPLOAD_REPLY {
1315 U8 ImageType; /*0x00 */
1316 U8 Reserved1; /*0x01 */
1317 U8 MsgLength; /*0x02 */
1318 U8 Function; /*0x03 */
1319 U16 Reserved2; /*0x04 */
1320 U8 Reserved3; /*0x06 */
1321 U8 MsgFlags; /*0x07 */
1322 U8 VP_ID; /*0x08 */
1323 U8 VF_ID; /*0x09 */
1324 U16 Reserved4; /*0x0A */
1325 U16 Reserved5; /*0x0C */
1326 U16 IOCStatus; /*0x0E */
1327 U32 IOCLogInfo; /*0x10 */
1328 U32 ActualImageSize; /*0x14 */
1329 } MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY,
1330 Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t;
1331
1332 /*FW Image Header */
1333 typedef struct _MPI2_FW_IMAGE_HEADER {
1334 U32 Signature; /*0x00 */
1335 U32 Signature0; /*0x04 */
1336 U32 Signature1; /*0x08 */
1337 U32 Signature2; /*0x0C */
1338 MPI2_VERSION_UNION MPIVersion; /*0x10 */
1339 MPI2_VERSION_UNION FWVersion; /*0x14 */
1340 MPI2_VERSION_UNION NVDATAVersion; /*0x18 */
1341 MPI2_VERSION_UNION PackageVersion; /*0x1C */
1342 U16 VendorID; /*0x20 */
1343 U16 ProductID; /*0x22 */
1344 U16 ProtocolFlags; /*0x24 */
1345 U16 Reserved26; /*0x26 */
1346 U32 IOCCapabilities; /*0x28 */
1347 U32 ImageSize; /*0x2C */
1348 U32 NextImageHeaderOffset; /*0x30 */
1349 U32 Checksum; /*0x34 */
1350 U32 Reserved38; /*0x38 */
1351 U32 Reserved3C; /*0x3C */
1352 U32 Reserved40; /*0x40 */
1353 U32 Reserved44; /*0x44 */
1354 U32 Reserved48; /*0x48 */
1355 U32 Reserved4C; /*0x4C */
1356 U32 Reserved50; /*0x50 */
1357 U32 Reserved54; /*0x54 */
1358 U32 Reserved58; /*0x58 */
1359 U32 Reserved5C; /*0x5C */
1360 U32 BootFlags; /*0x60 */
1361 U32 FirmwareVersionNameWhat; /*0x64 */
1362 U8 FirmwareVersionName[32]; /*0x68 */
1363 U32 VendorNameWhat; /*0x88 */
1364 U8 VendorName[32]; /*0x8C */
1365 U32 PackageNameWhat; /*0x88 */
1366 U8 PackageName[32]; /*0x8C */
1367 U32 ReservedD0; /*0xD0 */
1368 U32 ReservedD4; /*0xD4 */
1369 U32 ReservedD8; /*0xD8 */
1370 U32 ReservedDC; /*0xDC */
1371 U32 ReservedE0; /*0xE0 */
1372 U32 ReservedE4; /*0xE4 */
1373 U32 ReservedE8; /*0xE8 */
1374 U32 ReservedEC; /*0xEC */
1375 U32 ReservedF0; /*0xF0 */
1376 U32 ReservedF4; /*0xF4 */
1377 U32 ReservedF8; /*0xF8 */
1378 U32 ReservedFC; /*0xFC */
1379 } MPI2_FW_IMAGE_HEADER, *PTR_MPI2_FW_IMAGE_HEADER,
1380 Mpi2FWImageHeader_t, *pMpi2FWImageHeader_t;
1381
1382 /*Signature field */
1383 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1384 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1385 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1386 #define MPI26_FW_HEADER_SIGNATURE (0xEB000000)
1387
1388 /*Signature0 field */
1389 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1390 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1391 /* Last byte is defined by architecture */
1392 #define MPI26_FW_HEADER_SIGNATURE0_BASE (0x5AEAA500)
1393 #define MPI26_FW_HEADER_SIGNATURE0_ARC_0 (0x5A)
1394 #define MPI26_FW_HEADER_SIGNATURE0_ARC_1 (0x00)
1395 #define MPI26_FW_HEADER_SIGNATURE0_ARC_2 (0x01)
1396 /* legacy (0x5AEAA55A) */
1397 #define MPI26_FW_HEADER_SIGNATURE0 \
1398 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0)
1399 #define MPI26_FW_HEADER_SIGNATURE0_3516 \
1400 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1)
1401
1402 /*Signature1 field */
1403 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1404 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1405 #define MPI26_FW_HEADER_SIGNATURE1 (0xA55AEAA5)
1406
1407 /*Signature2 field */
1408 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1409 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1410 #define MPI26_FW_HEADER_SIGNATURE2 (0x5AA55AEA)
1411
1412 /*defines for using the ProductID field */
1413 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1414 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1415
1416 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1417 #define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1418 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1419 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1420
1421 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1422 /*SAS ProductID Family bits */
1423 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1424 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1425 #define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021)
1426 #define MPI26_FW_HEADER_PID_FAMILY_3324_SAS (0x0028)
1427 #define MPI26_FW_HEADER_PID_FAMILY_3516_SAS (0x0031)
1428
1429 /*use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1430
1431 /*use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1432
1433 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1434 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1435 #define MPI26_FW_HEADER_BOOTFLAGS_OFFSET (0x60)
1436 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1437
1438 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1439
1440 #define MPI2_FW_HEADER_SIZE (0x100)
1441
1442 /*Extended Image Header */
1443 typedef struct _MPI2_EXT_IMAGE_HEADER {
1444 U8 ImageType; /*0x00 */
1445 U8 Reserved1; /*0x01 */
1446 U16 Reserved2; /*0x02 */
1447 U32 Checksum; /*0x04 */
1448 U32 ImageSize; /*0x08 */
1449 U32 NextImageHeaderOffset; /*0x0C */
1450 U32 PackageVersion; /*0x10 */
1451 U32 Reserved3; /*0x14 */
1452 U32 Reserved4; /*0x18 */
1453 U32 Reserved5; /*0x1C */
1454 U8 IdentifyString[32]; /*0x20 */
1455 } MPI2_EXT_IMAGE_HEADER, *PTR_MPI2_EXT_IMAGE_HEADER,
1456 Mpi2ExtImageHeader_t, *pMpi2ExtImageHeader_t;
1457
1458 /*useful offsets */
1459 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1460 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1461 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1462
1463 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1464
1465 /*defines for the ImageType field */
1466 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1467 #define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1468 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1469 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1470 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1471 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1472 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1473 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1474 #define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09)
1475 #define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80)
1476 #define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF)
1477
1478 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC)
1479
1480 /*FLASH Layout Extended Image Data */
1481
1482 /*
1483 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1484 *one and check RegionsPerLayout at runtime.
1485 */
1486 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1487 #define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1488 #endif
1489
1490 /*
1491 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1492 *one and check NumberOfLayouts at runtime.
1493 */
1494 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1495 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1496 #endif
1497
1498 typedef struct _MPI2_FLASH_REGION {
1499 U8 RegionType; /*0x00 */
1500 U8 Reserved1; /*0x01 */
1501 U16 Reserved2; /*0x02 */
1502 U32 RegionOffset; /*0x04 */
1503 U32 RegionSize; /*0x08 */
1504 U32 Reserved3; /*0x0C */
1505 } MPI2_FLASH_REGION, *PTR_MPI2_FLASH_REGION,
1506 Mpi2FlashRegion_t, *pMpi2FlashRegion_t;
1507
1508 typedef struct _MPI2_FLASH_LAYOUT {
1509 U32 FlashSize; /*0x00 */
1510 U32 Reserved1; /*0x04 */
1511 U32 Reserved2; /*0x08 */
1512 U32 Reserved3; /*0x0C */
1513 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS]; /*0x10 */
1514 } MPI2_FLASH_LAYOUT, *PTR_MPI2_FLASH_LAYOUT,
1515 Mpi2FlashLayout_t, *pMpi2FlashLayout_t;
1516
1517 typedef struct _MPI2_FLASH_LAYOUT_DATA {
1518 U8 ImageRevision; /*0x00 */
1519 U8 Reserved1; /*0x01 */
1520 U8 SizeOfRegion; /*0x02 */
1521 U8 Reserved2; /*0x03 */
1522 U16 NumberOfLayouts; /*0x04 */
1523 U16 RegionsPerLayout; /*0x06 */
1524 U16 MinimumSectorAlignment; /*0x08 */
1525 U16 Reserved3; /*0x0A */
1526 U32 Reserved4; /*0x0C */
1527 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS]; /*0x10 */
1528 } MPI2_FLASH_LAYOUT_DATA, *PTR_MPI2_FLASH_LAYOUT_DATA,
1529 Mpi2FlashLayoutData_t, *pMpi2FlashLayoutData_t;
1530
1531 /*defines for the RegionType field */
1532 #define MPI2_FLASH_REGION_UNUSED (0x00)
1533 #define MPI2_FLASH_REGION_FIRMWARE (0x01)
1534 #define MPI2_FLASH_REGION_BIOS (0x02)
1535 #define MPI2_FLASH_REGION_NVDATA (0x03)
1536 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1537 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1538 #define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1539 #define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1540 #define MPI2_FLASH_REGION_MEGARAID (0x09)
1541 #define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK (0x0A)
1542 #define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK)
1543 #define MPI2_FLASH_REGION_CBB_BACKUP (0x0D)
1544
1545 /*ImageRevision */
1546 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1547
1548 /*Supported Devices Extended Image Data */
1549
1550 /*
1551 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1552 *one and check NumberOfDevices at runtime.
1553 */
1554 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1555 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1556 #endif
1557
1558 typedef struct _MPI2_SUPPORTED_DEVICE {
1559 U16 DeviceID; /*0x00 */
1560 U16 VendorID; /*0x02 */
1561 U16 DeviceIDMask; /*0x04 */
1562 U16 Reserved1; /*0x06 */
1563 U8 LowPCIRev; /*0x08 */
1564 U8 HighPCIRev; /*0x09 */
1565 U16 Reserved2; /*0x0A */
1566 U32 Reserved3; /*0x0C */
1567 } MPI2_SUPPORTED_DEVICE, *PTR_MPI2_SUPPORTED_DEVICE,
1568 Mpi2SupportedDevice_t, *pMpi2SupportedDevice_t;
1569
1570 typedef struct _MPI2_SUPPORTED_DEVICES_DATA {
1571 U8 ImageRevision; /*0x00 */
1572 U8 Reserved1; /*0x01 */
1573 U8 NumberOfDevices; /*0x02 */
1574 U8 Reserved2; /*0x03 */
1575 U32 Reserved3; /*0x04 */
1576 MPI2_SUPPORTED_DEVICE
1577 SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES];/*0x08 */
1578 } MPI2_SUPPORTED_DEVICES_DATA, *PTR_MPI2_SUPPORTED_DEVICES_DATA,
1579 Mpi2SupportedDevicesData_t, *pMpi2SupportedDevicesData_t;
1580
1581 /*ImageRevision */
1582 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1583
1584 /*Init Extended Image Data */
1585
1586 typedef struct _MPI2_INIT_IMAGE_FOOTER {
1587 U32 BootFlags; /*0x00 */
1588 U32 ImageSize; /*0x04 */
1589 U32 Signature0; /*0x08 */
1590 U32 Signature1; /*0x0C */
1591 U32 Signature2; /*0x10 */
1592 U32 ResetVector; /*0x14 */
1593 } MPI2_INIT_IMAGE_FOOTER, *PTR_MPI2_INIT_IMAGE_FOOTER,
1594 Mpi2InitImageFooter_t, *pMpi2InitImageFooter_t;
1595
1596 /*defines for the BootFlags field */
1597 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1598
1599 /*defines for the ImageSize field */
1600 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1601
1602 /*defines for the Signature0 field */
1603 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1604 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1605
1606 /*defines for the Signature1 field */
1607 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1608 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1609
1610 /*defines for the Signature2 field */
1611 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1612 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1613
1614 /*Signature fields as individual bytes */
1615 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1616 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1617 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1618 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1619
1620 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1621 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1622 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1623 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1624
1625 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1626 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1627 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1628 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1629
1630 /*defines for the ResetVector field */
1631 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1632
1633
1634 /* Encrypted Hash Extended Image Data */
1635
1636 typedef struct _MPI25_ENCRYPTED_HASH_ENTRY {
1637 U8 HashImageType; /* 0x00 */
1638 U8 HashAlgorithm; /* 0x01 */
1639 U8 EncryptionAlgorithm; /* 0x02 */
1640 U8 Reserved1; /* 0x03 */
1641 U32 Reserved2; /* 0x04 */
1642 U32 EncryptedHash[1]; /* 0x08 */ /* variable length */
1643 } MPI25_ENCRYPTED_HASH_ENTRY, *PTR_MPI25_ENCRYPTED_HASH_ENTRY,
1644 Mpi25EncryptedHashEntry_t, *pMpi25EncryptedHashEntry_t;
1645
1646 /* values for HashImageType */
1647 #define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00)
1648 #define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01)
1649 #define MPI25_HASH_IMAGE_TYPE_BIOS (0x02)
1650
1651 /* values for HashAlgorithm */
1652 #define MPI25_HASH_ALGORITHM_UNUSED (0x00)
1653 #define MPI25_HASH_ALGORITHM_SHA256 (0x01)
1654
1655 /* values for EncryptionAlgorithm */
1656 #define MPI25_ENCRYPTION_ALG_UNUSED (0x00)
1657 #define MPI25_ENCRYPTION_ALG_RSA256 (0x01)
1658
1659 typedef struct _MPI25_ENCRYPTED_HASH_DATA {
1660 U8 ImageVersion; /* 0x00 */
1661 U8 NumHash; /* 0x01 */
1662 U16 Reserved1; /* 0x02 */
1663 U32 Reserved2; /* 0x04 */
1664 MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /* 0x08 */
1665 } MPI25_ENCRYPTED_HASH_DATA, *PTR_MPI25_ENCRYPTED_HASH_DATA,
1666 Mpi25EncryptedHashData_t, *pMpi25EncryptedHashData_t;
1667
1668
1669 /****************************************************************************
1670 * PowerManagementControl message
1671 ****************************************************************************/
1672
1673 /*PowerManagementControl Request message */
1674 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1675 U8 Feature; /*0x00 */
1676 U8 Reserved1; /*0x01 */
1677 U8 ChainOffset; /*0x02 */
1678 U8 Function; /*0x03 */
1679 U16 Reserved2; /*0x04 */
1680 U8 Reserved3; /*0x06 */
1681 U8 MsgFlags; /*0x07 */
1682 U8 VP_ID; /*0x08 */
1683 U8 VF_ID; /*0x09 */
1684 U16 Reserved4; /*0x0A */
1685 U8 Parameter1; /*0x0C */
1686 U8 Parameter2; /*0x0D */
1687 U8 Parameter3; /*0x0E */
1688 U8 Parameter4; /*0x0F */
1689 U32 Reserved5; /*0x10 */
1690 U32 Reserved6; /*0x14 */
1691 } MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1692 Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t;
1693
1694 /*defines for the Feature field */
1695 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1696 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1697 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /*obsolete */
1698 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1699 #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05)
1700 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1701 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1702
1703 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1704 /*Parameter1 contains a PHY number */
1705 /*Parameter2 indicates power condition action using these defines */
1706 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1707 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1708 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1709 /*Parameter3 and Parameter4 are reserved */
1710
1711 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1712 * Feature */
1713 /*Parameter1 contains SAS port width modulation group number */
1714 /*Parameter2 indicates IOC action using these defines */
1715 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1716 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1717 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1718 /*Parameter3 indicates desired modulation level using these defines */
1719 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1720 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1721 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1722 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1723 /*Parameter4 is reserved */
1724
1725 /*this next set (_PCIE_LINK) is obsolete */
1726 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1727 /*Parameter1 indicates desired PCIe link speed using these defines */
1728 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /*obsolete */
1729 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /*obsolete */
1730 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /*obsolete */
1731 /*Parameter2 indicates desired PCIe link width using these defines */
1732 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /*obsolete */
1733 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /*obsolete */
1734 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /*obsolete */
1735 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /*obsolete */
1736 /*Parameter3 and Parameter4 are reserved */
1737
1738 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1739 /*Parameter1 indicates desired IOC hardware clock speed using these defines */
1740 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
1741 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
1742 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
1743 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
1744 /*Parameter2, Parameter3, and Parameter4 are reserved */
1745
1746 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/
1747 /*Parameter1 indicates host action regarding global power management mode */
1748 #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01)
1749 #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02)
1750 #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03)
1751 /*Parameter2 indicates the requested global power management mode */
1752 #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01)
1753 #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08)
1754 #define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40)
1755 /*Parameter3 and Parameter4 are reserved */
1756
1757 /*PowerManagementControl Reply message */
1758 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1759 U8 Feature; /*0x00 */
1760 U8 Reserved1; /*0x01 */
1761 U8 MsgLength; /*0x02 */
1762 U8 Function; /*0x03 */
1763 U16 Reserved2; /*0x04 */
1764 U8 Reserved3; /*0x06 */
1765 U8 MsgFlags; /*0x07 */
1766 U8 VP_ID; /*0x08 */
1767 U8 VF_ID; /*0x09 */
1768 U16 Reserved4; /*0x0A */
1769 U16 Reserved5; /*0x0C */
1770 U16 IOCStatus; /*0x0E */
1771 U32 IOCLogInfo; /*0x10 */
1772 } MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1773 Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t;
1774
1775 /****************************************************************************
1776 * IO Unit Control messages (MPI v2.6 and later only.)
1777 ****************************************************************************/
1778
1779 /* IO Unit Control Request Message */
1780 typedef struct _MPI26_IOUNIT_CONTROL_REQUEST {
1781 U8 Operation; /* 0x00 */
1782 U8 Reserved1; /* 0x01 */
1783 U8 ChainOffset; /* 0x02 */
1784 U8 Function; /* 0x03 */
1785 U16 DevHandle; /* 0x04 */
1786 U8 IOCParameter; /* 0x06 */
1787 U8 MsgFlags; /* 0x07 */
1788 U8 VP_ID; /* 0x08 */
1789 U8 VF_ID; /* 0x09 */
1790 U16 Reserved3; /* 0x0A */
1791 U16 Reserved4; /* 0x0C */
1792 U8 PhyNum; /* 0x0E */
1793 U8 PrimFlags; /* 0x0F */
1794 U32 Primitive; /* 0x10 */
1795 U8 LookupMethod; /* 0x14 */
1796 U8 Reserved5; /* 0x15 */
1797 U16 SlotNumber; /* 0x16 */
1798 U64 LookupAddress; /* 0x18 */
1799 U32 IOCParameterValue; /* 0x20 */
1800 U32 Reserved7; /* 0x24 */
1801 U32 Reserved8; /* 0x28 */
1802 } MPI26_IOUNIT_CONTROL_REQUEST,
1803 *PTR_MPI26_IOUNIT_CONTROL_REQUEST,
1804 Mpi26IoUnitControlRequest_t,
1805 *pMpi26IoUnitControlRequest_t;
1806
1807 /* values for the Operation field */
1808 #define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02)
1809 #define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06)
1810 #define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07)
1811 #define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08)
1812 #define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09)
1813 #define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A)
1814 #define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B)
1815 #define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D)
1816 #define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E)
1817 #define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F)
1818 #define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10)
1819 #define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11)
1820 #define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12)
1821 #define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13)
1822 #define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14)
1823 #define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15)
1824 #define MPI26_CTRL_OP_SHUTDOWN (0x16)
1825 #define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17)
1826 #define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18)
1827 #define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19)
1828 #define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80)
1829
1830 /* values for the PrimFlags field */
1831 #define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08)
1832 #define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02)
1833 #define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01)
1834
1835 /* values for the LookupMethod field */
1836 #define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01)
1837 #define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02)
1838 #define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)
1839
1840
1841 /* IO Unit Control Reply Message */
1842 typedef struct _MPI26_IOUNIT_CONTROL_REPLY {
1843 U8 Operation; /* 0x00 */
1844 U8 Reserved1; /* 0x01 */
1845 U8 MsgLength; /* 0x02 */
1846 U8 Function; /* 0x03 */
1847 U16 DevHandle; /* 0x04 */
1848 U8 IOCParameter; /* 0x06 */
1849 U8 MsgFlags; /* 0x07 */
1850 U8 VP_ID; /* 0x08 */
1851 U8 VF_ID; /* 0x09 */
1852 U16 Reserved3; /* 0x0A */
1853 U16 Reserved4; /* 0x0C */
1854 U16 IOCStatus; /* 0x0E */
1855 U32 IOCLogInfo; /* 0x10 */
1856 } MPI26_IOUNIT_CONTROL_REPLY,
1857 *PTR_MPI26_IOUNIT_CONTROL_REPLY,
1858 Mpi26IoUnitControlReply_t,
1859 *pMpi26IoUnitControlReply_t;
1860
1861
1862 #endif
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