2 * This is the Fusion MPT base driver providing common API layer interface
3 * for access to MPT (Message Passing Technology) firmware.
5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
6 * Copyright (C) 2012-2014 LSI Corporation
7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/init.h>
50 #include <linux/slab.h>
51 #include <linux/types.h>
52 #include <linux/pci.h>
53 #include <linux/kdev_t.h>
54 #include <linux/blkdev.h>
55 #include <linux/delay.h>
56 #include <linux/interrupt.h>
57 #include <linux/dma-mapping.h>
59 #include <linux/time.h>
60 #include <linux/ktime.h>
61 #include <linux/kthread.h>
62 #include <asm/page.h> /* To get host page size per arch */
63 #include <linux/aer.h>
66 #include "mpt3sas_base.h"
68 static MPT_CALLBACK mpt_callbacks
[MPT_MAX_CALLBACKS
];
71 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
73 /* maximum controller queue depth */
74 #define MAX_HBA_QUEUE_DEPTH 30000
75 #define MAX_CHAIN_DEPTH 100000
76 static int max_queue_depth
= -1;
77 module_param(max_queue_depth
, int, 0);
78 MODULE_PARM_DESC(max_queue_depth
, " max controller queue depth ");
80 static int max_sgl_entries
= -1;
81 module_param(max_sgl_entries
, int, 0);
82 MODULE_PARM_DESC(max_sgl_entries
, " max sg entries ");
84 static int msix_disable
= -1;
85 module_param(msix_disable
, int, 0);
86 MODULE_PARM_DESC(msix_disable
, " disable msix routed interrupts (default=0)");
88 static int smp_affinity_enable
= 1;
89 module_param(smp_affinity_enable
, int, S_IRUGO
);
90 MODULE_PARM_DESC(smp_affinity_enable
, "SMP affinity feature enable/disbale Default: enable(1)");
92 static int max_msix_vectors
= -1;
93 module_param(max_msix_vectors
, int, 0);
94 MODULE_PARM_DESC(max_msix_vectors
,
97 static int mpt3sas_fwfault_debug
;
98 MODULE_PARM_DESC(mpt3sas_fwfault_debug
,
99 " enable detection of firmware fault and halt firmware - (default=0)");
102 _base_get_ioc_facts(struct MPT3SAS_ADAPTER
*ioc
);
105 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
109 _scsih_set_fwfault_debug(const char *val
, struct kernel_param
*kp
)
111 int ret
= param_set_int(val
, kp
);
112 struct MPT3SAS_ADAPTER
*ioc
;
117 /* global ioc spinlock to protect controller list on list operations */
118 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug
);
119 spin_lock(&gioc_lock
);
120 list_for_each_entry(ioc
, &mpt3sas_ioc_list
, list
)
121 ioc
->fwfault_debug
= mpt3sas_fwfault_debug
;
122 spin_unlock(&gioc_lock
);
125 module_param_call(mpt3sas_fwfault_debug
, _scsih_set_fwfault_debug
,
126 param_get_int
, &mpt3sas_fwfault_debug
, 0644);
129 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
130 * @arg: input argument, used to derive ioc
132 * Return 0 if controller is removed from pci subsystem.
133 * Return -1 for other case.
135 static int mpt3sas_remove_dead_ioc_func(void *arg
)
137 struct MPT3SAS_ADAPTER
*ioc
= (struct MPT3SAS_ADAPTER
*)arg
;
138 struct pci_dev
*pdev
;
146 pci_stop_and_remove_bus_device_locked(pdev
);
151 * _base_fault_reset_work - workq handling ioc fault conditions
152 * @work: input argument, used to derive ioc
158 _base_fault_reset_work(struct work_struct
*work
)
160 struct MPT3SAS_ADAPTER
*ioc
=
161 container_of(work
, struct MPT3SAS_ADAPTER
, fault_reset_work
.work
);
165 struct task_struct
*p
;
168 spin_lock_irqsave(&ioc
->ioc_reset_in_progress_lock
, flags
);
169 if (ioc
->shost_recovery
|| ioc
->pci_error_recovery
)
171 spin_unlock_irqrestore(&ioc
->ioc_reset_in_progress_lock
, flags
);
173 doorbell
= mpt3sas_base_get_iocstate(ioc
, 0);
174 if ((doorbell
& MPI2_IOC_STATE_MASK
) == MPI2_IOC_STATE_MASK
) {
175 pr_err(MPT3SAS_FMT
"SAS host is non-operational !!!!\n",
178 /* It may be possible that EEH recovery can resolve some of
179 * pci bus failure issues rather removing the dead ioc function
180 * by considering controller is in a non-operational state. So
181 * here priority is given to the EEH recovery. If it doesn't
182 * not resolve this issue, mpt3sas driver will consider this
183 * controller to non-operational state and remove the dead ioc
186 if (ioc
->non_operational_loop
++ < 5) {
187 spin_lock_irqsave(&ioc
->ioc_reset_in_progress_lock
,
193 * Call _scsih_flush_pending_cmds callback so that we flush all
194 * pending commands back to OS. This call is required to aovid
195 * deadlock at block layer. Dead IOC will fail to do diag reset,
196 * and this call is safe since dead ioc will never return any
197 * command back from HW.
199 ioc
->schedule_dead_ioc_flush_running_cmds(ioc
);
201 * Set remove_host flag early since kernel thread will
202 * take some time to execute.
204 ioc
->remove_host
= 1;
205 /*Remove the Dead Host */
206 p
= kthread_run(mpt3sas_remove_dead_ioc_func
, ioc
,
207 "%s_dead_ioc_%d", ioc
->driver_name
, ioc
->id
);
210 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
211 ioc
->name
, __func__
);
214 "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
215 ioc
->name
, __func__
);
216 return; /* don't rearm timer */
219 ioc
->non_operational_loop
= 0;
221 if ((doorbell
& MPI2_IOC_STATE_MASK
) != MPI2_IOC_STATE_OPERATIONAL
) {
222 rc
= mpt3sas_base_hard_reset_handler(ioc
, FORCE_BIG_HAMMER
);
223 pr_warn(MPT3SAS_FMT
"%s: hard reset: %s\n", ioc
->name
,
224 __func__
, (rc
== 0) ? "success" : "failed");
225 doorbell
= mpt3sas_base_get_iocstate(ioc
, 0);
226 if ((doorbell
& MPI2_IOC_STATE_MASK
) == MPI2_IOC_STATE_FAULT
)
227 mpt3sas_base_fault_info(ioc
, doorbell
&
228 MPI2_DOORBELL_DATA_MASK
);
229 if (rc
&& (doorbell
& MPI2_IOC_STATE_MASK
) !=
230 MPI2_IOC_STATE_OPERATIONAL
)
231 return; /* don't rearm timer */
234 spin_lock_irqsave(&ioc
->ioc_reset_in_progress_lock
, flags
);
236 if (ioc
->fault_reset_work_q
)
237 queue_delayed_work(ioc
->fault_reset_work_q
,
238 &ioc
->fault_reset_work
,
239 msecs_to_jiffies(FAULT_POLLING_INTERVAL
));
240 spin_unlock_irqrestore(&ioc
->ioc_reset_in_progress_lock
, flags
);
244 * mpt3sas_base_start_watchdog - start the fault_reset_work_q
245 * @ioc: per adapter object
251 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER
*ioc
)
255 if (ioc
->fault_reset_work_q
)
258 /* initialize fault polling */
260 INIT_DELAYED_WORK(&ioc
->fault_reset_work
, _base_fault_reset_work
);
261 snprintf(ioc
->fault_reset_work_q_name
,
262 sizeof(ioc
->fault_reset_work_q_name
), "poll_%s%d_status",
263 ioc
->driver_name
, ioc
->id
);
264 ioc
->fault_reset_work_q
=
265 create_singlethread_workqueue(ioc
->fault_reset_work_q_name
);
266 if (!ioc
->fault_reset_work_q
) {
267 pr_err(MPT3SAS_FMT
"%s: failed (line=%d)\n",
268 ioc
->name
, __func__
, __LINE__
);
271 spin_lock_irqsave(&ioc
->ioc_reset_in_progress_lock
, flags
);
272 if (ioc
->fault_reset_work_q
)
273 queue_delayed_work(ioc
->fault_reset_work_q
,
274 &ioc
->fault_reset_work
,
275 msecs_to_jiffies(FAULT_POLLING_INTERVAL
));
276 spin_unlock_irqrestore(&ioc
->ioc_reset_in_progress_lock
, flags
);
280 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
281 * @ioc: per adapter object
287 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER
*ioc
)
290 struct workqueue_struct
*wq
;
292 spin_lock_irqsave(&ioc
->ioc_reset_in_progress_lock
, flags
);
293 wq
= ioc
->fault_reset_work_q
;
294 ioc
->fault_reset_work_q
= NULL
;
295 spin_unlock_irqrestore(&ioc
->ioc_reset_in_progress_lock
, flags
);
297 if (!cancel_delayed_work_sync(&ioc
->fault_reset_work
))
299 destroy_workqueue(wq
);
304 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
305 * @ioc: per adapter object
306 * @fault_code: fault code
311 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER
*ioc
, u16 fault_code
)
313 pr_err(MPT3SAS_FMT
"fault_state(0x%04x)!\n",
314 ioc
->name
, fault_code
);
318 * mpt3sas_halt_firmware - halt's mpt controller firmware
319 * @ioc: per adapter object
321 * For debugging timeout related issues. Writing 0xCOFFEE00
322 * to the doorbell register will halt controller firmware. With
323 * the purpose to stop both driver and firmware, the enduser can
324 * obtain a ring buffer from controller UART.
327 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER
*ioc
)
331 if (!ioc
->fwfault_debug
)
336 doorbell
= readl(&ioc
->chip
->Doorbell
);
337 if ((doorbell
& MPI2_IOC_STATE_MASK
) == MPI2_IOC_STATE_FAULT
)
338 mpt3sas_base_fault_info(ioc
, doorbell
);
340 writel(0xC0FFEE00, &ioc
->chip
->Doorbell
);
341 pr_err(MPT3SAS_FMT
"Firmware is halted due to command timeout\n",
345 if (ioc
->fwfault_debug
== 2)
349 panic("panic in %s\n", __func__
);
353 * _base_sas_ioc_info - verbose translation of the ioc status
354 * @ioc: per adapter object
355 * @mpi_reply: reply mf payload returned from firmware
356 * @request_hdr: request mf
361 _base_sas_ioc_info(struct MPT3SAS_ADAPTER
*ioc
, MPI2DefaultReply_t
*mpi_reply
,
362 MPI2RequestHeader_t
*request_hdr
)
364 u16 ioc_status
= le16_to_cpu(mpi_reply
->IOCStatus
) &
368 char *func_str
= NULL
;
370 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
371 if (request_hdr
->Function
== MPI2_FUNCTION_SCSI_IO_REQUEST
||
372 request_hdr
->Function
== MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH
||
373 request_hdr
->Function
== MPI2_FUNCTION_EVENT_NOTIFICATION
)
376 if (ioc_status
== MPI2_IOCSTATUS_CONFIG_INVALID_PAGE
)
379 switch (ioc_status
) {
381 /****************************************************************************
382 * Common IOCStatus values for all replies
383 ****************************************************************************/
385 case MPI2_IOCSTATUS_INVALID_FUNCTION
:
386 desc
= "invalid function";
388 case MPI2_IOCSTATUS_BUSY
:
391 case MPI2_IOCSTATUS_INVALID_SGL
:
392 desc
= "invalid sgl";
394 case MPI2_IOCSTATUS_INTERNAL_ERROR
:
395 desc
= "internal error";
397 case MPI2_IOCSTATUS_INVALID_VPID
:
398 desc
= "invalid vpid";
400 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES
:
401 desc
= "insufficient resources";
403 case MPI2_IOCSTATUS_INSUFFICIENT_POWER
:
404 desc
= "insufficient power";
406 case MPI2_IOCSTATUS_INVALID_FIELD
:
407 desc
= "invalid field";
409 case MPI2_IOCSTATUS_INVALID_STATE
:
410 desc
= "invalid state";
412 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED
:
413 desc
= "op state not supported";
416 /****************************************************************************
417 * Config IOCStatus values
418 ****************************************************************************/
420 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION
:
421 desc
= "config invalid action";
423 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE
:
424 desc
= "config invalid type";
426 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE
:
427 desc
= "config invalid page";
429 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA
:
430 desc
= "config invalid data";
432 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS
:
433 desc
= "config no defaults";
435 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT
:
436 desc
= "config cant commit";
439 /****************************************************************************
441 ****************************************************************************/
443 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR
:
444 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE
:
445 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE
:
446 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN
:
447 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN
:
448 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR
:
449 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR
:
450 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED
:
451 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH
:
452 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED
:
453 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED
:
454 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED
:
457 /****************************************************************************
458 * For use by SCSI Initiator and SCSI Target end-to-end data protection
459 ****************************************************************************/
461 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR
:
462 desc
= "eedp guard error";
464 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR
:
465 desc
= "eedp ref tag error";
467 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR
:
468 desc
= "eedp app tag error";
471 /****************************************************************************
473 ****************************************************************************/
475 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX
:
476 desc
= "target invalid io index";
478 case MPI2_IOCSTATUS_TARGET_ABORTED
:
479 desc
= "target aborted";
481 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE
:
482 desc
= "target no conn retryable";
484 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION
:
485 desc
= "target no connection";
487 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH
:
488 desc
= "target xfer count mismatch";
490 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR
:
491 desc
= "target data offset error";
493 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA
:
494 desc
= "target too much write data";
496 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT
:
497 desc
= "target iu too short";
499 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT
:
500 desc
= "target ack nak timeout";
502 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED
:
503 desc
= "target nak received";
506 /****************************************************************************
507 * Serial Attached SCSI values
508 ****************************************************************************/
510 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED
:
511 desc
= "smp request failed";
513 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN
:
514 desc
= "smp data overrun";
517 /****************************************************************************
518 * Diagnostic Buffer Post / Diagnostic Release values
519 ****************************************************************************/
521 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
:
522 desc
= "diagnostic released";
531 switch (request_hdr
->Function
) {
532 case MPI2_FUNCTION_CONFIG
:
533 frame_sz
= sizeof(Mpi2ConfigRequest_t
) + ioc
->sge_size
;
534 func_str
= "config_page";
536 case MPI2_FUNCTION_SCSI_TASK_MGMT
:
537 frame_sz
= sizeof(Mpi2SCSITaskManagementRequest_t
);
538 func_str
= "task_mgmt";
540 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL
:
541 frame_sz
= sizeof(Mpi2SasIoUnitControlRequest_t
);
542 func_str
= "sas_iounit_ctl";
544 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR
:
545 frame_sz
= sizeof(Mpi2SepRequest_t
);
546 func_str
= "enclosure";
548 case MPI2_FUNCTION_IOC_INIT
:
549 frame_sz
= sizeof(Mpi2IOCInitRequest_t
);
550 func_str
= "ioc_init";
552 case MPI2_FUNCTION_PORT_ENABLE
:
553 frame_sz
= sizeof(Mpi2PortEnableRequest_t
);
554 func_str
= "port_enable";
556 case MPI2_FUNCTION_SMP_PASSTHROUGH
:
557 frame_sz
= sizeof(Mpi2SmpPassthroughRequest_t
) + ioc
->sge_size
;
558 func_str
= "smp_passthru";
560 case MPI2_FUNCTION_NVME_ENCAPSULATED
:
561 frame_sz
= sizeof(Mpi26NVMeEncapsulatedRequest_t
) +
563 func_str
= "nvme_encapsulated";
567 func_str
= "unknown";
571 pr_warn(MPT3SAS_FMT
"ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
572 ioc
->name
, desc
, ioc_status
, request_hdr
, func_str
);
574 _debug_dump_mf(request_hdr
, frame_sz
/4);
578 * _base_display_event_data - verbose translation of firmware asyn events
579 * @ioc: per adapter object
580 * @mpi_reply: reply mf payload returned from firmware
585 _base_display_event_data(struct MPT3SAS_ADAPTER
*ioc
,
586 Mpi2EventNotificationReply_t
*mpi_reply
)
591 if (!(ioc
->logging_level
& MPT_DEBUG_EVENTS
))
594 event
= le16_to_cpu(mpi_reply
->Event
);
597 case MPI2_EVENT_LOG_DATA
:
600 case MPI2_EVENT_STATE_CHANGE
:
601 desc
= "Status Change";
603 case MPI2_EVENT_HARD_RESET_RECEIVED
:
604 desc
= "Hard Reset Received";
606 case MPI2_EVENT_EVENT_CHANGE
:
607 desc
= "Event Change";
609 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE
:
610 desc
= "Device Status Change";
612 case MPI2_EVENT_IR_OPERATION_STATUS
:
613 if (!ioc
->hide_ir_msg
)
614 desc
= "IR Operation Status";
616 case MPI2_EVENT_SAS_DISCOVERY
:
618 Mpi2EventDataSasDiscovery_t
*event_data
=
619 (Mpi2EventDataSasDiscovery_t
*)mpi_reply
->EventData
;
620 pr_info(MPT3SAS_FMT
"Discovery: (%s)", ioc
->name
,
621 (event_data
->ReasonCode
== MPI2_EVENT_SAS_DISC_RC_STARTED
) ?
623 if (event_data
->DiscoveryStatus
)
624 pr_cont(" discovery_status(0x%08x)",
625 le32_to_cpu(event_data
->DiscoveryStatus
));
629 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE
:
630 desc
= "SAS Broadcast Primitive";
632 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE
:
633 desc
= "SAS Init Device Status Change";
635 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW
:
636 desc
= "SAS Init Table Overflow";
638 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST
:
639 desc
= "SAS Topology Change List";
641 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE
:
642 desc
= "SAS Enclosure Device Status Change";
644 case MPI2_EVENT_IR_VOLUME
:
645 if (!ioc
->hide_ir_msg
)
648 case MPI2_EVENT_IR_PHYSICAL_DISK
:
649 if (!ioc
->hide_ir_msg
)
650 desc
= "IR Physical Disk";
652 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST
:
653 if (!ioc
->hide_ir_msg
)
654 desc
= "IR Configuration Change List";
656 case MPI2_EVENT_LOG_ENTRY_ADDED
:
657 if (!ioc
->hide_ir_msg
)
658 desc
= "Log Entry Added";
660 case MPI2_EVENT_TEMP_THRESHOLD
:
661 desc
= "Temperature Threshold";
663 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION
:
664 desc
= "Cable Event";
666 case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE
:
667 desc
= "PCIE Device Status Change";
669 case MPI2_EVENT_PCIE_ENUMERATION
:
671 Mpi26EventDataPCIeEnumeration_t
*event_data
=
672 (Mpi26EventDataPCIeEnumeration_t
*)mpi_reply
->EventData
;
673 pr_info(MPT3SAS_FMT
"PCIE Enumeration: (%s)", ioc
->name
,
674 (event_data
->ReasonCode
==
675 MPI26_EVENT_PCIE_ENUM_RC_STARTED
) ?
677 if (event_data
->EnumerationStatus
)
678 pr_info("enumeration_status(0x%08x)",
679 le32_to_cpu(event_data
->EnumerationStatus
));
683 case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST
:
684 desc
= "PCIE Topology Change List";
691 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
, desc
);
695 * _base_sas_log_info - verbose translation of firmware log info
696 * @ioc: per adapter object
697 * @log_info: log info
702 _base_sas_log_info(struct MPT3SAS_ADAPTER
*ioc
, u32 log_info
)
713 union loginfo_type sas_loginfo
;
714 char *originator_str
= NULL
;
716 sas_loginfo
.loginfo
= log_info
;
717 if (sas_loginfo
.dw
.bus_type
!= 3 /*SAS*/)
720 /* each nexus loss loginfo */
721 if (log_info
== 0x31170000)
724 /* eat the loginfos associated with task aborts */
725 if (ioc
->ignore_loginfos
&& (log_info
== 0x30050000 || log_info
==
726 0x31140000 || log_info
== 0x31130000))
729 switch (sas_loginfo
.dw
.originator
) {
731 originator_str
= "IOP";
734 originator_str
= "PL";
737 if (!ioc
->hide_ir_msg
)
738 originator_str
= "IR";
740 originator_str
= "WarpDrive";
745 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
747 originator_str
, sas_loginfo
.dw
.code
,
748 sas_loginfo
.dw
.subcode
);
752 * _base_display_reply_info -
753 * @ioc: per adapter object
754 * @smid: system request message index
755 * @msix_index: MSIX table index supplied by the OS
756 * @reply: reply message frame(lower 32bit addr)
761 _base_display_reply_info(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
, u8 msix_index
,
764 MPI2DefaultReply_t
*mpi_reply
;
768 mpi_reply
= mpt3sas_base_get_reply_virt_addr(ioc
, reply
);
769 if (unlikely(!mpi_reply
)) {
770 pr_err(MPT3SAS_FMT
"mpi_reply not valid at %s:%d/%s()!\n",
771 ioc
->name
, __FILE__
, __LINE__
, __func__
);
774 ioc_status
= le16_to_cpu(mpi_reply
->IOCStatus
);
776 if ((ioc_status
& MPI2_IOCSTATUS_MASK
) &&
777 (ioc
->logging_level
& MPT_DEBUG_REPLY
)) {
778 _base_sas_ioc_info(ioc
, mpi_reply
,
779 mpt3sas_base_get_msg_frame(ioc
, smid
));
782 if (ioc_status
& MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE
) {
783 loginfo
= le32_to_cpu(mpi_reply
->IOCLogInfo
);
784 _base_sas_log_info(ioc
, loginfo
);
787 if (ioc_status
|| loginfo
) {
788 ioc_status
&= MPI2_IOCSTATUS_MASK
;
789 mpt3sas_trigger_mpi(ioc
, ioc_status
, loginfo
);
794 * mpt3sas_base_done - base internal command completion routine
795 * @ioc: per adapter object
796 * @smid: system request message index
797 * @msix_index: MSIX table index supplied by the OS
798 * @reply: reply message frame(lower 32bit addr)
800 * Return 1 meaning mf should be freed from _base_interrupt
801 * 0 means the mf is freed from this function.
804 mpt3sas_base_done(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
, u8 msix_index
,
807 MPI2DefaultReply_t
*mpi_reply
;
809 mpi_reply
= mpt3sas_base_get_reply_virt_addr(ioc
, reply
);
810 if (mpi_reply
&& mpi_reply
->Function
== MPI2_FUNCTION_EVENT_ACK
)
811 return mpt3sas_check_for_pending_internal_cmds(ioc
, smid
);
813 if (ioc
->base_cmds
.status
== MPT3_CMD_NOT_USED
)
816 ioc
->base_cmds
.status
|= MPT3_CMD_COMPLETE
;
818 ioc
->base_cmds
.status
|= MPT3_CMD_REPLY_VALID
;
819 memcpy(ioc
->base_cmds
.reply
, mpi_reply
, mpi_reply
->MsgLength
*4);
821 ioc
->base_cmds
.status
&= ~MPT3_CMD_PENDING
;
823 complete(&ioc
->base_cmds
.done
);
828 * _base_async_event - main callback handler for firmware asyn events
829 * @ioc: per adapter object
830 * @msix_index: MSIX table index supplied by the OS
831 * @reply: reply message frame(lower 32bit addr)
833 * Return 1 meaning mf should be freed from _base_interrupt
834 * 0 means the mf is freed from this function.
837 _base_async_event(struct MPT3SAS_ADAPTER
*ioc
, u8 msix_index
, u32 reply
)
839 Mpi2EventNotificationReply_t
*mpi_reply
;
840 Mpi2EventAckRequest_t
*ack_request
;
842 struct _event_ack_list
*delayed_event_ack
;
844 mpi_reply
= mpt3sas_base_get_reply_virt_addr(ioc
, reply
);
847 if (mpi_reply
->Function
!= MPI2_FUNCTION_EVENT_NOTIFICATION
)
850 _base_display_event_data(ioc
, mpi_reply
);
852 if (!(mpi_reply
->AckRequired
& MPI2_EVENT_NOTIFICATION_ACK_REQUIRED
))
854 smid
= mpt3sas_base_get_smid(ioc
, ioc
->base_cb_idx
);
856 delayed_event_ack
= kzalloc(sizeof(*delayed_event_ack
),
858 if (!delayed_event_ack
)
860 INIT_LIST_HEAD(&delayed_event_ack
->list
);
861 delayed_event_ack
->Event
= mpi_reply
->Event
;
862 delayed_event_ack
->EventContext
= mpi_reply
->EventContext
;
863 list_add_tail(&delayed_event_ack
->list
,
864 &ioc
->delayed_event_ack_list
);
865 dewtprintk(ioc
, pr_info(MPT3SAS_FMT
866 "DELAYED: EVENT ACK: event (0x%04x)\n",
867 ioc
->name
, le16_to_cpu(mpi_reply
->Event
)));
871 ack_request
= mpt3sas_base_get_msg_frame(ioc
, smid
);
872 memset(ack_request
, 0, sizeof(Mpi2EventAckRequest_t
));
873 ack_request
->Function
= MPI2_FUNCTION_EVENT_ACK
;
874 ack_request
->Event
= mpi_reply
->Event
;
875 ack_request
->EventContext
= mpi_reply
->EventContext
;
876 ack_request
->VF_ID
= 0; /* TODO */
877 ack_request
->VP_ID
= 0;
878 ioc
->put_smid_default(ioc
, smid
);
882 /* scsih callback handler */
883 mpt3sas_scsih_event_callback(ioc
, msix_index
, reply
);
885 /* ctl callback handler */
886 mpt3sas_ctl_event_callback(ioc
, msix_index
, reply
);
892 * _base_get_cb_idx - obtain the callback index
893 * @ioc: per adapter object
894 * @smid: system request message index
896 * Return callback index.
899 _base_get_cb_idx(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
)
904 if (smid
< ioc
->hi_priority_smid
) {
906 cb_idx
= ioc
->scsi_lookup
[i
].cb_idx
;
907 } else if (smid
< ioc
->internal_smid
) {
908 i
= smid
- ioc
->hi_priority_smid
;
909 cb_idx
= ioc
->hpr_lookup
[i
].cb_idx
;
910 } else if (smid
<= ioc
->hba_queue_depth
) {
911 i
= smid
- ioc
->internal_smid
;
912 cb_idx
= ioc
->internal_lookup
[i
].cb_idx
;
919 * _base_mask_interrupts - disable interrupts
920 * @ioc: per adapter object
922 * Disabling ResetIRQ, Reply and Doorbell Interrupts
927 _base_mask_interrupts(struct MPT3SAS_ADAPTER
*ioc
)
931 ioc
->mask_interrupts
= 1;
932 him_register
= readl(&ioc
->chip
->HostInterruptMask
);
933 him_register
|= MPI2_HIM_DIM
+ MPI2_HIM_RIM
+ MPI2_HIM_RESET_IRQ_MASK
;
934 writel(him_register
, &ioc
->chip
->HostInterruptMask
);
935 readl(&ioc
->chip
->HostInterruptMask
);
939 * _base_unmask_interrupts - enable interrupts
940 * @ioc: per adapter object
942 * Enabling only Reply Interrupts
947 _base_unmask_interrupts(struct MPT3SAS_ADAPTER
*ioc
)
951 him_register
= readl(&ioc
->chip
->HostInterruptMask
);
952 him_register
&= ~MPI2_HIM_RIM
;
953 writel(him_register
, &ioc
->chip
->HostInterruptMask
);
954 ioc
->mask_interrupts
= 0;
957 union reply_descriptor
{
966 * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
967 * @irq: irq number (not used)
968 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
969 * @r: pt_regs pointer (not used)
971 * Return IRQ_HANDLE if processed, else IRQ_NONE.
974 _base_interrupt(int irq
, void *bus_id
)
976 struct adapter_reply_queue
*reply_q
= bus_id
;
977 union reply_descriptor rd
;
979 u8 request_desript_type
;
983 u8 msix_index
= reply_q
->msix_index
;
984 struct MPT3SAS_ADAPTER
*ioc
= reply_q
->ioc
;
985 Mpi2ReplyDescriptorsUnion_t
*rpf
;
988 if (ioc
->mask_interrupts
)
991 if (!atomic_add_unless(&reply_q
->busy
, 1, 1))
994 rpf
= &reply_q
->reply_post_free
[reply_q
->reply_post_host_index
];
995 request_desript_type
= rpf
->Default
.ReplyFlags
996 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK
;
997 if (request_desript_type
== MPI2_RPY_DESCRIPT_FLAGS_UNUSED
) {
998 atomic_dec(&reply_q
->busy
);
1005 rd
.word
= le64_to_cpu(rpf
->Words
);
1006 if (rd
.u
.low
== UINT_MAX
|| rd
.u
.high
== UINT_MAX
)
1009 smid
= le16_to_cpu(rpf
->Default
.DescriptorTypeDependent1
);
1010 if (request_desript_type
==
1011 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS
||
1012 request_desript_type
==
1013 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS
||
1014 request_desript_type
==
1015 MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS
) {
1016 cb_idx
= _base_get_cb_idx(ioc
, smid
);
1017 if ((likely(cb_idx
< MPT_MAX_CALLBACKS
)) &&
1018 (likely(mpt_callbacks
[cb_idx
] != NULL
))) {
1019 rc
= mpt_callbacks
[cb_idx
](ioc
, smid
,
1022 mpt3sas_base_free_smid(ioc
, smid
);
1024 } else if (request_desript_type
==
1025 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY
) {
1026 reply
= le32_to_cpu(
1027 rpf
->AddressReply
.ReplyFrameAddress
);
1028 if (reply
> ioc
->reply_dma_max_address
||
1029 reply
< ioc
->reply_dma_min_address
)
1032 cb_idx
= _base_get_cb_idx(ioc
, smid
);
1033 if ((likely(cb_idx
< MPT_MAX_CALLBACKS
)) &&
1034 (likely(mpt_callbacks
[cb_idx
] != NULL
))) {
1035 rc
= mpt_callbacks
[cb_idx
](ioc
, smid
,
1038 _base_display_reply_info(ioc
,
1039 smid
, msix_index
, reply
);
1041 mpt3sas_base_free_smid(ioc
,
1045 _base_async_event(ioc
, msix_index
, reply
);
1048 /* reply free queue handling */
1050 ioc
->reply_free_host_index
=
1051 (ioc
->reply_free_host_index
==
1052 (ioc
->reply_free_queue_depth
- 1)) ?
1053 0 : ioc
->reply_free_host_index
+ 1;
1054 ioc
->reply_free
[ioc
->reply_free_host_index
] =
1056 writel(ioc
->reply_free_host_index
,
1057 &ioc
->chip
->ReplyFreeHostIndex
);
1061 rpf
->Words
= cpu_to_le64(ULLONG_MAX
);
1062 reply_q
->reply_post_host_index
=
1063 (reply_q
->reply_post_host_index
==
1064 (ioc
->reply_post_queue_depth
- 1)) ? 0 :
1065 reply_q
->reply_post_host_index
+ 1;
1066 request_desript_type
=
1067 reply_q
->reply_post_free
[reply_q
->reply_post_host_index
].
1068 Default
.ReplyFlags
& MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK
;
1070 /* Update the reply post host index after continuously
1071 * processing the threshold number of Reply Descriptors.
1072 * So that FW can find enough entries to post the Reply
1073 * Descriptors in the reply descriptor post queue.
1075 if (completed_cmds
> ioc
->hba_queue_depth
/3) {
1076 if (ioc
->combined_reply_queue
) {
1077 writel(reply_q
->reply_post_host_index
|
1078 ((msix_index
& 7) <<
1079 MPI2_RPHI_MSIX_INDEX_SHIFT
),
1080 ioc
->replyPostRegisterIndex
[msix_index
/8]);
1082 writel(reply_q
->reply_post_host_index
|
1084 MPI2_RPHI_MSIX_INDEX_SHIFT
),
1085 &ioc
->chip
->ReplyPostHostIndex
);
1089 if (request_desript_type
== MPI2_RPY_DESCRIPT_FLAGS_UNUSED
)
1091 if (!reply_q
->reply_post_host_index
)
1092 rpf
= reply_q
->reply_post_free
;
1099 if (!completed_cmds
) {
1100 atomic_dec(&reply_q
->busy
);
1104 if (ioc
->is_warpdrive
) {
1105 writel(reply_q
->reply_post_host_index
,
1106 ioc
->reply_post_host_index
[msix_index
]);
1107 atomic_dec(&reply_q
->busy
);
1111 /* Update Reply Post Host Index.
1112 * For those HBA's which support combined reply queue feature
1113 * 1. Get the correct Supplemental Reply Post Host Index Register.
1114 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1115 * Index Register address bank i.e replyPostRegisterIndex[],
1116 * 2. Then update this register with new reply host index value
1117 * in ReplyPostIndex field and the MSIxIndex field with
1118 * msix_index value reduced to a value between 0 and 7,
1119 * using a modulo 8 operation. Since each Supplemental Reply Post
1120 * Host Index Register supports 8 MSI-X vectors.
1122 * For other HBA's just update the Reply Post Host Index register with
1123 * new reply host index value in ReplyPostIndex Field and msix_index
1124 * value in MSIxIndex field.
1126 if (ioc
->combined_reply_queue
)
1127 writel(reply_q
->reply_post_host_index
| ((msix_index
& 7) <<
1128 MPI2_RPHI_MSIX_INDEX_SHIFT
),
1129 ioc
->replyPostRegisterIndex
[msix_index
/8]);
1131 writel(reply_q
->reply_post_host_index
| (msix_index
<<
1132 MPI2_RPHI_MSIX_INDEX_SHIFT
),
1133 &ioc
->chip
->ReplyPostHostIndex
);
1134 atomic_dec(&reply_q
->busy
);
1139 * _base_is_controller_msix_enabled - is controller support muli-reply queues
1140 * @ioc: per adapter object
1144 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER
*ioc
)
1146 return (ioc
->facts
.IOCCapabilities
&
1147 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX
) && ioc
->msix_enable
;
1151 * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
1152 * @ioc: per adapter object
1153 * Context: non ISR conext
1155 * Called when a Task Management request has completed.
1160 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER
*ioc
)
1162 struct adapter_reply_queue
*reply_q
;
1164 /* If MSIX capability is turned off
1165 * then multi-queues are not enabled
1167 if (!_base_is_controller_msix_enabled(ioc
))
1170 list_for_each_entry(reply_q
, &ioc
->reply_queue_list
, list
) {
1171 if (ioc
->shost_recovery
|| ioc
->remove_host
||
1172 ioc
->pci_error_recovery
)
1174 /* TMs are on msix_index == 0 */
1175 if (reply_q
->msix_index
== 0)
1177 synchronize_irq(pci_irq_vector(ioc
->pdev
, reply_q
->msix_index
));
1182 * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1183 * @cb_idx: callback index
1188 mpt3sas_base_release_callback_handler(u8 cb_idx
)
1190 mpt_callbacks
[cb_idx
] = NULL
;
1194 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1195 * @cb_func: callback function
1200 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func
)
1204 for (cb_idx
= MPT_MAX_CALLBACKS
-1; cb_idx
; cb_idx
--)
1205 if (mpt_callbacks
[cb_idx
] == NULL
)
1208 mpt_callbacks
[cb_idx
] = cb_func
;
1213 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1218 mpt3sas_base_initialize_callback_handler(void)
1222 for (cb_idx
= 0; cb_idx
< MPT_MAX_CALLBACKS
; cb_idx
++)
1223 mpt3sas_base_release_callback_handler(cb_idx
);
1228 * _base_build_zero_len_sge - build zero length sg entry
1229 * @ioc: per adapter object
1230 * @paddr: virtual address for SGE
1232 * Create a zero length scatter gather entry to insure the IOCs hardware has
1233 * something to use if the target device goes brain dead and tries
1234 * to send data even when none is asked for.
1239 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER
*ioc
, void *paddr
)
1241 u32 flags_length
= (u32
)((MPI2_SGE_FLAGS_LAST_ELEMENT
|
1242 MPI2_SGE_FLAGS_END_OF_BUFFER
| MPI2_SGE_FLAGS_END_OF_LIST
|
1243 MPI2_SGE_FLAGS_SIMPLE_ELEMENT
) <<
1244 MPI2_SGE_FLAGS_SHIFT
);
1245 ioc
->base_add_sg_single(paddr
, flags_length
, -1);
1249 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1250 * @paddr: virtual address for SGE
1251 * @flags_length: SGE flags and data transfer length
1252 * @dma_addr: Physical address
1257 _base_add_sg_single_32(void *paddr
, u32 flags_length
, dma_addr_t dma_addr
)
1259 Mpi2SGESimple32_t
*sgel
= paddr
;
1261 flags_length
|= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING
|
1262 MPI2_SGE_FLAGS_SYSTEM_ADDRESS
) << MPI2_SGE_FLAGS_SHIFT
;
1263 sgel
->FlagsLength
= cpu_to_le32(flags_length
);
1264 sgel
->Address
= cpu_to_le32(dma_addr
);
1269 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1270 * @paddr: virtual address for SGE
1271 * @flags_length: SGE flags and data transfer length
1272 * @dma_addr: Physical address
1277 _base_add_sg_single_64(void *paddr
, u32 flags_length
, dma_addr_t dma_addr
)
1279 Mpi2SGESimple64_t
*sgel
= paddr
;
1281 flags_length
|= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING
|
1282 MPI2_SGE_FLAGS_SYSTEM_ADDRESS
) << MPI2_SGE_FLAGS_SHIFT
;
1283 sgel
->FlagsLength
= cpu_to_le32(flags_length
);
1284 sgel
->Address
= cpu_to_le64(dma_addr
);
1288 * _base_get_chain_buffer_tracker - obtain chain tracker
1289 * @ioc: per adapter object
1290 * @smid: smid associated to an IO request
1292 * Returns chain tracker(from ioc->free_chain_list)
1294 static struct chain_tracker
*
1295 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
)
1297 struct chain_tracker
*chain_req
;
1298 unsigned long flags
;
1300 spin_lock_irqsave(&ioc
->scsi_lookup_lock
, flags
);
1301 if (list_empty(&ioc
->free_chain_list
)) {
1302 spin_unlock_irqrestore(&ioc
->scsi_lookup_lock
, flags
);
1303 dfailprintk(ioc
, pr_warn(MPT3SAS_FMT
1304 "chain buffers not available\n", ioc
->name
));
1307 chain_req
= list_entry(ioc
->free_chain_list
.next
,
1308 struct chain_tracker
, tracker_list
);
1309 list_del_init(&chain_req
->tracker_list
);
1310 list_add_tail(&chain_req
->tracker_list
,
1311 &ioc
->scsi_lookup
[smid
- 1].chain_list
);
1312 spin_unlock_irqrestore(&ioc
->scsi_lookup_lock
, flags
);
1318 * _base_build_sg - build generic sg
1319 * @ioc: per adapter object
1320 * @psge: virtual address for SGE
1321 * @data_out_dma: physical address for WRITES
1322 * @data_out_sz: data xfer size for WRITES
1323 * @data_in_dma: physical address for READS
1324 * @data_in_sz: data xfer size for READS
1329 _base_build_sg(struct MPT3SAS_ADAPTER
*ioc
, void *psge
,
1330 dma_addr_t data_out_dma
, size_t data_out_sz
, dma_addr_t data_in_dma
,
1335 if (!data_out_sz
&& !data_in_sz
) {
1336 _base_build_zero_len_sge(ioc
, psge
);
1340 if (data_out_sz
&& data_in_sz
) {
1341 /* WRITE sgel first */
1342 sgl_flags
= (MPI2_SGE_FLAGS_SIMPLE_ELEMENT
|
1343 MPI2_SGE_FLAGS_END_OF_BUFFER
| MPI2_SGE_FLAGS_HOST_TO_IOC
);
1344 sgl_flags
= sgl_flags
<< MPI2_SGE_FLAGS_SHIFT
;
1345 ioc
->base_add_sg_single(psge
, sgl_flags
|
1346 data_out_sz
, data_out_dma
);
1349 psge
+= ioc
->sge_size
;
1351 /* READ sgel last */
1352 sgl_flags
= (MPI2_SGE_FLAGS_SIMPLE_ELEMENT
|
1353 MPI2_SGE_FLAGS_LAST_ELEMENT
| MPI2_SGE_FLAGS_END_OF_BUFFER
|
1354 MPI2_SGE_FLAGS_END_OF_LIST
);
1355 sgl_flags
= sgl_flags
<< MPI2_SGE_FLAGS_SHIFT
;
1356 ioc
->base_add_sg_single(psge
, sgl_flags
|
1357 data_in_sz
, data_in_dma
);
1358 } else if (data_out_sz
) /* WRITE */ {
1359 sgl_flags
= (MPI2_SGE_FLAGS_SIMPLE_ELEMENT
|
1360 MPI2_SGE_FLAGS_LAST_ELEMENT
| MPI2_SGE_FLAGS_END_OF_BUFFER
|
1361 MPI2_SGE_FLAGS_END_OF_LIST
| MPI2_SGE_FLAGS_HOST_TO_IOC
);
1362 sgl_flags
= sgl_flags
<< MPI2_SGE_FLAGS_SHIFT
;
1363 ioc
->base_add_sg_single(psge
, sgl_flags
|
1364 data_out_sz
, data_out_dma
);
1365 } else if (data_in_sz
) /* READ */ {
1366 sgl_flags
= (MPI2_SGE_FLAGS_SIMPLE_ELEMENT
|
1367 MPI2_SGE_FLAGS_LAST_ELEMENT
| MPI2_SGE_FLAGS_END_OF_BUFFER
|
1368 MPI2_SGE_FLAGS_END_OF_LIST
);
1369 sgl_flags
= sgl_flags
<< MPI2_SGE_FLAGS_SHIFT
;
1370 ioc
->base_add_sg_single(psge
, sgl_flags
|
1371 data_in_sz
, data_in_dma
);
1375 /* IEEE format sgls */
1378 * _base_build_nvme_prp - This function is called for NVMe end devices to build
1379 * a native SGL (NVMe PRP). The native SGL is built starting in the first PRP
1380 * entry of the NVMe message (PRP1). If the data buffer is small enough to be
1381 * described entirely using PRP1, then PRP2 is not used. If needed, PRP2 is
1382 * used to describe a larger data buffer. If the data buffer is too large to
1383 * describe using the two PRP entriess inside the NVMe message, then PRP1
1384 * describes the first data memory segment, and PRP2 contains a pointer to a PRP
1385 * list located elsewhere in memory to describe the remaining data memory
1386 * segments. The PRP list will be contiguous.
1388 * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP
1389 * consists of a list of PRP entries to describe a number of noncontigous
1390 * physical memory segments as a single memory buffer, just as a SGL does. Note
1391 * however, that this function is only used by the IOCTL call, so the memory
1392 * given will be guaranteed to be contiguous. There is no need to translate
1393 * non-contiguous SGL into a PRP in this case. All PRPs will describe
1394 * contiguous space that is one page size each.
1396 * Each NVMe message contains two PRP entries. The first (PRP1) either contains
1397 * a PRP list pointer or a PRP element, depending upon the command. PRP2
1398 * contains the second PRP element if the memory being described fits within 2
1399 * PRP entries, or a PRP list pointer if the PRP spans more than two entries.
1401 * A PRP list pointer contains the address of a PRP list, structured as a linear
1402 * array of PRP entries. Each PRP entry in this list describes a segment of
1405 * Each 64-bit PRP entry comprises an address and an offset field. The address
1406 * always points at the beginning of a 4KB physical memory page, and the offset
1407 * describes where within that 4KB page the memory segment begins. Only the
1408 * first element in a PRP list may contain a non-zero offest, implying that all
1409 * memory segments following the first begin at the start of a 4KB page.
1411 * Each PRP element normally describes 4KB of physical memory, with exceptions
1412 * for the first and last elements in the list. If the memory being described
1413 * by the list begins at a non-zero offset within the first 4KB page, then the
1414 * first PRP element will contain a non-zero offset indicating where the region
1415 * begins within the 4KB page. The last memory segment may end before the end
1416 * of the 4KB segment, depending upon the overall size of the memory being
1417 * described by the PRP list.
1419 * Since PRP entries lack any indication of size, the overall data buffer length
1420 * is used to determine where the end of the data memory buffer is located, and
1421 * how many PRP entries are required to describe it.
1423 * @ioc: per adapter object
1424 * @smid: system request message index for getting asscociated SGL
1425 * @nvme_encap_request: the NVMe request msg frame pointer
1426 * @data_out_dma: physical address for WRITES
1427 * @data_out_sz: data xfer size for WRITES
1428 * @data_in_dma: physical address for READS
1429 * @data_in_sz: data xfer size for READS
1434 _base_build_nvme_prp(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
,
1435 Mpi26NVMeEncapsulatedRequest_t
*nvme_encap_request
,
1436 dma_addr_t data_out_dma
, size_t data_out_sz
, dma_addr_t data_in_dma
,
1439 int prp_size
= NVME_PRP_SIZE
;
1440 __le64
*prp_entry
, *prp1_entry
, *prp2_entry
;
1442 dma_addr_t prp_entry_dma
, prp_page_dma
, dma_addr
;
1443 u32 offset
, entry_len
;
1444 u32 page_mask_result
, page_mask
;
1448 * Not all commands require a data transfer. If no data, just return
1449 * without constructing any PRP.
1451 if (!data_in_sz
&& !data_out_sz
)
1454 * Set pointers to PRP1 and PRP2, which are in the NVMe command.
1455 * PRP1 is located at a 24 byte offset from the start of the NVMe
1456 * command. Then set the current PRP entry pointer to PRP1.
1458 prp1_entry
= (__le64
*)(nvme_encap_request
->NVMe_Command
+
1459 NVME_CMD_PRP1_OFFSET
);
1460 prp2_entry
= (__le64
*)(nvme_encap_request
->NVMe_Command
+
1461 NVME_CMD_PRP2_OFFSET
);
1462 prp_entry
= prp1_entry
;
1464 * For the PRP entries, use the specially allocated buffer of
1465 * contiguous memory.
1467 prp_page
= (__le64
*)mpt3sas_base_get_pcie_sgl(ioc
, smid
);
1468 prp_page_dma
= mpt3sas_base_get_pcie_sgl_dma(ioc
, smid
);
1471 * Check if we are within 1 entry of a page boundary we don't
1472 * want our first entry to be a PRP List entry.
1474 page_mask
= ioc
->page_size
- 1;
1475 page_mask_result
= (uintptr_t)((u8
*)prp_page
+ prp_size
) & page_mask
;
1476 if (!page_mask_result
) {
1477 /* Bump up to next page boundary. */
1478 prp_page
= (__le64
*)((u8
*)prp_page
+ prp_size
);
1479 prp_page_dma
= prp_page_dma
+ prp_size
;
1483 * Set PRP physical pointer, which initially points to the current PRP
1486 prp_entry_dma
= prp_page_dma
;
1488 /* Get physical address and length of the data buffer. */
1490 dma_addr
= data_in_dma
;
1491 length
= data_in_sz
;
1493 dma_addr
= data_out_dma
;
1494 length
= data_out_sz
;
1497 /* Loop while the length is not zero. */
1500 * Check if we need to put a list pointer here if we are at
1501 * page boundary - prp_size (8 bytes).
1503 page_mask_result
= (prp_entry_dma
+ prp_size
) & page_mask
;
1504 if (!page_mask_result
) {
1506 * This is the last entry in a PRP List, so we need to
1507 * put a PRP list pointer here. What this does is:
1508 * - bump the current memory pointer to the next
1509 * address, which will be the next full page.
1510 * - set the PRP Entry to point to that page. This
1511 * is now the PRP List pointer.
1512 * - bump the PRP Entry pointer the start of the
1513 * next page. Since all of this PRP memory is
1514 * contiguous, no need to get a new page - it's
1515 * just the next address.
1518 *prp_entry
= cpu_to_le64(prp_entry_dma
);
1522 /* Need to handle if entry will be part of a page. */
1523 offset
= dma_addr
& page_mask
;
1524 entry_len
= ioc
->page_size
- offset
;
1526 if (prp_entry
== prp1_entry
) {
1528 * Must fill in the first PRP pointer (PRP1) before
1531 *prp1_entry
= cpu_to_le64(dma_addr
);
1534 * Now point to the second PRP entry within the
1537 prp_entry
= prp2_entry
;
1538 } else if (prp_entry
== prp2_entry
) {
1540 * Should the PRP2 entry be a PRP List pointer or just
1541 * a regular PRP pointer? If there is more than one
1542 * more page of data, must use a PRP List pointer.
1544 if (length
> ioc
->page_size
) {
1546 * PRP2 will contain a PRP List pointer because
1547 * more PRP's are needed with this command. The
1548 * list will start at the beginning of the
1549 * contiguous buffer.
1551 *prp2_entry
= cpu_to_le64(prp_entry_dma
);
1554 * The next PRP Entry will be the start of the
1557 prp_entry
= prp_page
;
1560 * After this, the PRP Entries are complete.
1561 * This command uses 2 PRP's and no PRP list.
1563 *prp2_entry
= cpu_to_le64(dma_addr
);
1567 * Put entry in list and bump the addresses.
1569 * After PRP1 and PRP2 are filled in, this will fill in
1570 * all remaining PRP entries in a PRP List, one per
1571 * each time through the loop.
1573 *prp_entry
= cpu_to_le64(dma_addr
);
1579 * Bump the phys address of the command's data buffer by the
1582 dma_addr
+= entry_len
;
1584 /* Decrement length accounting for last partial page. */
1585 if (entry_len
> length
)
1588 length
-= entry_len
;
1593 * base_make_prp_nvme -
1594 * Prepare PRPs(Physical Region Page)- SGLs specific to NVMe drives only
1596 * @ioc: per adapter object
1597 * @scmd: SCSI command from the mid-layer
1598 * @mpi_request: mpi request
1600 * @sge_count: scatter gather element count.
1602 * Returns: true: PRPs are built
1603 * false: IEEE SGLs needs to be built
1606 base_make_prp_nvme(struct MPT3SAS_ADAPTER
*ioc
,
1607 struct scsi_cmnd
*scmd
,
1608 Mpi25SCSIIORequest_t
*mpi_request
,
1609 u16 smid
, int sge_count
)
1611 int sge_len
, num_prp_in_chain
= 0;
1612 Mpi25IeeeSgeChain64_t
*main_chain_element
, *ptr_first_sgl
;
1614 dma_addr_t msg_dma
, sge_addr
, offset
;
1615 u32 page_mask
, page_mask_result
;
1616 struct scatterlist
*sg_scmd
;
1618 int data_len
= scsi_bufflen(scmd
);
1621 nvme_pg_size
= max_t(u32
, ioc
->page_size
, NVME_PRP_PAGE_SIZE
);
1623 * Nvme has a very convoluted prp format. One prp is required
1624 * for each page or partial page. Driver need to split up OS sg_list
1625 * entries if it is longer than one page or cross a page
1626 * boundary. Driver also have to insert a PRP list pointer entry as
1627 * the last entry in each physical page of the PRP list.
1629 * NOTE: The first PRP "entry" is actually placed in the first
1630 * SGL entry in the main message as IEEE 64 format. The 2nd
1631 * entry in the main message is the chain element, and the rest
1632 * of the PRP entries are built in the contiguous pcie buffer.
1634 page_mask
= nvme_pg_size
- 1;
1637 * Native SGL is needed.
1638 * Put a chain element in main message frame that points to the first
1641 * NOTE: The ChainOffset field must be 0 when using a chain pointer to
1645 /* Set main message chain element pointer */
1646 main_chain_element
= (pMpi25IeeeSgeChain64_t
)&mpi_request
->SGL
;
1648 * For NVMe the chain element needs to be the 2nd SG entry in the main
1651 main_chain_element
= (Mpi25IeeeSgeChain64_t
*)
1652 ((u8
*)main_chain_element
+ sizeof(MPI25_IEEE_SGE_CHAIN64
));
1655 * For the PRP entries, use the specially allocated buffer of
1656 * contiguous memory. Normal chain buffers can't be used
1657 * because each chain buffer would need to be the size of an OS
1660 curr_buff
= mpt3sas_base_get_pcie_sgl(ioc
, smid
);
1661 msg_dma
= mpt3sas_base_get_pcie_sgl_dma(ioc
, smid
);
1663 main_chain_element
->Address
= cpu_to_le64(msg_dma
);
1664 main_chain_element
->NextChainOffset
= 0;
1665 main_chain_element
->Flags
= MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT
|
1666 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR
|
1667 MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP
;
1669 /* Build first prp, sge need not to be page aligned*/
1670 ptr_first_sgl
= (pMpi25IeeeSgeChain64_t
)&mpi_request
->SGL
;
1671 sg_scmd
= scsi_sglist(scmd
);
1672 sge_addr
= sg_dma_address(sg_scmd
);
1673 sge_len
= sg_dma_len(sg_scmd
);
1675 offset
= sge_addr
& page_mask
;
1676 first_prp_len
= nvme_pg_size
- offset
;
1678 ptr_first_sgl
->Address
= cpu_to_le64(sge_addr
);
1679 ptr_first_sgl
->Length
= cpu_to_le32(first_prp_len
);
1681 data_len
-= first_prp_len
;
1683 if (sge_len
> first_prp_len
) {
1684 sge_addr
+= first_prp_len
;
1685 sge_len
-= first_prp_len
;
1686 } else if (data_len
&& (sge_len
== first_prp_len
)) {
1687 sg_scmd
= sg_next(sg_scmd
);
1688 sge_addr
= sg_dma_address(sg_scmd
);
1689 sge_len
= sg_dma_len(sg_scmd
);
1693 offset
= sge_addr
& page_mask
;
1695 /* Put PRP pointer due to page boundary*/
1696 page_mask_result
= (uintptr_t)(curr_buff
+ 1) & page_mask
;
1697 if (unlikely(!page_mask_result
)) {
1698 scmd_printk(KERN_NOTICE
,
1699 scmd
, "page boundary curr_buff: 0x%p\n",
1702 *curr_buff
= cpu_to_le64(msg_dma
);
1707 *curr_buff
= cpu_to_le64(sge_addr
);
1712 sge_addr
+= nvme_pg_size
;
1713 sge_len
-= nvme_pg_size
;
1714 data_len
-= nvme_pg_size
;
1722 sg_scmd
= sg_next(sg_scmd
);
1723 sge_addr
= sg_dma_address(sg_scmd
);
1724 sge_len
= sg_dma_len(sg_scmd
);
1727 main_chain_element
->Length
=
1728 cpu_to_le32(num_prp_in_chain
* sizeof(u64
));
1733 base_is_prp_possible(struct MPT3SAS_ADAPTER
*ioc
,
1734 struct _pcie_device
*pcie_device
, struct scsi_cmnd
*scmd
, int sge_count
)
1736 u32 data_length
= 0;
1737 struct scatterlist
*sg_scmd
;
1738 bool build_prp
= true;
1740 data_length
= scsi_bufflen(scmd
);
1741 sg_scmd
= scsi_sglist(scmd
);
1743 /* If Datalenth is <= 16K and number of SGE’s entries are <= 2
1746 if ((data_length
<= NVME_PRP_PAGE_SIZE
*4) && (sge_count
<= 2))
1753 * _base_check_pcie_native_sgl - This function is called for PCIe end devices to
1754 * determine if the driver needs to build a native SGL. If so, that native
1755 * SGL is built in the special contiguous buffers allocated especially for
1756 * PCIe SGL creation. If the driver will not build a native SGL, return
1757 * TRUE and a normal IEEE SGL will be built. Currently this routine
1759 * @ioc: per adapter object
1760 * @mpi_request: mf request pointer
1761 * @smid: system request message index
1762 * @scmd: scsi command
1763 * @pcie_device: points to the PCIe device's info
1765 * Returns 0 if native SGL was built, 1 if no SGL was built
1768 _base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER
*ioc
,
1769 Mpi25SCSIIORequest_t
*mpi_request
, u16 smid
, struct scsi_cmnd
*scmd
,
1770 struct _pcie_device
*pcie_device
)
1772 struct scatterlist
*sg_scmd
;
1775 /* Get the SG list pointer and info. */
1776 sg_scmd
= scsi_sglist(scmd
);
1777 sges_left
= scsi_dma_map(scmd
);
1778 if (sges_left
< 0) {
1779 sdev_printk(KERN_ERR
, scmd
->device
,
1780 "scsi_dma_map failed: request for %d bytes!\n",
1781 scsi_bufflen(scmd
));
1785 /* Check if we need to build a native SG list. */
1786 if (base_is_prp_possible(ioc
, pcie_device
,
1787 scmd
, sges_left
) == 0) {
1788 /* We built a native SG list, just return. */
1793 * Build native NVMe PRP.
1795 base_make_prp_nvme(ioc
, scmd
, mpi_request
,
1800 scsi_dma_unmap(scmd
);
1805 * _base_add_sg_single_ieee - add sg element for IEEE format
1806 * @paddr: virtual address for SGE
1808 * @chain_offset: number of 128 byte elements from start of segment
1809 * @length: data transfer length
1810 * @dma_addr: Physical address
1815 _base_add_sg_single_ieee(void *paddr
, u8 flags
, u8 chain_offset
, u32 length
,
1816 dma_addr_t dma_addr
)
1818 Mpi25IeeeSgeChain64_t
*sgel
= paddr
;
1820 sgel
->Flags
= flags
;
1821 sgel
->NextChainOffset
= chain_offset
;
1822 sgel
->Length
= cpu_to_le32(length
);
1823 sgel
->Address
= cpu_to_le64(dma_addr
);
1827 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1828 * @ioc: per adapter object
1829 * @paddr: virtual address for SGE
1831 * Create a zero length scatter gather entry to insure the IOCs hardware has
1832 * something to use if the target device goes brain dead and tries
1833 * to send data even when none is asked for.
1838 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER
*ioc
, void *paddr
)
1840 u8 sgl_flags
= (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT
|
1841 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR
|
1842 MPI25_IEEE_SGE_FLAGS_END_OF_LIST
);
1844 _base_add_sg_single_ieee(paddr
, sgl_flags
, 0, 0, -1);
1848 * _base_build_sg_scmd - main sg creation routine
1849 * pcie_device is unused here!
1850 * @ioc: per adapter object
1851 * @scmd: scsi command
1852 * @smid: system request message index
1853 * @unused: unused pcie_device pointer
1856 * The main routine that builds scatter gather table from a given
1857 * scsi request sent via the .queuecommand main handler.
1859 * Returns 0 success, anything else error
1862 _base_build_sg_scmd(struct MPT3SAS_ADAPTER
*ioc
,
1863 struct scsi_cmnd
*scmd
, u16 smid
, struct _pcie_device
*unused
)
1865 Mpi2SCSIIORequest_t
*mpi_request
;
1866 dma_addr_t chain_dma
;
1867 struct scatterlist
*sg_scmd
;
1868 void *sg_local
, *chain
;
1873 u32 sges_in_segment
;
1875 u32 sgl_flags_last_element
;
1876 u32 sgl_flags_end_buffer
;
1877 struct chain_tracker
*chain_req
;
1879 mpi_request
= mpt3sas_base_get_msg_frame(ioc
, smid
);
1881 /* init scatter gather flags */
1882 sgl_flags
= MPI2_SGE_FLAGS_SIMPLE_ELEMENT
;
1883 if (scmd
->sc_data_direction
== DMA_TO_DEVICE
)
1884 sgl_flags
|= MPI2_SGE_FLAGS_HOST_TO_IOC
;
1885 sgl_flags_last_element
= (sgl_flags
| MPI2_SGE_FLAGS_LAST_ELEMENT
)
1886 << MPI2_SGE_FLAGS_SHIFT
;
1887 sgl_flags_end_buffer
= (sgl_flags
| MPI2_SGE_FLAGS_LAST_ELEMENT
|
1888 MPI2_SGE_FLAGS_END_OF_BUFFER
| MPI2_SGE_FLAGS_END_OF_LIST
)
1889 << MPI2_SGE_FLAGS_SHIFT
;
1890 sgl_flags
= sgl_flags
<< MPI2_SGE_FLAGS_SHIFT
;
1892 sg_scmd
= scsi_sglist(scmd
);
1893 sges_left
= scsi_dma_map(scmd
);
1894 if (sges_left
< 0) {
1895 sdev_printk(KERN_ERR
, scmd
->device
,
1896 "pci_map_sg failed: request for %d bytes!\n",
1897 scsi_bufflen(scmd
));
1901 sg_local
= &mpi_request
->SGL
;
1902 sges_in_segment
= ioc
->max_sges_in_main_message
;
1903 if (sges_left
<= sges_in_segment
)
1904 goto fill_in_last_segment
;
1906 mpi_request
->ChainOffset
= (offsetof(Mpi2SCSIIORequest_t
, SGL
) +
1907 (sges_in_segment
* ioc
->sge_size
))/4;
1909 /* fill in main message segment when there is a chain following */
1910 while (sges_in_segment
) {
1911 if (sges_in_segment
== 1)
1912 ioc
->base_add_sg_single(sg_local
,
1913 sgl_flags_last_element
| sg_dma_len(sg_scmd
),
1914 sg_dma_address(sg_scmd
));
1916 ioc
->base_add_sg_single(sg_local
, sgl_flags
|
1917 sg_dma_len(sg_scmd
), sg_dma_address(sg_scmd
));
1918 sg_scmd
= sg_next(sg_scmd
);
1919 sg_local
+= ioc
->sge_size
;
1924 /* initializing the chain flags and pointers */
1925 chain_flags
= MPI2_SGE_FLAGS_CHAIN_ELEMENT
<< MPI2_SGE_FLAGS_SHIFT
;
1926 chain_req
= _base_get_chain_buffer_tracker(ioc
, smid
);
1929 chain
= chain_req
->chain_buffer
;
1930 chain_dma
= chain_req
->chain_buffer_dma
;
1932 sges_in_segment
= (sges_left
<=
1933 ioc
->max_sges_in_chain_message
) ? sges_left
:
1934 ioc
->max_sges_in_chain_message
;
1935 chain_offset
= (sges_left
== sges_in_segment
) ?
1936 0 : (sges_in_segment
* ioc
->sge_size
)/4;
1937 chain_length
= sges_in_segment
* ioc
->sge_size
;
1939 chain_offset
= chain_offset
<<
1940 MPI2_SGE_CHAIN_OFFSET_SHIFT
;
1941 chain_length
+= ioc
->sge_size
;
1943 ioc
->base_add_sg_single(sg_local
, chain_flags
| chain_offset
|
1944 chain_length
, chain_dma
);
1947 goto fill_in_last_segment
;
1949 /* fill in chain segments */
1950 while (sges_in_segment
) {
1951 if (sges_in_segment
== 1)
1952 ioc
->base_add_sg_single(sg_local
,
1953 sgl_flags_last_element
|
1954 sg_dma_len(sg_scmd
),
1955 sg_dma_address(sg_scmd
));
1957 ioc
->base_add_sg_single(sg_local
, sgl_flags
|
1958 sg_dma_len(sg_scmd
),
1959 sg_dma_address(sg_scmd
));
1960 sg_scmd
= sg_next(sg_scmd
);
1961 sg_local
+= ioc
->sge_size
;
1966 chain_req
= _base_get_chain_buffer_tracker(ioc
, smid
);
1969 chain
= chain_req
->chain_buffer
;
1970 chain_dma
= chain_req
->chain_buffer_dma
;
1974 fill_in_last_segment
:
1976 /* fill the last segment */
1979 ioc
->base_add_sg_single(sg_local
, sgl_flags_end_buffer
|
1980 sg_dma_len(sg_scmd
), sg_dma_address(sg_scmd
));
1982 ioc
->base_add_sg_single(sg_local
, sgl_flags
|
1983 sg_dma_len(sg_scmd
), sg_dma_address(sg_scmd
));
1984 sg_scmd
= sg_next(sg_scmd
);
1985 sg_local
+= ioc
->sge_size
;
1993 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
1994 * @ioc: per adapter object
1995 * @scmd: scsi command
1996 * @smid: system request message index
1997 * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be
1998 * constructed on need.
2001 * The main routine that builds scatter gather table from a given
2002 * scsi request sent via the .queuecommand main handler.
2004 * Returns 0 success, anything else error
2007 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER
*ioc
,
2008 struct scsi_cmnd
*scmd
, u16 smid
, struct _pcie_device
*pcie_device
)
2010 Mpi25SCSIIORequest_t
*mpi_request
;
2011 dma_addr_t chain_dma
;
2012 struct scatterlist
*sg_scmd
;
2013 void *sg_local
, *chain
;
2017 u32 sges_in_segment
;
2018 u8 simple_sgl_flags
;
2019 u8 simple_sgl_flags_last
;
2021 struct chain_tracker
*chain_req
;
2023 mpi_request
= mpt3sas_base_get_msg_frame(ioc
, smid
);
2025 /* init scatter gather flags */
2026 simple_sgl_flags
= MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT
|
2027 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR
;
2028 simple_sgl_flags_last
= simple_sgl_flags
|
2029 MPI25_IEEE_SGE_FLAGS_END_OF_LIST
;
2030 chain_sgl_flags
= MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT
|
2031 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR
;
2033 /* Check if we need to build a native SG list. */
2034 if ((pcie_device
) && (_base_check_pcie_native_sgl(ioc
, mpi_request
,
2035 smid
, scmd
, pcie_device
) == 0)) {
2036 /* We built a native SG list, just return. */
2040 sg_scmd
= scsi_sglist(scmd
);
2041 sges_left
= scsi_dma_map(scmd
);
2042 if (sges_left
< 0) {
2043 sdev_printk(KERN_ERR
, scmd
->device
,
2044 "pci_map_sg failed: request for %d bytes!\n",
2045 scsi_bufflen(scmd
));
2049 sg_local
= &mpi_request
->SGL
;
2050 sges_in_segment
= (ioc
->request_sz
-
2051 offsetof(Mpi25SCSIIORequest_t
, SGL
))/ioc
->sge_size_ieee
;
2052 if (sges_left
<= sges_in_segment
)
2053 goto fill_in_last_segment
;
2055 mpi_request
->ChainOffset
= (sges_in_segment
- 1 /* chain element */) +
2056 (offsetof(Mpi25SCSIIORequest_t
, SGL
)/ioc
->sge_size_ieee
);
2058 /* fill in main message segment when there is a chain following */
2059 while (sges_in_segment
> 1) {
2060 _base_add_sg_single_ieee(sg_local
, simple_sgl_flags
, 0,
2061 sg_dma_len(sg_scmd
), sg_dma_address(sg_scmd
));
2062 sg_scmd
= sg_next(sg_scmd
);
2063 sg_local
+= ioc
->sge_size_ieee
;
2068 /* initializing the pointers */
2069 chain_req
= _base_get_chain_buffer_tracker(ioc
, smid
);
2072 chain
= chain_req
->chain_buffer
;
2073 chain_dma
= chain_req
->chain_buffer_dma
;
2075 sges_in_segment
= (sges_left
<=
2076 ioc
->max_sges_in_chain_message
) ? sges_left
:
2077 ioc
->max_sges_in_chain_message
;
2078 chain_offset
= (sges_left
== sges_in_segment
) ?
2079 0 : sges_in_segment
;
2080 chain_length
= sges_in_segment
* ioc
->sge_size_ieee
;
2082 chain_length
+= ioc
->sge_size_ieee
;
2083 _base_add_sg_single_ieee(sg_local
, chain_sgl_flags
,
2084 chain_offset
, chain_length
, chain_dma
);
2088 goto fill_in_last_segment
;
2090 /* fill in chain segments */
2091 while (sges_in_segment
) {
2092 _base_add_sg_single_ieee(sg_local
, simple_sgl_flags
, 0,
2093 sg_dma_len(sg_scmd
), sg_dma_address(sg_scmd
));
2094 sg_scmd
= sg_next(sg_scmd
);
2095 sg_local
+= ioc
->sge_size_ieee
;
2100 chain_req
= _base_get_chain_buffer_tracker(ioc
, smid
);
2103 chain
= chain_req
->chain_buffer
;
2104 chain_dma
= chain_req
->chain_buffer_dma
;
2108 fill_in_last_segment
:
2110 /* fill the last segment */
2111 while (sges_left
> 0) {
2113 _base_add_sg_single_ieee(sg_local
,
2114 simple_sgl_flags_last
, 0, sg_dma_len(sg_scmd
),
2115 sg_dma_address(sg_scmd
));
2117 _base_add_sg_single_ieee(sg_local
, simple_sgl_flags
, 0,
2118 sg_dma_len(sg_scmd
), sg_dma_address(sg_scmd
));
2119 sg_scmd
= sg_next(sg_scmd
);
2120 sg_local
+= ioc
->sge_size_ieee
;
2128 * _base_build_sg_ieee - build generic sg for IEEE format
2129 * @ioc: per adapter object
2130 * @psge: virtual address for SGE
2131 * @data_out_dma: physical address for WRITES
2132 * @data_out_sz: data xfer size for WRITES
2133 * @data_in_dma: physical address for READS
2134 * @data_in_sz: data xfer size for READS
2139 _base_build_sg_ieee(struct MPT3SAS_ADAPTER
*ioc
, void *psge
,
2140 dma_addr_t data_out_dma
, size_t data_out_sz
, dma_addr_t data_in_dma
,
2145 if (!data_out_sz
&& !data_in_sz
) {
2146 _base_build_zero_len_sge_ieee(ioc
, psge
);
2150 if (data_out_sz
&& data_in_sz
) {
2151 /* WRITE sgel first */
2152 sgl_flags
= MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT
|
2153 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR
;
2154 _base_add_sg_single_ieee(psge
, sgl_flags
, 0, data_out_sz
,
2158 psge
+= ioc
->sge_size_ieee
;
2160 /* READ sgel last */
2161 sgl_flags
|= MPI25_IEEE_SGE_FLAGS_END_OF_LIST
;
2162 _base_add_sg_single_ieee(psge
, sgl_flags
, 0, data_in_sz
,
2164 } else if (data_out_sz
) /* WRITE */ {
2165 sgl_flags
= MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT
|
2166 MPI25_IEEE_SGE_FLAGS_END_OF_LIST
|
2167 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR
;
2168 _base_add_sg_single_ieee(psge
, sgl_flags
, 0, data_out_sz
,
2170 } else if (data_in_sz
) /* READ */ {
2171 sgl_flags
= MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT
|
2172 MPI25_IEEE_SGE_FLAGS_END_OF_LIST
|
2173 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR
;
2174 _base_add_sg_single_ieee(psge
, sgl_flags
, 0, data_in_sz
,
2179 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
2182 * _base_config_dma_addressing - set dma addressing
2183 * @ioc: per adapter object
2184 * @pdev: PCI device struct
2186 * Returns 0 for success, non-zero for failure.
2189 _base_config_dma_addressing(struct MPT3SAS_ADAPTER
*ioc
, struct pci_dev
*pdev
)
2192 u64 consistent_dma_mask
;
2195 consistent_dma_mask
= DMA_BIT_MASK(64);
2197 consistent_dma_mask
= DMA_BIT_MASK(32);
2199 if (sizeof(dma_addr_t
) > 4) {
2200 const uint64_t required_mask
=
2201 dma_get_required_mask(&pdev
->dev
);
2202 if ((required_mask
> DMA_BIT_MASK(32)) &&
2203 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) &&
2204 !pci_set_consistent_dma_mask(pdev
, consistent_dma_mask
)) {
2205 ioc
->base_add_sg_single
= &_base_add_sg_single_64
;
2206 ioc
->sge_size
= sizeof(Mpi2SGESimple64_t
);
2212 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(32))
2213 && !pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32))) {
2214 ioc
->base_add_sg_single
= &_base_add_sg_single_32
;
2215 ioc
->sge_size
= sizeof(Mpi2SGESimple32_t
);
2223 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
2224 ioc
->name
, ioc
->dma_mask
, convert_to_kb(s
.totalram
));
2230 _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER
*ioc
,
2231 struct pci_dev
*pdev
)
2233 if (pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64))) {
2234 if (pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)))
2241 * _base_check_enable_msix - checks MSIX capabable.
2242 * @ioc: per adapter object
2244 * Check to see if card is capable of MSIX, and set number
2245 * of available msix vectors
2248 _base_check_enable_msix(struct MPT3SAS_ADAPTER
*ioc
)
2251 u16 message_control
;
2253 /* Check whether controller SAS2008 B0 controller,
2254 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
2256 if (ioc
->pdev
->device
== MPI2_MFGPAGE_DEVID_SAS2008
&&
2257 ioc
->pdev
->revision
== SAS2_PCI_DEVICE_B0_REVISION
) {
2261 base
= pci_find_capability(ioc
->pdev
, PCI_CAP_ID_MSIX
);
2263 dfailprintk(ioc
, pr_info(MPT3SAS_FMT
"msix not supported\n",
2268 /* get msix vector count */
2269 /* NUMA_IO not supported for older controllers */
2270 if (ioc
->pdev
->device
== MPI2_MFGPAGE_DEVID_SAS2004
||
2271 ioc
->pdev
->device
== MPI2_MFGPAGE_DEVID_SAS2008
||
2272 ioc
->pdev
->device
== MPI2_MFGPAGE_DEVID_SAS2108_1
||
2273 ioc
->pdev
->device
== MPI2_MFGPAGE_DEVID_SAS2108_2
||
2274 ioc
->pdev
->device
== MPI2_MFGPAGE_DEVID_SAS2108_3
||
2275 ioc
->pdev
->device
== MPI2_MFGPAGE_DEVID_SAS2116_1
||
2276 ioc
->pdev
->device
== MPI2_MFGPAGE_DEVID_SAS2116_2
)
2277 ioc
->msix_vector_count
= 1;
2279 pci_read_config_word(ioc
->pdev
, base
+ 2, &message_control
);
2280 ioc
->msix_vector_count
= (message_control
& 0x3FF) + 1;
2282 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
2283 "msix is supported, vector_count(%d)\n",
2284 ioc
->name
, ioc
->msix_vector_count
));
2289 * _base_free_irq - free irq
2290 * @ioc: per adapter object
2292 * Freeing respective reply_queue from the list.
2295 _base_free_irq(struct MPT3SAS_ADAPTER
*ioc
)
2297 struct adapter_reply_queue
*reply_q
, *next
;
2299 if (list_empty(&ioc
->reply_queue_list
))
2302 list_for_each_entry_safe(reply_q
, next
, &ioc
->reply_queue_list
, list
) {
2303 list_del(&reply_q
->list
);
2304 free_irq(pci_irq_vector(ioc
->pdev
, reply_q
->msix_index
),
2311 * _base_request_irq - request irq
2312 * @ioc: per adapter object
2313 * @index: msix index into vector table
2315 * Inserting respective reply_queue into the list.
2318 _base_request_irq(struct MPT3SAS_ADAPTER
*ioc
, u8 index
)
2320 struct pci_dev
*pdev
= ioc
->pdev
;
2321 struct adapter_reply_queue
*reply_q
;
2324 reply_q
= kzalloc(sizeof(struct adapter_reply_queue
), GFP_KERNEL
);
2326 pr_err(MPT3SAS_FMT
"unable to allocate memory %d!\n",
2327 ioc
->name
, (int)sizeof(struct adapter_reply_queue
));
2331 reply_q
->msix_index
= index
;
2333 atomic_set(&reply_q
->busy
, 0);
2334 if (ioc
->msix_enable
)
2335 snprintf(reply_q
->name
, MPT_NAME_LENGTH
, "%s%d-msix%d",
2336 ioc
->driver_name
, ioc
->id
, index
);
2338 snprintf(reply_q
->name
, MPT_NAME_LENGTH
, "%s%d",
2339 ioc
->driver_name
, ioc
->id
);
2340 r
= request_irq(pci_irq_vector(pdev
, index
), _base_interrupt
,
2341 IRQF_SHARED
, reply_q
->name
, reply_q
);
2343 pr_err(MPT3SAS_FMT
"unable to allocate interrupt %d!\n",
2344 reply_q
->name
, pci_irq_vector(pdev
, index
));
2349 INIT_LIST_HEAD(&reply_q
->list
);
2350 list_add_tail(&reply_q
->list
, &ioc
->reply_queue_list
);
2355 * _base_assign_reply_queues - assigning msix index for each cpu
2356 * @ioc: per adapter object
2358 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
2360 * It would nice if we could call irq_set_affinity, however it is not
2361 * an exported symbol
2364 _base_assign_reply_queues(struct MPT3SAS_ADAPTER
*ioc
)
2366 unsigned int cpu
, nr_cpus
, nr_msix
, index
= 0;
2367 struct adapter_reply_queue
*reply_q
;
2369 if (!_base_is_controller_msix_enabled(ioc
))
2372 memset(ioc
->cpu_msix_table
, 0, ioc
->cpu_msix_table_sz
);
2374 nr_cpus
= num_online_cpus();
2375 nr_msix
= ioc
->reply_queue_count
= min(ioc
->reply_queue_count
,
2376 ioc
->facts
.MaxMSIxVectors
);
2380 if (smp_affinity_enable
) {
2381 list_for_each_entry(reply_q
, &ioc
->reply_queue_list
, list
) {
2382 const cpumask_t
*mask
= pci_irq_get_affinity(ioc
->pdev
,
2383 reply_q
->msix_index
);
2385 pr_warn(MPT3SAS_FMT
"no affinity for msi %x\n",
2386 ioc
->name
, reply_q
->msix_index
);
2390 for_each_cpu(cpu
, mask
)
2391 ioc
->cpu_msix_table
[cpu
] = reply_q
->msix_index
;
2395 cpu
= cpumask_first(cpu_online_mask
);
2397 list_for_each_entry(reply_q
, &ioc
->reply_queue_list
, list
) {
2399 unsigned int i
, group
= nr_cpus
/ nr_msix
;
2404 if (index
< nr_cpus
% nr_msix
)
2407 for (i
= 0 ; i
< group
; i
++) {
2408 ioc
->cpu_msix_table
[cpu
] = reply_q
->msix_index
;
2409 cpu
= cpumask_next(cpu
, cpu_online_mask
);
2416 * _base_disable_msix - disables msix
2417 * @ioc: per adapter object
2421 _base_disable_msix(struct MPT3SAS_ADAPTER
*ioc
)
2423 if (!ioc
->msix_enable
)
2425 pci_disable_msix(ioc
->pdev
);
2426 ioc
->msix_enable
= 0;
2430 * _base_enable_msix - enables msix, failback to io_apic
2431 * @ioc: per adapter object
2435 _base_enable_msix(struct MPT3SAS_ADAPTER
*ioc
)
2438 int i
, local_max_msix_vectors
;
2440 unsigned int irq_flags
= PCI_IRQ_MSIX
;
2442 if (msix_disable
== -1 || msix_disable
== 0)
2448 if (_base_check_enable_msix(ioc
) != 0)
2451 ioc
->reply_queue_count
= min_t(int, ioc
->cpu_count
,
2452 ioc
->msix_vector_count
);
2454 printk(MPT3SAS_FMT
"MSI-X vectors supported: %d, no of cores"
2455 ": %d, max_msix_vectors: %d\n", ioc
->name
, ioc
->msix_vector_count
,
2456 ioc
->cpu_count
, max_msix_vectors
);
2458 if (!ioc
->rdpq_array_enable
&& max_msix_vectors
== -1)
2459 local_max_msix_vectors
= (reset_devices
) ? 1 : 8;
2461 local_max_msix_vectors
= max_msix_vectors
;
2463 if (local_max_msix_vectors
> 0)
2464 ioc
->reply_queue_count
= min_t(int, local_max_msix_vectors
,
2465 ioc
->reply_queue_count
);
2466 else if (local_max_msix_vectors
== 0)
2469 if (ioc
->msix_vector_count
< ioc
->cpu_count
)
2470 smp_affinity_enable
= 0;
2472 if (smp_affinity_enable
)
2473 irq_flags
|= PCI_IRQ_AFFINITY
;
2475 r
= pci_alloc_irq_vectors(ioc
->pdev
, 1, ioc
->reply_queue_count
,
2478 dfailprintk(ioc
, pr_info(MPT3SAS_FMT
2479 "pci_alloc_irq_vectors failed (r=%d) !!!\n",
2484 ioc
->msix_enable
= 1;
2485 ioc
->reply_queue_count
= r
;
2486 for (i
= 0; i
< ioc
->reply_queue_count
; i
++) {
2487 r
= _base_request_irq(ioc
, i
);
2489 _base_free_irq(ioc
);
2490 _base_disable_msix(ioc
);
2497 /* failback to io_apic interrupt routing */
2500 ioc
->reply_queue_count
= 1;
2501 r
= pci_alloc_irq_vectors(ioc
->pdev
, 1, 1, PCI_IRQ_LEGACY
);
2503 dfailprintk(ioc
, pr_info(MPT3SAS_FMT
2504 "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n",
2507 r
= _base_request_irq(ioc
, 0);
2513 * mpt3sas_base_unmap_resources - free controller resources
2514 * @ioc: per adapter object
2517 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER
*ioc
)
2519 struct pci_dev
*pdev
= ioc
->pdev
;
2521 dexitprintk(ioc
, printk(MPT3SAS_FMT
"%s\n",
2522 ioc
->name
, __func__
));
2524 _base_free_irq(ioc
);
2525 _base_disable_msix(ioc
);
2527 if (ioc
->combined_reply_queue
) {
2528 kfree(ioc
->replyPostRegisterIndex
);
2529 ioc
->replyPostRegisterIndex
= NULL
;
2532 if (ioc
->chip_phys
) {
2537 if (pci_is_enabled(pdev
)) {
2538 pci_release_selected_regions(ioc
->pdev
, ioc
->bars
);
2539 pci_disable_pcie_error_reporting(pdev
);
2540 pci_disable_device(pdev
);
2545 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
2546 * @ioc: per adapter object
2548 * Returns 0 for success, non-zero for failure.
2551 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER
*ioc
)
2553 struct pci_dev
*pdev
= ioc
->pdev
;
2559 struct adapter_reply_queue
*reply_q
;
2561 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s\n",
2562 ioc
->name
, __func__
));
2564 ioc
->bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
2565 if (pci_enable_device_mem(pdev
)) {
2566 pr_warn(MPT3SAS_FMT
"pci_enable_device_mem: failed\n",
2573 if (pci_request_selected_regions(pdev
, ioc
->bars
,
2574 ioc
->driver_name
)) {
2575 pr_warn(MPT3SAS_FMT
"pci_request_selected_regions: failed\n",
2582 /* AER (Advanced Error Reporting) hooks */
2583 pci_enable_pcie_error_reporting(pdev
);
2585 pci_set_master(pdev
);
2588 if (_base_config_dma_addressing(ioc
, pdev
) != 0) {
2589 pr_warn(MPT3SAS_FMT
"no suitable DMA mask for %s\n",
2590 ioc
->name
, pci_name(pdev
));
2595 for (i
= 0, memap_sz
= 0, pio_sz
= 0; (i
< DEVICE_COUNT_RESOURCE
) &&
2596 (!memap_sz
|| !pio_sz
); i
++) {
2597 if (pci_resource_flags(pdev
, i
) & IORESOURCE_IO
) {
2600 pio_chip
= (u64
)pci_resource_start(pdev
, i
);
2601 pio_sz
= pci_resource_len(pdev
, i
);
2602 } else if (pci_resource_flags(pdev
, i
) & IORESOURCE_MEM
) {
2605 ioc
->chip_phys
= pci_resource_start(pdev
, i
);
2606 chip_phys
= (u64
)ioc
->chip_phys
;
2607 memap_sz
= pci_resource_len(pdev
, i
);
2608 ioc
->chip
= ioremap(ioc
->chip_phys
, memap_sz
);
2612 if (ioc
->chip
== NULL
) {
2613 pr_err(MPT3SAS_FMT
"unable to map adapter memory! "
2614 " or resource not found\n", ioc
->name
);
2619 _base_mask_interrupts(ioc
);
2621 r
= _base_get_ioc_facts(ioc
);
2625 if (!ioc
->rdpq_array_enable_assigned
) {
2626 ioc
->rdpq_array_enable
= ioc
->rdpq_array_capable
;
2627 ioc
->rdpq_array_enable_assigned
= 1;
2630 r
= _base_enable_msix(ioc
);
2634 /* Use the Combined reply queue feature only for SAS3 C0 & higher
2635 * revision HBAs and also only when reply queue count is greater than 8
2637 if (ioc
->combined_reply_queue
&& ioc
->reply_queue_count
> 8) {
2638 /* Determine the Supplemental Reply Post Host Index Registers
2639 * Addresse. Supplemental Reply Post Host Index Registers
2640 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
2641 * each register is at offset bytes of
2642 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
2644 ioc
->replyPostRegisterIndex
= kcalloc(
2645 ioc
->combined_reply_index_count
,
2646 sizeof(resource_size_t
*), GFP_KERNEL
);
2647 if (!ioc
->replyPostRegisterIndex
) {
2648 dfailprintk(ioc
, printk(MPT3SAS_FMT
2649 "allocation for reply Post Register Index failed!!!\n",
2655 for (i
= 0; i
< ioc
->combined_reply_index_count
; i
++) {
2656 ioc
->replyPostRegisterIndex
[i
] = (resource_size_t
*)
2657 ((u8
*)&ioc
->chip
->Doorbell
+
2658 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET
+
2659 (i
* MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET
));
2662 ioc
->combined_reply_queue
= 0;
2664 if (ioc
->is_warpdrive
) {
2665 ioc
->reply_post_host_index
[0] = (resource_size_t __iomem
*)
2666 &ioc
->chip
->ReplyPostHostIndex
;
2668 for (i
= 1; i
< ioc
->cpu_msix_table_sz
; i
++)
2669 ioc
->reply_post_host_index
[i
] =
2670 (resource_size_t __iomem
*)
2671 ((u8 __iomem
*)&ioc
->chip
->Doorbell
+ (0x4000 + ((i
- 1)
2675 list_for_each_entry(reply_q
, &ioc
->reply_queue_list
, list
)
2676 pr_info(MPT3SAS_FMT
"%s: IRQ %d\n",
2677 reply_q
->name
, ((ioc
->msix_enable
) ? "PCI-MSI-X enabled" :
2679 pci_irq_vector(ioc
->pdev
, reply_q
->msix_index
));
2681 pr_info(MPT3SAS_FMT
"iomem(0x%016llx), mapped(0x%p), size(%d)\n",
2682 ioc
->name
, (unsigned long long)chip_phys
, ioc
->chip
, memap_sz
);
2683 pr_info(MPT3SAS_FMT
"ioport(0x%016llx), size(%d)\n",
2684 ioc
->name
, (unsigned long long)pio_chip
, pio_sz
);
2686 /* Save PCI configuration state for recovery from PCI AER/EEH errors */
2687 pci_save_state(pdev
);
2691 mpt3sas_base_unmap_resources(ioc
);
2696 * mpt3sas_base_get_msg_frame - obtain request mf pointer
2697 * @ioc: per adapter object
2698 * @smid: system request message index(smid zero is invalid)
2700 * Returns virt pointer to message frame.
2703 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
)
2705 return (void *)(ioc
->request
+ (smid
* ioc
->request_sz
));
2709 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
2710 * @ioc: per adapter object
2711 * @smid: system request message index
2713 * Returns virt pointer to sense buffer.
2716 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
)
2718 return (void *)(ioc
->sense
+ ((smid
- 1) * SCSI_SENSE_BUFFERSIZE
));
2722 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
2723 * @ioc: per adapter object
2724 * @smid: system request message index
2726 * Returns phys pointer to the low 32bit address of the sense buffer.
2729 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
)
2731 return cpu_to_le32(ioc
->sense_dma
+ ((smid
- 1) *
2732 SCSI_SENSE_BUFFERSIZE
));
2736 * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr
2737 * @ioc: per adapter object
2738 * @smid: system request message index
2740 * Returns virt pointer to a PCIe SGL.
2743 mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
)
2745 return (void *)(ioc
->scsi_lookup
[smid
- 1].pcie_sg_list
.pcie_sgl
);
2749 * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr
2750 * @ioc: per adapter object
2751 * @smid: system request message index
2753 * Returns phys pointer to the address of the PCIe buffer.
2756 mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
)
2758 return ioc
->scsi_lookup
[smid
- 1].pcie_sg_list
.pcie_sgl_dma
;
2762 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
2763 * @ioc: per adapter object
2764 * @phys_addr: lower 32 physical addr of the reply
2766 * Converts 32bit lower physical addr into a virt address.
2769 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER
*ioc
, u32 phys_addr
)
2773 return ioc
->reply
+ (phys_addr
- (u32
)ioc
->reply_dma
);
2777 _base_get_msix_index(struct MPT3SAS_ADAPTER
*ioc
)
2779 return ioc
->cpu_msix_table
[raw_smp_processor_id()];
2783 * mpt3sas_base_get_smid - obtain a free smid from internal queue
2784 * @ioc: per adapter object
2785 * @cb_idx: callback index
2787 * Returns smid (zero is invalid)
2790 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER
*ioc
, u8 cb_idx
)
2792 unsigned long flags
;
2793 struct request_tracker
*request
;
2796 spin_lock_irqsave(&ioc
->scsi_lookup_lock
, flags
);
2797 if (list_empty(&ioc
->internal_free_list
)) {
2798 spin_unlock_irqrestore(&ioc
->scsi_lookup_lock
, flags
);
2799 pr_err(MPT3SAS_FMT
"%s: smid not available\n",
2800 ioc
->name
, __func__
);
2804 request
= list_entry(ioc
->internal_free_list
.next
,
2805 struct request_tracker
, tracker_list
);
2806 request
->cb_idx
= cb_idx
;
2807 smid
= request
->smid
;
2808 list_del(&request
->tracker_list
);
2809 spin_unlock_irqrestore(&ioc
->scsi_lookup_lock
, flags
);
2814 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
2815 * @ioc: per adapter object
2816 * @cb_idx: callback index
2817 * @scmd: pointer to scsi command object
2819 * Returns smid (zero is invalid)
2822 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER
*ioc
, u8 cb_idx
,
2823 struct scsi_cmnd
*scmd
)
2825 unsigned long flags
;
2826 struct scsiio_tracker
*request
;
2829 spin_lock_irqsave(&ioc
->scsi_lookup_lock
, flags
);
2830 if (list_empty(&ioc
->free_list
)) {
2831 spin_unlock_irqrestore(&ioc
->scsi_lookup_lock
, flags
);
2832 pr_err(MPT3SAS_FMT
"%s: smid not available\n",
2833 ioc
->name
, __func__
);
2837 request
= list_entry(ioc
->free_list
.next
,
2838 struct scsiio_tracker
, tracker_list
);
2839 request
->scmd
= scmd
;
2840 request
->cb_idx
= cb_idx
;
2841 smid
= request
->smid
;
2842 request
->msix_io
= _base_get_msix_index(ioc
);
2843 list_del(&request
->tracker_list
);
2844 spin_unlock_irqrestore(&ioc
->scsi_lookup_lock
, flags
);
2849 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2850 * @ioc: per adapter object
2851 * @cb_idx: callback index
2853 * Returns smid (zero is invalid)
2856 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER
*ioc
, u8 cb_idx
)
2858 unsigned long flags
;
2859 struct request_tracker
*request
;
2862 spin_lock_irqsave(&ioc
->scsi_lookup_lock
, flags
);
2863 if (list_empty(&ioc
->hpr_free_list
)) {
2864 spin_unlock_irqrestore(&ioc
->scsi_lookup_lock
, flags
);
2868 request
= list_entry(ioc
->hpr_free_list
.next
,
2869 struct request_tracker
, tracker_list
);
2870 request
->cb_idx
= cb_idx
;
2871 smid
= request
->smid
;
2872 list_del(&request
->tracker_list
);
2873 spin_unlock_irqrestore(&ioc
->scsi_lookup_lock
, flags
);
2878 * mpt3sas_base_free_smid - put smid back on free_list
2879 * @ioc: per adapter object
2880 * @smid: system request message index
2885 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
)
2887 unsigned long flags
;
2889 struct chain_tracker
*chain_req
, *next
;
2891 spin_lock_irqsave(&ioc
->scsi_lookup_lock
, flags
);
2892 if (smid
< ioc
->hi_priority_smid
) {
2895 if (!list_empty(&ioc
->scsi_lookup
[i
].chain_list
)) {
2896 list_for_each_entry_safe(chain_req
, next
,
2897 &ioc
->scsi_lookup
[i
].chain_list
, tracker_list
) {
2898 list_del_init(&chain_req
->tracker_list
);
2899 list_add(&chain_req
->tracker_list
,
2900 &ioc
->free_chain_list
);
2903 ioc
->scsi_lookup
[i
].cb_idx
= 0xFF;
2904 ioc
->scsi_lookup
[i
].scmd
= NULL
;
2905 ioc
->scsi_lookup
[i
].direct_io
= 0;
2906 list_add(&ioc
->scsi_lookup
[i
].tracker_list
, &ioc
->free_list
);
2907 spin_unlock_irqrestore(&ioc
->scsi_lookup_lock
, flags
);
2910 * See _wait_for_commands_to_complete() call with regards
2913 if (ioc
->shost_recovery
&& ioc
->pending_io_count
) {
2914 if (ioc
->pending_io_count
== 1)
2915 wake_up(&ioc
->reset_wq
);
2916 ioc
->pending_io_count
--;
2919 } else if (smid
< ioc
->internal_smid
) {
2921 i
= smid
- ioc
->hi_priority_smid
;
2922 ioc
->hpr_lookup
[i
].cb_idx
= 0xFF;
2923 list_add(&ioc
->hpr_lookup
[i
].tracker_list
, &ioc
->hpr_free_list
);
2924 } else if (smid
<= ioc
->hba_queue_depth
) {
2925 /* internal queue */
2926 i
= smid
- ioc
->internal_smid
;
2927 ioc
->internal_lookup
[i
].cb_idx
= 0xFF;
2928 list_add(&ioc
->internal_lookup
[i
].tracker_list
,
2929 &ioc
->internal_free_list
);
2931 spin_unlock_irqrestore(&ioc
->scsi_lookup_lock
, flags
);
2935 * _base_writeq - 64 bit write to MMIO
2936 * @ioc: per adapter object
2938 * @addr: address in MMIO space
2939 * @writeq_lock: spin lock
2941 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2942 * care of 32 bit environment where its not quarenteed to send the entire word
2945 #if defined(writeq) && defined(CONFIG_64BIT)
2947 _base_writeq(__u64 b
, volatile void __iomem
*addr
, spinlock_t
*writeq_lock
)
2949 writeq(cpu_to_le64(b
), addr
);
2953 _base_writeq(__u64 b
, volatile void __iomem
*addr
, spinlock_t
*writeq_lock
)
2955 unsigned long flags
;
2956 __u64 data_out
= cpu_to_le64(b
);
2958 spin_lock_irqsave(writeq_lock
, flags
);
2959 writel((u32
)(data_out
), addr
);
2960 writel((u32
)(data_out
>> 32), (addr
+ 4));
2961 spin_unlock_irqrestore(writeq_lock
, flags
);
2966 * _base_put_smid_scsi_io - send SCSI_IO request to firmware
2967 * @ioc: per adapter object
2968 * @smid: system request message index
2969 * @handle: device handle
2974 _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
, u16 handle
)
2976 Mpi2RequestDescriptorUnion_t descriptor
;
2977 u64
*request
= (u64
*)&descriptor
;
2980 descriptor
.SCSIIO
.RequestFlags
= MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO
;
2981 descriptor
.SCSIIO
.MSIxIndex
= _base_get_msix_index(ioc
);
2982 descriptor
.SCSIIO
.SMID
= cpu_to_le16(smid
);
2983 descriptor
.SCSIIO
.DevHandle
= cpu_to_le16(handle
);
2984 descriptor
.SCSIIO
.LMID
= 0;
2985 _base_writeq(*request
, &ioc
->chip
->RequestDescriptorPostLow
,
2986 &ioc
->scsi_lookup_lock
);
2990 * _base_put_smid_fast_path - send fast path request to firmware
2991 * @ioc: per adapter object
2992 * @smid: system request message index
2993 * @handle: device handle
2998 _base_put_smid_fast_path(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
,
3001 Mpi2RequestDescriptorUnion_t descriptor
;
3002 u64
*request
= (u64
*)&descriptor
;
3004 descriptor
.SCSIIO
.RequestFlags
=
3005 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO
;
3006 descriptor
.SCSIIO
.MSIxIndex
= _base_get_msix_index(ioc
);
3007 descriptor
.SCSIIO
.SMID
= cpu_to_le16(smid
);
3008 descriptor
.SCSIIO
.DevHandle
= cpu_to_le16(handle
);
3009 descriptor
.SCSIIO
.LMID
= 0;
3010 _base_writeq(*request
, &ioc
->chip
->RequestDescriptorPostLow
,
3011 &ioc
->scsi_lookup_lock
);
3015 * _base_put_smid_hi_priority - send Task Management request to firmware
3016 * @ioc: per adapter object
3017 * @smid: system request message index
3018 * @msix_task: msix_task will be same as msix of IO incase of task abort else 0.
3022 _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
,
3025 Mpi2RequestDescriptorUnion_t descriptor
;
3026 u64
*request
= (u64
*)&descriptor
;
3028 descriptor
.HighPriority
.RequestFlags
=
3029 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY
;
3030 descriptor
.HighPriority
.MSIxIndex
= msix_task
;
3031 descriptor
.HighPriority
.SMID
= cpu_to_le16(smid
);
3032 descriptor
.HighPriority
.LMID
= 0;
3033 descriptor
.HighPriority
.Reserved1
= 0;
3034 _base_writeq(*request
, &ioc
->chip
->RequestDescriptorPostLow
,
3035 &ioc
->scsi_lookup_lock
);
3039 * _base_put_smid_nvme_encap - send NVMe encapsulated request to
3041 * @ioc: per adapter object
3042 * @smid: system request message index
3047 _base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
)
3049 Mpi2RequestDescriptorUnion_t descriptor
;
3050 u64
*request
= (u64
*)&descriptor
;
3052 descriptor
.Default
.RequestFlags
=
3053 MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED
;
3054 descriptor
.Default
.MSIxIndex
= _base_get_msix_index(ioc
);
3055 descriptor
.Default
.SMID
= cpu_to_le16(smid
);
3056 descriptor
.Default
.LMID
= 0;
3057 descriptor
.Default
.DescriptorTypeDependent
= 0;
3058 _base_writeq(*request
, &ioc
->chip
->RequestDescriptorPostLow
,
3059 &ioc
->scsi_lookup_lock
);
3063 * _base_put_smid_default - Default, primarily used for config pages
3064 * @ioc: per adapter object
3065 * @smid: system request message index
3070 _base_put_smid_default(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
)
3072 Mpi2RequestDescriptorUnion_t descriptor
;
3073 u64
*request
= (u64
*)&descriptor
;
3075 descriptor
.Default
.RequestFlags
= MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE
;
3076 descriptor
.Default
.MSIxIndex
= _base_get_msix_index(ioc
);
3077 descriptor
.Default
.SMID
= cpu_to_le16(smid
);
3078 descriptor
.Default
.LMID
= 0;
3079 descriptor
.Default
.DescriptorTypeDependent
= 0;
3080 _base_writeq(*request
, &ioc
->chip
->RequestDescriptorPostLow
,
3081 &ioc
->scsi_lookup_lock
);
3085 * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using
3086 * Atomic Request Descriptor
3087 * @ioc: per adapter object
3088 * @smid: system request message index
3089 * @handle: device handle, unused in this function, for function type match
3094 _base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
,
3097 Mpi26AtomicRequestDescriptor_t descriptor
;
3098 u32
*request
= (u32
*)&descriptor
;
3100 descriptor
.RequestFlags
= MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO
;
3101 descriptor
.MSIxIndex
= _base_get_msix_index(ioc
);
3102 descriptor
.SMID
= cpu_to_le16(smid
);
3104 writel(cpu_to_le32(*request
), &ioc
->chip
->AtomicRequestDescriptorPost
);
3108 * _base_put_smid_fast_path_atomic - send fast path request to firmware
3109 * using Atomic Request Descriptor
3110 * @ioc: per adapter object
3111 * @smid: system request message index
3112 * @handle: device handle, unused in this function, for function type match
3116 _base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
,
3119 Mpi26AtomicRequestDescriptor_t descriptor
;
3120 u32
*request
= (u32
*)&descriptor
;
3122 descriptor
.RequestFlags
= MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO
;
3123 descriptor
.MSIxIndex
= _base_get_msix_index(ioc
);
3124 descriptor
.SMID
= cpu_to_le16(smid
);
3126 writel(cpu_to_le32(*request
), &ioc
->chip
->AtomicRequestDescriptorPost
);
3130 * _base_put_smid_hi_priority_atomic - send Task Management request to
3131 * firmware using Atomic Request Descriptor
3132 * @ioc: per adapter object
3133 * @smid: system request message index
3134 * @msix_task: msix_task will be same as msix of IO incase of task abort else 0
3139 _base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
,
3142 Mpi26AtomicRequestDescriptor_t descriptor
;
3143 u32
*request
= (u32
*)&descriptor
;
3145 descriptor
.RequestFlags
= MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY
;
3146 descriptor
.MSIxIndex
= msix_task
;
3147 descriptor
.SMID
= cpu_to_le16(smid
);
3149 writel(cpu_to_le32(*request
), &ioc
->chip
->AtomicRequestDescriptorPost
);
3153 * _base_put_smid_nvme_encap_atomic - send NVMe encapsulated request to
3154 * firmware using Atomic Request Descriptor
3155 * @ioc: per adapter object
3156 * @smid: system request message index
3161 _base_put_smid_nvme_encap_atomic(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
)
3163 Mpi26AtomicRequestDescriptor_t descriptor
;
3164 u32
*request
= (u32
*)&descriptor
;
3166 descriptor
.RequestFlags
= MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED
;
3167 descriptor
.MSIxIndex
= _base_get_msix_index(ioc
);
3168 descriptor
.SMID
= cpu_to_le16(smid
);
3170 writel(cpu_to_le32(*request
), &ioc
->chip
->AtomicRequestDescriptorPost
);
3174 * _base_put_smid_default - Default, primarily used for config pages
3175 * use Atomic Request Descriptor
3176 * @ioc: per adapter object
3177 * @smid: system request message index
3182 _base_put_smid_default_atomic(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
)
3184 Mpi26AtomicRequestDescriptor_t descriptor
;
3185 u32
*request
= (u32
*)&descriptor
;
3187 descriptor
.RequestFlags
= MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE
;
3188 descriptor
.MSIxIndex
= _base_get_msix_index(ioc
);
3189 descriptor
.SMID
= cpu_to_le16(smid
);
3191 writel(cpu_to_le32(*request
), &ioc
->chip
->AtomicRequestDescriptorPost
);
3195 * _base_display_OEMs_branding - Display branding string
3196 * @ioc: per adapter object
3201 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER
*ioc
)
3203 if (ioc
->pdev
->subsystem_vendor
!= PCI_VENDOR_ID_INTEL
)
3206 switch (ioc
->pdev
->subsystem_vendor
) {
3207 case PCI_VENDOR_ID_INTEL
:
3208 switch (ioc
->pdev
->device
) {
3209 case MPI2_MFGPAGE_DEVID_SAS2008
:
3210 switch (ioc
->pdev
->subsystem_device
) {
3211 case MPT2SAS_INTEL_RMS2LL080_SSDID
:
3212 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3213 MPT2SAS_INTEL_RMS2LL080_BRANDING
);
3215 case MPT2SAS_INTEL_RMS2LL040_SSDID
:
3216 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3217 MPT2SAS_INTEL_RMS2LL040_BRANDING
);
3219 case MPT2SAS_INTEL_SSD910_SSDID
:
3220 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3221 MPT2SAS_INTEL_SSD910_BRANDING
);
3225 "Intel(R) Controller: Subsystem ID: 0x%X\n",
3226 ioc
->name
, ioc
->pdev
->subsystem_device
);
3229 case MPI2_MFGPAGE_DEVID_SAS2308_2
:
3230 switch (ioc
->pdev
->subsystem_device
) {
3231 case MPT2SAS_INTEL_RS25GB008_SSDID
:
3232 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3233 MPT2SAS_INTEL_RS25GB008_BRANDING
);
3235 case MPT2SAS_INTEL_RMS25JB080_SSDID
:
3236 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3237 MPT2SAS_INTEL_RMS25JB080_BRANDING
);
3239 case MPT2SAS_INTEL_RMS25JB040_SSDID
:
3240 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3241 MPT2SAS_INTEL_RMS25JB040_BRANDING
);
3243 case MPT2SAS_INTEL_RMS25KB080_SSDID
:
3244 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3245 MPT2SAS_INTEL_RMS25KB080_BRANDING
);
3247 case MPT2SAS_INTEL_RMS25KB040_SSDID
:
3248 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3249 MPT2SAS_INTEL_RMS25KB040_BRANDING
);
3251 case MPT2SAS_INTEL_RMS25LB040_SSDID
:
3252 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3253 MPT2SAS_INTEL_RMS25LB040_BRANDING
);
3255 case MPT2SAS_INTEL_RMS25LB080_SSDID
:
3256 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3257 MPT2SAS_INTEL_RMS25LB080_BRANDING
);
3261 "Intel(R) Controller: Subsystem ID: 0x%X\n",
3262 ioc
->name
, ioc
->pdev
->subsystem_device
);
3265 case MPI25_MFGPAGE_DEVID_SAS3008
:
3266 switch (ioc
->pdev
->subsystem_device
) {
3267 case MPT3SAS_INTEL_RMS3JC080_SSDID
:
3268 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3269 MPT3SAS_INTEL_RMS3JC080_BRANDING
);
3272 case MPT3SAS_INTEL_RS3GC008_SSDID
:
3273 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3274 MPT3SAS_INTEL_RS3GC008_BRANDING
);
3276 case MPT3SAS_INTEL_RS3FC044_SSDID
:
3277 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3278 MPT3SAS_INTEL_RS3FC044_BRANDING
);
3280 case MPT3SAS_INTEL_RS3UC080_SSDID
:
3281 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3282 MPT3SAS_INTEL_RS3UC080_BRANDING
);
3286 "Intel(R) Controller: Subsystem ID: 0x%X\n",
3287 ioc
->name
, ioc
->pdev
->subsystem_device
);
3293 "Intel(R) Controller: Subsystem ID: 0x%X\n",
3294 ioc
->name
, ioc
->pdev
->subsystem_device
);
3298 case PCI_VENDOR_ID_DELL
:
3299 switch (ioc
->pdev
->device
) {
3300 case MPI2_MFGPAGE_DEVID_SAS2008
:
3301 switch (ioc
->pdev
->subsystem_device
) {
3302 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID
:
3303 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3304 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING
);
3306 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID
:
3307 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3308 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING
);
3310 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID
:
3311 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3312 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING
);
3314 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID
:
3315 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3316 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING
);
3318 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID
:
3319 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3320 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING
);
3322 case MPT2SAS_DELL_PERC_H200_SSDID
:
3323 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3324 MPT2SAS_DELL_PERC_H200_BRANDING
);
3326 case MPT2SAS_DELL_6GBPS_SAS_SSDID
:
3327 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3328 MPT2SAS_DELL_6GBPS_SAS_BRANDING
);
3332 "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
3333 ioc
->name
, ioc
->pdev
->subsystem_device
);
3337 case MPI25_MFGPAGE_DEVID_SAS3008
:
3338 switch (ioc
->pdev
->subsystem_device
) {
3339 case MPT3SAS_DELL_12G_HBA_SSDID
:
3340 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3341 MPT3SAS_DELL_12G_HBA_BRANDING
);
3345 "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
3346 ioc
->name
, ioc
->pdev
->subsystem_device
);
3352 "Dell HBA: Subsystem ID: 0x%X\n", ioc
->name
,
3353 ioc
->pdev
->subsystem_device
);
3357 case PCI_VENDOR_ID_CISCO
:
3358 switch (ioc
->pdev
->device
) {
3359 case MPI25_MFGPAGE_DEVID_SAS3008
:
3360 switch (ioc
->pdev
->subsystem_device
) {
3361 case MPT3SAS_CISCO_12G_8E_HBA_SSDID
:
3362 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3363 MPT3SAS_CISCO_12G_8E_HBA_BRANDING
);
3365 case MPT3SAS_CISCO_12G_8I_HBA_SSDID
:
3366 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3367 MPT3SAS_CISCO_12G_8I_HBA_BRANDING
);
3369 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID
:
3370 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3371 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING
);
3375 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
3376 ioc
->name
, ioc
->pdev
->subsystem_device
);
3380 case MPI25_MFGPAGE_DEVID_SAS3108_1
:
3381 switch (ioc
->pdev
->subsystem_device
) {
3382 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID
:
3383 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3384 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING
);
3386 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID
:
3387 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3388 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING
3393 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
3394 ioc
->name
, ioc
->pdev
->subsystem_device
);
3400 "Cisco SAS HBA: Subsystem ID: 0x%X\n",
3401 ioc
->name
, ioc
->pdev
->subsystem_device
);
3405 case MPT2SAS_HP_3PAR_SSVID
:
3406 switch (ioc
->pdev
->device
) {
3407 case MPI2_MFGPAGE_DEVID_SAS2004
:
3408 switch (ioc
->pdev
->subsystem_device
) {
3409 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID
:
3410 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3411 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING
);
3415 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
3416 ioc
->name
, ioc
->pdev
->subsystem_device
);
3419 case MPI2_MFGPAGE_DEVID_SAS2308_2
:
3420 switch (ioc
->pdev
->subsystem_device
) {
3421 case MPT2SAS_HP_2_4_INTERNAL_SSDID
:
3422 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3423 MPT2SAS_HP_2_4_INTERNAL_BRANDING
);
3425 case MPT2SAS_HP_2_4_EXTERNAL_SSDID
:
3426 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3427 MPT2SAS_HP_2_4_EXTERNAL_BRANDING
);
3429 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID
:
3430 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3431 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING
);
3433 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID
:
3434 pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3435 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING
);
3439 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
3440 ioc
->name
, ioc
->pdev
->subsystem_device
);
3445 "HP SAS HBA: Subsystem ID: 0x%X\n",
3446 ioc
->name
, ioc
->pdev
->subsystem_device
);
3455 * _base_display_ioc_capabilities - Disply IOC's capabilities.
3456 * @ioc: per adapter object
3461 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER
*ioc
)
3465 u32 iounit_pg1_flags
;
3468 bios_version
= le32_to_cpu(ioc
->bios_pg3
.BiosVersion
);
3469 strncpy(desc
, ioc
->manu_pg0
.ChipName
, 16);
3470 pr_info(MPT3SAS_FMT
"%s: FWVersion(%02d.%02d.%02d.%02d), "\
3471 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
3473 (ioc
->facts
.FWVersion
.Word
& 0xFF000000) >> 24,
3474 (ioc
->facts
.FWVersion
.Word
& 0x00FF0000) >> 16,
3475 (ioc
->facts
.FWVersion
.Word
& 0x0000FF00) >> 8,
3476 ioc
->facts
.FWVersion
.Word
& 0x000000FF,
3477 ioc
->pdev
->revision
,
3478 (bios_version
& 0xFF000000) >> 24,
3479 (bios_version
& 0x00FF0000) >> 16,
3480 (bios_version
& 0x0000FF00) >> 8,
3481 bios_version
& 0x000000FF);
3483 _base_display_OEMs_branding(ioc
);
3485 if (ioc
->facts
.ProtocolFlags
& MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES
) {
3486 pr_info("%sNVMe", i
? "," : "");
3490 pr_info(MPT3SAS_FMT
"Protocol=(", ioc
->name
);
3492 if (ioc
->facts
.ProtocolFlags
& MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR
) {
3493 pr_info("Initiator");
3497 if (ioc
->facts
.ProtocolFlags
& MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET
) {
3498 pr_info("%sTarget", i
? "," : "");
3504 pr_info("Capabilities=(");
3506 if (!ioc
->hide_ir_msg
) {
3507 if (ioc
->facts
.IOCCapabilities
&
3508 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID
) {
3514 if (ioc
->facts
.IOCCapabilities
& MPI2_IOCFACTS_CAPABILITY_TLR
) {
3515 pr_info("%sTLR", i
? "," : "");
3519 if (ioc
->facts
.IOCCapabilities
& MPI2_IOCFACTS_CAPABILITY_MULTICAST
) {
3520 pr_info("%sMulticast", i
? "," : "");
3524 if (ioc
->facts
.IOCCapabilities
&
3525 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET
) {
3526 pr_info("%sBIDI Target", i
? "," : "");
3530 if (ioc
->facts
.IOCCapabilities
& MPI2_IOCFACTS_CAPABILITY_EEDP
) {
3531 pr_info("%sEEDP", i
? "," : "");
3535 if (ioc
->facts
.IOCCapabilities
&
3536 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER
) {
3537 pr_info("%sSnapshot Buffer", i
? "," : "");
3541 if (ioc
->facts
.IOCCapabilities
&
3542 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER
) {
3543 pr_info("%sDiag Trace Buffer", i
? "," : "");
3547 if (ioc
->facts
.IOCCapabilities
&
3548 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER
) {
3549 pr_info("%sDiag Extended Buffer", i
? "," : "");
3553 if (ioc
->facts
.IOCCapabilities
&
3554 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING
) {
3555 pr_info("%sTask Set Full", i
? "," : "");
3559 iounit_pg1_flags
= le32_to_cpu(ioc
->iounit_pg1
.Flags
);
3560 if (!(iounit_pg1_flags
& MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE
)) {
3561 pr_info("%sNCQ", i
? "," : "");
3569 * mpt3sas_base_update_missing_delay - change the missing delay timers
3570 * @ioc: per adapter object
3571 * @device_missing_delay: amount of time till device is reported missing
3572 * @io_missing_delay: interval IO is returned when there is a missing device
3576 * Passed on the command line, this function will modify the device missing
3577 * delay, as well as the io missing delay. This should be called at driver
3581 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER
*ioc
,
3582 u16 device_missing_delay
, u8 io_missing_delay
)
3584 u16 dmd
, dmd_new
, dmd_orignal
;
3585 u8 io_missing_delay_original
;
3587 Mpi2SasIOUnitPage1_t
*sas_iounit_pg1
= NULL
;
3588 Mpi2ConfigReply_t mpi_reply
;
3592 mpt3sas_config_get_number_hba_phys(ioc
, &num_phys
);
3596 sz
= offsetof(Mpi2SasIOUnitPage1_t
, PhyData
) + (num_phys
*
3597 sizeof(Mpi2SasIOUnit1PhyData_t
));
3598 sas_iounit_pg1
= kzalloc(sz
, GFP_KERNEL
);
3599 if (!sas_iounit_pg1
) {
3600 pr_err(MPT3SAS_FMT
"failure at %s:%d/%s()!\n",
3601 ioc
->name
, __FILE__
, __LINE__
, __func__
);
3604 if ((mpt3sas_config_get_sas_iounit_pg1(ioc
, &mpi_reply
,
3605 sas_iounit_pg1
, sz
))) {
3606 pr_err(MPT3SAS_FMT
"failure at %s:%d/%s()!\n",
3607 ioc
->name
, __FILE__
, __LINE__
, __func__
);
3610 ioc_status
= le16_to_cpu(mpi_reply
.IOCStatus
) &
3611 MPI2_IOCSTATUS_MASK
;
3612 if (ioc_status
!= MPI2_IOCSTATUS_SUCCESS
) {
3613 pr_err(MPT3SAS_FMT
"failure at %s:%d/%s()!\n",
3614 ioc
->name
, __FILE__
, __LINE__
, __func__
);
3618 /* device missing delay */
3619 dmd
= sas_iounit_pg1
->ReportDeviceMissingDelay
;
3620 if (dmd
& MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16
)
3621 dmd
= (dmd
& MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK
) * 16;
3623 dmd
= dmd
& MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK
;
3625 if (device_missing_delay
> 0x7F) {
3626 dmd
= (device_missing_delay
> 0x7F0) ? 0x7F0 :
3627 device_missing_delay
;
3629 dmd
|= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16
;
3631 dmd
= device_missing_delay
;
3632 sas_iounit_pg1
->ReportDeviceMissingDelay
= dmd
;
3634 /* io missing delay */
3635 io_missing_delay_original
= sas_iounit_pg1
->IODeviceMissingDelay
;
3636 sas_iounit_pg1
->IODeviceMissingDelay
= io_missing_delay
;
3638 if (!mpt3sas_config_set_sas_iounit_pg1(ioc
, &mpi_reply
, sas_iounit_pg1
,
3640 if (dmd
& MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16
)
3642 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK
) * 16;
3645 dmd
& MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK
;
3646 pr_info(MPT3SAS_FMT
"device_missing_delay: old(%d), new(%d)\n",
3647 ioc
->name
, dmd_orignal
, dmd_new
);
3648 pr_info(MPT3SAS_FMT
"ioc_missing_delay: old(%d), new(%d)\n",
3649 ioc
->name
, io_missing_delay_original
,
3651 ioc
->device_missing_delay
= dmd_new
;
3652 ioc
->io_missing_delay
= io_missing_delay
;
3656 kfree(sas_iounit_pg1
);
3659 * _base_static_config_pages - static start of day config pages
3660 * @ioc: per adapter object
3665 _base_static_config_pages(struct MPT3SAS_ADAPTER
*ioc
)
3667 Mpi2ConfigReply_t mpi_reply
;
3668 u32 iounit_pg1_flags
;
3670 mpt3sas_config_get_manufacturing_pg0(ioc
, &mpi_reply
, &ioc
->manu_pg0
);
3671 if (ioc
->ir_firmware
)
3672 mpt3sas_config_get_manufacturing_pg10(ioc
, &mpi_reply
,
3676 * Ensure correct T10 PI operation if vendor left EEDPTagMode
3677 * flag unset in NVDATA.
3679 mpt3sas_config_get_manufacturing_pg11(ioc
, &mpi_reply
, &ioc
->manu_pg11
);
3680 if (ioc
->manu_pg11
.EEDPTagMode
== 0) {
3681 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
3683 ioc
->manu_pg11
.EEDPTagMode
&= ~0x3;
3684 ioc
->manu_pg11
.EEDPTagMode
|= 0x1;
3685 mpt3sas_config_set_manufacturing_pg11(ioc
, &mpi_reply
,
3689 mpt3sas_config_get_bios_pg2(ioc
, &mpi_reply
, &ioc
->bios_pg2
);
3690 mpt3sas_config_get_bios_pg3(ioc
, &mpi_reply
, &ioc
->bios_pg3
);
3691 mpt3sas_config_get_ioc_pg8(ioc
, &mpi_reply
, &ioc
->ioc_pg8
);
3692 mpt3sas_config_get_iounit_pg0(ioc
, &mpi_reply
, &ioc
->iounit_pg0
);
3693 mpt3sas_config_get_iounit_pg1(ioc
, &mpi_reply
, &ioc
->iounit_pg1
);
3694 mpt3sas_config_get_iounit_pg8(ioc
, &mpi_reply
, &ioc
->iounit_pg8
);
3695 _base_display_ioc_capabilities(ioc
);
3698 * Enable task_set_full handling in iounit_pg1 when the
3699 * facts capabilities indicate that its supported.
3701 iounit_pg1_flags
= le32_to_cpu(ioc
->iounit_pg1
.Flags
);
3702 if ((ioc
->facts
.IOCCapabilities
&
3703 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING
))
3705 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING
;
3708 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING
;
3709 ioc
->iounit_pg1
.Flags
= cpu_to_le32(iounit_pg1_flags
);
3710 mpt3sas_config_set_iounit_pg1(ioc
, &mpi_reply
, &ioc
->iounit_pg1
);
3712 if (ioc
->iounit_pg8
.NumSensors
)
3713 ioc
->temp_sensors_count
= ioc
->iounit_pg8
.NumSensors
;
3717 * _base_release_memory_pools - release memory
3718 * @ioc: per adapter object
3720 * Free memory allocated from _base_allocate_memory_pools.
3725 _base_release_memory_pools(struct MPT3SAS_ADAPTER
*ioc
)
3728 struct reply_post_struct
*rps
;
3730 dexitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3734 pci_free_consistent(ioc
->pdev
, ioc
->request_dma_sz
,
3735 ioc
->request
, ioc
->request_dma
);
3736 dexitprintk(ioc
, pr_info(MPT3SAS_FMT
3737 "request_pool(0x%p): free\n",
3738 ioc
->name
, ioc
->request
));
3739 ioc
->request
= NULL
;
3743 dma_pool_free(ioc
->sense_dma_pool
, ioc
->sense
, ioc
->sense_dma
);
3744 dma_pool_destroy(ioc
->sense_dma_pool
);
3745 dexitprintk(ioc
, pr_info(MPT3SAS_FMT
3746 "sense_pool(0x%p): free\n",
3747 ioc
->name
, ioc
->sense
));
3752 dma_pool_free(ioc
->reply_dma_pool
, ioc
->reply
, ioc
->reply_dma
);
3753 dma_pool_destroy(ioc
->reply_dma_pool
);
3754 dexitprintk(ioc
, pr_info(MPT3SAS_FMT
3755 "reply_pool(0x%p): free\n",
3756 ioc
->name
, ioc
->reply
));
3760 if (ioc
->reply_free
) {
3761 dma_pool_free(ioc
->reply_free_dma_pool
, ioc
->reply_free
,
3762 ioc
->reply_free_dma
);
3763 dma_pool_destroy(ioc
->reply_free_dma_pool
);
3764 dexitprintk(ioc
, pr_info(MPT3SAS_FMT
3765 "reply_free_pool(0x%p): free\n",
3766 ioc
->name
, ioc
->reply_free
));
3767 ioc
->reply_free
= NULL
;
3770 if (ioc
->reply_post
) {
3772 rps
= &ioc
->reply_post
[i
];
3773 if (rps
->reply_post_free
) {
3775 ioc
->reply_post_free_dma_pool
,
3776 rps
->reply_post_free
,
3777 rps
->reply_post_free_dma
);
3778 dexitprintk(ioc
, pr_info(MPT3SAS_FMT
3779 "reply_post_free_pool(0x%p): free\n",
3780 ioc
->name
, rps
->reply_post_free
));
3781 rps
->reply_post_free
= NULL
;
3783 } while (ioc
->rdpq_array_enable
&&
3784 (++i
< ioc
->reply_queue_count
));
3786 dma_pool_destroy(ioc
->reply_post_free_dma_pool
);
3787 kfree(ioc
->reply_post
);
3790 if (ioc
->pcie_sgl_dma_pool
) {
3791 for (i
= 0; i
< ioc
->scsiio_depth
; i
++) {
3792 if (ioc
->scsi_lookup
[i
].pcie_sg_list
.pcie_sgl
)
3793 pci_pool_free(ioc
->pcie_sgl_dma_pool
,
3794 ioc
->scsi_lookup
[i
].pcie_sg_list
.pcie_sgl
,
3795 ioc
->scsi_lookup
[i
].pcie_sg_list
.pcie_sgl_dma
);
3797 if (ioc
->pcie_sgl_dma_pool
)
3798 pci_pool_destroy(ioc
->pcie_sgl_dma_pool
);
3801 if (ioc
->config_page
) {
3802 dexitprintk(ioc
, pr_info(MPT3SAS_FMT
3803 "config_page(0x%p): free\n", ioc
->name
,
3805 pci_free_consistent(ioc
->pdev
, ioc
->config_page_sz
,
3806 ioc
->config_page
, ioc
->config_page_dma
);
3809 if (ioc
->scsi_lookup
) {
3810 free_pages((ulong
)ioc
->scsi_lookup
, ioc
->scsi_lookup_pages
);
3811 ioc
->scsi_lookup
= NULL
;
3813 kfree(ioc
->hpr_lookup
);
3814 kfree(ioc
->internal_lookup
);
3815 if (ioc
->chain_lookup
) {
3816 for (i
= 0; i
< ioc
->chain_depth
; i
++) {
3817 if (ioc
->chain_lookup
[i
].chain_buffer
)
3818 dma_pool_free(ioc
->chain_dma_pool
,
3819 ioc
->chain_lookup
[i
].chain_buffer
,
3820 ioc
->chain_lookup
[i
].chain_buffer_dma
);
3822 dma_pool_destroy(ioc
->chain_dma_pool
);
3823 free_pages((ulong
)ioc
->chain_lookup
, ioc
->chain_pages
);
3824 ioc
->chain_lookup
= NULL
;
3829 * _base_allocate_memory_pools - allocate start of day memory pools
3830 * @ioc: per adapter object
3832 * Returns 0 success, anything else error
3835 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER
*ioc
)
3837 struct mpt3sas_facts
*facts
;
3838 u16 max_sge_elements
;
3839 u16 chains_needed_per_io
;
3840 u32 sz
, total_sz
, reply_post_free_sz
;
3842 u16 max_request_credit
, nvme_blocks_needed
;
3843 unsigned short sg_tablesize
;
3847 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
3852 facts
= &ioc
->facts
;
3854 /* command line tunables for max sgl entries */
3855 if (max_sgl_entries
!= -1)
3856 sg_tablesize
= max_sgl_entries
;
3858 if (ioc
->hba_mpi_version_belonged
== MPI2_VERSION
)
3859 sg_tablesize
= MPT2SAS_SG_DEPTH
;
3861 sg_tablesize
= MPT3SAS_SG_DEPTH
;
3864 /* max sgl entries <= MPT_KDUMP_MIN_PHYS_SEGMENTS in KDUMP mode */
3866 sg_tablesize
= min_t(unsigned short, sg_tablesize
,
3867 MPT_KDUMP_MIN_PHYS_SEGMENTS
);
3869 if (sg_tablesize
< MPT_MIN_PHYS_SEGMENTS
)
3870 sg_tablesize
= MPT_MIN_PHYS_SEGMENTS
;
3871 else if (sg_tablesize
> MPT_MAX_PHYS_SEGMENTS
) {
3872 sg_tablesize
= min_t(unsigned short, sg_tablesize
,
3875 "sg_tablesize(%u) is bigger than kernel"
3876 " defined SG_CHUNK_SIZE(%u)\n", ioc
->name
,
3877 sg_tablesize
, MPT_MAX_PHYS_SEGMENTS
);
3879 ioc
->shost
->sg_tablesize
= sg_tablesize
;
3881 ioc
->internal_depth
= min_t(int, (facts
->HighPriorityCredit
+ (5)),
3882 (facts
->RequestCredit
/ 4));
3883 if (ioc
->internal_depth
< INTERNAL_CMDS_COUNT
) {
3884 if (facts
->RequestCredit
<= (INTERNAL_CMDS_COUNT
+
3885 INTERNAL_SCSIIO_CMDS_COUNT
)) {
3886 pr_err(MPT3SAS_FMT
"IOC doesn't have enough Request \
3887 Credits, it has just %d number of credits\n",
3888 ioc
->name
, facts
->RequestCredit
);
3891 ioc
->internal_depth
= 10;
3894 ioc
->hi_priority_depth
= ioc
->internal_depth
- (5);
3895 /* command line tunables for max controller queue depth */
3896 if (max_queue_depth
!= -1 && max_queue_depth
!= 0) {
3897 max_request_credit
= min_t(u16
, max_queue_depth
+
3898 ioc
->internal_depth
, facts
->RequestCredit
);
3899 if (max_request_credit
> MAX_HBA_QUEUE_DEPTH
)
3900 max_request_credit
= MAX_HBA_QUEUE_DEPTH
;
3901 } else if (reset_devices
)
3902 max_request_credit
= min_t(u16
, facts
->RequestCredit
,
3903 (MPT3SAS_KDUMP_SCSI_IO_DEPTH
+ ioc
->internal_depth
));
3905 max_request_credit
= min_t(u16
, facts
->RequestCredit
,
3906 MAX_HBA_QUEUE_DEPTH
);
3908 /* Firmware maintains additional facts->HighPriorityCredit number of
3909 * credits for HiPriprity Request messages, so hba queue depth will be
3910 * sum of max_request_credit and high priority queue depth.
3912 ioc
->hba_queue_depth
= max_request_credit
+ ioc
->hi_priority_depth
;
3914 /* request frame size */
3915 ioc
->request_sz
= facts
->IOCRequestFrameSize
* 4;
3917 /* reply frame size */
3918 ioc
->reply_sz
= facts
->ReplyFrameSize
* 4;
3920 /* chain segment size */
3921 if (ioc
->hba_mpi_version_belonged
!= MPI2_VERSION
) {
3922 if (facts
->IOCMaxChainSegmentSize
)
3923 ioc
->chain_segment_sz
=
3924 facts
->IOCMaxChainSegmentSize
*
3927 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
3928 ioc
->chain_segment_sz
= DEFAULT_NUM_FWCHAIN_ELEMTS
*
3931 ioc
->chain_segment_sz
= ioc
->request_sz
;
3933 /* calculate the max scatter element size */
3934 sge_size
= max_t(u16
, ioc
->sge_size
, ioc
->sge_size_ieee
);
3938 /* calculate number of sg elements left over in the 1st frame */
3939 max_sge_elements
= ioc
->request_sz
- ((sizeof(Mpi2SCSIIORequest_t
) -
3940 sizeof(Mpi2SGEIOUnion_t
)) + sge_size
);
3941 ioc
->max_sges_in_main_message
= max_sge_elements
/sge_size
;
3943 /* now do the same for a chain buffer */
3944 max_sge_elements
= ioc
->chain_segment_sz
- sge_size
;
3945 ioc
->max_sges_in_chain_message
= max_sge_elements
/sge_size
;
3948 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
3950 chains_needed_per_io
= ((ioc
->shost
->sg_tablesize
-
3951 ioc
->max_sges_in_main_message
)/ioc
->max_sges_in_chain_message
)
3953 if (chains_needed_per_io
> facts
->MaxChainDepth
) {
3954 chains_needed_per_io
= facts
->MaxChainDepth
;
3955 ioc
->shost
->sg_tablesize
= min_t(u16
,
3956 ioc
->max_sges_in_main_message
+ (ioc
->max_sges_in_chain_message
3957 * chains_needed_per_io
), ioc
->shost
->sg_tablesize
);
3959 ioc
->chains_needed_per_io
= chains_needed_per_io
;
3961 /* reply free queue sizing - taking into account for 64 FW events */
3962 ioc
->reply_free_queue_depth
= ioc
->hba_queue_depth
+ 64;
3964 /* calculate reply descriptor post queue depth */
3965 ioc
->reply_post_queue_depth
= ioc
->hba_queue_depth
+
3966 ioc
->reply_free_queue_depth
+ 1 ;
3967 /* align the reply post queue on the next 16 count boundary */
3968 if (ioc
->reply_post_queue_depth
% 16)
3969 ioc
->reply_post_queue_depth
+= 16 -
3970 (ioc
->reply_post_queue_depth
% 16);
3972 if (ioc
->reply_post_queue_depth
>
3973 facts
->MaxReplyDescriptorPostQueueDepth
) {
3974 ioc
->reply_post_queue_depth
=
3975 facts
->MaxReplyDescriptorPostQueueDepth
-
3976 (facts
->MaxReplyDescriptorPostQueueDepth
% 16);
3977 ioc
->hba_queue_depth
=
3978 ((ioc
->reply_post_queue_depth
- 64) / 2) - 1;
3979 ioc
->reply_free_queue_depth
= ioc
->hba_queue_depth
+ 64;
3982 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"scatter gather: " \
3983 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
3984 "chains_per_io(%d)\n", ioc
->name
, ioc
->max_sges_in_main_message
,
3985 ioc
->max_sges_in_chain_message
, ioc
->shost
->sg_tablesize
,
3986 ioc
->chains_needed_per_io
));
3988 /* reply post queue, 16 byte align */
3989 reply_post_free_sz
= ioc
->reply_post_queue_depth
*
3990 sizeof(Mpi2DefaultReplyDescriptor_t
);
3992 sz
= reply_post_free_sz
;
3993 if (_base_is_controller_msix_enabled(ioc
) && !ioc
->rdpq_array_enable
)
3994 sz
*= ioc
->reply_queue_count
;
3996 ioc
->reply_post
= kcalloc((ioc
->rdpq_array_enable
) ?
3997 (ioc
->reply_queue_count
):1,
3998 sizeof(struct reply_post_struct
), GFP_KERNEL
);
4000 if (!ioc
->reply_post
) {
4001 pr_err(MPT3SAS_FMT
"reply_post_free pool: kcalloc failed\n",
4005 ioc
->reply_post_free_dma_pool
= dma_pool_create("reply_post_free pool",
4006 &ioc
->pdev
->dev
, sz
, 16, 0);
4007 if (!ioc
->reply_post_free_dma_pool
) {
4009 "reply_post_free pool: dma_pool_create failed\n",
4015 ioc
->reply_post
[i
].reply_post_free
=
4016 dma_pool_alloc(ioc
->reply_post_free_dma_pool
,
4018 &ioc
->reply_post
[i
].reply_post_free_dma
);
4019 if (!ioc
->reply_post
[i
].reply_post_free
) {
4021 "reply_post_free pool: dma_pool_alloc failed\n",
4025 memset(ioc
->reply_post
[i
].reply_post_free
, 0, sz
);
4026 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
4027 "reply post free pool (0x%p): depth(%d),"
4028 "element_size(%d), pool_size(%d kB)\n", ioc
->name
,
4029 ioc
->reply_post
[i
].reply_post_free
,
4030 ioc
->reply_post_queue_depth
, 8, sz
/1024));
4031 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
4032 "reply_post_free_dma = (0x%llx)\n", ioc
->name
,
4033 (unsigned long long)
4034 ioc
->reply_post
[i
].reply_post_free_dma
));
4036 } while (ioc
->rdpq_array_enable
&& (++i
< ioc
->reply_queue_count
));
4038 if (ioc
->dma_mask
== 64) {
4039 if (_base_change_consistent_dma_mask(ioc
, ioc
->pdev
) != 0) {
4041 "no suitable consistent DMA mask for %s\n",
4042 ioc
->name
, pci_name(ioc
->pdev
));
4047 ioc
->scsiio_depth
= ioc
->hba_queue_depth
-
4048 ioc
->hi_priority_depth
- ioc
->internal_depth
;
4050 /* set the scsi host can_queue depth
4051 * with some internal commands that could be outstanding
4053 ioc
->shost
->can_queue
= ioc
->scsiio_depth
- INTERNAL_SCSIIO_CMDS_COUNT
;
4054 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
4055 "scsi host: can_queue depth (%d)\n",
4056 ioc
->name
, ioc
->shost
->can_queue
));
4059 /* contiguous pool for request and chains, 16 byte align, one extra "
4062 ioc
->chain_depth
= ioc
->chains_needed_per_io
* ioc
->scsiio_depth
;
4063 sz
= ((ioc
->scsiio_depth
+ 1) * ioc
->request_sz
);
4065 /* hi-priority queue */
4066 sz
+= (ioc
->hi_priority_depth
* ioc
->request_sz
);
4068 /* internal queue */
4069 sz
+= (ioc
->internal_depth
* ioc
->request_sz
);
4071 ioc
->request_dma_sz
= sz
;
4072 ioc
->request
= pci_alloc_consistent(ioc
->pdev
, sz
, &ioc
->request_dma
);
4073 if (!ioc
->request
) {
4074 pr_err(MPT3SAS_FMT
"request pool: pci_alloc_consistent " \
4075 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
4076 "total(%d kB)\n", ioc
->name
, ioc
->hba_queue_depth
,
4077 ioc
->chains_needed_per_io
, ioc
->request_sz
, sz
/1024);
4078 if (ioc
->scsiio_depth
< MPT3SAS_SAS_QUEUE_DEPTH
)
4081 ioc
->hba_queue_depth
-= retry_sz
;
4082 _base_release_memory_pools(ioc
);
4083 goto retry_allocation
;
4087 pr_err(MPT3SAS_FMT
"request pool: pci_alloc_consistent " \
4088 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
4089 "total(%d kb)\n", ioc
->name
, ioc
->hba_queue_depth
,
4090 ioc
->chains_needed_per_io
, ioc
->request_sz
, sz
/1024);
4092 /* hi-priority queue */
4093 ioc
->hi_priority
= ioc
->request
+ ((ioc
->scsiio_depth
+ 1) *
4095 ioc
->hi_priority_dma
= ioc
->request_dma
+ ((ioc
->scsiio_depth
+ 1) *
4098 /* internal queue */
4099 ioc
->internal
= ioc
->hi_priority
+ (ioc
->hi_priority_depth
*
4101 ioc
->internal_dma
= ioc
->hi_priority_dma
+ (ioc
->hi_priority_depth
*
4104 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
4105 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
4106 ioc
->name
, ioc
->request
, ioc
->hba_queue_depth
, ioc
->request_sz
,
4107 (ioc
->hba_queue_depth
* ioc
->request_sz
)/1024));
4109 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"request pool: dma(0x%llx)\n",
4110 ioc
->name
, (unsigned long long) ioc
->request_dma
));
4113 sz
= ioc
->scsiio_depth
* sizeof(struct scsiio_tracker
);
4114 ioc
->scsi_lookup_pages
= get_order(sz
);
4115 ioc
->scsi_lookup
= (struct scsiio_tracker
*)__get_free_pages(
4116 GFP_KERNEL
, ioc
->scsi_lookup_pages
);
4117 if (!ioc
->scsi_lookup
) {
4118 pr_err(MPT3SAS_FMT
"scsi_lookup: get_free_pages failed, sz(%d)\n",
4119 ioc
->name
, (int)sz
);
4123 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"scsiio(0x%p): depth(%d)\n",
4124 ioc
->name
, ioc
->request
, ioc
->scsiio_depth
));
4126 ioc
->chain_depth
= min_t(u32
, ioc
->chain_depth
, MAX_CHAIN_DEPTH
);
4127 sz
= ioc
->chain_depth
* sizeof(struct chain_tracker
);
4128 ioc
->chain_pages
= get_order(sz
);
4129 ioc
->chain_lookup
= (struct chain_tracker
*)__get_free_pages(
4130 GFP_KERNEL
, ioc
->chain_pages
);
4131 if (!ioc
->chain_lookup
) {
4132 pr_err(MPT3SAS_FMT
"chain_lookup: __get_free_pages failed\n",
4136 ioc
->chain_dma_pool
= dma_pool_create("chain pool", &ioc
->pdev
->dev
,
4137 ioc
->chain_segment_sz
, 16, 0);
4138 if (!ioc
->chain_dma_pool
) {
4139 pr_err(MPT3SAS_FMT
"chain_dma_pool: dma_pool_create failed\n",
4143 for (i
= 0; i
< ioc
->chain_depth
; i
++) {
4144 ioc
->chain_lookup
[i
].chain_buffer
= dma_pool_alloc(
4145 ioc
->chain_dma_pool
, GFP_KERNEL
,
4146 &ioc
->chain_lookup
[i
].chain_buffer_dma
);
4147 if (!ioc
->chain_lookup
[i
].chain_buffer
) {
4148 ioc
->chain_depth
= i
;
4151 total_sz
+= ioc
->chain_segment_sz
;
4154 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
4155 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
4156 ioc
->name
, ioc
->chain_depth
, ioc
->chain_segment_sz
,
4157 ((ioc
->chain_depth
* ioc
->chain_segment_sz
))/1024));
4159 /* initialize hi-priority queue smid's */
4160 ioc
->hpr_lookup
= kcalloc(ioc
->hi_priority_depth
,
4161 sizeof(struct request_tracker
), GFP_KERNEL
);
4162 if (!ioc
->hpr_lookup
) {
4163 pr_err(MPT3SAS_FMT
"hpr_lookup: kcalloc failed\n",
4167 ioc
->hi_priority_smid
= ioc
->scsiio_depth
+ 1;
4168 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
4169 "hi_priority(0x%p): depth(%d), start smid(%d)\n",
4170 ioc
->name
, ioc
->hi_priority
,
4171 ioc
->hi_priority_depth
, ioc
->hi_priority_smid
));
4173 /* initialize internal queue smid's */
4174 ioc
->internal_lookup
= kcalloc(ioc
->internal_depth
,
4175 sizeof(struct request_tracker
), GFP_KERNEL
);
4176 if (!ioc
->internal_lookup
) {
4177 pr_err(MPT3SAS_FMT
"internal_lookup: kcalloc failed\n",
4181 ioc
->internal_smid
= ioc
->hi_priority_smid
+ ioc
->hi_priority_depth
;
4182 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
4183 "internal(0x%p): depth(%d), start smid(%d)\n",
4184 ioc
->name
, ioc
->internal
,
4185 ioc
->internal_depth
, ioc
->internal_smid
));
4187 * The number of NVMe page sized blocks needed is:
4188 * (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1
4189 * ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry
4190 * that is placed in the main message frame. 8 is the size of each PRP
4191 * entry or PRP list pointer entry. 8 is subtracted from page_size
4192 * because of the PRP list pointer entry at the end of a page, so this
4193 * is not counted as a PRP entry. The 1 added page is a round up.
4195 * To avoid allocation failures due to the amount of memory that could
4196 * be required for NVMe PRP's, only each set of NVMe blocks will be
4197 * contiguous, so a new set is allocated for each possible I/O.
4199 if (ioc
->facts
.ProtocolFlags
& MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES
) {
4200 nvme_blocks_needed
=
4201 (ioc
->shost
->sg_tablesize
* NVME_PRP_SIZE
) - 1;
4202 nvme_blocks_needed
/= (ioc
->page_size
- NVME_PRP_SIZE
);
4203 nvme_blocks_needed
++;
4205 sz
= nvme_blocks_needed
* ioc
->page_size
;
4206 ioc
->pcie_sgl_dma_pool
=
4207 pci_pool_create("PCIe SGL pool", ioc
->pdev
, sz
, 16, 0);
4208 if (!ioc
->pcie_sgl_dma_pool
) {
4210 "PCIe SGL pool: pci_pool_create failed\n",
4214 for (i
= 0; i
< ioc
->scsiio_depth
; i
++) {
4215 ioc
->scsi_lookup
[i
].pcie_sg_list
.pcie_sgl
=
4216 pci_pool_alloc(ioc
->pcie_sgl_dma_pool
,
4218 &ioc
->scsi_lookup
[i
].pcie_sg_list
.pcie_sgl_dma
);
4219 if (!ioc
->scsi_lookup
[i
].pcie_sg_list
.pcie_sgl
) {
4221 "PCIe SGL pool: pci_pool_alloc failed\n",
4227 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"PCIe sgl pool depth(%d), "
4228 "element_size(%d), pool_size(%d kB)\n", ioc
->name
,
4229 ioc
->scsiio_depth
, sz
, (sz
* ioc
->scsiio_depth
)/1024));
4230 total_sz
+= sz
* ioc
->scsiio_depth
;
4232 /* sense buffers, 4 byte align */
4233 sz
= ioc
->scsiio_depth
* SCSI_SENSE_BUFFERSIZE
;
4234 ioc
->sense_dma_pool
= dma_pool_create("sense pool", &ioc
->pdev
->dev
, sz
,
4236 if (!ioc
->sense_dma_pool
) {
4237 pr_err(MPT3SAS_FMT
"sense pool: dma_pool_create failed\n",
4241 ioc
->sense
= dma_pool_alloc(ioc
->sense_dma_pool
, GFP_KERNEL
,
4244 pr_err(MPT3SAS_FMT
"sense pool: dma_pool_alloc failed\n",
4248 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
4249 "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
4250 "(%d kB)\n", ioc
->name
, ioc
->sense
, ioc
->scsiio_depth
,
4251 SCSI_SENSE_BUFFERSIZE
, sz
/1024));
4252 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"sense_dma(0x%llx)\n",
4253 ioc
->name
, (unsigned long long)ioc
->sense_dma
));
4256 /* reply pool, 4 byte align */
4257 sz
= ioc
->reply_free_queue_depth
* ioc
->reply_sz
;
4258 ioc
->reply_dma_pool
= dma_pool_create("reply pool", &ioc
->pdev
->dev
, sz
,
4260 if (!ioc
->reply_dma_pool
) {
4261 pr_err(MPT3SAS_FMT
"reply pool: dma_pool_create failed\n",
4265 ioc
->reply
= dma_pool_alloc(ioc
->reply_dma_pool
, GFP_KERNEL
,
4268 pr_err(MPT3SAS_FMT
"reply pool: dma_pool_alloc failed\n",
4272 ioc
->reply_dma_min_address
= (u32
)(ioc
->reply_dma
);
4273 ioc
->reply_dma_max_address
= (u32
)(ioc
->reply_dma
) + sz
;
4274 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
4275 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
4276 ioc
->name
, ioc
->reply
,
4277 ioc
->reply_free_queue_depth
, ioc
->reply_sz
, sz
/1024));
4278 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"reply_dma(0x%llx)\n",
4279 ioc
->name
, (unsigned long long)ioc
->reply_dma
));
4282 /* reply free queue, 16 byte align */
4283 sz
= ioc
->reply_free_queue_depth
* 4;
4284 ioc
->reply_free_dma_pool
= dma_pool_create("reply_free pool",
4285 &ioc
->pdev
->dev
, sz
, 16, 0);
4286 if (!ioc
->reply_free_dma_pool
) {
4287 pr_err(MPT3SAS_FMT
"reply_free pool: dma_pool_create failed\n",
4291 ioc
->reply_free
= dma_pool_alloc(ioc
->reply_free_dma_pool
, GFP_KERNEL
,
4292 &ioc
->reply_free_dma
);
4293 if (!ioc
->reply_free
) {
4294 pr_err(MPT3SAS_FMT
"reply_free pool: dma_pool_alloc failed\n",
4298 memset(ioc
->reply_free
, 0, sz
);
4299 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"reply_free pool(0x%p): " \
4300 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc
->name
,
4301 ioc
->reply_free
, ioc
->reply_free_queue_depth
, 4, sz
/1024));
4302 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
4303 "reply_free_dma (0x%llx)\n",
4304 ioc
->name
, (unsigned long long)ioc
->reply_free_dma
));
4307 ioc
->config_page_sz
= 512;
4308 ioc
->config_page
= pci_alloc_consistent(ioc
->pdev
,
4309 ioc
->config_page_sz
, &ioc
->config_page_dma
);
4310 if (!ioc
->config_page
) {
4312 "config page: dma_pool_alloc failed\n",
4316 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
4317 "config page(0x%p): size(%d)\n",
4318 ioc
->name
, ioc
->config_page
, ioc
->config_page_sz
));
4319 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"config_page_dma(0x%llx)\n",
4320 ioc
->name
, (unsigned long long)ioc
->config_page_dma
));
4321 total_sz
+= ioc
->config_page_sz
;
4323 pr_info(MPT3SAS_FMT
"Allocated physical memory: size(%d kB)\n",
4324 ioc
->name
, total_sz
/1024);
4326 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
4327 ioc
->name
, ioc
->shost
->can_queue
, facts
->RequestCredit
);
4328 pr_info(MPT3SAS_FMT
"Scatter Gather Elements per IO(%d)\n",
4329 ioc
->name
, ioc
->shost
->sg_tablesize
);
4337 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
4338 * @ioc: Pointer to MPT_ADAPTER structure
4339 * @cooked: Request raw or cooked IOC state
4341 * Returns all IOC Doorbell register bits if cooked==0, else just the
4342 * Doorbell bits in MPI_IOC_STATE_MASK.
4345 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER
*ioc
, int cooked
)
4349 s
= readl(&ioc
->chip
->Doorbell
);
4350 sc
= s
& MPI2_IOC_STATE_MASK
;
4351 return cooked
? sc
: s
;
4355 * _base_wait_on_iocstate - waiting on a particular ioc state
4356 * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
4357 * @timeout: timeout in second
4359 * Returns 0 for success, non-zero for failure.
4362 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER
*ioc
, u32 ioc_state
, int timeout
)
4368 cntdn
= 1000 * timeout
;
4370 current_state
= mpt3sas_base_get_iocstate(ioc
, 1);
4371 if (current_state
== ioc_state
)
4373 if (count
&& current_state
== MPI2_IOC_STATE_FAULT
)
4376 usleep_range(1000, 1500);
4380 return current_state
;
4384 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
4385 * a write to the doorbell)
4386 * @ioc: per adapter object
4387 * @timeout: timeout in second
4389 * Returns 0 for success, non-zero for failure.
4391 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
4394 _base_diag_reset(struct MPT3SAS_ADAPTER
*ioc
);
4397 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER
*ioc
, int timeout
)
4403 cntdn
= 1000 * timeout
;
4405 int_status
= readl(&ioc
->chip
->HostInterruptStatus
);
4406 if (int_status
& MPI2_HIS_IOC2SYS_DB_STATUS
) {
4407 dhsprintk(ioc
, pr_info(MPT3SAS_FMT
4408 "%s: successful count(%d), timeout(%d)\n",
4409 ioc
->name
, __func__
, count
, timeout
));
4413 usleep_range(1000, 1500);
4418 "%s: failed due to timeout count(%d), int_status(%x)!\n",
4419 ioc
->name
, __func__
, count
, int_status
);
4424 _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER
*ioc
, int timeout
)
4430 cntdn
= 2000 * timeout
;
4432 int_status
= readl(&ioc
->chip
->HostInterruptStatus
);
4433 if (int_status
& MPI2_HIS_IOC2SYS_DB_STATUS
) {
4434 dhsprintk(ioc
, pr_info(MPT3SAS_FMT
4435 "%s: successful count(%d), timeout(%d)\n",
4436 ioc
->name
, __func__
, count
, timeout
));
4445 "%s: failed due to timeout count(%d), int_status(%x)!\n",
4446 ioc
->name
, __func__
, count
, int_status
);
4452 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
4453 * @ioc: per adapter object
4454 * @timeout: timeout in second
4456 * Returns 0 for success, non-zero for failure.
4458 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
4462 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER
*ioc
, int timeout
)
4469 cntdn
= 1000 * timeout
;
4471 int_status
= readl(&ioc
->chip
->HostInterruptStatus
);
4472 if (!(int_status
& MPI2_HIS_SYS2IOC_DB_STATUS
)) {
4473 dhsprintk(ioc
, pr_info(MPT3SAS_FMT
4474 "%s: successful count(%d), timeout(%d)\n",
4475 ioc
->name
, __func__
, count
, timeout
));
4477 } else if (int_status
& MPI2_HIS_IOC2SYS_DB_STATUS
) {
4478 doorbell
= readl(&ioc
->chip
->Doorbell
);
4479 if ((doorbell
& MPI2_IOC_STATE_MASK
) ==
4480 MPI2_IOC_STATE_FAULT
) {
4481 mpt3sas_base_fault_info(ioc
, doorbell
);
4484 } else if (int_status
== 0xFFFFFFFF)
4487 usleep_range(1000, 1500);
4493 "%s: failed due to timeout count(%d), int_status(%x)!\n",
4494 ioc
->name
, __func__
, count
, int_status
);
4499 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
4500 * @ioc: per adapter object
4501 * @timeout: timeout in second
4503 * Returns 0 for success, non-zero for failure.
4507 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER
*ioc
, int timeout
)
4513 cntdn
= 1000 * timeout
;
4515 doorbell_reg
= readl(&ioc
->chip
->Doorbell
);
4516 if (!(doorbell_reg
& MPI2_DOORBELL_USED
)) {
4517 dhsprintk(ioc
, pr_info(MPT3SAS_FMT
4518 "%s: successful count(%d), timeout(%d)\n",
4519 ioc
->name
, __func__
, count
, timeout
));
4523 usleep_range(1000, 1500);
4528 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
4529 ioc
->name
, __func__
, count
, doorbell_reg
);
4534 * _base_send_ioc_reset - send doorbell reset
4535 * @ioc: per adapter object
4536 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
4537 * @timeout: timeout in second
4539 * Returns 0 for success, non-zero for failure.
4542 _base_send_ioc_reset(struct MPT3SAS_ADAPTER
*ioc
, u8 reset_type
, int timeout
)
4547 if (reset_type
!= MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
) {
4548 pr_err(MPT3SAS_FMT
"%s: unknown reset_type\n",
4549 ioc
->name
, __func__
);
4553 if (!(ioc
->facts
.IOCCapabilities
&
4554 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY
))
4557 pr_info(MPT3SAS_FMT
"sending message unit reset !!\n", ioc
->name
);
4559 writel(reset_type
<< MPI2_DOORBELL_FUNCTION_SHIFT
,
4560 &ioc
->chip
->Doorbell
);
4561 if ((_base_wait_for_doorbell_ack(ioc
, 15))) {
4565 ioc_state
= _base_wait_on_iocstate(ioc
, MPI2_IOC_STATE_READY
, timeout
);
4568 "%s: failed going to ready state (ioc_state=0x%x)\n",
4569 ioc
->name
, __func__
, ioc_state
);
4574 pr_info(MPT3SAS_FMT
"message unit reset: %s\n",
4575 ioc
->name
, ((r
== 0) ? "SUCCESS" : "FAILED"));
4580 * _base_handshake_req_reply_wait - send request thru doorbell interface
4581 * @ioc: per adapter object
4582 * @request_bytes: request length
4583 * @request: pointer having request payload
4584 * @reply_bytes: reply length
4585 * @reply: pointer to reply payload
4586 * @timeout: timeout in second
4588 * Returns 0 for success, non-zero for failure.
4591 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER
*ioc
, int request_bytes
,
4592 u32
*request
, int reply_bytes
, u16
*reply
, int timeout
)
4594 MPI2DefaultReply_t
*default_reply
= (MPI2DefaultReply_t
*)reply
;
4599 /* make sure doorbell is not in use */
4600 if ((readl(&ioc
->chip
->Doorbell
) & MPI2_DOORBELL_USED
)) {
4602 "doorbell is in use (line=%d)\n",
4603 ioc
->name
, __LINE__
);
4607 /* clear pending doorbell interrupts from previous state changes */
4608 if (readl(&ioc
->chip
->HostInterruptStatus
) &
4609 MPI2_HIS_IOC2SYS_DB_STATUS
)
4610 writel(0, &ioc
->chip
->HostInterruptStatus
);
4612 /* send message to ioc */
4613 writel(((MPI2_FUNCTION_HANDSHAKE
<<MPI2_DOORBELL_FUNCTION_SHIFT
) |
4614 ((request_bytes
/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT
)),
4615 &ioc
->chip
->Doorbell
);
4617 if ((_base_spin_on_doorbell_int(ioc
, 5))) {
4619 "doorbell handshake int failed (line=%d)\n",
4620 ioc
->name
, __LINE__
);
4623 writel(0, &ioc
->chip
->HostInterruptStatus
);
4625 if ((_base_wait_for_doorbell_ack(ioc
, 5))) {
4627 "doorbell handshake ack failed (line=%d)\n",
4628 ioc
->name
, __LINE__
);
4632 /* send message 32-bits at a time */
4633 for (i
= 0, failed
= 0; i
< request_bytes
/4 && !failed
; i
++) {
4634 writel(cpu_to_le32(request
[i
]), &ioc
->chip
->Doorbell
);
4635 if ((_base_wait_for_doorbell_ack(ioc
, 5)))
4641 "doorbell handshake sending request failed (line=%d)\n",
4642 ioc
->name
, __LINE__
);
4646 /* now wait for the reply */
4647 if ((_base_wait_for_doorbell_int(ioc
, timeout
))) {
4649 "doorbell handshake int failed (line=%d)\n",
4650 ioc
->name
, __LINE__
);
4654 /* read the first two 16-bits, it gives the total length of the reply */
4655 reply
[0] = le16_to_cpu(readl(&ioc
->chip
->Doorbell
)
4656 & MPI2_DOORBELL_DATA_MASK
);
4657 writel(0, &ioc
->chip
->HostInterruptStatus
);
4658 if ((_base_wait_for_doorbell_int(ioc
, 5))) {
4660 "doorbell handshake int failed (line=%d)\n",
4661 ioc
->name
, __LINE__
);
4664 reply
[1] = le16_to_cpu(readl(&ioc
->chip
->Doorbell
)
4665 & MPI2_DOORBELL_DATA_MASK
);
4666 writel(0, &ioc
->chip
->HostInterruptStatus
);
4668 for (i
= 2; i
< default_reply
->MsgLength
* 2; i
++) {
4669 if ((_base_wait_for_doorbell_int(ioc
, 5))) {
4671 "doorbell handshake int failed (line=%d)\n",
4672 ioc
->name
, __LINE__
);
4675 if (i
>= reply_bytes
/2) /* overflow case */
4676 readl(&ioc
->chip
->Doorbell
);
4678 reply
[i
] = le16_to_cpu(readl(&ioc
->chip
->Doorbell
)
4679 & MPI2_DOORBELL_DATA_MASK
);
4680 writel(0, &ioc
->chip
->HostInterruptStatus
);
4683 _base_wait_for_doorbell_int(ioc
, 5);
4684 if (_base_wait_for_doorbell_not_used(ioc
, 5) != 0) {
4685 dhsprintk(ioc
, pr_info(MPT3SAS_FMT
4686 "doorbell is in use (line=%d)\n", ioc
->name
, __LINE__
));
4688 writel(0, &ioc
->chip
->HostInterruptStatus
);
4690 if (ioc
->logging_level
& MPT_DEBUG_INIT
) {
4691 mfp
= (__le32
*)reply
;
4692 pr_info("\toffset:data\n");
4693 for (i
= 0; i
< reply_bytes
/4; i
++)
4694 pr_info("\t[0x%02x]:%08x\n", i
*4,
4695 le32_to_cpu(mfp
[i
]));
4701 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
4702 * @ioc: per adapter object
4703 * @mpi_reply: the reply payload from FW
4704 * @mpi_request: the request payload sent to FW
4706 * The SAS IO Unit Control Request message allows the host to perform low-level
4707 * operations, such as resets on the PHYs of the IO Unit, also allows the host
4708 * to obtain the IOC assigned device handles for a device if it has other
4709 * identifying information about the device, in addition allows the host to
4710 * remove IOC resources associated with the device.
4712 * Returns 0 for success, non-zero for failure.
4715 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER
*ioc
,
4716 Mpi2SasIoUnitControlReply_t
*mpi_reply
,
4717 Mpi2SasIoUnitControlRequest_t
*mpi_request
)
4721 bool issue_reset
= false;
4724 u16 wait_state_count
;
4726 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
4729 mutex_lock(&ioc
->base_cmds
.mutex
);
4731 if (ioc
->base_cmds
.status
!= MPT3_CMD_NOT_USED
) {
4732 pr_err(MPT3SAS_FMT
"%s: base_cmd in use\n",
4733 ioc
->name
, __func__
);
4738 wait_state_count
= 0;
4739 ioc_state
= mpt3sas_base_get_iocstate(ioc
, 1);
4740 while (ioc_state
!= MPI2_IOC_STATE_OPERATIONAL
) {
4741 if (wait_state_count
++ == 10) {
4743 "%s: failed due to ioc not operational\n",
4744 ioc
->name
, __func__
);
4749 ioc_state
= mpt3sas_base_get_iocstate(ioc
, 1);
4751 "%s: waiting for operational state(count=%d)\n",
4752 ioc
->name
, __func__
, wait_state_count
);
4755 smid
= mpt3sas_base_get_smid(ioc
, ioc
->base_cb_idx
);
4757 pr_err(MPT3SAS_FMT
"%s: failed obtaining a smid\n",
4758 ioc
->name
, __func__
);
4764 ioc
->base_cmds
.status
= MPT3_CMD_PENDING
;
4765 request
= mpt3sas_base_get_msg_frame(ioc
, smid
);
4766 ioc
->base_cmds
.smid
= smid
;
4767 memcpy(request
, mpi_request
, sizeof(Mpi2SasIoUnitControlRequest_t
));
4768 if (mpi_request
->Operation
== MPI2_SAS_OP_PHY_HARD_RESET
||
4769 mpi_request
->Operation
== MPI2_SAS_OP_PHY_LINK_RESET
)
4770 ioc
->ioc_link_reset_in_progress
= 1;
4771 init_completion(&ioc
->base_cmds
.done
);
4772 ioc
->put_smid_default(ioc
, smid
);
4773 wait_for_completion_timeout(&ioc
->base_cmds
.done
,
4774 msecs_to_jiffies(10000));
4775 if ((mpi_request
->Operation
== MPI2_SAS_OP_PHY_HARD_RESET
||
4776 mpi_request
->Operation
== MPI2_SAS_OP_PHY_LINK_RESET
) &&
4777 ioc
->ioc_link_reset_in_progress
)
4778 ioc
->ioc_link_reset_in_progress
= 0;
4779 if (!(ioc
->base_cmds
.status
& MPT3_CMD_COMPLETE
)) {
4780 pr_err(MPT3SAS_FMT
"%s: timeout\n",
4781 ioc
->name
, __func__
);
4782 _debug_dump_mf(mpi_request
,
4783 sizeof(Mpi2SasIoUnitControlRequest_t
)/4);
4784 if (!(ioc
->base_cmds
.status
& MPT3_CMD_RESET
))
4786 goto issue_host_reset
;
4788 if (ioc
->base_cmds
.status
& MPT3_CMD_REPLY_VALID
)
4789 memcpy(mpi_reply
, ioc
->base_cmds
.reply
,
4790 sizeof(Mpi2SasIoUnitControlReply_t
));
4792 memset(mpi_reply
, 0, sizeof(Mpi2SasIoUnitControlReply_t
));
4793 ioc
->base_cmds
.status
= MPT3_CMD_NOT_USED
;
4798 mpt3sas_base_hard_reset_handler(ioc
, FORCE_BIG_HAMMER
);
4799 ioc
->base_cmds
.status
= MPT3_CMD_NOT_USED
;
4802 mutex_unlock(&ioc
->base_cmds
.mutex
);
4807 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
4808 * @ioc: per adapter object
4809 * @mpi_reply: the reply payload from FW
4810 * @mpi_request: the request payload sent to FW
4812 * The SCSI Enclosure Processor request message causes the IOC to
4813 * communicate with SES devices to control LED status signals.
4815 * Returns 0 for success, non-zero for failure.
4818 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER
*ioc
,
4819 Mpi2SepReply_t
*mpi_reply
, Mpi2SepRequest_t
*mpi_request
)
4823 bool issue_reset
= false;
4826 u16 wait_state_count
;
4828 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
4831 mutex_lock(&ioc
->base_cmds
.mutex
);
4833 if (ioc
->base_cmds
.status
!= MPT3_CMD_NOT_USED
) {
4834 pr_err(MPT3SAS_FMT
"%s: base_cmd in use\n",
4835 ioc
->name
, __func__
);
4840 wait_state_count
= 0;
4841 ioc_state
= mpt3sas_base_get_iocstate(ioc
, 1);
4842 while (ioc_state
!= MPI2_IOC_STATE_OPERATIONAL
) {
4843 if (wait_state_count
++ == 10) {
4845 "%s: failed due to ioc not operational\n",
4846 ioc
->name
, __func__
);
4851 ioc_state
= mpt3sas_base_get_iocstate(ioc
, 1);
4853 "%s: waiting for operational state(count=%d)\n",
4855 __func__
, wait_state_count
);
4858 smid
= mpt3sas_base_get_smid(ioc
, ioc
->base_cb_idx
);
4860 pr_err(MPT3SAS_FMT
"%s: failed obtaining a smid\n",
4861 ioc
->name
, __func__
);
4867 ioc
->base_cmds
.status
= MPT3_CMD_PENDING
;
4868 request
= mpt3sas_base_get_msg_frame(ioc
, smid
);
4869 ioc
->base_cmds
.smid
= smid
;
4870 memcpy(request
, mpi_request
, sizeof(Mpi2SepReply_t
));
4871 init_completion(&ioc
->base_cmds
.done
);
4872 ioc
->put_smid_default(ioc
, smid
);
4873 wait_for_completion_timeout(&ioc
->base_cmds
.done
,
4874 msecs_to_jiffies(10000));
4875 if (!(ioc
->base_cmds
.status
& MPT3_CMD_COMPLETE
)) {
4876 pr_err(MPT3SAS_FMT
"%s: timeout\n",
4877 ioc
->name
, __func__
);
4878 _debug_dump_mf(mpi_request
,
4879 sizeof(Mpi2SepRequest_t
)/4);
4880 if (!(ioc
->base_cmds
.status
& MPT3_CMD_RESET
))
4881 issue_reset
= false;
4882 goto issue_host_reset
;
4884 if (ioc
->base_cmds
.status
& MPT3_CMD_REPLY_VALID
)
4885 memcpy(mpi_reply
, ioc
->base_cmds
.reply
,
4886 sizeof(Mpi2SepReply_t
));
4888 memset(mpi_reply
, 0, sizeof(Mpi2SepReply_t
));
4889 ioc
->base_cmds
.status
= MPT3_CMD_NOT_USED
;
4894 mpt3sas_base_hard_reset_handler(ioc
, FORCE_BIG_HAMMER
);
4895 ioc
->base_cmds
.status
= MPT3_CMD_NOT_USED
;
4898 mutex_unlock(&ioc
->base_cmds
.mutex
);
4903 * _base_get_port_facts - obtain port facts reply and save in ioc
4904 * @ioc: per adapter object
4906 * Returns 0 for success, non-zero for failure.
4909 _base_get_port_facts(struct MPT3SAS_ADAPTER
*ioc
, int port
)
4911 Mpi2PortFactsRequest_t mpi_request
;
4912 Mpi2PortFactsReply_t mpi_reply
;
4913 struct mpt3sas_port_facts
*pfacts
;
4914 int mpi_reply_sz
, mpi_request_sz
, r
;
4916 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
4919 mpi_reply_sz
= sizeof(Mpi2PortFactsReply_t
);
4920 mpi_request_sz
= sizeof(Mpi2PortFactsRequest_t
);
4921 memset(&mpi_request
, 0, mpi_request_sz
);
4922 mpi_request
.Function
= MPI2_FUNCTION_PORT_FACTS
;
4923 mpi_request
.PortNumber
= port
;
4924 r
= _base_handshake_req_reply_wait(ioc
, mpi_request_sz
,
4925 (u32
*)&mpi_request
, mpi_reply_sz
, (u16
*)&mpi_reply
, 5);
4928 pr_err(MPT3SAS_FMT
"%s: handshake failed (r=%d)\n",
4929 ioc
->name
, __func__
, r
);
4933 pfacts
= &ioc
->pfacts
[port
];
4934 memset(pfacts
, 0, sizeof(struct mpt3sas_port_facts
));
4935 pfacts
->PortNumber
= mpi_reply
.PortNumber
;
4936 pfacts
->VP_ID
= mpi_reply
.VP_ID
;
4937 pfacts
->VF_ID
= mpi_reply
.VF_ID
;
4938 pfacts
->MaxPostedCmdBuffers
=
4939 le16_to_cpu(mpi_reply
.MaxPostedCmdBuffers
);
4945 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
4946 * @ioc: per adapter object
4949 * Returns 0 for success, non-zero for failure.
4952 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER
*ioc
, int timeout
)
4957 dinitprintk(ioc
, printk(MPT3SAS_FMT
"%s\n", ioc
->name
,
4960 if (ioc
->pci_error_recovery
) {
4961 dfailprintk(ioc
, printk(MPT3SAS_FMT
4962 "%s: host in pci error recovery\n", ioc
->name
, __func__
));
4966 ioc_state
= mpt3sas_base_get_iocstate(ioc
, 0);
4967 dhsprintk(ioc
, printk(MPT3SAS_FMT
"%s: ioc_state(0x%08x)\n",
4968 ioc
->name
, __func__
, ioc_state
));
4970 if (((ioc_state
& MPI2_IOC_STATE_MASK
) == MPI2_IOC_STATE_READY
) ||
4971 (ioc_state
& MPI2_IOC_STATE_MASK
) == MPI2_IOC_STATE_OPERATIONAL
)
4974 if (ioc_state
& MPI2_DOORBELL_USED
) {
4975 dhsprintk(ioc
, printk(MPT3SAS_FMT
4976 "unexpected doorbell active!\n", ioc
->name
));
4977 goto issue_diag_reset
;
4980 if ((ioc_state
& MPI2_IOC_STATE_MASK
) == MPI2_IOC_STATE_FAULT
) {
4981 mpt3sas_base_fault_info(ioc
, ioc_state
&
4982 MPI2_DOORBELL_DATA_MASK
);
4983 goto issue_diag_reset
;
4986 ioc_state
= _base_wait_on_iocstate(ioc
, MPI2_IOC_STATE_READY
, timeout
);
4988 dfailprintk(ioc
, printk(MPT3SAS_FMT
4989 "%s: failed going to ready state (ioc_state=0x%x)\n",
4990 ioc
->name
, __func__
, ioc_state
));
4995 rc
= _base_diag_reset(ioc
);
5000 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
5001 * @ioc: per adapter object
5003 * Returns 0 for success, non-zero for failure.
5006 _base_get_ioc_facts(struct MPT3SAS_ADAPTER
*ioc
)
5008 Mpi2IOCFactsRequest_t mpi_request
;
5009 Mpi2IOCFactsReply_t mpi_reply
;
5010 struct mpt3sas_facts
*facts
;
5011 int mpi_reply_sz
, mpi_request_sz
, r
;
5013 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
5016 r
= _base_wait_for_iocstate(ioc
, 10);
5018 dfailprintk(ioc
, printk(MPT3SAS_FMT
5019 "%s: failed getting to correct state\n",
5020 ioc
->name
, __func__
));
5023 mpi_reply_sz
= sizeof(Mpi2IOCFactsReply_t
);
5024 mpi_request_sz
= sizeof(Mpi2IOCFactsRequest_t
);
5025 memset(&mpi_request
, 0, mpi_request_sz
);
5026 mpi_request
.Function
= MPI2_FUNCTION_IOC_FACTS
;
5027 r
= _base_handshake_req_reply_wait(ioc
, mpi_request_sz
,
5028 (u32
*)&mpi_request
, mpi_reply_sz
, (u16
*)&mpi_reply
, 5);
5031 pr_err(MPT3SAS_FMT
"%s: handshake failed (r=%d)\n",
5032 ioc
->name
, __func__
, r
);
5036 facts
= &ioc
->facts
;
5037 memset(facts
, 0, sizeof(struct mpt3sas_facts
));
5038 facts
->MsgVersion
= le16_to_cpu(mpi_reply
.MsgVersion
);
5039 facts
->HeaderVersion
= le16_to_cpu(mpi_reply
.HeaderVersion
);
5040 facts
->VP_ID
= mpi_reply
.VP_ID
;
5041 facts
->VF_ID
= mpi_reply
.VF_ID
;
5042 facts
->IOCExceptions
= le16_to_cpu(mpi_reply
.IOCExceptions
);
5043 facts
->MaxChainDepth
= mpi_reply
.MaxChainDepth
;
5044 facts
->WhoInit
= mpi_reply
.WhoInit
;
5045 facts
->NumberOfPorts
= mpi_reply
.NumberOfPorts
;
5046 facts
->MaxMSIxVectors
= mpi_reply
.MaxMSIxVectors
;
5047 facts
->RequestCredit
= le16_to_cpu(mpi_reply
.RequestCredit
);
5048 facts
->MaxReplyDescriptorPostQueueDepth
=
5049 le16_to_cpu(mpi_reply
.MaxReplyDescriptorPostQueueDepth
);
5050 facts
->ProductID
= le16_to_cpu(mpi_reply
.ProductID
);
5051 facts
->IOCCapabilities
= le32_to_cpu(mpi_reply
.IOCCapabilities
);
5052 if ((facts
->IOCCapabilities
& MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID
))
5053 ioc
->ir_firmware
= 1;
5054 if ((facts
->IOCCapabilities
&
5055 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE
) && (!reset_devices
))
5056 ioc
->rdpq_array_capable
= 1;
5057 if (facts
->IOCCapabilities
& MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ
)
5058 ioc
->atomic_desc_capable
= 1;
5059 facts
->FWVersion
.Word
= le32_to_cpu(mpi_reply
.FWVersion
.Word
);
5060 facts
->IOCRequestFrameSize
=
5061 le16_to_cpu(mpi_reply
.IOCRequestFrameSize
);
5062 if (ioc
->hba_mpi_version_belonged
!= MPI2_VERSION
) {
5063 facts
->IOCMaxChainSegmentSize
=
5064 le16_to_cpu(mpi_reply
.IOCMaxChainSegmentSize
);
5066 facts
->MaxInitiators
= le16_to_cpu(mpi_reply
.MaxInitiators
);
5067 facts
->MaxTargets
= le16_to_cpu(mpi_reply
.MaxTargets
);
5068 ioc
->shost
->max_id
= -1;
5069 facts
->MaxSasExpanders
= le16_to_cpu(mpi_reply
.MaxSasExpanders
);
5070 facts
->MaxEnclosures
= le16_to_cpu(mpi_reply
.MaxEnclosures
);
5071 facts
->ProtocolFlags
= le16_to_cpu(mpi_reply
.ProtocolFlags
);
5072 facts
->HighPriorityCredit
=
5073 le16_to_cpu(mpi_reply
.HighPriorityCredit
);
5074 facts
->ReplyFrameSize
= mpi_reply
.ReplyFrameSize
;
5075 facts
->MaxDevHandle
= le16_to_cpu(mpi_reply
.MaxDevHandle
);
5076 facts
->CurrentHostPageSize
= mpi_reply
.CurrentHostPageSize
;
5079 * Get the Page Size from IOC Facts. If it's 0, default to 4k.
5081 ioc
->page_size
= 1 << facts
->CurrentHostPageSize
;
5082 if (ioc
->page_size
== 1) {
5083 pr_info(MPT3SAS_FMT
"CurrentHostPageSize is 0: Setting "
5084 "default host page size to 4k\n", ioc
->name
);
5085 ioc
->page_size
= 1 << MPT3SAS_HOST_PAGE_SIZE_4K
;
5087 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"CurrentHostPageSize(%d)\n",
5088 ioc
->name
, facts
->CurrentHostPageSize
));
5090 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
5091 "hba queue depth(%d), max chains per io(%d)\n",
5092 ioc
->name
, facts
->RequestCredit
,
5093 facts
->MaxChainDepth
));
5094 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
5095 "request frame size(%d), reply frame size(%d)\n", ioc
->name
,
5096 facts
->IOCRequestFrameSize
* 4, facts
->ReplyFrameSize
* 4));
5101 * _base_send_ioc_init - send ioc_init to firmware
5102 * @ioc: per adapter object
5104 * Returns 0 for success, non-zero for failure.
5107 _base_send_ioc_init(struct MPT3SAS_ADAPTER
*ioc
)
5109 Mpi2IOCInitRequest_t mpi_request
;
5110 Mpi2IOCInitReply_t mpi_reply
;
5112 ktime_t current_time
;
5114 u32 reply_post_free_array_sz
= 0;
5115 Mpi2IOCInitRDPQArrayEntry
*reply_post_free_array
= NULL
;
5116 dma_addr_t reply_post_free_array_dma
;
5118 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
5121 memset(&mpi_request
, 0, sizeof(Mpi2IOCInitRequest_t
));
5122 mpi_request
.Function
= MPI2_FUNCTION_IOC_INIT
;
5123 mpi_request
.WhoInit
= MPI2_WHOINIT_HOST_DRIVER
;
5124 mpi_request
.VF_ID
= 0; /* TODO */
5125 mpi_request
.VP_ID
= 0;
5126 mpi_request
.MsgVersion
= cpu_to_le16(ioc
->hba_mpi_version_belonged
);
5127 mpi_request
.HeaderVersion
= cpu_to_le16(MPI2_HEADER_VERSION
);
5128 mpi_request
.HostPageSize
= MPT3SAS_HOST_PAGE_SIZE_4K
;
5130 if (_base_is_controller_msix_enabled(ioc
))
5131 mpi_request
.HostMSIxVectors
= ioc
->reply_queue_count
;
5132 mpi_request
.SystemRequestFrameSize
= cpu_to_le16(ioc
->request_sz
/4);
5133 mpi_request
.ReplyDescriptorPostQueueDepth
=
5134 cpu_to_le16(ioc
->reply_post_queue_depth
);
5135 mpi_request
.ReplyFreeQueueDepth
=
5136 cpu_to_le16(ioc
->reply_free_queue_depth
);
5138 mpi_request
.SenseBufferAddressHigh
=
5139 cpu_to_le32((u64
)ioc
->sense_dma
>> 32);
5140 mpi_request
.SystemReplyAddressHigh
=
5141 cpu_to_le32((u64
)ioc
->reply_dma
>> 32);
5142 mpi_request
.SystemRequestFrameBaseAddress
=
5143 cpu_to_le64((u64
)ioc
->request_dma
);
5144 mpi_request
.ReplyFreeQueueAddress
=
5145 cpu_to_le64((u64
)ioc
->reply_free_dma
);
5147 if (ioc
->rdpq_array_enable
) {
5148 reply_post_free_array_sz
= ioc
->reply_queue_count
*
5149 sizeof(Mpi2IOCInitRDPQArrayEntry
);
5150 reply_post_free_array
= pci_alloc_consistent(ioc
->pdev
,
5151 reply_post_free_array_sz
, &reply_post_free_array_dma
);
5152 if (!reply_post_free_array
) {
5154 "reply_post_free_array: pci_alloc_consistent failed\n",
5159 memset(reply_post_free_array
, 0, reply_post_free_array_sz
);
5160 for (i
= 0; i
< ioc
->reply_queue_count
; i
++)
5161 reply_post_free_array
[i
].RDPQBaseAddress
=
5163 (u64
)ioc
->reply_post
[i
].reply_post_free_dma
);
5164 mpi_request
.MsgFlags
= MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
;
5165 mpi_request
.ReplyDescriptorPostQueueAddress
=
5166 cpu_to_le64((u64
)reply_post_free_array_dma
);
5168 mpi_request
.ReplyDescriptorPostQueueAddress
=
5169 cpu_to_le64((u64
)ioc
->reply_post
[0].reply_post_free_dma
);
5172 /* This time stamp specifies number of milliseconds
5173 * since epoch ~ midnight January 1, 1970.
5175 current_time
= ktime_get_real();
5176 mpi_request
.TimeStamp
= cpu_to_le64(ktime_to_ms(current_time
));
5178 if (ioc
->logging_level
& MPT_DEBUG_INIT
) {
5182 mfp
= (__le32
*)&mpi_request
;
5183 pr_info("\toffset:data\n");
5184 for (i
= 0; i
< sizeof(Mpi2IOCInitRequest_t
)/4; i
++)
5185 pr_info("\t[0x%02x]:%08x\n", i
*4,
5186 le32_to_cpu(mfp
[i
]));
5189 r
= _base_handshake_req_reply_wait(ioc
,
5190 sizeof(Mpi2IOCInitRequest_t
), (u32
*)&mpi_request
,
5191 sizeof(Mpi2IOCInitReply_t
), (u16
*)&mpi_reply
, 10);
5194 pr_err(MPT3SAS_FMT
"%s: handshake failed (r=%d)\n",
5195 ioc
->name
, __func__
, r
);
5199 ioc_status
= le16_to_cpu(mpi_reply
.IOCStatus
) & MPI2_IOCSTATUS_MASK
;
5200 if (ioc_status
!= MPI2_IOCSTATUS_SUCCESS
||
5201 mpi_reply
.IOCLogInfo
) {
5202 pr_err(MPT3SAS_FMT
"%s: failed\n", ioc
->name
, __func__
);
5207 if (reply_post_free_array
)
5208 pci_free_consistent(ioc
->pdev
, reply_post_free_array_sz
,
5209 reply_post_free_array
,
5210 reply_post_free_array_dma
);
5215 * mpt3sas_port_enable_done - command completion routine for port enable
5216 * @ioc: per adapter object
5217 * @smid: system request message index
5218 * @msix_index: MSIX table index supplied by the OS
5219 * @reply: reply message frame(lower 32bit addr)
5221 * Return 1 meaning mf should be freed from _base_interrupt
5222 * 0 means the mf is freed from this function.
5225 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER
*ioc
, u16 smid
, u8 msix_index
,
5228 MPI2DefaultReply_t
*mpi_reply
;
5231 if (ioc
->port_enable_cmds
.status
== MPT3_CMD_NOT_USED
)
5234 mpi_reply
= mpt3sas_base_get_reply_virt_addr(ioc
, reply
);
5238 if (mpi_reply
->Function
!= MPI2_FUNCTION_PORT_ENABLE
)
5241 ioc
->port_enable_cmds
.status
&= ~MPT3_CMD_PENDING
;
5242 ioc
->port_enable_cmds
.status
|= MPT3_CMD_COMPLETE
;
5243 ioc
->port_enable_cmds
.status
|= MPT3_CMD_REPLY_VALID
;
5244 memcpy(ioc
->port_enable_cmds
.reply
, mpi_reply
, mpi_reply
->MsgLength
*4);
5245 ioc_status
= le16_to_cpu(mpi_reply
->IOCStatus
) & MPI2_IOCSTATUS_MASK
;
5246 if (ioc_status
!= MPI2_IOCSTATUS_SUCCESS
)
5247 ioc
->port_enable_failed
= 1;
5249 if (ioc
->is_driver_loading
) {
5250 if (ioc_status
== MPI2_IOCSTATUS_SUCCESS
) {
5251 mpt3sas_port_enable_complete(ioc
);
5254 ioc
->start_scan_failed
= ioc_status
;
5255 ioc
->start_scan
= 0;
5259 complete(&ioc
->port_enable_cmds
.done
);
5264 * _base_send_port_enable - send port_enable(discovery stuff) to firmware
5265 * @ioc: per adapter object
5267 * Returns 0 for success, non-zero for failure.
5270 _base_send_port_enable(struct MPT3SAS_ADAPTER
*ioc
)
5272 Mpi2PortEnableRequest_t
*mpi_request
;
5273 Mpi2PortEnableReply_t
*mpi_reply
;
5278 pr_info(MPT3SAS_FMT
"sending port enable !!\n", ioc
->name
);
5280 if (ioc
->port_enable_cmds
.status
& MPT3_CMD_PENDING
) {
5281 pr_err(MPT3SAS_FMT
"%s: internal command already in use\n",
5282 ioc
->name
, __func__
);
5286 smid
= mpt3sas_base_get_smid(ioc
, ioc
->port_enable_cb_idx
);
5288 pr_err(MPT3SAS_FMT
"%s: failed obtaining a smid\n",
5289 ioc
->name
, __func__
);
5293 ioc
->port_enable_cmds
.status
= MPT3_CMD_PENDING
;
5294 mpi_request
= mpt3sas_base_get_msg_frame(ioc
, smid
);
5295 ioc
->port_enable_cmds
.smid
= smid
;
5296 memset(mpi_request
, 0, sizeof(Mpi2PortEnableRequest_t
));
5297 mpi_request
->Function
= MPI2_FUNCTION_PORT_ENABLE
;
5299 init_completion(&ioc
->port_enable_cmds
.done
);
5300 ioc
->put_smid_default(ioc
, smid
);
5301 wait_for_completion_timeout(&ioc
->port_enable_cmds
.done
, 300*HZ
);
5302 if (!(ioc
->port_enable_cmds
.status
& MPT3_CMD_COMPLETE
)) {
5303 pr_err(MPT3SAS_FMT
"%s: timeout\n",
5304 ioc
->name
, __func__
);
5305 _debug_dump_mf(mpi_request
,
5306 sizeof(Mpi2PortEnableRequest_t
)/4);
5307 if (ioc
->port_enable_cmds
.status
& MPT3_CMD_RESET
)
5314 mpi_reply
= ioc
->port_enable_cmds
.reply
;
5315 ioc_status
= le16_to_cpu(mpi_reply
->IOCStatus
) & MPI2_IOCSTATUS_MASK
;
5316 if (ioc_status
!= MPI2_IOCSTATUS_SUCCESS
) {
5317 pr_err(MPT3SAS_FMT
"%s: failed with (ioc_status=0x%08x)\n",
5318 ioc
->name
, __func__
, ioc_status
);
5324 ioc
->port_enable_cmds
.status
= MPT3_CMD_NOT_USED
;
5325 pr_info(MPT3SAS_FMT
"port enable: %s\n", ioc
->name
, ((r
== 0) ?
5326 "SUCCESS" : "FAILED"));
5331 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
5332 * @ioc: per adapter object
5334 * Returns 0 for success, non-zero for failure.
5337 mpt3sas_port_enable(struct MPT3SAS_ADAPTER
*ioc
)
5339 Mpi2PortEnableRequest_t
*mpi_request
;
5342 pr_info(MPT3SAS_FMT
"sending port enable !!\n", ioc
->name
);
5344 if (ioc
->port_enable_cmds
.status
& MPT3_CMD_PENDING
) {
5345 pr_err(MPT3SAS_FMT
"%s: internal command already in use\n",
5346 ioc
->name
, __func__
);
5350 smid
= mpt3sas_base_get_smid(ioc
, ioc
->port_enable_cb_idx
);
5352 pr_err(MPT3SAS_FMT
"%s: failed obtaining a smid\n",
5353 ioc
->name
, __func__
);
5357 ioc
->port_enable_cmds
.status
= MPT3_CMD_PENDING
;
5358 mpi_request
= mpt3sas_base_get_msg_frame(ioc
, smid
);
5359 ioc
->port_enable_cmds
.smid
= smid
;
5360 memset(mpi_request
, 0, sizeof(Mpi2PortEnableRequest_t
));
5361 mpi_request
->Function
= MPI2_FUNCTION_PORT_ENABLE
;
5363 ioc
->put_smid_default(ioc
, smid
);
5368 * _base_determine_wait_on_discovery - desposition
5369 * @ioc: per adapter object
5371 * Decide whether to wait on discovery to complete. Used to either
5372 * locate boot device, or report volumes ahead of physical devices.
5374 * Returns 1 for wait, 0 for don't wait
5377 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER
*ioc
)
5379 /* We wait for discovery to complete if IR firmware is loaded.
5380 * The sas topology events arrive before PD events, so we need time to
5381 * turn on the bit in ioc->pd_handles to indicate PD
5382 * Also, it maybe required to report Volumes ahead of physical
5383 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
5385 if (ioc
->ir_firmware
)
5388 /* if no Bios, then we don't need to wait */
5389 if (!ioc
->bios_pg3
.BiosVersion
)
5392 /* Bios is present, then we drop down here.
5394 * If there any entries in the Bios Page 2, then we wait
5395 * for discovery to complete.
5398 /* Current Boot Device */
5399 if ((ioc
->bios_pg2
.CurrentBootDeviceForm
&
5400 MPI2_BIOSPAGE2_FORM_MASK
) ==
5401 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED
&&
5402 /* Request Boot Device */
5403 (ioc
->bios_pg2
.ReqBootDeviceForm
&
5404 MPI2_BIOSPAGE2_FORM_MASK
) ==
5405 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED
&&
5406 /* Alternate Request Boot Device */
5407 (ioc
->bios_pg2
.ReqAltBootDeviceForm
&
5408 MPI2_BIOSPAGE2_FORM_MASK
) ==
5409 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED
)
5416 * _base_unmask_events - turn on notification for this event
5417 * @ioc: per adapter object
5418 * @event: firmware event
5420 * The mask is stored in ioc->event_masks.
5423 _base_unmask_events(struct MPT3SAS_ADAPTER
*ioc
, u16 event
)
5430 desired_event
= (1 << (event
% 32));
5433 ioc
->event_masks
[0] &= ~desired_event
;
5434 else if (event
< 64)
5435 ioc
->event_masks
[1] &= ~desired_event
;
5436 else if (event
< 96)
5437 ioc
->event_masks
[2] &= ~desired_event
;
5438 else if (event
< 128)
5439 ioc
->event_masks
[3] &= ~desired_event
;
5443 * _base_event_notification - send event notification
5444 * @ioc: per adapter object
5446 * Returns 0 for success, non-zero for failure.
5449 _base_event_notification(struct MPT3SAS_ADAPTER
*ioc
)
5451 Mpi2EventNotificationRequest_t
*mpi_request
;
5456 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
5459 if (ioc
->base_cmds
.status
& MPT3_CMD_PENDING
) {
5460 pr_err(MPT3SAS_FMT
"%s: internal command already in use\n",
5461 ioc
->name
, __func__
);
5465 smid
= mpt3sas_base_get_smid(ioc
, ioc
->base_cb_idx
);
5467 pr_err(MPT3SAS_FMT
"%s: failed obtaining a smid\n",
5468 ioc
->name
, __func__
);
5471 ioc
->base_cmds
.status
= MPT3_CMD_PENDING
;
5472 mpi_request
= mpt3sas_base_get_msg_frame(ioc
, smid
);
5473 ioc
->base_cmds
.smid
= smid
;
5474 memset(mpi_request
, 0, sizeof(Mpi2EventNotificationRequest_t
));
5475 mpi_request
->Function
= MPI2_FUNCTION_EVENT_NOTIFICATION
;
5476 mpi_request
->VF_ID
= 0; /* TODO */
5477 mpi_request
->VP_ID
= 0;
5478 for (i
= 0; i
< MPI2_EVENT_NOTIFY_EVENTMASK_WORDS
; i
++)
5479 mpi_request
->EventMasks
[i
] =
5480 cpu_to_le32(ioc
->event_masks
[i
]);
5481 init_completion(&ioc
->base_cmds
.done
);
5482 ioc
->put_smid_default(ioc
, smid
);
5483 wait_for_completion_timeout(&ioc
->base_cmds
.done
, 30*HZ
);
5484 if (!(ioc
->base_cmds
.status
& MPT3_CMD_COMPLETE
)) {
5485 pr_err(MPT3SAS_FMT
"%s: timeout\n",
5486 ioc
->name
, __func__
);
5487 _debug_dump_mf(mpi_request
,
5488 sizeof(Mpi2EventNotificationRequest_t
)/4);
5489 if (ioc
->base_cmds
.status
& MPT3_CMD_RESET
)
5494 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s: complete\n",
5495 ioc
->name
, __func__
));
5496 ioc
->base_cmds
.status
= MPT3_CMD_NOT_USED
;
5501 * mpt3sas_base_validate_event_type - validating event types
5502 * @ioc: per adapter object
5503 * @event: firmware event
5505 * This will turn on firmware event notification when application
5506 * ask for that event. We don't mask events that are already enabled.
5509 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER
*ioc
, u32
*event_type
)
5512 u32 event_mask
, desired_event
;
5513 u8 send_update_to_fw
;
5515 for (i
= 0, send_update_to_fw
= 0; i
<
5516 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS
; i
++) {
5517 event_mask
= ~event_type
[i
];
5519 for (j
= 0; j
< 32; j
++) {
5520 if (!(event_mask
& desired_event
) &&
5521 (ioc
->event_masks
[i
] & desired_event
)) {
5522 ioc
->event_masks
[i
] &= ~desired_event
;
5523 send_update_to_fw
= 1;
5525 desired_event
= (desired_event
<< 1);
5529 if (!send_update_to_fw
)
5532 mutex_lock(&ioc
->base_cmds
.mutex
);
5533 _base_event_notification(ioc
);
5534 mutex_unlock(&ioc
->base_cmds
.mutex
);
5538 * _base_diag_reset - the "big hammer" start of day reset
5539 * @ioc: per adapter object
5541 * Returns 0 for success, non-zero for failure.
5544 _base_diag_reset(struct MPT3SAS_ADAPTER
*ioc
)
5546 u32 host_diagnostic
;
5551 pr_info(MPT3SAS_FMT
"sending diag reset !!\n", ioc
->name
);
5553 drsprintk(ioc
, pr_info(MPT3SAS_FMT
"clear interrupts\n",
5558 /* Write magic sequence to WriteSequence register
5559 * Loop until in diagnostic mode
5561 drsprintk(ioc
, pr_info(MPT3SAS_FMT
5562 "write magic sequence\n", ioc
->name
));
5563 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE
, &ioc
->chip
->WriteSequence
);
5564 writel(MPI2_WRSEQ_1ST_KEY_VALUE
, &ioc
->chip
->WriteSequence
);
5565 writel(MPI2_WRSEQ_2ND_KEY_VALUE
, &ioc
->chip
->WriteSequence
);
5566 writel(MPI2_WRSEQ_3RD_KEY_VALUE
, &ioc
->chip
->WriteSequence
);
5567 writel(MPI2_WRSEQ_4TH_KEY_VALUE
, &ioc
->chip
->WriteSequence
);
5568 writel(MPI2_WRSEQ_5TH_KEY_VALUE
, &ioc
->chip
->WriteSequence
);
5569 writel(MPI2_WRSEQ_6TH_KEY_VALUE
, &ioc
->chip
->WriteSequence
);
5577 host_diagnostic
= readl(&ioc
->chip
->HostDiagnostic
);
5578 drsprintk(ioc
, pr_info(MPT3SAS_FMT
5579 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
5580 ioc
->name
, count
, host_diagnostic
));
5582 } while ((host_diagnostic
& MPI2_DIAG_DIAG_WRITE_ENABLE
) == 0);
5584 hcb_size
= readl(&ioc
->chip
->HCBSize
);
5586 drsprintk(ioc
, pr_info(MPT3SAS_FMT
"diag reset: issued\n",
5588 writel(host_diagnostic
| MPI2_DIAG_RESET_ADAPTER
,
5589 &ioc
->chip
->HostDiagnostic
);
5591 /*This delay allows the chip PCIe hardware time to finish reset tasks*/
5592 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC
/1000);
5594 /* Approximately 300 second max wait */
5595 for (count
= 0; count
< (300000000 /
5596 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
); count
++) {
5598 host_diagnostic
= readl(&ioc
->chip
->HostDiagnostic
);
5600 if (host_diagnostic
== 0xFFFFFFFF)
5602 if (!(host_diagnostic
& MPI2_DIAG_RESET_ADAPTER
))
5605 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
/ 1000);
5608 if (host_diagnostic
& MPI2_DIAG_HCB_MODE
) {
5610 drsprintk(ioc
, pr_info(MPT3SAS_FMT
5611 "restart the adapter assuming the HCB Address points to good F/W\n",
5613 host_diagnostic
&= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK
;
5614 host_diagnostic
|= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW
;
5615 writel(host_diagnostic
, &ioc
->chip
->HostDiagnostic
);
5617 drsprintk(ioc
, pr_info(MPT3SAS_FMT
5618 "re-enable the HCDW\n", ioc
->name
));
5619 writel(hcb_size
| MPI2_HCB_SIZE_HCB_ENABLE
,
5620 &ioc
->chip
->HCBSize
);
5623 drsprintk(ioc
, pr_info(MPT3SAS_FMT
"restart the adapter\n",
5625 writel(host_diagnostic
& ~MPI2_DIAG_HOLD_IOC_RESET
,
5626 &ioc
->chip
->HostDiagnostic
);
5628 drsprintk(ioc
, pr_info(MPT3SAS_FMT
5629 "disable writes to the diagnostic register\n", ioc
->name
));
5630 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE
, &ioc
->chip
->WriteSequence
);
5632 drsprintk(ioc
, pr_info(MPT3SAS_FMT
5633 "Wait for FW to go to the READY state\n", ioc
->name
));
5634 ioc_state
= _base_wait_on_iocstate(ioc
, MPI2_IOC_STATE_READY
, 20);
5637 "%s: failed going to ready state (ioc_state=0x%x)\n",
5638 ioc
->name
, __func__
, ioc_state
);
5642 pr_info(MPT3SAS_FMT
"diag reset: SUCCESS\n", ioc
->name
);
5646 pr_err(MPT3SAS_FMT
"diag reset: FAILED\n", ioc
->name
);
5651 * _base_make_ioc_ready - put controller in READY state
5652 * @ioc: per adapter object
5653 * @type: FORCE_BIG_HAMMER or SOFT_RESET
5655 * Returns 0 for success, non-zero for failure.
5658 _base_make_ioc_ready(struct MPT3SAS_ADAPTER
*ioc
, enum reset_type type
)
5664 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
5667 if (ioc
->pci_error_recovery
)
5670 ioc_state
= mpt3sas_base_get_iocstate(ioc
, 0);
5671 dhsprintk(ioc
, pr_info(MPT3SAS_FMT
"%s: ioc_state(0x%08x)\n",
5672 ioc
->name
, __func__
, ioc_state
));
5674 /* if in RESET state, it should move to READY state shortly */
5676 if ((ioc_state
& MPI2_IOC_STATE_MASK
) == MPI2_IOC_STATE_RESET
) {
5677 while ((ioc_state
& MPI2_IOC_STATE_MASK
) !=
5678 MPI2_IOC_STATE_READY
) {
5679 if (count
++ == 10) {
5681 "%s: failed going to ready state (ioc_state=0x%x)\n",
5682 ioc
->name
, __func__
, ioc_state
);
5686 ioc_state
= mpt3sas_base_get_iocstate(ioc
, 0);
5690 if ((ioc_state
& MPI2_IOC_STATE_MASK
) == MPI2_IOC_STATE_READY
)
5693 if (ioc_state
& MPI2_DOORBELL_USED
) {
5694 dhsprintk(ioc
, pr_info(MPT3SAS_FMT
5695 "unexpected doorbell active!\n",
5697 goto issue_diag_reset
;
5700 if ((ioc_state
& MPI2_IOC_STATE_MASK
) == MPI2_IOC_STATE_FAULT
) {
5701 mpt3sas_base_fault_info(ioc
, ioc_state
&
5702 MPI2_DOORBELL_DATA_MASK
);
5703 goto issue_diag_reset
;
5706 if (type
== FORCE_BIG_HAMMER
)
5707 goto issue_diag_reset
;
5709 if ((ioc_state
& MPI2_IOC_STATE_MASK
) == MPI2_IOC_STATE_OPERATIONAL
)
5710 if (!(_base_send_ioc_reset(ioc
,
5711 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
, 15))) {
5716 rc
= _base_diag_reset(ioc
);
5721 * _base_make_ioc_operational - put controller in OPERATIONAL state
5722 * @ioc: per adapter object
5724 * Returns 0 for success, non-zero for failure.
5727 _base_make_ioc_operational(struct MPT3SAS_ADAPTER
*ioc
)
5730 unsigned long flags
;
5733 struct _tr_list
*delayed_tr
, *delayed_tr_next
;
5734 struct _sc_list
*delayed_sc
, *delayed_sc_next
;
5735 struct _event_ack_list
*delayed_event_ack
, *delayed_event_ack_next
;
5737 struct adapter_reply_queue
*reply_q
;
5738 Mpi2ReplyDescriptorsUnion_t
*reply_post_free_contig
;
5740 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
5743 /* clean the delayed target reset list */
5744 list_for_each_entry_safe(delayed_tr
, delayed_tr_next
,
5745 &ioc
->delayed_tr_list
, list
) {
5746 list_del(&delayed_tr
->list
);
5751 list_for_each_entry_safe(delayed_tr
, delayed_tr_next
,
5752 &ioc
->delayed_tr_volume_list
, list
) {
5753 list_del(&delayed_tr
->list
);
5757 list_for_each_entry_safe(delayed_sc
, delayed_sc_next
,
5758 &ioc
->delayed_sc_list
, list
) {
5759 list_del(&delayed_sc
->list
);
5763 list_for_each_entry_safe(delayed_event_ack
, delayed_event_ack_next
,
5764 &ioc
->delayed_event_ack_list
, list
) {
5765 list_del(&delayed_event_ack
->list
);
5766 kfree(delayed_event_ack
);
5769 /* initialize the scsi lookup free list */
5770 spin_lock_irqsave(&ioc
->scsi_lookup_lock
, flags
);
5771 INIT_LIST_HEAD(&ioc
->free_list
);
5773 for (i
= 0; i
< ioc
->scsiio_depth
; i
++, smid
++) {
5774 INIT_LIST_HEAD(&ioc
->scsi_lookup
[i
].chain_list
);
5775 ioc
->scsi_lookup
[i
].cb_idx
= 0xFF;
5776 ioc
->scsi_lookup
[i
].smid
= smid
;
5777 ioc
->scsi_lookup
[i
].scmd
= NULL
;
5778 ioc
->scsi_lookup
[i
].direct_io
= 0;
5779 list_add_tail(&ioc
->scsi_lookup
[i
].tracker_list
,
5783 /* hi-priority queue */
5784 INIT_LIST_HEAD(&ioc
->hpr_free_list
);
5785 smid
= ioc
->hi_priority_smid
;
5786 for (i
= 0; i
< ioc
->hi_priority_depth
; i
++, smid
++) {
5787 ioc
->hpr_lookup
[i
].cb_idx
= 0xFF;
5788 ioc
->hpr_lookup
[i
].smid
= smid
;
5789 list_add_tail(&ioc
->hpr_lookup
[i
].tracker_list
,
5790 &ioc
->hpr_free_list
);
5793 /* internal queue */
5794 INIT_LIST_HEAD(&ioc
->internal_free_list
);
5795 smid
= ioc
->internal_smid
;
5796 for (i
= 0; i
< ioc
->internal_depth
; i
++, smid
++) {
5797 ioc
->internal_lookup
[i
].cb_idx
= 0xFF;
5798 ioc
->internal_lookup
[i
].smid
= smid
;
5799 list_add_tail(&ioc
->internal_lookup
[i
].tracker_list
,
5800 &ioc
->internal_free_list
);
5804 INIT_LIST_HEAD(&ioc
->free_chain_list
);
5805 for (i
= 0; i
< ioc
->chain_depth
; i
++)
5806 list_add_tail(&ioc
->chain_lookup
[i
].tracker_list
,
5807 &ioc
->free_chain_list
);
5809 spin_unlock_irqrestore(&ioc
->scsi_lookup_lock
, flags
);
5811 /* initialize Reply Free Queue */
5812 for (i
= 0, reply_address
= (u32
)ioc
->reply_dma
;
5813 i
< ioc
->reply_free_queue_depth
; i
++, reply_address
+=
5815 ioc
->reply_free
[i
] = cpu_to_le32(reply_address
);
5817 /* initialize reply queues */
5818 if (ioc
->is_driver_loading
)
5819 _base_assign_reply_queues(ioc
);
5821 /* initialize Reply Post Free Queue */
5823 reply_post_free_contig
= ioc
->reply_post
[0].reply_post_free
;
5824 list_for_each_entry(reply_q
, &ioc
->reply_queue_list
, list
) {
5826 * If RDPQ is enabled, switch to the next allocation.
5827 * Otherwise advance within the contiguous region.
5829 if (ioc
->rdpq_array_enable
) {
5830 reply_q
->reply_post_free
=
5831 ioc
->reply_post
[index
++].reply_post_free
;
5833 reply_q
->reply_post_free
= reply_post_free_contig
;
5834 reply_post_free_contig
+= ioc
->reply_post_queue_depth
;
5837 reply_q
->reply_post_host_index
= 0;
5838 for (i
= 0; i
< ioc
->reply_post_queue_depth
; i
++)
5839 reply_q
->reply_post_free
[i
].Words
=
5840 cpu_to_le64(ULLONG_MAX
);
5841 if (!_base_is_controller_msix_enabled(ioc
))
5842 goto skip_init_reply_post_free_queue
;
5844 skip_init_reply_post_free_queue
:
5846 r
= _base_send_ioc_init(ioc
);
5850 /* initialize reply free host index */
5851 ioc
->reply_free_host_index
= ioc
->reply_free_queue_depth
- 1;
5852 writel(ioc
->reply_free_host_index
, &ioc
->chip
->ReplyFreeHostIndex
);
5854 /* initialize reply post host index */
5855 list_for_each_entry(reply_q
, &ioc
->reply_queue_list
, list
) {
5856 if (ioc
->combined_reply_queue
)
5857 writel((reply_q
->msix_index
& 7)<<
5858 MPI2_RPHI_MSIX_INDEX_SHIFT
,
5859 ioc
->replyPostRegisterIndex
[reply_q
->msix_index
/8]);
5861 writel(reply_q
->msix_index
<<
5862 MPI2_RPHI_MSIX_INDEX_SHIFT
,
5863 &ioc
->chip
->ReplyPostHostIndex
);
5865 if (!_base_is_controller_msix_enabled(ioc
))
5866 goto skip_init_reply_post_host_index
;
5869 skip_init_reply_post_host_index
:
5871 _base_unmask_interrupts(ioc
);
5872 r
= _base_event_notification(ioc
);
5876 _base_static_config_pages(ioc
);
5878 if (ioc
->is_driver_loading
) {
5880 if (ioc
->is_warpdrive
&& ioc
->manu_pg10
.OEMIdentifier
5883 le32_to_cpu(ioc
->manu_pg10
.OEMSpecificFlags0
) &
5884 MFG_PAGE10_HIDE_SSDS_MASK
);
5885 if (hide_flag
!= MFG_PAGE10_HIDE_SSDS_MASK
)
5886 ioc
->mfg_pg10_hide_flag
= hide_flag
;
5889 ioc
->wait_for_discovery_to_complete
=
5890 _base_determine_wait_on_discovery(ioc
);
5892 return r
; /* scan_start and scan_finished support */
5895 r
= _base_send_port_enable(ioc
);
5903 * mpt3sas_base_free_resources - free resources controller resources
5904 * @ioc: per adapter object
5909 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER
*ioc
)
5911 dexitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
5914 /* synchronizing freeing resource with pci_access_mutex lock */
5915 mutex_lock(&ioc
->pci_access_mutex
);
5916 if (ioc
->chip_phys
&& ioc
->chip
) {
5917 _base_mask_interrupts(ioc
);
5918 ioc
->shost_recovery
= 1;
5919 _base_make_ioc_ready(ioc
, SOFT_RESET
);
5920 ioc
->shost_recovery
= 0;
5923 mpt3sas_base_unmap_resources(ioc
);
5924 mutex_unlock(&ioc
->pci_access_mutex
);
5929 * mpt3sas_base_attach - attach controller instance
5930 * @ioc: per adapter object
5932 * Returns 0 for success, non-zero for failure.
5935 mpt3sas_base_attach(struct MPT3SAS_ADAPTER
*ioc
)
5938 int cpu_id
, last_cpu_id
= 0;
5940 dinitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
5943 /* setup cpu_msix_table */
5944 ioc
->cpu_count
= num_online_cpus();
5945 for_each_online_cpu(cpu_id
)
5946 last_cpu_id
= cpu_id
;
5947 ioc
->cpu_msix_table_sz
= last_cpu_id
+ 1;
5948 ioc
->cpu_msix_table
= kzalloc(ioc
->cpu_msix_table_sz
, GFP_KERNEL
);
5949 ioc
->reply_queue_count
= 1;
5950 if (!ioc
->cpu_msix_table
) {
5951 dfailprintk(ioc
, pr_info(MPT3SAS_FMT
5952 "allocation for cpu_msix_table failed!!!\n",
5955 goto out_free_resources
;
5958 if (ioc
->is_warpdrive
) {
5959 ioc
->reply_post_host_index
= kcalloc(ioc
->cpu_msix_table_sz
,
5960 sizeof(resource_size_t
*), GFP_KERNEL
);
5961 if (!ioc
->reply_post_host_index
) {
5962 dfailprintk(ioc
, pr_info(MPT3SAS_FMT
"allocation "
5963 "for reply_post_host_index failed!!!\n",
5966 goto out_free_resources
;
5970 ioc
->rdpq_array_enable_assigned
= 0;
5972 r
= mpt3sas_base_map_resources(ioc
);
5974 goto out_free_resources
;
5976 pci_set_drvdata(ioc
->pdev
, ioc
->shost
);
5977 r
= _base_get_ioc_facts(ioc
);
5979 goto out_free_resources
;
5981 switch (ioc
->hba_mpi_version_belonged
) {
5983 ioc
->build_sg_scmd
= &_base_build_sg_scmd
;
5984 ioc
->build_sg
= &_base_build_sg
;
5985 ioc
->build_zero_len_sge
= &_base_build_zero_len_sge
;
5991 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
5992 * Target Status - all require the IEEE formated scatter gather
5995 ioc
->build_sg_scmd
= &_base_build_sg_scmd_ieee
;
5996 ioc
->build_sg
= &_base_build_sg_ieee
;
5997 ioc
->build_nvme_prp
= &_base_build_nvme_prp
;
5998 ioc
->build_zero_len_sge
= &_base_build_zero_len_sge_ieee
;
5999 ioc
->sge_size_ieee
= sizeof(Mpi2IeeeSgeSimple64_t
);
6004 if (ioc
->atomic_desc_capable
) {
6005 ioc
->put_smid_default
= &_base_put_smid_default_atomic
;
6006 ioc
->put_smid_scsi_io
= &_base_put_smid_scsi_io_atomic
;
6007 ioc
->put_smid_fast_path
= &_base_put_smid_fast_path_atomic
;
6008 ioc
->put_smid_hi_priority
= &_base_put_smid_hi_priority_atomic
;
6009 ioc
->put_smid_nvme_encap
= &_base_put_smid_nvme_encap_atomic
;
6011 ioc
->put_smid_default
= &_base_put_smid_default
;
6012 ioc
->put_smid_scsi_io
= &_base_put_smid_scsi_io
;
6013 ioc
->put_smid_fast_path
= &_base_put_smid_fast_path
;
6014 ioc
->put_smid_hi_priority
= &_base_put_smid_hi_priority
;
6015 ioc
->put_smid_nvme_encap
= &_base_put_smid_nvme_encap
;
6020 * These function pointers for other requests that don't
6021 * the require IEEE scatter gather elements.
6023 * For example Configuration Pages and SAS IOUNIT Control don't.
6025 ioc
->build_sg_mpi
= &_base_build_sg
;
6026 ioc
->build_zero_len_sge_mpi
= &_base_build_zero_len_sge
;
6028 r
= _base_make_ioc_ready(ioc
, SOFT_RESET
);
6030 goto out_free_resources
;
6032 ioc
->pfacts
= kcalloc(ioc
->facts
.NumberOfPorts
,
6033 sizeof(struct mpt3sas_port_facts
), GFP_KERNEL
);
6036 goto out_free_resources
;
6039 for (i
= 0 ; i
< ioc
->facts
.NumberOfPorts
; i
++) {
6040 r
= _base_get_port_facts(ioc
, i
);
6042 goto out_free_resources
;
6045 r
= _base_allocate_memory_pools(ioc
);
6047 goto out_free_resources
;
6049 init_waitqueue_head(&ioc
->reset_wq
);
6051 /* allocate memory pd handle bitmask list */
6052 ioc
->pd_handles_sz
= (ioc
->facts
.MaxDevHandle
/ 8);
6053 if (ioc
->facts
.MaxDevHandle
% 8)
6054 ioc
->pd_handles_sz
++;
6055 ioc
->pd_handles
= kzalloc(ioc
->pd_handles_sz
,
6057 if (!ioc
->pd_handles
) {
6059 goto out_free_resources
;
6061 ioc
->blocking_handles
= kzalloc(ioc
->pd_handles_sz
,
6063 if (!ioc
->blocking_handles
) {
6065 goto out_free_resources
;
6068 /* allocate memory for pending OS device add list */
6069 ioc
->pend_os_device_add_sz
= (ioc
->facts
.MaxDevHandle
/ 8);
6070 if (ioc
->facts
.MaxDevHandle
% 8)
6071 ioc
->pend_os_device_add_sz
++;
6072 ioc
->pend_os_device_add
= kzalloc(ioc
->pend_os_device_add_sz
,
6074 if (!ioc
->pend_os_device_add
)
6075 goto out_free_resources
;
6077 ioc
->device_remove_in_progress_sz
= ioc
->pend_os_device_add_sz
;
6078 ioc
->device_remove_in_progress
=
6079 kzalloc(ioc
->device_remove_in_progress_sz
, GFP_KERNEL
);
6080 if (!ioc
->device_remove_in_progress
)
6081 goto out_free_resources
;
6083 ioc
->fwfault_debug
= mpt3sas_fwfault_debug
;
6085 /* base internal command bits */
6086 mutex_init(&ioc
->base_cmds
.mutex
);
6087 ioc
->base_cmds
.reply
= kzalloc(ioc
->reply_sz
, GFP_KERNEL
);
6088 ioc
->base_cmds
.status
= MPT3_CMD_NOT_USED
;
6090 /* port_enable command bits */
6091 ioc
->port_enable_cmds
.reply
= kzalloc(ioc
->reply_sz
, GFP_KERNEL
);
6092 ioc
->port_enable_cmds
.status
= MPT3_CMD_NOT_USED
;
6094 /* transport internal command bits */
6095 ioc
->transport_cmds
.reply
= kzalloc(ioc
->reply_sz
, GFP_KERNEL
);
6096 ioc
->transport_cmds
.status
= MPT3_CMD_NOT_USED
;
6097 mutex_init(&ioc
->transport_cmds
.mutex
);
6099 /* scsih internal command bits */
6100 ioc
->scsih_cmds
.reply
= kzalloc(ioc
->reply_sz
, GFP_KERNEL
);
6101 ioc
->scsih_cmds
.status
= MPT3_CMD_NOT_USED
;
6102 mutex_init(&ioc
->scsih_cmds
.mutex
);
6104 /* task management internal command bits */
6105 ioc
->tm_cmds
.reply
= kzalloc(ioc
->reply_sz
, GFP_KERNEL
);
6106 ioc
->tm_cmds
.status
= MPT3_CMD_NOT_USED
;
6107 mutex_init(&ioc
->tm_cmds
.mutex
);
6109 /* config page internal command bits */
6110 ioc
->config_cmds
.reply
= kzalloc(ioc
->reply_sz
, GFP_KERNEL
);
6111 ioc
->config_cmds
.status
= MPT3_CMD_NOT_USED
;
6112 mutex_init(&ioc
->config_cmds
.mutex
);
6114 /* ctl module internal command bits */
6115 ioc
->ctl_cmds
.reply
= kzalloc(ioc
->reply_sz
, GFP_KERNEL
);
6116 ioc
->ctl_cmds
.sense
= kzalloc(SCSI_SENSE_BUFFERSIZE
, GFP_KERNEL
);
6117 ioc
->ctl_cmds
.status
= MPT3_CMD_NOT_USED
;
6118 mutex_init(&ioc
->ctl_cmds
.mutex
);
6120 if (!ioc
->base_cmds
.reply
|| !ioc
->port_enable_cmds
.reply
||
6121 !ioc
->transport_cmds
.reply
|| !ioc
->scsih_cmds
.reply
||
6122 !ioc
->tm_cmds
.reply
|| !ioc
->config_cmds
.reply
||
6123 !ioc
->ctl_cmds
.reply
|| !ioc
->ctl_cmds
.sense
) {
6125 goto out_free_resources
;
6128 for (i
= 0; i
< MPI2_EVENT_NOTIFY_EVENTMASK_WORDS
; i
++)
6129 ioc
->event_masks
[i
] = -1;
6131 /* here we enable the events we care about */
6132 _base_unmask_events(ioc
, MPI2_EVENT_SAS_DISCOVERY
);
6133 _base_unmask_events(ioc
, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE
);
6134 _base_unmask_events(ioc
, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST
);
6135 _base_unmask_events(ioc
, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE
);
6136 _base_unmask_events(ioc
, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE
);
6137 _base_unmask_events(ioc
, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST
);
6138 _base_unmask_events(ioc
, MPI2_EVENT_IR_VOLUME
);
6139 _base_unmask_events(ioc
, MPI2_EVENT_IR_PHYSICAL_DISK
);
6140 _base_unmask_events(ioc
, MPI2_EVENT_IR_OPERATION_STATUS
);
6141 _base_unmask_events(ioc
, MPI2_EVENT_LOG_ENTRY_ADDED
);
6142 _base_unmask_events(ioc
, MPI2_EVENT_TEMP_THRESHOLD
);
6143 _base_unmask_events(ioc
, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION
);
6144 if (ioc
->hba_mpi_version_belonged
== MPI26_VERSION
) {
6145 if (ioc
->is_gen35_ioc
) {
6146 _base_unmask_events(ioc
,
6147 MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE
);
6148 _base_unmask_events(ioc
, MPI2_EVENT_PCIE_ENUMERATION
);
6149 _base_unmask_events(ioc
,
6150 MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST
);
6153 r
= _base_make_ioc_operational(ioc
);
6155 goto out_free_resources
;
6157 ioc
->non_operational_loop
= 0;
6158 ioc
->got_task_abort_from_ioctl
= 0;
6163 ioc
->remove_host
= 1;
6165 mpt3sas_base_free_resources(ioc
);
6166 _base_release_memory_pools(ioc
);
6167 pci_set_drvdata(ioc
->pdev
, NULL
);
6168 kfree(ioc
->cpu_msix_table
);
6169 if (ioc
->is_warpdrive
)
6170 kfree(ioc
->reply_post_host_index
);
6171 kfree(ioc
->pd_handles
);
6172 kfree(ioc
->blocking_handles
);
6173 kfree(ioc
->device_remove_in_progress
);
6174 kfree(ioc
->pend_os_device_add
);
6175 kfree(ioc
->tm_cmds
.reply
);
6176 kfree(ioc
->transport_cmds
.reply
);
6177 kfree(ioc
->scsih_cmds
.reply
);
6178 kfree(ioc
->config_cmds
.reply
);
6179 kfree(ioc
->base_cmds
.reply
);
6180 kfree(ioc
->port_enable_cmds
.reply
);
6181 kfree(ioc
->ctl_cmds
.reply
);
6182 kfree(ioc
->ctl_cmds
.sense
);
6184 ioc
->ctl_cmds
.reply
= NULL
;
6185 ioc
->base_cmds
.reply
= NULL
;
6186 ioc
->tm_cmds
.reply
= NULL
;
6187 ioc
->scsih_cmds
.reply
= NULL
;
6188 ioc
->transport_cmds
.reply
= NULL
;
6189 ioc
->config_cmds
.reply
= NULL
;
6196 * mpt3sas_base_detach - remove controller instance
6197 * @ioc: per adapter object
6202 mpt3sas_base_detach(struct MPT3SAS_ADAPTER
*ioc
)
6204 dexitprintk(ioc
, pr_info(MPT3SAS_FMT
"%s\n", ioc
->name
,
6207 mpt3sas_base_stop_watchdog(ioc
);
6208 mpt3sas_base_free_resources(ioc
);
6209 _base_release_memory_pools(ioc
);
6210 pci_set_drvdata(ioc
->pdev
, NULL
);
6211 kfree(ioc
->cpu_msix_table
);
6212 if (ioc
->is_warpdrive
)
6213 kfree(ioc
->reply_post_host_index
);
6214 kfree(ioc
->pd_handles
);
6215 kfree(ioc
->blocking_handles
);
6216 kfree(ioc
->device_remove_in_progress
);
6217 kfree(ioc
->pend_os_device_add
);
6219 kfree(ioc
->ctl_cmds
.reply
);
6220 kfree(ioc
->ctl_cmds
.sense
);
6221 kfree(ioc
->base_cmds
.reply
);
6222 kfree(ioc
->port_enable_cmds
.reply
);
6223 kfree(ioc
->tm_cmds
.reply
);
6224 kfree(ioc
->transport_cmds
.reply
);
6225 kfree(ioc
->scsih_cmds
.reply
);
6226 kfree(ioc
->config_cmds
.reply
);
6230 * _base_reset_handler - reset callback handler (for base)
6231 * @ioc: per adapter object
6232 * @reset_phase: phase
6234 * The handler for doing any required cleanup or initialization.
6236 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
6237 * MPT3_IOC_DONE_RESET
6242 _base_reset_handler(struct MPT3SAS_ADAPTER
*ioc
, int reset_phase
)
6244 mpt3sas_scsih_reset_handler(ioc
, reset_phase
);
6245 mpt3sas_ctl_reset_handler(ioc
, reset_phase
);
6246 switch (reset_phase
) {
6247 case MPT3_IOC_PRE_RESET
:
6248 dtmprintk(ioc
, pr_info(MPT3SAS_FMT
6249 "%s: MPT3_IOC_PRE_RESET\n", ioc
->name
, __func__
));
6251 case MPT3_IOC_AFTER_RESET
:
6252 dtmprintk(ioc
, pr_info(MPT3SAS_FMT
6253 "%s: MPT3_IOC_AFTER_RESET\n", ioc
->name
, __func__
));
6254 if (ioc
->transport_cmds
.status
& MPT3_CMD_PENDING
) {
6255 ioc
->transport_cmds
.status
|= MPT3_CMD_RESET
;
6256 mpt3sas_base_free_smid(ioc
, ioc
->transport_cmds
.smid
);
6257 complete(&ioc
->transport_cmds
.done
);
6259 if (ioc
->base_cmds
.status
& MPT3_CMD_PENDING
) {
6260 ioc
->base_cmds
.status
|= MPT3_CMD_RESET
;
6261 mpt3sas_base_free_smid(ioc
, ioc
->base_cmds
.smid
);
6262 complete(&ioc
->base_cmds
.done
);
6264 if (ioc
->port_enable_cmds
.status
& MPT3_CMD_PENDING
) {
6265 ioc
->port_enable_failed
= 1;
6266 ioc
->port_enable_cmds
.status
|= MPT3_CMD_RESET
;
6267 mpt3sas_base_free_smid(ioc
, ioc
->port_enable_cmds
.smid
);
6268 if (ioc
->is_driver_loading
) {
6269 ioc
->start_scan_failed
=
6270 MPI2_IOCSTATUS_INTERNAL_ERROR
;
6271 ioc
->start_scan
= 0;
6272 ioc
->port_enable_cmds
.status
=
6275 complete(&ioc
->port_enable_cmds
.done
);
6277 if (ioc
->config_cmds
.status
& MPT3_CMD_PENDING
) {
6278 ioc
->config_cmds
.status
|= MPT3_CMD_RESET
;
6279 mpt3sas_base_free_smid(ioc
, ioc
->config_cmds
.smid
);
6280 ioc
->config_cmds
.smid
= USHRT_MAX
;
6281 complete(&ioc
->config_cmds
.done
);
6284 case MPT3_IOC_DONE_RESET
:
6285 dtmprintk(ioc
, pr_info(MPT3SAS_FMT
6286 "%s: MPT3_IOC_DONE_RESET\n", ioc
->name
, __func__
));
6292 * _wait_for_commands_to_complete - reset controller
6293 * @ioc: Pointer to MPT_ADAPTER structure
6295 * This function waiting(3s) for all pending commands to complete
6296 * prior to putting controller in reset.
6299 _wait_for_commands_to_complete(struct MPT3SAS_ADAPTER
*ioc
)
6302 unsigned long flags
;
6305 ioc
->pending_io_count
= 0;
6307 ioc_state
= mpt3sas_base_get_iocstate(ioc
, 0);
6308 if ((ioc_state
& MPI2_IOC_STATE_MASK
) != MPI2_IOC_STATE_OPERATIONAL
)
6311 /* pending command count */
6312 spin_lock_irqsave(&ioc
->scsi_lookup_lock
, flags
);
6313 for (i
= 0; i
< ioc
->scsiio_depth
; i
++)
6314 if (ioc
->scsi_lookup
[i
].cb_idx
!= 0xFF)
6315 ioc
->pending_io_count
++;
6316 spin_unlock_irqrestore(&ioc
->scsi_lookup_lock
, flags
);
6318 if (!ioc
->pending_io_count
)
6321 /* wait for pending commands to complete */
6322 wait_event_timeout(ioc
->reset_wq
, ioc
->pending_io_count
== 0, 10 * HZ
);
6326 * mpt3sas_base_hard_reset_handler - reset controller
6327 * @ioc: Pointer to MPT_ADAPTER structure
6328 * @type: FORCE_BIG_HAMMER or SOFT_RESET
6330 * Returns 0 for success, non-zero for failure.
6333 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER
*ioc
,
6334 enum reset_type type
)
6337 unsigned long flags
;
6339 u8 is_fault
= 0, is_trigger
= 0;
6341 dtmprintk(ioc
, pr_info(MPT3SAS_FMT
"%s: enter\n", ioc
->name
,
6344 if (ioc
->pci_error_recovery
) {
6345 pr_err(MPT3SAS_FMT
"%s: pci error recovery reset\n",
6346 ioc
->name
, __func__
);
6351 if (mpt3sas_fwfault_debug
)
6352 mpt3sas_halt_firmware(ioc
);
6354 /* wait for an active reset in progress to complete */
6355 if (!mutex_trylock(&ioc
->reset_in_progress_mutex
)) {
6358 } while (ioc
->shost_recovery
== 1);
6359 dtmprintk(ioc
, pr_info(MPT3SAS_FMT
"%s: exit\n", ioc
->name
,
6361 return ioc
->ioc_reset_in_progress_status
;
6364 spin_lock_irqsave(&ioc
->ioc_reset_in_progress_lock
, flags
);
6365 ioc
->shost_recovery
= 1;
6366 spin_unlock_irqrestore(&ioc
->ioc_reset_in_progress_lock
, flags
);
6368 if ((ioc
->diag_buffer_status
[MPI2_DIAG_BUF_TYPE_TRACE
] &
6369 MPT3_DIAG_BUFFER_IS_REGISTERED
) &&
6370 (!(ioc
->diag_buffer_status
[MPI2_DIAG_BUF_TYPE_TRACE
] &
6371 MPT3_DIAG_BUFFER_IS_RELEASED
))) {
6373 ioc_state
= mpt3sas_base_get_iocstate(ioc
, 0);
6374 if ((ioc_state
& MPI2_IOC_STATE_MASK
) == MPI2_IOC_STATE_FAULT
)
6377 _base_reset_handler(ioc
, MPT3_IOC_PRE_RESET
);
6378 _wait_for_commands_to_complete(ioc
);
6379 _base_mask_interrupts(ioc
);
6380 r
= _base_make_ioc_ready(ioc
, type
);
6383 _base_reset_handler(ioc
, MPT3_IOC_AFTER_RESET
);
6385 /* If this hard reset is called while port enable is active, then
6386 * there is no reason to call make_ioc_operational
6388 if (ioc
->is_driver_loading
&& ioc
->port_enable_failed
) {
6389 ioc
->remove_host
= 1;
6393 r
= _base_get_ioc_facts(ioc
);
6397 if (ioc
->rdpq_array_enable
&& !ioc
->rdpq_array_capable
)
6398 panic("%s: Issue occurred with flashing controller firmware."
6399 "Please reboot the system and ensure that the correct"
6400 " firmware version is running\n", ioc
->name
);
6402 r
= _base_make_ioc_operational(ioc
);
6404 _base_reset_handler(ioc
, MPT3_IOC_DONE_RESET
);
6407 dtmprintk(ioc
, pr_info(MPT3SAS_FMT
"%s: %s\n",
6408 ioc
->name
, __func__
, ((r
== 0) ? "SUCCESS" : "FAILED")));
6410 spin_lock_irqsave(&ioc
->ioc_reset_in_progress_lock
, flags
);
6411 ioc
->ioc_reset_in_progress_status
= r
;
6412 ioc
->shost_recovery
= 0;
6413 spin_unlock_irqrestore(&ioc
->ioc_reset_in_progress_lock
, flags
);
6414 ioc
->ioc_reset_count
++;
6415 mutex_unlock(&ioc
->reset_in_progress_mutex
);
6418 if ((r
== 0) && is_trigger
) {
6420 mpt3sas_trigger_master(ioc
, MASTER_TRIGGER_FW_FAULT
);
6422 mpt3sas_trigger_master(ioc
,
6423 MASTER_TRIGGER_ADAPTER_RESET
);
6425 dtmprintk(ioc
, pr_info(MPT3SAS_FMT
"%s: exit\n", ioc
->name
,