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[SCSI] qla2xxx: Add support for ISP2071.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_dbg.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7
8 /*
9 * Table for showing the current message id in use for particular level
10 * Change this table for addition of log/debug messages.
11 * ----------------------------------------------------------------------
12 * | Level | Last Value Used | Holes |
13 * ----------------------------------------------------------------------
14 * | Module Init and Probe | 0x017d | 0x004b,0x0141 |
15 * | | | 0x0144,0x0146 |
16 * | | | 0x015b-0x0160 |
17 * | | | 0x016e-0x0170 |
18 * | Mailbox commands | 0x1187 | 0x1018-0x1019 |
19 * | | | 0x10ca |
20 * | | | 0x1115-0x1116 |
21 * | | | 0x111a-0x111b |
22 * | | | 0x1155-0x1158 |
23 * | Device Discovery | 0x2095 | 0x2020-0x2022, |
24 * | | | 0x2011-0x2012, |
25 * | | | 0x2016 |
26 * | Queue Command and IO tracing | 0x3059 | 0x3006-0x300b |
27 * | | | 0x3027-0x3028 |
28 * | | | 0x303d-0x3041 |
29 * | | | 0x302d,0x3033 |
30 * | | | 0x3036,0x3038 |
31 * | | | 0x303a |
32 * | DPC Thread | 0x4023 | 0x4002,0x4013 |
33 * | Async Events | 0x5087 | 0x502b-0x502f |
34 * | | | 0x5047,0x5052 |
35 * | | | 0x5084,0x5075 |
36 * | | | 0x503d,0x5044 |
37 * | Timer Routines | 0x6012 | |
38 * | User Space Interactions | 0x70e2 | 0x7018,0x702e |
39 * | | | 0x7020,0x7024 |
40 * | | | 0x7039,0x7045 |
41 * | | | 0x7073-0x7075 |
42 * | | | 0x70a5-0x70a6 |
43 * | | | 0x70a8,0x70ab |
44 * | | | 0x70ad-0x70ae |
45 * | | | 0x70d7-0x70db |
46 * | | | 0x70de-0x70df |
47 * | Task Management | 0x803d | 0x8025-0x8026 |
48 * | | | 0x800b,0x8039 |
49 * | AER/EEH | 0x9011 | |
50 * | Virtual Port | 0xa007 | |
51 * | ISP82XX Specific | 0xb14c | 0xb002,0xb024 |
52 * | | | 0xb09e,0xb0ae |
53 * | | | 0xb0e0-0xb0ef |
54 * | | | 0xb085,0xb0dc |
55 * | | | 0xb107,0xb108 |
56 * | | | 0xb111,0xb11e |
57 * | | | 0xb12c,0xb12d |
58 * | | | 0xb13a,0xb142 |
59 * | | | 0xb13c-0xb140 |
60 * | | | 0xb149 |
61 * | MultiQ | 0xc00c | |
62 * | Misc | 0xd2ff | 0xd017-0xd019 |
63 * | | | 0xd020 |
64 * | | | 0xd02e-0xd0ff |
65 * | | | 0xd101-0xd1fe |
66 * | | | 0xd212-0xd2fe |
67 * | Target Mode | 0xe070 | 0xe021 |
68 * | Target Mode Management | 0xf072 | 0xf002-0xf003 |
69 * | | | 0xf046-0xf049 |
70 * | Target Mode Task Management | 0x1000b | |
71 * ----------------------------------------------------------------------
72 */
73
74 #include "qla_def.h"
75
76 #include <linux/delay.h>
77
78 static uint32_t ql_dbg_offset = 0x800;
79
80 static inline void
81 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
82 {
83 fw_dump->fw_major_version = htonl(ha->fw_major_version);
84 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
85 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
86 fw_dump->fw_attributes = htonl(ha->fw_attributes);
87
88 fw_dump->vendor = htonl(ha->pdev->vendor);
89 fw_dump->device = htonl(ha->pdev->device);
90 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
91 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
92 }
93
94 static inline void *
95 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
96 {
97 struct req_que *req = ha->req_q_map[0];
98 struct rsp_que *rsp = ha->rsp_q_map[0];
99 /* Request queue. */
100 memcpy(ptr, req->ring, req->length *
101 sizeof(request_t));
102
103 /* Response queue. */
104 ptr += req->length * sizeof(request_t);
105 memcpy(ptr, rsp->ring, rsp->length *
106 sizeof(response_t));
107
108 return ptr + (rsp->length * sizeof(response_t));
109 }
110
111 int
112 qla27xx_dump_mpi_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
113 uint32_t ram_dwords, void **nxt)
114 {
115 int rval;
116 uint32_t cnt, stat, timer, dwords, idx;
117 uint16_t mb0, mb1;
118 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
119 dma_addr_t dump_dma = ha->gid_list_dma;
120 uint32_t *dump = (uint32_t *)ha->gid_list;
121
122 rval = QLA_SUCCESS;
123 mb0 = 0;
124
125 WRT_REG_WORD(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
126 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
127
128 dwords = qla2x00_gid_list_size(ha) / 4;
129 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
130 cnt += dwords, addr += dwords) {
131 if (cnt + dwords > ram_dwords)
132 dwords = ram_dwords - cnt;
133
134 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
135 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
136
137 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
138 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
139 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
140 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
141
142 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
143 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
144
145 WRT_REG_WORD(&reg->mailbox9, 0);
146 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
147
148 ha->flags.mbox_int = 0;
149 for (timer = 6000000; timer; timer--) {
150 /* Check for pending interrupts. */
151 stat = RD_REG_DWORD(&reg->host_status);
152 if (stat & HSRX_RISC_INT) {
153 stat &= 0xff;
154
155 if (stat == 0x1 || stat == 0x2 ||
156 stat == 0x10 || stat == 0x11) {
157 set_bit(MBX_INTERRUPT,
158 &ha->mbx_cmd_flags);
159
160 mb0 = RD_REG_WORD(&reg->mailbox0);
161 mb1 = RD_REG_WORD(&reg->mailbox1);
162
163 WRT_REG_DWORD(&reg->hccr,
164 HCCRX_CLR_RISC_INT);
165 RD_REG_DWORD(&reg->hccr);
166 break;
167 }
168
169 /* Clear this intr; it wasn't a mailbox intr */
170 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
171 RD_REG_DWORD(&reg->hccr);
172 }
173 udelay(5);
174 }
175 ha->flags.mbox_int = 1;
176
177 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
178 rval = mb0 & MBS_MASK;
179 for (idx = 0; idx < dwords; idx++)
180 ram[cnt + idx] = IS_QLA27XX(ha) ?
181 le32_to_cpu(dump[idx]) : swab32(dump[idx]);
182 } else {
183 rval = QLA_FUNCTION_FAILED;
184 }
185 }
186
187 *nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL;
188 return rval;
189 }
190
191 int
192 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
193 uint32_t ram_dwords, void **nxt)
194 {
195 int rval;
196 uint32_t cnt, stat, timer, dwords, idx;
197 uint16_t mb0;
198 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
199 dma_addr_t dump_dma = ha->gid_list_dma;
200 uint32_t *dump = (uint32_t *)ha->gid_list;
201
202 rval = QLA_SUCCESS;
203 mb0 = 0;
204
205 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
206 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
207
208 dwords = qla2x00_gid_list_size(ha) / 4;
209 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
210 cnt += dwords, addr += dwords) {
211 if (cnt + dwords > ram_dwords)
212 dwords = ram_dwords - cnt;
213
214 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
215 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
216
217 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
218 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
219 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
220 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
221
222 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
223 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
224 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
225
226 ha->flags.mbox_int = 0;
227 for (timer = 6000000; timer; timer--) {
228 /* Check for pending interrupts. */
229 stat = RD_REG_DWORD(&reg->host_status);
230 if (stat & HSRX_RISC_INT) {
231 stat &= 0xff;
232
233 if (stat == 0x1 || stat == 0x2 ||
234 stat == 0x10 || stat == 0x11) {
235 set_bit(MBX_INTERRUPT,
236 &ha->mbx_cmd_flags);
237
238 mb0 = RD_REG_WORD(&reg->mailbox0);
239
240 WRT_REG_DWORD(&reg->hccr,
241 HCCRX_CLR_RISC_INT);
242 RD_REG_DWORD(&reg->hccr);
243 break;
244 }
245
246 /* Clear this intr; it wasn't a mailbox intr */
247 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
248 RD_REG_DWORD(&reg->hccr);
249 }
250 udelay(5);
251 }
252 ha->flags.mbox_int = 1;
253
254 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
255 rval = mb0 & MBS_MASK;
256 for (idx = 0; idx < dwords; idx++)
257 ram[cnt + idx] = IS_QLA27XX(ha) ?
258 le32_to_cpu(dump[idx]) : swab32(dump[idx]);
259 } else {
260 rval = QLA_FUNCTION_FAILED;
261 }
262 }
263
264 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
265 return rval;
266 }
267
268 static int
269 qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
270 uint32_t cram_size, void **nxt)
271 {
272 int rval;
273
274 /* Code RAM. */
275 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
276 if (rval != QLA_SUCCESS)
277 return rval;
278
279 /* External Memory. */
280 return qla24xx_dump_ram(ha, 0x100000, *nxt,
281 ha->fw_memory_size - 0x100000 + 1, nxt);
282 }
283
284 static uint32_t *
285 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
286 uint32_t count, uint32_t *buf)
287 {
288 uint32_t __iomem *dmp_reg;
289
290 WRT_REG_DWORD(&reg->iobase_addr, iobase);
291 dmp_reg = &reg->iobase_window;
292 while (count--)
293 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
294
295 return buf;
296 }
297
298 int
299 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
300 {
301 int rval = QLA_SUCCESS;
302 uint32_t cnt;
303
304 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
305 for (cnt = 30000;
306 ((RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) == 0) &&
307 rval == QLA_SUCCESS; cnt--) {
308 if (cnt)
309 udelay(100);
310 else
311 rval = QLA_FUNCTION_TIMEOUT;
312 }
313
314 return rval;
315 }
316
317 int
318 qla24xx_soft_reset(struct qla_hw_data *ha)
319 {
320 int rval = QLA_SUCCESS;
321 uint32_t cnt;
322 uint16_t mb0, wd;
323 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
324
325 /* Reset RISC. */
326 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
327 for (cnt = 0; cnt < 30000; cnt++) {
328 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
329 break;
330
331 udelay(10);
332 }
333
334 WRT_REG_DWORD(&reg->ctrl_status,
335 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
336 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
337
338 udelay(100);
339 /* Wait for firmware to complete NVRAM accesses. */
340 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
341 for (cnt = 10000 ; cnt && mb0; cnt--) {
342 udelay(5);
343 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
344 barrier();
345 }
346
347 /* Wait for soft-reset to complete. */
348 for (cnt = 0; cnt < 30000; cnt++) {
349 if ((RD_REG_DWORD(&reg->ctrl_status) &
350 CSRX_ISP_SOFT_RESET) == 0)
351 break;
352
353 udelay(10);
354 }
355 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
356 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
357
358 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
359 rval == QLA_SUCCESS; cnt--) {
360 if (cnt)
361 udelay(100);
362 else
363 rval = QLA_FUNCTION_TIMEOUT;
364 }
365
366 return rval;
367 }
368
369 static int
370 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
371 uint32_t ram_words, void **nxt)
372 {
373 int rval;
374 uint32_t cnt, stat, timer, words, idx;
375 uint16_t mb0;
376 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
377 dma_addr_t dump_dma = ha->gid_list_dma;
378 uint16_t *dump = (uint16_t *)ha->gid_list;
379
380 rval = QLA_SUCCESS;
381 mb0 = 0;
382
383 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
384 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
385
386 words = qla2x00_gid_list_size(ha) / 2;
387 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
388 cnt += words, addr += words) {
389 if (cnt + words > ram_words)
390 words = ram_words - cnt;
391
392 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
393 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
394
395 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
396 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
397 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
398 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
399
400 WRT_MAILBOX_REG(ha, reg, 4, words);
401 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
402
403 for (timer = 6000000; timer; timer--) {
404 /* Check for pending interrupts. */
405 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
406 if (stat & HSR_RISC_INT) {
407 stat &= 0xff;
408
409 if (stat == 0x1 || stat == 0x2) {
410 set_bit(MBX_INTERRUPT,
411 &ha->mbx_cmd_flags);
412
413 mb0 = RD_MAILBOX_REG(ha, reg, 0);
414
415 /* Release mailbox registers. */
416 WRT_REG_WORD(&reg->semaphore, 0);
417 WRT_REG_WORD(&reg->hccr,
418 HCCR_CLR_RISC_INT);
419 RD_REG_WORD(&reg->hccr);
420 break;
421 } else if (stat == 0x10 || stat == 0x11) {
422 set_bit(MBX_INTERRUPT,
423 &ha->mbx_cmd_flags);
424
425 mb0 = RD_MAILBOX_REG(ha, reg, 0);
426
427 WRT_REG_WORD(&reg->hccr,
428 HCCR_CLR_RISC_INT);
429 RD_REG_WORD(&reg->hccr);
430 break;
431 }
432
433 /* clear this intr; it wasn't a mailbox intr */
434 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
435 RD_REG_WORD(&reg->hccr);
436 }
437 udelay(5);
438 }
439
440 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
441 rval = mb0 & MBS_MASK;
442 for (idx = 0; idx < words; idx++)
443 ram[cnt + idx] = swab16(dump[idx]);
444 } else {
445 rval = QLA_FUNCTION_FAILED;
446 }
447 }
448
449 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
450 return rval;
451 }
452
453 static inline void
454 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
455 uint16_t *buf)
456 {
457 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
458
459 while (count--)
460 *buf++ = htons(RD_REG_WORD(dmp_reg++));
461 }
462
463 static inline void *
464 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
465 {
466 if (!ha->eft)
467 return ptr;
468
469 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
470 return ptr + ntohl(ha->fw_dump->eft_size);
471 }
472
473 static inline void *
474 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
475 {
476 uint32_t cnt;
477 uint32_t *iter_reg;
478 struct qla2xxx_fce_chain *fcec = ptr;
479
480 if (!ha->fce)
481 return ptr;
482
483 *last_chain = &fcec->type;
484 fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
485 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
486 fce_calc_size(ha->fce_bufs));
487 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
488 fcec->addr_l = htonl(LSD(ha->fce_dma));
489 fcec->addr_h = htonl(MSD(ha->fce_dma));
490
491 iter_reg = fcec->eregs;
492 for (cnt = 0; cnt < 8; cnt++)
493 *iter_reg++ = htonl(ha->fce_mb[cnt]);
494
495 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
496
497 return (char *)iter_reg + ntohl(fcec->size);
498 }
499
500 static inline void *
501 qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr,
502 uint32_t **last_chain)
503 {
504 struct qla2xxx_mqueue_chain *q;
505 struct qla2xxx_mqueue_header *qh;
506 uint32_t num_queues;
507 int que;
508 struct {
509 int length;
510 void *ring;
511 } aq, *aqp;
512
513 if (!ha->tgt.atio_ring)
514 return ptr;
515
516 num_queues = 1;
517 aqp = &aq;
518 aqp->length = ha->tgt.atio_q_length;
519 aqp->ring = ha->tgt.atio_ring;
520
521 for (que = 0; que < num_queues; que++) {
522 /* aqp = ha->atio_q_map[que]; */
523 q = ptr;
524 *last_chain = &q->type;
525 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
526 q->chain_size = htonl(
527 sizeof(struct qla2xxx_mqueue_chain) +
528 sizeof(struct qla2xxx_mqueue_header) +
529 (aqp->length * sizeof(request_t)));
530 ptr += sizeof(struct qla2xxx_mqueue_chain);
531
532 /* Add header. */
533 qh = ptr;
534 qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
535 qh->number = htonl(que);
536 qh->size = htonl(aqp->length * sizeof(request_t));
537 ptr += sizeof(struct qla2xxx_mqueue_header);
538
539 /* Add data. */
540 memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
541
542 ptr += aqp->length * sizeof(request_t);
543 }
544
545 return ptr;
546 }
547
548 static inline void *
549 qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
550 {
551 struct qla2xxx_mqueue_chain *q;
552 struct qla2xxx_mqueue_header *qh;
553 struct req_que *req;
554 struct rsp_que *rsp;
555 int que;
556
557 if (!ha->mqenable)
558 return ptr;
559
560 /* Request queues */
561 for (que = 1; que < ha->max_req_queues; que++) {
562 req = ha->req_q_map[que];
563 if (!req)
564 break;
565
566 /* Add chain. */
567 q = ptr;
568 *last_chain = &q->type;
569 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
570 q->chain_size = htonl(
571 sizeof(struct qla2xxx_mqueue_chain) +
572 sizeof(struct qla2xxx_mqueue_header) +
573 (req->length * sizeof(request_t)));
574 ptr += sizeof(struct qla2xxx_mqueue_chain);
575
576 /* Add header. */
577 qh = ptr;
578 qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
579 qh->number = htonl(que);
580 qh->size = htonl(req->length * sizeof(request_t));
581 ptr += sizeof(struct qla2xxx_mqueue_header);
582
583 /* Add data. */
584 memcpy(ptr, req->ring, req->length * sizeof(request_t));
585 ptr += req->length * sizeof(request_t);
586 }
587
588 /* Response queues */
589 for (que = 1; que < ha->max_rsp_queues; que++) {
590 rsp = ha->rsp_q_map[que];
591 if (!rsp)
592 break;
593
594 /* Add chain. */
595 q = ptr;
596 *last_chain = &q->type;
597 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
598 q->chain_size = htonl(
599 sizeof(struct qla2xxx_mqueue_chain) +
600 sizeof(struct qla2xxx_mqueue_header) +
601 (rsp->length * sizeof(response_t)));
602 ptr += sizeof(struct qla2xxx_mqueue_chain);
603
604 /* Add header. */
605 qh = ptr;
606 qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
607 qh->number = htonl(que);
608 qh->size = htonl(rsp->length * sizeof(response_t));
609 ptr += sizeof(struct qla2xxx_mqueue_header);
610
611 /* Add data. */
612 memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
613 ptr += rsp->length * sizeof(response_t);
614 }
615
616 return ptr;
617 }
618
619 static inline void *
620 qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
621 {
622 uint32_t cnt, que_idx;
623 uint8_t que_cnt;
624 struct qla2xxx_mq_chain *mq = ptr;
625 device_reg_t __iomem *reg;
626
627 if (!ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha))
628 return ptr;
629
630 mq = ptr;
631 *last_chain = &mq->type;
632 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
633 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
634
635 que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
636 ha->max_req_queues : ha->max_rsp_queues;
637 mq->count = htonl(que_cnt);
638 for (cnt = 0; cnt < que_cnt; cnt++) {
639 reg = ISP_QUE_REG(ha, cnt);
640 que_idx = cnt * 4;
641 mq->qregs[que_idx] =
642 htonl(RD_REG_DWORD(&reg->isp25mq.req_q_in));
643 mq->qregs[que_idx+1] =
644 htonl(RD_REG_DWORD(&reg->isp25mq.req_q_out));
645 mq->qregs[que_idx+2] =
646 htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_in));
647 mq->qregs[que_idx+3] =
648 htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_out));
649 }
650
651 return ptr + sizeof(struct qla2xxx_mq_chain);
652 }
653
654 void
655 qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
656 {
657 struct qla_hw_data *ha = vha->hw;
658
659 if (rval != QLA_SUCCESS) {
660 ql_log(ql_log_warn, vha, 0xd000,
661 "Failed to dump firmware (%x).\n", rval);
662 ha->fw_dumped = 0;
663 } else {
664 ql_log(ql_log_info, vha, 0xd001,
665 "Firmware dump saved to temp buffer (%ld/%p).\n",
666 vha->host_no, ha->fw_dump);
667 ha->fw_dumped = 1;
668 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
669 }
670 }
671
672 /**
673 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
674 * @ha: HA context
675 * @hardware_locked: Called with the hardware_lock
676 */
677 void
678 qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
679 {
680 int rval;
681 uint32_t cnt;
682 struct qla_hw_data *ha = vha->hw;
683 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
684 uint16_t __iomem *dmp_reg;
685 unsigned long flags;
686 struct qla2300_fw_dump *fw;
687 void *nxt;
688 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
689
690 flags = 0;
691
692 if (!hardware_locked)
693 spin_lock_irqsave(&ha->hardware_lock, flags);
694
695 if (!ha->fw_dump) {
696 ql_log(ql_log_warn, vha, 0xd002,
697 "No buffer available for dump.\n");
698 goto qla2300_fw_dump_failed;
699 }
700
701 if (ha->fw_dumped) {
702 ql_log(ql_log_warn, vha, 0xd003,
703 "Firmware has been previously dumped (%p) "
704 "-- ignoring request.\n",
705 ha->fw_dump);
706 goto qla2300_fw_dump_failed;
707 }
708 fw = &ha->fw_dump->isp.isp23;
709 qla2xxx_prep_dump(ha, ha->fw_dump);
710
711 rval = QLA_SUCCESS;
712 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
713
714 /* Pause RISC. */
715 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
716 if (IS_QLA2300(ha)) {
717 for (cnt = 30000;
718 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
719 rval == QLA_SUCCESS; cnt--) {
720 if (cnt)
721 udelay(100);
722 else
723 rval = QLA_FUNCTION_TIMEOUT;
724 }
725 } else {
726 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
727 udelay(10);
728 }
729
730 if (rval == QLA_SUCCESS) {
731 dmp_reg = &reg->flash_address;
732 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
733 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
734
735 dmp_reg = &reg->u.isp2300.req_q_in;
736 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
737 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
738
739 dmp_reg = &reg->u.isp2300.mailbox0;
740 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
741 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
742
743 WRT_REG_WORD(&reg->ctrl_status, 0x40);
744 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
745
746 WRT_REG_WORD(&reg->ctrl_status, 0x50);
747 qla2xxx_read_window(reg, 48, fw->dma_reg);
748
749 WRT_REG_WORD(&reg->ctrl_status, 0x00);
750 dmp_reg = &reg->risc_hw;
751 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
752 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
753
754 WRT_REG_WORD(&reg->pcr, 0x2000);
755 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
756
757 WRT_REG_WORD(&reg->pcr, 0x2200);
758 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
759
760 WRT_REG_WORD(&reg->pcr, 0x2400);
761 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
762
763 WRT_REG_WORD(&reg->pcr, 0x2600);
764 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
765
766 WRT_REG_WORD(&reg->pcr, 0x2800);
767 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
768
769 WRT_REG_WORD(&reg->pcr, 0x2A00);
770 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
771
772 WRT_REG_WORD(&reg->pcr, 0x2C00);
773 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
774
775 WRT_REG_WORD(&reg->pcr, 0x2E00);
776 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
777
778 WRT_REG_WORD(&reg->ctrl_status, 0x10);
779 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
780
781 WRT_REG_WORD(&reg->ctrl_status, 0x20);
782 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
783
784 WRT_REG_WORD(&reg->ctrl_status, 0x30);
785 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
786
787 /* Reset RISC. */
788 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
789 for (cnt = 0; cnt < 30000; cnt++) {
790 if ((RD_REG_WORD(&reg->ctrl_status) &
791 CSR_ISP_SOFT_RESET) == 0)
792 break;
793
794 udelay(10);
795 }
796 }
797
798 if (!IS_QLA2300(ha)) {
799 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
800 rval == QLA_SUCCESS; cnt--) {
801 if (cnt)
802 udelay(100);
803 else
804 rval = QLA_FUNCTION_TIMEOUT;
805 }
806 }
807
808 /* Get RISC SRAM. */
809 if (rval == QLA_SUCCESS)
810 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
811 sizeof(fw->risc_ram) / 2, &nxt);
812
813 /* Get stack SRAM. */
814 if (rval == QLA_SUCCESS)
815 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
816 sizeof(fw->stack_ram) / 2, &nxt);
817
818 /* Get data SRAM. */
819 if (rval == QLA_SUCCESS)
820 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
821 ha->fw_memory_size - 0x11000 + 1, &nxt);
822
823 if (rval == QLA_SUCCESS)
824 qla2xxx_copy_queues(ha, nxt);
825
826 qla2xxx_dump_post_process(base_vha, rval);
827
828 qla2300_fw_dump_failed:
829 if (!hardware_locked)
830 spin_unlock_irqrestore(&ha->hardware_lock, flags);
831 }
832
833 /**
834 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
835 * @ha: HA context
836 * @hardware_locked: Called with the hardware_lock
837 */
838 void
839 qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
840 {
841 int rval;
842 uint32_t cnt, timer;
843 uint16_t risc_address;
844 uint16_t mb0, mb2;
845 struct qla_hw_data *ha = vha->hw;
846 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
847 uint16_t __iomem *dmp_reg;
848 unsigned long flags;
849 struct qla2100_fw_dump *fw;
850 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
851
852 risc_address = 0;
853 mb0 = mb2 = 0;
854 flags = 0;
855
856 if (!hardware_locked)
857 spin_lock_irqsave(&ha->hardware_lock, flags);
858
859 if (!ha->fw_dump) {
860 ql_log(ql_log_warn, vha, 0xd004,
861 "No buffer available for dump.\n");
862 goto qla2100_fw_dump_failed;
863 }
864
865 if (ha->fw_dumped) {
866 ql_log(ql_log_warn, vha, 0xd005,
867 "Firmware has been previously dumped (%p) "
868 "-- ignoring request.\n",
869 ha->fw_dump);
870 goto qla2100_fw_dump_failed;
871 }
872 fw = &ha->fw_dump->isp.isp21;
873 qla2xxx_prep_dump(ha, ha->fw_dump);
874
875 rval = QLA_SUCCESS;
876 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
877
878 /* Pause RISC. */
879 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
880 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
881 rval == QLA_SUCCESS; cnt--) {
882 if (cnt)
883 udelay(100);
884 else
885 rval = QLA_FUNCTION_TIMEOUT;
886 }
887 if (rval == QLA_SUCCESS) {
888 dmp_reg = &reg->flash_address;
889 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
890 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
891
892 dmp_reg = &reg->u.isp2100.mailbox0;
893 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
894 if (cnt == 8)
895 dmp_reg = &reg->u_end.isp2200.mailbox8;
896
897 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
898 }
899
900 dmp_reg = &reg->u.isp2100.unused_2[0];
901 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
902 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
903
904 WRT_REG_WORD(&reg->ctrl_status, 0x00);
905 dmp_reg = &reg->risc_hw;
906 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
907 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
908
909 WRT_REG_WORD(&reg->pcr, 0x2000);
910 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
911
912 WRT_REG_WORD(&reg->pcr, 0x2100);
913 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
914
915 WRT_REG_WORD(&reg->pcr, 0x2200);
916 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
917
918 WRT_REG_WORD(&reg->pcr, 0x2300);
919 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
920
921 WRT_REG_WORD(&reg->pcr, 0x2400);
922 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
923
924 WRT_REG_WORD(&reg->pcr, 0x2500);
925 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
926
927 WRT_REG_WORD(&reg->pcr, 0x2600);
928 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
929
930 WRT_REG_WORD(&reg->pcr, 0x2700);
931 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
932
933 WRT_REG_WORD(&reg->ctrl_status, 0x10);
934 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
935
936 WRT_REG_WORD(&reg->ctrl_status, 0x20);
937 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
938
939 WRT_REG_WORD(&reg->ctrl_status, 0x30);
940 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
941
942 /* Reset the ISP. */
943 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
944 }
945
946 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
947 rval == QLA_SUCCESS; cnt--) {
948 if (cnt)
949 udelay(100);
950 else
951 rval = QLA_FUNCTION_TIMEOUT;
952 }
953
954 /* Pause RISC. */
955 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
956 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
957
958 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
959 for (cnt = 30000;
960 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
961 rval == QLA_SUCCESS; cnt--) {
962 if (cnt)
963 udelay(100);
964 else
965 rval = QLA_FUNCTION_TIMEOUT;
966 }
967 if (rval == QLA_SUCCESS) {
968 /* Set memory configuration and timing. */
969 if (IS_QLA2100(ha))
970 WRT_REG_WORD(&reg->mctr, 0xf1);
971 else
972 WRT_REG_WORD(&reg->mctr, 0xf2);
973 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
974
975 /* Release RISC. */
976 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
977 }
978 }
979
980 if (rval == QLA_SUCCESS) {
981 /* Get RISC SRAM. */
982 risc_address = 0x1000;
983 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
984 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
985 }
986 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
987 cnt++, risc_address++) {
988 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
989 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
990
991 for (timer = 6000000; timer != 0; timer--) {
992 /* Check for pending interrupts. */
993 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
994 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
995 set_bit(MBX_INTERRUPT,
996 &ha->mbx_cmd_flags);
997
998 mb0 = RD_MAILBOX_REG(ha, reg, 0);
999 mb2 = RD_MAILBOX_REG(ha, reg, 2);
1000
1001 WRT_REG_WORD(&reg->semaphore, 0);
1002 WRT_REG_WORD(&reg->hccr,
1003 HCCR_CLR_RISC_INT);
1004 RD_REG_WORD(&reg->hccr);
1005 break;
1006 }
1007 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1008 RD_REG_WORD(&reg->hccr);
1009 }
1010 udelay(5);
1011 }
1012
1013 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1014 rval = mb0 & MBS_MASK;
1015 fw->risc_ram[cnt] = htons(mb2);
1016 } else {
1017 rval = QLA_FUNCTION_FAILED;
1018 }
1019 }
1020
1021 if (rval == QLA_SUCCESS)
1022 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
1023
1024 qla2xxx_dump_post_process(base_vha, rval);
1025
1026 qla2100_fw_dump_failed:
1027 if (!hardware_locked)
1028 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1029 }
1030
1031 void
1032 qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1033 {
1034 int rval;
1035 uint32_t cnt;
1036 uint32_t risc_address;
1037 struct qla_hw_data *ha = vha->hw;
1038 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1039 uint32_t __iomem *dmp_reg;
1040 uint32_t *iter_reg;
1041 uint16_t __iomem *mbx_reg;
1042 unsigned long flags;
1043 struct qla24xx_fw_dump *fw;
1044 uint32_t ext_mem_cnt;
1045 void *nxt;
1046 void *nxt_chain;
1047 uint32_t *last_chain = NULL;
1048 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1049
1050 if (IS_P3P_TYPE(ha))
1051 return;
1052
1053 risc_address = ext_mem_cnt = 0;
1054 flags = 0;
1055
1056 if (!hardware_locked)
1057 spin_lock_irqsave(&ha->hardware_lock, flags);
1058
1059 if (!ha->fw_dump) {
1060 ql_log(ql_log_warn, vha, 0xd006,
1061 "No buffer available for dump.\n");
1062 goto qla24xx_fw_dump_failed;
1063 }
1064
1065 if (ha->fw_dumped) {
1066 ql_log(ql_log_warn, vha, 0xd007,
1067 "Firmware has been previously dumped (%p) "
1068 "-- ignoring request.\n",
1069 ha->fw_dump);
1070 goto qla24xx_fw_dump_failed;
1071 }
1072 fw = &ha->fw_dump->isp.isp24;
1073 qla2xxx_prep_dump(ha, ha->fw_dump);
1074
1075 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1076
1077 /* Pause RISC. */
1078 rval = qla24xx_pause_risc(reg);
1079 if (rval != QLA_SUCCESS)
1080 goto qla24xx_fw_dump_failed_0;
1081
1082 /* Host interface registers. */
1083 dmp_reg = &reg->flash_addr;
1084 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1085 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1086
1087 /* Disable interrupts. */
1088 WRT_REG_DWORD(&reg->ictrl, 0);
1089 RD_REG_DWORD(&reg->ictrl);
1090
1091 /* Shadow registers. */
1092 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1093 RD_REG_DWORD(&reg->iobase_addr);
1094 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1095 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1096
1097 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1098 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1099
1100 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1101 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1102
1103 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1104 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1105
1106 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1107 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1108
1109 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1110 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1111
1112 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1113 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1114
1115 /* Mailbox registers. */
1116 mbx_reg = &reg->mailbox0;
1117 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1118 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1119
1120 /* Transfer sequence registers. */
1121 iter_reg = fw->xseq_gp_reg;
1122 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1123 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1124 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1125 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1126 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1127 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1128 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1129 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1130
1131 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
1132 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1133
1134 /* Receive sequence registers. */
1135 iter_reg = fw->rseq_gp_reg;
1136 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1137 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1138 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1139 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1140 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1141 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1142 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1143 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1144
1145 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
1146 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1147 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1148
1149 /* Command DMA registers. */
1150 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1151
1152 /* Queues. */
1153 iter_reg = fw->req0_dma_reg;
1154 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1155 dmp_reg = &reg->iobase_q;
1156 for (cnt = 0; cnt < 7; cnt++)
1157 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1158
1159 iter_reg = fw->resp0_dma_reg;
1160 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1161 dmp_reg = &reg->iobase_q;
1162 for (cnt = 0; cnt < 7; cnt++)
1163 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1164
1165 iter_reg = fw->req1_dma_reg;
1166 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1167 dmp_reg = &reg->iobase_q;
1168 for (cnt = 0; cnt < 7; cnt++)
1169 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1170
1171 /* Transmit DMA registers. */
1172 iter_reg = fw->xmt0_dma_reg;
1173 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1174 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1175
1176 iter_reg = fw->xmt1_dma_reg;
1177 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1178 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1179
1180 iter_reg = fw->xmt2_dma_reg;
1181 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1182 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1183
1184 iter_reg = fw->xmt3_dma_reg;
1185 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1186 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1187
1188 iter_reg = fw->xmt4_dma_reg;
1189 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1190 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1191
1192 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1193
1194 /* Receive DMA registers. */
1195 iter_reg = fw->rcvt0_data_dma_reg;
1196 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1197 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1198
1199 iter_reg = fw->rcvt1_data_dma_reg;
1200 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1201 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1202
1203 /* RISC registers. */
1204 iter_reg = fw->risc_gp_reg;
1205 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1206 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1207 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1208 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1209 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1210 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1211 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1212 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1213
1214 /* Local memory controller registers. */
1215 iter_reg = fw->lmc_reg;
1216 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1217 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1218 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1219 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1220 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1221 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1222 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1223
1224 /* Fibre Protocol Module registers. */
1225 iter_reg = fw->fpm_hdw_reg;
1226 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1227 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1228 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1229 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1230 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1231 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1232 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1233 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1234 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1235 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1236 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1237 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1238
1239 /* Frame Buffer registers. */
1240 iter_reg = fw->fb_hdw_reg;
1241 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1242 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1243 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1244 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1245 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1246 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1247 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1248 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1249 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1250 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1251 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1252
1253 rval = qla24xx_soft_reset(ha);
1254 if (rval != QLA_SUCCESS)
1255 goto qla24xx_fw_dump_failed_0;
1256
1257 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1258 &nxt);
1259 if (rval != QLA_SUCCESS)
1260 goto qla24xx_fw_dump_failed_0;
1261
1262 nxt = qla2xxx_copy_queues(ha, nxt);
1263
1264 qla24xx_copy_eft(ha, nxt);
1265
1266 nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
1267 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1268 if (last_chain) {
1269 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1270 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1271 }
1272
1273 /* Adjust valid length. */
1274 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1275
1276 qla24xx_fw_dump_failed_0:
1277 qla2xxx_dump_post_process(base_vha, rval);
1278
1279 qla24xx_fw_dump_failed:
1280 if (!hardware_locked)
1281 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1282 }
1283
1284 void
1285 qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1286 {
1287 int rval;
1288 uint32_t cnt;
1289 uint32_t risc_address;
1290 struct qla_hw_data *ha = vha->hw;
1291 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1292 uint32_t __iomem *dmp_reg;
1293 uint32_t *iter_reg;
1294 uint16_t __iomem *mbx_reg;
1295 unsigned long flags;
1296 struct qla25xx_fw_dump *fw;
1297 uint32_t ext_mem_cnt;
1298 void *nxt, *nxt_chain;
1299 uint32_t *last_chain = NULL;
1300 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1301
1302 risc_address = ext_mem_cnt = 0;
1303 flags = 0;
1304
1305 if (!hardware_locked)
1306 spin_lock_irqsave(&ha->hardware_lock, flags);
1307
1308 if (!ha->fw_dump) {
1309 ql_log(ql_log_warn, vha, 0xd008,
1310 "No buffer available for dump.\n");
1311 goto qla25xx_fw_dump_failed;
1312 }
1313
1314 if (ha->fw_dumped) {
1315 ql_log(ql_log_warn, vha, 0xd009,
1316 "Firmware has been previously dumped (%p) "
1317 "-- ignoring request.\n",
1318 ha->fw_dump);
1319 goto qla25xx_fw_dump_failed;
1320 }
1321 fw = &ha->fw_dump->isp.isp25;
1322 qla2xxx_prep_dump(ha, ha->fw_dump);
1323 ha->fw_dump->version = __constant_htonl(2);
1324
1325 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1326
1327 /* Pause RISC. */
1328 rval = qla24xx_pause_risc(reg);
1329 if (rval != QLA_SUCCESS)
1330 goto qla25xx_fw_dump_failed_0;
1331
1332 /* Host/Risc registers. */
1333 iter_reg = fw->host_risc_reg;
1334 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1335 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1336
1337 /* PCIe registers. */
1338 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1339 RD_REG_DWORD(&reg->iobase_addr);
1340 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1341 dmp_reg = &reg->iobase_c4;
1342 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1343 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1344 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1345 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1346
1347 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1348 RD_REG_DWORD(&reg->iobase_window);
1349
1350 /* Host interface registers. */
1351 dmp_reg = &reg->flash_addr;
1352 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1353 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1354
1355 /* Disable interrupts. */
1356 WRT_REG_DWORD(&reg->ictrl, 0);
1357 RD_REG_DWORD(&reg->ictrl);
1358
1359 /* Shadow registers. */
1360 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1361 RD_REG_DWORD(&reg->iobase_addr);
1362 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1363 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1364
1365 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1366 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1367
1368 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1369 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1370
1371 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1372 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1373
1374 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1375 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1376
1377 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1378 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1379
1380 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1381 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1382
1383 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1384 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1385
1386 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1387 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1388
1389 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1390 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1391
1392 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1393 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1394
1395 /* RISC I/O register. */
1396 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1397 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1398
1399 /* Mailbox registers. */
1400 mbx_reg = &reg->mailbox0;
1401 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1402 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1403
1404 /* Transfer sequence registers. */
1405 iter_reg = fw->xseq_gp_reg;
1406 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1407 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1408 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1409 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1410 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1411 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1412 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1413 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1414
1415 iter_reg = fw->xseq_0_reg;
1416 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1417 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1418 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1419
1420 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1421
1422 /* Receive sequence registers. */
1423 iter_reg = fw->rseq_gp_reg;
1424 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1425 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1426 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1427 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1428 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1429 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1430 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1431 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1432
1433 iter_reg = fw->rseq_0_reg;
1434 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1435 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1436
1437 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1438 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1439
1440 /* Auxiliary sequence registers. */
1441 iter_reg = fw->aseq_gp_reg;
1442 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1443 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1444 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1445 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1446 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1447 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1448 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1449 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1450
1451 iter_reg = fw->aseq_0_reg;
1452 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1453 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1454
1455 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1456 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1457
1458 /* Command DMA registers. */
1459 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1460
1461 /* Queues. */
1462 iter_reg = fw->req0_dma_reg;
1463 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1464 dmp_reg = &reg->iobase_q;
1465 for (cnt = 0; cnt < 7; cnt++)
1466 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1467
1468 iter_reg = fw->resp0_dma_reg;
1469 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1470 dmp_reg = &reg->iobase_q;
1471 for (cnt = 0; cnt < 7; cnt++)
1472 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1473
1474 iter_reg = fw->req1_dma_reg;
1475 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1476 dmp_reg = &reg->iobase_q;
1477 for (cnt = 0; cnt < 7; cnt++)
1478 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1479
1480 /* Transmit DMA registers. */
1481 iter_reg = fw->xmt0_dma_reg;
1482 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1483 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1484
1485 iter_reg = fw->xmt1_dma_reg;
1486 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1487 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1488
1489 iter_reg = fw->xmt2_dma_reg;
1490 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1491 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1492
1493 iter_reg = fw->xmt3_dma_reg;
1494 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1495 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1496
1497 iter_reg = fw->xmt4_dma_reg;
1498 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1499 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1500
1501 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1502
1503 /* Receive DMA registers. */
1504 iter_reg = fw->rcvt0_data_dma_reg;
1505 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1506 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1507
1508 iter_reg = fw->rcvt1_data_dma_reg;
1509 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1510 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1511
1512 /* RISC registers. */
1513 iter_reg = fw->risc_gp_reg;
1514 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1515 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1516 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1517 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1518 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1519 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1520 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1521 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1522
1523 /* Local memory controller registers. */
1524 iter_reg = fw->lmc_reg;
1525 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1526 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1527 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1528 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1529 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1530 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1531 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1532 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1533
1534 /* Fibre Protocol Module registers. */
1535 iter_reg = fw->fpm_hdw_reg;
1536 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1537 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1538 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1539 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1540 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1541 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1542 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1543 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1544 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1545 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1546 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1547 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1548
1549 /* Frame Buffer registers. */
1550 iter_reg = fw->fb_hdw_reg;
1551 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1552 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1553 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1554 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1555 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1556 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1557 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1558 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1559 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1560 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1561 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1562 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1563
1564 /* Multi queue registers */
1565 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1566 &last_chain);
1567
1568 rval = qla24xx_soft_reset(ha);
1569 if (rval != QLA_SUCCESS)
1570 goto qla25xx_fw_dump_failed_0;
1571
1572 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1573 &nxt);
1574 if (rval != QLA_SUCCESS)
1575 goto qla25xx_fw_dump_failed_0;
1576
1577 nxt = qla2xxx_copy_queues(ha, nxt);
1578
1579 qla24xx_copy_eft(ha, nxt);
1580
1581 /* Chain entries -- started with MQ. */
1582 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1583 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
1584 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1585 if (last_chain) {
1586 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1587 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1588 }
1589
1590 /* Adjust valid length. */
1591 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1592
1593 qla25xx_fw_dump_failed_0:
1594 qla2xxx_dump_post_process(base_vha, rval);
1595
1596 qla25xx_fw_dump_failed:
1597 if (!hardware_locked)
1598 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1599 }
1600
1601 void
1602 qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1603 {
1604 int rval;
1605 uint32_t cnt;
1606 uint32_t risc_address;
1607 struct qla_hw_data *ha = vha->hw;
1608 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1609 uint32_t __iomem *dmp_reg;
1610 uint32_t *iter_reg;
1611 uint16_t __iomem *mbx_reg;
1612 unsigned long flags;
1613 struct qla81xx_fw_dump *fw;
1614 uint32_t ext_mem_cnt;
1615 void *nxt, *nxt_chain;
1616 uint32_t *last_chain = NULL;
1617 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1618
1619 risc_address = ext_mem_cnt = 0;
1620 flags = 0;
1621
1622 if (!hardware_locked)
1623 spin_lock_irqsave(&ha->hardware_lock, flags);
1624
1625 if (!ha->fw_dump) {
1626 ql_log(ql_log_warn, vha, 0xd00a,
1627 "No buffer available for dump.\n");
1628 goto qla81xx_fw_dump_failed;
1629 }
1630
1631 if (ha->fw_dumped) {
1632 ql_log(ql_log_warn, vha, 0xd00b,
1633 "Firmware has been previously dumped (%p) "
1634 "-- ignoring request.\n",
1635 ha->fw_dump);
1636 goto qla81xx_fw_dump_failed;
1637 }
1638 fw = &ha->fw_dump->isp.isp81;
1639 qla2xxx_prep_dump(ha, ha->fw_dump);
1640
1641 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1642
1643 /* Pause RISC. */
1644 rval = qla24xx_pause_risc(reg);
1645 if (rval != QLA_SUCCESS)
1646 goto qla81xx_fw_dump_failed_0;
1647
1648 /* Host/Risc registers. */
1649 iter_reg = fw->host_risc_reg;
1650 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1651 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1652
1653 /* PCIe registers. */
1654 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1655 RD_REG_DWORD(&reg->iobase_addr);
1656 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1657 dmp_reg = &reg->iobase_c4;
1658 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1659 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1660 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1661 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1662
1663 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1664 RD_REG_DWORD(&reg->iobase_window);
1665
1666 /* Host interface registers. */
1667 dmp_reg = &reg->flash_addr;
1668 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1669 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1670
1671 /* Disable interrupts. */
1672 WRT_REG_DWORD(&reg->ictrl, 0);
1673 RD_REG_DWORD(&reg->ictrl);
1674
1675 /* Shadow registers. */
1676 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1677 RD_REG_DWORD(&reg->iobase_addr);
1678 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1679 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1680
1681 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1682 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1683
1684 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1685 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1686
1687 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1688 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1689
1690 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1691 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1692
1693 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1694 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1695
1696 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1697 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1698
1699 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1700 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1701
1702 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1703 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1704
1705 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1706 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1707
1708 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1709 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1710
1711 /* RISC I/O register. */
1712 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1713 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1714
1715 /* Mailbox registers. */
1716 mbx_reg = &reg->mailbox0;
1717 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1718 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1719
1720 /* Transfer sequence registers. */
1721 iter_reg = fw->xseq_gp_reg;
1722 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1723 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1724 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1725 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1726 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1727 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1728 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1729 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1730
1731 iter_reg = fw->xseq_0_reg;
1732 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1733 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1734 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1735
1736 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1737
1738 /* Receive sequence registers. */
1739 iter_reg = fw->rseq_gp_reg;
1740 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1741 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1742 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1743 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1744 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1745 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1746 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1747 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1748
1749 iter_reg = fw->rseq_0_reg;
1750 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1751 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1752
1753 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1754 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1755
1756 /* Auxiliary sequence registers. */
1757 iter_reg = fw->aseq_gp_reg;
1758 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1759 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1760 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1761 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1762 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1763 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1764 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1765 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1766
1767 iter_reg = fw->aseq_0_reg;
1768 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1769 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1770
1771 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1772 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1773
1774 /* Command DMA registers. */
1775 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1776
1777 /* Queues. */
1778 iter_reg = fw->req0_dma_reg;
1779 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1780 dmp_reg = &reg->iobase_q;
1781 for (cnt = 0; cnt < 7; cnt++)
1782 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1783
1784 iter_reg = fw->resp0_dma_reg;
1785 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1786 dmp_reg = &reg->iobase_q;
1787 for (cnt = 0; cnt < 7; cnt++)
1788 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1789
1790 iter_reg = fw->req1_dma_reg;
1791 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1792 dmp_reg = &reg->iobase_q;
1793 for (cnt = 0; cnt < 7; cnt++)
1794 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1795
1796 /* Transmit DMA registers. */
1797 iter_reg = fw->xmt0_dma_reg;
1798 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1799 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1800
1801 iter_reg = fw->xmt1_dma_reg;
1802 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1803 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1804
1805 iter_reg = fw->xmt2_dma_reg;
1806 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1807 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1808
1809 iter_reg = fw->xmt3_dma_reg;
1810 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1811 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1812
1813 iter_reg = fw->xmt4_dma_reg;
1814 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1815 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1816
1817 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1818
1819 /* Receive DMA registers. */
1820 iter_reg = fw->rcvt0_data_dma_reg;
1821 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1822 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1823
1824 iter_reg = fw->rcvt1_data_dma_reg;
1825 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1826 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1827
1828 /* RISC registers. */
1829 iter_reg = fw->risc_gp_reg;
1830 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1831 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1832 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1833 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1834 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1835 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1836 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1837 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1838
1839 /* Local memory controller registers. */
1840 iter_reg = fw->lmc_reg;
1841 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1842 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1843 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1844 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1845 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1846 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1847 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1848 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1849
1850 /* Fibre Protocol Module registers. */
1851 iter_reg = fw->fpm_hdw_reg;
1852 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1853 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1854 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1855 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1856 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1857 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1858 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1859 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1860 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1861 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1862 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1863 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1864 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1865 qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1866
1867 /* Frame Buffer registers. */
1868 iter_reg = fw->fb_hdw_reg;
1869 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1870 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1871 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1872 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1873 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1874 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1875 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1876 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1877 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1878 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1879 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1880 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1881 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1882
1883 /* Multi queue registers */
1884 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1885 &last_chain);
1886
1887 rval = qla24xx_soft_reset(ha);
1888 if (rval != QLA_SUCCESS)
1889 goto qla81xx_fw_dump_failed_0;
1890
1891 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1892 &nxt);
1893 if (rval != QLA_SUCCESS)
1894 goto qla81xx_fw_dump_failed_0;
1895
1896 nxt = qla2xxx_copy_queues(ha, nxt);
1897
1898 qla24xx_copy_eft(ha, nxt);
1899
1900 /* Chain entries -- started with MQ. */
1901 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1902 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
1903 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1904 if (last_chain) {
1905 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1906 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1907 }
1908
1909 /* Adjust valid length. */
1910 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1911
1912 qla81xx_fw_dump_failed_0:
1913 qla2xxx_dump_post_process(base_vha, rval);
1914
1915 qla81xx_fw_dump_failed:
1916 if (!hardware_locked)
1917 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1918 }
1919
1920 void
1921 qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1922 {
1923 int rval;
1924 uint32_t cnt, reg_data;
1925 uint32_t risc_address;
1926 struct qla_hw_data *ha = vha->hw;
1927 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1928 uint32_t __iomem *dmp_reg;
1929 uint32_t *iter_reg;
1930 uint16_t __iomem *mbx_reg;
1931 unsigned long flags;
1932 struct qla83xx_fw_dump *fw;
1933 uint32_t ext_mem_cnt;
1934 void *nxt, *nxt_chain;
1935 uint32_t *last_chain = NULL;
1936 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1937
1938 risc_address = ext_mem_cnt = 0;
1939 flags = 0;
1940
1941 if (!hardware_locked)
1942 spin_lock_irqsave(&ha->hardware_lock, flags);
1943
1944 if (!ha->fw_dump) {
1945 ql_log(ql_log_warn, vha, 0xd00c,
1946 "No buffer available for dump!!!\n");
1947 goto qla83xx_fw_dump_failed;
1948 }
1949
1950 if (ha->fw_dumped) {
1951 ql_log(ql_log_warn, vha, 0xd00d,
1952 "Firmware has been previously dumped (%p) -- ignoring "
1953 "request...\n", ha->fw_dump);
1954 goto qla83xx_fw_dump_failed;
1955 }
1956 fw = &ha->fw_dump->isp.isp83;
1957 qla2xxx_prep_dump(ha, ha->fw_dump);
1958
1959 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1960
1961 /* Pause RISC. */
1962 rval = qla24xx_pause_risc(reg);
1963 if (rval != QLA_SUCCESS)
1964 goto qla83xx_fw_dump_failed_0;
1965
1966 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1967 dmp_reg = &reg->iobase_window;
1968 reg_data = RD_REG_DWORD(dmp_reg);
1969 WRT_REG_DWORD(dmp_reg, 0);
1970
1971 dmp_reg = &reg->unused_4_1[0];
1972 reg_data = RD_REG_DWORD(dmp_reg);
1973 WRT_REG_DWORD(dmp_reg, 0);
1974
1975 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1976 dmp_reg = &reg->unused_4_1[2];
1977 reg_data = RD_REG_DWORD(dmp_reg);
1978 WRT_REG_DWORD(dmp_reg, 0);
1979
1980 /* select PCR and disable ecc checking and correction */
1981 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1982 RD_REG_DWORD(&reg->iobase_addr);
1983 WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
1984
1985 /* Host/Risc registers. */
1986 iter_reg = fw->host_risc_reg;
1987 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1988 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1989 qla24xx_read_window(reg, 0x7040, 16, iter_reg);
1990
1991 /* PCIe registers. */
1992 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1993 RD_REG_DWORD(&reg->iobase_addr);
1994 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1995 dmp_reg = &reg->iobase_c4;
1996 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1997 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1998 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1999 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
2000
2001 WRT_REG_DWORD(&reg->iobase_window, 0x00);
2002 RD_REG_DWORD(&reg->iobase_window);
2003
2004 /* Host interface registers. */
2005 dmp_reg = &reg->flash_addr;
2006 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
2007 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
2008
2009 /* Disable interrupts. */
2010 WRT_REG_DWORD(&reg->ictrl, 0);
2011 RD_REG_DWORD(&reg->ictrl);
2012
2013 /* Shadow registers. */
2014 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
2015 RD_REG_DWORD(&reg->iobase_addr);
2016 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
2017 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2018
2019 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
2020 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2021
2022 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
2023 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2024
2025 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
2026 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2027
2028 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
2029 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2030
2031 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
2032 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2033
2034 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
2035 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2036
2037 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
2038 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2039
2040 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
2041 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2042
2043 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
2044 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2045
2046 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
2047 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2048
2049 /* RISC I/O register. */
2050 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
2051 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
2052
2053 /* Mailbox registers. */
2054 mbx_reg = &reg->mailbox0;
2055 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
2056 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
2057
2058 /* Transfer sequence registers. */
2059 iter_reg = fw->xseq_gp_reg;
2060 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
2061 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
2062 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
2063 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
2064 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
2065 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
2066 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
2067 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
2068 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
2069 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
2070 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
2071 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
2072 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
2073 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
2074 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
2075 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
2076
2077 iter_reg = fw->xseq_0_reg;
2078 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
2079 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
2080 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
2081
2082 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
2083
2084 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
2085
2086 /* Receive sequence registers. */
2087 iter_reg = fw->rseq_gp_reg;
2088 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
2089 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
2090 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
2091 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
2092 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
2093 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
2094 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
2095 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
2096 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
2097 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
2098 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
2099 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
2100 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
2101 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
2102 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
2103 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
2104
2105 iter_reg = fw->rseq_0_reg;
2106 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
2107 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
2108
2109 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
2110 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
2111 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
2112
2113 /* Auxiliary sequence registers. */
2114 iter_reg = fw->aseq_gp_reg;
2115 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
2116 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
2117 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
2118 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
2119 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
2120 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
2121 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
2122 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
2123 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
2124 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
2125 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
2126 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
2127 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
2128 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
2129 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
2130 qla24xx_read_window(reg, 0xB170, 16, iter_reg);
2131
2132 iter_reg = fw->aseq_0_reg;
2133 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
2134 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
2135
2136 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
2137 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
2138 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
2139
2140 /* Command DMA registers. */
2141 iter_reg = fw->cmd_dma_reg;
2142 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
2143 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
2144 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
2145 qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
2146
2147 /* Queues. */
2148 iter_reg = fw->req0_dma_reg;
2149 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
2150 dmp_reg = &reg->iobase_q;
2151 for (cnt = 0; cnt < 7; cnt++)
2152 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2153
2154 iter_reg = fw->resp0_dma_reg;
2155 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
2156 dmp_reg = &reg->iobase_q;
2157 for (cnt = 0; cnt < 7; cnt++)
2158 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2159
2160 iter_reg = fw->req1_dma_reg;
2161 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
2162 dmp_reg = &reg->iobase_q;
2163 for (cnt = 0; cnt < 7; cnt++)
2164 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2165
2166 /* Transmit DMA registers. */
2167 iter_reg = fw->xmt0_dma_reg;
2168 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
2169 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
2170
2171 iter_reg = fw->xmt1_dma_reg;
2172 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
2173 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
2174
2175 iter_reg = fw->xmt2_dma_reg;
2176 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
2177 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
2178
2179 iter_reg = fw->xmt3_dma_reg;
2180 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
2181 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
2182
2183 iter_reg = fw->xmt4_dma_reg;
2184 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
2185 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
2186
2187 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
2188
2189 /* Receive DMA registers. */
2190 iter_reg = fw->rcvt0_data_dma_reg;
2191 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
2192 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
2193
2194 iter_reg = fw->rcvt1_data_dma_reg;
2195 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
2196 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
2197
2198 /* RISC registers. */
2199 iter_reg = fw->risc_gp_reg;
2200 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
2201 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
2202 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
2203 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
2204 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
2205 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
2206 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
2207 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
2208
2209 /* Local memory controller registers. */
2210 iter_reg = fw->lmc_reg;
2211 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
2212 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
2213 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
2214 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
2215 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
2216 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
2217 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
2218 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
2219
2220 /* Fibre Protocol Module registers. */
2221 iter_reg = fw->fpm_hdw_reg;
2222 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
2223 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
2224 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
2225 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
2226 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
2227 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
2228 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
2229 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
2230 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
2231 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
2232 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
2233 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
2234 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
2235 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
2236 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
2237 qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
2238
2239 /* RQ0 Array registers. */
2240 iter_reg = fw->rq0_array_reg;
2241 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
2242 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
2243 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
2244 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
2245 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
2246 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
2247 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
2248 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
2249 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
2250 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
2251 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
2252 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
2253 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
2254 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
2255 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
2256 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
2257
2258 /* RQ1 Array registers. */
2259 iter_reg = fw->rq1_array_reg;
2260 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
2261 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
2262 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
2263 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
2264 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
2265 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
2266 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
2267 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
2268 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
2269 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
2270 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
2271 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
2272 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
2273 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
2274 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
2275 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
2276
2277 /* RP0 Array registers. */
2278 iter_reg = fw->rp0_array_reg;
2279 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
2280 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
2281 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
2282 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
2283 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
2284 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
2285 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
2286 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
2287 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
2288 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
2289 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
2290 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
2291 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
2292 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
2293 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
2294 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
2295
2296 /* RP1 Array registers. */
2297 iter_reg = fw->rp1_array_reg;
2298 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
2299 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
2300 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
2301 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
2302 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
2303 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
2304 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
2305 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
2306 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
2307 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
2308 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
2309 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
2310 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
2311 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
2312 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
2313 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
2314
2315 iter_reg = fw->at0_array_reg;
2316 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
2317 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
2318 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
2319 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
2320 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
2321 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
2322 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
2323 qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
2324
2325 /* I/O Queue Control registers. */
2326 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
2327
2328 /* Frame Buffer registers. */
2329 iter_reg = fw->fb_hdw_reg;
2330 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
2331 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
2332 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
2333 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
2334 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
2335 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
2336 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
2337 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
2338 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
2339 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
2340 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
2341 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
2342 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
2343 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
2344 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
2345 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
2346 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
2347 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
2348 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
2349 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
2350 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
2351 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
2352 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
2353 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
2354 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
2355 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
2356 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
2357
2358 /* Multi queue registers */
2359 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
2360 &last_chain);
2361
2362 rval = qla24xx_soft_reset(ha);
2363 if (rval != QLA_SUCCESS) {
2364 ql_log(ql_log_warn, vha, 0xd00e,
2365 "SOFT RESET FAILED, forcing continuation of dump!!!\n");
2366 rval = QLA_SUCCESS;
2367
2368 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
2369
2370 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2371 RD_REG_DWORD(&reg->hccr);
2372
2373 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2374 RD_REG_DWORD(&reg->hccr);
2375
2376 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2377 RD_REG_DWORD(&reg->hccr);
2378
2379 for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
2380 udelay(5);
2381
2382 if (!cnt) {
2383 nxt = fw->code_ram;
2384 nxt += sizeof(fw->code_ram);
2385 nxt += (ha->fw_memory_size - 0x100000 + 1);
2386 goto copy_queue;
2387 } else
2388 ql_log(ql_log_warn, vha, 0xd010,
2389 "bigger hammer success?\n");
2390 }
2391
2392 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
2393 &nxt);
2394 if (rval != QLA_SUCCESS)
2395 goto qla83xx_fw_dump_failed_0;
2396
2397 copy_queue:
2398 nxt = qla2xxx_copy_queues(ha, nxt);
2399
2400 qla24xx_copy_eft(ha, nxt);
2401
2402 /* Chain entries -- started with MQ. */
2403 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
2404 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2405 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
2406 if (last_chain) {
2407 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
2408 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
2409 }
2410
2411 /* Adjust valid length. */
2412 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
2413
2414 qla83xx_fw_dump_failed_0:
2415 qla2xxx_dump_post_process(base_vha, rval);
2416
2417 qla83xx_fw_dump_failed:
2418 if (!hardware_locked)
2419 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2420 }
2421
2422 /****************************************************************************/
2423 /* Driver Debug Functions. */
2424 /****************************************************************************/
2425
2426 static inline int
2427 ql_mask_match(uint32_t level)
2428 {
2429 if (ql2xextended_error_logging == 1)
2430 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2431 return (level & ql2xextended_error_logging) == level;
2432 }
2433
2434 /*
2435 * This function is for formatting and logging debug information.
2436 * It is to be used when vha is available. It formats the message
2437 * and logs it to the messages file.
2438 * parameters:
2439 * level: The level of the debug messages to be printed.
2440 * If ql2xextended_error_logging value is correctly set,
2441 * this message will appear in the messages file.
2442 * vha: Pointer to the scsi_qla_host_t.
2443 * id: This is a unique identifier for the level. It identifies the
2444 * part of the code from where the message originated.
2445 * msg: The message to be displayed.
2446 */
2447 void
2448 ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2449 {
2450 va_list va;
2451 struct va_format vaf;
2452
2453 if (!ql_mask_match(level))
2454 return;
2455
2456 va_start(va, fmt);
2457
2458 vaf.fmt = fmt;
2459 vaf.va = &va;
2460
2461 if (vha != NULL) {
2462 const struct pci_dev *pdev = vha->hw->pdev;
2463 /* <module-name> <pci-name> <msg-id>:<host> Message */
2464 pr_warn("%s [%s]-%04x:%ld: %pV",
2465 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
2466 vha->host_no, &vaf);
2467 } else {
2468 pr_warn("%s [%s]-%04x: : %pV",
2469 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
2470 }
2471
2472 va_end(va);
2473
2474 }
2475
2476 /*
2477 * This function is for formatting and logging debug information.
2478 * It is to be used when vha is not available and pci is available,
2479 * i.e., before host allocation. It formats the message and logs it
2480 * to the messages file.
2481 * parameters:
2482 * level: The level of the debug messages to be printed.
2483 * If ql2xextended_error_logging value is correctly set,
2484 * this message will appear in the messages file.
2485 * pdev: Pointer to the struct pci_dev.
2486 * id: This is a unique id for the level. It identifies the part
2487 * of the code from where the message originated.
2488 * msg: The message to be displayed.
2489 */
2490 void
2491 ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2492 const char *fmt, ...)
2493 {
2494 va_list va;
2495 struct va_format vaf;
2496
2497 if (pdev == NULL)
2498 return;
2499 if (!ql_mask_match(level))
2500 return;
2501
2502 va_start(va, fmt);
2503
2504 vaf.fmt = fmt;
2505 vaf.va = &va;
2506
2507 /* <module-name> <dev-name>:<msg-id> Message */
2508 pr_warn("%s [%s]-%04x: : %pV",
2509 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
2510
2511 va_end(va);
2512 }
2513
2514 /*
2515 * This function is for formatting and logging log messages.
2516 * It is to be used when vha is available. It formats the message
2517 * and logs it to the messages file. All the messages will be logged
2518 * irrespective of value of ql2xextended_error_logging.
2519 * parameters:
2520 * level: The level of the log messages to be printed in the
2521 * messages file.
2522 * vha: Pointer to the scsi_qla_host_t
2523 * id: This is a unique id for the level. It identifies the
2524 * part of the code from where the message originated.
2525 * msg: The message to be displayed.
2526 */
2527 void
2528 ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2529 {
2530 va_list va;
2531 struct va_format vaf;
2532 char pbuf[128];
2533
2534 if (level > ql_errlev)
2535 return;
2536
2537 if (vha != NULL) {
2538 const struct pci_dev *pdev = vha->hw->pdev;
2539 /* <module-name> <msg-id>:<host> Message */
2540 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
2541 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
2542 } else {
2543 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2544 QL_MSGHDR, "0000:00:00.0", id);
2545 }
2546 pbuf[sizeof(pbuf) - 1] = 0;
2547
2548 va_start(va, fmt);
2549
2550 vaf.fmt = fmt;
2551 vaf.va = &va;
2552
2553 switch (level) {
2554 case ql_log_fatal: /* FATAL LOG */
2555 pr_crit("%s%pV", pbuf, &vaf);
2556 break;
2557 case ql_log_warn:
2558 pr_err("%s%pV", pbuf, &vaf);
2559 break;
2560 case ql_log_info:
2561 pr_warn("%s%pV", pbuf, &vaf);
2562 break;
2563 default:
2564 pr_info("%s%pV", pbuf, &vaf);
2565 break;
2566 }
2567
2568 va_end(va);
2569 }
2570
2571 /*
2572 * This function is for formatting and logging log messages.
2573 * It is to be used when vha is not available and pci is available,
2574 * i.e., before host allocation. It formats the message and logs
2575 * it to the messages file. All the messages are logged irrespective
2576 * of the value of ql2xextended_error_logging.
2577 * parameters:
2578 * level: The level of the log messages to be printed in the
2579 * messages file.
2580 * pdev: Pointer to the struct pci_dev.
2581 * id: This is a unique id for the level. It identifies the
2582 * part of the code from where the message originated.
2583 * msg: The message to be displayed.
2584 */
2585 void
2586 ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2587 const char *fmt, ...)
2588 {
2589 va_list va;
2590 struct va_format vaf;
2591 char pbuf[128];
2592
2593 if (pdev == NULL)
2594 return;
2595 if (level > ql_errlev)
2596 return;
2597
2598 /* <module-name> <dev-name>:<msg-id> Message */
2599 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2600 QL_MSGHDR, dev_name(&(pdev->dev)), id);
2601 pbuf[sizeof(pbuf) - 1] = 0;
2602
2603 va_start(va, fmt);
2604
2605 vaf.fmt = fmt;
2606 vaf.va = &va;
2607
2608 switch (level) {
2609 case ql_log_fatal: /* FATAL LOG */
2610 pr_crit("%s%pV", pbuf, &vaf);
2611 break;
2612 case ql_log_warn:
2613 pr_err("%s%pV", pbuf, &vaf);
2614 break;
2615 case ql_log_info:
2616 pr_warn("%s%pV", pbuf, &vaf);
2617 break;
2618 default:
2619 pr_info("%s%pV", pbuf, &vaf);
2620 break;
2621 }
2622
2623 va_end(va);
2624 }
2625
2626 void
2627 ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
2628 {
2629 int i;
2630 struct qla_hw_data *ha = vha->hw;
2631 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2632 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
2633 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
2634 uint16_t __iomem *mbx_reg;
2635
2636 if (!ql_mask_match(level))
2637 return;
2638
2639 if (IS_P3P_TYPE(ha))
2640 mbx_reg = &reg82->mailbox_in[0];
2641 else if (IS_FWI2_CAPABLE(ha))
2642 mbx_reg = &reg24->mailbox0;
2643 else
2644 mbx_reg = MAILBOX_REG(ha, reg, 0);
2645
2646 ql_dbg(level, vha, id, "Mailbox registers:\n");
2647 for (i = 0; i < 6; i++)
2648 ql_dbg(level, vha, id,
2649 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
2650 }
2651
2652
2653 void
2654 ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
2655 uint8_t *b, uint32_t size)
2656 {
2657 uint32_t cnt;
2658 uint8_t c;
2659
2660 if (!ql_mask_match(level))
2661 return;
2662
2663 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
2664 "9 Ah Bh Ch Dh Eh Fh\n");
2665 ql_dbg(level, vha, id, "----------------------------------"
2666 "----------------------------\n");
2667
2668 ql_dbg(level, vha, id, " ");
2669 for (cnt = 0; cnt < size;) {
2670 c = *b++;
2671 printk("%02x", (uint32_t) c);
2672 cnt++;
2673 if (!(cnt % 16))
2674 printk("\n");
2675 else
2676 printk(" ");
2677 }
2678 if (cnt % 16)
2679 ql_dbg(level, vha, id, "\n");
2680 }
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