drivers/scsi/qla2xxx/qla_dbg.h

   1 /******************************************************************************
   2  *                  QLOGIC LINUX SOFTWARE
   3  *
   4  * QLogic ISP2x00 device driver for Linux 2.6.x
   5  * Copyright (C) 2003-2005 QLogic Corporation
   6  * (www.qlogic.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the
  10  * Free Software Foundation; either version 2, or (at your option) any
  11  * later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  ******************************************************************************/
  19
  20 /*
  21  * Driver debug definitions.
  22  */
  23 /* #define QL_DEBUG_LEVEL_1  */ /* Output register accesses to COM1 */
  24 /* #define QL_DEBUG_LEVEL_2  */ /* Output error msgs to COM1 */
  25 /* #define QL_DEBUG_LEVEL_3  */ /* Output function trace msgs to COM1 */
  26 /* #define QL_DEBUG_LEVEL_4  */ /* Output NVRAM trace msgs to COM1 */
  27 /* #define QL_DEBUG_LEVEL_5  */ /* Output ring trace msgs to COM1 */
  28 /* #define QL_DEBUG_LEVEL_6  */ /* Output WATCHDOG timer trace to COM1 */
  29 /* #define QL_DEBUG_LEVEL_7  */ /* Output RISC load trace msgs to COM1 */
  30 /* #define QL_DEBUG_LEVEL_8  */ /* Output ring saturation msgs to COM1 */
  31 /* #define QL_DEBUG_LEVEL_9  */ /* Output IOCTL trace msgs */
  32 /* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */
  33 /* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */
  34 /* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */
  35 /* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */
  36 /* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */
  37 /*
  38  *  Local Macro Definitions.
  39  */
  40 #if defined(QL_DEBUG_LEVEL_1)  || defined(QL_DEBUG_LEVEL_2) || \
  41     defined(QL_DEBUG_LEVEL_3)  || defined(QL_DEBUG_LEVEL_4) || \
  42     defined(QL_DEBUG_LEVEL_5)  || defined(QL_DEBUG_LEVEL_6) || \
  43     defined(QL_DEBUG_LEVEL_7)  || defined(QL_DEBUG_LEVEL_8) || \
  44     defined(QL_DEBUG_LEVEL_9)  || defined(QL_DEBUG_LEVEL_10) || \
  45     defined(QL_DEBUG_LEVEL_11) || defined(QL_DEBUG_LEVEL_12) || \
  46     defined(QL_DEBUG_LEVEL_13) || defined(QL_DEBUG_LEVEL_14)
  47     #define QL_DEBUG_ROUTINES
  48 #endif
  49
  50 /*
  51 * Macros use for debugging the driver.
  52 */
  53 #undef ENTER_TRACE
  54 #if defined(ENTER_TRACE)
  55 #define ENTER(x)        do { printk("qla2100 : Entering %s()\n", x); } while (0)
  56 #define LEAVE(x)        do { printk("qla2100 : Leaving %s()\n", x);  } while (0)
  57 #define ENTER_INTR(x)   do { printk("qla2100 : Entering %s()\n", x); } while (0)
  58 #define LEAVE_INTR(x)   do { printk("qla2100 : Leaving %s()\n", x);  } while (0)
  59 #else
  60 #define ENTER(x)        do {} while (0)
  61 #define LEAVE(x)        do {} while (0)
  62 #define ENTER_INTR(x)   do {} while (0)
  63 #define LEAVE_INTR(x)   do {} while (0)
  64 #endif
  65
  66 #if  DEBUG_QLA2100
  67 #define DEBUG(x)        do {x;} while (0);
  68 #else
  69 #define DEBUG(x)        do {} while (0);
  70 #endif
  71
  72 #if defined(QL_DEBUG_LEVEL_1)
  73 #define DEBUG1(x)       do {x;} while (0);
  74 #else
  75 #define DEBUG1(x)       do {} while (0);
  76 #endif
  77
  78 #if defined(QL_DEBUG_LEVEL_2)
  79 #define DEBUG2(x)       do {x;} while (0);
  80 #define DEBUG2_3(x)     do {x;} while (0);
  81 #define DEBUG2_3_11(x)  do {x;} while (0);
  82 #define DEBUG2_9_10(x)    do {x;} while (0);
  83 #define DEBUG2_11(x)    do {x;} while (0);
  84 #define DEBUG2_13(x)    do {x;} while (0);
  85 #else
  86 #define DEBUG2(x)       do {} while (0);
  87 #endif
  88
  89 #if defined(QL_DEBUG_LEVEL_3)
  90 #define DEBUG3(x)       do {x;} while (0);
  91 #define DEBUG2_3(x)     do {x;} while (0);
  92 #define DEBUG2_3_11(x)  do {x;} while (0);
  93 #define DEBUG3_11(x)    do {x;} while (0);
  94 #else
  95 #define DEBUG3(x)       do {} while (0);
  96   #if !defined(QL_DEBUG_LEVEL_2)
  97   #define DEBUG2_3(x)   do {} while (0);
  98   #endif
  99 #endif
 100
 101 #if defined(QL_DEBUG_LEVEL_4)
 102 #define DEBUG4(x)       do {x;} while (0);
 103 #else
 104 #define DEBUG4(x)       do {} while (0);
 105 #endif
 106
 107 #if defined(QL_DEBUG_LEVEL_5)
 108 #define DEBUG5(x)          do {x;} while (0);
 109 #else
 110 #define DEBUG5(x)       do {} while (0);
 111 #endif
 112
 113 #if defined(QL_DEBUG_LEVEL_7)
 114 #define DEBUG7(x)          do {x;} while (0);
 115 #else
 116 #define DEBUG7(x)          do {} while (0);
 117 #endif
 118
 119 #if defined(QL_DEBUG_LEVEL_9)
 120 #define DEBUG9(x)       do {x;} while (0);
 121 #define DEBUG9_10(x)    do {x;} while (0);
 122 #define DEBUG2_9_10(x)  do {x;} while (0);
 123 #else
 124 #define DEBUG9(x)       do {} while (0);
 125 #endif
 126
 127 #if defined(QL_DEBUG_LEVEL_10)
 128 #define DEBUG10(x)      do {x;} while (0);
 129 #define DEBUG2_9_10(x)  do {x;} while (0);
 130 #define DEBUG9_10(x)    do {x;} while (0);
 131 #else
 132 #define DEBUG10(x)      do {} while (0);
 133   #if !defined(DEBUG2_9_10)
 134   #define DEBUG2_9_10(x)        do {} while (0);
 135   #endif
 136   #if !defined(DEBUG9_10)
 137   #define DEBUG9_10(x)  do {} while (0);
 138   #endif
 139 #endif
 140
 141 #if defined(QL_DEBUG_LEVEL_11)
 142 #define DEBUG11(x)      do{x;} while(0);
 143 #if !defined(DEBUG2_11)
 144 #define DEBUG2_11(x)    do{x;} while(0);
 145 #endif
 146 #if !defined(DEBUG2_3_11)
 147 #define DEBUG2_3_11(x)  do{x;} while(0);
 148 #endif
 149 #if !defined(DEBUG3_11)
 150 #define DEBUG3_11(x)    do{x;} while(0);
 151 #endif
 152 #else
 153 #define DEBUG11(x)      do{} while(0);
 154   #if !defined(QL_DEBUG_LEVEL_2)
 155   #define DEBUG2_11(x)  do{} while(0);
 156     #if !defined(QL_DEBUG_LEVEL_3)
 157     #define DEBUG2_3_11(x) do{} while(0);
 158     #endif
 159   #endif
 160   #if !defined(QL_DEBUG_LEVEL_3)
 161   #define DEBUG3_11(x)  do{} while(0);
 162   #endif
 163 #endif
 164
 165 #if defined(QL_DEBUG_LEVEL_12)
 166 #define DEBUG12(x)      do {x;} while (0);
 167 #else
 168 #define DEBUG12(x)      do {} while (0);
 169 #endif
 170
 171 #if defined(QL_DEBUG_LEVEL_13)
 172 #define DEBUG13(x)      do {x;} while (0)
 173 #if !defined(DEBUG2_13)
 174 #define DEBUG2_13(x)    do {x;} while(0)
 175 #endif
 176 #else
 177 #define DEBUG13(x)      do {} while (0)
 178 #if !defined(QL_DEBUG_LEVEL_2)
 179 #define DEBUG2_13(x)    do {} while(0)
 180 #endif
 181 #endif
 182
 183 #if defined(QL_DEBUG_LEVEL_14)
 184 #define DEBUG14(x)      do {x;} while (0)
 185 #else
 186 #define DEBUG14(x)      do {} while (0)
 187 #endif
 188
 189 /*
 190  * Firmware Dump structure definition
 191  */
 192 #define FW_DUMP_SIZE_128K       0xBC000
 193 #define FW_DUMP_SIZE_512K       0x2FC000
 194 #define FW_DUMP_SIZE_1M         0x5FC000
 195
 196 struct qla2300_fw_dump {
 197         uint16_t hccr;
 198         uint16_t pbiu_reg[8];
 199         uint16_t risc_host_reg[8];
 200         uint16_t mailbox_reg[32];
 201         uint16_t resp_dma_reg[32];
 202         uint16_t dma_reg[48];
 203         uint16_t risc_hdw_reg[16];
 204         uint16_t risc_gp0_reg[16];
 205         uint16_t risc_gp1_reg[16];
 206         uint16_t risc_gp2_reg[16];
 207         uint16_t risc_gp3_reg[16];
 208         uint16_t risc_gp4_reg[16];
 209         uint16_t risc_gp5_reg[16];
 210         uint16_t risc_gp6_reg[16];
 211         uint16_t risc_gp7_reg[16];
 212         uint16_t frame_buf_hdw_reg[64];
 213         uint16_t fpm_b0_reg[64];
 214         uint16_t fpm_b1_reg[64];
 215         uint16_t risc_ram[0xf800];
 216         uint16_t stack_ram[0x1000];
 217         uint16_t data_ram[1];
 218 };
 219
 220 struct qla2100_fw_dump {
 221         uint16_t hccr;
 222         uint16_t pbiu_reg[8];
 223         uint16_t mailbox_reg[32];
 224         uint16_t dma_reg[48];
 225         uint16_t risc_hdw_reg[16];
 226         uint16_t risc_gp0_reg[16];
 227         uint16_t risc_gp1_reg[16];
 228         uint16_t risc_gp2_reg[16];
 229         uint16_t risc_gp3_reg[16];
 230         uint16_t risc_gp4_reg[16];
 231         uint16_t risc_gp5_reg[16];
 232         uint16_t risc_gp6_reg[16];
 233         uint16_t risc_gp7_reg[16];
 234         uint16_t frame_buf_hdw_reg[16];
 235         uint16_t fpm_b0_reg[64];
 236         uint16_t fpm_b1_reg[64];
 237         uint16_t risc_ram[0xf000];
 238 };
 239
 240 #define FW_DUMP_SIZE_24XX       0x2B0000
 241
 242 struct qla24xx_fw_dump {
 243         uint32_t hccr;
 244         uint32_t host_reg[32];
 245         uint16_t mailbox_reg[32];
 246         uint32_t xseq_gp_reg[128];
 247         uint32_t xseq_0_reg[16];
 248         uint32_t xseq_1_reg[16];
 249         uint32_t rseq_gp_reg[128];
 250         uint32_t rseq_0_reg[16];
 251         uint32_t rseq_1_reg[16];
 252         uint32_t rseq_2_reg[16];
 253         uint32_t cmd_dma_reg[16];
 254         uint32_t req0_dma_reg[15];
 255         uint32_t resp0_dma_reg[15];
 256         uint32_t req1_dma_reg[15];
 257         uint32_t xmt0_dma_reg[32];
 258         uint32_t xmt1_dma_reg[32];
 259         uint32_t xmt2_dma_reg[32];
 260         uint32_t xmt3_dma_reg[32];
 261         uint32_t xmt4_dma_reg[32];
 262         uint32_t xmt_data_dma_reg[16];
 263         uint32_t rcvt0_data_dma_reg[32];
 264         uint32_t rcvt1_data_dma_reg[32];
 265         uint32_t risc_gp_reg[128];
 266         uint32_t shadow_reg[7];
 267         uint32_t lmc_reg[112];
 268         uint32_t fpm_hdw_reg[192];
 269         uint32_t fb_hdw_reg[176];
 270         uint32_t code_ram[0x2000];
 271         uint32_t ext_mem[1];
 272 };