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[mirror_ubuntu-artful-kernel.git] / drivers / scsi / qla2xxx / qla_def.h
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34 #include <scsi/scsi_bsg_fc.h>
35
36 #include "qla_bsg.h"
37 #include "qla_nx.h"
38 #include "qla_nx2.h"
39 #define QLA2XXX_DRIVER_NAME "qla2xxx"
40 #define QLA2XXX_APIDEV "ql2xapidev"
41 #define QLA2XXX_MANUFACTURER "QLogic Corporation"
42
43 /*
44 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
45 * but that's fine as we don't look at the last 24 ones for
46 * ISP2100 HBAs.
47 */
48 #define MAILBOX_REGISTER_COUNT_2100 8
49 #define MAILBOX_REGISTER_COUNT_2200 24
50 #define MAILBOX_REGISTER_COUNT 32
51
52 #define QLA2200A_RISC_ROM_VER 4
53 #define FPM_2300 6
54 #define FPM_2310 7
55
56 #include "qla_settings.h"
57
58 /*
59 * Data bit definitions
60 */
61 #define BIT_0 0x1
62 #define BIT_1 0x2
63 #define BIT_2 0x4
64 #define BIT_3 0x8
65 #define BIT_4 0x10
66 #define BIT_5 0x20
67 #define BIT_6 0x40
68 #define BIT_7 0x80
69 #define BIT_8 0x100
70 #define BIT_9 0x200
71 #define BIT_10 0x400
72 #define BIT_11 0x800
73 #define BIT_12 0x1000
74 #define BIT_13 0x2000
75 #define BIT_14 0x4000
76 #define BIT_15 0x8000
77 #define BIT_16 0x10000
78 #define BIT_17 0x20000
79 #define BIT_18 0x40000
80 #define BIT_19 0x80000
81 #define BIT_20 0x100000
82 #define BIT_21 0x200000
83 #define BIT_22 0x400000
84 #define BIT_23 0x800000
85 #define BIT_24 0x1000000
86 #define BIT_25 0x2000000
87 #define BIT_26 0x4000000
88 #define BIT_27 0x8000000
89 #define BIT_28 0x10000000
90 #define BIT_29 0x20000000
91 #define BIT_30 0x40000000
92 #define BIT_31 0x80000000
93
94 #define LSB(x) ((uint8_t)(x))
95 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
96
97 #define LSW(x) ((uint16_t)(x))
98 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
99
100 #define LSD(x) ((uint32_t)((uint64_t)(x)))
101 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
102
103 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
104
105 /*
106 * I/O register
107 */
108
109 #define RD_REG_BYTE(addr) readb(addr)
110 #define RD_REG_WORD(addr) readw(addr)
111 #define RD_REG_DWORD(addr) readl(addr)
112 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
113 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
114 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
115 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
116 #define WRT_REG_WORD(addr, data) writew(data,addr)
117 #define WRT_REG_DWORD(addr, data) writel(data,addr)
118
119 /*
120 * ISP83XX specific remote register addresses
121 */
122 #define QLA83XX_LED_PORT0 0x00201320
123 #define QLA83XX_LED_PORT1 0x00201328
124 #define QLA83XX_IDC_DEV_STATE 0x22102384
125 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
126 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
127 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
128 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
129 #define QLA83XX_IDC_CONTROL 0x22102390
130 #define QLA83XX_IDC_AUDIT 0x22102394
131 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
132 #define QLA83XX_DRIVER_LOCKID 0x22102104
133 #define QLA83XX_DRIVER_LOCK 0x8111c028
134 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
135 #define QLA83XX_FLASH_LOCKID 0x22102100
136 #define QLA83XX_FLASH_LOCK 0x8111c010
137 #define QLA83XX_FLASH_UNLOCK 0x8111c014
138 #define QLA83XX_DEV_PARTINFO1 0x221023e0
139 #define QLA83XX_DEV_PARTINFO2 0x221023e4
140 #define QLA83XX_FW_HEARTBEAT 0x221020b0
141 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
142 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
143
144 /* 83XX: Macros defining 8200 AEN Reason codes */
145 #define IDC_DEVICE_STATE_CHANGE BIT_0
146 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
147 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
148 #define IDC_HEARTBEAT_FAILURE BIT_3
149
150 /* 83XX: Macros defining 8200 AEN Error-levels */
151 #define ERR_LEVEL_NON_FATAL 0x1
152 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
153 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
154
155 /* 83XX: Macros for IDC Version */
156 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
157 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
158
159 /* 83XX: Macros for scheduling dpc tasks */
160 #define QLA83XX_NIC_CORE_RESET 0x1
161 #define QLA83XX_IDC_STATE_HANDLER 0x2
162 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
163
164 /* 83XX: Macros for defining IDC-Control bits */
165 #define QLA83XX_IDC_RESET_DISABLED BIT_0
166 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
167
168 /* 83XX: Macros for different timeouts */
169 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
170 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
171 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
172
173 /* 83XX: Macros for defining class in DEV-Partition Info register */
174 #define QLA83XX_CLASS_TYPE_NONE 0x0
175 #define QLA83XX_CLASS_TYPE_NIC 0x1
176 #define QLA83XX_CLASS_TYPE_FCOE 0x2
177 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
178
179 /* 83XX: Macros for IDC Lock-Recovery stages */
180 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
181 * lock-recovery
182 */
183 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
184
185 /* 83XX: Macros for IDC Audit type */
186 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
187 * dev-state change to NEED-RESET
188 * or NEED-QUIESCENT
189 */
190 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
191 * reset-recovery completion is
192 * second
193 */
194 /* ISP2031: Values for laser on/off */
195 #define PORT_0_2031 0x00201340
196 #define PORT_1_2031 0x00201350
197 #define LASER_ON_2031 0x01800100
198 #define LASER_OFF_2031 0x01800180
199
200 /*
201 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
202 * 133Mhz slot.
203 */
204 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
205 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
206
207 /*
208 * Fibre Channel device definitions.
209 */
210 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
211 #define MAX_FIBRE_DEVICES_2100 512
212 #define MAX_FIBRE_DEVICES_2400 2048
213 #define MAX_FIBRE_DEVICES_LOOP 128
214 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
215 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
216 #define MAX_FIBRE_LUNS 0xFFFF
217 #define MAX_HOST_COUNT 16
218
219 /*
220 * Host adapter default definitions.
221 */
222 #define MAX_BUSES 1 /* We only have one bus today */
223 #define MIN_LUNS 8
224 #define MAX_LUNS MAX_FIBRE_LUNS
225 #define MAX_CMDS_PER_LUN 255
226
227 /*
228 * Fibre Channel device definitions.
229 */
230 #define SNS_LAST_LOOP_ID_2100 0xfe
231 #define SNS_LAST_LOOP_ID_2300 0x7ff
232
233 #define LAST_LOCAL_LOOP_ID 0x7d
234 #define SNS_FL_PORT 0x7e
235 #define FABRIC_CONTROLLER 0x7f
236 #define SIMPLE_NAME_SERVER 0x80
237 #define SNS_FIRST_LOOP_ID 0x81
238 #define MANAGEMENT_SERVER 0xfe
239 #define BROADCAST 0xff
240
241 /*
242 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
243 * valid range of an N-PORT id is 0 through 0x7ef.
244 */
245 #define NPH_LAST_HANDLE 0x7ef
246 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
247 #define NPH_SNS 0x7fc /* FFFFFC */
248 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
249 #define NPH_F_PORT 0x7fe /* FFFFFE */
250 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
251
252 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
253 #include "qla_fw.h"
254 /*
255 * Timeout timer counts in seconds
256 */
257 #define PORT_RETRY_TIME 1
258 #define LOOP_DOWN_TIMEOUT 60
259 #define LOOP_DOWN_TIME 255 /* 240 */
260 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
261
262 #define DEFAULT_OUTSTANDING_COMMANDS 4096
263 #define MIN_OUTSTANDING_COMMANDS 128
264
265 /* ISP request and response entry counts (37-65535) */
266 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
267 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
268 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
269 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
270 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
271 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
272 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
273 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
274 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
275 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
276 #define EXTENDED_EXCH_ENTRY_CNT 32768 /* Entries for offload case */
277
278 struct req_que;
279 struct qla_tgt_sess;
280
281 /*
282 * SCSI Request Block
283 */
284 struct srb_cmd {
285 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
286 uint32_t request_sense_length;
287 uint32_t fw_sense_length;
288 uint8_t *request_sense_ptr;
289 void *ctx;
290 };
291
292 /*
293 * SRB flag definitions
294 */
295 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
296 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
297 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
298 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
299 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
300
301 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
302 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
303
304 struct els_logo_payload {
305 uint8_t opcode;
306 uint8_t rsvd[3];
307 uint8_t s_id[3];
308 uint8_t rsvd1[1];
309 uint8_t wwpn[WWN_SIZE];
310 };
311
312 /*
313 * SRB extensions.
314 */
315 struct srb_iocb {
316 union {
317 struct {
318 uint16_t flags;
319 #define SRB_LOGIN_RETRIED BIT_0
320 #define SRB_LOGIN_COND_PLOGI BIT_1
321 #define SRB_LOGIN_SKIP_PRLI BIT_2
322 uint16_t data[2];
323 } logio;
324 struct {
325 #define ELS_DCMD_TIMEOUT 20
326 #define ELS_DCMD_LOGO 0x5
327 uint32_t flags;
328 uint32_t els_cmd;
329 struct completion comp;
330 struct els_logo_payload *els_logo_pyld;
331 dma_addr_t els_logo_pyld_dma;
332 } els_logo;
333 struct {
334 /*
335 * Values for flags field below are as
336 * defined in tsk_mgmt_entry struct
337 * for control_flags field in qla_fw.h.
338 */
339 uint64_t lun;
340 uint32_t flags;
341 uint32_t data;
342 struct completion comp;
343 __le16 comp_status;
344 } tmf;
345 struct {
346 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
347 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
348 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
349 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
350 #define FXDISC_TIMEOUT 20
351 uint8_t flags;
352 uint32_t req_len;
353 uint32_t rsp_len;
354 void *req_addr;
355 void *rsp_addr;
356 dma_addr_t req_dma_handle;
357 dma_addr_t rsp_dma_handle;
358 __le32 adapter_id;
359 __le32 adapter_id_hi;
360 __le16 req_func_type;
361 __le32 req_data;
362 __le32 req_data_extra;
363 __le32 result;
364 __le32 seq_number;
365 __le16 fw_flags;
366 struct completion fxiocb_comp;
367 __le32 reserved_0;
368 uint8_t reserved_1;
369 } fxiocb;
370 struct {
371 uint32_t cmd_hndl;
372 __le16 comp_status;
373 struct completion comp;
374 } abt;
375 } u;
376
377 struct timer_list timer;
378 void (*timeout)(void *);
379 };
380
381 /* Values for srb_ctx type */
382 #define SRB_LOGIN_CMD 1
383 #define SRB_LOGOUT_CMD 2
384 #define SRB_ELS_CMD_RPT 3
385 #define SRB_ELS_CMD_HST 4
386 #define SRB_CT_CMD 5
387 #define SRB_ADISC_CMD 6
388 #define SRB_TM_CMD 7
389 #define SRB_SCSI_CMD 8
390 #define SRB_BIDI_CMD 9
391 #define SRB_FXIOCB_DCMD 10
392 #define SRB_FXIOCB_BCMD 11
393 #define SRB_ABT_CMD 12
394 #define SRB_ELS_DCMD 13
395
396 typedef struct srb {
397 atomic_t ref_count;
398 struct fc_port *fcport;
399 uint32_t handle;
400 uint16_t flags;
401 uint16_t type;
402 char *name;
403 int iocbs;
404 struct qla_qpair *qpair;
405 union {
406 struct srb_iocb iocb_cmd;
407 struct bsg_job *bsg_job;
408 struct srb_cmd scmd;
409 } u;
410 void (*done)(void *, void *, int);
411 void (*free)(void *, void *);
412 } srb_t;
413
414 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
415 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
416 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
417
418 #define GET_CMD_SENSE_LEN(sp) \
419 (sp->u.scmd.request_sense_length)
420 #define SET_CMD_SENSE_LEN(sp, len) \
421 (sp->u.scmd.request_sense_length = len)
422 #define GET_CMD_SENSE_PTR(sp) \
423 (sp->u.scmd.request_sense_ptr)
424 #define SET_CMD_SENSE_PTR(sp, ptr) \
425 (sp->u.scmd.request_sense_ptr = ptr)
426 #define GET_FW_SENSE_LEN(sp) \
427 (sp->u.scmd.fw_sense_length)
428 #define SET_FW_SENSE_LEN(sp, len) \
429 (sp->u.scmd.fw_sense_length = len)
430
431 struct msg_echo_lb {
432 dma_addr_t send_dma;
433 dma_addr_t rcv_dma;
434 uint16_t req_sg_cnt;
435 uint16_t rsp_sg_cnt;
436 uint16_t options;
437 uint32_t transfer_size;
438 uint32_t iteration_count;
439 };
440
441 /*
442 * ISP I/O Register Set structure definitions.
443 */
444 struct device_reg_2xxx {
445 uint16_t flash_address; /* Flash BIOS address */
446 uint16_t flash_data; /* Flash BIOS data */
447 uint16_t unused_1[1]; /* Gap */
448 uint16_t ctrl_status; /* Control/Status */
449 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
450 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
451 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
452
453 uint16_t ictrl; /* Interrupt control */
454 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
455 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
456
457 uint16_t istatus; /* Interrupt status */
458 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
459
460 uint16_t semaphore; /* Semaphore */
461 uint16_t nvram; /* NVRAM register. */
462 #define NVR_DESELECT 0
463 #define NVR_BUSY BIT_15
464 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
465 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
466 #define NVR_DATA_IN BIT_3
467 #define NVR_DATA_OUT BIT_2
468 #define NVR_SELECT BIT_1
469 #define NVR_CLOCK BIT_0
470
471 #define NVR_WAIT_CNT 20000
472
473 union {
474 struct {
475 uint16_t mailbox0;
476 uint16_t mailbox1;
477 uint16_t mailbox2;
478 uint16_t mailbox3;
479 uint16_t mailbox4;
480 uint16_t mailbox5;
481 uint16_t mailbox6;
482 uint16_t mailbox7;
483 uint16_t unused_2[59]; /* Gap */
484 } __attribute__((packed)) isp2100;
485 struct {
486 /* Request Queue */
487 uint16_t req_q_in; /* In-Pointer */
488 uint16_t req_q_out; /* Out-Pointer */
489 /* Response Queue */
490 uint16_t rsp_q_in; /* In-Pointer */
491 uint16_t rsp_q_out; /* Out-Pointer */
492
493 /* RISC to Host Status */
494 uint32_t host_status;
495 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
496 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
497
498 /* Host to Host Semaphore */
499 uint16_t host_semaphore;
500 uint16_t unused_3[17]; /* Gap */
501 uint16_t mailbox0;
502 uint16_t mailbox1;
503 uint16_t mailbox2;
504 uint16_t mailbox3;
505 uint16_t mailbox4;
506 uint16_t mailbox5;
507 uint16_t mailbox6;
508 uint16_t mailbox7;
509 uint16_t mailbox8;
510 uint16_t mailbox9;
511 uint16_t mailbox10;
512 uint16_t mailbox11;
513 uint16_t mailbox12;
514 uint16_t mailbox13;
515 uint16_t mailbox14;
516 uint16_t mailbox15;
517 uint16_t mailbox16;
518 uint16_t mailbox17;
519 uint16_t mailbox18;
520 uint16_t mailbox19;
521 uint16_t mailbox20;
522 uint16_t mailbox21;
523 uint16_t mailbox22;
524 uint16_t mailbox23;
525 uint16_t mailbox24;
526 uint16_t mailbox25;
527 uint16_t mailbox26;
528 uint16_t mailbox27;
529 uint16_t mailbox28;
530 uint16_t mailbox29;
531 uint16_t mailbox30;
532 uint16_t mailbox31;
533 uint16_t fb_cmd;
534 uint16_t unused_4[10]; /* Gap */
535 } __attribute__((packed)) isp2300;
536 } u;
537
538 uint16_t fpm_diag_config;
539 uint16_t unused_5[0x4]; /* Gap */
540 uint16_t risc_hw;
541 uint16_t unused_5_1; /* Gap */
542 uint16_t pcr; /* Processor Control Register. */
543 uint16_t unused_6[0x5]; /* Gap */
544 uint16_t mctr; /* Memory Configuration and Timing. */
545 uint16_t unused_7[0x3]; /* Gap */
546 uint16_t fb_cmd_2100; /* Unused on 23XX */
547 uint16_t unused_8[0x3]; /* Gap */
548 uint16_t hccr; /* Host command & control register. */
549 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
550 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
551 /* HCCR commands */
552 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
553 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
554 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
555 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
556 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
557 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
558 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
559 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
560
561 uint16_t unused_9[5]; /* Gap */
562 uint16_t gpiod; /* GPIO Data register. */
563 uint16_t gpioe; /* GPIO Enable register. */
564 #define GPIO_LED_MASK 0x00C0
565 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
566 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
567 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
568 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
569 #define GPIO_LED_ALL_OFF 0x0000
570 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
571 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
572
573 union {
574 struct {
575 uint16_t unused_10[8]; /* Gap */
576 uint16_t mailbox8;
577 uint16_t mailbox9;
578 uint16_t mailbox10;
579 uint16_t mailbox11;
580 uint16_t mailbox12;
581 uint16_t mailbox13;
582 uint16_t mailbox14;
583 uint16_t mailbox15;
584 uint16_t mailbox16;
585 uint16_t mailbox17;
586 uint16_t mailbox18;
587 uint16_t mailbox19;
588 uint16_t mailbox20;
589 uint16_t mailbox21;
590 uint16_t mailbox22;
591 uint16_t mailbox23; /* Also probe reg. */
592 } __attribute__((packed)) isp2200;
593 } u_end;
594 };
595
596 struct device_reg_25xxmq {
597 uint32_t req_q_in;
598 uint32_t req_q_out;
599 uint32_t rsp_q_in;
600 uint32_t rsp_q_out;
601 uint32_t atio_q_in;
602 uint32_t atio_q_out;
603 };
604
605
606 struct device_reg_fx00 {
607 uint32_t mailbox0; /* 00 */
608 uint32_t mailbox1; /* 04 */
609 uint32_t mailbox2; /* 08 */
610 uint32_t mailbox3; /* 0C */
611 uint32_t mailbox4; /* 10 */
612 uint32_t mailbox5; /* 14 */
613 uint32_t mailbox6; /* 18 */
614 uint32_t mailbox7; /* 1C */
615 uint32_t mailbox8; /* 20 */
616 uint32_t mailbox9; /* 24 */
617 uint32_t mailbox10; /* 28 */
618 uint32_t mailbox11;
619 uint32_t mailbox12;
620 uint32_t mailbox13;
621 uint32_t mailbox14;
622 uint32_t mailbox15;
623 uint32_t mailbox16;
624 uint32_t mailbox17;
625 uint32_t mailbox18;
626 uint32_t mailbox19;
627 uint32_t mailbox20;
628 uint32_t mailbox21;
629 uint32_t mailbox22;
630 uint32_t mailbox23;
631 uint32_t mailbox24;
632 uint32_t mailbox25;
633 uint32_t mailbox26;
634 uint32_t mailbox27;
635 uint32_t mailbox28;
636 uint32_t mailbox29;
637 uint32_t mailbox30;
638 uint32_t mailbox31;
639 uint32_t aenmailbox0;
640 uint32_t aenmailbox1;
641 uint32_t aenmailbox2;
642 uint32_t aenmailbox3;
643 uint32_t aenmailbox4;
644 uint32_t aenmailbox5;
645 uint32_t aenmailbox6;
646 uint32_t aenmailbox7;
647 /* Request Queue. */
648 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */
649 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */
650 /* Response Queue. */
651 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */
652 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */
653 /* Init values shadowed on FW Up Event */
654 uint32_t initval0; /* B0 */
655 uint32_t initval1; /* B4 */
656 uint32_t initval2; /* B8 */
657 uint32_t initval3; /* BC */
658 uint32_t initval4; /* C0 */
659 uint32_t initval5; /* C4 */
660 uint32_t initval6; /* C8 */
661 uint32_t initval7; /* CC */
662 uint32_t fwheartbeat; /* D0 */
663 uint32_t pseudoaen; /* D4 */
664 };
665
666
667
668 typedef union {
669 struct device_reg_2xxx isp;
670 struct device_reg_24xx isp24;
671 struct device_reg_25xxmq isp25mq;
672 struct device_reg_82xx isp82;
673 struct device_reg_fx00 ispfx00;
674 } __iomem device_reg_t;
675
676 #define ISP_REQ_Q_IN(ha, reg) \
677 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
678 &(reg)->u.isp2100.mailbox4 : \
679 &(reg)->u.isp2300.req_q_in)
680 #define ISP_REQ_Q_OUT(ha, reg) \
681 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
682 &(reg)->u.isp2100.mailbox4 : \
683 &(reg)->u.isp2300.req_q_out)
684 #define ISP_RSP_Q_IN(ha, reg) \
685 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
686 &(reg)->u.isp2100.mailbox5 : \
687 &(reg)->u.isp2300.rsp_q_in)
688 #define ISP_RSP_Q_OUT(ha, reg) \
689 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
690 &(reg)->u.isp2100.mailbox5 : \
691 &(reg)->u.isp2300.rsp_q_out)
692
693 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
694 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
695
696 #define MAILBOX_REG(ha, reg, num) \
697 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
698 (num < 8 ? \
699 &(reg)->u.isp2100.mailbox0 + (num) : \
700 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
701 &(reg)->u.isp2300.mailbox0 + (num))
702 #define RD_MAILBOX_REG(ha, reg, num) \
703 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
704 #define WRT_MAILBOX_REG(ha, reg, num, data) \
705 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
706
707 #define FB_CMD_REG(ha, reg) \
708 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
709 &(reg)->fb_cmd_2100 : \
710 &(reg)->u.isp2300.fb_cmd)
711 #define RD_FB_CMD_REG(ha, reg) \
712 RD_REG_WORD(FB_CMD_REG(ha, reg))
713 #define WRT_FB_CMD_REG(ha, reg, data) \
714 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
715
716 typedef struct {
717 uint32_t out_mb; /* outbound from driver */
718 uint32_t in_mb; /* Incoming from RISC */
719 uint16_t mb[MAILBOX_REGISTER_COUNT];
720 long buf_size;
721 void *bufp;
722 uint32_t tov;
723 uint8_t flags;
724 #define MBX_DMA_IN BIT_0
725 #define MBX_DMA_OUT BIT_1
726 #define IOCTL_CMD BIT_2
727 } mbx_cmd_t;
728
729 struct mbx_cmd_32 {
730 uint32_t out_mb; /* outbound from driver */
731 uint32_t in_mb; /* Incoming from RISC */
732 uint32_t mb[MAILBOX_REGISTER_COUNT];
733 long buf_size;
734 void *bufp;
735 uint32_t tov;
736 uint8_t flags;
737 #define MBX_DMA_IN BIT_0
738 #define MBX_DMA_OUT BIT_1
739 #define IOCTL_CMD BIT_2
740 };
741
742
743 #define MBX_TOV_SECONDS 30
744
745 /*
746 * ISP product identification definitions in mailboxes after reset.
747 */
748 #define PROD_ID_1 0x4953
749 #define PROD_ID_2 0x0000
750 #define PROD_ID_2a 0x5020
751 #define PROD_ID_3 0x2020
752
753 /*
754 * ISP mailbox Self-Test status codes
755 */
756 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
757 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
758 #define MBS_BUSY 4 /* Busy. */
759
760 /*
761 * ISP mailbox command complete status codes
762 */
763 #define MBS_COMMAND_COMPLETE 0x4000
764 #define MBS_INVALID_COMMAND 0x4001
765 #define MBS_HOST_INTERFACE_ERROR 0x4002
766 #define MBS_TEST_FAILED 0x4003
767 #define MBS_COMMAND_ERROR 0x4005
768 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
769 #define MBS_PORT_ID_USED 0x4007
770 #define MBS_LOOP_ID_USED 0x4008
771 #define MBS_ALL_IDS_IN_USE 0x4009
772 #define MBS_NOT_LOGGED_IN 0x400A
773 #define MBS_LINK_DOWN_ERROR 0x400B
774 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
775
776 /*
777 * ISP mailbox asynchronous event status codes
778 */
779 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
780 #define MBA_RESET 0x8001 /* Reset Detected. */
781 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
782 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
783 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
784 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
785 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
786 /* occurred. */
787 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
788 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
789 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
790 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
791 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
792 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
793 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
794 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
795 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
796 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
797 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
798 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
799 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
800 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
801 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
802 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
803 /* used. */
804 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
805 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
806 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
807 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
808 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
809 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
810 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
811 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
812 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
813 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
814 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
815 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
816 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
817 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
818 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
819 #define MBA_FW_STARTING 0x8051 /* Firmware starting */
820 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
821 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
822 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
823 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
824 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
825 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
826 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
827 Notification */
828 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
829 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
830 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
831 /* 83XX FCoE specific */
832 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
833
834 /* Interrupt type codes */
835 #define INTR_ROM_MB_SUCCESS 0x1
836 #define INTR_ROM_MB_FAILED 0x2
837 #define INTR_MB_SUCCESS 0x10
838 #define INTR_MB_FAILED 0x11
839 #define INTR_ASYNC_EVENT 0x12
840 #define INTR_RSP_QUE_UPDATE 0x13
841 #define INTR_RSP_QUE_UPDATE_83XX 0x14
842 #define INTR_ATIO_QUE_UPDATE 0x1C
843 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
844
845 /* ISP mailbox loopback echo diagnostic error code */
846 #define MBS_LB_RESET 0x17
847 /*
848 * Firmware options 1, 2, 3.
849 */
850 #define FO1_AE_ON_LIPF8 BIT_0
851 #define FO1_AE_ALL_LIP_RESET BIT_1
852 #define FO1_CTIO_RETRY BIT_3
853 #define FO1_DISABLE_LIP_F7_SW BIT_4
854 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
855 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
856 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
857 #define FO1_SET_EMPHASIS_SWING BIT_8
858 #define FO1_AE_AUTO_BYPASS BIT_9
859 #define FO1_ENABLE_PURE_IOCB BIT_10
860 #define FO1_AE_PLOGI_RJT BIT_11
861 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
862 #define FO1_AE_QUEUE_FULL BIT_13
863
864 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
865 #define FO2_REV_LOOPBACK BIT_1
866
867 #define FO3_ENABLE_EMERG_IOCB BIT_0
868 #define FO3_AE_RND_ERROR BIT_1
869
870 /* 24XX additional firmware options */
871 #define ADD_FO_COUNT 3
872 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
873 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
874
875 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
876
877 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
878
879 /*
880 * ISP mailbox commands
881 */
882 #define MBC_LOAD_RAM 1 /* Load RAM. */
883 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
884 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
885 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
886 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
887 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
888 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
889 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
890 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
891 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
892 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
893 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
894 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
895 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
896 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
897 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
898 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
899 #define MBC_RESET 0x18 /* Reset. */
900 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
901 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
902 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
903 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
904 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
905 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
906 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
907 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
908 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
909 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
910 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
911 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
912 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
913 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
914 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
915 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
916 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
917 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
918 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
919 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
920 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
921 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
922 #define MBC_DATA_RATE 0x5d /* Data Rate */
923 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
924 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
925 /* Initialization Procedure */
926 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
927 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
928 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
929 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
930 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
931 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
932 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
933 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
934 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
935 #define MBC_LIP_RESET 0x6c /* LIP reset. */
936 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
937 /* commandd. */
938 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
939 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
940 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
941 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
942 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
943 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
944 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
945 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
946 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
947 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
948 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
949
950 /*
951 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
952 * should be defined with MBC_MR_*
953 */
954 #define MBC_MR_DRV_SHUTDOWN 0x6A
955
956 /*
957 * ISP24xx mailbox commands
958 */
959 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
960 #define MBC_READ_SERDES 0x4 /* Read serdes word. */
961 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
962 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
963 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
964 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
965 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
966 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
967 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
968 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
969 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
970 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
971 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
972 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
973 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
974 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
975 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
976 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
977 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
978 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
979 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
980 #define MBC_PORT_RESET 0x120 /* Port Reset */
981 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
982 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
983
984 /*
985 * ISP81xx mailbox commands
986 */
987 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
988
989 /*
990 * ISP8044 mailbox commands
991 */
992 #define MBC_SET_GET_ETH_SERDES_REG 0x150
993 #define HCS_WRITE_SERDES 0x3
994 #define HCS_READ_SERDES 0x4
995
996 /* Firmware return data sizes */
997 #define FCAL_MAP_SIZE 128
998
999 /* Mailbox bit definitions for out_mb and in_mb */
1000 #define MBX_31 BIT_31
1001 #define MBX_30 BIT_30
1002 #define MBX_29 BIT_29
1003 #define MBX_28 BIT_28
1004 #define MBX_27 BIT_27
1005 #define MBX_26 BIT_26
1006 #define MBX_25 BIT_25
1007 #define MBX_24 BIT_24
1008 #define MBX_23 BIT_23
1009 #define MBX_22 BIT_22
1010 #define MBX_21 BIT_21
1011 #define MBX_20 BIT_20
1012 #define MBX_19 BIT_19
1013 #define MBX_18 BIT_18
1014 #define MBX_17 BIT_17
1015 #define MBX_16 BIT_16
1016 #define MBX_15 BIT_15
1017 #define MBX_14 BIT_14
1018 #define MBX_13 BIT_13
1019 #define MBX_12 BIT_12
1020 #define MBX_11 BIT_11
1021 #define MBX_10 BIT_10
1022 #define MBX_9 BIT_9
1023 #define MBX_8 BIT_8
1024 #define MBX_7 BIT_7
1025 #define MBX_6 BIT_6
1026 #define MBX_5 BIT_5
1027 #define MBX_4 BIT_4
1028 #define MBX_3 BIT_3
1029 #define MBX_2 BIT_2
1030 #define MBX_1 BIT_1
1031 #define MBX_0 BIT_0
1032
1033 #define RNID_TYPE_SET_VERSION 0x9
1034 #define RNID_TYPE_ASIC_TEMP 0xC
1035
1036 /*
1037 * Firmware state codes from get firmware state mailbox command
1038 */
1039 #define FSTATE_CONFIG_WAIT 0
1040 #define FSTATE_WAIT_AL_PA 1
1041 #define FSTATE_WAIT_LOGIN 2
1042 #define FSTATE_READY 3
1043 #define FSTATE_LOSS_OF_SYNC 4
1044 #define FSTATE_ERROR 5
1045 #define FSTATE_REINIT 6
1046 #define FSTATE_NON_PART 7
1047
1048 #define FSTATE_CONFIG_CORRECT 0
1049 #define FSTATE_P2P_RCV_LIP 1
1050 #define FSTATE_P2P_CHOOSE_LOOP 2
1051 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
1052 #define FSTATE_FATAL_ERROR 4
1053 #define FSTATE_LOOP_BACK_CONN 5
1054
1055 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1056 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1057 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1058 #define QLA27XX_PRIMARY_IMAGE 1
1059 #define QLA27XX_SECONDARY_IMAGE 2
1060
1061 /*
1062 * Port Database structure definition
1063 * Little endian except where noted.
1064 */
1065 #define PORT_DATABASE_SIZE 128 /* bytes */
1066 typedef struct {
1067 uint8_t options;
1068 uint8_t control;
1069 uint8_t master_state;
1070 uint8_t slave_state;
1071 uint8_t reserved[2];
1072 uint8_t hard_address;
1073 uint8_t reserved_1;
1074 uint8_t port_id[4];
1075 uint8_t node_name[WWN_SIZE];
1076 uint8_t port_name[WWN_SIZE];
1077 uint16_t execution_throttle;
1078 uint16_t execution_count;
1079 uint8_t reset_count;
1080 uint8_t reserved_2;
1081 uint16_t resource_allocation;
1082 uint16_t current_allocation;
1083 uint16_t queue_head;
1084 uint16_t queue_tail;
1085 uint16_t transmit_execution_list_next;
1086 uint16_t transmit_execution_list_previous;
1087 uint16_t common_features;
1088 uint16_t total_concurrent_sequences;
1089 uint16_t RO_by_information_category;
1090 uint8_t recipient;
1091 uint8_t initiator;
1092 uint16_t receive_data_size;
1093 uint16_t concurrent_sequences;
1094 uint16_t open_sequences_per_exchange;
1095 uint16_t lun_abort_flags;
1096 uint16_t lun_stop_flags;
1097 uint16_t stop_queue_head;
1098 uint16_t stop_queue_tail;
1099 uint16_t port_retry_timer;
1100 uint16_t next_sequence_id;
1101 uint16_t frame_count;
1102 uint16_t PRLI_payload_length;
1103 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1104 /* Bits 15-0 of word 0 */
1105 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1106 /* Bits 15-0 of word 3 */
1107 uint16_t loop_id;
1108 uint16_t extended_lun_info_list_pointer;
1109 uint16_t extended_lun_stop_list_pointer;
1110 } port_database_t;
1111
1112 /*
1113 * Port database slave/master states
1114 */
1115 #define PD_STATE_DISCOVERY 0
1116 #define PD_STATE_WAIT_DISCOVERY_ACK 1
1117 #define PD_STATE_PORT_LOGIN 2
1118 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1119 #define PD_STATE_PROCESS_LOGIN 4
1120 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1121 #define PD_STATE_PORT_LOGGED_IN 6
1122 #define PD_STATE_PORT_UNAVAILABLE 7
1123 #define PD_STATE_PROCESS_LOGOUT 8
1124 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1125 #define PD_STATE_PORT_LOGOUT 10
1126 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1127
1128
1129 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1130 #define QLA_ZIO_DISABLED 0
1131 #define QLA_ZIO_DEFAULT_TIMER 2
1132
1133 /*
1134 * ISP Initialization Control Block.
1135 * Little endian except where noted.
1136 */
1137 #define ICB_VERSION 1
1138 typedef struct {
1139 uint8_t version;
1140 uint8_t reserved_1;
1141
1142 /*
1143 * LSB BIT 0 = Enable Hard Loop Id
1144 * LSB BIT 1 = Enable Fairness
1145 * LSB BIT 2 = Enable Full-Duplex
1146 * LSB BIT 3 = Enable Fast Posting
1147 * LSB BIT 4 = Enable Target Mode
1148 * LSB BIT 5 = Disable Initiator Mode
1149 * LSB BIT 6 = Enable ADISC
1150 * LSB BIT 7 = Enable Target Inquiry Data
1151 *
1152 * MSB BIT 0 = Enable PDBC Notify
1153 * MSB BIT 1 = Non Participating LIP
1154 * MSB BIT 2 = Descending Loop ID Search
1155 * MSB BIT 3 = Acquire Loop ID in LIPA
1156 * MSB BIT 4 = Stop PortQ on Full Status
1157 * MSB BIT 5 = Full Login after LIP
1158 * MSB BIT 6 = Node Name Option
1159 * MSB BIT 7 = Ext IFWCB enable bit
1160 */
1161 uint8_t firmware_options[2];
1162
1163 uint16_t frame_payload_size;
1164 uint16_t max_iocb_allocation;
1165 uint16_t execution_throttle;
1166 uint8_t retry_count;
1167 uint8_t retry_delay; /* unused */
1168 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1169 uint16_t hard_address;
1170 uint8_t inquiry_data;
1171 uint8_t login_timeout;
1172 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1173
1174 uint16_t request_q_outpointer;
1175 uint16_t response_q_inpointer;
1176 uint16_t request_q_length;
1177 uint16_t response_q_length;
1178 uint32_t request_q_address[2];
1179 uint32_t response_q_address[2];
1180
1181 uint16_t lun_enables;
1182 uint8_t command_resource_count;
1183 uint8_t immediate_notify_resource_count;
1184 uint16_t timeout;
1185 uint8_t reserved_2[2];
1186
1187 /*
1188 * LSB BIT 0 = Timer Operation mode bit 0
1189 * LSB BIT 1 = Timer Operation mode bit 1
1190 * LSB BIT 2 = Timer Operation mode bit 2
1191 * LSB BIT 3 = Timer Operation mode bit 3
1192 * LSB BIT 4 = Init Config Mode bit 0
1193 * LSB BIT 5 = Init Config Mode bit 1
1194 * LSB BIT 6 = Init Config Mode bit 2
1195 * LSB BIT 7 = Enable Non part on LIHA failure
1196 *
1197 * MSB BIT 0 = Enable class 2
1198 * MSB BIT 1 = Enable ACK0
1199 * MSB BIT 2 =
1200 * MSB BIT 3 =
1201 * MSB BIT 4 = FC Tape Enable
1202 * MSB BIT 5 = Enable FC Confirm
1203 * MSB BIT 6 = Enable command queuing in target mode
1204 * MSB BIT 7 = No Logo On Link Down
1205 */
1206 uint8_t add_firmware_options[2];
1207
1208 uint8_t response_accumulation_timer;
1209 uint8_t interrupt_delay_timer;
1210
1211 /*
1212 * LSB BIT 0 = Enable Read xfr_rdy
1213 * LSB BIT 1 = Soft ID only
1214 * LSB BIT 2 =
1215 * LSB BIT 3 =
1216 * LSB BIT 4 = FCP RSP Payload [0]
1217 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1218 * LSB BIT 6 = Enable Out-of-Order frame handling
1219 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1220 *
1221 * MSB BIT 0 = Sbus enable - 2300
1222 * MSB BIT 1 =
1223 * MSB BIT 2 =
1224 * MSB BIT 3 =
1225 * MSB BIT 4 = LED mode
1226 * MSB BIT 5 = enable 50 ohm termination
1227 * MSB BIT 6 = Data Rate (2300 only)
1228 * MSB BIT 7 = Data Rate (2300 only)
1229 */
1230 uint8_t special_options[2];
1231
1232 uint8_t reserved_3[26];
1233 } init_cb_t;
1234
1235 /*
1236 * Get Link Status mailbox command return buffer.
1237 */
1238 #define GLSO_SEND_RPS BIT_0
1239 #define GLSO_USE_DID BIT_3
1240
1241 struct link_statistics {
1242 uint32_t link_fail_cnt;
1243 uint32_t loss_sync_cnt;
1244 uint32_t loss_sig_cnt;
1245 uint32_t prim_seq_err_cnt;
1246 uint32_t inval_xmit_word_cnt;
1247 uint32_t inval_crc_cnt;
1248 uint32_t lip_cnt;
1249 uint32_t link_up_cnt;
1250 uint32_t link_down_loop_init_tmo;
1251 uint32_t link_down_los;
1252 uint32_t link_down_loss_rcv_clk;
1253 uint32_t reserved0[5];
1254 uint32_t port_cfg_chg;
1255 uint32_t reserved1[11];
1256 uint32_t rsp_q_full;
1257 uint32_t atio_q_full;
1258 uint32_t drop_ae;
1259 uint32_t els_proto_err;
1260 uint32_t reserved2;
1261 uint32_t tx_frames;
1262 uint32_t rx_frames;
1263 uint32_t discarded_frames;
1264 uint32_t dropped_frames;
1265 uint32_t reserved3;
1266 uint32_t nos_rcvd;
1267 uint32_t reserved4[4];
1268 uint32_t tx_prjt;
1269 uint32_t rcv_exfail;
1270 uint32_t rcv_abts;
1271 uint32_t seq_frm_miss;
1272 uint32_t corr_err;
1273 uint32_t mb_rqst;
1274 uint32_t nport_full;
1275 uint32_t eofa;
1276 uint32_t reserved5;
1277 uint32_t fpm_recv_word_cnt_lo;
1278 uint32_t fpm_recv_word_cnt_hi;
1279 uint32_t fpm_disc_word_cnt_lo;
1280 uint32_t fpm_disc_word_cnt_hi;
1281 uint32_t fpm_xmit_word_cnt_lo;
1282 uint32_t fpm_xmit_word_cnt_hi;
1283 uint32_t reserved6[70];
1284 };
1285
1286 /*
1287 * NVRAM Command values.
1288 */
1289 #define NV_START_BIT BIT_2
1290 #define NV_WRITE_OP (BIT_26+BIT_24)
1291 #define NV_READ_OP (BIT_26+BIT_25)
1292 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1293 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1294 #define NV_DELAY_COUNT 10
1295
1296 /*
1297 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1298 */
1299 typedef struct {
1300 /*
1301 * NVRAM header
1302 */
1303 uint8_t id[4];
1304 uint8_t nvram_version;
1305 uint8_t reserved_0;
1306
1307 /*
1308 * NVRAM RISC parameter block
1309 */
1310 uint8_t parameter_block_version;
1311 uint8_t reserved_1;
1312
1313 /*
1314 * LSB BIT 0 = Enable Hard Loop Id
1315 * LSB BIT 1 = Enable Fairness
1316 * LSB BIT 2 = Enable Full-Duplex
1317 * LSB BIT 3 = Enable Fast Posting
1318 * LSB BIT 4 = Enable Target Mode
1319 * LSB BIT 5 = Disable Initiator Mode
1320 * LSB BIT 6 = Enable ADISC
1321 * LSB BIT 7 = Enable Target Inquiry Data
1322 *
1323 * MSB BIT 0 = Enable PDBC Notify
1324 * MSB BIT 1 = Non Participating LIP
1325 * MSB BIT 2 = Descending Loop ID Search
1326 * MSB BIT 3 = Acquire Loop ID in LIPA
1327 * MSB BIT 4 = Stop PortQ on Full Status
1328 * MSB BIT 5 = Full Login after LIP
1329 * MSB BIT 6 = Node Name Option
1330 * MSB BIT 7 = Ext IFWCB enable bit
1331 */
1332 uint8_t firmware_options[2];
1333
1334 uint16_t frame_payload_size;
1335 uint16_t max_iocb_allocation;
1336 uint16_t execution_throttle;
1337 uint8_t retry_count;
1338 uint8_t retry_delay; /* unused */
1339 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1340 uint16_t hard_address;
1341 uint8_t inquiry_data;
1342 uint8_t login_timeout;
1343 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1344
1345 /*
1346 * LSB BIT 0 = Timer Operation mode bit 0
1347 * LSB BIT 1 = Timer Operation mode bit 1
1348 * LSB BIT 2 = Timer Operation mode bit 2
1349 * LSB BIT 3 = Timer Operation mode bit 3
1350 * LSB BIT 4 = Init Config Mode bit 0
1351 * LSB BIT 5 = Init Config Mode bit 1
1352 * LSB BIT 6 = Init Config Mode bit 2
1353 * LSB BIT 7 = Enable Non part on LIHA failure
1354 *
1355 * MSB BIT 0 = Enable class 2
1356 * MSB BIT 1 = Enable ACK0
1357 * MSB BIT 2 =
1358 * MSB BIT 3 =
1359 * MSB BIT 4 = FC Tape Enable
1360 * MSB BIT 5 = Enable FC Confirm
1361 * MSB BIT 6 = Enable command queuing in target mode
1362 * MSB BIT 7 = No Logo On Link Down
1363 */
1364 uint8_t add_firmware_options[2];
1365
1366 uint8_t response_accumulation_timer;
1367 uint8_t interrupt_delay_timer;
1368
1369 /*
1370 * LSB BIT 0 = Enable Read xfr_rdy
1371 * LSB BIT 1 = Soft ID only
1372 * LSB BIT 2 =
1373 * LSB BIT 3 =
1374 * LSB BIT 4 = FCP RSP Payload [0]
1375 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1376 * LSB BIT 6 = Enable Out-of-Order frame handling
1377 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1378 *
1379 * MSB BIT 0 = Sbus enable - 2300
1380 * MSB BIT 1 =
1381 * MSB BIT 2 =
1382 * MSB BIT 3 =
1383 * MSB BIT 4 = LED mode
1384 * MSB BIT 5 = enable 50 ohm termination
1385 * MSB BIT 6 = Data Rate (2300 only)
1386 * MSB BIT 7 = Data Rate (2300 only)
1387 */
1388 uint8_t special_options[2];
1389
1390 /* Reserved for expanded RISC parameter block */
1391 uint8_t reserved_2[22];
1392
1393 /*
1394 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1395 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1396 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1397 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1398 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1399 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1400 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1401 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1402 *
1403 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1404 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1405 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1406 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1407 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1408 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1409 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1410 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1411 *
1412 * LSB BIT 0 = Output Swing 1G bit 0
1413 * LSB BIT 1 = Output Swing 1G bit 1
1414 * LSB BIT 2 = Output Swing 1G bit 2
1415 * LSB BIT 3 = Output Emphasis 1G bit 0
1416 * LSB BIT 4 = Output Emphasis 1G bit 1
1417 * LSB BIT 5 = Output Swing 2G bit 0
1418 * LSB BIT 6 = Output Swing 2G bit 1
1419 * LSB BIT 7 = Output Swing 2G bit 2
1420 *
1421 * MSB BIT 0 = Output Emphasis 2G bit 0
1422 * MSB BIT 1 = Output Emphasis 2G bit 1
1423 * MSB BIT 2 = Output Enable
1424 * MSB BIT 3 =
1425 * MSB BIT 4 =
1426 * MSB BIT 5 =
1427 * MSB BIT 6 =
1428 * MSB BIT 7 =
1429 */
1430 uint8_t seriallink_options[4];
1431
1432 /*
1433 * NVRAM host parameter block
1434 *
1435 * LSB BIT 0 = Enable spinup delay
1436 * LSB BIT 1 = Disable BIOS
1437 * LSB BIT 2 = Enable Memory Map BIOS
1438 * LSB BIT 3 = Enable Selectable Boot
1439 * LSB BIT 4 = Disable RISC code load
1440 * LSB BIT 5 = Set cache line size 1
1441 * LSB BIT 6 = PCI Parity Disable
1442 * LSB BIT 7 = Enable extended logging
1443 *
1444 * MSB BIT 0 = Enable 64bit addressing
1445 * MSB BIT 1 = Enable lip reset
1446 * MSB BIT 2 = Enable lip full login
1447 * MSB BIT 3 = Enable target reset
1448 * MSB BIT 4 = Enable database storage
1449 * MSB BIT 5 = Enable cache flush read
1450 * MSB BIT 6 = Enable database load
1451 * MSB BIT 7 = Enable alternate WWN
1452 */
1453 uint8_t host_p[2];
1454
1455 uint8_t boot_node_name[WWN_SIZE];
1456 uint8_t boot_lun_number;
1457 uint8_t reset_delay;
1458 uint8_t port_down_retry_count;
1459 uint8_t boot_id_number;
1460 uint16_t max_luns_per_target;
1461 uint8_t fcode_boot_port_name[WWN_SIZE];
1462 uint8_t alternate_port_name[WWN_SIZE];
1463 uint8_t alternate_node_name[WWN_SIZE];
1464
1465 /*
1466 * BIT 0 = Selective Login
1467 * BIT 1 = Alt-Boot Enable
1468 * BIT 2 =
1469 * BIT 3 = Boot Order List
1470 * BIT 4 =
1471 * BIT 5 = Selective LUN
1472 * BIT 6 =
1473 * BIT 7 = unused
1474 */
1475 uint8_t efi_parameters;
1476
1477 uint8_t link_down_timeout;
1478
1479 uint8_t adapter_id[16];
1480
1481 uint8_t alt1_boot_node_name[WWN_SIZE];
1482 uint16_t alt1_boot_lun_number;
1483 uint8_t alt2_boot_node_name[WWN_SIZE];
1484 uint16_t alt2_boot_lun_number;
1485 uint8_t alt3_boot_node_name[WWN_SIZE];
1486 uint16_t alt3_boot_lun_number;
1487 uint8_t alt4_boot_node_name[WWN_SIZE];
1488 uint16_t alt4_boot_lun_number;
1489 uint8_t alt5_boot_node_name[WWN_SIZE];
1490 uint16_t alt5_boot_lun_number;
1491 uint8_t alt6_boot_node_name[WWN_SIZE];
1492 uint16_t alt6_boot_lun_number;
1493 uint8_t alt7_boot_node_name[WWN_SIZE];
1494 uint16_t alt7_boot_lun_number;
1495
1496 uint8_t reserved_3[2];
1497
1498 /* Offset 200-215 : Model Number */
1499 uint8_t model_number[16];
1500
1501 /* OEM related items */
1502 uint8_t oem_specific[16];
1503
1504 /*
1505 * NVRAM Adapter Features offset 232-239
1506 *
1507 * LSB BIT 0 = External GBIC
1508 * LSB BIT 1 = Risc RAM parity
1509 * LSB BIT 2 = Buffer Plus Module
1510 * LSB BIT 3 = Multi Chip Adapter
1511 * LSB BIT 4 = Internal connector
1512 * LSB BIT 5 =
1513 * LSB BIT 6 =
1514 * LSB BIT 7 =
1515 *
1516 * MSB BIT 0 =
1517 * MSB BIT 1 =
1518 * MSB BIT 2 =
1519 * MSB BIT 3 =
1520 * MSB BIT 4 =
1521 * MSB BIT 5 =
1522 * MSB BIT 6 =
1523 * MSB BIT 7 =
1524 */
1525 uint8_t adapter_features[2];
1526
1527 uint8_t reserved_4[16];
1528
1529 /* Subsystem vendor ID for ISP2200 */
1530 uint16_t subsystem_vendor_id_2200;
1531
1532 /* Subsystem device ID for ISP2200 */
1533 uint16_t subsystem_device_id_2200;
1534
1535 uint8_t reserved_5;
1536 uint8_t checksum;
1537 } nvram_t;
1538
1539 /*
1540 * ISP queue - response queue entry definition.
1541 */
1542 typedef struct {
1543 uint8_t entry_type; /* Entry type. */
1544 uint8_t entry_count; /* Entry count. */
1545 uint8_t sys_define; /* System defined. */
1546 uint8_t entry_status; /* Entry Status. */
1547 uint32_t handle; /* System defined handle */
1548 uint8_t data[52];
1549 uint32_t signature;
1550 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1551 } response_t;
1552
1553 /*
1554 * ISP queue - ATIO queue entry definition.
1555 */
1556 struct atio {
1557 uint8_t entry_type; /* Entry type. */
1558 uint8_t entry_count; /* Entry count. */
1559 __le16 attr_n_length;
1560 uint8_t data[56];
1561 uint32_t signature;
1562 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1563 };
1564
1565 typedef union {
1566 uint16_t extended;
1567 struct {
1568 uint8_t reserved;
1569 uint8_t standard;
1570 } id;
1571 } target_id_t;
1572
1573 #define SET_TARGET_ID(ha, to, from) \
1574 do { \
1575 if (HAS_EXTENDED_IDS(ha)) \
1576 to.extended = cpu_to_le16(from); \
1577 else \
1578 to.id.standard = (uint8_t)from; \
1579 } while (0)
1580
1581 /*
1582 * ISP queue - command entry structure definition.
1583 */
1584 #define COMMAND_TYPE 0x11 /* Command entry */
1585 typedef struct {
1586 uint8_t entry_type; /* Entry type. */
1587 uint8_t entry_count; /* Entry count. */
1588 uint8_t sys_define; /* System defined. */
1589 uint8_t entry_status; /* Entry Status. */
1590 uint32_t handle; /* System handle. */
1591 target_id_t target; /* SCSI ID */
1592 uint16_t lun; /* SCSI LUN */
1593 uint16_t control_flags; /* Control flags. */
1594 #define CF_WRITE BIT_6
1595 #define CF_READ BIT_5
1596 #define CF_SIMPLE_TAG BIT_3
1597 #define CF_ORDERED_TAG BIT_2
1598 #define CF_HEAD_TAG BIT_1
1599 uint16_t reserved_1;
1600 uint16_t timeout; /* Command timeout. */
1601 uint16_t dseg_count; /* Data segment count. */
1602 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1603 uint32_t byte_count; /* Total byte count. */
1604 uint32_t dseg_0_address; /* Data segment 0 address. */
1605 uint32_t dseg_0_length; /* Data segment 0 length. */
1606 uint32_t dseg_1_address; /* Data segment 1 address. */
1607 uint32_t dseg_1_length; /* Data segment 1 length. */
1608 uint32_t dseg_2_address; /* Data segment 2 address. */
1609 uint32_t dseg_2_length; /* Data segment 2 length. */
1610 } cmd_entry_t;
1611
1612 /*
1613 * ISP queue - 64-Bit addressing, command entry structure definition.
1614 */
1615 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1616 typedef struct {
1617 uint8_t entry_type; /* Entry type. */
1618 uint8_t entry_count; /* Entry count. */
1619 uint8_t sys_define; /* System defined. */
1620 uint8_t entry_status; /* Entry Status. */
1621 uint32_t handle; /* System handle. */
1622 target_id_t target; /* SCSI ID */
1623 uint16_t lun; /* SCSI LUN */
1624 uint16_t control_flags; /* Control flags. */
1625 uint16_t reserved_1;
1626 uint16_t timeout; /* Command timeout. */
1627 uint16_t dseg_count; /* Data segment count. */
1628 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1629 uint32_t byte_count; /* Total byte count. */
1630 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1631 uint32_t dseg_0_length; /* Data segment 0 length. */
1632 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1633 uint32_t dseg_1_length; /* Data segment 1 length. */
1634 } cmd_a64_entry_t, request_t;
1635
1636 /*
1637 * ISP queue - continuation entry structure definition.
1638 */
1639 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1640 typedef struct {
1641 uint8_t entry_type; /* Entry type. */
1642 uint8_t entry_count; /* Entry count. */
1643 uint8_t sys_define; /* System defined. */
1644 uint8_t entry_status; /* Entry Status. */
1645 uint32_t reserved;
1646 uint32_t dseg_0_address; /* Data segment 0 address. */
1647 uint32_t dseg_0_length; /* Data segment 0 length. */
1648 uint32_t dseg_1_address; /* Data segment 1 address. */
1649 uint32_t dseg_1_length; /* Data segment 1 length. */
1650 uint32_t dseg_2_address; /* Data segment 2 address. */
1651 uint32_t dseg_2_length; /* Data segment 2 length. */
1652 uint32_t dseg_3_address; /* Data segment 3 address. */
1653 uint32_t dseg_3_length; /* Data segment 3 length. */
1654 uint32_t dseg_4_address; /* Data segment 4 address. */
1655 uint32_t dseg_4_length; /* Data segment 4 length. */
1656 uint32_t dseg_5_address; /* Data segment 5 address. */
1657 uint32_t dseg_5_length; /* Data segment 5 length. */
1658 uint32_t dseg_6_address; /* Data segment 6 address. */
1659 uint32_t dseg_6_length; /* Data segment 6 length. */
1660 } cont_entry_t;
1661
1662 /*
1663 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1664 */
1665 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1666 typedef struct {
1667 uint8_t entry_type; /* Entry type. */
1668 uint8_t entry_count; /* Entry count. */
1669 uint8_t sys_define; /* System defined. */
1670 uint8_t entry_status; /* Entry Status. */
1671 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1672 uint32_t dseg_0_length; /* Data segment 0 length. */
1673 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1674 uint32_t dseg_1_length; /* Data segment 1 length. */
1675 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1676 uint32_t dseg_2_length; /* Data segment 2 length. */
1677 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1678 uint32_t dseg_3_length; /* Data segment 3 length. */
1679 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1680 uint32_t dseg_4_length; /* Data segment 4 length. */
1681 } cont_a64_entry_t;
1682
1683 #define PO_MODE_DIF_INSERT 0
1684 #define PO_MODE_DIF_REMOVE 1
1685 #define PO_MODE_DIF_PASS 2
1686 #define PO_MODE_DIF_REPLACE 3
1687 #define PO_MODE_DIF_TCP_CKSUM 6
1688 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1689 #define PO_DISABLE_GUARD_CHECK BIT_4
1690 #define PO_DISABLE_INCR_REF_TAG BIT_5
1691 #define PO_DIS_HEADER_MODE BIT_7
1692 #define PO_ENABLE_DIF_BUNDLING BIT_8
1693 #define PO_DIS_FRAME_MODE BIT_9
1694 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
1695 #define PO_DIS_VALD_APP_REF_ESC BIT_11
1696
1697 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
1698 #define PO_DIS_REF_TAG_REPL BIT_13
1699 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
1700 #define PO_DIS_REF_TAG_VALD BIT_15
1701
1702 /*
1703 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1704 */
1705 struct crc_context {
1706 uint32_t handle; /* System handle. */
1707 __le32 ref_tag;
1708 __le16 app_tag;
1709 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1710 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1711 __le16 guard_seed; /* Initial Guard Seed */
1712 __le16 prot_opts; /* Requested Data Protection Mode */
1713 __le16 blk_size; /* Data size in bytes */
1714 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1715 * only) */
1716 __le32 byte_count; /* Total byte count/ total data
1717 * transfer count */
1718 union {
1719 struct {
1720 uint32_t reserved_1;
1721 uint16_t reserved_2;
1722 uint16_t reserved_3;
1723 uint32_t reserved_4;
1724 uint32_t data_address[2];
1725 uint32_t data_length;
1726 uint32_t reserved_5[2];
1727 uint32_t reserved_6;
1728 } nobundling;
1729 struct {
1730 __le32 dif_byte_count; /* Total DIF byte
1731 * count */
1732 uint16_t reserved_1;
1733 __le16 dseg_count; /* Data segment count */
1734 uint32_t reserved_2;
1735 uint32_t data_address[2];
1736 uint32_t data_length;
1737 uint32_t dif_address[2];
1738 uint32_t dif_length; /* Data segment 0
1739 * length */
1740 } bundling;
1741 } u;
1742
1743 struct fcp_cmnd fcp_cmnd;
1744 dma_addr_t crc_ctx_dma;
1745 /* List of DMA context transfers */
1746 struct list_head dsd_list;
1747
1748 /* This structure should not exceed 512 bytes */
1749 };
1750
1751 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1752 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1753
1754 /*
1755 * ISP queue - status entry structure definition.
1756 */
1757 #define STATUS_TYPE 0x03 /* Status entry. */
1758 typedef struct {
1759 uint8_t entry_type; /* Entry type. */
1760 uint8_t entry_count; /* Entry count. */
1761 uint8_t sys_define; /* System defined. */
1762 uint8_t entry_status; /* Entry Status. */
1763 uint32_t handle; /* System handle. */
1764 uint16_t scsi_status; /* SCSI status. */
1765 uint16_t comp_status; /* Completion status. */
1766 uint16_t state_flags; /* State flags. */
1767 uint16_t status_flags; /* Status flags. */
1768 uint16_t rsp_info_len; /* Response Info Length. */
1769 uint16_t req_sense_length; /* Request sense data length. */
1770 uint32_t residual_length; /* Residual transfer length. */
1771 uint8_t rsp_info[8]; /* FCP response information. */
1772 uint8_t req_sense_data[32]; /* Request sense data. */
1773 } sts_entry_t;
1774
1775 /*
1776 * Status entry entry status
1777 */
1778 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1779 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1780 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1781 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1782 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1783 #define RF_BUSY BIT_1 /* Busy */
1784 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1785 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1786 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1787 RF_INV_E_TYPE)
1788
1789 /*
1790 * Status entry SCSI status bit definitions.
1791 */
1792 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1793 #define SS_RESIDUAL_UNDER BIT_11
1794 #define SS_RESIDUAL_OVER BIT_10
1795 #define SS_SENSE_LEN_VALID BIT_9
1796 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1797
1798 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1799 #define SS_BUSY_CONDITION BIT_3
1800 #define SS_CONDITION_MET BIT_2
1801 #define SS_CHECK_CONDITION BIT_1
1802
1803 /*
1804 * Status entry completion status
1805 */
1806 #define CS_COMPLETE 0x0 /* No errors */
1807 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1808 #define CS_DMA 0x2 /* A DMA direction error. */
1809 #define CS_TRANSPORT 0x3 /* Transport error. */
1810 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1811 #define CS_ABORTED 0x5 /* System aborted command. */
1812 #define CS_TIMEOUT 0x6 /* Timeout error. */
1813 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1814 #define CS_DIF_ERROR 0xC /* DIF error detected */
1815
1816 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1817 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1818 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1819 /* (selection timeout) */
1820 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1821 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1822 #define CS_PORT_BUSY 0x2B /* Port Busy */
1823 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1824 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
1825 failure */
1826 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1827 #define CS_UNKNOWN 0x81 /* Driver defined */
1828 #define CS_RETRY 0x82 /* Driver defined */
1829 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1830
1831 #define CS_BIDIR_RD_OVERRUN 0x700
1832 #define CS_BIDIR_RD_WR_OVERRUN 0x707
1833 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
1834 #define CS_BIDIR_RD_UNDERRUN 0x1500
1835 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
1836 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
1837 #define CS_BIDIR_DMA 0x200
1838 /*
1839 * Status entry status flags
1840 */
1841 #define SF_ABTS_TERMINATED BIT_10
1842 #define SF_LOGOUT_SENT BIT_13
1843
1844 /*
1845 * ISP queue - status continuation entry structure definition.
1846 */
1847 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1848 typedef struct {
1849 uint8_t entry_type; /* Entry type. */
1850 uint8_t entry_count; /* Entry count. */
1851 uint8_t sys_define; /* System defined. */
1852 uint8_t entry_status; /* Entry Status. */
1853 uint8_t data[60]; /* data */
1854 } sts_cont_entry_t;
1855
1856 /*
1857 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1858 * structure definition.
1859 */
1860 #define STATUS_TYPE_21 0x21 /* Status entry. */
1861 typedef struct {
1862 uint8_t entry_type; /* Entry type. */
1863 uint8_t entry_count; /* Entry count. */
1864 uint8_t handle_count; /* Handle count. */
1865 uint8_t entry_status; /* Entry Status. */
1866 uint32_t handle[15]; /* System handles. */
1867 } sts21_entry_t;
1868
1869 /*
1870 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1871 * structure definition.
1872 */
1873 #define STATUS_TYPE_22 0x22 /* Status entry. */
1874 typedef struct {
1875 uint8_t entry_type; /* Entry type. */
1876 uint8_t entry_count; /* Entry count. */
1877 uint8_t handle_count; /* Handle count. */
1878 uint8_t entry_status; /* Entry Status. */
1879 uint16_t handle[30]; /* System handles. */
1880 } sts22_entry_t;
1881
1882 /*
1883 * ISP queue - marker entry structure definition.
1884 */
1885 #define MARKER_TYPE 0x04 /* Marker entry. */
1886 typedef struct {
1887 uint8_t entry_type; /* Entry type. */
1888 uint8_t entry_count; /* Entry count. */
1889 uint8_t handle_count; /* Handle count. */
1890 uint8_t entry_status; /* Entry Status. */
1891 uint32_t sys_define_2; /* System defined. */
1892 target_id_t target; /* SCSI ID */
1893 uint8_t modifier; /* Modifier (7-0). */
1894 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1895 #define MK_SYNC_ID 1 /* Synchronize ID */
1896 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1897 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1898 /* clear port changed, */
1899 /* use sequence number. */
1900 uint8_t reserved_1;
1901 uint16_t sequence_number; /* Sequence number of event */
1902 uint16_t lun; /* SCSI LUN */
1903 uint8_t reserved_2[48];
1904 } mrk_entry_t;
1905
1906 /*
1907 * ISP queue - Management Server entry structure definition.
1908 */
1909 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1910 typedef struct {
1911 uint8_t entry_type; /* Entry type. */
1912 uint8_t entry_count; /* Entry count. */
1913 uint8_t handle_count; /* Handle count. */
1914 uint8_t entry_status; /* Entry Status. */
1915 uint32_t handle1; /* System handle. */
1916 target_id_t loop_id;
1917 uint16_t status;
1918 uint16_t control_flags; /* Control flags. */
1919 uint16_t reserved2;
1920 uint16_t timeout;
1921 uint16_t cmd_dsd_count;
1922 uint16_t total_dsd_count;
1923 uint8_t type;
1924 uint8_t r_ctl;
1925 uint16_t rx_id;
1926 uint16_t reserved3;
1927 uint32_t handle2;
1928 uint32_t rsp_bytecount;
1929 uint32_t req_bytecount;
1930 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1931 uint32_t dseg_req_length; /* Data segment 0 length. */
1932 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1933 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1934 } ms_iocb_entry_t;
1935
1936
1937 /*
1938 * ISP queue - Mailbox Command entry structure definition.
1939 */
1940 #define MBX_IOCB_TYPE 0x39
1941 struct mbx_entry {
1942 uint8_t entry_type;
1943 uint8_t entry_count;
1944 uint8_t sys_define1;
1945 /* Use sys_define1 for source type */
1946 #define SOURCE_SCSI 0x00
1947 #define SOURCE_IP 0x01
1948 #define SOURCE_VI 0x02
1949 #define SOURCE_SCTP 0x03
1950 #define SOURCE_MP 0x04
1951 #define SOURCE_MPIOCTL 0x05
1952 #define SOURCE_ASYNC_IOCB 0x07
1953
1954 uint8_t entry_status;
1955
1956 uint32_t handle;
1957 target_id_t loop_id;
1958
1959 uint16_t status;
1960 uint16_t state_flags;
1961 uint16_t status_flags;
1962
1963 uint32_t sys_define2[2];
1964
1965 uint16_t mb0;
1966 uint16_t mb1;
1967 uint16_t mb2;
1968 uint16_t mb3;
1969 uint16_t mb6;
1970 uint16_t mb7;
1971 uint16_t mb9;
1972 uint16_t mb10;
1973 uint32_t reserved_2[2];
1974 uint8_t node_name[WWN_SIZE];
1975 uint8_t port_name[WWN_SIZE];
1976 };
1977
1978 /*
1979 * ISP request and response queue entry sizes
1980 */
1981 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1982 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1983
1984
1985 /*
1986 * 24 bit port ID type definition.
1987 */
1988 typedef union {
1989 uint32_t b24 : 24;
1990
1991 struct {
1992 #ifdef __BIG_ENDIAN
1993 uint8_t domain;
1994 uint8_t area;
1995 uint8_t al_pa;
1996 #elif defined(__LITTLE_ENDIAN)
1997 uint8_t al_pa;
1998 uint8_t area;
1999 uint8_t domain;
2000 #else
2001 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
2002 #endif
2003 uint8_t rsvd_1;
2004 } b;
2005 } port_id_t;
2006 #define INVALID_PORT_ID 0xFFFFFF
2007
2008 /*
2009 * Switch info gathering structure.
2010 */
2011 typedef struct {
2012 port_id_t d_id;
2013 uint8_t node_name[WWN_SIZE];
2014 uint8_t port_name[WWN_SIZE];
2015 uint8_t fabric_port_name[WWN_SIZE];
2016 uint16_t fp_speed;
2017 uint8_t fc4_type;
2018 } sw_info_t;
2019
2020 /* FCP-4 types */
2021 #define FC4_TYPE_FCP_SCSI 0x08
2022 #define FC4_TYPE_OTHER 0x0
2023 #define FC4_TYPE_UNKNOWN 0xff
2024
2025 /*
2026 * Fibre channel port type.
2027 */
2028 typedef enum {
2029 FCT_UNKNOWN,
2030 FCT_RSCN,
2031 FCT_SWITCH,
2032 FCT_BROADCAST,
2033 FCT_INITIATOR,
2034 FCT_TARGET
2035 } fc_port_type_t;
2036
2037 /*
2038 * Fibre channel port structure.
2039 */
2040 typedef struct fc_port {
2041 struct list_head list;
2042 struct scsi_qla_host *vha;
2043
2044 uint8_t node_name[WWN_SIZE];
2045 uint8_t port_name[WWN_SIZE];
2046 port_id_t d_id;
2047 uint16_t loop_id;
2048 uint16_t old_loop_id;
2049
2050 uint16_t tgt_id;
2051 uint16_t old_tgt_id;
2052
2053 uint8_t fcp_prio;
2054
2055 uint8_t fabric_port_name[WWN_SIZE];
2056 uint16_t fp_speed;
2057
2058 fc_port_type_t port_type;
2059
2060 atomic_t state;
2061 uint32_t flags;
2062
2063 int login_retry;
2064
2065 struct fc_rport *rport, *drport;
2066 u32 supported_classes;
2067
2068 uint8_t fc4_type;
2069 uint8_t scan_state;
2070
2071 unsigned long last_queue_full;
2072 unsigned long last_ramp_up;
2073
2074 uint16_t port_id;
2075
2076 unsigned long retry_delay_timestamp;
2077 struct qla_tgt_sess *tgt_session;
2078 } fc_port_t;
2079
2080 #include "qla_mr.h"
2081
2082 /*
2083 * Fibre channel port/lun states.
2084 */
2085 #define FCS_UNCONFIGURED 1
2086 #define FCS_DEVICE_DEAD 2
2087 #define FCS_DEVICE_LOST 3
2088 #define FCS_ONLINE 4
2089
2090 static const char * const port_state_str[] = {
2091 "Unknown",
2092 "UNCONFIGURED",
2093 "DEAD",
2094 "LOST",
2095 "ONLINE"
2096 };
2097
2098 /*
2099 * FC port flags.
2100 */
2101 #define FCF_FABRIC_DEVICE BIT_0
2102 #define FCF_LOGIN_NEEDED BIT_1
2103 #define FCF_FCP2_DEVICE BIT_2
2104 #define FCF_ASYNC_SENT BIT_3
2105 #define FCF_CONF_COMP_SUPPORTED BIT_4
2106
2107 /* No loop ID flag. */
2108 #define FC_NO_LOOP_ID 0x1000
2109
2110 /*
2111 * FC-CT interface
2112 *
2113 * NOTE: All structures are big-endian in form.
2114 */
2115
2116 #define CT_REJECT_RESPONSE 0x8001
2117 #define CT_ACCEPT_RESPONSE 0x8002
2118 #define CT_REASON_INVALID_COMMAND_CODE 0x01
2119 #define CT_REASON_CANNOT_PERFORM 0x09
2120 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2121 #define CT_EXPL_ALREADY_REGISTERED 0x10
2122 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2123 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2124 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2125 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2126 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2127 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2128 #define CT_EXPL_HBA_NOT_REGISTERED 0x17
2129 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2130 #define CT_EXPL_PORT_NOT_REGISTERED 0x21
2131 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2132 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2133
2134 #define NS_N_PORT_TYPE 0x01
2135 #define NS_NL_PORT_TYPE 0x02
2136 #define NS_NX_PORT_TYPE 0x7F
2137
2138 #define GA_NXT_CMD 0x100
2139 #define GA_NXT_REQ_SIZE (16 + 4)
2140 #define GA_NXT_RSP_SIZE (16 + 620)
2141
2142 #define GID_PT_CMD 0x1A1
2143 #define GID_PT_REQ_SIZE (16 + 4)
2144
2145 #define GPN_ID_CMD 0x112
2146 #define GPN_ID_REQ_SIZE (16 + 4)
2147 #define GPN_ID_RSP_SIZE (16 + 8)
2148
2149 #define GNN_ID_CMD 0x113
2150 #define GNN_ID_REQ_SIZE (16 + 4)
2151 #define GNN_ID_RSP_SIZE (16 + 8)
2152
2153 #define GFT_ID_CMD 0x117
2154 #define GFT_ID_REQ_SIZE (16 + 4)
2155 #define GFT_ID_RSP_SIZE (16 + 32)
2156
2157 #define RFT_ID_CMD 0x217
2158 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
2159 #define RFT_ID_RSP_SIZE 16
2160
2161 #define RFF_ID_CMD 0x21F
2162 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2163 #define RFF_ID_RSP_SIZE 16
2164
2165 #define RNN_ID_CMD 0x213
2166 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
2167 #define RNN_ID_RSP_SIZE 16
2168
2169 #define RSNN_NN_CMD 0x239
2170 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2171 #define RSNN_NN_RSP_SIZE 16
2172
2173 #define GFPN_ID_CMD 0x11C
2174 #define GFPN_ID_REQ_SIZE (16 + 4)
2175 #define GFPN_ID_RSP_SIZE (16 + 8)
2176
2177 #define GPSC_CMD 0x127
2178 #define GPSC_REQ_SIZE (16 + 8)
2179 #define GPSC_RSP_SIZE (16 + 2 + 2)
2180
2181 #define GFF_ID_CMD 0x011F
2182 #define GFF_ID_REQ_SIZE (16 + 4)
2183 #define GFF_ID_RSP_SIZE (16 + 128)
2184
2185 /*
2186 * HBA attribute types.
2187 */
2188 #define FDMI_HBA_ATTR_COUNT 9
2189 #define FDMIV2_HBA_ATTR_COUNT 17
2190 #define FDMI_HBA_NODE_NAME 0x1
2191 #define FDMI_HBA_MANUFACTURER 0x2
2192 #define FDMI_HBA_SERIAL_NUMBER 0x3
2193 #define FDMI_HBA_MODEL 0x4
2194 #define FDMI_HBA_MODEL_DESCRIPTION 0x5
2195 #define FDMI_HBA_HARDWARE_VERSION 0x6
2196 #define FDMI_HBA_DRIVER_VERSION 0x7
2197 #define FDMI_HBA_OPTION_ROM_VERSION 0x8
2198 #define FDMI_HBA_FIRMWARE_VERSION 0x9
2199 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2200 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2201 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2202 #define FDMI_HBA_VENDOR_ID 0xd
2203 #define FDMI_HBA_NUM_PORTS 0xe
2204 #define FDMI_HBA_FABRIC_NAME 0xf
2205 #define FDMI_HBA_BOOT_BIOS_NAME 0x10
2206 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0
2207
2208 struct ct_fdmi_hba_attr {
2209 uint16_t type;
2210 uint16_t len;
2211 union {
2212 uint8_t node_name[WWN_SIZE];
2213 uint8_t manufacturer[64];
2214 uint8_t serial_num[32];
2215 uint8_t model[16+1];
2216 uint8_t model_desc[80];
2217 uint8_t hw_version[32];
2218 uint8_t driver_version[32];
2219 uint8_t orom_version[16];
2220 uint8_t fw_version[32];
2221 uint8_t os_version[128];
2222 uint32_t max_ct_len;
2223 } a;
2224 };
2225
2226 struct ct_fdmi_hba_attributes {
2227 uint32_t count;
2228 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2229 };
2230
2231 struct ct_fdmiv2_hba_attr {
2232 uint16_t type;
2233 uint16_t len;
2234 union {
2235 uint8_t node_name[WWN_SIZE];
2236 uint8_t manufacturer[64];
2237 uint8_t serial_num[32];
2238 uint8_t model[16+1];
2239 uint8_t model_desc[80];
2240 uint8_t hw_version[16];
2241 uint8_t driver_version[32];
2242 uint8_t orom_version[16];
2243 uint8_t fw_version[32];
2244 uint8_t os_version[128];
2245 uint32_t max_ct_len;
2246 uint8_t sym_name[256];
2247 uint32_t vendor_id;
2248 uint32_t num_ports;
2249 uint8_t fabric_name[WWN_SIZE];
2250 uint8_t bios_name[32];
2251 uint8_t vendor_identifier[8];
2252 } a;
2253 };
2254
2255 struct ct_fdmiv2_hba_attributes {
2256 uint32_t count;
2257 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT];
2258 };
2259
2260 /*
2261 * Port attribute types.
2262 */
2263 #define FDMI_PORT_ATTR_COUNT 6
2264 #define FDMIV2_PORT_ATTR_COUNT 16
2265 #define FDMI_PORT_FC4_TYPES 0x1
2266 #define FDMI_PORT_SUPPORT_SPEED 0x2
2267 #define FDMI_PORT_CURRENT_SPEED 0x3
2268 #define FDMI_PORT_MAX_FRAME_SIZE 0x4
2269 #define FDMI_PORT_OS_DEVICE_NAME 0x5
2270 #define FDMI_PORT_HOST_NAME 0x6
2271 #define FDMI_PORT_NODE_NAME 0x7
2272 #define FDMI_PORT_NAME 0x8
2273 #define FDMI_PORT_SYM_NAME 0x9
2274 #define FDMI_PORT_TYPE 0xa
2275 #define FDMI_PORT_SUPP_COS 0xb
2276 #define FDMI_PORT_FABRIC_NAME 0xc
2277 #define FDMI_PORT_FC4_TYPE 0xd
2278 #define FDMI_PORT_STATE 0x101
2279 #define FDMI_PORT_COUNT 0x102
2280 #define FDMI_PORT_ID 0x103
2281
2282 #define FDMI_PORT_SPEED_1GB 0x1
2283 #define FDMI_PORT_SPEED_2GB 0x2
2284 #define FDMI_PORT_SPEED_10GB 0x4
2285 #define FDMI_PORT_SPEED_4GB 0x8
2286 #define FDMI_PORT_SPEED_8GB 0x10
2287 #define FDMI_PORT_SPEED_16GB 0x20
2288 #define FDMI_PORT_SPEED_32GB 0x40
2289 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2290
2291 #define FC_CLASS_2 0x04
2292 #define FC_CLASS_3 0x08
2293 #define FC_CLASS_2_3 0x0C
2294
2295 struct ct_fdmiv2_port_attr {
2296 uint16_t type;
2297 uint16_t len;
2298 union {
2299 uint8_t fc4_types[32];
2300 uint32_t sup_speed;
2301 uint32_t cur_speed;
2302 uint32_t max_frame_size;
2303 uint8_t os_dev_name[32];
2304 uint8_t host_name[256];
2305 uint8_t node_name[WWN_SIZE];
2306 uint8_t port_name[WWN_SIZE];
2307 uint8_t port_sym_name[128];
2308 uint32_t port_type;
2309 uint32_t port_supported_cos;
2310 uint8_t fabric_name[WWN_SIZE];
2311 uint8_t port_fc4_type[32];
2312 uint32_t port_state;
2313 uint32_t num_ports;
2314 uint32_t port_id;
2315 } a;
2316 };
2317
2318 /*
2319 * Port Attribute Block.
2320 */
2321 struct ct_fdmiv2_port_attributes {
2322 uint32_t count;
2323 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT];
2324 };
2325
2326 struct ct_fdmi_port_attr {
2327 uint16_t type;
2328 uint16_t len;
2329 union {
2330 uint8_t fc4_types[32];
2331 uint32_t sup_speed;
2332 uint32_t cur_speed;
2333 uint32_t max_frame_size;
2334 uint8_t os_dev_name[32];
2335 uint8_t host_name[256];
2336 } a;
2337 };
2338
2339 struct ct_fdmi_port_attributes {
2340 uint32_t count;
2341 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2342 };
2343
2344 /* FDMI definitions. */
2345 #define GRHL_CMD 0x100
2346 #define GHAT_CMD 0x101
2347 #define GRPL_CMD 0x102
2348 #define GPAT_CMD 0x110
2349
2350 #define RHBA_CMD 0x200
2351 #define RHBA_RSP_SIZE 16
2352
2353 #define RHAT_CMD 0x201
2354 #define RPRT_CMD 0x210
2355
2356 #define RPA_CMD 0x211
2357 #define RPA_RSP_SIZE 16
2358
2359 #define DHBA_CMD 0x300
2360 #define DHBA_REQ_SIZE (16 + 8)
2361 #define DHBA_RSP_SIZE 16
2362
2363 #define DHAT_CMD 0x301
2364 #define DPRT_CMD 0x310
2365 #define DPA_CMD 0x311
2366
2367 /* CT command header -- request/response common fields */
2368 struct ct_cmd_hdr {
2369 uint8_t revision;
2370 uint8_t in_id[3];
2371 uint8_t gs_type;
2372 uint8_t gs_subtype;
2373 uint8_t options;
2374 uint8_t reserved;
2375 };
2376
2377 /* CT command request */
2378 struct ct_sns_req {
2379 struct ct_cmd_hdr header;
2380 uint16_t command;
2381 uint16_t max_rsp_size;
2382 uint8_t fragment_id;
2383 uint8_t reserved[3];
2384
2385 union {
2386 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
2387 struct {
2388 uint8_t reserved;
2389 uint8_t port_id[3];
2390 } port_id;
2391
2392 struct {
2393 uint8_t port_type;
2394 uint8_t domain;
2395 uint8_t area;
2396 uint8_t reserved;
2397 } gid_pt;
2398
2399 struct {
2400 uint8_t reserved;
2401 uint8_t port_id[3];
2402 uint8_t fc4_types[32];
2403 } rft_id;
2404
2405 struct {
2406 uint8_t reserved;
2407 uint8_t port_id[3];
2408 uint16_t reserved2;
2409 uint8_t fc4_feature;
2410 uint8_t fc4_type;
2411 } rff_id;
2412
2413 struct {
2414 uint8_t reserved;
2415 uint8_t port_id[3];
2416 uint8_t node_name[8];
2417 } rnn_id;
2418
2419 struct {
2420 uint8_t node_name[8];
2421 uint8_t name_len;
2422 uint8_t sym_node_name[255];
2423 } rsnn_nn;
2424
2425 struct {
2426 uint8_t hba_identifier[8];
2427 } ghat;
2428
2429 struct {
2430 uint8_t hba_identifier[8];
2431 uint32_t entry_count;
2432 uint8_t port_name[8];
2433 struct ct_fdmi_hba_attributes attrs;
2434 } rhba;
2435
2436 struct {
2437 uint8_t hba_identifier[8];
2438 uint32_t entry_count;
2439 uint8_t port_name[8];
2440 struct ct_fdmiv2_hba_attributes attrs;
2441 } rhba2;
2442
2443 struct {
2444 uint8_t hba_identifier[8];
2445 struct ct_fdmi_hba_attributes attrs;
2446 } rhat;
2447
2448 struct {
2449 uint8_t port_name[8];
2450 struct ct_fdmi_port_attributes attrs;
2451 } rpa;
2452
2453 struct {
2454 uint8_t port_name[8];
2455 struct ct_fdmiv2_port_attributes attrs;
2456 } rpa2;
2457
2458 struct {
2459 uint8_t port_name[8];
2460 } dhba;
2461
2462 struct {
2463 uint8_t port_name[8];
2464 } dhat;
2465
2466 struct {
2467 uint8_t port_name[8];
2468 } dprt;
2469
2470 struct {
2471 uint8_t port_name[8];
2472 } dpa;
2473
2474 struct {
2475 uint8_t port_name[8];
2476 } gpsc;
2477
2478 struct {
2479 uint8_t reserved;
2480 uint8_t port_name[3];
2481 } gff_id;
2482 } req;
2483 };
2484
2485 /* CT command response header */
2486 struct ct_rsp_hdr {
2487 struct ct_cmd_hdr header;
2488 uint16_t response;
2489 uint16_t residual;
2490 uint8_t fragment_id;
2491 uint8_t reason_code;
2492 uint8_t explanation_code;
2493 uint8_t vendor_unique;
2494 };
2495
2496 struct ct_sns_gid_pt_data {
2497 uint8_t control_byte;
2498 uint8_t port_id[3];
2499 };
2500
2501 struct ct_sns_rsp {
2502 struct ct_rsp_hdr header;
2503
2504 union {
2505 struct {
2506 uint8_t port_type;
2507 uint8_t port_id[3];
2508 uint8_t port_name[8];
2509 uint8_t sym_port_name_len;
2510 uint8_t sym_port_name[255];
2511 uint8_t node_name[8];
2512 uint8_t sym_node_name_len;
2513 uint8_t sym_node_name[255];
2514 uint8_t init_proc_assoc[8];
2515 uint8_t node_ip_addr[16];
2516 uint8_t class_of_service[4];
2517 uint8_t fc4_types[32];
2518 uint8_t ip_address[16];
2519 uint8_t fabric_port_name[8];
2520 uint8_t reserved;
2521 uint8_t hard_address[3];
2522 } ga_nxt;
2523
2524 struct {
2525 /* Assume the largest number of targets for the union */
2526 struct ct_sns_gid_pt_data
2527 entries[MAX_FIBRE_DEVICES_MAX];
2528 } gid_pt;
2529
2530 struct {
2531 uint8_t port_name[8];
2532 } gpn_id;
2533
2534 struct {
2535 uint8_t node_name[8];
2536 } gnn_id;
2537
2538 struct {
2539 uint8_t fc4_types[32];
2540 } gft_id;
2541
2542 struct {
2543 uint32_t entry_count;
2544 uint8_t port_name[8];
2545 struct ct_fdmi_hba_attributes attrs;
2546 } ghat;
2547
2548 struct {
2549 uint8_t port_name[8];
2550 } gfpn_id;
2551
2552 struct {
2553 uint16_t speeds;
2554 uint16_t speed;
2555 } gpsc;
2556
2557 #define GFF_FCP_SCSI_OFFSET 7
2558 struct {
2559 uint8_t fc4_features[128];
2560 } gff_id;
2561 } rsp;
2562 };
2563
2564 struct ct_sns_pkt {
2565 union {
2566 struct ct_sns_req req;
2567 struct ct_sns_rsp rsp;
2568 } p;
2569 };
2570
2571 /*
2572 * SNS command structures -- for 2200 compatibility.
2573 */
2574 #define RFT_ID_SNS_SCMD_LEN 22
2575 #define RFT_ID_SNS_CMD_SIZE 60
2576 #define RFT_ID_SNS_DATA_SIZE 16
2577
2578 #define RNN_ID_SNS_SCMD_LEN 10
2579 #define RNN_ID_SNS_CMD_SIZE 36
2580 #define RNN_ID_SNS_DATA_SIZE 16
2581
2582 #define GA_NXT_SNS_SCMD_LEN 6
2583 #define GA_NXT_SNS_CMD_SIZE 28
2584 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
2585
2586 #define GID_PT_SNS_SCMD_LEN 6
2587 #define GID_PT_SNS_CMD_SIZE 28
2588 /*
2589 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
2590 * adapters.
2591 */
2592 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
2593
2594 #define GPN_ID_SNS_SCMD_LEN 6
2595 #define GPN_ID_SNS_CMD_SIZE 28
2596 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
2597
2598 #define GNN_ID_SNS_SCMD_LEN 6
2599 #define GNN_ID_SNS_CMD_SIZE 28
2600 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
2601
2602 struct sns_cmd_pkt {
2603 union {
2604 struct {
2605 uint16_t buffer_length;
2606 uint16_t reserved_1;
2607 uint32_t buffer_address[2];
2608 uint16_t subcommand_length;
2609 uint16_t reserved_2;
2610 uint16_t subcommand;
2611 uint16_t size;
2612 uint32_t reserved_3;
2613 uint8_t param[36];
2614 } cmd;
2615
2616 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2617 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2618 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2619 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2620 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2621 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2622 } p;
2623 };
2624
2625 struct fw_blob {
2626 char *name;
2627 uint32_t segs[4];
2628 const struct firmware *fw;
2629 };
2630
2631 /* Return data from MBC_GET_ID_LIST call. */
2632 struct gid_list_info {
2633 uint8_t al_pa;
2634 uint8_t area;
2635 uint8_t domain;
2636 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2637 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2638 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2639 };
2640
2641 /* NPIV */
2642 typedef struct vport_info {
2643 uint8_t port_name[WWN_SIZE];
2644 uint8_t node_name[WWN_SIZE];
2645 int vp_id;
2646 uint16_t loop_id;
2647 unsigned long host_no;
2648 uint8_t port_id[3];
2649 int loop_state;
2650 } vport_info_t;
2651
2652 typedef struct vport_params {
2653 uint8_t port_name[WWN_SIZE];
2654 uint8_t node_name[WWN_SIZE];
2655 uint32_t options;
2656 #define VP_OPTS_RETRY_ENABLE BIT_0
2657 #define VP_OPTS_VP_DISABLE BIT_1
2658 } vport_params_t;
2659
2660 /* NPIV - return codes of VP create and modify */
2661 #define VP_RET_CODE_OK 0
2662 #define VP_RET_CODE_FATAL 1
2663 #define VP_RET_CODE_WRONG_ID 2
2664 #define VP_RET_CODE_WWPN 3
2665 #define VP_RET_CODE_RESOURCES 4
2666 #define VP_RET_CODE_NO_MEM 5
2667 #define VP_RET_CODE_NOT_FOUND 6
2668
2669 struct qla_hw_data;
2670 struct rsp_que;
2671 /*
2672 * ISP operations
2673 */
2674 struct isp_operations {
2675
2676 int (*pci_config) (struct scsi_qla_host *);
2677 void (*reset_chip) (struct scsi_qla_host *);
2678 int (*chip_diag) (struct scsi_qla_host *);
2679 void (*config_rings) (struct scsi_qla_host *);
2680 void (*reset_adapter) (struct scsi_qla_host *);
2681 int (*nvram_config) (struct scsi_qla_host *);
2682 void (*update_fw_options) (struct scsi_qla_host *);
2683 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2684
2685 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2686 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
2687
2688 irq_handler_t intr_handler;
2689 void (*enable_intrs) (struct qla_hw_data *);
2690 void (*disable_intrs) (struct qla_hw_data *);
2691
2692 int (*abort_command) (srb_t *);
2693 int (*target_reset) (struct fc_port *, uint64_t, int);
2694 int (*lun_reset) (struct fc_port *, uint64_t, int);
2695 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2696 uint8_t, uint8_t, uint16_t *, uint8_t);
2697 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2698 uint8_t, uint8_t);
2699
2700 uint16_t (*calc_req_entries) (uint16_t);
2701 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2702 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2703 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2704 uint32_t);
2705
2706 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2707 uint32_t, uint32_t);
2708 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2709 uint32_t);
2710
2711 void (*fw_dump) (struct scsi_qla_host *, int);
2712
2713 int (*beacon_on) (struct scsi_qla_host *);
2714 int (*beacon_off) (struct scsi_qla_host *);
2715 void (*beacon_blink) (struct scsi_qla_host *);
2716
2717 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2718 uint32_t, uint32_t);
2719 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2720 uint32_t);
2721
2722 int (*get_flash_version) (struct scsi_qla_host *, void *);
2723 int (*start_scsi) (srb_t *);
2724 int (*start_scsi_mq) (srb_t *);
2725 int (*abort_isp) (struct scsi_qla_host *);
2726 int (*iospace_config)(struct qla_hw_data*);
2727 int (*initialize_adapter)(struct scsi_qla_host *);
2728 };
2729
2730 /* MSI-X Support *************************************************************/
2731
2732 #define QLA_MSIX_CHIP_REV_24XX 3
2733 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2734 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2735
2736 #define QLA_BASE_VECTORS 2 /* default + RSP */
2737 #define QLA_MSIX_RSP_Q 0x01
2738 #define QLA_ATIO_VECTOR 0x02
2739 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
2740
2741 #define QLA_MIDX_DEFAULT 0
2742 #define QLA_MIDX_RSP_Q 1
2743 #define QLA_PCI_MSIX_CONTROL 0xa2
2744 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
2745
2746 struct scsi_qla_host;
2747
2748
2749 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
2750
2751 struct qla_msix_entry {
2752 int have_irq;
2753 int in_use;
2754 uint32_t vector;
2755 uint16_t entry;
2756 char name[30];
2757 void *handle;
2758 int cpuid;
2759 };
2760
2761 #define WATCH_INTERVAL 1 /* number of seconds */
2762
2763 /* Work events. */
2764 enum qla_work_type {
2765 QLA_EVT_AEN,
2766 QLA_EVT_IDC_ACK,
2767 QLA_EVT_ASYNC_LOGIN,
2768 QLA_EVT_ASYNC_LOGIN_DONE,
2769 QLA_EVT_ASYNC_LOGOUT,
2770 QLA_EVT_ASYNC_LOGOUT_DONE,
2771 QLA_EVT_ASYNC_ADISC,
2772 QLA_EVT_ASYNC_ADISC_DONE,
2773 QLA_EVT_UEVENT,
2774 QLA_EVT_AENFX,
2775 };
2776
2777
2778 struct qla_work_evt {
2779 struct list_head list;
2780 enum qla_work_type type;
2781 u32 flags;
2782 #define QLA_EVT_FLAG_FREE 0x1
2783
2784 union {
2785 struct {
2786 enum fc_host_event_code code;
2787 u32 data;
2788 } aen;
2789 struct {
2790 #define QLA_IDC_ACK_REGS 7
2791 uint16_t mb[QLA_IDC_ACK_REGS];
2792 } idc_ack;
2793 struct {
2794 struct fc_port *fcport;
2795 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
2796 u16 data[2];
2797 } logio;
2798 struct {
2799 u32 code;
2800 #define QLA_UEVENT_CODE_FW_DUMP 0
2801 } uevent;
2802 struct {
2803 uint32_t evtcode;
2804 uint32_t mbx[8];
2805 uint32_t count;
2806 } aenfx;
2807 struct {
2808 srb_t *sp;
2809 } iosb;
2810 } u;
2811 };
2812
2813 struct qla_chip_state_84xx {
2814 struct list_head list;
2815 struct kref kref;
2816
2817 void *bus;
2818 spinlock_t access_lock;
2819 struct mutex fw_update_mutex;
2820 uint32_t fw_update;
2821 uint32_t op_fw_version;
2822 uint32_t op_fw_size;
2823 uint32_t op_fw_seq_size;
2824 uint32_t diag_fw_version;
2825 uint32_t gold_fw_version;
2826 };
2827
2828 struct qla_statistics {
2829 uint32_t total_isp_aborts;
2830 uint64_t input_bytes;
2831 uint64_t output_bytes;
2832 uint64_t input_requests;
2833 uint64_t output_requests;
2834 uint32_t control_requests;
2835
2836 uint64_t jiffies_at_last_reset;
2837 uint32_t stat_max_pend_cmds;
2838 uint32_t stat_max_qfull_cmds_alloc;
2839 uint32_t stat_max_qfull_cmds_dropped;
2840 };
2841
2842 struct bidi_statistics {
2843 unsigned long long io_count;
2844 unsigned long long transfer_bytes;
2845 };
2846
2847 /* Multi queue support */
2848 #define MBC_INITIALIZE_MULTIQ 0x1f
2849 #define QLA_QUE_PAGE 0X1000
2850 #define QLA_MQ_SIZE 32
2851 #define QLA_MAX_QUEUES 256
2852 #define ISP_QUE_REG(ha, id) \
2853 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \
2854 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
2855 ((void __iomem *)ha->iobase))
2856 #define QLA_REQ_QUE_ID(tag) \
2857 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2858 #define QLA_DEFAULT_QUE_QOS 5
2859 #define QLA_PRECONFIG_VPORTS 32
2860 #define QLA_MAX_VPORTS_QLA24XX 128
2861 #define QLA_MAX_VPORTS_QLA25XX 256
2862 /* Response queue data structure */
2863 struct rsp_que {
2864 dma_addr_t dma;
2865 response_t *ring;
2866 response_t *ring_ptr;
2867 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2868 uint32_t __iomem *rsp_q_out;
2869 uint16_t ring_index;
2870 uint16_t out_ptr;
2871 uint16_t *in_ptr; /* queue shadow in index */
2872 uint16_t length;
2873 uint16_t options;
2874 uint16_t rid;
2875 uint16_t id;
2876 uint16_t vp_idx;
2877 struct qla_hw_data *hw;
2878 struct qla_msix_entry *msix;
2879 struct req_que *req;
2880 srb_t *status_srb; /* status continuation entry */
2881
2882 dma_addr_t dma_fx00;
2883 response_t *ring_fx00;
2884 uint16_t length_fx00;
2885 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
2886 };
2887
2888 /* Request queue data structure */
2889 struct req_que {
2890 dma_addr_t dma;
2891 request_t *ring;
2892 request_t *ring_ptr;
2893 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2894 uint32_t __iomem *req_q_out;
2895 uint16_t ring_index;
2896 uint16_t in_ptr;
2897 uint16_t *out_ptr; /* queue shadow out index */
2898 uint16_t cnt;
2899 uint16_t length;
2900 uint16_t options;
2901 uint16_t rid;
2902 uint16_t id;
2903 uint16_t qos;
2904 uint16_t vp_idx;
2905 struct rsp_que *rsp;
2906 srb_t **outstanding_cmds;
2907 uint32_t current_outstanding_cmd;
2908 uint16_t num_outstanding_cmds;
2909 int max_q_depth;
2910
2911 dma_addr_t dma_fx00;
2912 request_t *ring_fx00;
2913 uint16_t length_fx00;
2914 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
2915 };
2916
2917 /*Queue pair data structure */
2918 struct qla_qpair {
2919 spinlock_t qp_lock;
2920 atomic_t ref_count;
2921 /* distill these fields down to 'online=0/1'
2922 * ha->flags.eeh_busy
2923 * ha->flags.pci_channel_io_perm_failure
2924 * base_vha->loop_state
2925 */
2926 uint32_t online:1;
2927 /* move vha->flags.difdix_supported here */
2928 uint32_t difdix_supported:1;
2929 uint32_t delete_in_progress:1;
2930
2931 uint16_t id; /* qp number used with FW */
2932 uint16_t num_active_cmd; /* cmds down at firmware */
2933 cpumask_t cpu_mask; /* CPU mask for cpu affinity operation */
2934 uint16_t vp_idx; /* vport ID */
2935
2936 mempool_t *srb_mempool;
2937
2938 /* to do: New driver: move queues to here instead of pointers */
2939 struct req_que *req;
2940 struct rsp_que *rsp;
2941 struct atio_que *atio;
2942 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
2943 struct qla_hw_data *hw;
2944 struct work_struct q_work;
2945 struct list_head qp_list_elem; /* vha->qp_list */
2946 };
2947
2948 /* Place holder for FW buffer parameters */
2949 struct qlfc_fw {
2950 void *fw_buf;
2951 dma_addr_t fw_dma;
2952 uint32_t len;
2953 };
2954
2955 struct scsi_qlt_host {
2956 void *target_lport_ptr;
2957 struct mutex tgt_mutex;
2958 struct mutex tgt_host_action_mutex;
2959 struct qla_tgt *qla_tgt;
2960 };
2961
2962 struct qlt_hw_data {
2963 /* Protected by hw lock */
2964 uint32_t enable_class_2:1;
2965 uint32_t enable_explicit_conf:1;
2966 uint32_t ini_mode_force_reverse:1;
2967 uint32_t node_name_set:1;
2968
2969 dma_addr_t atio_dma; /* Physical address. */
2970 struct atio *atio_ring; /* Base virtual address */
2971 struct atio *atio_ring_ptr; /* Current address. */
2972 uint16_t atio_ring_index; /* Current index. */
2973 uint16_t atio_q_length;
2974 uint32_t __iomem *atio_q_in;
2975 uint32_t __iomem *atio_q_out;
2976
2977 struct qla_tgt_func_tmpl *tgt_ops;
2978 struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS];
2979 uint16_t current_handle;
2980
2981 struct qla_tgt_vp_map *tgt_vp_map;
2982
2983 int saved_set;
2984 uint16_t saved_exchange_count;
2985 uint32_t saved_firmware_options_1;
2986 uint32_t saved_firmware_options_2;
2987 uint32_t saved_firmware_options_3;
2988 uint8_t saved_firmware_options[2];
2989 uint8_t saved_add_firmware_options[2];
2990
2991 uint8_t tgt_node_name[WWN_SIZE];
2992
2993 struct dentry *dfs_tgt_sess;
2994 struct list_head q_full_list;
2995 uint32_t num_pend_cmds;
2996 uint32_t num_qfull_cmds_alloc;
2997 uint32_t num_qfull_cmds_dropped;
2998 spinlock_t q_full_lock;
2999 uint32_t leak_exchg_thresh_hold;
3000 spinlock_t sess_lock;
3001 int rspq_vector_cpuid;
3002 spinlock_t atio_lock ____cacheline_aligned;
3003 };
3004
3005 #define MAX_QFULL_CMDS_ALLOC 8192
3006 #define Q_FULL_THRESH_HOLD_PERCENT 90
3007 #define Q_FULL_THRESH_HOLD(ha) \
3008 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3009
3010 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
3011
3012 /*
3013 * Qlogic host adapter specific data structure.
3014 */
3015 struct qla_hw_data {
3016 struct pci_dev *pdev;
3017 /* SRB cache. */
3018 #define SRB_MIN_REQ 128
3019 mempool_t *srb_mempool;
3020
3021 volatile struct {
3022 uint32_t mbox_int :1;
3023 uint32_t mbox_busy :1;
3024 uint32_t disable_risc_code_load :1;
3025 uint32_t enable_64bit_addressing :1;
3026 uint32_t enable_lip_reset :1;
3027 uint32_t enable_target_reset :1;
3028 uint32_t enable_lip_full_login :1;
3029 uint32_t enable_led_scheme :1;
3030
3031 uint32_t msi_enabled :1;
3032 uint32_t msix_enabled :1;
3033 uint32_t disable_serdes :1;
3034 uint32_t gpsc_supported :1;
3035 uint32_t npiv_supported :1;
3036 uint32_t pci_channel_io_perm_failure :1;
3037 uint32_t fce_enabled :1;
3038 uint32_t fac_supported :1;
3039
3040 uint32_t chip_reset_done :1;
3041 uint32_t running_gold_fw :1;
3042 uint32_t eeh_busy :1;
3043 uint32_t disable_msix_handshake :1;
3044 uint32_t fcp_prio_enabled :1;
3045 uint32_t isp82xx_fw_hung:1;
3046 uint32_t nic_core_hung:1;
3047
3048 uint32_t quiesce_owner:1;
3049 uint32_t nic_core_reset_hdlr_active:1;
3050 uint32_t nic_core_reset_owner:1;
3051 uint32_t isp82xx_no_md_cap:1;
3052 uint32_t host_shutting_down:1;
3053 uint32_t idc_compl_status:1;
3054 uint32_t mr_reset_hdlr_active:1;
3055 uint32_t mr_intr_valid:1;
3056
3057 uint32_t dport_enabled:1;
3058 uint32_t fawwpn_enabled:1;
3059 uint32_t exlogins_enabled:1;
3060 uint32_t exchoffld_enabled:1;
3061 /* 35 bits */
3062 } flags;
3063
3064 /* This spinlock is used to protect "io transactions", you must
3065 * acquire it before doing any IO to the card, eg with RD_REG*() and
3066 * WRT_REG*() for the duration of your entire commandtransaction.
3067 *
3068 * This spinlock is of lower priority than the io request lock.
3069 */
3070
3071 spinlock_t hardware_lock ____cacheline_aligned;
3072 int bars;
3073 int mem_only;
3074 device_reg_t *iobase; /* Base I/O address */
3075 resource_size_t pio_address;
3076
3077 #define MIN_IOBASE_LEN 0x100
3078 dma_addr_t bar0_hdl;
3079
3080 void __iomem *cregbase;
3081 dma_addr_t bar2_hdl;
3082 #define BAR0_LEN_FX00 (1024 * 1024)
3083 #define BAR2_LEN_FX00 (128 * 1024)
3084
3085 uint32_t rqstq_intr_code;
3086 uint32_t mbx_intr_code;
3087 uint32_t req_que_len;
3088 uint32_t rsp_que_len;
3089 uint32_t req_que_off;
3090 uint32_t rsp_que_off;
3091
3092 /* Multi queue data structs */
3093 device_reg_t *mqiobase;
3094 device_reg_t *msixbase;
3095 uint16_t msix_count;
3096 uint8_t mqenable;
3097 struct req_que **req_q_map;
3098 struct rsp_que **rsp_q_map;
3099 struct qla_qpair **queue_pair_map;
3100 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3101 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3102 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3103 / sizeof(unsigned long)];
3104 uint8_t max_req_queues;
3105 uint8_t max_rsp_queues;
3106 uint8_t max_qpairs;
3107 struct qla_qpair *base_qpair;
3108 struct qla_npiv_entry *npiv_info;
3109 uint16_t nvram_npiv_size;
3110
3111 uint16_t switch_cap;
3112 #define FLOGI_SEQ_DEL BIT_8
3113 #define FLOGI_MID_SUPPORT BIT_10
3114 #define FLOGI_VSAN_SUPPORT BIT_12
3115 #define FLOGI_SP_SUPPORT BIT_13
3116
3117 uint8_t port_no; /* Physical port of adapter */
3118
3119 /* Timeout timers. */
3120 uint8_t loop_down_abort_time; /* port down timer */
3121 atomic_t loop_down_timer; /* loop down timer */
3122 uint8_t link_down_timeout; /* link down timeout */
3123 uint16_t max_loop_id;
3124 uint16_t max_fibre_devices; /* Maximum number of targets */
3125
3126 uint16_t fb_rev;
3127 uint16_t min_external_loopid; /* First external loop Id */
3128
3129 #define PORT_SPEED_UNKNOWN 0xFFFF
3130 #define PORT_SPEED_1GB 0x00
3131 #define PORT_SPEED_2GB 0x01
3132 #define PORT_SPEED_4GB 0x03
3133 #define PORT_SPEED_8GB 0x04
3134 #define PORT_SPEED_16GB 0x05
3135 #define PORT_SPEED_32GB 0x06
3136 #define PORT_SPEED_10GB 0x13
3137 uint16_t link_data_rate; /* F/W operating speed */
3138
3139 uint8_t current_topology;
3140 uint8_t prev_topology;
3141 #define ISP_CFG_NL 1
3142 #define ISP_CFG_N 2
3143 #define ISP_CFG_FL 4
3144 #define ISP_CFG_F 8
3145
3146 uint8_t operating_mode; /* F/W operating mode */
3147 #define LOOP 0
3148 #define P2P 1
3149 #define LOOP_P2P 2
3150 #define P2P_LOOP 3
3151 uint8_t interrupts_on;
3152 uint32_t isp_abort_cnt;
3153
3154 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3155 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3156 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
3157 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
3158 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
3159 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3160 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3161 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
3162
3163 uint32_t isp_type;
3164 #define DT_ISP2100 BIT_0
3165 #define DT_ISP2200 BIT_1
3166 #define DT_ISP2300 BIT_2
3167 #define DT_ISP2312 BIT_3
3168 #define DT_ISP2322 BIT_4
3169 #define DT_ISP6312 BIT_5
3170 #define DT_ISP6322 BIT_6
3171 #define DT_ISP2422 BIT_7
3172 #define DT_ISP2432 BIT_8
3173 #define DT_ISP5422 BIT_9
3174 #define DT_ISP5432 BIT_10
3175 #define DT_ISP2532 BIT_11
3176 #define DT_ISP8432 BIT_12
3177 #define DT_ISP8001 BIT_13
3178 #define DT_ISP8021 BIT_14
3179 #define DT_ISP2031 BIT_15
3180 #define DT_ISP8031 BIT_16
3181 #define DT_ISPFX00 BIT_17
3182 #define DT_ISP8044 BIT_18
3183 #define DT_ISP2071 BIT_19
3184 #define DT_ISP2271 BIT_20
3185 #define DT_ISP2261 BIT_21
3186 #define DT_ISP_LAST (DT_ISP2261 << 1)
3187
3188 uint32_t device_type;
3189 #define DT_T10_PI BIT_25
3190 #define DT_IIDMA BIT_26
3191 #define DT_FWI2 BIT_27
3192 #define DT_ZIO_SUPPORTED BIT_28
3193 #define DT_OEM_001 BIT_29
3194 #define DT_ISP2200A BIT_30
3195 #define DT_EXTENDED_IDS BIT_31
3196
3197 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
3198 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
3199 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
3200 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
3201 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
3202 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
3203 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
3204 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
3205 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
3206 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
3207 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
3208 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
3209 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
3210 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
3211 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
3212 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
3213 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
3214 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
3215 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
3216 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
3217 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
3218 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
3219 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
3220 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
3221
3222 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
3223 IS_QLA6312(ha) || IS_QLA6322(ha))
3224 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
3225 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
3226 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
3227 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
3228 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
3229 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
3230 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
3231 IS_QLA84XX(ha))
3232 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
3233 IS_QLA8031(ha) || IS_QLA8044(ha))
3234 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
3235 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
3236 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
3237 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
3238 IS_QLA8044(ha) || IS_QLA27XX(ha))
3239 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3240 IS_QLA27XX(ha))
3241 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
3242 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3243 IS_QLA27XX(ha))
3244 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3245 IS_QLA27XX(ha))
3246 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
3247
3248 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
3249 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
3250 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
3251 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
3252 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3253 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
3254 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
3255 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
3256 IS_QLA27XX(ha))
3257 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha)))
3258 /* Bit 21 of fw_attributes decides the MCTP capabilities */
3259 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3260 ((ha)->fw_attributes_ext[0] & BIT_0))
3261 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3262 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3263 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3264 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3265 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3266 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
3267 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3268 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
3269 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha))
3270 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3271 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3272
3273 /* HBA serial number */
3274 uint8_t serial0;
3275 uint8_t serial1;
3276 uint8_t serial2;
3277
3278 /* NVRAM configuration data */
3279 #define MAX_NVRAM_SIZE 4096
3280 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
3281 uint16_t nvram_size;
3282 uint16_t nvram_base;
3283 void *nvram;
3284 uint16_t vpd_size;
3285 uint16_t vpd_base;
3286 void *vpd;
3287
3288 uint16_t loop_reset_delay;
3289 uint8_t retry_count;
3290 uint8_t login_timeout;
3291 uint16_t r_a_tov;
3292 int port_down_retry_count;
3293 uint8_t mbx_count;
3294 uint8_t aen_mbx_count;
3295
3296 uint32_t login_retry_count;
3297 /* SNS command interfaces. */
3298 ms_iocb_entry_t *ms_iocb;
3299 dma_addr_t ms_iocb_dma;
3300 struct ct_sns_pkt *ct_sns;
3301 dma_addr_t ct_sns_dma;
3302 /* SNS command interfaces for 2200. */
3303 struct sns_cmd_pkt *sns_cmd;
3304 dma_addr_t sns_cmd_dma;
3305
3306 #define SFP_DEV_SIZE 256
3307 #define SFP_BLOCK_SIZE 64
3308 void *sfp_data;
3309 dma_addr_t sfp_data_dma;
3310
3311 #define XGMAC_DATA_SIZE 4096
3312 void *xgmac_data;
3313 dma_addr_t xgmac_data_dma;
3314
3315 #define DCBX_TLV_DATA_SIZE 4096
3316 void *dcbx_tlv;
3317 dma_addr_t dcbx_tlv_dma;
3318
3319 struct task_struct *dpc_thread;
3320 uint8_t dpc_active; /* DPC routine is active */
3321
3322 dma_addr_t gid_list_dma;
3323 struct gid_list_info *gid_list;
3324 int gid_list_info_size;
3325
3326 /* Small DMA pool allocations -- maximum 256 bytes in length. */
3327 #define DMA_POOL_SIZE 256
3328 struct dma_pool *s_dma_pool;
3329
3330 dma_addr_t init_cb_dma;
3331 init_cb_t *init_cb;
3332 int init_cb_size;
3333 dma_addr_t ex_init_cb_dma;
3334 struct ex_init_cb_81xx *ex_init_cb;
3335
3336 void *async_pd;
3337 dma_addr_t async_pd_dma;
3338
3339 #define ENABLE_EXTENDED_LOGIN BIT_7
3340
3341 /* Extended Logins */
3342 void *exlogin_buf;
3343 dma_addr_t exlogin_buf_dma;
3344 int exlogin_size;
3345
3346 #define ENABLE_EXCHANGE_OFFLD BIT_2
3347
3348 /* Exchange Offload */
3349 void *exchoffld_buf;
3350 dma_addr_t exchoffld_buf_dma;
3351 int exchoffld_size;
3352 int exchoffld_count;
3353
3354 void *swl;
3355
3356 /* These are used by mailbox operations. */
3357 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
3358 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
3359 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
3360
3361 mbx_cmd_t *mcp;
3362 struct mbx_cmd_32 *mcp32;
3363
3364 unsigned long mbx_cmd_flags;
3365 #define MBX_INTERRUPT 1
3366 #define MBX_INTR_WAIT 2
3367 #define MBX_UPDATE_FLASH_ACTIVE 3
3368
3369 struct mutex vport_lock; /* Virtual port synchronization */
3370 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
3371 struct mutex mq_lock; /* multi-queue synchronization */
3372 struct completion mbx_cmd_comp; /* Serialize mbx access */
3373 struct completion mbx_intr_comp; /* Used for completion notification */
3374 struct completion dcbx_comp; /* For set port config notification */
3375 struct completion lb_portup_comp; /* Used to wait for link up during
3376 * loopback */
3377 #define DCBX_COMP_TIMEOUT 20
3378 #define LB_PORTUP_COMP_TIMEOUT 10
3379
3380 int notify_dcbx_comp;
3381 int notify_lb_portup_comp;
3382 struct mutex selflogin_lock;
3383
3384 /* Basic firmware related information. */
3385 uint16_t fw_major_version;
3386 uint16_t fw_minor_version;
3387 uint16_t fw_subminor_version;
3388 uint16_t fw_attributes;
3389 uint16_t fw_attributes_h;
3390 uint16_t fw_attributes_ext[2];
3391 uint32_t fw_memory_size;
3392 uint32_t fw_transfer_size;
3393 uint32_t fw_srisc_address;
3394 #define RISC_START_ADDRESS_2100 0x1000
3395 #define RISC_START_ADDRESS_2300 0x800
3396 #define RISC_START_ADDRESS_2400 0x100000
3397
3398 uint16_t orig_fw_tgt_xcb_count;
3399 uint16_t cur_fw_tgt_xcb_count;
3400 uint16_t orig_fw_xcb_count;
3401 uint16_t cur_fw_xcb_count;
3402 uint16_t orig_fw_iocb_count;
3403 uint16_t cur_fw_iocb_count;
3404 uint16_t fw_max_fcf_count;
3405
3406 uint32_t fw_shared_ram_start;
3407 uint32_t fw_shared_ram_end;
3408 uint32_t fw_ddr_ram_start;
3409 uint32_t fw_ddr_ram_end;
3410
3411 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
3412 uint8_t fw_seriallink_options[4];
3413 uint16_t fw_seriallink_options24[4];
3414
3415 uint8_t mpi_version[3];
3416 uint32_t mpi_capabilities;
3417 uint8_t phy_version[3];
3418 uint8_t pep_version[3];
3419
3420 /* Firmware dump template */
3421 void *fw_dump_template;
3422 uint32_t fw_dump_template_len;
3423 /* Firmware dump information. */
3424 struct qla2xxx_fw_dump *fw_dump;
3425 uint32_t fw_dump_len;
3426 int fw_dumped;
3427 unsigned long fw_dump_cap_flags;
3428 #define RISC_PAUSE_CMPL 0
3429 #define DMA_SHUTDOWN_CMPL 1
3430 #define ISP_RESET_CMPL 2
3431 #define RISC_RDY_AFT_RESET 3
3432 #define RISC_SRAM_DUMP_CMPL 4
3433 #define RISC_EXT_MEM_DUMP_CMPL 5
3434 #define ISP_MBX_RDY 6
3435 #define ISP_SOFT_RESET_CMPL 7
3436 int fw_dump_reading;
3437 int prev_minidump_failed;
3438 dma_addr_t eft_dma;
3439 void *eft;
3440 /* Current size of mctp dump is 0x086064 bytes */
3441 #define MCTP_DUMP_SIZE 0x086064
3442 dma_addr_t mctp_dump_dma;
3443 void *mctp_dump;
3444 int mctp_dumped;
3445 int mctp_dump_reading;
3446 uint32_t chain_offset;
3447 struct dentry *dfs_dir;
3448 struct dentry *dfs_fce;
3449 struct dentry *dfs_tgt_counters;
3450 struct dentry *dfs_fw_resource_cnt;
3451
3452 dma_addr_t fce_dma;
3453 void *fce;
3454 uint32_t fce_bufs;
3455 uint16_t fce_mb[8];
3456 uint64_t fce_wr, fce_rd;
3457 struct mutex fce_mutex;
3458
3459 uint32_t pci_attr;
3460 uint16_t chip_revision;
3461
3462 uint16_t product_id[4];
3463
3464 uint8_t model_number[16+1];
3465 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
3466 char model_desc[80];
3467 uint8_t adapter_id[16+1];
3468
3469 /* Option ROM information. */
3470 char *optrom_buffer;
3471 uint32_t optrom_size;
3472 int optrom_state;
3473 #define QLA_SWAITING 0
3474 #define QLA_SREADING 1
3475 #define QLA_SWRITING 2
3476 uint32_t optrom_region_start;
3477 uint32_t optrom_region_size;
3478 struct mutex optrom_mutex;
3479
3480 /* PCI expansion ROM image information. */
3481 #define ROM_CODE_TYPE_BIOS 0
3482 #define ROM_CODE_TYPE_FCODE 1
3483 #define ROM_CODE_TYPE_EFI 3
3484 uint8_t bios_revision[2];
3485 uint8_t efi_revision[2];
3486 uint8_t fcode_revision[16];
3487 uint32_t fw_revision[4];
3488
3489 uint32_t gold_fw_version[4];
3490
3491 /* Offsets for flash/nvram access (set to ~0 if not used). */
3492 uint32_t flash_conf_off;
3493 uint32_t flash_data_off;
3494 uint32_t nvram_conf_off;
3495 uint32_t nvram_data_off;
3496
3497 uint32_t fdt_wrt_disable;
3498 uint32_t fdt_wrt_enable;
3499 uint32_t fdt_erase_cmd;
3500 uint32_t fdt_block_size;
3501 uint32_t fdt_unprotect_sec_cmd;
3502 uint32_t fdt_protect_sec_cmd;
3503 uint32_t fdt_wrt_sts_reg_cmd;
3504
3505 uint32_t flt_region_flt;
3506 uint32_t flt_region_fdt;
3507 uint32_t flt_region_boot;
3508 uint32_t flt_region_boot_sec;
3509 uint32_t flt_region_fw;
3510 uint32_t flt_region_fw_sec;
3511 uint32_t flt_region_vpd_nvram;
3512 uint32_t flt_region_vpd;
3513 uint32_t flt_region_vpd_sec;
3514 uint32_t flt_region_nvram;
3515 uint32_t flt_region_npiv_conf;
3516 uint32_t flt_region_gold_fw;
3517 uint32_t flt_region_fcp_prio;
3518 uint32_t flt_region_bootload;
3519 uint32_t flt_region_img_status_pri;
3520 uint32_t flt_region_img_status_sec;
3521 uint8_t active_image;
3522
3523 /* Needed for BEACON */
3524 uint16_t beacon_blink_led;
3525 uint8_t beacon_color_state;
3526 #define QLA_LED_GRN_ON 0x01
3527 #define QLA_LED_YLW_ON 0x02
3528 #define QLA_LED_ABR_ON 0x04
3529 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
3530 /* ISP2322: red, green, amber. */
3531 uint16_t zio_mode;
3532 uint16_t zio_timer;
3533
3534 struct qla_msix_entry *msix_entries;
3535
3536 struct list_head vp_list; /* list of VP */
3537 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
3538 sizeof(unsigned long)];
3539 uint16_t num_vhosts; /* number of vports created */
3540 uint16_t num_vsans; /* number of vsan created */
3541 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
3542 int cur_vport_count;
3543
3544 struct qla_chip_state_84xx *cs84xx;
3545 struct isp_operations *isp_ops;
3546 struct workqueue_struct *wq;
3547 struct qlfc_fw fw_buf;
3548
3549 /* FCP_CMND priority support */
3550 struct qla_fcp_prio_cfg *fcp_prio_cfg;
3551
3552 struct dma_pool *dl_dma_pool;
3553 #define DSD_LIST_DMA_POOL_SIZE 512
3554
3555 struct dma_pool *fcp_cmnd_dma_pool;
3556 mempool_t *ctx_mempool;
3557 #define FCP_CMND_DMA_POOL_SIZE 512
3558
3559 void __iomem *nx_pcibase; /* Base I/O address */
3560 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
3561 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
3562
3563 uint32_t crb_win;
3564 uint32_t curr_window;
3565 uint32_t ddr_mn_window;
3566 unsigned long mn_win_crb;
3567 unsigned long ms_win_crb;
3568 int qdr_sn_window;
3569 uint32_t fcoe_dev_init_timeout;
3570 uint32_t fcoe_reset_timeout;
3571 rwlock_t hw_lock;
3572 uint16_t portnum; /* port number */
3573 int link_width;
3574 struct fw_blob *hablob;
3575 struct qla82xx_legacy_intr_set nx_legacy_intr;
3576
3577 uint16_t gbl_dsd_inuse;
3578 uint16_t gbl_dsd_avail;
3579 struct list_head gbl_dsd_list;
3580 #define NUM_DSD_CHAIN 4096
3581
3582 uint8_t fw_type;
3583 __le32 file_prd_off; /* File firmware product offset */
3584
3585 uint32_t md_template_size;
3586 void *md_tmplt_hdr;
3587 dma_addr_t md_tmplt_hdr_dma;
3588 void *md_dump;
3589 uint32_t md_dump_size;
3590
3591 void *loop_id_map;
3592
3593 /* QLA83XX IDC specific fields */
3594 uint32_t idc_audit_ts;
3595 uint32_t idc_extend_tmo;
3596
3597 /* DPC low-priority workqueue */
3598 struct workqueue_struct *dpc_lp_wq;
3599 struct work_struct idc_aen;
3600 /* DPC high-priority workqueue */
3601 struct workqueue_struct *dpc_hp_wq;
3602 struct work_struct nic_core_reset;
3603 struct work_struct idc_state_handler;
3604 struct work_struct nic_core_unrecoverable;
3605 struct work_struct board_disable;
3606
3607 struct mr_data_fx00 mr;
3608 uint32_t chip_reset;
3609
3610 struct qlt_hw_data tgt;
3611 int allow_cna_fw_dump;
3612 };
3613
3614 struct qla_tgt_counters {
3615 uint64_t qla_core_sbt_cmd;
3616 uint64_t core_qla_que_buf;
3617 uint64_t qla_core_ret_ctio;
3618 uint64_t core_qla_snd_status;
3619 uint64_t qla_core_ret_sta_ctio;
3620 uint64_t core_qla_free_cmd;
3621 uint64_t num_q_full_sent;
3622 uint64_t num_alloc_iocb_failed;
3623 uint64_t num_term_xchg_sent;
3624 };
3625
3626 /*
3627 * Qlogic scsi host structure
3628 */
3629 typedef struct scsi_qla_host {
3630 struct list_head list;
3631 struct list_head vp_fcports; /* list of fcports */
3632 struct list_head work_list;
3633 spinlock_t work_lock;
3634
3635 /* Commonly used flags and state information. */
3636 struct Scsi_Host *host;
3637 unsigned long host_no;
3638 uint8_t host_str[16];
3639
3640 volatile struct {
3641 uint32_t init_done :1;
3642 uint32_t online :1;
3643 uint32_t reset_active :1;
3644
3645 uint32_t management_server_logged_in :1;
3646 uint32_t process_response_queue :1;
3647 uint32_t difdix_supported:1;
3648 uint32_t delete_progress:1;
3649
3650 uint32_t fw_tgt_reported:1;
3651 uint32_t bbcr_enable:1;
3652 uint32_t qpairs_available:1;
3653 } flags;
3654
3655 atomic_t loop_state;
3656 #define LOOP_TIMEOUT 1
3657 #define LOOP_DOWN 2
3658 #define LOOP_UP 3
3659 #define LOOP_UPDATE 4
3660 #define LOOP_READY 5
3661 #define LOOP_DEAD 6
3662
3663 unsigned long dpc_flags;
3664 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
3665 #define RESET_ACTIVE 1
3666 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
3667 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
3668 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
3669 #define LOOP_RESYNC_ACTIVE 5
3670 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
3671 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
3672 #define RELOGIN_NEEDED 8
3673 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
3674 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
3675 #define BEACON_BLINK_NEEDED 11
3676 #define REGISTER_FDMI_NEEDED 12
3677 #define FCPORT_UPDATE_NEEDED 13
3678 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
3679 #define UNLOADING 15
3680 #define NPIV_CONFIG_NEEDED 16
3681 #define ISP_UNRECOVERABLE 17
3682 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
3683 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
3684 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
3685 #define SCR_PENDING 21 /* SCR in target mode */
3686 #define PORT_UPDATE_NEEDED 22
3687 #define FX00_RESET_RECOVERY 23
3688 #define FX00_TARGET_SCAN 24
3689 #define FX00_CRITEMP_RECOVERY 25
3690 #define FX00_HOST_INFO_RESEND 26
3691 #define QPAIR_ONLINE_CHECK_NEEDED 27
3692
3693 unsigned long pci_flags;
3694 #define PFLG_DISCONNECTED 0 /* PCI device removed */
3695 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
3696 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
3697 #define PCI_ERR 30
3698
3699 uint32_t device_flags;
3700 #define SWITCH_FOUND BIT_0
3701 #define DFLG_NO_CABLE BIT_1
3702 #define DFLG_DEV_FAILED BIT_5
3703
3704 /* ISP configuration data. */
3705 uint16_t loop_id; /* Host adapter loop id */
3706 uint16_t self_login_loop_id; /* host adapter loop id
3707 * get it on self login
3708 */
3709 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
3710 * no need of allocating it for
3711 * each command
3712 */
3713
3714 port_id_t d_id; /* Host adapter port id */
3715 uint8_t marker_needed;
3716 uint16_t mgmt_svr_loop_id;
3717
3718
3719
3720 /* Timeout timers. */
3721 uint8_t loop_down_abort_time; /* port down timer */
3722 atomic_t loop_down_timer; /* loop down timer */
3723 uint8_t link_down_timeout; /* link down timeout */
3724
3725 uint32_t timer_active;
3726 struct timer_list timer;
3727
3728 uint8_t node_name[WWN_SIZE];
3729 uint8_t port_name[WWN_SIZE];
3730 uint8_t fabric_node_name[WWN_SIZE];
3731
3732 uint16_t fcoe_vlan_id;
3733 uint16_t fcoe_fcf_idx;
3734 uint8_t fcoe_vn_port_mac[6];
3735
3736 /* list of commands waiting on workqueue */
3737 struct list_head qla_cmd_list;
3738 struct list_head qla_sess_op_cmd_list;
3739 spinlock_t cmd_list_lock;
3740
3741 /* Counter to detect races between ELS and RSCN events */
3742 atomic_t generation_tick;
3743 /* Time when global fcport update has been scheduled */
3744 int total_fcport_update_gen;
3745 /* List of pending LOGOs, protected by tgt_mutex */
3746 struct list_head logo_list;
3747 /* List of pending PLOGI acks, protected by hw lock */
3748 struct list_head plogi_ack_list;
3749
3750 struct list_head qp_list;
3751
3752 uint32_t vp_abort_cnt;
3753
3754 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
3755 uint16_t vp_idx; /* vport ID */
3756 struct qla_qpair *qpair; /* base qpair */
3757
3758 unsigned long vp_flags;
3759 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
3760 #define VP_CREATE_NEEDED 1
3761 #define VP_BIND_NEEDED 2
3762 #define VP_DELETE_NEEDED 3
3763 #define VP_SCR_NEEDED 4 /* State Change Request registration */
3764 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
3765 atomic_t vp_state;
3766 #define VP_OFFLINE 0
3767 #define VP_ACTIVE 1
3768 #define VP_FAILED 2
3769 // #define VP_DISABLE 3
3770 uint16_t vp_err_state;
3771 uint16_t vp_prev_err_state;
3772 #define VP_ERR_UNKWN 0
3773 #define VP_ERR_PORTDWN 1
3774 #define VP_ERR_FAB_UNSUPPORTED 2
3775 #define VP_ERR_FAB_NORESOURCES 3
3776 #define VP_ERR_FAB_LOGOUT 4
3777 #define VP_ERR_ADAP_NORESOURCES 5
3778 struct qla_hw_data *hw;
3779 struct scsi_qlt_host vha_tgt;
3780 struct req_que *req;
3781 int fw_heartbeat_counter;
3782 int seconds_since_last_heartbeat;
3783 struct fc_host_statistics fc_host_stat;
3784 struct qla_statistics qla_stats;
3785 struct bidi_statistics bidi_stats;
3786
3787 atomic_t vref_count;
3788 struct qla8044_reset_template reset_tmplt;
3789 struct qla_tgt_counters tgt_counters;
3790 uint16_t bbcr;
3791 } scsi_qla_host_t;
3792
3793 struct qla27xx_image_status {
3794 uint8_t image_status_mask;
3795 uint16_t generation_number;
3796 uint8_t reserved[3];
3797 uint8_t ver_minor;
3798 uint8_t ver_major;
3799 uint32_t checksum;
3800 uint32_t signature;
3801 } __packed;
3802
3803 #define SET_VP_IDX 1
3804 #define SET_AL_PA 2
3805 #define RESET_VP_IDX 3
3806 #define RESET_AL_PA 4
3807 struct qla_tgt_vp_map {
3808 uint8_t idx;
3809 scsi_qla_host_t *vha;
3810 };
3811
3812 struct qla2_sgx {
3813 dma_addr_t dma_addr; /* OUT */
3814 uint32_t dma_len; /* OUT */
3815
3816 uint32_t tot_bytes; /* IN */
3817 struct scatterlist *cur_sg; /* IN */
3818
3819 /* for book keeping, bzero on initial invocation */
3820 uint32_t bytes_consumed;
3821 uint32_t num_bytes;
3822 uint32_t tot_partial;
3823
3824 /* for debugging */
3825 uint32_t num_sg;
3826 srb_t *sp;
3827 };
3828
3829 /*
3830 * Macros to help code, maintain, etc.
3831 */
3832 #define LOOP_TRANSITION(ha) \
3833 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
3834 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
3835 atomic_read(&ha->loop_state) == LOOP_DOWN)
3836
3837 #define STATE_TRANSITION(ha) \
3838 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
3839 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
3840
3841 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
3842 atomic_inc(&__vha->vref_count); \
3843 mb(); \
3844 if (__vha->flags.delete_progress) { \
3845 atomic_dec(&__vha->vref_count); \
3846 __bail = 1; \
3847 } else { \
3848 __bail = 0; \
3849 } \
3850 } while (0)
3851
3852 #define QLA_VHA_MARK_NOT_BUSY(__vha) \
3853 atomic_dec(&__vha->vref_count); \
3854
3855 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
3856 atomic_inc(&__qpair->ref_count); \
3857 mb(); \
3858 if (__qpair->delete_in_progress) { \
3859 atomic_dec(&__qpair->ref_count); \
3860 __bail = 1; \
3861 } else { \
3862 __bail = 0; \
3863 } \
3864 } while (0)
3865
3866 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
3867 atomic_dec(&__qpair->ref_count); \
3868
3869 /*
3870 * qla2x00 local function return status codes
3871 */
3872 #define MBS_MASK 0x3fff
3873
3874 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
3875 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
3876 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
3877 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
3878 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
3879 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
3880 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
3881 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
3882 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
3883 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
3884
3885 #define QLA_FUNCTION_TIMEOUT 0x100
3886 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
3887 #define QLA_FUNCTION_FAILED 0x102
3888 #define QLA_MEMORY_ALLOC_FAILED 0x103
3889 #define QLA_LOCK_TIMEOUT 0x104
3890 #define QLA_ABORTED 0x105
3891 #define QLA_SUSPENDED 0x106
3892 #define QLA_BUSY 0x107
3893 #define QLA_ALREADY_REGISTERED 0x109
3894
3895 #define NVRAM_DELAY() udelay(10)
3896
3897 /*
3898 * Flash support definitions
3899 */
3900 #define OPTROM_SIZE_2300 0x20000
3901 #define OPTROM_SIZE_2322 0x100000
3902 #define OPTROM_SIZE_24XX 0x100000
3903 #define OPTROM_SIZE_25XX 0x200000
3904 #define OPTROM_SIZE_81XX 0x400000
3905 #define OPTROM_SIZE_82XX 0x800000
3906 #define OPTROM_SIZE_83XX 0x1000000
3907
3908 #define OPTROM_BURST_SIZE 0x1000
3909 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
3910
3911 #define QLA_DSDS_PER_IOCB 37
3912
3913 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
3914
3915 #define QLA_SG_ALL 1024
3916
3917 enum nexus_wait_type {
3918 WAIT_HOST = 0,
3919 WAIT_TARGET,
3920 WAIT_LUN,
3921 };
3922
3923 #include "qla_gbl.h"
3924 #include "qla_dbg.h"
3925 #include "qla_inline.h"
3926 #endif
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