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Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_def.h
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2011 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34 #include <scsi/scsi_bsg_fc.h>
35
36 #include "qla_bsg.h"
37 #include "qla_nx.h"
38 #define QLA2XXX_DRIVER_NAME "qla2xxx"
39 #define QLA2XXX_APIDEV "ql2xapidev"
40
41 /*
42 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
43 * but that's fine as we don't look at the last 24 ones for
44 * ISP2100 HBAs.
45 */
46 #define MAILBOX_REGISTER_COUNT_2100 8
47 #define MAILBOX_REGISTER_COUNT_2200 24
48 #define MAILBOX_REGISTER_COUNT 32
49
50 #define QLA2200A_RISC_ROM_VER 4
51 #define FPM_2300 6
52 #define FPM_2310 7
53
54 #include "qla_settings.h"
55
56 /*
57 * Data bit definitions
58 */
59 #define BIT_0 0x1
60 #define BIT_1 0x2
61 #define BIT_2 0x4
62 #define BIT_3 0x8
63 #define BIT_4 0x10
64 #define BIT_5 0x20
65 #define BIT_6 0x40
66 #define BIT_7 0x80
67 #define BIT_8 0x100
68 #define BIT_9 0x200
69 #define BIT_10 0x400
70 #define BIT_11 0x800
71 #define BIT_12 0x1000
72 #define BIT_13 0x2000
73 #define BIT_14 0x4000
74 #define BIT_15 0x8000
75 #define BIT_16 0x10000
76 #define BIT_17 0x20000
77 #define BIT_18 0x40000
78 #define BIT_19 0x80000
79 #define BIT_20 0x100000
80 #define BIT_21 0x200000
81 #define BIT_22 0x400000
82 #define BIT_23 0x800000
83 #define BIT_24 0x1000000
84 #define BIT_25 0x2000000
85 #define BIT_26 0x4000000
86 #define BIT_27 0x8000000
87 #define BIT_28 0x10000000
88 #define BIT_29 0x20000000
89 #define BIT_30 0x40000000
90 #define BIT_31 0x80000000
91
92 #define LSB(x) ((uint8_t)(x))
93 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
94
95 #define LSW(x) ((uint16_t)(x))
96 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
97
98 #define LSD(x) ((uint32_t)((uint64_t)(x)))
99 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
100
101 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
102
103 /*
104 * I/O register
105 */
106
107 #define RD_REG_BYTE(addr) readb(addr)
108 #define RD_REG_WORD(addr) readw(addr)
109 #define RD_REG_DWORD(addr) readl(addr)
110 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
111 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
112 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
113 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
114 #define WRT_REG_WORD(addr, data) writew(data,addr)
115 #define WRT_REG_DWORD(addr, data) writel(data,addr)
116
117 /*
118 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
119 * 133Mhz slot.
120 */
121 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
122 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
123
124 /*
125 * Fibre Channel device definitions.
126 */
127 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
128 #define MAX_FIBRE_DEVICES_2100 512
129 #define MAX_FIBRE_DEVICES_2400 2048
130 #define MAX_FIBRE_DEVICES_LOOP 128
131 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
132 #define MAX_FIBRE_LUNS 0xFFFF
133 #define MAX_HOST_COUNT 16
134
135 /*
136 * Host adapter default definitions.
137 */
138 #define MAX_BUSES 1 /* We only have one bus today */
139 #define MIN_LUNS 8
140 #define MAX_LUNS MAX_FIBRE_LUNS
141 #define MAX_CMDS_PER_LUN 255
142
143 /*
144 * Fibre Channel device definitions.
145 */
146 #define SNS_LAST_LOOP_ID_2100 0xfe
147 #define SNS_LAST_LOOP_ID_2300 0x7ff
148
149 #define LAST_LOCAL_LOOP_ID 0x7d
150 #define SNS_FL_PORT 0x7e
151 #define FABRIC_CONTROLLER 0x7f
152 #define SIMPLE_NAME_SERVER 0x80
153 #define SNS_FIRST_LOOP_ID 0x81
154 #define MANAGEMENT_SERVER 0xfe
155 #define BROADCAST 0xff
156
157 /*
158 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
159 * valid range of an N-PORT id is 0 through 0x7ef.
160 */
161 #define NPH_LAST_HANDLE 0x7ef
162 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
163 #define NPH_SNS 0x7fc /* FFFFFC */
164 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
165 #define NPH_F_PORT 0x7fe /* FFFFFE */
166 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
167
168 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
169 #include "qla_fw.h"
170
171 /*
172 * Timeout timer counts in seconds
173 */
174 #define PORT_RETRY_TIME 1
175 #define LOOP_DOWN_TIMEOUT 60
176 #define LOOP_DOWN_TIME 255 /* 240 */
177 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
178
179 /* Maximum outstanding commands in ISP queues (1-65535) */
180 #define MAX_OUTSTANDING_COMMANDS 1024
181
182 /* ISP request and response entry counts (37-65535) */
183 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
184 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
185 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
186 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
187 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
188 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
189 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
190
191 struct req_que;
192
193 /*
194 * (sd.h is not exported, hence local inclusion)
195 * Data Integrity Field tuple.
196 */
197 struct sd_dif_tuple {
198 __be16 guard_tag; /* Checksum */
199 __be16 app_tag; /* Opaque storage */
200 __be32 ref_tag; /* Target LBA or indirect LBA */
201 };
202
203 /*
204 * SCSI Request Block
205 */
206 struct srb_cmd {
207 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
208 uint32_t request_sense_length;
209 uint8_t *request_sense_ptr;
210 void *ctx;
211 };
212
213 /*
214 * SRB flag definitions
215 */
216 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
217 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
218 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
219 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
220 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
221
222 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
223 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
224
225 /*
226 * SRB extensions.
227 */
228 struct srb_iocb {
229 union {
230 struct {
231 uint16_t flags;
232 #define SRB_LOGIN_RETRIED BIT_0
233 #define SRB_LOGIN_COND_PLOGI BIT_1
234 #define SRB_LOGIN_SKIP_PRLI BIT_2
235 uint16_t data[2];
236 } logio;
237 struct {
238 /*
239 * Values for flags field below are as
240 * defined in tsk_mgmt_entry struct
241 * for control_flags field in qla_fw.h.
242 */
243 uint32_t flags;
244 uint32_t lun;
245 uint32_t data;
246 } tmf;
247 } u;
248
249 struct timer_list timer;
250 void (*timeout)(void *);
251 };
252
253 /* Values for srb_ctx type */
254 #define SRB_LOGIN_CMD 1
255 #define SRB_LOGOUT_CMD 2
256 #define SRB_ELS_CMD_RPT 3
257 #define SRB_ELS_CMD_HST 4
258 #define SRB_CT_CMD 5
259 #define SRB_ADISC_CMD 6
260 #define SRB_TM_CMD 7
261 #define SRB_SCSI_CMD 8
262
263 typedef struct srb {
264 atomic_t ref_count;
265 struct fc_port *fcport;
266 uint32_t handle;
267 uint16_t flags;
268 uint16_t type;
269 char *name;
270 int iocbs;
271 union {
272 struct srb_iocb iocb_cmd;
273 struct fc_bsg_job *bsg_job;
274 struct srb_cmd scmd;
275 } u;
276 void (*done)(void *, void *, int);
277 void (*free)(void *, void *);
278 } srb_t;
279
280 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
281 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
282 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
283
284 #define GET_CMD_SENSE_LEN(sp) \
285 (sp->u.scmd.request_sense_length)
286 #define SET_CMD_SENSE_LEN(sp, len) \
287 (sp->u.scmd.request_sense_length = len)
288 #define GET_CMD_SENSE_PTR(sp) \
289 (sp->u.scmd.request_sense_ptr)
290 #define SET_CMD_SENSE_PTR(sp, ptr) \
291 (sp->u.scmd.request_sense_ptr = ptr)
292
293 struct msg_echo_lb {
294 dma_addr_t send_dma;
295 dma_addr_t rcv_dma;
296 uint16_t req_sg_cnt;
297 uint16_t rsp_sg_cnt;
298 uint16_t options;
299 uint32_t transfer_size;
300 };
301
302 /*
303 * ISP I/O Register Set structure definitions.
304 */
305 struct device_reg_2xxx {
306 uint16_t flash_address; /* Flash BIOS address */
307 uint16_t flash_data; /* Flash BIOS data */
308 uint16_t unused_1[1]; /* Gap */
309 uint16_t ctrl_status; /* Control/Status */
310 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
311 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
312 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
313
314 uint16_t ictrl; /* Interrupt control */
315 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
316 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
317
318 uint16_t istatus; /* Interrupt status */
319 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
320
321 uint16_t semaphore; /* Semaphore */
322 uint16_t nvram; /* NVRAM register. */
323 #define NVR_DESELECT 0
324 #define NVR_BUSY BIT_15
325 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
326 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
327 #define NVR_DATA_IN BIT_3
328 #define NVR_DATA_OUT BIT_2
329 #define NVR_SELECT BIT_1
330 #define NVR_CLOCK BIT_0
331
332 #define NVR_WAIT_CNT 20000
333
334 union {
335 struct {
336 uint16_t mailbox0;
337 uint16_t mailbox1;
338 uint16_t mailbox2;
339 uint16_t mailbox3;
340 uint16_t mailbox4;
341 uint16_t mailbox5;
342 uint16_t mailbox6;
343 uint16_t mailbox7;
344 uint16_t unused_2[59]; /* Gap */
345 } __attribute__((packed)) isp2100;
346 struct {
347 /* Request Queue */
348 uint16_t req_q_in; /* In-Pointer */
349 uint16_t req_q_out; /* Out-Pointer */
350 /* Response Queue */
351 uint16_t rsp_q_in; /* In-Pointer */
352 uint16_t rsp_q_out; /* Out-Pointer */
353
354 /* RISC to Host Status */
355 uint32_t host_status;
356 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
357 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
358
359 /* Host to Host Semaphore */
360 uint16_t host_semaphore;
361 uint16_t unused_3[17]; /* Gap */
362 uint16_t mailbox0;
363 uint16_t mailbox1;
364 uint16_t mailbox2;
365 uint16_t mailbox3;
366 uint16_t mailbox4;
367 uint16_t mailbox5;
368 uint16_t mailbox6;
369 uint16_t mailbox7;
370 uint16_t mailbox8;
371 uint16_t mailbox9;
372 uint16_t mailbox10;
373 uint16_t mailbox11;
374 uint16_t mailbox12;
375 uint16_t mailbox13;
376 uint16_t mailbox14;
377 uint16_t mailbox15;
378 uint16_t mailbox16;
379 uint16_t mailbox17;
380 uint16_t mailbox18;
381 uint16_t mailbox19;
382 uint16_t mailbox20;
383 uint16_t mailbox21;
384 uint16_t mailbox22;
385 uint16_t mailbox23;
386 uint16_t mailbox24;
387 uint16_t mailbox25;
388 uint16_t mailbox26;
389 uint16_t mailbox27;
390 uint16_t mailbox28;
391 uint16_t mailbox29;
392 uint16_t mailbox30;
393 uint16_t mailbox31;
394 uint16_t fb_cmd;
395 uint16_t unused_4[10]; /* Gap */
396 } __attribute__((packed)) isp2300;
397 } u;
398
399 uint16_t fpm_diag_config;
400 uint16_t unused_5[0x4]; /* Gap */
401 uint16_t risc_hw;
402 uint16_t unused_5_1; /* Gap */
403 uint16_t pcr; /* Processor Control Register. */
404 uint16_t unused_6[0x5]; /* Gap */
405 uint16_t mctr; /* Memory Configuration and Timing. */
406 uint16_t unused_7[0x3]; /* Gap */
407 uint16_t fb_cmd_2100; /* Unused on 23XX */
408 uint16_t unused_8[0x3]; /* Gap */
409 uint16_t hccr; /* Host command & control register. */
410 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
411 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
412 /* HCCR commands */
413 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
414 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
415 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
416 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
417 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
418 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
419 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
420 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
421
422 uint16_t unused_9[5]; /* Gap */
423 uint16_t gpiod; /* GPIO Data register. */
424 uint16_t gpioe; /* GPIO Enable register. */
425 #define GPIO_LED_MASK 0x00C0
426 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
427 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
428 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
429 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
430 #define GPIO_LED_ALL_OFF 0x0000
431 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
432 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
433
434 union {
435 struct {
436 uint16_t unused_10[8]; /* Gap */
437 uint16_t mailbox8;
438 uint16_t mailbox9;
439 uint16_t mailbox10;
440 uint16_t mailbox11;
441 uint16_t mailbox12;
442 uint16_t mailbox13;
443 uint16_t mailbox14;
444 uint16_t mailbox15;
445 uint16_t mailbox16;
446 uint16_t mailbox17;
447 uint16_t mailbox18;
448 uint16_t mailbox19;
449 uint16_t mailbox20;
450 uint16_t mailbox21;
451 uint16_t mailbox22;
452 uint16_t mailbox23; /* Also probe reg. */
453 } __attribute__((packed)) isp2200;
454 } u_end;
455 };
456
457 struct device_reg_25xxmq {
458 uint32_t req_q_in;
459 uint32_t req_q_out;
460 uint32_t rsp_q_in;
461 uint32_t rsp_q_out;
462 };
463
464 typedef union {
465 struct device_reg_2xxx isp;
466 struct device_reg_24xx isp24;
467 struct device_reg_25xxmq isp25mq;
468 struct device_reg_82xx isp82;
469 } device_reg_t;
470
471 #define ISP_REQ_Q_IN(ha, reg) \
472 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
473 &(reg)->u.isp2100.mailbox4 : \
474 &(reg)->u.isp2300.req_q_in)
475 #define ISP_REQ_Q_OUT(ha, reg) \
476 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
477 &(reg)->u.isp2100.mailbox4 : \
478 &(reg)->u.isp2300.req_q_out)
479 #define ISP_RSP_Q_IN(ha, reg) \
480 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
481 &(reg)->u.isp2100.mailbox5 : \
482 &(reg)->u.isp2300.rsp_q_in)
483 #define ISP_RSP_Q_OUT(ha, reg) \
484 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
485 &(reg)->u.isp2100.mailbox5 : \
486 &(reg)->u.isp2300.rsp_q_out)
487
488 #define MAILBOX_REG(ha, reg, num) \
489 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
490 (num < 8 ? \
491 &(reg)->u.isp2100.mailbox0 + (num) : \
492 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
493 &(reg)->u.isp2300.mailbox0 + (num))
494 #define RD_MAILBOX_REG(ha, reg, num) \
495 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
496 #define WRT_MAILBOX_REG(ha, reg, num, data) \
497 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
498
499 #define FB_CMD_REG(ha, reg) \
500 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
501 &(reg)->fb_cmd_2100 : \
502 &(reg)->u.isp2300.fb_cmd)
503 #define RD_FB_CMD_REG(ha, reg) \
504 RD_REG_WORD(FB_CMD_REG(ha, reg))
505 #define WRT_FB_CMD_REG(ha, reg, data) \
506 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
507
508 typedef struct {
509 uint32_t out_mb; /* outbound from driver */
510 uint32_t in_mb; /* Incoming from RISC */
511 uint16_t mb[MAILBOX_REGISTER_COUNT];
512 long buf_size;
513 void *bufp;
514 uint32_t tov;
515 uint8_t flags;
516 #define MBX_DMA_IN BIT_0
517 #define MBX_DMA_OUT BIT_1
518 #define IOCTL_CMD BIT_2
519 } mbx_cmd_t;
520
521 #define MBX_TOV_SECONDS 30
522
523 /*
524 * ISP product identification definitions in mailboxes after reset.
525 */
526 #define PROD_ID_1 0x4953
527 #define PROD_ID_2 0x0000
528 #define PROD_ID_2a 0x5020
529 #define PROD_ID_3 0x2020
530
531 /*
532 * ISP mailbox Self-Test status codes
533 */
534 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
535 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
536 #define MBS_BUSY 4 /* Busy. */
537
538 /*
539 * ISP mailbox command complete status codes
540 */
541 #define MBS_COMMAND_COMPLETE 0x4000
542 #define MBS_INVALID_COMMAND 0x4001
543 #define MBS_HOST_INTERFACE_ERROR 0x4002
544 #define MBS_TEST_FAILED 0x4003
545 #define MBS_COMMAND_ERROR 0x4005
546 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
547 #define MBS_PORT_ID_USED 0x4007
548 #define MBS_LOOP_ID_USED 0x4008
549 #define MBS_ALL_IDS_IN_USE 0x4009
550 #define MBS_NOT_LOGGED_IN 0x400A
551 #define MBS_LINK_DOWN_ERROR 0x400B
552 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
553
554 /*
555 * ISP mailbox asynchronous event status codes
556 */
557 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
558 #define MBA_RESET 0x8001 /* Reset Detected. */
559 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
560 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
561 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
562 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
563 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
564 /* occurred. */
565 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
566 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
567 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
568 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
569 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
570 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
571 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
572 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
573 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
574 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
575 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
576 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
577 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
578 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
579 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
580 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
581 /* used. */
582 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
583 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
584 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
585 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
586 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
587 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
588 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
589 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
590 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
591 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
592 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
593 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
594 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
595 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
596
597 /* ISP mailbox loopback echo diagnostic error code */
598 #define MBS_LB_RESET 0x17
599 /*
600 * Firmware options 1, 2, 3.
601 */
602 #define FO1_AE_ON_LIPF8 BIT_0
603 #define FO1_AE_ALL_LIP_RESET BIT_1
604 #define FO1_CTIO_RETRY BIT_3
605 #define FO1_DISABLE_LIP_F7_SW BIT_4
606 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
607 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
608 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
609 #define FO1_SET_EMPHASIS_SWING BIT_8
610 #define FO1_AE_AUTO_BYPASS BIT_9
611 #define FO1_ENABLE_PURE_IOCB BIT_10
612 #define FO1_AE_PLOGI_RJT BIT_11
613 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
614 #define FO1_AE_QUEUE_FULL BIT_13
615
616 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
617 #define FO2_REV_LOOPBACK BIT_1
618
619 #define FO3_ENABLE_EMERG_IOCB BIT_0
620 #define FO3_AE_RND_ERROR BIT_1
621
622 /* 24XX additional firmware options */
623 #define ADD_FO_COUNT 3
624 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
625 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
626
627 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
628
629 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
630
631 /*
632 * ISP mailbox commands
633 */
634 #define MBC_LOAD_RAM 1 /* Load RAM. */
635 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
636 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
637 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
638 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
639 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
640 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
641 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
642 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
643 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
644 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
645 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
646 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
647 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
648 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
649 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
650 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
651 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
652 #define MBC_RESET 0x18 /* Reset. */
653 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
654 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
655 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
656 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
657 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
658 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
659 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
660 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
661 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
662 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
663 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
664 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
665 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
666 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
667 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
668 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
669 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
670 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
671 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
672 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
673 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
674 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
675 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
676 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
677 /* Initialization Procedure */
678 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
679 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
680 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
681 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
682 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
683 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
684 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
685 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
686 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
687 #define MBC_LIP_RESET 0x6c /* LIP reset. */
688 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
689 /* commandd. */
690 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
691 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
692 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
693 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
694 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
695 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
696 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
697 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
698 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
699 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
700 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
701
702 /*
703 * ISP24xx mailbox commands
704 */
705 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
706 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
707 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
708 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
709 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
710 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
711 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
712 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
713 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
714 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
715 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
716 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
717 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
718 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
719 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
720 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
721 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
722 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
723
724 /*
725 * ISP81xx mailbox commands
726 */
727 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
728
729 /* Firmware return data sizes */
730 #define FCAL_MAP_SIZE 128
731
732 /* Mailbox bit definitions for out_mb and in_mb */
733 #define MBX_31 BIT_31
734 #define MBX_30 BIT_30
735 #define MBX_29 BIT_29
736 #define MBX_28 BIT_28
737 #define MBX_27 BIT_27
738 #define MBX_26 BIT_26
739 #define MBX_25 BIT_25
740 #define MBX_24 BIT_24
741 #define MBX_23 BIT_23
742 #define MBX_22 BIT_22
743 #define MBX_21 BIT_21
744 #define MBX_20 BIT_20
745 #define MBX_19 BIT_19
746 #define MBX_18 BIT_18
747 #define MBX_17 BIT_17
748 #define MBX_16 BIT_16
749 #define MBX_15 BIT_15
750 #define MBX_14 BIT_14
751 #define MBX_13 BIT_13
752 #define MBX_12 BIT_12
753 #define MBX_11 BIT_11
754 #define MBX_10 BIT_10
755 #define MBX_9 BIT_9
756 #define MBX_8 BIT_8
757 #define MBX_7 BIT_7
758 #define MBX_6 BIT_6
759 #define MBX_5 BIT_5
760 #define MBX_4 BIT_4
761 #define MBX_3 BIT_3
762 #define MBX_2 BIT_2
763 #define MBX_1 BIT_1
764 #define MBX_0 BIT_0
765
766 /*
767 * Firmware state codes from get firmware state mailbox command
768 */
769 #define FSTATE_CONFIG_WAIT 0
770 #define FSTATE_WAIT_AL_PA 1
771 #define FSTATE_WAIT_LOGIN 2
772 #define FSTATE_READY 3
773 #define FSTATE_LOSS_OF_SYNC 4
774 #define FSTATE_ERROR 5
775 #define FSTATE_REINIT 6
776 #define FSTATE_NON_PART 7
777
778 #define FSTATE_CONFIG_CORRECT 0
779 #define FSTATE_P2P_RCV_LIP 1
780 #define FSTATE_P2P_CHOOSE_LOOP 2
781 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
782 #define FSTATE_FATAL_ERROR 4
783 #define FSTATE_LOOP_BACK_CONN 5
784
785 /*
786 * Port Database structure definition
787 * Little endian except where noted.
788 */
789 #define PORT_DATABASE_SIZE 128 /* bytes */
790 typedef struct {
791 uint8_t options;
792 uint8_t control;
793 uint8_t master_state;
794 uint8_t slave_state;
795 uint8_t reserved[2];
796 uint8_t hard_address;
797 uint8_t reserved_1;
798 uint8_t port_id[4];
799 uint8_t node_name[WWN_SIZE];
800 uint8_t port_name[WWN_SIZE];
801 uint16_t execution_throttle;
802 uint16_t execution_count;
803 uint8_t reset_count;
804 uint8_t reserved_2;
805 uint16_t resource_allocation;
806 uint16_t current_allocation;
807 uint16_t queue_head;
808 uint16_t queue_tail;
809 uint16_t transmit_execution_list_next;
810 uint16_t transmit_execution_list_previous;
811 uint16_t common_features;
812 uint16_t total_concurrent_sequences;
813 uint16_t RO_by_information_category;
814 uint8_t recipient;
815 uint8_t initiator;
816 uint16_t receive_data_size;
817 uint16_t concurrent_sequences;
818 uint16_t open_sequences_per_exchange;
819 uint16_t lun_abort_flags;
820 uint16_t lun_stop_flags;
821 uint16_t stop_queue_head;
822 uint16_t stop_queue_tail;
823 uint16_t port_retry_timer;
824 uint16_t next_sequence_id;
825 uint16_t frame_count;
826 uint16_t PRLI_payload_length;
827 uint8_t prli_svc_param_word_0[2]; /* Big endian */
828 /* Bits 15-0 of word 0 */
829 uint8_t prli_svc_param_word_3[2]; /* Big endian */
830 /* Bits 15-0 of word 3 */
831 uint16_t loop_id;
832 uint16_t extended_lun_info_list_pointer;
833 uint16_t extended_lun_stop_list_pointer;
834 } port_database_t;
835
836 /*
837 * Port database slave/master states
838 */
839 #define PD_STATE_DISCOVERY 0
840 #define PD_STATE_WAIT_DISCOVERY_ACK 1
841 #define PD_STATE_PORT_LOGIN 2
842 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
843 #define PD_STATE_PROCESS_LOGIN 4
844 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
845 #define PD_STATE_PORT_LOGGED_IN 6
846 #define PD_STATE_PORT_UNAVAILABLE 7
847 #define PD_STATE_PROCESS_LOGOUT 8
848 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
849 #define PD_STATE_PORT_LOGOUT 10
850 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
851
852
853 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
854 #define QLA_ZIO_DISABLED 0
855 #define QLA_ZIO_DEFAULT_TIMER 2
856
857 /*
858 * ISP Initialization Control Block.
859 * Little endian except where noted.
860 */
861 #define ICB_VERSION 1
862 typedef struct {
863 uint8_t version;
864 uint8_t reserved_1;
865
866 /*
867 * LSB BIT 0 = Enable Hard Loop Id
868 * LSB BIT 1 = Enable Fairness
869 * LSB BIT 2 = Enable Full-Duplex
870 * LSB BIT 3 = Enable Fast Posting
871 * LSB BIT 4 = Enable Target Mode
872 * LSB BIT 5 = Disable Initiator Mode
873 * LSB BIT 6 = Enable ADISC
874 * LSB BIT 7 = Enable Target Inquiry Data
875 *
876 * MSB BIT 0 = Enable PDBC Notify
877 * MSB BIT 1 = Non Participating LIP
878 * MSB BIT 2 = Descending Loop ID Search
879 * MSB BIT 3 = Acquire Loop ID in LIPA
880 * MSB BIT 4 = Stop PortQ on Full Status
881 * MSB BIT 5 = Full Login after LIP
882 * MSB BIT 6 = Node Name Option
883 * MSB BIT 7 = Ext IFWCB enable bit
884 */
885 uint8_t firmware_options[2];
886
887 uint16_t frame_payload_size;
888 uint16_t max_iocb_allocation;
889 uint16_t execution_throttle;
890 uint8_t retry_count;
891 uint8_t retry_delay; /* unused */
892 uint8_t port_name[WWN_SIZE]; /* Big endian. */
893 uint16_t hard_address;
894 uint8_t inquiry_data;
895 uint8_t login_timeout;
896 uint8_t node_name[WWN_SIZE]; /* Big endian. */
897
898 uint16_t request_q_outpointer;
899 uint16_t response_q_inpointer;
900 uint16_t request_q_length;
901 uint16_t response_q_length;
902 uint32_t request_q_address[2];
903 uint32_t response_q_address[2];
904
905 uint16_t lun_enables;
906 uint8_t command_resource_count;
907 uint8_t immediate_notify_resource_count;
908 uint16_t timeout;
909 uint8_t reserved_2[2];
910
911 /*
912 * LSB BIT 0 = Timer Operation mode bit 0
913 * LSB BIT 1 = Timer Operation mode bit 1
914 * LSB BIT 2 = Timer Operation mode bit 2
915 * LSB BIT 3 = Timer Operation mode bit 3
916 * LSB BIT 4 = Init Config Mode bit 0
917 * LSB BIT 5 = Init Config Mode bit 1
918 * LSB BIT 6 = Init Config Mode bit 2
919 * LSB BIT 7 = Enable Non part on LIHA failure
920 *
921 * MSB BIT 0 = Enable class 2
922 * MSB BIT 1 = Enable ACK0
923 * MSB BIT 2 =
924 * MSB BIT 3 =
925 * MSB BIT 4 = FC Tape Enable
926 * MSB BIT 5 = Enable FC Confirm
927 * MSB BIT 6 = Enable command queuing in target mode
928 * MSB BIT 7 = No Logo On Link Down
929 */
930 uint8_t add_firmware_options[2];
931
932 uint8_t response_accumulation_timer;
933 uint8_t interrupt_delay_timer;
934
935 /*
936 * LSB BIT 0 = Enable Read xfr_rdy
937 * LSB BIT 1 = Soft ID only
938 * LSB BIT 2 =
939 * LSB BIT 3 =
940 * LSB BIT 4 = FCP RSP Payload [0]
941 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
942 * LSB BIT 6 = Enable Out-of-Order frame handling
943 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
944 *
945 * MSB BIT 0 = Sbus enable - 2300
946 * MSB BIT 1 =
947 * MSB BIT 2 =
948 * MSB BIT 3 =
949 * MSB BIT 4 = LED mode
950 * MSB BIT 5 = enable 50 ohm termination
951 * MSB BIT 6 = Data Rate (2300 only)
952 * MSB BIT 7 = Data Rate (2300 only)
953 */
954 uint8_t special_options[2];
955
956 uint8_t reserved_3[26];
957 } init_cb_t;
958
959 /*
960 * Get Link Status mailbox command return buffer.
961 */
962 #define GLSO_SEND_RPS BIT_0
963 #define GLSO_USE_DID BIT_3
964
965 struct link_statistics {
966 uint32_t link_fail_cnt;
967 uint32_t loss_sync_cnt;
968 uint32_t loss_sig_cnt;
969 uint32_t prim_seq_err_cnt;
970 uint32_t inval_xmit_word_cnt;
971 uint32_t inval_crc_cnt;
972 uint32_t lip_cnt;
973 uint32_t unused1[0x1a];
974 uint32_t tx_frames;
975 uint32_t rx_frames;
976 uint32_t dumped_frames;
977 uint32_t unused2[2];
978 uint32_t nos_rcvd;
979 };
980
981 /*
982 * NVRAM Command values.
983 */
984 #define NV_START_BIT BIT_2
985 #define NV_WRITE_OP (BIT_26+BIT_24)
986 #define NV_READ_OP (BIT_26+BIT_25)
987 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
988 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
989 #define NV_DELAY_COUNT 10
990
991 /*
992 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
993 */
994 typedef struct {
995 /*
996 * NVRAM header
997 */
998 uint8_t id[4];
999 uint8_t nvram_version;
1000 uint8_t reserved_0;
1001
1002 /*
1003 * NVRAM RISC parameter block
1004 */
1005 uint8_t parameter_block_version;
1006 uint8_t reserved_1;
1007
1008 /*
1009 * LSB BIT 0 = Enable Hard Loop Id
1010 * LSB BIT 1 = Enable Fairness
1011 * LSB BIT 2 = Enable Full-Duplex
1012 * LSB BIT 3 = Enable Fast Posting
1013 * LSB BIT 4 = Enable Target Mode
1014 * LSB BIT 5 = Disable Initiator Mode
1015 * LSB BIT 6 = Enable ADISC
1016 * LSB BIT 7 = Enable Target Inquiry Data
1017 *
1018 * MSB BIT 0 = Enable PDBC Notify
1019 * MSB BIT 1 = Non Participating LIP
1020 * MSB BIT 2 = Descending Loop ID Search
1021 * MSB BIT 3 = Acquire Loop ID in LIPA
1022 * MSB BIT 4 = Stop PortQ on Full Status
1023 * MSB BIT 5 = Full Login after LIP
1024 * MSB BIT 6 = Node Name Option
1025 * MSB BIT 7 = Ext IFWCB enable bit
1026 */
1027 uint8_t firmware_options[2];
1028
1029 uint16_t frame_payload_size;
1030 uint16_t max_iocb_allocation;
1031 uint16_t execution_throttle;
1032 uint8_t retry_count;
1033 uint8_t retry_delay; /* unused */
1034 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1035 uint16_t hard_address;
1036 uint8_t inquiry_data;
1037 uint8_t login_timeout;
1038 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1039
1040 /*
1041 * LSB BIT 0 = Timer Operation mode bit 0
1042 * LSB BIT 1 = Timer Operation mode bit 1
1043 * LSB BIT 2 = Timer Operation mode bit 2
1044 * LSB BIT 3 = Timer Operation mode bit 3
1045 * LSB BIT 4 = Init Config Mode bit 0
1046 * LSB BIT 5 = Init Config Mode bit 1
1047 * LSB BIT 6 = Init Config Mode bit 2
1048 * LSB BIT 7 = Enable Non part on LIHA failure
1049 *
1050 * MSB BIT 0 = Enable class 2
1051 * MSB BIT 1 = Enable ACK0
1052 * MSB BIT 2 =
1053 * MSB BIT 3 =
1054 * MSB BIT 4 = FC Tape Enable
1055 * MSB BIT 5 = Enable FC Confirm
1056 * MSB BIT 6 = Enable command queuing in target mode
1057 * MSB BIT 7 = No Logo On Link Down
1058 */
1059 uint8_t add_firmware_options[2];
1060
1061 uint8_t response_accumulation_timer;
1062 uint8_t interrupt_delay_timer;
1063
1064 /*
1065 * LSB BIT 0 = Enable Read xfr_rdy
1066 * LSB BIT 1 = Soft ID only
1067 * LSB BIT 2 =
1068 * LSB BIT 3 =
1069 * LSB BIT 4 = FCP RSP Payload [0]
1070 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1071 * LSB BIT 6 = Enable Out-of-Order frame handling
1072 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1073 *
1074 * MSB BIT 0 = Sbus enable - 2300
1075 * MSB BIT 1 =
1076 * MSB BIT 2 =
1077 * MSB BIT 3 =
1078 * MSB BIT 4 = LED mode
1079 * MSB BIT 5 = enable 50 ohm termination
1080 * MSB BIT 6 = Data Rate (2300 only)
1081 * MSB BIT 7 = Data Rate (2300 only)
1082 */
1083 uint8_t special_options[2];
1084
1085 /* Reserved for expanded RISC parameter block */
1086 uint8_t reserved_2[22];
1087
1088 /*
1089 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1090 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1091 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1092 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1093 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1094 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1095 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1096 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1097 *
1098 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1099 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1100 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1101 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1102 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1103 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1104 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1105 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1106 *
1107 * LSB BIT 0 = Output Swing 1G bit 0
1108 * LSB BIT 1 = Output Swing 1G bit 1
1109 * LSB BIT 2 = Output Swing 1G bit 2
1110 * LSB BIT 3 = Output Emphasis 1G bit 0
1111 * LSB BIT 4 = Output Emphasis 1G bit 1
1112 * LSB BIT 5 = Output Swing 2G bit 0
1113 * LSB BIT 6 = Output Swing 2G bit 1
1114 * LSB BIT 7 = Output Swing 2G bit 2
1115 *
1116 * MSB BIT 0 = Output Emphasis 2G bit 0
1117 * MSB BIT 1 = Output Emphasis 2G bit 1
1118 * MSB BIT 2 = Output Enable
1119 * MSB BIT 3 =
1120 * MSB BIT 4 =
1121 * MSB BIT 5 =
1122 * MSB BIT 6 =
1123 * MSB BIT 7 =
1124 */
1125 uint8_t seriallink_options[4];
1126
1127 /*
1128 * NVRAM host parameter block
1129 *
1130 * LSB BIT 0 = Enable spinup delay
1131 * LSB BIT 1 = Disable BIOS
1132 * LSB BIT 2 = Enable Memory Map BIOS
1133 * LSB BIT 3 = Enable Selectable Boot
1134 * LSB BIT 4 = Disable RISC code load
1135 * LSB BIT 5 = Set cache line size 1
1136 * LSB BIT 6 = PCI Parity Disable
1137 * LSB BIT 7 = Enable extended logging
1138 *
1139 * MSB BIT 0 = Enable 64bit addressing
1140 * MSB BIT 1 = Enable lip reset
1141 * MSB BIT 2 = Enable lip full login
1142 * MSB BIT 3 = Enable target reset
1143 * MSB BIT 4 = Enable database storage
1144 * MSB BIT 5 = Enable cache flush read
1145 * MSB BIT 6 = Enable database load
1146 * MSB BIT 7 = Enable alternate WWN
1147 */
1148 uint8_t host_p[2];
1149
1150 uint8_t boot_node_name[WWN_SIZE];
1151 uint8_t boot_lun_number;
1152 uint8_t reset_delay;
1153 uint8_t port_down_retry_count;
1154 uint8_t boot_id_number;
1155 uint16_t max_luns_per_target;
1156 uint8_t fcode_boot_port_name[WWN_SIZE];
1157 uint8_t alternate_port_name[WWN_SIZE];
1158 uint8_t alternate_node_name[WWN_SIZE];
1159
1160 /*
1161 * BIT 0 = Selective Login
1162 * BIT 1 = Alt-Boot Enable
1163 * BIT 2 =
1164 * BIT 3 = Boot Order List
1165 * BIT 4 =
1166 * BIT 5 = Selective LUN
1167 * BIT 6 =
1168 * BIT 7 = unused
1169 */
1170 uint8_t efi_parameters;
1171
1172 uint8_t link_down_timeout;
1173
1174 uint8_t adapter_id[16];
1175
1176 uint8_t alt1_boot_node_name[WWN_SIZE];
1177 uint16_t alt1_boot_lun_number;
1178 uint8_t alt2_boot_node_name[WWN_SIZE];
1179 uint16_t alt2_boot_lun_number;
1180 uint8_t alt3_boot_node_name[WWN_SIZE];
1181 uint16_t alt3_boot_lun_number;
1182 uint8_t alt4_boot_node_name[WWN_SIZE];
1183 uint16_t alt4_boot_lun_number;
1184 uint8_t alt5_boot_node_name[WWN_SIZE];
1185 uint16_t alt5_boot_lun_number;
1186 uint8_t alt6_boot_node_name[WWN_SIZE];
1187 uint16_t alt6_boot_lun_number;
1188 uint8_t alt7_boot_node_name[WWN_SIZE];
1189 uint16_t alt7_boot_lun_number;
1190
1191 uint8_t reserved_3[2];
1192
1193 /* Offset 200-215 : Model Number */
1194 uint8_t model_number[16];
1195
1196 /* OEM related items */
1197 uint8_t oem_specific[16];
1198
1199 /*
1200 * NVRAM Adapter Features offset 232-239
1201 *
1202 * LSB BIT 0 = External GBIC
1203 * LSB BIT 1 = Risc RAM parity
1204 * LSB BIT 2 = Buffer Plus Module
1205 * LSB BIT 3 = Multi Chip Adapter
1206 * LSB BIT 4 = Internal connector
1207 * LSB BIT 5 =
1208 * LSB BIT 6 =
1209 * LSB BIT 7 =
1210 *
1211 * MSB BIT 0 =
1212 * MSB BIT 1 =
1213 * MSB BIT 2 =
1214 * MSB BIT 3 =
1215 * MSB BIT 4 =
1216 * MSB BIT 5 =
1217 * MSB BIT 6 =
1218 * MSB BIT 7 =
1219 */
1220 uint8_t adapter_features[2];
1221
1222 uint8_t reserved_4[16];
1223
1224 /* Subsystem vendor ID for ISP2200 */
1225 uint16_t subsystem_vendor_id_2200;
1226
1227 /* Subsystem device ID for ISP2200 */
1228 uint16_t subsystem_device_id_2200;
1229
1230 uint8_t reserved_5;
1231 uint8_t checksum;
1232 } nvram_t;
1233
1234 /*
1235 * ISP queue - response queue entry definition.
1236 */
1237 typedef struct {
1238 uint8_t entry_type; /* Entry type. */
1239 uint8_t entry_count; /* Entry count. */
1240 uint8_t sys_define; /* System defined. */
1241 uint8_t entry_status; /* Entry Status. */
1242 uint32_t handle; /* System defined handle */
1243 uint8_t data[52];
1244 uint32_t signature;
1245 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1246 } response_t;
1247
1248 /*
1249 * ISP queue - ATIO queue entry definition.
1250 */
1251 struct atio {
1252 uint8_t entry_type; /* Entry type. */
1253 uint8_t entry_count; /* Entry count. */
1254 uint8_t data[58];
1255 uint32_t signature;
1256 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1257 };
1258
1259 typedef union {
1260 uint16_t extended;
1261 struct {
1262 uint8_t reserved;
1263 uint8_t standard;
1264 } id;
1265 } target_id_t;
1266
1267 #define SET_TARGET_ID(ha, to, from) \
1268 do { \
1269 if (HAS_EXTENDED_IDS(ha)) \
1270 to.extended = cpu_to_le16(from); \
1271 else \
1272 to.id.standard = (uint8_t)from; \
1273 } while (0)
1274
1275 /*
1276 * ISP queue - command entry structure definition.
1277 */
1278 #define COMMAND_TYPE 0x11 /* Command entry */
1279 typedef struct {
1280 uint8_t entry_type; /* Entry type. */
1281 uint8_t entry_count; /* Entry count. */
1282 uint8_t sys_define; /* System defined. */
1283 uint8_t entry_status; /* Entry Status. */
1284 uint32_t handle; /* System handle. */
1285 target_id_t target; /* SCSI ID */
1286 uint16_t lun; /* SCSI LUN */
1287 uint16_t control_flags; /* Control flags. */
1288 #define CF_WRITE BIT_6
1289 #define CF_READ BIT_5
1290 #define CF_SIMPLE_TAG BIT_3
1291 #define CF_ORDERED_TAG BIT_2
1292 #define CF_HEAD_TAG BIT_1
1293 uint16_t reserved_1;
1294 uint16_t timeout; /* Command timeout. */
1295 uint16_t dseg_count; /* Data segment count. */
1296 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1297 uint32_t byte_count; /* Total byte count. */
1298 uint32_t dseg_0_address; /* Data segment 0 address. */
1299 uint32_t dseg_0_length; /* Data segment 0 length. */
1300 uint32_t dseg_1_address; /* Data segment 1 address. */
1301 uint32_t dseg_1_length; /* Data segment 1 length. */
1302 uint32_t dseg_2_address; /* Data segment 2 address. */
1303 uint32_t dseg_2_length; /* Data segment 2 length. */
1304 } cmd_entry_t;
1305
1306 /*
1307 * ISP queue - 64-Bit addressing, command entry structure definition.
1308 */
1309 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1310 typedef struct {
1311 uint8_t entry_type; /* Entry type. */
1312 uint8_t entry_count; /* Entry count. */
1313 uint8_t sys_define; /* System defined. */
1314 uint8_t entry_status; /* Entry Status. */
1315 uint32_t handle; /* System handle. */
1316 target_id_t target; /* SCSI ID */
1317 uint16_t lun; /* SCSI LUN */
1318 uint16_t control_flags; /* Control flags. */
1319 uint16_t reserved_1;
1320 uint16_t timeout; /* Command timeout. */
1321 uint16_t dseg_count; /* Data segment count. */
1322 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1323 uint32_t byte_count; /* Total byte count. */
1324 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1325 uint32_t dseg_0_length; /* Data segment 0 length. */
1326 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1327 uint32_t dseg_1_length; /* Data segment 1 length. */
1328 } cmd_a64_entry_t, request_t;
1329
1330 /*
1331 * ISP queue - continuation entry structure definition.
1332 */
1333 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1334 typedef struct {
1335 uint8_t entry_type; /* Entry type. */
1336 uint8_t entry_count; /* Entry count. */
1337 uint8_t sys_define; /* System defined. */
1338 uint8_t entry_status; /* Entry Status. */
1339 uint32_t reserved;
1340 uint32_t dseg_0_address; /* Data segment 0 address. */
1341 uint32_t dseg_0_length; /* Data segment 0 length. */
1342 uint32_t dseg_1_address; /* Data segment 1 address. */
1343 uint32_t dseg_1_length; /* Data segment 1 length. */
1344 uint32_t dseg_2_address; /* Data segment 2 address. */
1345 uint32_t dseg_2_length; /* Data segment 2 length. */
1346 uint32_t dseg_3_address; /* Data segment 3 address. */
1347 uint32_t dseg_3_length; /* Data segment 3 length. */
1348 uint32_t dseg_4_address; /* Data segment 4 address. */
1349 uint32_t dseg_4_length; /* Data segment 4 length. */
1350 uint32_t dseg_5_address; /* Data segment 5 address. */
1351 uint32_t dseg_5_length; /* Data segment 5 length. */
1352 uint32_t dseg_6_address; /* Data segment 6 address. */
1353 uint32_t dseg_6_length; /* Data segment 6 length. */
1354 } cont_entry_t;
1355
1356 /*
1357 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1358 */
1359 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1360 typedef struct {
1361 uint8_t entry_type; /* Entry type. */
1362 uint8_t entry_count; /* Entry count. */
1363 uint8_t sys_define; /* System defined. */
1364 uint8_t entry_status; /* Entry Status. */
1365 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1366 uint32_t dseg_0_length; /* Data segment 0 length. */
1367 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1368 uint32_t dseg_1_length; /* Data segment 1 length. */
1369 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1370 uint32_t dseg_2_length; /* Data segment 2 length. */
1371 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1372 uint32_t dseg_3_length; /* Data segment 3 length. */
1373 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1374 uint32_t dseg_4_length; /* Data segment 4 length. */
1375 } cont_a64_entry_t;
1376
1377 #define PO_MODE_DIF_INSERT 0
1378 #define PO_MODE_DIF_REMOVE BIT_0
1379 #define PO_MODE_DIF_PASS BIT_1
1380 #define PO_MODE_DIF_REPLACE (BIT_0 + BIT_1)
1381 #define PO_ENABLE_DIF_BUNDLING BIT_8
1382 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1383 #define PO_DISABLE_INCR_REF_TAG BIT_5
1384 #define PO_DISABLE_GUARD_CHECK BIT_4
1385 /*
1386 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1387 */
1388 struct crc_context {
1389 uint32_t handle; /* System handle. */
1390 uint32_t ref_tag;
1391 uint16_t app_tag;
1392 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1393 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1394 uint16_t guard_seed; /* Initial Guard Seed */
1395 uint16_t prot_opts; /* Requested Data Protection Mode */
1396 uint16_t blk_size; /* Data size in bytes */
1397 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1398 * only) */
1399 uint32_t byte_count; /* Total byte count/ total data
1400 * transfer count */
1401 union {
1402 struct {
1403 uint32_t reserved_1;
1404 uint16_t reserved_2;
1405 uint16_t reserved_3;
1406 uint32_t reserved_4;
1407 uint32_t data_address[2];
1408 uint32_t data_length;
1409 uint32_t reserved_5[2];
1410 uint32_t reserved_6;
1411 } nobundling;
1412 struct {
1413 uint32_t dif_byte_count; /* Total DIF byte
1414 * count */
1415 uint16_t reserved_1;
1416 uint16_t dseg_count; /* Data segment count */
1417 uint32_t reserved_2;
1418 uint32_t data_address[2];
1419 uint32_t data_length;
1420 uint32_t dif_address[2];
1421 uint32_t dif_length; /* Data segment 0
1422 * length */
1423 } bundling;
1424 } u;
1425
1426 struct fcp_cmnd fcp_cmnd;
1427 dma_addr_t crc_ctx_dma;
1428 /* List of DMA context transfers */
1429 struct list_head dsd_list;
1430
1431 /* This structure should not exceed 512 bytes */
1432 };
1433
1434 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1435 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1436
1437 /*
1438 * ISP queue - status entry structure definition.
1439 */
1440 #define STATUS_TYPE 0x03 /* Status entry. */
1441 typedef struct {
1442 uint8_t entry_type; /* Entry type. */
1443 uint8_t entry_count; /* Entry count. */
1444 uint8_t sys_define; /* System defined. */
1445 uint8_t entry_status; /* Entry Status. */
1446 uint32_t handle; /* System handle. */
1447 uint16_t scsi_status; /* SCSI status. */
1448 uint16_t comp_status; /* Completion status. */
1449 uint16_t state_flags; /* State flags. */
1450 uint16_t status_flags; /* Status flags. */
1451 uint16_t rsp_info_len; /* Response Info Length. */
1452 uint16_t req_sense_length; /* Request sense data length. */
1453 uint32_t residual_length; /* Residual transfer length. */
1454 uint8_t rsp_info[8]; /* FCP response information. */
1455 uint8_t req_sense_data[32]; /* Request sense data. */
1456 } sts_entry_t;
1457
1458 /*
1459 * Status entry entry status
1460 */
1461 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1462 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1463 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1464 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1465 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1466 #define RF_BUSY BIT_1 /* Busy */
1467 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1468 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1469 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1470 RF_INV_E_TYPE)
1471
1472 /*
1473 * Status entry SCSI status bit definitions.
1474 */
1475 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1476 #define SS_RESIDUAL_UNDER BIT_11
1477 #define SS_RESIDUAL_OVER BIT_10
1478 #define SS_SENSE_LEN_VALID BIT_9
1479 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1480
1481 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1482 #define SS_BUSY_CONDITION BIT_3
1483 #define SS_CONDITION_MET BIT_2
1484 #define SS_CHECK_CONDITION BIT_1
1485
1486 /*
1487 * Status entry completion status
1488 */
1489 #define CS_COMPLETE 0x0 /* No errors */
1490 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1491 #define CS_DMA 0x2 /* A DMA direction error. */
1492 #define CS_TRANSPORT 0x3 /* Transport error. */
1493 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1494 #define CS_ABORTED 0x5 /* System aborted command. */
1495 #define CS_TIMEOUT 0x6 /* Timeout error. */
1496 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1497 #define CS_DIF_ERROR 0xC /* DIF error detected */
1498
1499 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1500 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1501 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1502 /* (selection timeout) */
1503 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1504 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1505 #define CS_PORT_BUSY 0x2B /* Port Busy */
1506 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1507 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1508 #define CS_UNKNOWN 0x81 /* Driver defined */
1509 #define CS_RETRY 0x82 /* Driver defined */
1510 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1511
1512 /*
1513 * Status entry status flags
1514 */
1515 #define SF_ABTS_TERMINATED BIT_10
1516 #define SF_LOGOUT_SENT BIT_13
1517
1518 /*
1519 * ISP queue - status continuation entry structure definition.
1520 */
1521 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1522 typedef struct {
1523 uint8_t entry_type; /* Entry type. */
1524 uint8_t entry_count; /* Entry count. */
1525 uint8_t sys_define; /* System defined. */
1526 uint8_t entry_status; /* Entry Status. */
1527 uint8_t data[60]; /* data */
1528 } sts_cont_entry_t;
1529
1530 /*
1531 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1532 * structure definition.
1533 */
1534 #define STATUS_TYPE_21 0x21 /* Status entry. */
1535 typedef struct {
1536 uint8_t entry_type; /* Entry type. */
1537 uint8_t entry_count; /* Entry count. */
1538 uint8_t handle_count; /* Handle count. */
1539 uint8_t entry_status; /* Entry Status. */
1540 uint32_t handle[15]; /* System handles. */
1541 } sts21_entry_t;
1542
1543 /*
1544 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1545 * structure definition.
1546 */
1547 #define STATUS_TYPE_22 0x22 /* Status entry. */
1548 typedef struct {
1549 uint8_t entry_type; /* Entry type. */
1550 uint8_t entry_count; /* Entry count. */
1551 uint8_t handle_count; /* Handle count. */
1552 uint8_t entry_status; /* Entry Status. */
1553 uint16_t handle[30]; /* System handles. */
1554 } sts22_entry_t;
1555
1556 /*
1557 * ISP queue - marker entry structure definition.
1558 */
1559 #define MARKER_TYPE 0x04 /* Marker entry. */
1560 typedef struct {
1561 uint8_t entry_type; /* Entry type. */
1562 uint8_t entry_count; /* Entry count. */
1563 uint8_t handle_count; /* Handle count. */
1564 uint8_t entry_status; /* Entry Status. */
1565 uint32_t sys_define_2; /* System defined. */
1566 target_id_t target; /* SCSI ID */
1567 uint8_t modifier; /* Modifier (7-0). */
1568 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1569 #define MK_SYNC_ID 1 /* Synchronize ID */
1570 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1571 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1572 /* clear port changed, */
1573 /* use sequence number. */
1574 uint8_t reserved_1;
1575 uint16_t sequence_number; /* Sequence number of event */
1576 uint16_t lun; /* SCSI LUN */
1577 uint8_t reserved_2[48];
1578 } mrk_entry_t;
1579
1580 /*
1581 * ISP queue - Management Server entry structure definition.
1582 */
1583 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1584 typedef struct {
1585 uint8_t entry_type; /* Entry type. */
1586 uint8_t entry_count; /* Entry count. */
1587 uint8_t handle_count; /* Handle count. */
1588 uint8_t entry_status; /* Entry Status. */
1589 uint32_t handle1; /* System handle. */
1590 target_id_t loop_id;
1591 uint16_t status;
1592 uint16_t control_flags; /* Control flags. */
1593 uint16_t reserved2;
1594 uint16_t timeout;
1595 uint16_t cmd_dsd_count;
1596 uint16_t total_dsd_count;
1597 uint8_t type;
1598 uint8_t r_ctl;
1599 uint16_t rx_id;
1600 uint16_t reserved3;
1601 uint32_t handle2;
1602 uint32_t rsp_bytecount;
1603 uint32_t req_bytecount;
1604 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1605 uint32_t dseg_req_length; /* Data segment 0 length. */
1606 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1607 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1608 } ms_iocb_entry_t;
1609
1610
1611 /*
1612 * ISP queue - Mailbox Command entry structure definition.
1613 */
1614 #define MBX_IOCB_TYPE 0x39
1615 struct mbx_entry {
1616 uint8_t entry_type;
1617 uint8_t entry_count;
1618 uint8_t sys_define1;
1619 /* Use sys_define1 for source type */
1620 #define SOURCE_SCSI 0x00
1621 #define SOURCE_IP 0x01
1622 #define SOURCE_VI 0x02
1623 #define SOURCE_SCTP 0x03
1624 #define SOURCE_MP 0x04
1625 #define SOURCE_MPIOCTL 0x05
1626 #define SOURCE_ASYNC_IOCB 0x07
1627
1628 uint8_t entry_status;
1629
1630 uint32_t handle;
1631 target_id_t loop_id;
1632
1633 uint16_t status;
1634 uint16_t state_flags;
1635 uint16_t status_flags;
1636
1637 uint32_t sys_define2[2];
1638
1639 uint16_t mb0;
1640 uint16_t mb1;
1641 uint16_t mb2;
1642 uint16_t mb3;
1643 uint16_t mb6;
1644 uint16_t mb7;
1645 uint16_t mb9;
1646 uint16_t mb10;
1647 uint32_t reserved_2[2];
1648 uint8_t node_name[WWN_SIZE];
1649 uint8_t port_name[WWN_SIZE];
1650 };
1651
1652 /*
1653 * ISP request and response queue entry sizes
1654 */
1655 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1656 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1657
1658
1659 /*
1660 * 24 bit port ID type definition.
1661 */
1662 typedef union {
1663 uint32_t b24 : 24;
1664
1665 struct {
1666 #ifdef __BIG_ENDIAN
1667 uint8_t domain;
1668 uint8_t area;
1669 uint8_t al_pa;
1670 #elif defined(__LITTLE_ENDIAN)
1671 uint8_t al_pa;
1672 uint8_t area;
1673 uint8_t domain;
1674 #else
1675 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1676 #endif
1677 uint8_t rsvd_1;
1678 } b;
1679 } port_id_t;
1680 #define INVALID_PORT_ID 0xFFFFFF
1681
1682 /*
1683 * Switch info gathering structure.
1684 */
1685 typedef struct {
1686 port_id_t d_id;
1687 uint8_t node_name[WWN_SIZE];
1688 uint8_t port_name[WWN_SIZE];
1689 uint8_t fabric_port_name[WWN_SIZE];
1690 uint16_t fp_speed;
1691 uint8_t fc4_type;
1692 } sw_info_t;
1693
1694 /* FCP-4 types */
1695 #define FC4_TYPE_FCP_SCSI 0x08
1696 #define FC4_TYPE_OTHER 0x0
1697 #define FC4_TYPE_UNKNOWN 0xff
1698
1699 /*
1700 * Fibre channel port type.
1701 */
1702 typedef enum {
1703 FCT_UNKNOWN,
1704 FCT_RSCN,
1705 FCT_SWITCH,
1706 FCT_BROADCAST,
1707 FCT_INITIATOR,
1708 FCT_TARGET
1709 } fc_port_type_t;
1710
1711 /*
1712 * Fibre channel port structure.
1713 */
1714 typedef struct fc_port {
1715 struct list_head list;
1716 struct scsi_qla_host *vha;
1717
1718 uint8_t node_name[WWN_SIZE];
1719 uint8_t port_name[WWN_SIZE];
1720 port_id_t d_id;
1721 uint16_t loop_id;
1722 uint16_t old_loop_id;
1723
1724 uint8_t fcp_prio;
1725
1726 uint8_t fabric_port_name[WWN_SIZE];
1727 uint16_t fp_speed;
1728
1729 fc_port_type_t port_type;
1730
1731 atomic_t state;
1732 uint32_t flags;
1733
1734 int login_retry;
1735
1736 struct fc_rport *rport, *drport;
1737 u32 supported_classes;
1738
1739 uint8_t fc4_type;
1740 uint8_t scan_state;
1741 } fc_port_t;
1742
1743 #define QLA_FCPORT_SCAN_NONE 0
1744 #define QLA_FCPORT_SCAN_FOUND 1
1745
1746 /*
1747 * Fibre channel port/lun states.
1748 */
1749 #define FCS_UNCONFIGURED 1
1750 #define FCS_DEVICE_DEAD 2
1751 #define FCS_DEVICE_LOST 3
1752 #define FCS_ONLINE 4
1753
1754 static const char * const port_state_str[] = {
1755 "Unknown",
1756 "UNCONFIGURED",
1757 "DEAD",
1758 "LOST",
1759 "ONLINE"
1760 };
1761
1762 /*
1763 * FC port flags.
1764 */
1765 #define FCF_FABRIC_DEVICE BIT_0
1766 #define FCF_LOGIN_NEEDED BIT_1
1767 #define FCF_FCP2_DEVICE BIT_2
1768 #define FCF_ASYNC_SENT BIT_3
1769 #define FCF_CONF_COMP_SUPPORTED BIT_4
1770
1771 /* No loop ID flag. */
1772 #define FC_NO_LOOP_ID 0x1000
1773
1774 /*
1775 * FC-CT interface
1776 *
1777 * NOTE: All structures are big-endian in form.
1778 */
1779
1780 #define CT_REJECT_RESPONSE 0x8001
1781 #define CT_ACCEPT_RESPONSE 0x8002
1782 #define CT_REASON_INVALID_COMMAND_CODE 0x01
1783 #define CT_REASON_CANNOT_PERFORM 0x09
1784 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1785 #define CT_EXPL_ALREADY_REGISTERED 0x10
1786
1787 #define NS_N_PORT_TYPE 0x01
1788 #define NS_NL_PORT_TYPE 0x02
1789 #define NS_NX_PORT_TYPE 0x7F
1790
1791 #define GA_NXT_CMD 0x100
1792 #define GA_NXT_REQ_SIZE (16 + 4)
1793 #define GA_NXT_RSP_SIZE (16 + 620)
1794
1795 #define GID_PT_CMD 0x1A1
1796 #define GID_PT_REQ_SIZE (16 + 4)
1797
1798 #define GPN_ID_CMD 0x112
1799 #define GPN_ID_REQ_SIZE (16 + 4)
1800 #define GPN_ID_RSP_SIZE (16 + 8)
1801
1802 #define GNN_ID_CMD 0x113
1803 #define GNN_ID_REQ_SIZE (16 + 4)
1804 #define GNN_ID_RSP_SIZE (16 + 8)
1805
1806 #define GFT_ID_CMD 0x117
1807 #define GFT_ID_REQ_SIZE (16 + 4)
1808 #define GFT_ID_RSP_SIZE (16 + 32)
1809
1810 #define RFT_ID_CMD 0x217
1811 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1812 #define RFT_ID_RSP_SIZE 16
1813
1814 #define RFF_ID_CMD 0x21F
1815 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1816 #define RFF_ID_RSP_SIZE 16
1817
1818 #define RNN_ID_CMD 0x213
1819 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1820 #define RNN_ID_RSP_SIZE 16
1821
1822 #define RSNN_NN_CMD 0x239
1823 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1824 #define RSNN_NN_RSP_SIZE 16
1825
1826 #define GFPN_ID_CMD 0x11C
1827 #define GFPN_ID_REQ_SIZE (16 + 4)
1828 #define GFPN_ID_RSP_SIZE (16 + 8)
1829
1830 #define GPSC_CMD 0x127
1831 #define GPSC_REQ_SIZE (16 + 8)
1832 #define GPSC_RSP_SIZE (16 + 2 + 2)
1833
1834 #define GFF_ID_CMD 0x011F
1835 #define GFF_ID_REQ_SIZE (16 + 4)
1836 #define GFF_ID_RSP_SIZE (16 + 128)
1837
1838 /*
1839 * HBA attribute types.
1840 */
1841 #define FDMI_HBA_ATTR_COUNT 9
1842 #define FDMI_HBA_NODE_NAME 1
1843 #define FDMI_HBA_MANUFACTURER 2
1844 #define FDMI_HBA_SERIAL_NUMBER 3
1845 #define FDMI_HBA_MODEL 4
1846 #define FDMI_HBA_MODEL_DESCRIPTION 5
1847 #define FDMI_HBA_HARDWARE_VERSION 6
1848 #define FDMI_HBA_DRIVER_VERSION 7
1849 #define FDMI_HBA_OPTION_ROM_VERSION 8
1850 #define FDMI_HBA_FIRMWARE_VERSION 9
1851 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1852 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1853
1854 struct ct_fdmi_hba_attr {
1855 uint16_t type;
1856 uint16_t len;
1857 union {
1858 uint8_t node_name[WWN_SIZE];
1859 uint8_t manufacturer[32];
1860 uint8_t serial_num[8];
1861 uint8_t model[16];
1862 uint8_t model_desc[80];
1863 uint8_t hw_version[16];
1864 uint8_t driver_version[32];
1865 uint8_t orom_version[16];
1866 uint8_t fw_version[16];
1867 uint8_t os_version[128];
1868 uint8_t max_ct_len[4];
1869 } a;
1870 };
1871
1872 struct ct_fdmi_hba_attributes {
1873 uint32_t count;
1874 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1875 };
1876
1877 /*
1878 * Port attribute types.
1879 */
1880 #define FDMI_PORT_ATTR_COUNT 6
1881 #define FDMI_PORT_FC4_TYPES 1
1882 #define FDMI_PORT_SUPPORT_SPEED 2
1883 #define FDMI_PORT_CURRENT_SPEED 3
1884 #define FDMI_PORT_MAX_FRAME_SIZE 4
1885 #define FDMI_PORT_OS_DEVICE_NAME 5
1886 #define FDMI_PORT_HOST_NAME 6
1887
1888 #define FDMI_PORT_SPEED_1GB 0x1
1889 #define FDMI_PORT_SPEED_2GB 0x2
1890 #define FDMI_PORT_SPEED_10GB 0x4
1891 #define FDMI_PORT_SPEED_4GB 0x8
1892 #define FDMI_PORT_SPEED_8GB 0x10
1893 #define FDMI_PORT_SPEED_16GB 0x20
1894 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
1895
1896 struct ct_fdmi_port_attr {
1897 uint16_t type;
1898 uint16_t len;
1899 union {
1900 uint8_t fc4_types[32];
1901 uint32_t sup_speed;
1902 uint32_t cur_speed;
1903 uint32_t max_frame_size;
1904 uint8_t os_dev_name[32];
1905 uint8_t host_name[32];
1906 } a;
1907 };
1908
1909 /*
1910 * Port Attribute Block.
1911 */
1912 struct ct_fdmi_port_attributes {
1913 uint32_t count;
1914 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1915 };
1916
1917 /* FDMI definitions. */
1918 #define GRHL_CMD 0x100
1919 #define GHAT_CMD 0x101
1920 #define GRPL_CMD 0x102
1921 #define GPAT_CMD 0x110
1922
1923 #define RHBA_CMD 0x200
1924 #define RHBA_RSP_SIZE 16
1925
1926 #define RHAT_CMD 0x201
1927 #define RPRT_CMD 0x210
1928
1929 #define RPA_CMD 0x211
1930 #define RPA_RSP_SIZE 16
1931
1932 #define DHBA_CMD 0x300
1933 #define DHBA_REQ_SIZE (16 + 8)
1934 #define DHBA_RSP_SIZE 16
1935
1936 #define DHAT_CMD 0x301
1937 #define DPRT_CMD 0x310
1938 #define DPA_CMD 0x311
1939
1940 /* CT command header -- request/response common fields */
1941 struct ct_cmd_hdr {
1942 uint8_t revision;
1943 uint8_t in_id[3];
1944 uint8_t gs_type;
1945 uint8_t gs_subtype;
1946 uint8_t options;
1947 uint8_t reserved;
1948 };
1949
1950 /* CT command request */
1951 struct ct_sns_req {
1952 struct ct_cmd_hdr header;
1953 uint16_t command;
1954 uint16_t max_rsp_size;
1955 uint8_t fragment_id;
1956 uint8_t reserved[3];
1957
1958 union {
1959 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
1960 struct {
1961 uint8_t reserved;
1962 uint8_t port_id[3];
1963 } port_id;
1964
1965 struct {
1966 uint8_t port_type;
1967 uint8_t domain;
1968 uint8_t area;
1969 uint8_t reserved;
1970 } gid_pt;
1971
1972 struct {
1973 uint8_t reserved;
1974 uint8_t port_id[3];
1975 uint8_t fc4_types[32];
1976 } rft_id;
1977
1978 struct {
1979 uint8_t reserved;
1980 uint8_t port_id[3];
1981 uint16_t reserved2;
1982 uint8_t fc4_feature;
1983 uint8_t fc4_type;
1984 } rff_id;
1985
1986 struct {
1987 uint8_t reserved;
1988 uint8_t port_id[3];
1989 uint8_t node_name[8];
1990 } rnn_id;
1991
1992 struct {
1993 uint8_t node_name[8];
1994 uint8_t name_len;
1995 uint8_t sym_node_name[255];
1996 } rsnn_nn;
1997
1998 struct {
1999 uint8_t hba_indentifier[8];
2000 } ghat;
2001
2002 struct {
2003 uint8_t hba_identifier[8];
2004 uint32_t entry_count;
2005 uint8_t port_name[8];
2006 struct ct_fdmi_hba_attributes attrs;
2007 } rhba;
2008
2009 struct {
2010 uint8_t hba_identifier[8];
2011 struct ct_fdmi_hba_attributes attrs;
2012 } rhat;
2013
2014 struct {
2015 uint8_t port_name[8];
2016 struct ct_fdmi_port_attributes attrs;
2017 } rpa;
2018
2019 struct {
2020 uint8_t port_name[8];
2021 } dhba;
2022
2023 struct {
2024 uint8_t port_name[8];
2025 } dhat;
2026
2027 struct {
2028 uint8_t port_name[8];
2029 } dprt;
2030
2031 struct {
2032 uint8_t port_name[8];
2033 } dpa;
2034
2035 struct {
2036 uint8_t port_name[8];
2037 } gpsc;
2038
2039 struct {
2040 uint8_t reserved;
2041 uint8_t port_name[3];
2042 } gff_id;
2043 } req;
2044 };
2045
2046 /* CT command response header */
2047 struct ct_rsp_hdr {
2048 struct ct_cmd_hdr header;
2049 uint16_t response;
2050 uint16_t residual;
2051 uint8_t fragment_id;
2052 uint8_t reason_code;
2053 uint8_t explanation_code;
2054 uint8_t vendor_unique;
2055 };
2056
2057 struct ct_sns_gid_pt_data {
2058 uint8_t control_byte;
2059 uint8_t port_id[3];
2060 };
2061
2062 struct ct_sns_rsp {
2063 struct ct_rsp_hdr header;
2064
2065 union {
2066 struct {
2067 uint8_t port_type;
2068 uint8_t port_id[3];
2069 uint8_t port_name[8];
2070 uint8_t sym_port_name_len;
2071 uint8_t sym_port_name[255];
2072 uint8_t node_name[8];
2073 uint8_t sym_node_name_len;
2074 uint8_t sym_node_name[255];
2075 uint8_t init_proc_assoc[8];
2076 uint8_t node_ip_addr[16];
2077 uint8_t class_of_service[4];
2078 uint8_t fc4_types[32];
2079 uint8_t ip_address[16];
2080 uint8_t fabric_port_name[8];
2081 uint8_t reserved;
2082 uint8_t hard_address[3];
2083 } ga_nxt;
2084
2085 struct {
2086 /* Assume the largest number of targets for the union */
2087 struct ct_sns_gid_pt_data
2088 entries[MAX_FIBRE_DEVICES_MAX];
2089 } gid_pt;
2090
2091 struct {
2092 uint8_t port_name[8];
2093 } gpn_id;
2094
2095 struct {
2096 uint8_t node_name[8];
2097 } gnn_id;
2098
2099 struct {
2100 uint8_t fc4_types[32];
2101 } gft_id;
2102
2103 struct {
2104 uint32_t entry_count;
2105 uint8_t port_name[8];
2106 struct ct_fdmi_hba_attributes attrs;
2107 } ghat;
2108
2109 struct {
2110 uint8_t port_name[8];
2111 } gfpn_id;
2112
2113 struct {
2114 uint16_t speeds;
2115 uint16_t speed;
2116 } gpsc;
2117
2118 #define GFF_FCP_SCSI_OFFSET 7
2119 struct {
2120 uint8_t fc4_features[128];
2121 } gff_id;
2122 } rsp;
2123 };
2124
2125 struct ct_sns_pkt {
2126 union {
2127 struct ct_sns_req req;
2128 struct ct_sns_rsp rsp;
2129 } p;
2130 };
2131
2132 /*
2133 * SNS command structures -- for 2200 compatibility.
2134 */
2135 #define RFT_ID_SNS_SCMD_LEN 22
2136 #define RFT_ID_SNS_CMD_SIZE 60
2137 #define RFT_ID_SNS_DATA_SIZE 16
2138
2139 #define RNN_ID_SNS_SCMD_LEN 10
2140 #define RNN_ID_SNS_CMD_SIZE 36
2141 #define RNN_ID_SNS_DATA_SIZE 16
2142
2143 #define GA_NXT_SNS_SCMD_LEN 6
2144 #define GA_NXT_SNS_CMD_SIZE 28
2145 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
2146
2147 #define GID_PT_SNS_SCMD_LEN 6
2148 #define GID_PT_SNS_CMD_SIZE 28
2149 /*
2150 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
2151 * adapters.
2152 */
2153 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
2154
2155 #define GPN_ID_SNS_SCMD_LEN 6
2156 #define GPN_ID_SNS_CMD_SIZE 28
2157 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
2158
2159 #define GNN_ID_SNS_SCMD_LEN 6
2160 #define GNN_ID_SNS_CMD_SIZE 28
2161 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
2162
2163 struct sns_cmd_pkt {
2164 union {
2165 struct {
2166 uint16_t buffer_length;
2167 uint16_t reserved_1;
2168 uint32_t buffer_address[2];
2169 uint16_t subcommand_length;
2170 uint16_t reserved_2;
2171 uint16_t subcommand;
2172 uint16_t size;
2173 uint32_t reserved_3;
2174 uint8_t param[36];
2175 } cmd;
2176
2177 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2178 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2179 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2180 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2181 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2182 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2183 } p;
2184 };
2185
2186 struct fw_blob {
2187 char *name;
2188 uint32_t segs[4];
2189 const struct firmware *fw;
2190 };
2191
2192 /* Return data from MBC_GET_ID_LIST call. */
2193 struct gid_list_info {
2194 uint8_t al_pa;
2195 uint8_t area;
2196 uint8_t domain;
2197 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2198 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2199 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2200 };
2201
2202 /* NPIV */
2203 typedef struct vport_info {
2204 uint8_t port_name[WWN_SIZE];
2205 uint8_t node_name[WWN_SIZE];
2206 int vp_id;
2207 uint16_t loop_id;
2208 unsigned long host_no;
2209 uint8_t port_id[3];
2210 int loop_state;
2211 } vport_info_t;
2212
2213 typedef struct vport_params {
2214 uint8_t port_name[WWN_SIZE];
2215 uint8_t node_name[WWN_SIZE];
2216 uint32_t options;
2217 #define VP_OPTS_RETRY_ENABLE BIT_0
2218 #define VP_OPTS_VP_DISABLE BIT_1
2219 } vport_params_t;
2220
2221 /* NPIV - return codes of VP create and modify */
2222 #define VP_RET_CODE_OK 0
2223 #define VP_RET_CODE_FATAL 1
2224 #define VP_RET_CODE_WRONG_ID 2
2225 #define VP_RET_CODE_WWPN 3
2226 #define VP_RET_CODE_RESOURCES 4
2227 #define VP_RET_CODE_NO_MEM 5
2228 #define VP_RET_CODE_NOT_FOUND 6
2229
2230 struct qla_hw_data;
2231 struct rsp_que;
2232 /*
2233 * ISP operations
2234 */
2235 struct isp_operations {
2236
2237 int (*pci_config) (struct scsi_qla_host *);
2238 void (*reset_chip) (struct scsi_qla_host *);
2239 int (*chip_diag) (struct scsi_qla_host *);
2240 void (*config_rings) (struct scsi_qla_host *);
2241 void (*reset_adapter) (struct scsi_qla_host *);
2242 int (*nvram_config) (struct scsi_qla_host *);
2243 void (*update_fw_options) (struct scsi_qla_host *);
2244 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2245
2246 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2247 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2248
2249 irq_handler_t intr_handler;
2250 void (*enable_intrs) (struct qla_hw_data *);
2251 void (*disable_intrs) (struct qla_hw_data *);
2252
2253 int (*abort_command) (srb_t *);
2254 int (*target_reset) (struct fc_port *, unsigned int, int);
2255 int (*lun_reset) (struct fc_port *, unsigned int, int);
2256 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2257 uint8_t, uint8_t, uint16_t *, uint8_t);
2258 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2259 uint8_t, uint8_t);
2260
2261 uint16_t (*calc_req_entries) (uint16_t);
2262 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2263 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2264 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2265 uint32_t);
2266
2267 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2268 uint32_t, uint32_t);
2269 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2270 uint32_t);
2271
2272 void (*fw_dump) (struct scsi_qla_host *, int);
2273
2274 int (*beacon_on) (struct scsi_qla_host *);
2275 int (*beacon_off) (struct scsi_qla_host *);
2276 void (*beacon_blink) (struct scsi_qla_host *);
2277
2278 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2279 uint32_t, uint32_t);
2280 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2281 uint32_t);
2282
2283 int (*get_flash_version) (struct scsi_qla_host *, void *);
2284 int (*start_scsi) (srb_t *);
2285 int (*abort_isp) (struct scsi_qla_host *);
2286 int (*iospace_config)(struct qla_hw_data*);
2287 };
2288
2289 /* MSI-X Support *************************************************************/
2290
2291 #define QLA_MSIX_CHIP_REV_24XX 3
2292 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2293 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2294
2295 #define QLA_MSIX_DEFAULT 0x00
2296 #define QLA_MSIX_RSP_Q 0x01
2297
2298 #define QLA_MIDX_DEFAULT 0
2299 #define QLA_MIDX_RSP_Q 1
2300 #define QLA_PCI_MSIX_CONTROL 0xa2
2301 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
2302
2303 struct scsi_qla_host;
2304
2305 struct qla_msix_entry {
2306 int have_irq;
2307 uint32_t vector;
2308 uint16_t entry;
2309 struct rsp_que *rsp;
2310 };
2311
2312 #define WATCH_INTERVAL 1 /* number of seconds */
2313
2314 /* Work events. */
2315 enum qla_work_type {
2316 QLA_EVT_AEN,
2317 QLA_EVT_IDC_ACK,
2318 QLA_EVT_ASYNC_LOGIN,
2319 QLA_EVT_ASYNC_LOGIN_DONE,
2320 QLA_EVT_ASYNC_LOGOUT,
2321 QLA_EVT_ASYNC_LOGOUT_DONE,
2322 QLA_EVT_ASYNC_ADISC,
2323 QLA_EVT_ASYNC_ADISC_DONE,
2324 QLA_EVT_UEVENT,
2325 };
2326
2327
2328 struct qla_work_evt {
2329 struct list_head list;
2330 enum qla_work_type type;
2331 u32 flags;
2332 #define QLA_EVT_FLAG_FREE 0x1
2333
2334 union {
2335 struct {
2336 enum fc_host_event_code code;
2337 u32 data;
2338 } aen;
2339 struct {
2340 #define QLA_IDC_ACK_REGS 7
2341 uint16_t mb[QLA_IDC_ACK_REGS];
2342 } idc_ack;
2343 struct {
2344 struct fc_port *fcport;
2345 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
2346 u16 data[2];
2347 } logio;
2348 struct {
2349 u32 code;
2350 #define QLA_UEVENT_CODE_FW_DUMP 0
2351 } uevent;
2352 } u;
2353 };
2354
2355 struct qla_chip_state_84xx {
2356 struct list_head list;
2357 struct kref kref;
2358
2359 void *bus;
2360 spinlock_t access_lock;
2361 struct mutex fw_update_mutex;
2362 uint32_t fw_update;
2363 uint32_t op_fw_version;
2364 uint32_t op_fw_size;
2365 uint32_t op_fw_seq_size;
2366 uint32_t diag_fw_version;
2367 uint32_t gold_fw_version;
2368 };
2369
2370 struct qla_statistics {
2371 uint32_t total_isp_aborts;
2372 uint64_t input_bytes;
2373 uint64_t output_bytes;
2374 };
2375
2376 /* Multi queue support */
2377 #define MBC_INITIALIZE_MULTIQ 0x1f
2378 #define QLA_QUE_PAGE 0X1000
2379 #define QLA_MQ_SIZE 32
2380 #define QLA_MAX_QUEUES 256
2381 #define ISP_QUE_REG(ha, id) \
2382 ((ha->mqenable || IS_QLA83XX(ha)) ? \
2383 ((void *)(ha->mqiobase) +\
2384 (QLA_QUE_PAGE * id)) :\
2385 ((void *)(ha->iobase)))
2386 #define QLA_REQ_QUE_ID(tag) \
2387 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2388 #define QLA_DEFAULT_QUE_QOS 5
2389 #define QLA_PRECONFIG_VPORTS 32
2390 #define QLA_MAX_VPORTS_QLA24XX 128
2391 #define QLA_MAX_VPORTS_QLA25XX 256
2392 /* Response queue data structure */
2393 struct rsp_que {
2394 dma_addr_t dma;
2395 response_t *ring;
2396 response_t *ring_ptr;
2397 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2398 uint32_t __iomem *rsp_q_out;
2399 uint16_t ring_index;
2400 uint16_t out_ptr;
2401 uint16_t length;
2402 uint16_t options;
2403 uint16_t rid;
2404 uint16_t id;
2405 uint16_t vp_idx;
2406 struct qla_hw_data *hw;
2407 struct qla_msix_entry *msix;
2408 struct req_que *req;
2409 srb_t *status_srb; /* status continuation entry */
2410 struct work_struct q_work;
2411 };
2412
2413 /* Request queue data structure */
2414 struct req_que {
2415 dma_addr_t dma;
2416 request_t *ring;
2417 request_t *ring_ptr;
2418 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2419 uint32_t __iomem *req_q_out;
2420 uint16_t ring_index;
2421 uint16_t in_ptr;
2422 uint16_t cnt;
2423 uint16_t length;
2424 uint16_t options;
2425 uint16_t rid;
2426 uint16_t id;
2427 uint16_t qos;
2428 uint16_t vp_idx;
2429 struct rsp_que *rsp;
2430 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2431 uint32_t current_outstanding_cmd;
2432 int max_q_depth;
2433 };
2434
2435 /* Place holder for FW buffer parameters */
2436 struct qlfc_fw {
2437 void *fw_buf;
2438 dma_addr_t fw_dma;
2439 uint32_t len;
2440 };
2441
2442 struct qlt_hw_data {
2443 /* Protected by hw lock */
2444 uint32_t enable_class_2:1;
2445 uint32_t enable_explicit_conf:1;
2446 uint32_t ini_mode_force_reverse:1;
2447 uint32_t node_name_set:1;
2448
2449 dma_addr_t atio_dma; /* Physical address. */
2450 struct atio *atio_ring; /* Base virtual address */
2451 struct atio *atio_ring_ptr; /* Current address. */
2452 uint16_t atio_ring_index; /* Current index. */
2453 uint16_t atio_q_length;
2454
2455 void *target_lport_ptr;
2456 struct qla_tgt_func_tmpl *tgt_ops;
2457 struct qla_tgt *qla_tgt;
2458 struct qla_tgt_cmd *cmds[MAX_OUTSTANDING_COMMANDS];
2459 uint16_t current_handle;
2460
2461 struct qla_tgt_vp_map *tgt_vp_map;
2462 struct mutex tgt_mutex;
2463 struct mutex tgt_host_action_mutex;
2464
2465 int saved_set;
2466 uint16_t saved_exchange_count;
2467 uint32_t saved_firmware_options_1;
2468 uint32_t saved_firmware_options_2;
2469 uint32_t saved_firmware_options_3;
2470 uint8_t saved_firmware_options[2];
2471 uint8_t saved_add_firmware_options[2];
2472
2473 uint8_t tgt_node_name[WWN_SIZE];
2474 };
2475
2476 /*
2477 * Qlogic host adapter specific data structure.
2478 */
2479 struct qla_hw_data {
2480 struct pci_dev *pdev;
2481 /* SRB cache. */
2482 #define SRB_MIN_REQ 128
2483 mempool_t *srb_mempool;
2484
2485 volatile struct {
2486 uint32_t mbox_int :1;
2487 uint32_t mbox_busy :1;
2488 uint32_t disable_risc_code_load :1;
2489 uint32_t enable_64bit_addressing :1;
2490 uint32_t enable_lip_reset :1;
2491 uint32_t enable_target_reset :1;
2492 uint32_t enable_lip_full_login :1;
2493 uint32_t enable_led_scheme :1;
2494
2495 uint32_t msi_enabled :1;
2496 uint32_t msix_enabled :1;
2497 uint32_t disable_serdes :1;
2498 uint32_t gpsc_supported :1;
2499 uint32_t npiv_supported :1;
2500 uint32_t pci_channel_io_perm_failure :1;
2501 uint32_t fce_enabled :1;
2502 uint32_t fac_supported :1;
2503
2504 uint32_t chip_reset_done :1;
2505 uint32_t port0 :1;
2506 uint32_t running_gold_fw :1;
2507 uint32_t eeh_busy :1;
2508 uint32_t cpu_affinity_enabled :1;
2509 uint32_t disable_msix_handshake :1;
2510 uint32_t fcp_prio_enabled :1;
2511 uint32_t isp82xx_fw_hung:1;
2512
2513 uint32_t quiesce_owner:1;
2514 uint32_t thermal_supported:1;
2515 uint32_t isp82xx_reset_hdlr_active:1;
2516 uint32_t isp82xx_reset_owner:1;
2517 uint32_t isp82xx_no_md_cap:1;
2518 uint32_t host_shutting_down:1;
2519 /* 30 bits */
2520 } flags;
2521
2522 /* This spinlock is used to protect "io transactions", you must
2523 * acquire it before doing any IO to the card, eg with RD_REG*() and
2524 * WRT_REG*() for the duration of your entire commandtransaction.
2525 *
2526 * This spinlock is of lower priority than the io request lock.
2527 */
2528
2529 spinlock_t hardware_lock ____cacheline_aligned;
2530 int bars;
2531 int mem_only;
2532 device_reg_t __iomem *iobase; /* Base I/O address */
2533 resource_size_t pio_address;
2534
2535 #define MIN_IOBASE_LEN 0x100
2536 /* Multi queue data structs */
2537 device_reg_t __iomem *mqiobase;
2538 device_reg_t __iomem *msixbase;
2539 uint16_t msix_count;
2540 uint8_t mqenable;
2541 struct req_que **req_q_map;
2542 struct rsp_que **rsp_q_map;
2543 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2544 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2545 uint8_t max_req_queues;
2546 uint8_t max_rsp_queues;
2547 struct qla_npiv_entry *npiv_info;
2548 uint16_t nvram_npiv_size;
2549
2550 uint16_t switch_cap;
2551 #define FLOGI_SEQ_DEL BIT_8
2552 #define FLOGI_MID_SUPPORT BIT_10
2553 #define FLOGI_VSAN_SUPPORT BIT_12
2554 #define FLOGI_SP_SUPPORT BIT_13
2555
2556 uint8_t port_no; /* Physical port of adapter */
2557
2558 /* Timeout timers. */
2559 uint8_t loop_down_abort_time; /* port down timer */
2560 atomic_t loop_down_timer; /* loop down timer */
2561 uint8_t link_down_timeout; /* link down timeout */
2562 uint16_t max_loop_id;
2563 uint16_t max_fibre_devices; /* Maximum number of targets */
2564
2565 uint16_t fb_rev;
2566 uint16_t min_external_loopid; /* First external loop Id */
2567
2568 #define PORT_SPEED_UNKNOWN 0xFFFF
2569 #define PORT_SPEED_1GB 0x00
2570 #define PORT_SPEED_2GB 0x01
2571 #define PORT_SPEED_4GB 0x03
2572 #define PORT_SPEED_8GB 0x04
2573 #define PORT_SPEED_16GB 0x05
2574 #define PORT_SPEED_10GB 0x13
2575 uint16_t link_data_rate; /* F/W operating speed */
2576
2577 uint8_t current_topology;
2578 uint8_t prev_topology;
2579 #define ISP_CFG_NL 1
2580 #define ISP_CFG_N 2
2581 #define ISP_CFG_FL 4
2582 #define ISP_CFG_F 8
2583
2584 uint8_t operating_mode; /* F/W operating mode */
2585 #define LOOP 0
2586 #define P2P 1
2587 #define LOOP_P2P 2
2588 #define P2P_LOOP 3
2589 uint8_t interrupts_on;
2590 uint32_t isp_abort_cnt;
2591
2592 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2593 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2594 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2595 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
2596 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
2597 uint32_t device_type;
2598 #define DT_ISP2100 BIT_0
2599 #define DT_ISP2200 BIT_1
2600 #define DT_ISP2300 BIT_2
2601 #define DT_ISP2312 BIT_3
2602 #define DT_ISP2322 BIT_4
2603 #define DT_ISP6312 BIT_5
2604 #define DT_ISP6322 BIT_6
2605 #define DT_ISP2422 BIT_7
2606 #define DT_ISP2432 BIT_8
2607 #define DT_ISP5422 BIT_9
2608 #define DT_ISP5432 BIT_10
2609 #define DT_ISP2532 BIT_11
2610 #define DT_ISP8432 BIT_12
2611 #define DT_ISP8001 BIT_13
2612 #define DT_ISP8021 BIT_14
2613 #define DT_ISP2031 BIT_15
2614 #define DT_ISP8031 BIT_16
2615 #define DT_ISP_LAST (DT_ISP8031 << 1)
2616
2617 #define DT_T10_PI BIT_25
2618 #define DT_IIDMA BIT_26
2619 #define DT_FWI2 BIT_27
2620 #define DT_ZIO_SUPPORTED BIT_28
2621 #define DT_OEM_001 BIT_29
2622 #define DT_ISP2200A BIT_30
2623 #define DT_EXTENDED_IDS BIT_31
2624 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2625 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2626 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2627 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2628 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2629 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2630 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2631 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2632 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2633 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2634 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2635 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2636 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2637 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2638 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2639 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
2640 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
2641 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
2642 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
2643
2644 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2645 IS_QLA6312(ha) || IS_QLA6322(ha))
2646 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2647 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2648 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
2649 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
2650 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
2651 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2652 IS_QLA84XX(ha))
2653 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
2654 IS_QLA8031(ha))
2655 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2656 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2657 IS_QLA82XX(ha) || IS_QLA83XX(ha))
2658 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2659 #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2660 IS_QLA83XX(ha)) && (ha)->flags.msix_enabled)
2661 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2662 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2663 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
2664
2665 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
2666 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2667 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2668 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2669 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2670 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2671 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
2672 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha))
2673
2674 /* HBA serial number */
2675 uint8_t serial0;
2676 uint8_t serial1;
2677 uint8_t serial2;
2678
2679 /* NVRAM configuration data */
2680 #define MAX_NVRAM_SIZE 4096
2681 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
2682 uint16_t nvram_size;
2683 uint16_t nvram_base;
2684 void *nvram;
2685 uint16_t vpd_size;
2686 uint16_t vpd_base;
2687 void *vpd;
2688
2689 uint16_t loop_reset_delay;
2690 uint8_t retry_count;
2691 uint8_t login_timeout;
2692 uint16_t r_a_tov;
2693 int port_down_retry_count;
2694 uint8_t mbx_count;
2695
2696 uint32_t login_retry_count;
2697 /* SNS command interfaces. */
2698 ms_iocb_entry_t *ms_iocb;
2699 dma_addr_t ms_iocb_dma;
2700 struct ct_sns_pkt *ct_sns;
2701 dma_addr_t ct_sns_dma;
2702 /* SNS command interfaces for 2200. */
2703 struct sns_cmd_pkt *sns_cmd;
2704 dma_addr_t sns_cmd_dma;
2705
2706 #define SFP_DEV_SIZE 256
2707 #define SFP_BLOCK_SIZE 64
2708 void *sfp_data;
2709 dma_addr_t sfp_data_dma;
2710
2711 #define XGMAC_DATA_SIZE 4096
2712 void *xgmac_data;
2713 dma_addr_t xgmac_data_dma;
2714
2715 #define DCBX_TLV_DATA_SIZE 4096
2716 void *dcbx_tlv;
2717 dma_addr_t dcbx_tlv_dma;
2718
2719 struct task_struct *dpc_thread;
2720 uint8_t dpc_active; /* DPC routine is active */
2721
2722 dma_addr_t gid_list_dma;
2723 struct gid_list_info *gid_list;
2724 int gid_list_info_size;
2725
2726 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2727 #define DMA_POOL_SIZE 256
2728 struct dma_pool *s_dma_pool;
2729
2730 dma_addr_t init_cb_dma;
2731 init_cb_t *init_cb;
2732 int init_cb_size;
2733 dma_addr_t ex_init_cb_dma;
2734 struct ex_init_cb_81xx *ex_init_cb;
2735
2736 void *async_pd;
2737 dma_addr_t async_pd_dma;
2738
2739 void *swl;
2740
2741 /* These are used by mailbox operations. */
2742 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2743
2744 mbx_cmd_t *mcp;
2745 unsigned long mbx_cmd_flags;
2746 #define MBX_INTERRUPT 1
2747 #define MBX_INTR_WAIT 2
2748 #define MBX_UPDATE_FLASH_ACTIVE 3
2749
2750 struct mutex vport_lock; /* Virtual port synchronization */
2751 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
2752 struct completion mbx_cmd_comp; /* Serialize mbx access */
2753 struct completion mbx_intr_comp; /* Used for completion notification */
2754 struct completion dcbx_comp; /* For set port config notification */
2755 int notify_dcbx_comp;
2756
2757 /* Basic firmware related information. */
2758 uint16_t fw_major_version;
2759 uint16_t fw_minor_version;
2760 uint16_t fw_subminor_version;
2761 uint16_t fw_attributes;
2762 uint16_t fw_attributes_h;
2763 uint16_t fw_attributes_ext[2];
2764 uint32_t fw_memory_size;
2765 uint32_t fw_transfer_size;
2766 uint32_t fw_srisc_address;
2767 #define RISC_START_ADDRESS_2100 0x1000
2768 #define RISC_START_ADDRESS_2300 0x800
2769 #define RISC_START_ADDRESS_2400 0x100000
2770 uint16_t fw_xcb_count;
2771
2772 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2773 uint8_t fw_seriallink_options[4];
2774 uint16_t fw_seriallink_options24[4];
2775
2776 uint8_t mpi_version[3];
2777 uint32_t mpi_capabilities;
2778 uint8_t phy_version[3];
2779
2780 /* Firmware dump information. */
2781 struct qla2xxx_fw_dump *fw_dump;
2782 uint32_t fw_dump_len;
2783 int fw_dumped;
2784 int fw_dump_reading;
2785 dma_addr_t eft_dma;
2786 void *eft;
2787
2788 uint32_t chain_offset;
2789 struct dentry *dfs_dir;
2790 struct dentry *dfs_fce;
2791 dma_addr_t fce_dma;
2792 void *fce;
2793 uint32_t fce_bufs;
2794 uint16_t fce_mb[8];
2795 uint64_t fce_wr, fce_rd;
2796 struct mutex fce_mutex;
2797
2798 uint32_t pci_attr;
2799 uint16_t chip_revision;
2800
2801 uint16_t product_id[4];
2802
2803 uint8_t model_number[16+1];
2804 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2805 char model_desc[80];
2806 uint8_t adapter_id[16+1];
2807
2808 /* Option ROM information. */
2809 char *optrom_buffer;
2810 uint32_t optrom_size;
2811 int optrom_state;
2812 #define QLA_SWAITING 0
2813 #define QLA_SREADING 1
2814 #define QLA_SWRITING 2
2815 uint32_t optrom_region_start;
2816 uint32_t optrom_region_size;
2817
2818 /* PCI expansion ROM image information. */
2819 #define ROM_CODE_TYPE_BIOS 0
2820 #define ROM_CODE_TYPE_FCODE 1
2821 #define ROM_CODE_TYPE_EFI 3
2822 uint8_t bios_revision[2];
2823 uint8_t efi_revision[2];
2824 uint8_t fcode_revision[16];
2825 uint32_t fw_revision[4];
2826
2827 uint32_t gold_fw_version[4];
2828
2829 /* Offsets for flash/nvram access (set to ~0 if not used). */
2830 uint32_t flash_conf_off;
2831 uint32_t flash_data_off;
2832 uint32_t nvram_conf_off;
2833 uint32_t nvram_data_off;
2834
2835 uint32_t fdt_wrt_disable;
2836 uint32_t fdt_erase_cmd;
2837 uint32_t fdt_block_size;
2838 uint32_t fdt_unprotect_sec_cmd;
2839 uint32_t fdt_protect_sec_cmd;
2840
2841 uint32_t flt_region_flt;
2842 uint32_t flt_region_fdt;
2843 uint32_t flt_region_boot;
2844 uint32_t flt_region_fw;
2845 uint32_t flt_region_vpd_nvram;
2846 uint32_t flt_region_vpd;
2847 uint32_t flt_region_nvram;
2848 uint32_t flt_region_npiv_conf;
2849 uint32_t flt_region_gold_fw;
2850 uint32_t flt_region_fcp_prio;
2851 uint32_t flt_region_bootload;
2852
2853 /* Needed for BEACON */
2854 uint16_t beacon_blink_led;
2855 uint8_t beacon_color_state;
2856 #define QLA_LED_GRN_ON 0x01
2857 #define QLA_LED_YLW_ON 0x02
2858 #define QLA_LED_ABR_ON 0x04
2859 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2860 /* ISP2322: red, green, amber. */
2861 uint16_t zio_mode;
2862 uint16_t zio_timer;
2863
2864 struct qla_msix_entry *msix_entries;
2865
2866 struct list_head vp_list; /* list of VP */
2867 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
2868 sizeof(unsigned long)];
2869 uint16_t num_vhosts; /* number of vports created */
2870 uint16_t num_vsans; /* number of vsan created */
2871 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
2872 int cur_vport_count;
2873
2874 struct qla_chip_state_84xx *cs84xx;
2875 struct isp_operations *isp_ops;
2876 struct workqueue_struct *wq;
2877 struct qlfc_fw fw_buf;
2878
2879 /* FCP_CMND priority support */
2880 struct qla_fcp_prio_cfg *fcp_prio_cfg;
2881
2882 struct dma_pool *dl_dma_pool;
2883 #define DSD_LIST_DMA_POOL_SIZE 512
2884
2885 struct dma_pool *fcp_cmnd_dma_pool;
2886 mempool_t *ctx_mempool;
2887 #define FCP_CMND_DMA_POOL_SIZE 512
2888
2889 unsigned long nx_pcibase; /* Base I/O address */
2890 uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */
2891 unsigned long nxdb_wr_ptr; /* Door bell write pointer */
2892
2893 uint32_t crb_win;
2894 uint32_t curr_window;
2895 uint32_t ddr_mn_window;
2896 unsigned long mn_win_crb;
2897 unsigned long ms_win_crb;
2898 int qdr_sn_window;
2899 uint32_t nx_dev_init_timeout;
2900 uint32_t nx_reset_timeout;
2901 rwlock_t hw_lock;
2902 uint16_t portnum; /* port number */
2903 int link_width;
2904 struct fw_blob *hablob;
2905 struct qla82xx_legacy_intr_set nx_legacy_intr;
2906
2907 uint16_t gbl_dsd_inuse;
2908 uint16_t gbl_dsd_avail;
2909 struct list_head gbl_dsd_list;
2910 #define NUM_DSD_CHAIN 4096
2911
2912 uint8_t fw_type;
2913 __le32 file_prd_off; /* File firmware product offset */
2914
2915 uint32_t md_template_size;
2916 void *md_tmplt_hdr;
2917 dma_addr_t md_tmplt_hdr_dma;
2918 void *md_dump;
2919 uint32_t md_dump_size;
2920
2921 struct qlt_hw_data tgt;
2922 };
2923
2924 /*
2925 * Qlogic scsi host structure
2926 */
2927 typedef struct scsi_qla_host {
2928 struct list_head list;
2929 struct list_head vp_fcports; /* list of fcports */
2930 struct list_head work_list;
2931 spinlock_t work_lock;
2932
2933 /* Commonly used flags and state information. */
2934 struct Scsi_Host *host;
2935 unsigned long host_no;
2936 uint8_t host_str[16];
2937
2938 volatile struct {
2939 uint32_t init_done :1;
2940 uint32_t online :1;
2941 uint32_t reset_active :1;
2942
2943 uint32_t management_server_logged_in :1;
2944 uint32_t process_response_queue :1;
2945 uint32_t difdix_supported:1;
2946 uint32_t delete_progress:1;
2947 } flags;
2948
2949 atomic_t loop_state;
2950 #define LOOP_TIMEOUT 1
2951 #define LOOP_DOWN 2
2952 #define LOOP_UP 3
2953 #define LOOP_UPDATE 4
2954 #define LOOP_READY 5
2955 #define LOOP_DEAD 6
2956
2957 unsigned long dpc_flags;
2958 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2959 #define RESET_ACTIVE 1
2960 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2961 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2962 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2963 #define LOOP_RESYNC_ACTIVE 5
2964 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2965 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2966 #define RELOGIN_NEEDED 8
2967 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
2968 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
2969 #define BEACON_BLINK_NEEDED 11
2970 #define REGISTER_FDMI_NEEDED 12
2971 #define FCPORT_UPDATE_NEEDED 13
2972 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
2973 #define UNLOADING 15
2974 #define NPIV_CONFIG_NEEDED 16
2975 #define ISP_UNRECOVERABLE 17
2976 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
2977 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
2978 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
2979 #define SCR_PENDING 21 /* SCR in target mode */
2980
2981 uint32_t device_flags;
2982 #define SWITCH_FOUND BIT_0
2983 #define DFLG_NO_CABLE BIT_1
2984 #define DFLG_DEV_FAILED BIT_5
2985
2986 /* ISP configuration data. */
2987 uint16_t loop_id; /* Host adapter loop id */
2988
2989 port_id_t d_id; /* Host adapter port id */
2990 uint8_t marker_needed;
2991 uint16_t mgmt_svr_loop_id;
2992
2993
2994
2995 /* Timeout timers. */
2996 uint8_t loop_down_abort_time; /* port down timer */
2997 atomic_t loop_down_timer; /* loop down timer */
2998 uint8_t link_down_timeout; /* link down timeout */
2999
3000 uint32_t timer_active;
3001 struct timer_list timer;
3002
3003 uint8_t node_name[WWN_SIZE];
3004 uint8_t port_name[WWN_SIZE];
3005 uint8_t fabric_node_name[WWN_SIZE];
3006
3007 uint16_t fcoe_vlan_id;
3008 uint16_t fcoe_fcf_idx;
3009 uint8_t fcoe_vn_port_mac[6];
3010
3011 uint32_t vp_abort_cnt;
3012
3013 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
3014 uint16_t vp_idx; /* vport ID */
3015
3016 unsigned long vp_flags;
3017 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
3018 #define VP_CREATE_NEEDED 1
3019 #define VP_BIND_NEEDED 2
3020 #define VP_DELETE_NEEDED 3
3021 #define VP_SCR_NEEDED 4 /* State Change Request registration */
3022 atomic_t vp_state;
3023 #define VP_OFFLINE 0
3024 #define VP_ACTIVE 1
3025 #define VP_FAILED 2
3026 // #define VP_DISABLE 3
3027 uint16_t vp_err_state;
3028 uint16_t vp_prev_err_state;
3029 #define VP_ERR_UNKWN 0
3030 #define VP_ERR_PORTDWN 1
3031 #define VP_ERR_FAB_UNSUPPORTED 2
3032 #define VP_ERR_FAB_NORESOURCES 3
3033 #define VP_ERR_FAB_LOGOUT 4
3034 #define VP_ERR_ADAP_NORESOURCES 5
3035 struct qla_hw_data *hw;
3036 struct req_que *req;
3037 int fw_heartbeat_counter;
3038 int seconds_since_last_heartbeat;
3039 struct fc_host_statistics fc_host_stat;
3040 struct qla_statistics qla_stats;
3041
3042 atomic_t vref_count;
3043 } scsi_qla_host_t;
3044
3045 #define SET_VP_IDX 1
3046 #define SET_AL_PA 2
3047 #define RESET_VP_IDX 3
3048 #define RESET_AL_PA 4
3049 struct qla_tgt_vp_map {
3050 uint8_t idx;
3051 scsi_qla_host_t *vha;
3052 };
3053
3054 /*
3055 * Macros to help code, maintain, etc.
3056 */
3057 #define LOOP_TRANSITION(ha) \
3058 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
3059 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
3060 atomic_read(&ha->loop_state) == LOOP_DOWN)
3061
3062 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
3063 atomic_inc(&__vha->vref_count); \
3064 mb(); \
3065 if (__vha->flags.delete_progress) { \
3066 atomic_dec(&__vha->vref_count); \
3067 __bail = 1; \
3068 } else { \
3069 __bail = 0; \
3070 } \
3071 } while (0)
3072
3073 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
3074 atomic_dec(&__vha->vref_count); \
3075 } while (0)
3076
3077 /*
3078 * qla2x00 local function return status codes
3079 */
3080 #define MBS_MASK 0x3fff
3081
3082 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
3083 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
3084 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
3085 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
3086 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
3087 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
3088 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
3089 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
3090 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
3091 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
3092
3093 #define QLA_FUNCTION_TIMEOUT 0x100
3094 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
3095 #define QLA_FUNCTION_FAILED 0x102
3096 #define QLA_MEMORY_ALLOC_FAILED 0x103
3097 #define QLA_LOCK_TIMEOUT 0x104
3098 #define QLA_ABORTED 0x105
3099 #define QLA_SUSPENDED 0x106
3100 #define QLA_BUSY 0x107
3101 #define QLA_ALREADY_REGISTERED 0x109
3102
3103 #define NVRAM_DELAY() udelay(10)
3104
3105 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
3106
3107 /*
3108 * Flash support definitions
3109 */
3110 #define OPTROM_SIZE_2300 0x20000
3111 #define OPTROM_SIZE_2322 0x100000
3112 #define OPTROM_SIZE_24XX 0x100000
3113 #define OPTROM_SIZE_25XX 0x200000
3114 #define OPTROM_SIZE_81XX 0x400000
3115 #define OPTROM_SIZE_82XX 0x800000
3116 #define OPTROM_SIZE_83XX 0x1000000
3117
3118 #define OPTROM_BURST_SIZE 0x1000
3119 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
3120
3121 #define QLA_DSDS_PER_IOCB 37
3122
3123 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
3124
3125 #define QLA_SG_ALL 1024
3126
3127 enum nexus_wait_type {
3128 WAIT_HOST = 0,
3129 WAIT_TARGET,
3130 WAIT_LUN,
3131 };
3132
3133 #include "qla_gbl.h"
3134 #include "qla_dbg.h"
3135 #include "qla_inline.h"
3136 #endif
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